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[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [coregen_xil_3244_19.cgc] - Blame information for rev 26

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   xilinx.com
   CoreGen
   coregen_xil_3244_19
   1.0
   
   
      
       
         coregen_xil_3244_19
         ./
         ./tmp/
         ./tmp/_cg
       
       
         xc5vlx20t
         virtex5
         ff323
         -2
       
       
         BusFormatAngleBracketNotRipped
         VHDL
         true
         Other
         false
         false
         false
         Ngc
         false
       
       
         Behavioral
         VHDL
         false
       
     
   


Line No.	Rev	Author	Line
1	26	mcleod_ide
2
3			`xilinx.com`
4			`CoreGen`
5			`coregen_xil_3244_19`
6			`1.0`
7
8
9
10
11			`coregen_xil_3244_19`
12			`./`
13			`./tmp/`
14			`./tmp/_cg`
15
16
17			`xc5vlx20t`
18			`virtex5`
19			`ff323`
20			`-2`
21
22
23			`BusFormatAngleBracketNotRipped`
24			`VHDL`
25			`true`
26			`Other`
27			`false`
28			`false`
29			`false`
30			`Ngc`
31			`false`
32
33
34			`Behavioral`
35			`VHDL`
36			`false`
37
38
39
40

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Subversion Repositories zx_ula

[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [coregen_xil_3244_19.cgc] - Blame information for rev 26