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[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [coregen_xil_3244_19.cgp] - Blame information for rev 26

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Line No. Rev Author Line
1 26 mcleod_ide 
# Date: Tue Sep 25 16:31:44 2012
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc5vlx20t
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SET devicefamily = virtex5
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ff323
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = false
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SET vhdlsim = true
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SET workingdirectory = ./tmp/
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# CRC: e2b133ab

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