URL https://opencores.org/ocsvn/zx_ula/zx_ula/trunk

Subversion Repositories zx_ula

[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [iseconfig/] [ulaplus_replacement.projectmgr] - Blame information for rev 29

Details | Compare with Previous | View Log







   
   
      
         2
         /tld_spartan3_sp48k C:|Documents and Settings|rodriguj|Mis documentos|opencores|zx_ula|branches|xilinx|ulaplus_replacement-upgrade_for_sp16-48k|rtl_ulaplus|ulaplus_tld.v/audio_mix - mixer
         /tld_spartan3_sp48k C:|Documents and Settings|rodriguj|Mis documentos|opencores|zx_ula|branches|xilinx|ulaplus_replacement-upgrade_for_sp16-48k|rtl_ulaplus|ulaplus_tld.v/the_ula - ula
         /ulaplus_tld C:|Documents and Settings|rodriguj|Mis documentos|opencores|zx_ula|branches|xilinx|ulaplus_replacement-upgrade_for_sp16-48k|rtl_ulaplus|ulaplus_tld.v/audio_mix - mixer
         /ulaplus_tld C:|Documents and Settings|rodriguj|Mis documentos|opencores|zx_ula|branches|xilinx|ulaplus_replacement-upgrade_for_sp16-48k|rtl_ulaplus|ulaplus_tld.v/the_ula - ula
         /ulaplus_tld C:|Documents and Settings|rodriguj|Mis documentos|opencores|zx_ula|branches|xilinx|ulaplus_replacement-upgrade_for_sp16-48k|rtl_ulaplus|ulaplus_tld.v/video_final_stage - rgbdtoa
      
      
         clock28mhz - master_ula_clock (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw)
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000015f000000020000000000000000000000000000000064ffffffff0000008100000000000000020000015f0000000100000000000000000000000100000000
      false
      clock28mhz - master_ula_clock (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000040101000100000000000000000000000064ffffffff0000008100000000000000040000005600000001000000000000009d0000000100000000000000660000000100000000000002480000000100000000
      false
      ula_pins.ucf
   
   
      
         1
         work
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000
      false
      work
   
   
      
         1
         User Constraints
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
      false
      
   
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design
         Synthesize - XST
         User Constraints
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
      false
      
   
   
      
         1
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
      false
      
   
   000000ff00000000000000020000011b0000011b01000000040100000002
   Implementation


Line No.	Rev	Author	Line
1	29	mcleod_ide
2	26	mcleod_ide
3
4
5
6
7
8
9			`2`
10			`/tld_spartan3_sp48k C:\|Documents and Settings\|rodriguj\|Mis documentos\|opencores\|zx_ula\|branches\|xilinx\|ulaplus_replacement-upgrade_for_sp16-48k\|rtl_ulaplus\|ulaplus_tld.v/audio_mix - mixer`
11			`/tld_spartan3_sp48k C:\|Documents and Settings\|rodriguj\|Mis documentos\|opencores\|zx_ula\|branches\|xilinx\|ulaplus_replacement-upgrade_for_sp16-48k\|rtl_ulaplus\|ulaplus_tld.v/the_ula - ula`
12			`/ulaplus_tld C:\|Documents and Settings\|rodriguj\|Mis documentos\|opencores\|zx_ula\|branches\|xilinx\|ulaplus_replacement-upgrade_for_sp16-48k\|rtl_ulaplus\|ulaplus_tld.v/audio_mix - mixer`
13			`/ulaplus_tld C:\|Documents and Settings\|rodriguj\|Mis documentos\|opencores\|zx_ula\|branches\|xilinx\|ulaplus_replacement-upgrade_for_sp16-48k\|rtl_ulaplus\|ulaplus_tld.v/the_ula - ula`
14			`/ulaplus_tld C:\|Documents and Settings\|rodriguj\|Mis documentos\|opencores\|zx_ula\|branches\|xilinx\|ulaplus_replacement-upgrade_for_sp16-48k\|rtl_ulaplus\|ulaplus_tld.v/video_final_stage - rgbdtoa`
15
16
17	29	mcleod_ide	`clock28mhz - master_ula_clock (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw)`
18	26	mcleod_ide
19			`0`
20			`0`
21			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000015f000000020000000000000000000000000000000064ffffffff0000008100000000000000020000015f0000000100000000000000000000000100000000`
22			`false`
23	29	mcleod_ide	`clock28mhz - master_ula_clock (C:/Documents and Settings/rodriguj/Mis documentos/opencores/zx_ula/branches/xilinx/ulaplus_replacement-upgrade_for_sp16-48k/rtl_ulaplus/ipcore_dir/master_ula_clock.xaw)`
24	26	mcleod_ide
25
26
27			`1`
28			`Design Utilities`
29
30
31	29	mcleod_ide
32	26	mcleod_ide
33			`0`
34			`0`
35			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000`
36			`false`
37	29	mcleod_ide
38	26	mcleod_ide
39
40
41			`1`
42
43
44			`0`
45			`0`
46			`000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000040101000100000000000000000000000064ffffffff0000008100000000000000040000005600000001000000000000009d0000000100000000000000660000000100000000000002480000000100000000`
47			`false`
48			`ula_pins.ucf`
49
50
51
52			`1`
53			`work`
54
55
56			`0`
57			`0`
58			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000`
59			`false`
60			`work`
61
62
63
64			`1`
65			`User Constraints`
66
67
68	29	mcleod_ide
69	26	mcleod_ide
70			`0`
71			`0`
72			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000`
73			`false`
74	29	mcleod_ide
75	26	mcleod_ide
76
77
78			`1`
79			`Configure Target Device`
80			`Design Utilities`
81			`Implement Design`
82			`Synthesize - XST`
83			`User Constraints`
84
85
86
87
88			`0`
89			`0`
90			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000`
91			`false`
92
93
94
95
96			`1`
97
98	29	mcleod_ide
99
100
101	26	mcleod_ide	`0`
102			`0`
103	29	mcleod_ide	`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000`
104	26	mcleod_ide	`false`
105
106
107			`000000ff00000000000000020000011b0000011b01000000040100000002`
108			`Implementation`
109

Browse

Tools

Subversion Repositories zx_ula

[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [iseconfig/] [ulaplus_replacement.projectmgr] - Blame information for rev 29