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[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [ulaplus_tld.v] - Blame information for rev 26

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Line No. Rev Author Line
1 26 mcleod_ide 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:        Dept. Architecture and Computing Technology. University of Seville
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// Engineer:       Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
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//
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// Create Date:    19:13:39 4-Apr-2012
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// Design Name:    ULAplus replacement
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// Module Name:    ulaplus_tld
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 1.00 - File Created
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// Additional Comments: GPL License policies apply to the contents of this file.
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ulaplus_tld(
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         // Clock and reset
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    input clk50,
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         input reset,
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         // CPU interface
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         input a15,
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         input a14,
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         input a7,
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         input a6,
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         input a2,
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         input mreq_n,
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         input ioreq_n,
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         input iorq_n,
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         input rd_n,
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         input wr_n,
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         inout [7:0] d,
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         output int_n,
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         output cpuclk_n,
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         // DRAM interface
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         output [6:0] va,
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         output ras_n,
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         output cas_n,
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         output dramwe_n,
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         // ROM interface
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         output romcs_n,
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         // Keyboard & audio interface
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         input [4:0] kbd,
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    output audio_out,
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         input ear,
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         // RGB video interface
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         output [2:0] r,
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         output [2:0] g,
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         output [2:0] b,
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         output csync
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    );
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        wire clk14;
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        master_ula_clock clock14mhz (
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    .CLKIN_IN(clk50),
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    .CLKFX_OUT(clk14),
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    .CLKIN_IBUFG_OUT(),
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    .CLK0_OUT()
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    );
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   /////////////////////////////////////
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   // The ULA
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   /////////////////////////////////////
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        wire ula_r,ula_g,ula_b,ula_i,ulaplus_enabled;
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        wire mic,spk;
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        wire [7:0] rgbulaplus;
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        ula the_ula (
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                .clk14(clk14),
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                .reset_n(reset_n),
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                .a15(a15),
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                .a14(a14),
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                .a7(a7),
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                .a6(a6),
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                .a2(a2),
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                .din(uladin),
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                .dout(uladout),
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                .mreq_n(mreq_n),
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                .ioreq_n(ioreq_n),
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                .iorq_n(iorq_n),
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                .rd_n(rd_n),
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                .wr_n(wr_n),
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                .clkcpu(cpuclk_n),
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                .int_n(int_n),
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                .va(va),
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                .ear(ear),
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                .mic(mic),
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                .spk(spk),
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                .kbd(kbd),
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                .r(ula_r),
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                .g(ula_g),
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                .b(ula_b),
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                .i(ula_i),
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                .rgbulaplus(rgbulaplus),
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                .ulaplus_enabled(ulaplus_enabled),
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                .csync(csync)
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        );
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   /////////////////////////////////////
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   // ULA/ULA+ video selector and enconding
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   /////////////////////////////////////
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   rgb_builder video_final_stage (
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                .select(ulaplus_enabled),
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                .ri(ula_r),
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                .gi(ula_g),
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                .bi(ula_b),
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                .hi(ula_i),
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                .rgbulap(rgbulaplus),
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                .r(r),
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                .g(g),
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                .b(b)
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    );
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   /////////////////////////////////////
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   // Audio mixer
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   /////////////////////////////////////
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        mixer audio_mix (
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                .clkdac(clk14),
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                .reset_n(reset_n),
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                .ear(ear),
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                .mic(mic),
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                .spk(spk),
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                .audio(audio_out)
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        );
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endmodule

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