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[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [cpu.v] - Blame information for rev 21

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:50:27 05/02/2012 
// Design Name: 
// Module Name:    cpu 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
 
module z80memr (
        input clk,
        output [15:0] a,
        output [7:0] d,
        output mreq,
        output rd
        );
 
        reg rmreq = 1;
        reg rrd = 1;
        assign mreq = rmreq;
        assign rd = rrd;
        reg [1:0] estado = 2;
        assign d = 8'bzzzzzzzz;
 
        reg [15:0] ra = 16'h7FFF;
        assign a = ra;
 
        always @(posedge clk) begin
                if (estado==2) begin
                        estado <= 0;
                        ra <= ~ra;
                end
                else
                        estado <= estado + 1;
        end
 
        always @(*) begin
                if (estado==0 && clk)
                        {rmreq,rrd} = 2'b11;
                else if (estado==0 && !clk)
                        {rmreq,rrd} = 2'b00;
                else if (estado==1)
                        {rmreq,rrd} = 2'b00;
                else if (estado==2 && clk)
                        {rmreq,rrd} = 2'b00;
                else
                        {rmreq,rrd} = 2'b11;
        end
endmodule
 
 
module z80memio (
        input clk,
        output [15:0] a,
        output [7:0] d,
        output mreq_n,
        output iorq_n,
        output wr_n,
        output rfsh_n
        );
 
        reg rmreq = 1;
        reg riorq = 1;
        reg rwr = 1;
        reg rrfsh = 1;
        assign mreq_n = rmreq;
        assign iorq_n = riorq;
        assign wr_n = rwr;
        assign rfsh_n = rrfsh;
 
        reg [1:0] estado = 0;
 
        reg [5:0] memioseq = 6'b011001;
        reg [5:0] io2seq =   5'b011000;
        reg [4:0] hiloseq =  5'b01010;
        wire memio = memioseq[0];  // 0 = mem, 1 = io
        wire hilo = hiloseq[0];   // 0 = access to lower RAM/Port FEh
        wire iohi = io2seq[0];    // 0 = port 00FF/00FE, 1 = port 40FE,40FF
 
 
        reg [15:0] ra;
        assign a = ra;
 
        reg [7:0] rd;
        assign d = rd;
 
        reg [7:0] iodata = 0;
        reg [7:0] memdata = 0;
        reg [15:0] memaddr = 16384;
 
        always @(posedge clk) begin
                if (estado==2 && !memio) begin
                        estado <= 0;
                        memioseq <= { memioseq[0], memioseq[5:1] };
                        hiloseq <= { hiloseq[0], hiloseq[4:1] };
                        io2seq <= { io2seq[0], io2seq[5:1] };
                        memdata <= memdata + 1;
                        if (memaddr == 23295)
                                memaddr <= 16384;
                        else
                                memaddr <= memaddr + 1;
                end
                else if (estado==3 && memio) begin
                        estado <= 0;
                        memioseq <= { memioseq[0], memioseq[5:1] };
                        hiloseq <= { hiloseq[0], hiloseq[4:1] };
                        io2seq <= { io2seq[0], io2seq[5:1] };
                        iodata <= iodata + 1;
                end
                else
                        estado <= estado + 1;
        end
 
        always @(*) begin
                if (memio) begin // if this is an I/O bus cycle...
                        case ({estado,clk})
                                3'b001 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = 8'bzzzzzzzz;
                                                        end
                                3'b000 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = iodata;
                                                        end
                                3'b011,3'b010,3'b101,3'b100,3'b111 :
                                         begin
                                                                {rmreq,riorq,rwr} = 3'b100;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = iodata;
                                                        end
                                3'b110 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = iodata;
                                                        end
                        endcase
                end
                else begin      // this is a MEM bus cycle
                        case ({estado,clk})
                                3'b001 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = 8'bzzzzzzzz;
                                                        end
                                3'b000,3'b011 :
                                         begin
                                                                {rmreq,riorq,rwr} = 3'b011;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = memdata;
                                                        end
                                3'b010,3'b101 :
                                         begin
                                                                {rmreq,riorq,rwr} = 3'b010;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = memdata;
                                                        end
                                3'b100 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = memdata;
                                                        end
                        endcase
                end
        end
endmodule

Line No.	Rev	Author	Line
1	21	mcleod_ide	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 16:50:27 05/02/2012`
7			`// Design Name:`
8			`// Module Name: cpu`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21
22			`module z80memr (`
23			`input clk,`
24			`output [15:0] a,`
25			`output [7:0] d,`
26			`output mreq,`
27			`output rd`
28			`);`
29
30			`reg rmreq = 1;`
31			`reg rrd = 1;`
32			`assign mreq = rmreq;`
33			`assign rd = rrd;`
34			`reg [1:0] estado = 2;`
35			`assign d = 8'bzzzzzzzz;`
36
37			`reg [15:0] ra = 16'h7FFF;`
38			`assign a = ra;`
39
40			`always @(posedge clk) begin`
41			`if (estado==2) begin`
42			`estado <= 0;`
43			`ra <= ~ra;`
44			`end`
45			`else`
46			`estado <= estado + 1;`
47			`end`
48
49			`always @(*) begin`
50			`if (estado==0 && clk)`
51			`{rmreq,rrd} = 2'b11;`
52			`else if (estado==0 && !clk)`
53			`{rmreq,rrd} = 2'b00;`
54			`else if (estado==1)`
55			`{rmreq,rrd} = 2'b00;`
56			`else if (estado==2 && clk)`
57			`{rmreq,rrd} = 2'b00;`
58			`else`
59			`{rmreq,rrd} = 2'b11;`
60			`end`
61			`endmodule`
62
63
64			`module z80memio (`
65			`input clk,`
66			`output [15:0] a,`
67			`output [7:0] d,`
68			`output mreq_n,`
69			`output iorq_n,`
70			`output wr_n,`
71			`output rfsh_n`
72			`);`
73
74			`reg rmreq = 1;`
75			`reg riorq = 1;`
76			`reg rwr = 1;`
77			`reg rrfsh = 1;`
78			`assign mreq_n = rmreq;`
79			`assign iorq_n = riorq;`
80			`assign wr_n = rwr;`
81			`assign rfsh_n = rrfsh;`
82
83			`reg [1:0] estado = 0;`
84
85			`reg [5:0] memioseq = 6'b011001;`
86			`reg [5:0] io2seq = 5'b011000;`
87			`reg [4:0] hiloseq = 5'b01010;`
88			`wire memio = memioseq[0]; // 0 = mem, 1 = io`
89			`wire hilo = hiloseq[0]; // 0 = access to lower RAM/Port FEh`
90			`wire iohi = io2seq[0]; // 0 = port 00FF/00FE, 1 = port 40FE,40FF`
91
92
93			`reg [15:0] ra;`
94			`assign a = ra;`
95
96			`reg [7:0] rd;`
97			`assign d = rd;`
98
99			`reg [7:0] iodata = 0;`
100			`reg [7:0] memdata = 0;`
101			`reg [15:0] memaddr = 16384;`
102
103			`always @(posedge clk) begin`
104			`if (estado==2 && !memio) begin`
105			`estado <= 0;`
106			`memioseq <= { memioseq[0], memioseq[5:1] };`
107			`hiloseq <= { hiloseq[0], hiloseq[4:1] };`
108			`io2seq <= { io2seq[0], io2seq[5:1] };`
109			`memdata <= memdata + 1;`
110			`if (memaddr == 23295)`
111			`memaddr <= 16384;`
112			`else`
113			`memaddr <= memaddr + 1;`
114			`end`
115			`else if (estado==3 && memio) begin`
116			`estado <= 0;`
117			`memioseq <= { memioseq[0], memioseq[5:1] };`
118			`hiloseq <= { hiloseq[0], hiloseq[4:1] };`
119			`io2seq <= { io2seq[0], io2seq[5:1] };`
120			`iodata <= iodata + 1;`
121			`end`
122			`else`
123			`estado <= estado + 1;`
124			`end`
125
126			`always @(*) begin`
127			`if (memio) begin // if this is an I/O bus cycle...`
128			`case ({estado,clk})`
129			`3'b001 : begin`
130			`{rmreq,riorq,rwr} = 3'b111;`
131			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
132			`rd = 8'bzzzzzzzz;`
133			`end`
134			`3'b000 : begin`
135			`{rmreq,riorq,rwr} = 3'b111;`
136			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
137			`rd = iodata;`
138			`end`
139			`3'b011,3'b010,3'b101,3'b100,3'b111 :`
140			`begin`
141			`{rmreq,riorq,rwr} = 3'b100;`
142			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
143			`rd = iodata;`
144			`end`
145			`3'b110 : begin`
146			`{rmreq,riorq,rwr} = 3'b111;`
147			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
148			`rd = iodata;`
149			`end`
150			`endcase`
151			`end`
152			`else begin // this is a MEM bus cycle`
153			`case ({estado,clk})`
154			`3'b001 : begin`
155			`{rmreq,riorq,rwr} = 3'b111;`
156			`ra = {hilo,memaddr[14:0]};`
157			`rd = 8'bzzzzzzzz;`
158			`end`
159			`3'b000,3'b011 :`
160			`begin`
161			`{rmreq,riorq,rwr} = 3'b011;`
162			`ra = {hilo,memaddr[14:0]};`
163			`rd = memdata;`
164			`end`
165			`3'b010,3'b101 :`
166			`begin`
167			`{rmreq,riorq,rwr} = 3'b010;`
168			`ra = {hilo,memaddr[14:0]};`
169			`rd = memdata;`
170			`end`
171			`3'b100 : begin`
172			`{rmreq,riorq,rwr} = 3'b111;`
173			`ra = {hilo,memaddr[14:0]};`
174			`rd = memdata;`
175			`end`
176			`endcase`
177			`end`
178			`end`
179			`endmodule`

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[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [cpu.v] - Blame information for rev 21