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[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [signalview_ulaplus.wcfg] - Blame information for rev 21

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      clk7
      clk7
   
   
      Counters
      label
      128 128 255
      230 230 230
   
   
      hc[8:0]
      hc[8:0]
      UNSIGNEDDECRADIX
   
   
      vc[8:0]
      vc[8:0]
      UNSIGNEDDECRADIX
   
   
      Syncs
      label
      128 128 255
      230 230 230
   
   
      HBlank_n
      HBlank_n
   
   
      HSync_n
      HSync_n
   
   
      VSync_n
      VSync_n
   
   
      msk_int_n
      msk_int_n
   
   
      Control clocks
      label
      128 128 255
      230 230 230
   
   
      Border_n
      Border_n
   
   
      VidEN_n
      VidEN_n
   
   
      DataLatch_n
      DataLatch_n
   
   
      AttrLatch_n
      AttrLatch_n
   
   
      SLoad
      SLoad
   
   
      AOLatch_n
      AOLatch_n
   
   
      Data
      label
      128 128 255
      230 230 230
   
   
      clk14
      clk14
   
   
      va[13:0]
      va[13:0]
      HEXRADIX
   
   
      BitmapReg[7:0]
      BitmapReg[7:0]
      HEXRADIX
   
   
      SRegister[7:0]
      SRegister[7:0]
      HEXRADIX
   
   
      AttrReg[7:0]
      AttrReg[7:0]
      HEXRADIX
   
   
      AttrOut[7:0]
      AttrOut[7:0]
      HEXRADIX
   
   
      ULA+ palette address and data buses
      label
      128 128 255
      230 230 230
   
   
      paletteaddr[5:0]
      paletteaddr[5:0]
      UNSIGNEDDECRADIX
   
   
      ULAPlusPaper[7:0]
      ULAPlusPaper[7:0]
      UNSIGNEDDECRADIX
   
   
      ULAPlusInk[7:0]
      ULAPlusInk[7:0]
      UNSIGNEDDECRADIX
   
   
      ULAPlusBorder[7:0]
      ULAPlusBorder[7:0]
      UNSIGNEDDECRADIX
   
   
      ULAPlusPaperOut[7:0]
      ULAPlusPaperOut[7:0]
      UNSIGNEDDECRADIX
   
   
      ULAPlusInkOut[7:0]
      ULAPlusInkOut[7:0]
      UNSIGNEDDECRADIX
   
   
      rRGBULAPlus[7:0]
      rRGBULAPlus[7:0]
      UNSIGNEDDECRADIX
   
   
      TV Output
      label
      128 128 255
      230 230 230
   
   
      RGB
      label
      UNSIGNEDDECRADIX
      
         g
         g
      
      
         r
         r
      
      
         b
         b
      
   
   
      i
      i
   
   
      csync
      csync
   
   
      Contention handler
      label
      128 128 255
      230 230 230
   
   
      CLKContention
      CLKContention
   
   
      Nor1
      Nor1
   
   
      Nor2
      Nor2
   
   
      CPU
      label
      128 128 255
      230 230 230
   
   
      clk7
      clk7
   
   
      clk
      clk
   
   
      a[15:0]
      a[15:0]
      HEXRADIX
   
   
      mreq_n
      mreq_n
   
   
      iorq_n
      iorq_n
   
   
      wr_n
      wr_n
   
   
      d[7:0]
      d[7:0]
      UNSIGNEDDECRADIX
   


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Subversion Repositories zx_ula

[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [signalview_ulaplus.wcfg] - Blame information for rev 21

Line No.	Rev	Author	Line
1	21	mcleod_ide
2
3
4
5
6
7
8
9
10
11
12
13
14
15			`clk7`
16			`clk7`
17
18
19			`Counters`
20			`label`
21			`128 128 255`
22			`230 230 230`
23
24
25			`hc[8:0]`
26			`hc[8:0]`
27			`UNSIGNEDDECRADIX`
28
29
30			`vc[8:0]`
31			`vc[8:0]`
32			`UNSIGNEDDECRADIX`
33
34
35			`Syncs`
36			`label`
37			`128 128 255`
38			`230 230 230`
39
40
41			`HBlank_n`
42			`HBlank_n`
43
44
45			`HSync_n`
46			`HSync_n`
47
48
49			`VSync_n`
50			`VSync_n`
51
52
53			`msk_int_n`
54			`msk_int_n`
55
56
57			`Control clocks`
58			`label`
59			`128 128 255`
60			`230 230 230`
61
62
63			`Border_n`
64			`Border_n`
65
66
67			`VidEN_n`
68			`VidEN_n`
69
70
71			`DataLatch_n`
72			`DataLatch_n`
73
74
75			`AttrLatch_n`
76			`AttrLatch_n`
77
78
79			`SLoad`
80			`SLoad`
81
82
83			`AOLatch_n`
84			`AOLatch_n`
85
86
87			`Data`
88			`label`
89			`128 128 255`
90			`230 230 230`
91
92
93			`clk14`
94			`clk14`
95
96
97			`va[13:0]`
98			`va[13:0]`
99			`HEXRADIX`
100
101
102			`BitmapReg[7:0]`
103			`BitmapReg[7:0]`
104			`HEXRADIX`
105
106
107			`SRegister[7:0]`
108			`SRegister[7:0]`
109			`HEXRADIX`
110
111
112			`AttrReg[7:0]`
113			`AttrReg[7:0]`
114			`HEXRADIX`
115
116
117			`AttrOut[7:0]`
118			`AttrOut[7:0]`
119			`HEXRADIX`
120
121
122			`ULA+ palette address and data buses`
123			`label`
124			`128 128 255`
125			`230 230 230`
126
127
128			`paletteaddr[5:0]`
129			`paletteaddr[5:0]`
130			`UNSIGNEDDECRADIX`
131
132
133			`ULAPlusPaper[7:0]`
134			`ULAPlusPaper[7:0]`
135			`UNSIGNEDDECRADIX`
136
137
138			`ULAPlusInk[7:0]`
139			`ULAPlusInk[7:0]`
140			`UNSIGNEDDECRADIX`
141
142
143			`ULAPlusBorder[7:0]`
144			`ULAPlusBorder[7:0]`
145			`UNSIGNEDDECRADIX`
146
147
148			`ULAPlusPaperOut[7:0]`
149			`ULAPlusPaperOut[7:0]`
150			`UNSIGNEDDECRADIX`
151
152
153			`ULAPlusInkOut[7:0]`
154			`ULAPlusInkOut[7:0]`
155			`UNSIGNEDDECRADIX`
156
157
158			`rRGBULAPlus[7:0]`
159			`rRGBULAPlus[7:0]`
160			`UNSIGNEDDECRADIX`
161
162
163			`TV Output`
164			`label`
165			`128 128 255`
166			`230 230 230`
167
168
169			`RGB`
170			`label`
171			`UNSIGNEDDECRADIX`
172
173			`g`
174			`g`
175
176
177			`r`
178			`r`
179
180
181			`b`
182			`b`
183
184
185
186			`i`
187			`i`
188
189
190			`csync`
191			`csync`
192
193
194			`Contention handler`
195			`label`
196			`128 128 255`
197			`230 230 230`
198
199
200			`CLKContention`
201			`CLKContention`
202
203
204			`Nor1`
205			`Nor1`
206
207
208			`Nor2`
209			`Nor2`
210
211
212			`CPU`
213			`label`
214			`128 128 255`
215			`230 230 230`
216
217
218			`clk7`
219			`clk7`
220
221
222			`clk`
223			`clk`
224
225
226			`a[15:0]`
227			`a[15:0]`
228			`HEXRADIX`
229
230
231			`mreq_n`
232			`mreq_n`
233
234
235			`iorq_n`
236			`iorq_n`
237
238
239			`wr_n`
240			`wr_n`
241
242
243			`d[7:0]`
244			`d[7:0]`
245			`UNSIGNEDDECRADIX`
246
247