URL
https://opencores.org/ocsvn/configurable_crc_core/configurable_crc_core/trunk
Subversion Repositories configurable_crc_core
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/configurable_crc_core/trunk/rtl/cfg_crc.v
0,0 → 1,33
module cfg_crc #( |
parameter datw = 6, |
parameter [datw - 1: 0] coff = 6'b10_0101 |
) |
( |
input clk, rst, |
input rst_syn, |
input crc_en, |
input dat_i, |
output reg [datw - 2: 0] dat_o |
); |
|
wire lsb = dat_i ^ dat_o[datw - 2]; |
integer i; |
|
always@(posedge clk or posedge rst) begin |
if (rst) |
dat_o <= 0; |
else if (rst_syn) |
dat_o <= 0; |
else if (crc_en) begin |
dat_o[0] <= lsb; |
//dat_o[datw - 2: 1] <= dat_o[datw - 3: 0] ^ coff[datw -2: 1]; |
for (i = 0; i <= (datw - 3) ; i = i + 1) begin |
if (coff[i + 1]) |
dat_o[i + 1] <= dat_o[i] ^ lsb; |
else |
dat_o[i + 1] <= dat_o[i]; |
end |
end |
end |
|
endmodule |
/configurable_crc_core/trunk/tb/crc_cmp_tb.v
0,0 → 1,71
module crc_cmp_tb(); |
|
parameter datw = 8; |
reg clk, rst, rst_syn; |
reg crc_en; |
reg [15: 0] random_dat; |
wire dat_i = random_dat[15]; |
wire [datw - 2: 0] dat_o, dat_o_2; |
|
initial begin |
clk = 0; |
forever #5 clk = ~clk; |
end |
|
initial begin |
rst_syn = 0; |
crc_en = 0; |
end |
|
initial begin |
rst = 0; |
#200 rst = 1; |
#20 rst = 0; |
end |
|
initial begin |
@(negedge rst) |
repeat(20) begin |
CRC_task; |
if (dat_o == dat_o_2) |
$display("\tData is correct!\n"); |
end |
end |
|
task CRC_task; |
|
begin |
random_dat = 16'hff;//$random(); |
rst_syn = 1; |
#20 |
rst_syn = 0; |
repeat (16) begin |
crc_en = 1; |
@(posedge clk) |
random_dat = random_dat << 1; |
end |
crc_en = 0; |
end |
endtask |
|
|
cfg_crc |
#( |
.datw(datw), |
.coff(8'b1000_1001) |
) CRC_F0 |
( |
.clk(clk), .rst(rst), |
.rst_syn(rst_syn), |
.crc_en(crc_en), |
.dat_i(dat_i), |
.dat_o(dat_o) |
); |
|
crc_7 CRC_F1( |
.clk(clk), .rst(rst_syn), |
.crc_en(crc_en), |
.sda_i(dat_i), |
.crc_o(dat_o_2) |
); |
endmodule |
/configurable_crc_core/trunk/tb/crc_7.v
0,0 → 1,28
module crc_7( |
input clk, rst, |
input crc_en, |
input sda_i, |
output reg [ 6: 0] crc_o |
); |
|
wire inv = sda_i ^ crc_o[6]; |
//CRC-7 = x7 + x3 + 1 |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
crc_o <= 0; |
end |
else begin |
if (crc_en == 1) begin |
crc_o[6] <= crc_o[5]; |
crc_o[5] <= crc_o[4]; |
crc_o[4] <= crc_o[3]; |
crc_o[3] <= crc_o[2] ^ inv; |
crc_o[2] <= crc_o[1]; |
crc_o[1] <= crc_o[0]; |
crc_o[0] <= inv; |
end |
end |
end |
|
endmodule |
|
/configurable_crc_core/trunk/readme.txt
0,0 → 1,3
I konw little of CRC calculation, |
this module is base on https://www.ghsi.de/CRC/index.php? |
I just make is configurable... |