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/ps2_keyboard_interface/Keyboard_Controller.ucf
0,0 → 1,23
NET "Clk" LOC = "M16"; |
NET "Clk" CLOCK_DEDICATED_ROUTE = FALSE; |
NET "DataIn" LOC = "M15"; |
NET "Enables<0>" LOC = "E13" ; |
NET "Enables<1>" LOC = "F14" ; |
NET "Enables<2>" LOC = "G14" ; |
NET "Enables<3>" LOC = "D14" ; |
NET "Segments<0>" LOC = "E14" ; |
NET "Segments<1>" LOC = "G13" ; |
NET "Segments<2>" LOC = "N15" ; |
NET "Segments<3>" LOC = "P15" ; |
NET "Segments<4>" LOC = "R16" ; |
NET "Segments<5>" LOC = "F13" ; |
NET "Segments<6>" LOC = "N16" ; |
NET "Clk2" LOC = "T9"; |
NET "pressed<0>" LOC = "K12" ; |
NET "pressed<1>" LOC = "P14" ; |
NET "pressed<2>" LOC = "L12" ; |
NET "pressed<3>" LOC = "N14" ; |
NET "pressed<4>" LOC = "P13" ; |
NET "pressed<5>" LOC = "N12" ; |
NET "pressed<6>" LOC = "P12" ; |
NET "pressed<7>" LOC = "P11" ; |
/ps2_keyboard_interface/Keyboard_Controller.bit
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ps2_keyboard_interface/Keyboard_Controller.bit
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Index: ps2_keyboard_interface/Keyboard_Controller.stx
===================================================================
Index: ps2_keyboard_interface/Keyboard_Controller.par
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.par (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.par (revision 2)
@@ -0,0 +1,206 @@
+Release 12.3 par M.70d (lin64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+
+omar:: Fri Dec 03 00:08:23 2010
+
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd
+Keyboard_Controller.ncd Keyboard_Controller.pcf
+
+
+Constraints file: Keyboard_Controller.pcf.
+Loading device for application Rf_Device from file '3s200.nph' in environment /home/omar/ISE_DS/ISE/.
+ "Keyboard_Controller" is an NCD, version 3.2, device xc3s200, package ft256, speed -5
+
+Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
+Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
+
+INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
+ -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
+ internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
+ reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
+ Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
+
+Device speed data version: "PRODUCTION 1.39 2010-09-15".
+
+
+Device Utilization Summary:
+
+ Number of BUFGMUXs 2 out of 8 25%
+ Number of External IOBs 23 out of 173 13%
+ Number of LOCed IOBs 22 out of 23 95%
+
+ Number of Slices 42 out of 1920 2%
+ Number of SLICEMs 2 out of 960 1%
+
+
+
+Overall effort level (-ol): High
+Placer effort level (-pl): High
+Placer cost table entry (-t): 1
+Router effort level (-rl): High
+
+Starting initial Timing Analysis. REAL time: 1 secs
+Finished initial Timing Analysis. REAL time: 1 secs
+
+
+Starting Placer
+Total REAL time at the beginning of Placer: 1 secs
+Total CPU time at the beginning of Placer: 1 secs
+
+Phase 1.1 Initial Placement Analysis
+Phase 1.1 Initial Placement Analysis (Checksum:b776f53f) REAL time: 1 secs
+
+Phase 2.7 Design Feasibility Check
+WARNING:Place:837 - Partially locked IO Bus is found.
+ Following components of the bus are not locked:
+ Comp: Segments<7>
+
+INFO:Place:834 - Only a subset of IOs are locked. Out of 23 IOs, 22 are locked and 1 are not locked. If you would like
+ to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
+Phase 2.7 Design Feasibility Check (Checksum:b776f53f) REAL time: 1 secs
+
+Phase 3.31 Local Placement Optimization
+Phase 3.31 Local Placement Optimization (Checksum:b776f53f) REAL time: 1 secs
+
+Phase 4.2 Initial Clock and IO Placement
+...
+......................
+WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
+ clock site pair. The clock component is placed at site . The IO component is placed
+ at site . This will not allow the use of the fast path between the IO and the Clock buffer. This is normally
+ an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN allowing your design to continue.
+ This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly
+ discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
+ the design.
+Phase 4.2 Initial Clock and IO Placement (Checksum:c750f087) REAL time: 5 secs
+
+Phase 5.36 Local Placement Optimization
+Phase 5.36 Local Placement Optimization (Checksum:c750f087) REAL time: 5 secs
+
+Phase 6.3 Local Placement Optimization
+...
+Phase 6.3 Local Placement Optimization (Checksum:dacaa2e7) REAL time: 5 secs
+
+Phase 7.5 Local Placement Optimization
+Phase 7.5 Local Placement Optimization (Checksum:dacaa2e7) REAL time: 5 secs
+
+Phase 8.8 Global Placement
+..
+..
+Phase 8.8 Global Placement (Checksum:cd0abfbb) REAL time: 5 secs
+
+Phase 9.5 Local Placement Optimization
+Phase 9.5 Local Placement Optimization (Checksum:cd0abfbb) REAL time: 5 secs
+
+Phase 10.18 Placement Optimization
+Phase 10.18 Placement Optimization (Checksum:d439aee6) REAL time: 6 secs
+
+Phase 11.5 Local Placement Optimization
+Phase 11.5 Local Placement Optimization (Checksum:d439aee6) REAL time: 6 secs
+
+Total REAL time to Placer completion: 6 secs
+Total CPU time to Placer completion: 5 secs
+Writing design to file Keyboard_Controller.ncd
+
+
+
+Starting Router
+
+
+Phase 1 : 237 unrouted; REAL time: 6 secs
+
+Phase 2 : 192 unrouted; REAL time: 6 secs
+
+Phase 3 : 41 unrouted; REAL time: 6 secs
+
+Phase 4 : 52 unrouted; (Par is working to improve performance) REAL time: 6 secs
+
+Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
+
+Updating file: Keyboard_Controller.ncd with current fully routed design.
+
+Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
+
+Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 6 secs
+
+Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
+
+Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
+
+Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
+
+Total REAL time to Router completion: 7 secs
+Total CPU time to Router completion: 6 secs
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+Generating "PAR" statistics.
+
+**************************
+Generating Clock Report
+**************************
+
++---------------------+--------------+------+------+------------+-------------+
+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
++---------------------+--------------+------+------+------------+-------------+
+| Clk_BUFGP | BUFGMUX1| No | 23 | 0.000 | 0.881 |
++---------------------+--------------+------+------+------------+-------------+
+| Clk2_BUFGP | BUFGMUX0| No | 7 | 0.000 | 0.881 |
++---------------------+--------------+------+------+------------+-------------+
+
+* Net Skew is the difference between the minimum and maximum routing
+only delays for the net. Note this is different from Clock Skew which
+is reported in TRCE timing report. Clock Skew is the difference between
+the minimum and maximum path delays which includes logic delays.
+
+Timing Score: 0 (Setup: 0, Hold: 0)
+
+Asterisk (*) preceding a constraint indicates it was not met.
+ This may be due to a setup or hold violation.
+
+----------------------------------------------------------------------------------------------------------
+ Constraint | Check | Worst Case | Best Case | Timing | Timing
+ | | Slack | Achievable | Errors | Score
+----------------------------------------------------------------------------------------------------------
+ Autotimespec constraint for clock net Clk | SETUP | N/A| 3.763ns| N/A| 0
+ _BUFGP | HOLD | 0.702ns| | 0| 0
+----------------------------------------------------------------------------------------------------------
+ Autotimespec constraint for clock net Clk | SETUP | N/A| 3.314ns| N/A| 0
+ 2_BUFGP | HOLD | 1.103ns| | 0| 0
+----------------------------------------------------------------------------------------------------------
+
+
+All constraints were met.
+INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
+ constraint is not analyzed due to the following: No paths covered by this
+ constraint; Other constraints intersect with this constraint; or This
+ constraint was disabled by a Path Tracing Control. Please run the Timespec
+ Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
+
+
+Generating Pad Report.
+
+All signals are completely routed.
+
+Total REAL time to PAR completion: 7 secs
+Total CPU time to PAR completion: 7 secs
+
+Peak Memory Usage: 325 MB
+
+Placement: Completed - No errors found.
+Routing: Completed - No errors found.
+
+Number of error messages: 0
+Number of warning messages: 2
+Number of info messages: 2
+
+Writing design to file Keyboard_Controller.ncd
+
+
+
+PAR done!
Index: ps2_keyboard_interface/Keyboard_Controller.unroutes
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.unroutes (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.unroutes (revision 2)
@@ -0,0 +1,9 @@
+Release 12.3 - par M.70d (lin64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+
+Fri Dec 3 00:08:31 2010
+
+All signals are completely routed.
+
+
+
Index: ps2_keyboard_interface/Keyboard_Controller.ngr
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.ngr (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.ngr (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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<`=:<1e5h4<;|aad<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;<0qd?j:188m62=831d484?::aag<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab3<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab=<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab<<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::abd<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::abg<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::abf<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::aba<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab`<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::a22<72=0;6=u+b087`>Ne<2Fi:74=i9;=1>45ri0g94?=n9o0;66g<4;29?j>22900qo87:187>5<7s-h:69j4Hc68Hg0=:r.:>;4>;o313?4>3tc:i7>5;h3e>5<1<75`8483>>{e>00;694?:1y'f4<3l2Bi86Bm6;0x 441281e=?95289~m4c=831b=k4?::k00?6=3f2>6=44}c4b>5<3290;w)l>:5f8Lg2v*>2782?k75?3827pg>e;29?l7a2900e>:50;9l<0<722wi:o4?:583>5}#j80?h6Fm4:Na2?4|,88=6<5a13596<=za8o1<75f1g83>>o4<3:17b6::188yg0d290?6=4?{%`2>1b<@k>0@o852z&263<63g;9;7<6;|k2a?6=3`;m6=44i2694?=h0<0;66sm6e83>1<729q/n<4;d:Ja0>Je>38p(<<9:09m571=:01ve5;n:6>5<Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::aaa<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::aa`<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::aac<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab5<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab4<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab7<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab6<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab1<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab0<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::ab2<72:0;6=u+b087a>Ne<2Fi97?t$4696>{Kj?09w)?=6;38j4402;?0qd?j:188m62=831d484?::a3d<72=0;6=u+b087`>Ne<2Fi:74=i9;=1>l5ri0g94?=n9o0;66g<4;29?j>22900qo9m:187>5<7s-h:69j4Hc68Hg0=:r.:>;4>;o313?4f3tc:i7>5;h3e>5<1<75`8483>>{e?j0;694?:1y'f4<3l2Bi86Bm6;0x 441281e=?952`9~m4c=831b=k4?::k00?6=3f2>6=44}c5g>5<3290;w)l>:5f8Lg2v*>2782?k75?38j7pg>e;29?l7a2900e>:50;9l<0<722wi;h4?:583>5}#j80?h6Fm4:Na2?4|,88=6<5a13596d=za8o1<75f1g83>>o4<3:17b6::188yg1a290?6=4?{%`2>1b<@k>0@o852z&263<63g;9;71<729q/n<4;d:Ja0>Je>38p(<<9:09m571=:h1ve5;n:6>5<0;6=uCb78a!75<3i97)??0;31<>"69:0886*>0g82g>"69<0396*>10813>h68j0;7)?>7;c3?k77m3;0(<<9:09m571=:o1v(o?52`9Y5a<6s881qd<8:188md6=831d4;4?:%:7>=c!>321o0b5=53:9l=h0m0;6)6;:9g8j=5=921d4k4?:%:7>=c5513:8 4742:>0(<>i:0a8 47221?0(:358j46d291/=<<5289m55b=92.:>;4>;o313?4e3t.i=7?=2:X2`?7|9:0ve?950;9j6<<722e3:7>5$969=7=i0:0<76a7b;29 =2=1;1e4>49;:m;g?6=,1>15?5a8286?>i?l3:1(5:5939m<6<332e3j7>5$969=7=i0:0876a60;29 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<`=l91e5h4n;|q`0?6=:r7no76:;62<,0l1h=5a9d8a?xuc03:1?v3ie;:6?80b2:>01hm5359'=c5<4s4lo65;4=gg971=:>m0886*6f;f3?k?b2m1vi850;1x9ce=0<16ji4<4:?5g?533-3m6i>4n8g9a>{tl<0;6>u2fc8;1>;ak39?708m:268 <`=l91e5h4i;|qg0?6=;r7mm76:;62<5?k1?95+9g8g4>h>m3;;7p}k3;297~;a132>70hn:26893?=;=1/5k4k0:l:a?763tyo>7>53z?e234l26>:4=7:971=#1o0o<6`6e;31?xuc93:1?v3i6;:6?8`?2:>01;95359'=c62<,0l1h=5a9d820>{tk:0;6?u2e`8;1>;bj39?7)7i:e28j=50;0x97g=0o16;=4:3:&:b?553g3n6=5rs2394?4|5;k14i527187b>">n3997c7j:09~w66=838p1?o58b9>35<292.2j7==;o;f>7=z{;l1<7<6*6f;11?k?b2:1v?l50;0x97g=0?16;=4:2:&:b?553g3n695rs7494?4|5">n3<>7c7j:19~w32=838p18;5dd9>2a4=z{?91<7j0396*6f;46?k?b2;1v;<50;0x903=lj16:o475:&:b?023g3n6>5rs7394?4|5">n3<>7c7j:59~w36=838p18;5d`9>2<0=z{10396*6f;46?k?b2?1v8k50;0x903=m116::475:&:b?023g3n6:5rs6;94?4|5">n3=37c7j:19~w21=838p18;5e79><54=z{><1<75rs6694?4|5527e8;1>">n3=37c7j:59~w25=838p18;5e39>3f0=z{>81<7:ok426~DED|8tJK\vsO@
\ No newline at end of file
Index: ps2_keyboard_interface/Keyboard_Controller.gise
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.gise (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.gise (revision 2)
@@ -0,0 +1,194 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: ps2_keyboard_interface/Keyboard_Controller_map.mrp
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller_map.mrp (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller_map.mrp (revision 2)
@@ -0,0 +1,176 @@
+Release 12.3 Map M.70d (lin64)
+Xilinx Mapping Report File for Design 'Keyboard_Controller'
+
+Design Information
+------------------
+Command Line : map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off
+-c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd
+Keyboard_Controller.pcf
+Target Device : xc3s200
+Target Package : ft256
+Target Speed : -5
+Mapper Version : spartan3 -- $Revision: 1.52 $
+Mapped Date : Fri Dec 3 00:08:20 2010
+
+Design Summary
+--------------
+Number of errors: 0
+Number of warnings: 0
+Logic Utilization:
+ Number of Slice Flip Flops: 58 out of 3,840 1%
+ Number of 4 input LUTs: 32 out of 3,840 1%
+Logic Distribution:
+ Number of occupied Slices: 42 out of 1,920 2%
+ Number of Slices containing only related logic: 42 out of 42 100%
+ Number of Slices containing unrelated logic: 0 out of 42 0%
+ *See NOTES below for an explanation of the effects of unrelated logic.
+ Total Number of 4 input LUTs: 51 out of 3,840 1%
+ Number used as logic: 30
+ Number used as a route-thru: 19
+ Number used as Shift registers: 2
+
+ The Slice Logic Distribution report is not meaningful if the design is
+ over-mapped for a non-slice resource or if Placement fails.
+
+ Number of bonded IOBs: 23 out of 173 13%
+ Number of BUFGMUXs: 2 out of 8 25%
+
+Average Fanout of Non-Clock Nets: 2.32
+
+Peak Memory Usage: 336 MB
+Total REAL time to MAP completion: 1 secs
+Total CPU time to MAP completion: 1 secs
+
+NOTES:
+
+ Related logic is defined as being logic that shares connectivity - e.g. two
+ LUTs are "related" if they share common inputs. When assembling slices,
+ Map gives priority to combine logic that is related. Doing so results in
+ the best timing performance.
+
+ Unrelated logic shares no connectivity. Map will only begin packing
+ unrelated logic into a slice once 99% of the slices are occupied through
+ related logic packing.
+
+ Note that once logic distribution reaches the 99% level through related
+ logic packing, this does not mean the device is completely utilized.
+ Unrelated logic packing will then begin, continuing until all usable LUTs
+ and FFs are occupied. Depending on your timing budget, increased levels of
+ unrelated logic packing may adversely affect the overall timing performance
+ of your design.
+
+Table of Contents
+-----------------
+Section 1 - Errors
+Section 2 - Warnings
+Section 3 - Informational
+Section 4 - Removed Logic Summary
+Section 5 - Removed Logic
+Section 6 - IOB Properties
+Section 7 - RPMs
+Section 8 - Guide Report
+Section 9 - Area Group and Partition Summary
+Section 10 - Timing Report
+Section 11 - Configuration String Information
+Section 12 - Control Set Information
+Section 13 - Utilization by Hierarchy
+
+Section 1 - Errors
+------------------
+
+Section 2 - Warnings
+--------------------
+
+Section 3 - Informational
+-------------------------
+INFO:MapLib:562 - No environment variables are currently set.
+INFO:LIT:244 - All of the single ended outputs in this design are using slew
+ rate limited output drivers. The delay on speed critical single ended outputs
+ can be dramatically reduced by designating them as fast outputs.
+
+Section 4 - Removed Logic Summary
+---------------------------------
+ 4 block(s) optimized away
+
+Section 5 - Removed Logic
+-------------------------
+
+Optimized Block(s):
+TYPE BLOCK
+GND XST_GND
+VCC XST_VCC
+
+To enable printing of redundant blocks removed and signals merged, set the
+detailed map report option and rerun map.
+
+Section 6 - IOB Properties
+--------------------------
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
+| | | | | Term | Strength | Rate | | | Delay |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| Clk | IOB | INPUT | LVCMOS25 | | | | | | |
+| Clk2 | IOB | INPUT | LVCMOS25 | | | | | | |
+| DataIn | IOB | INPUT | LVCMOS25 | | | | | | |
+| Enables<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Enables<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Enables<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Enables<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| Segments<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| pressed<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+Section 7 - RPMs
+----------------
+
+Section 8 - Guide Report
+------------------------
+Guide not run on this design.
+
+Section 9 - Area Group and Partition Summary
+--------------------------------------------
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+Area Group Information
+----------------------
+
+ No area groups were found in this design.
+
+----------------------
+
+Section 10 - Timing Report
+--------------------------
+This design was not run using timing mode.
+
+Section 11 - Configuration String Details
+-----------------------------------------
+Use the "-detail" map option to print out Configuration Strings
+
+Section 12 - Control Set Information
+------------------------------------
+No control set information for this architecture.
+
+Section 13 - Utilization by Hierarchy
+-------------------------------------
+Use the "-detail" map option to print out the Utilization by Hierarchy section.
Index: ps2_keyboard_interface/Keyboard_Controller.lso
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.lso (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.lso (revision 2)
@@ -0,0 +1 @@
+work
Index: ps2_keyboard_interface/Keyboard_Controller_par.xrpt
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller_par.xrpt (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller_par.xrpt (revision 2)
@@ -0,0 +1,1913 @@
+
+
+
+
+
+
+
+
+
+ -
+
+
+
+
+
+
+
+
+
+
+ -
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: ps2_keyboard_interface/Keyboard_Controller.bld
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.bld (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.bld (revision 2)
@@ -0,0 +1,37 @@
+Release 12.3 ngdbuild M.70d (lin64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+
+Command Line: /home/omar/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle ise
+-dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5
+Keyboard_Controller.ngc Keyboard_Controller.ngd
+
+Reading NGO file
+"/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.ngc" ...
+Gathering constraint information from source properties...
+Done.
+
+Annotating constraints to design from ucf file "Keyboard_Controller.ucf" ...
+Resolving constraint associations...
+Checking Constraint Associations...
+Done...
+
+Checking expanded design ...
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+ Number of errors: 0
+ Number of warnings: 0
+
+Total memory usage is 244240 kilobytes
+
+Writing NGD file "Keyboard_Controller.ngd" ...
+Total REAL time to NGDBUILD completion: 2 sec
+Total CPU time to NGDBUILD completion: 2 sec
+
+Writing NGDBUILD log file "Keyboard_Controller.bld"...
Index: ps2_keyboard_interface/Keyboard_Controller_map.ncd
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller_map.ncd (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller_map.ncd (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###5244:XlxV32DM 3fff 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wYM5y//ZOQsfm7OCF48hho7NWcuXz1my2OIpUZ2zfInj+jkLp4MImtXNWTgdRMJazFlREUoZRFoRSB1E5P84iOJjg8iSg4i8dBDhY4NIl4MofNkgMuXkAq7zQWTpCpgPIl8B80GEFLAYREp7ZRDJARMXgygfHLEyiMwCk4MoH1ixOohIDh4MouBnBxE9Noiilw8icmwQhS8fRHI1BqcHgyj4HwTnL2o=###3932:XlxV32DM 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\ No newline at end of file
Index: ps2_keyboard_interface/Keyboard_Controller.ptwx
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.ptwx (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.ptwx (revision 2)
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+]>
+Autotimespec constraint for clock net Clk_BUFGP Autotimespec constraint for clock net Clk2_BUFGP 0 INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
+2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
+3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator.
+
+INPUT FILE: Keyboard_Controller_map.ncd
+OUTPUT FILE: Keyboard_Controller_pad.txt
+PART TYPE: xc3s200
+SPEED GRADE: -5
+PACKAGE: ft256
+
+Pinout by Pin Number:
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+|A1 | | |GND | | | | | | | | | | | |
+|A2 | | |TDI | | | | | | | | | | | |
+|A3 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | |
+|A4 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | |
+|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | |
+|A6 | | |VCCAUX | | | | | | | |2.5 | | | |
+|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | |
+|A8 | |DIFFM |IO_L32P_0/GCLK6 |UNUSED | |0 | | | | | | | | |
+|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | |
+|A10 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
+|A11 | | |VCCAUX | | | | | | | |2.5 | | | |
+|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | |
+|A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
+|A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | |
+|A15 | | |TDO | | | | | | | | | | | |
+|A16 | | |GND | | | | | | | | | | | |
+|B1 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | |
+|B2 | | |GND | | | | | | | | | | | |
+|B3 | | |PROG_B | | | | | | | | | | | |
+|B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | |
+|B5 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | |
+|B6 | |DIFFM |IO_L28P_0 |UNUSED | |0 | | | | | | | | |
+|B7 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | |
+|B8 | |DIFFS |IO_L32N_0/GCLK7 |UNUSED | |0 | | | | | | | | |
+|B9 | | |GND | | | | | | | | | | | |
+|B10 | |DIFFM |IO_L31P_1 |UNUSED | |1 | | | | | | | | |
+|B11 | |DIFFS |IO_L29N_1 |UNUSED | |1 | | | | | | | | |
+|B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | |
+|B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | |
+|B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | |
+|B15 | | |GND | | | | | | | | | | | |
+|B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | |
+|C1 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | |
+|C2 | |DIFFS |IO_L16N_7 |UNUSED | |7 | | | | | | | | |
+|C3 | |DIFFM |IO_L16P_7/VREF_7 |UNUSED | |7 | | | | | | | | |
+|C4 | | |HSWAP_EN | | | | | | | | | | | |
+|C5 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | |
+|C6 | |DIFFS |IO_L28N_0 |UNUSED | |0 | | | | | | | | |
+|C7 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | |
+|C8 | |DIFFM |IO_L31P_0/VREF_0 |UNUSED | |0 | | | | | | | | |
+|C9 | |DIFFS |IO_L32N_1/GCLK5 |UNUSED | |1 | | | | | | | | |
+|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | |
+|C11 | |DIFFM |IO_L29P_1 |UNUSED | |1 | | | | | | | | |
+|C12 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | |
+|C13 | | |TMS | | | | | | | | | | | |
+|C14 | | |TCK | | | | | | | | | | | |
+|C15 | |DIFFS |IO_L16N_2 |UNUSED | |2 | | | | | | | | |
+|C16 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | |
+|D1 | |DIFFS |IO_L17N_7 |UNUSED | |7 | | | | | | | | |
+|D2 | |DIFFM |IO_L17P_7 |UNUSED | |7 | | | | | | | | |
+|D3 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | |
+|D4 | | |VCCINT | | | | | | | |1.2 | | | |
+|D5 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | |
+|D6 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | |
+|D7 | |DIFFM |IO_L29P_0 |UNUSED | |0 | | | | | | | | |
+|D8 | |DIFFS |IO_L31N_0 |UNUSED | |0 | | | | | | | | |
+|D9 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | |
+|D10 | |DIFFS |IO_L30N_1 |UNUSED | |1 | | | | | | | | |
+|D11 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | |
+|D12 | |IOB |IO/VREF_1 |UNUSED | |1 | | | | | | | | |
+|D13 | | |VCCINT | | | | | | | |1.2 | | | |
+|D14 |Enables<3> |IOB |IO_L16P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|D15 | |DIFFS |IO_L17N_2 |UNUSED | |2 | | | | | | | | |
+|D16 | |DIFFM |IO_L17P_2/VREF_2 |UNUSED | |2 | | | | | | | | |
+|E1 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | |
+|E2 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | |
+|E3 | |DIFFS |IO_L19N_7/VREF_7 |UNUSED | |7 | | | | | | | | |
+|E4 | |DIFFM |IO_L21P_7 |UNUSED | |7 | | | | | | | | |
+|E5 | | |VCCINT | | | | | | | |1.2 | | | |
+|E6 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | |
+|E7 | |DIFFS |IO_L29N_0 |UNUSED | |0 | | | | | | | | |
+|E8 | | |VCCO_0 | | |0 | | | | |any******| | | |
+|E9 | | |VCCO_1 | | |1 | | | | |any******| | | |
+|E10 | |DIFFM |IO_L30P_1 |UNUSED | |1 | | | | | | | | |
+|E11 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | |
+|E12 | | |VCCINT | | | | | | | |1.2 | | | |
+|E13 |Enables<0> |IOB |IO_L19N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|E14 |Segments<0>|IOB |IO_L19P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|E15 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | |
+|E16 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | |
+|F1 | | |VCCAUX | | | | | | | |2.5 | | | |
+|F2 | |DIFFS |IO_L22N_7 |UNUSED | |7 | | | | | | | | |
+|F3 | |DIFFM |IO_L22P_7 |UNUSED | |7 | | | | | | | | |
+|F4 | |DIFFS |IO_L21N_7 |UNUSED | |7 | | | | | | | | |
+|F5 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | |
+|F6 | | |GND | | | | | | | | | | | |
+|F7 | | |VCCO_0 | | |0 | | | | |any******| | | |
+|F8 | | |VCCO_0 | | |0 | | | | |any******| | | |
+|F9 | | |VCCO_1 | | |1 | | | | |any******| | | |
+|F10 | | |VCCO_1 | | |1 | | | | |any******| | | |
+|F11 | | |GND | | | | | | | | | | | |
+|F12 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | |
+|F13 |Segments<5>|IOB |IO_L21P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|F14 |Enables<1> |IOB |IO_L22N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|F15 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | |
+|F16 | | |VCCAUX | | | | | | | |2.5 | | | |
+|G1 | |DIFFM |IO_L40P_7 |UNUSED | |7 | | | | | | | | |
+|G2 | |DIFFS |IO |UNUSED | |7 | | | | | | | | |
+|G3 | |DIFFS |IO_L24N_7 |UNUSED | |7 | | | | | | | | |
+|G4 | |DIFFM |IO_L24P_7 |UNUSED | |7 | | | | | | | | |
+|G5 | |DIFFS |IO_L23N_7 |UNUSED | |7 | | | | | | | | |
+|G6 | | |VCCO_7 | | |7 | | | | |any******| | | |
+|G7 | | |GND | | | | | | | | | | | |
+|G8 | | |GND | | | | | | | | | | | |
+|G9 | | |GND | | | | | | | | | | | |
+|G10 | | |GND | | | | | | | | | | | |
+|G11 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
+|G12 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | |
+|G13 |Segments<1>|IOB |IO_L23P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|G14 |Enables<2> |IOB |IO_L24N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|G15 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | |
+|G16 | |DIFFM |IO |UNUSED | |2 | | | | | | | | |
+|H1 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | |
+|H2 | | |GND | | | | | | | | | | | |
+|H3 | |DIFFS |IO_L39N_7 |UNUSED | |7 | | | | | | | | |
+|H4 | |DIFFM |IO_L39P_7 |UNUSED | |7 | | | | | | | | |
+|H5 | | |VCCO_7 | | |7 | | | | |any******| | | |
+|H6 | | |VCCO_7 | | |7 | | | | |any******| | | |
+|H7 | | |GND | | | | | | | | | | | |
+|H8 | | |GND | | | | | | | | | | | |
+|H9 | | |GND | | | | | | | | | | | |
+|H10 | | |GND | | | | | | | | | | | |
+|H11 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
+|H12 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
+|H13 | |DIFFS |IO_L39N_2 |UNUSED | |2 | | | | | | | | |
+|H14 | |DIFFM |IO_L39P_2 |UNUSED | |2 | | | | | | | | |
+|H15 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | |
+|H16 |Segments<7>|IOB |IO_L40P_2/VREF_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
+|J1 | |DIFFM |IO_L40P_6/VREF_6 |UNUSED | |6 | | | | | | | | |
+|J2 | |DIFFS |IO_L40N_6 |UNUSED | |6 | | | | | | | | |
+|J3 | |DIFFM |IO_L39P_6 |UNUSED | |6 | | | | | | | | |
+|J4 | |DIFFS |IO_L39N_6 |UNUSED | |6 | | | | | | | | |
+|J5 | | |VCCO_6 | | |6 | | | | |any******| | | |
+|J6 | | |VCCO_6 | | |6 | | | | |any******| | | |
+|J7 | | |GND | | | | | | | | | | | |
+|J8 | | |GND | | | | | | | | | | | |
+|J9 | | |GND | | | | | | | | | | | |
+|J10 | | |GND | | | | | | | | | | | |
+|J11 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
+|J12 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
+|J13 | |DIFFM |IO_L39P_3 |UNUSED | |3 | | | | | | | | |
+|J14 | |DIFFS |IO_L39N_3 |UNUSED | |3 | | | | | | | | |
+|J15 | | |GND | | | | | | | | | | | |
+|J16 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | |
+|K1 | |DIFFM |IO |UNUSED | |6 | | | | | | | | |
+|K2 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | |
+|K3 | |DIFFS |IO_L24N_6/VREF_6 |UNUSED | |6 | | | | | | | | |
+|K4 | |DIFFM |IO_L23P_6 |UNUSED | |6 | | | | | | | | |
+|K5 | |DIFFS |IO_L23N_6 |UNUSED | |6 | | | | | | | | |
+|K6 | | |VCCO_6 | | |6 | | | | |any******| | | |
+|K7 | | |GND | | | | | | | | | | | |
+|K8 | | |GND | | | | | | | | | | | |
+|K9 | | |GND | | | | | | | | | | | |
+|K10 | | |GND | | | | | | | | | | | |
+|K11 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
+|K12 |pressed<0> |IOB |IO_L23N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|K13 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | |
+|K14 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | |
+|K15 | |DIFFS |IO |UNUSED | |3 | | | | | | | | |
+|K16 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | |
+|L1 | | |VCCAUX | | | | | | | |2.5 | | | |
+|L2 | |DIFFM |IO_L22P_6 |UNUSED | |6 | | | | | | | | |
+|L3 | |DIFFS |IO_L22N_6 |UNUSED | |6 | | | | | | | | |
+|L4 | |DIFFM |IO_L21P_6 |UNUSED | |6 | | | | | | | | |
+|L5 | |DIFFS |IO_L21N_6 |UNUSED | |6 | | | | | | | | |
+|L6 | | |GND | | | | | | | | | | | |
+|L7 | | |VCCO_5 | | |5 | | | | |any******| | | |
+|L8 | | |VCCO_5 | | |5 | | | | |any******| | | |
+|L9 | | |VCCO_4 | | |4 | | | | |2.50 | | | |
+|L10 | | |VCCO_4 | | |4 | | | | |2.50 | | | |
+|L11 | | |GND | | | | | | | | | | | |
+|L12 |pressed<2> |IOB |IO_L23P_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|L13 | |DIFFS |IO_L21N_3 |UNUSED | |3 | | | | | | | | |
+|L14 | |DIFFM |IO_L22P_3 |UNUSED | |3 | | | | | | | | |
+|L15 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | |
+|L16 | | |VCCAUX | | | | | | | |2.5 | | | |
+|M1 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | |
+|M2 | |DIFFS |IO_L20N_6 |UNUSED | |6 | | | | | | | | |
+|M3 | |DIFFM |IO_L19P_6 |UNUSED | |6 | | | | | | | | |
+|M4 | |DIFFS |IO_L19N_6 |UNUSED | |6 | | | | | | | | |
+|M5 | | |VCCINT | | | | | | | |1.2 | | | |
+|M6 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | |
+|M7 | |DIFFM |IO_L30P_5 |UNUSED | |5 | | | | | | | | |
+|M8 | | |VCCO_5 | | |5 | | | | |any******| | | |
+|M9 | | |VCCO_4 | | |4 | | | | |2.50 | | | |
+|M10 | |DIFFS |IO_L29N_4 |UNUSED | |4 | | | | | | | | |
+|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | |
+|M12 | | |VCCINT | | | | | | | |1.2 | | | |
+|M13 | |DIFFM |IO_L21P_3 |UNUSED | |3 | | | | | | | | |
+|M14 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | |
+|M15 |DataIn |IOB |IO_L20P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
+|M16 |Clk |IOB |IO_L20N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
+|N1 | |DIFFM |IO_L17P_6/VREF_6 |UNUSED | |6 | | | | | | | | |
+|N2 | |DIFFS |IO_L17N_6 |UNUSED | |6 | | | | | | | | |
+|N3 | |DIFFM |IO_L16P_6 |UNUSED | |6 | | | | | | | | |
+|N4 | | |VCCINT | | | | | | | |1.2 | | | |
+|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | |
+|N6 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | |
+|N7 | |DIFFS |IO_L30N_5 |UNUSED | |5 | | | | | | | | |
+|N8 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | |
+|N9 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | |
+|N10 | |DIFFM |IO_L29P_4 |UNUSED | |4 | | | | | | | | |
+|N11 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | |
+|N12 |pressed<5> |IOB |IO/VREF_4 |OUTPUT |LVCMOS25* |4 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|N13 | | |VCCINT | | | | | | | |1.2 | | | |
+|N14 |pressed<3> |IOB |IO_L19P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|N15 |Segments<2>|IOB |IO_L17P_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|N16 |Segments<6>|IOB |IO_L17N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|P1 | |DIFFM |IO_L01P_6/VRN_6 |UNUSED | |6 | | | | | | | | |
+|P2 | |DIFFS |IO_L16N_6 |UNUSED | |6 | | | | | | | | |
+|P3 | | |M0 | | | | | | | | | | | |
+|P4 | | |M2 | | | | | | | | | | | |
+|P5 | |DIFFM |IO_L27P_5 |UNUSED | |5 | | | | | | | | |
+|P6 | |DIFFM |IO_L29P_5/VREF_5 |UNUSED | |5 | | | | | | | | |
+|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | |
+|P8 | |DIFFS |IO_L32N_5/GCLK3 |UNUSED | |5 | | | | | | | | |
+|P9 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | |
+|P10 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | |
+|P11 |pressed<7> |IOB |IO_L28N_4 |OUTPUT |LVCMOS25* |4 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|P12 |pressed<6> |IOB |IO_L25N_4 |OUTPUT |LVCMOS25* |4 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|P13 |pressed<4> |IOB |IO/VREF_4 |OUTPUT |LVCMOS25* |4 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|P14 |pressed<1> |IOB |IO_L16P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|P15 |Segments<3>|IOB |IO_L16N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|P16 | |DIFFS |IO_L01N_3/VRP_3 |UNUSED | |3 | | | | | | | | |
+|R1 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | |
+|R2 | | |GND | | | | | | | | | | | |
+|R3 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | |
+|R4 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | |
+|R5 | |DIFFS |IO_L27N_5/VREF_5 |UNUSED | |5 | | | | | | | | |
+|R6 | |DIFFS |IO_L29N_5 |UNUSED | |5 | | | | | | | | |
+|R7 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | |
+|R8 | | |GND | | | | | | | | | | | |
+|R9 | |DIFFS |IO_L32N_4/GCLK1 |UNUSED | |4 | | | | | | | | |
+|R10 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | |
+|R11 | |DIFFM |IO_L28P_4 |UNUSED | |4 | | | | | | | | |
+|R12 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | |
+|R13 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | |
+|R14 | | |DONE | | | | | | | | | | | |
+|R15 | | |GND | | | | | | | | | | | |
+|R16 |Segments<4>|IOB |IO_L01P_3/VRN_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
+|T1 | | |GND | | | | | | | | | | | |
+|T2 | | |M1 | | | | | | | | | | | |
+|T3 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | |
+|T4 | |DIFFS |IO_L10N_5/VRP_5 |UNUSED | |5 | | | | | | | | |
+|T5 | |IOB |IO |UNUSED | |5 | | | | | | | | |
+|T6 | | |VCCAUX | | | | | | | |2.5 | | | |
+|T7 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | |
+|T8 | |IOB |IO/VREF_5 |UNUSED | |5 | | | | | | | | |
+|T9 |Clk2 |IOB |IO_L32P_4/GCLK0 |INPUT |LVCMOS25* |4 | | | |NONE | |LOCATED |NO |NONE |
+|T10 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
+|T11 | | |VCCAUX | | | | | | | |2.5 | | | |
+|T12 | |IOB |IO |UNUSED | |4 | | | | | | | | |
+|T13 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | |
+|T14 | |DIFFS |IO |UNUSED | |4 | | | | | | | | |
+|T15 | | |CCLK | | | | | | | | | | | |
+|T16 | | |GND | | | | | | | | | | | |
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+* Default value.
+** This default Pullup/Pulldown value can be overridden in Bitgen.
+****** Special VCCO requirements may apply. Please consult the device
+ family datasheet for specific guideline on VCCO requirements.
+
+
Index: ps2_keyboard_interface/iseconfig/Keyboard_Controller.xreport
===================================================================
--- ps2_keyboard_interface/iseconfig/Keyboard_Controller.xreport (nonexistent)
+++ ps2_keyboard_interface/iseconfig/Keyboard_Controller.xreport (revision 2)
@@ -0,0 +1,217 @@
+
+
+
+ 2010-12-02T22:57:52
+ Keyboard_Controller
+ 2010-12-02T22:47:59
+ /home/omar/MyOpenCores/Keyboard_Controller/iseconfig/Keyboard_Controller.xreport
+ /home/omar/MyOpenCores/Keyboard_Controller/
+ 2010-12-02T22:19:25
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: ps2_keyboard_interface/SevenSegment.cmd_log
===================================================================
--- ps2_keyboard_interface/SevenSegment.cmd_log (nonexistent)
+++ ps2_keyboard_interface/SevenSegment.cmd_log (revision 2)
@@ -0,0 +1 @@
+vhdtdtfi -prj Keyboard_Controller -o /home/omar/MyOpenCores/Keyboard_Controller/SevenSegment.vhi -lib work /home/omar/Mano/Mano//SevenSegment.vhd -module SevenSegment -template /home/omar/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror
Index: ps2_keyboard_interface/Keyboard_Controller.cmd_log
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.cmd_log (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.cmd_log (revision 2)
@@ -0,0 +1,72 @@
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+xst -intstyle ise -ifn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.xst" -ofn "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Keyboard_Controller.ucf -p xc3s200-ft256-5 Keyboard_Controller.ngc Keyboard_Controller.ngd
+map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off -c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd Keyboard_Controller.pcf
+par -w -intstyle ise -ol high -t 1 Keyboard_Controller_map.ncd Keyboard_Controller.ncd Keyboard_Controller.pcf
+trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+bitgen -intstyle ise -f Keyboard_Controller.ut Keyboard_Controller.ncd
Index: ps2_keyboard_interface/webtalk.log
===================================================================
--- ps2_keyboard_interface/webtalk.log (nonexistent)
+++ ps2_keyboard_interface/webtalk.log (revision 2)
@@ -0,0 +1,16 @@
+Release 12.3 - WebTalk (M.70d)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+
+Project Information
+--------------------
+ProjectID=3B4FE3E2530F3D173AEA023E56D4E7AC
+ProjectIteration=11
+
+WebTalk Summary
+----------------
+INFO:WebTalk:2 - WebTalk is enabled.
+
+INFO:WebTalk:8 - WebTalk Install setting is ON.
+INFO:WebTalk:6 - WebTalk User setting is ON.
+
+INFO:WebTalk:5 - /home/omar/MyOpenCores/Keyboard_Controller/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at /home/omar/ISE_DS/ISE/data/reports/webtalk_introduction.html
Index: ps2_keyboard_interface/Keyboard_Controller.drc
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.drc (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.drc (revision 2)
@@ -0,0 +1,8 @@
+Release 12.3 Drc M.70d (lin64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+
+Fri Dec 3 00:08:34 2010
+
+drc -z Keyboard_Controller.ncd Keyboard_Controller.pcf
+
+DRC detected 0 errors and 0 warnings.
Index: ps2_keyboard_interface/Keyboard_Controller_map.map
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller_map.map (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller_map.map (revision 2)
@@ -0,0 +1,71 @@
+Release 12.3 Map M.70d (lin64)
+Xilinx Map Application Log File for Design 'Keyboard_Controller'
+
+Design Information
+------------------
+Command Line : map -intstyle ise -p xc3s200-ft256-5 -cm area -ir off -pr off
+-c 100 -o Keyboard_Controller_map.ncd Keyboard_Controller.ngd
+Keyboard_Controller.pcf
+Target Device : xc3s200
+Target Package : ft256
+Target Speed : -5
+Mapper Version : spartan3 -- $Revision: 1.52 $
+Mapped Date : Fri Dec 3 00:08:20 2010
+
+Mapping design into LUTs...
+Running directed packing...
+Running delay-based LUT packing...
+Running related packing...
+Updating timing models...
+
+Design Summary
+--------------
+
+Design Summary:
+Number of errors: 0
+Number of warnings: 0
+Logic Utilization:
+ Number of Slice Flip Flops: 58 out of 3,840 1%
+ Number of 4 input LUTs: 32 out of 3,840 1%
+Logic Distribution:
+ Number of occupied Slices: 42 out of 1,920 2%
+ Number of Slices containing only related logic: 42 out of 42 100%
+ Number of Slices containing unrelated logic: 0 out of 42 0%
+ *See NOTES below for an explanation of the effects of unrelated logic.
+ Total Number of 4 input LUTs: 51 out of 3,840 1%
+ Number used as logic: 30
+ Number used as a route-thru: 19
+ Number used as Shift registers: 2
+
+ The Slice Logic Distribution report is not meaningful if the design is
+ over-mapped for a non-slice resource or if Placement fails.
+
+ Number of bonded IOBs: 23 out of 173 13%
+ Number of BUFGMUXs: 2 out of 8 25%
+
+Average Fanout of Non-Clock Nets: 2.32
+
+Peak Memory Usage: 336 MB
+Total REAL time to MAP completion: 1 secs
+Total CPU time to MAP completion: 1 secs
+
+NOTES:
+
+ Related logic is defined as being logic that shares connectivity - e.g. two
+ LUTs are "related" if they share common inputs. When assembling slices,
+ Map gives priority to combine logic that is related. Doing so results in
+ the best timing performance.
+
+ Unrelated logic shares no connectivity. Map will only begin packing
+ unrelated logic into a slice once 99% of the slices are occupied through
+ related logic packing.
+
+ Note that once logic distribution reaches the 99% level through related
+ logic packing, this does not mean the device is completely utilized.
+ Unrelated logic packing will then begin, continuing until all usable LUTs
+ and FFs are occupied. Depending on your timing budget, increased levels of
+ unrelated logic packing may adversely affect the overall timing performance
+ of your design.
+
+Mapping completed.
+See MAP report file "Keyboard_Controller_map.mrp" for details.
Index: ps2_keyboard_interface/Keyboard_Controller.twr
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.twr (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.twr (revision 2)
@@ -0,0 +1,117 @@
+--------------------------------------------------------------------------------
+Release 12.3 Trace (lin64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+
+/home/omar/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3
+-fastpaths -xml Keyboard_Controller.twx Keyboard_Controller.ncd -o
+Keyboard_Controller.twr Keyboard_Controller.pcf -ucf Keyboard_Controller.ucf
+
+Design file: Keyboard_Controller.ncd
+Physical constraint file: Keyboard_Controller.pcf
+Device,package,speed: xc3s200,ft256,-5 (PRODUCTION 1.39 2010-09-15)
+Report level: verbose report
+
+Environment Variable Effect
+-------------------- ------
+NONE No environment variables were set
+--------------------------------------------------------------------------------
+
+INFO:Timing:2698 - No timing constraints found, doing default enumeration.
+INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
+ option. All paths that are not constrained will be reported in the
+ unconstrained paths section(s) of the report.
+INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
+ a 50 Ohm transmission line loading model. For the details of this model,
+ and for more information on accounting for different loading conditions,
+ please see the device datasheet.
+INFO:Timing:3390 - This architecture does not support a default System Jitter
+ value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
+ Uncertainty calculation.
+INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
+ 'Phase Error' calculations, these terms will be zero in the Clock
+ Uncertainty calculation. Please make appropriate modification to
+ SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
+ Error.
+
+
+
+Data Sheet report:
+-----------------
+All values displayed in nanoseconds (ns)
+
+Setup/Hold to clock Clk
+------------+------------+------------+------------------+--------+
+ |Max Setup to|Max Hold to | | Clock |
+Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
+------------+------------+------------+------------------+--------+
+DataIn | -1.282(F)| 2.962(F)|Clk_BUFGP | 0.000|
+------------+------------+------------+------------------+--------+
+
+Clock Clk to Pad
+------------+------------+------------------+--------+
+ | clk (edge) | | Clock |
+Destination | to PAD |Internal Clock(s) | Phase |
+------------+------------+------------------+--------+
+Segments<0> | 15.527(F)|Clk_BUFGP | 0.000|
+Segments<1> | 15.547(F)|Clk_BUFGP | 0.000|
+Segments<2> | 14.902(F)|Clk_BUFGP | 0.000|
+Segments<3> | 14.832(F)|Clk_BUFGP | 0.000|
+Segments<4> | 14.881(F)|Clk_BUFGP | 0.000|
+Segments<5> | 15.667(F)|Clk_BUFGP | 0.000|
+Segments<6> | 14.621(F)|Clk_BUFGP | 0.000|
+pressed<0> | 11.811(F)|Clk_BUFGP | 0.000|
+pressed<1> | 10.757(F)|Clk_BUFGP | 0.000|
+pressed<2> | 11.797(F)|Clk_BUFGP | 0.000|
+pressed<3> | 11.135(F)|Clk_BUFGP | 0.000|
+pressed<4> | 11.133(F)|Clk_BUFGP | 0.000|
+pressed<5> | 10.677(F)|Clk_BUFGP | 0.000|
+pressed<6> | 10.652(F)|Clk_BUFGP | 0.000|
+pressed<7> | 10.781(F)|Clk_BUFGP | 0.000|
+------------+------------+------------------+--------+
+
+Clock Clk2 to Pad
+------------+------------+------------------+--------+
+ | clk (edge) | | Clock |
+Destination | to PAD |Internal Clock(s) | Phase |
+------------+------------+------------------+--------+
+Enables<0> | 10.006(R)|Clk2_BUFGP | 0.000|
+Enables<1> | 9.793(R)|Clk2_BUFGP | 0.000|
+Enables<2> | 9.495(R)|Clk2_BUFGP | 0.000|
+Enables<3> | 10.361(R)|Clk2_BUFGP | 0.000|
+Segments<0> | 12.189(R)|Clk2_BUFGP | 0.000|
+Segments<1> | 12.586(R)|Clk2_BUFGP | 0.000|
+Segments<2> | 11.867(R)|Clk2_BUFGP | 0.000|
+Segments<3> | 11.528(R)|Clk2_BUFGP | 0.000|
+Segments<4> | 11.497(R)|Clk2_BUFGP | 0.000|
+Segments<5> | 12.433(R)|Clk2_BUFGP | 0.000|
+Segments<6> | 11.330(R)|Clk2_BUFGP | 0.000|
+------------+------------+------------------+--------+
+
+Clock to Setup on destination clock Clk
+---------------+---------+---------+---------+---------+
+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+---------------+---------+---------+---------+---------+
+Clk | | | | 3.763|
+---------------+---------+---------+---------+---------+
+
+Clock to Setup on destination clock Clk2
+---------------+---------+---------+---------+---------+
+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+---------------+---------+---------+---------+---------+
+Clk2 | 3.314| | | |
+---------------+---------+---------+---------+---------+
+
+
+Analysis completed Fri Dec 3 00:08:32 2010
+--------------------------------------------------------------------------------
+
+Trace Settings:
+-------------------------
+Trace Settings
+
+Peak Memory Usage: 208 MB
+
+
+
Index: ps2_keyboard_interface/Keyboard_Controller_bitgen.xwbt
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller_bitgen.xwbt (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller_bitgen.xwbt (revision 2)
@@ -0,0 +1,8 @@
+INTSTYLE=ise
+INFILE=/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.ncd
+OUTFILE=/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.bit
+FAMILY=Spartan3
+PART=xc3s200-5ft256
+WORKINGDIR=/home/omar/MyOpenCores/Keyboard_Controller
+LICENSE=WebPack
+USER_INFO=0_0_316
Index: ps2_keyboard_interface/Keyboard_Controller_summary.xml
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller_summary.xml (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller_summary.xml (revision 2)
@@ -0,0 +1,10 @@
+
+
+
+
+
+
Index: ps2_keyboard_interface/Keyboard_Controller.syr
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.syr (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.syr (revision 2)
@@ -0,0 +1,484 @@
+Release 12.3 - xst M.70d (lin64)
+Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+-->
+Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.04 secs
+
+-->
+Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.04 secs
+
+-->
+Reading design: Keyboard_Controller.prj
+
+TABLE OF CONTENTS
+ 1) Synthesis Options Summary
+ 2) HDL Compilation
+ 3) Design Hierarchy Analysis
+ 4) HDL Analysis
+ 5) HDL Synthesis
+ 5.1) HDL Synthesis Report
+ 6) Advanced HDL Synthesis
+ 6.1) Advanced HDL Synthesis Report
+ 7) Low Level Synthesis
+ 8) Partition Report
+ 9) Final Report
+ 9.1) Device utilization summary
+ 9.2) Partition Resource Summary
+ 9.3) TIMING REPORT
+
+
+=========================================================================
+* Synthesis Options Summary *
+=========================================================================
+---- Source Parameters
+Input File Name : "Keyboard_Controller.prj"
+Input Format : mixed
+Ignore Synthesis Constraint File : NO
+
+---- Target Parameters
+Output File Name : "Keyboard_Controller"
+Output Format : NGC
+Target Device : xc3s200-5-ft256
+
+---- Source Options
+Top Module Name : Keyboard_Controller
+Automatic FSM Extraction : YES
+FSM Encoding Algorithm : Auto
+Safe Implementation : No
+FSM Style : LUT
+RAM Extraction : Yes
+RAM Style : Auto
+ROM Extraction : Yes
+Mux Style : Auto
+Decoder Extraction : YES
+Priority Encoder Extraction : Yes
+Shift Register Extraction : YES
+Logical Shifter Extraction : YES
+XOR Collapsing : YES
+ROM Style : Auto
+Mux Extraction : Yes
+Resource Sharing : YES
+Asynchronous To Synchronous : NO
+Multiplier Style : Auto
+Automatic Register Balancing : No
+
+---- Target Options
+Add IO Buffers : YES
+Global Maximum Fanout : 500
+Add Generic Clock Buffer(BUFG) : 8
+Register Duplication : YES
+Slice Packing : YES
+Optimize Instantiated Primitives : NO
+Use Clock Enable : Yes
+Use Synchronous Set : Yes
+Use Synchronous Reset : Yes
+Pack IO Registers into IOBs : Auto
+Equivalent register Removal : YES
+
+---- General Options
+Optimization Goal : Speed
+Optimization Effort : 1
+Keep Hierarchy : No
+Netlist Hierarchy : As_Optimized
+RTL Output : Yes
+Global Optimization : AllClockNets
+Read Cores : YES
+Write Timing Constraints : NO
+Cross Clock Analysis : NO
+Hierarchy Separator : /
+Bus Delimiter : <>
+Case Specifier : Maintain
+Slice Utilization Ratio : 100
+BRAM Utilization Ratio : 100
+Verilog 2001 : YES
+Auto BRAM Packing : NO
+Slice Utilization Ratio Delta : 5
+
+=========================================================================
+
+
+=========================================================================
+* HDL Compilation *
+=========================================================================
+Compiling vhdl file "/home/omar/Mano/Mano/SevenSegment.vhd" in Library work.
+Architecture behavioral of Entity sevensegment is up to date.
+Compiling vhdl file "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd" in Library work.
+Entity compiled.
+Entity (Architecture ) compiled.
+
+=========================================================================
+* Design Hierarchy Analysis *
+=========================================================================
+Analyzing hierarchy for entity in library (architecture ).
+
+Analyzing hierarchy for entity in library (architecture ).
+
+
+=========================================================================
+* HDL Analysis *
+=========================================================================
+Analyzing Entity in library (Architecture ).
+Entity analyzed. Unit generated.
+
+Analyzing Entity in library (Architecture ).
+Entity analyzed. Unit generated.
+
+
+=========================================================================
+* HDL Synthesis *
+=========================================================================
+
+Performing bidirectional port resolution...
+
+Synthesizing Unit .
+ Related source file is "/home/omar/Mano/Mano/SevenSegment.vhd".
+ Found 16x8-bit ROM for signal .
+ Found 1-of-4 decoder for signal .
+ Found 4-bit 4-to-1 multiplexer for signal .
+ Found 13-bit up counter for signal .
+ Summary:
+ inferred 1 ROM(s).
+ inferred 1 Counter(s).
+ inferred 4 Multiplexer(s).
+ inferred 1 Decoder(s).
+Unit synthesized.
+
+
+Synthesizing Unit .
+ Related source file is "/home/omar/MyOpenCores/Keyboard_Controller/Keyboard_Controller.vhd".
+WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+ Found 5-bit up counter for signal .
+ Found 21-bit register for signal >.
+ Found 8-bit register for signal .
+ Found 8-bit register for signal .
+ Found 8-bit up counter for signal .
+ Summary:
+ inferred 2 Counter(s).
+ inferred 37 D-type flip-flop(s).
+Unit synthesized.
+
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# ROMs : 1
+ 16x8-bit ROM : 1
+# Counters : 3
+ 13-bit up counter : 1
+ 5-bit up counter : 1
+ 8-bit up counter : 1
+# Registers : 23
+ 1-bit register : 21
+ 8-bit register : 2
+# Multiplexers : 1
+ 4-bit 4-to-1 multiplexer : 1
+# Decoders : 1
+ 1-of-4 decoder : 1
+
+=========================================================================
+
+=========================================================================
+* Advanced HDL Synthesis *
+=========================================================================
+
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# ROMs : 1
+ 16x8-bit ROM : 1
+# Counters : 3
+ 13-bit up counter : 1
+ 5-bit up counter : 1
+ 8-bit up counter : 1
+# Registers : 37
+ Flip-Flops : 37
+# Multiplexers : 1
+ 4-bit 4-to-1 multiplexer : 1
+# Decoders : 1
+ 1-of-4 decoder : 1
+
+=========================================================================
+
+=========================================================================
+* Low Level Synthesis *
+=========================================================================
+
+Optimizing unit ...
+
+Mapping all equations...
+Building and optimizing final netlist ...
+Found area constraint ratio of 100 (+ 5) on block Keyboard_Controller, actual ratio is 2.
+
+Final Macro Processing ...
+
+Processing Unit :
+ Found 3-bit shift register for signal .
+ Found 4-bit shift register for signal .
+Unit processed.
+
+=========================================================================
+Final Register Report
+
+Macro Statistics
+# Registers : 56
+ Flip-Flops : 56
+# Shift Registers : 2
+ 3-bit shift register : 1
+ 4-bit shift register : 1
+
+=========================================================================
+
+=========================================================================
+* Partition Report *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+* Final Report *
+=========================================================================
+Final Results
+RTL Top Level Output File Name : Keyboard_Controller.ngr
+Top Level Output File Name : Keyboard_Controller
+Output Format : NGC
+Optimization Goal : Speed
+Keep Hierarchy : No
+
+Design Statistics
+# IOs : 23
+
+Cell Usage :
+# BELS : 97
+# GND : 1
+# INV : 4
+# LUT1 : 19
+# LUT2 : 5
+# LUT2_D : 1
+# LUT3 : 10
+# LUT3_L : 1
+# LUT4 : 11
+# MUXCY : 19
+# MUXF5 : 4
+# VCC : 1
+# XORCY : 21
+# FlipFlops/Latches : 58
+# FD : 13
+# FD_1 : 16
+# FDE : 8
+# FDE_1 : 16
+# FDR : 5
+# Shift Registers : 2
+# SRL16_1 : 2
+# Clock Buffers : 2
+# BUFGP : 2
+# IO Buffers : 21
+# IBUF : 1
+# OBUF : 20
+=========================================================================
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 3s200ft256-5
+
+ Number of Slices: 40 out of 1920 2%
+ Number of Slice Flip Flops: 58 out of 3840 1%
+ Number of 4 input LUTs: 53 out of 3840 1%
+ Number used as logic: 51
+ Number used as Shift registers: 2
+ Number of IOs: 23
+ Number of bonded IOBs: 23 out of 173 13%
+ Number of GCLKs: 2 out of 8 25%
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+ No Partitions were found in this design.
+
+---------------------------
+
+
+=========================================================================
+TIMING REPORT
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+ FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+ GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+-----------------------------------+------------------------+-------+
+Clock Signal | Clock buffer(FF name) | Load |
+-----------------------------------+------------------------+-------+
+Clk | BUFGP | 47 |
+Clk2 | BUFGP | 13 |
+-----------------------------------+------------------------+-------+
+
+Asynchronous Control Signals Information:
+----------------------------------------
+No asynchronous control signals found in this design
+
+Timing Summary:
+---------------
+Speed Grade: -5
+
+ Minimum period: 5.006ns (Maximum Frequency: 199.770MHz)
+ Minimum input arrival time before clock: 1.778ns
+ Maximum output required time after clock: 9.978ns
+ Maximum combinational path delay: No path found
+
+Timing Detail:
+--------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'Clk'
+ Clock period: 5.006ns (frequency: 199.770MHz)
+ Total number of paths / destination ports: 229 / 75
+-------------------------------------------------------------------------
+Delay: 5.006ns (Levels of Logic = 2)
+ Source: Counter_1 (FF)
+ Destination: OutByte1_0 (FF)
+ Source Clock: Clk falling
+ Destination Clock: Clk falling
+
+ Data Path: Counter_1 to OutByte1_0
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ FDR:C->Q 5 0.626 1.078 Counter_1 (Counter_1)
+ LUT2_D:I0->O 2 0.479 0.768 OutByte1_cmp_eq0000_SW0 (N14)
+ LUT4:I3->O 16 0.479 1.051 OutByte1_cmp_eq0000_1 (OutByte1_cmp_eq00001)
+ FDE_1:CE 0.524 OutByte2_0
+ ----------------------------------------
+ Total 5.006ns (2.108ns logic, 2.898ns route)
+ (42.1% logic, 57.9% route)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'Clk2'
+ Clock period: 4.033ns (frequency: 247.964MHz)
+ Total number of paths / destination ports: 91 / 13
+-------------------------------------------------------------------------
+Delay: 4.033ns (Levels of Logic = 13)
+ Source: Inst_SevenSegment/Counter_1 (FF)
+ Destination: Inst_SevenSegment/Counter_12 (FF)
+ Source Clock: Clk2 rising
+ Destination Clock: Clk2 rising
+
+ Data Path: Inst_SevenSegment/Counter_1 to Inst_SevenSegment/Counter_12
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ FD:C->Q 1 0.626 0.976 Inst_SevenSegment/Counter_1 (Inst_SevenSegment/Counter_1)
+ LUT1:I0->O 1 0.479 0.000 Inst_SevenSegment/Mcount_Counter_cy<1>_rt (Inst_SevenSegment/Mcount_Counter_cy<1>_rt)
+ MUXCY:S->O 1 0.435 0.000 Inst_SevenSegment/Mcount_Counter_cy<1> (Inst_SevenSegment/Mcount_Counter_cy<1>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<2> (Inst_SevenSegment/Mcount_Counter_cy<2>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<3> (Inst_SevenSegment/Mcount_Counter_cy<3>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<4> (Inst_SevenSegment/Mcount_Counter_cy<4>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<5> (Inst_SevenSegment/Mcount_Counter_cy<5>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<6> (Inst_SevenSegment/Mcount_Counter_cy<6>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<7> (Inst_SevenSegment/Mcount_Counter_cy<7>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<8> (Inst_SevenSegment/Mcount_Counter_cy<8>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<9> (Inst_SevenSegment/Mcount_Counter_cy<9>)
+ MUXCY:CI->O 1 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<10> (Inst_SevenSegment/Mcount_Counter_cy<10>)
+ MUXCY:CI->O 0 0.056 0.000 Inst_SevenSegment/Mcount_Counter_cy<11> (Inst_SevenSegment/Mcount_Counter_cy<11>)
+ XORCY:CI->O 1 0.786 0.000 Inst_SevenSegment/Mcount_Counter_xor<12> (Result<12>)
+ FD:D 0.176 Inst_SevenSegment/Counter_12
+ ----------------------------------------
+ Total 4.033ns (3.057ns logic, 0.976ns route)
+ (75.8% logic, 24.2% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
+ Total number of paths / destination ports: 1 / 1
+-------------------------------------------------------------------------
+Offset: 1.778ns (Levels of Logic = 1)
+ Source: DataIn (PAD)
+ Destination: Mshreg_data_2 (FF)
+ Destination Clock: Clk falling
+
+ Data Path: DataIn to Mshreg_data_2
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ IBUF:I->O 1 0.715 0.681 DataIn_IBUF (DataIn_IBUF)
+ SRL16_1:D 0.382 Mshreg_data_2
+ ----------------------------------------
+ Total 1.778ns (1.097ns logic, 0.681ns route)
+ (61.7% logic, 38.3% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk2'
+ Total number of paths / destination ports: 92 / 11
+-------------------------------------------------------------------------
+Offset: 9.978ns (Levels of Logic = 4)
+ Source: Inst_SevenSegment/Counter_11 (FF)
+ Destination: Segments<6> (PAD)
+ Source Clock: Clk2 rising
+
+ Data Path: Inst_SevenSegment/Counter_11 to Segments<6>
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ FD:C->Q 13 0.626 1.290 Inst_SevenSegment/Counter_11 (Inst_SevenSegment/Counter_11)
+ LUT3:I0->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_3 (Inst_SevenSegment/Mmux_Chosen_3)
+ MUXF5:I1->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5 (Inst_SevenSegment/Chosen<0>)
+ LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments111 (Segments_1_OBUF)
+ OBUF:I->O 4.909 Segments_1_OBUF (Segments<1>)
+ ----------------------------------------
+ Total 9.978ns (6.807ns logic, 3.171ns route)
+ (68.2% logic, 31.8% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
+ Total number of paths / destination ports: 120 / 15
+-------------------------------------------------------------------------
+Offset: 9.540ns (Levels of Logic = 4)
+ Source: OutByte1_5 (FF)
+ Destination: Segments<6> (PAD)
+ Source Clock: Clk falling
+
+ Data Path: OutByte1_5 to Segments<6>
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ FDE_1:C->Q 1 0.626 0.851 OutByte1_5 (OutByte1_5)
+ LUT3:I1->O 1 0.479 0.000 Inst_SevenSegment/Mmux_Chosen_41 (Inst_SevenSegment/Mmux_Chosen_41)
+ MUXF5:I0->O 7 0.314 1.201 Inst_SevenSegment/Mmux_Chosen_2_f5_0 (Inst_SevenSegment/Chosen<1>)
+ LUT4:I0->O 1 0.479 0.681 Inst_SevenSegment/Mrom_Segments21 (Segments_2_OBUF)
+ OBUF:I->O 4.909 Segments_2_OBUF (Segments<2>)
+ ----------------------------------------
+ Total 9.540ns (6.807ns logic, 2.733ns route)
+ (71.4% logic, 28.6% route)
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 5.00 secs
+Total CPU time to Xst completion: 4.77 secs
+
+-->
+
+
+Total memory usage is 339112 kilobytes
+
+Number of errors : 0 ( 0 filtered)
+Number of warnings : 1 ( 0 filtered)
+Number of infos : 0 ( 0 filtered)
+
Index: ps2_keyboard_interface/Keyboard_Controller.xst
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller.xst (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller.xst (revision 2)
@@ -0,0 +1,56 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn Keyboard_Controller.prj
+-ifmt mixed
+-ofn Keyboard_Controller
+-ofmt NGC
+-p xc3s200-5-ft256
+-top Keyboard_Controller
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: ps2_keyboard_interface/Keyboard_Controller_map.ngm
===================================================================
--- ps2_keyboard_interface/Keyboard_Controller_map.ngm (nonexistent)
+++ ps2_keyboard_interface/Keyboard_Controller_map.ngm (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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