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URL https://opencores.org/ocsvn/wb2axi4/wb2axi4/trunk

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/wb2axi4/trunk/rtl/sync_single_ff.sv
0,0 → 1,28
module sync_single_ff (
// *************************** Ports ********************************
DIN ,
DOUT ,
CLK ,
RESET_N
);
// ************************ Parameters ******************************
parameter DATA_W = 32 ;
 
// ********************** Inputs/Outputs ****************************
input wire [DATA_W-1:0] DIN ;
output reg [DATA_W-1:0] DOUT ;
input CLK ;
input RESET_N ;
 
// ************************** Regs ********************************
always @(posedge CLK or negedge RESET_N)
begin
if (!RESET_N) {DOUT } <= 0;
else {DOUT} <= { DIN};
end
 
endmodule // sync_single_ff
//*****************************************************************************
 
/wb2axi4/trunk/rtl/axi_ingress.sv
0,0 → 1,112
//Author : Alex Zhang (cgzhangwei@gmail.com)
//Date : 03-11-2015
//Basic : How to storage the AXI info and data into sram or fifo.
`include "wb2axi_parameters.vh"
module axi_ingress (
axi_clk,
reset_n,
AXI_IF,
fifo_full,
fifo_addr_info,
fifo_data_info,
fifo_addr_wr,
fifo_data_wr
);
parameter AXI_WID_W = 5;
parameter AXI_MAX_RESP_W = 3;
input axi_clk;
input reset_n;
axi_if.target AXI_IF;
output fifo_full;
output [FIFO_AW-1:0] fifo_addr_info;
output [FIFO_DW-1:0] fifo_data_info;
output reg fifo_addr_wr;
output reg fifo_data_wr;
localparam ST_W = 2;
localparam ST_IDLE = 2'b00;
localparam ST_WDATA = 2'b01;
localparam ST_BRESP = 2'b10;
localparam AXI_MAX_RESP_VAL = {AXI_MAX_RESP_W{1'b1}};
 
wire input_addr_event;
wire input_data_event;
wire inc_bresp;
wire dec_bresp;
wire bresp_cnt_max;
 
 
reg [ST_W-1:0] state;
reg [ST_W-1:0] next_state;
reg [AXI_MAX_RESP_W-1:0] bresp_pending_cnt; //responses pending to generate
reg [AXI_WID_W-1:0] last_wid;
reg [FIFO_AW-1:0] fifo_addr_in;
reg [FIFO_DW-1:0] fifo_data_in;
 
assign input_addr_event = AXI_IF.AWVALID & AXI_IF.AWREADY;
assign input_data_event = AXI_FI.WVALID & AXI_IF.WREADY;
assign inc_bresp = AXI_IF.WLAST & input_data_event;
assign dec_bresp = AXI_IF.BREADY & AXI_IF.BVALID;
assign bresp_cnt_max = (bresp_pending_cnt == AXI_MAX_RESP_VAL);
 
always_comb begin
next_state = state;
fifo_addr_wr = 0;
case (state)
ST_IDLE : begin
if(input_addr_event) begin
fifo_addr_wr = 1;
fifo_addr_in = {AXI_IF.AWID, AXI_IF.AWADDR, AXI_IF.AWLEN, AXI_IF.AWSIZE, AXI_IF.AWBURST, AXI_IF.AWLOCK, AXI_IF.AWCACHE, AXI_IF.AWPROT, 1'b1}; //Wr address info
next_state = ST_WDATA;
end else begin
fifo_addr_wr = 0;
next_state = ST_IDLE;
end
end
ST_WDATA: begin
if (input_data_event) begin
fifo_data_wr = 1;
fifo_data_in = {AXI_IF.WID, AXI_IF.WDATA, AXI_IF.WSTRB, AXI_IF.WLAST, AXI_IF.WVALID};
next_state = ST_BRESP;
end else begin
fifo_data_wr = 0;
next_state = ST_WDATA;
end
end
ST_BRESP : begin
next_state = ST_IDLE;
end
 
endcase
end
 
always @(posedge axi_clk or negedge reset_n) begin
if (~reset_n) begin
state <= ST_IDLE;
bresp_pending_cnt <= 0;
last_wid <= 0;
end else begin
state <= next_state;
bresp_pending_cnt <= ( inc_bresp & !dec_bresp) ? bresp_pending_cnt +1 :
(!inc_bresp & dec_bresp) ? bresp_pending_cnt -1 : bresp_pending_cnt ;
last_wid <= input_data_event ? AXI_IF.WID : last_wid;
 
end
end
 
assign AXI_IF.BRESP = 2'b00; //Response is always OK.
assign AXI_IF.BID = last_wid;
assign AXI_IF.BVALID= (state == ST_BRESP) && bresp_pending_cnt !=0;
assign AXI_IF.ARREADY = 0;
assign AXI_IF.RDATA = 0;
assign AXI_IF.RRESP = 0;
assign AXI_IF.RLAST = 0;
assign AXI_IF.RVALID = 0;
assign AIX_IF.AWREADY = (state ==ST_IDLE || state==ST_WDATA) & ~fifo_full & ~bresp_cnt_max;
assign AXI_IF.WREADY = ~fifo_full & ~bresp_cnt_max;
 
assign fifo_addr_info = fifo_addr_in;
assign fifo_data_info = fifo_data_in;
 
endmodule
/wb2axi4/trunk/rtl/axi2wb.sv
0,0 → 1,161
//Author : Alex Zhang (cgzhangwei@gmail.com)
//Date : 03-11-2015
module axi2wb (
axi_clk,
wb_clk,
axi_resetn,
wb_resetn,
ENABLE,
AXI_IF,
WB_TX_IF
);
parameter AXI_WID_W = 4;
parameter AXI_ADDR_W = 32;
parameter AXI_DATA_W = 32;
parameter AXI_PROT_W = 3;
parameter AXI_STB_W = 4;
parameter AXI_LEN_W = 4;
parameter AXI_ASIZE_W = 3;
parameter AXI_ABURST_W = 2;
parameter AXI_ALOCK_W = 2;
parameter AXI_ACACHE_W = 4;
parameter AXI_RESP_W = 2;
 
parameter FIFO_DEPTH_W = 10;
parameter FIFO_W = 64;
 
parameter WB_ADR_W = 32;
parameter WB_DAT_W = 32;
parameter WB_TGA_W = 8;
parameter WB_TGD_W = 8;
parameter WB_TGC_W = 4;
parameter WB_SEL_W = 4;
parameter WB_CTI_W = 3;
parameter WB_BTE_W = 2;
 
parameter AXI_MAX_RESP_W = 3;
parameter SRAM_UNUSED_ADDR_W= 4;
 
input wire axi_clk;
input wire wb_clk;
input wire axi_resetn;
input wire wb_resetn;
axi_if.target AXI_IF;
wb_if.master WB_TX_IF;
sram_if.initiator SRAM_ADR_IF;
sram_if.initiator SRAM_DAT_IF;
 
wire sync_ENABLE_axi;
wire sync_ENABLE_wb;
sync_doble_ff #(.DATA_W(1)) I_SYNC_ENABLE_AXI (
.CLK ( AXI_CLK ),
.RESET_N ( AXI_RESET_N ),
.DIN ( ENABLE ),
.DOUT ( sync_ENABLE_axi )
);
sync_doble_ff #(.DATA_W(1)) I_SYNC_ENABLE_WB (
.CLK ( MAC_CLK ),
.RESET_N ( MAC_RESET_N ),
.DIN ( ENABLE ),
.DOUT ( sync_ENABLE_wb )
);
 
axi_ingress #(
.AXI_WID_W ( AXI_WID_W ),
.AXI_ADDR_W ( AXI_ADDR_W ),
.AXI_DATA_W ( AXI_DATA_W ),
.AXI_PROT_W ( AXI_PROT_W ),
.AXI_STB_W ( AXI_STB_W ),
.AXI_LEN_W ( AXI_LEN_W ),
.AXI_ASIZE_W ( AXI_ASIZE_W ),
.AXI_ABURST_W ( AXI_ABURST_W ),
.AXI_ALOCK_W ( AXI_ALOCK_W ),
.AXI_ACACHE_W ( AXI_ACACHE_W ),
.AXI_RESP_W ( AXI_RESP_W ),
.AXI_MAX_RESP_W ( AXI_MAX_RESP_W )
) I_AXI_INGRESS (
.axi_clk ( axi_clk ),
.reset_n ( axi_resetn ),
.AXI_IF ( AXI_IF ),
.fifo_full ( fifo_full ),
.fifo_addr_info ( fifo_addr_info),
.fifo_data_info ( fifo_data_info),
.fifo_addr_wr ( fifo_addr_wr ),
.fifo_data_wr ( fifo_data_wr )
);
 
assign fifo_full = fifo_adr_full | fifo_dat_full;
 
async_fifo #(
.FIFO_DEPTH_W (FIFO_ADDR_DEPTH_W),
.FIFO_W (FIFO_ADDR_W),
.SRAM_UNUSED_ADDR_W(FA_SRAM_UNUSED_ADDR_W)
) I_FIFO_ADR (
.wrclk_RESET_N ( axi_resetn ),
.rdclk_RESET_N ( wb_resetn ),
.wr_en ( sync_ENABLE_axi ),
.rd_en ( sync_ENABLE_wb ),
.fifo_wr_clk ( axi_clk ),
.fifo_rd_clk ( wb_clk ),
.fifo_wr ( fifo_adr_wr ),
.fifo_rd ( fifo_adr_rd ),
.fifo_wdata ( fifo_adr_wdata ),
.fifo_rdata ( fifo_adr_rdata ),
.fifo_empty ( fifo_adr_empty ),
.fifo_full ( fifo_adr_full ),
);
assign fifo_adr_wr = fifo_addr_wr;
assign fifo_adr_wdata = fifo_addr_info;
async_fifo #(
.FIFO_DEPTH_W (FIFO_DATA_DEPTH_W),
.FIFO_W (FIFO_DATA_W),
.SRAM_UNUSED_ADDR_W(FD_SRAM_UNUSED_ADDR_W)
) I_FIFO_DAT (
.wrclk_RESET_N ( axi_resetn ),
.rdclk_RESET_N ( wb_resetn ),
.wr_en ( sync_ENABLE_axi ),
.rd_en ( sync_ENABLE_wb ),
.fifo_wr_clk ( axi_clk ),
.fifo_rd_clk ( wb_clk ),
.fifo_wr ( fifo_dat_wr ),
.fifo_rd ( fifo_dat_rd ),
.fifo_wdata ( fifo_dat_wdata ),
.fifo_rdata ( fifo_dat_rdata ),
.fifo_empty ( fifo_dat_empty ),
.fifo_full ( fifo_dat_full ),
);
assign fifo_dat_wr = fifo_data_wr;
assign fifo_dat_wdata = fifo_data_info;
wb_egress #(
.WB_ADR_W (WB_ADR_W )
.WB_DAT_W (WB_DAT_W )
.WB_TGA_W (WB_TGA_W )
.WB_TGD_W (WB_TGD_W )
.WB_TGC_W (WB_TGC_W )
.WB_SEL_W (WB_SEL_W )
.WB_CTI_W (WB_CTI_W )
.WB_BTE_W (WB_BTE_W )
.AXI_ID_W (AXI_ID_W )
.AXI_ADDR_W (AXI_ADDR_W )
.AXI_LEN_W (AXI_LEN_W )
.AXI_SIZE_W (AXI_SIZE_W )
.AXI_BURST_W(AXI_BURST_W)
.AXI_LOCK_W (AXI_LOCK_W )
.AXI_CACHE_W(AXI_CACHE_W)
.AXI_PROT_W (AXI_PROT_W )
.AXI_DATA_W (AXI_DATA_W )
.AXI_STRB_W (AXI_STRB_W )
) I_WB_EGRESS(
.wb_clk ( wb_clk ),
.wb_resetn ( wb_resetn ),
.ENABLE ( sync_ENABLE_wb ),
.WB_TX_IF ( WB_TX_IF ),
.fifo_adr_rdata ( fifo_adr_rdata ),
.fifo_adr_rd ( fifo_adr_rd ),
.fifo_adr_empty ( fifo_adr_empty ),
.fifo_dat_rdata ( fifo_dat_rdata ),
.fifo_dat_rd ( fifo_dat_rd ),
.fifo_dat_empty ( fifo_dat_empty ),
);
 
endmodule
/wb2axi4/trunk/rtl/bin2gray.sv
0,0 → 1,16
module bin2gray (
// *************************** Ports ********************************
bin,
gray
);
// ************************ Parameters ******************************
parameter DATA_W = 32 ;
// ********************** Inputs/Outputs ****************************
input wire [DATA_W-1:0] bin ;
output wire [DATA_W-1:0] gray ;
 
assign gray = {1'b0, bin[DATA_W-1:1] } ^ bin;
 
endmodule // bin2gray
/wb2axi4/trunk/rtl/async_fifo.sv
0,0 → 1,157
module async_fifo
// *************************** Ports ********************************
(
rdclk_RESET_N ,
wrclk_RESET_N ,
fifo_rd_clk ,
fifo_wr_clk ,
rd_en ,
wr_en ,
fifo_rd ,
fifo_wr ,
fifo_wdata ,
fifo_rdata ,
fifo_empty ,
fifo_full ,
fifo_level ,
SRAM_IF
);
// ************************ Parameters ******************************
parameter FIFO_DEPTH_W = 10 ;
parameter FIFO_W = 64 ;
 
parameter SRAM_DATA_W = 64 ;
parameter SRAM_ADDR_W = 14 ;
 
parameter SRAM_UNUSED_ADDR_W = 4 ;
// ********************* Local Parameters **************************
// ********************** Inputs/Outputs ****************************
input wire rdclk_RESET_N ;
input wire wrclk_RESET_N ;
input wire fifo_rd_clk ;
input wire fifo_wr_clk ;
input wire rd_en ;
input wire wr_en ;
input wire fifo_rd ;
input wire fifo_wr ;
input wire [FIFO_W-1:0] fifo_wdata ;
output wire [FIFO_W-1:0] fifo_rdata ;
output reg fifo_empty ;
output reg fifo_full ;
output reg [FIFO_DEPTH_W:0] fifo_level ;
sram_if.initiator SRAM_IF ;
// ************************** Wires *******************************
wire next_fifo_full;
wire next_fifo_empty;
wire [FIFO_DEPTH_W:0] next_fifo_level;
wire [FIFO_DEPTH_W:0] next_wr_ptr;
wire [FIFO_DEPTH_W:0] next_rd_ptr;
wire [FIFO_DEPTH_W:0] next_gray_wr_ptr;
wire [FIFO_DEPTH_W:0] next_gray_rd_ptr;
wire [FIFO_DEPTH_W:0] sync_wr_ptr_rdclk;
wire [FIFO_DEPTH_W:0] sync_gray_wr_ptr_rdclk;
wire [FIFO_DEPTH_W:0] sync_gray_rd_ptr_wrclk;
 
// ************************** Regs *******************************
reg [FIFO_DEPTH_W:0] wr_ptr;
reg [FIFO_DEPTH_W:0] rd_ptr;
reg [FIFO_DEPTH_W:0] gray_wr_ptr;
reg [FIFO_DEPTH_W:0] gray_rd_ptr;
 
// ******************** SRAM_IF control *****************************
assign SRAM_IF.rd_l = ~fifo_rd;
assign SRAM_IF.wr_l = ~(fifo_wr & ~fifo_full);
assign SRAM_IF.rd_address = { {SRAM_UNUSED_ADDR_W{1'b0}}, rd_ptr[FIFO_DEPTH_W-1:0] }; // rd_ptr in positions (64b words each)
assign SRAM_IF.wr_address = { {SRAM_UNUSED_ADDR_W{1'b0}}, wr_ptr[FIFO_DEPTH_W-1:0] }; // wr_ptr in positions (64b words each)
assign SRAM_IF.wdata = fifo_wdata;
assign fifo_rdata = SRAM_IF.rdata;
// ********************* Write pointer *****************************
always_ff @(posedge fifo_wr_clk or negedge wrclk_RESET_N)
begin
if (!wrclk_RESET_N) begin
wr_ptr <= 0;
gray_wr_ptr <= 0;
end
else if (wr_en) begin
wr_ptr <= next_wr_ptr;
gray_wr_ptr <= next_gray_wr_ptr;
end
end
 
assign next_wr_ptr = wr_ptr + (fifo_wr & ~fifo_full);
bin2gray #(.DATA_W(FIFO_DEPTH_W+1)) I_BIN2GRAY (
.bin ( next_wr_ptr ),
.gray ( next_gray_wr_ptr )
);
 
// ******************* Read pointer resync *************************
sync_doble_ff #(.DATA_W(FIFO_DEPTH_W+1)) I_SYNC_RD (
.CLK ( fifo_wr_clk ),
.RESET_N ( wrclk_RESET_N ),
.DIN ( gray_rd_ptr ),
.DOUT ( sync_gray_rd_ptr_wrclk )
);
// *********************** FIFO full *******************************
assign next_fifo_full = (next_gray_wr_ptr == { ~sync_gray_rd_ptr_wrclk[FIFO_DEPTH_W:FIFO_DEPTH_W-1], sync_gray_rd_ptr_wrclk[FIFO_DEPTH_W-2:0] });
always_ff @(posedge fifo_wr_clk or negedge wrclk_RESET_N)
begin
if (!wrclk_RESET_N) fifo_full <= 0;
else if (wr_en) fifo_full <= next_fifo_full;
end
// ********************** Read pointer *****************************
always_ff @(posedge fifo_rd_clk or negedge rdclk_RESET_N)
begin
if (!rdclk_RESET_N) begin
rd_ptr <= 0;
gray_rd_ptr <= 0;
end
else if (rd_en) begin
rd_ptr <= next_rd_ptr;
gray_rd_ptr <= next_gray_rd_ptr;
end
end
 
assign next_rd_ptr = rd_ptr + (fifo_rd & ~fifo_empty);
bin2gray #(.DATA_W(FIFO_DEPTH_W+1)) I_BIN2GRAY_RD (
.bin ( next_rd_ptr ),
.gray ( next_gray_rd_ptr )
);
 
// ***************xt_**** Write pointer resync *************************
sync_doble_ff #(.DATA_W(FIFO_DEPTH_W+1)) I_SYNC_WR (
.CLK ( fifo_rd_clk ),
.RESET_N ( rdclk_RESET_N ),
.DIN ( gray_wr_ptr ),
.DOUT ( sync_gray_wr_ptr_rdclk )
);
// ******************** FIFO empty, level ***************************
assign next_fifo_empty = (next_gray_rd_ptr == sync_gray_wr_ptr_rdclk );
gray2bin #(.DATA_W(FIFO_DEPTH_W+1)) I_GRAY2BIN_WR (
.gray ( sync_gray_wr_ptr_rdclk ),
.bin ( sync_wr_ptr_rdclk )
);
assign next_fifo_level = sync_wr_ptr_rdclk - next_rd_ptr;
always_ff @(posedge fifo_rd_clk or negedge rdclk_RESET_N)
begin
if (!rdclk_RESET_N) begin
fifo_empty <= 1;
fifo_level <= 0;
end
else if (rd_en) begin
fifo_empty <= next_fifo_empty;
fifo_level <= next_fifo_level;
end
end
endmodule
/wb2axi4/trunk/rtl/wb_egress.sv
0,0 → 1,300
//Author : Alex Zhang (cgzhangwei@gmail.com)
//Date : 03-11-2015
//Description: Now support the classic WB protocol.
// Change the ACK_I meaing to improve the efficiency.
//TODO : 4 beat wrapper or 8 beat wrapper is not supported yet.
 
module wb_egress(
wb_clk,
wb_resetn,
ENABLE,
WB_TX_IF,
fifo_adr_rdata,
fifo_adr_rd,
fifo_adr_empty,
fifo_dat_rdata,
fifo_dat_rd,
fifo_dat_empty,
);
 
parameter WB_ADR_W = 32;
parameter WB_DAT_W = 32;
parameter WB_TGA_W = 8;
parameter WB_TGD_W = 8;
parameter WB_TGC_W = 4;
parameter WB_SEL_W = 4;
parameter WB_CTI_W = 3;
parameter WB_BTE_W = 2;
parameter AXI_ID_W = 3;
parameter AXI_ADDR_W = 32;
parameter AXI_LEN_W = 4;
parameter AXI_SIZE_W = 3;
parameter AXI_BURST_W = 2;
parameter AXI_LOCK_W = 2;
parameter AXI_CACHE_W = 4;
parameter AXI_PROT_W = 3;
parameter AXI_DATA_W = 32;
parameter AXI_STRB_W = 4;
parameter FIFO_ADR_W = AXI_ID_W + AXI_ADDR_W + AXI_LEN_W + AXI_SIZE_W + AXI_BURST_W + AXI_LOCK_W + AXI_CACHE_W + AXI_PROT_W +1 ;
parameter FIFO_DAT_W = AXI_ID_W + AXI_DATA_W + AXI_STRB_W + 2;
parameter ST_W = 2 ;
parameter ST_IDLE = 2'b00,
ST_READ_ADDR = 2'b01,
ST_WAIT_DATA = 2'b10,
ST_READ_DATA = 2'b11;
parameter WB_W = 2;
parameter WB_IDLE = 2'b00,
WB_FIRST_DATA = 2'b01,
WB_NEXT_DATA = 2'b10;
 
input wire wb_clk;
input wire wb_resetn;
input wire ENABLE;
wb_if.master WB_TX_IF;
input wire [FIFO_ADR_W-1:0] fifo_adr_rdata;
output wire fifo_adr_rd;
input wire fifo_adr_empty;
input wire [FIFO_DAT_W-1:0] fifo_dat_rdata;
output wire fifo_dat_rd;
input wire fifo_dat_empty;
 
 
reg [ST_W-1:0] state;
reg [ST_W-1:0] next_state;
reg inc_dat_ptr;
reg [4:0] data_count;
wire allow_adr_rd;
wire fifo_adr_rd;
wire fifo_adr_rd_q;
wire fifo_dat_rd;
reg [AXI_ID_W -1:0] axi_id ;
reg [AXI_ADDR_W -1:0] axi_addr ;
reg [AXI_LEN_W -1:0] axi_len ;
reg [AXI_SIZE_W -1:0] axi_size ;
reg [AXI_BURST_W-1:0] axi_burst ;
reg [AXI_LOCK_W -1:0] axi_lock ;
reg [AXI_CACHE_W-1:0] axi_cache ;
reg [AXI_PROT_W -1:0] axi_prot ;
reg wr_req ;
reg [AXI_ID_W -1:0] axi_wid ;
reg [AXI_DATA_W -1:0] axi_wdata ;
reg [AXI_STRB_W -1:0] axi_wstrb ;
reg axi_wlast ;
reg axi_wvalid;
reg wb_we_o ;
reg [WB_ADR_W-1:0] wb_adr_o;
reg [WB_TGA_W-1:0] wb_tga_o;
reg [WB_ADR_W-1:0] wb_adr_tmp;
reg [WB_BTE_W-1:0] wb_bte_o;
reg wb_cyc_o;
reg [WB_TGC_W-1:0] wb_tgc_o;
reg [WB_CTI_W-1:0] wb_cti_o;
reg [WB_STB_W-1:0] wb_stb_o;
reg [WB_DAT_W-1:0] wb_dat_o;
reg [WB_TGD_W-1:0] wb_tgd_o;
reg [WB_SEL_W-1:0] wb_sel_o;
 
 
assign allow_adr_rd = wb_cs == WB_IDLE;
always_comb begin
next_state = state;
inc_dat_ptr = 0; //int- internal
case (state)
ST_IDLE : begin
if (!fifo_adr_empty&allow_adr_rd) begin
next_state = ST_READ_ADDR;
end else begin
next_state = ST_IDLE;
end
end
ST_READ_ADDR : begin
next_state = ST_WAIT_DATA;
end
ST_WAIT_DATA : begin
if (WB_TX_IF.ACK_I & !fifo_dat_empty) begin
next_state = ST_READ_DATA;
end else begin
next_state = ST_WAIT_DATA;
end
end
ST_READ_DATA : begin
if (data_count>0 & WB_TX_IF.ACK_I) begin
next_state = ST_READ_DATA;
inc_dat_ptr = 1;
end else if (data_count>0) begin
next_state = ST_WAIT_DATA;
inc_dat_ptr = 0;
end
next_state = ST_IDLE;
inc_dat_ptr = 0;
end
end
endcase
end
 
assign fifo_adr_rd = state == ST_READ_ADDR;
assign fifo_dat_rd = inc_dat_ptr;
 
sync_single_ff #(.DATA_W(1)) adr_rd_ff (
.DIN ( fifo_adr_rd ),
.DOUT ( fifo_adr_rd_q ),
.CLK ( wb_clk ),
.RESET_N( wb_resetn )
)
always @(posedge wb_clk or negedge wb_resetn)
if (~wb_resetn) begin
state <= ST_IDLE;
data_count <= 0 ;
end else begin
state <= next_state;
data_count <= state==ST_READ_ADDR ? axi_len + 1 :
state==ST_READ_DATA ? data_count -1 : data_count ;
end
 
//AXI3 only accept the alignment input of 4Byte-aligned data.i.e. awaddr[1:0]==0
 
 
always @(posedge wb_clk or negedge wb_resetn)
if (~wb_resetn) begin
axi_id <= 0;
axi_addr <= 0;
axi_len <= 0;
axi_size <= 0;
axi_burst <= 0;
axi_lock <= 0;
axi_cache <= 0;
axi_prot <= 0;
wr_req <= 0;
axi_wid <= 0;
axi_wdata <= 0;
axi_wstrb <= 0;
axi_wlast <= 0;
axi_wvalid <= 0;
end else begin
if ( fifo_adr_rd )
{axi_id, axi_addr, axi_len, axi_size, axi_burst, axi_lock, axi_cache, axi_prot, wr_req}<= fifo_adr_rdata;
if ( fifo_dat_rd )
{axi_wid, axi_wdata, axi_wstrb, axi_wlast, axi_wvalid}<= fifo_dat_rdata;
end
 
always @(posedge wb_clk or negedge wb_resetn) begin
if (~wb_resetn) begin
wb_cs <= WB_IDLE;
end else begin
wb_cs <= wb_ns;
end
end
///Wishbone master output
always @(*) begin
wb_ns = wb_cs;
case (wb_cs)
WB_IDLE : begin
if (fifo_data_rd) begin
wb_ns = WB_FIRST_DATA;
end else begin
wb_ns = WB_IDLE;
end
end
WB_FIRST_DATA : begin
if (axi_wlast & WB_TX_IF.ACK_I)
wb_ns = WB_IDLE;
else if (~axi_wlast & WB_TX_IF.ACK_I)
wb_ns = WB_NEXT_DATA;
else
wb_ns = WB_FIRST_DATA;
end
WB_NEXT_DATA : begin
if (axi_wlast & WB_TX_IF.ACK_I)
wb_ns = WB_IDLE;
else
wb_ns = WB_NEXT_DATA;
end
endcase
end
 
 
always @(posedge wb_clk or negedge wb_resetn) begin
if (~wb_resetn) begin
wb_we_o <= 0;
wb_adr_o <= 0;
wb_tga_o <= 0;
 
wb_adr_tmp <= 0;
wb_bte_o <= 0;
wb_cyc_o <= 0;
wb_tgc_o <= 0;
wb_cti_o <= 0;
wb_stb_o <= 0;
 
wb_dat_o <= 0;
wb_tgd_o <= 0;
wb_sel_o <= 0;
end else begin
case (wb_cs)
WB_IDLE : begin
wb_we_o <= 0;
wb_adr_o <= 0;
wb_tga_o <= 0;
 
wb_bte_o <= 0;
wb_cyc_o <= 0;
wb_tgc_o <= 0;
wb_cti_o <= 0;
wb_stb_o <= 0;
 
wb_dat_o <= 0;
wb_tgd_o <= 0;
wb_sel_o <= 0;
end
WB_FIRST_DATA : begin
wb_we_o <= wr_req;
wb_adr_o <= axi_addr;
wb_adr_tmp <= axi_addr;
wb_len_tmp <= axi_len-1;
wb_tga_o <= axi_id;
wb_bte_o <= 2'b00; //burst
wb_cyc_o <= 1;
wb_tgc_o <= {axi_prot, axi_cache, axi_lock, axi_len};
wb_cti_o <= axi_wlast ? 3'b111 : 3'b000;
wb_stb_o <= 1;
 
wb_dat_o <= axi_wdata;
wb_tgd_o <= axi_wid;
wb_sel_o <= axi_wstrb;
end
WB_NEXT_DATA : begin
wb_we_o <= wr_req;
wb_adr_o <= wb_adr_tmp + 4'b100;
wb_adr_tmp <= wb_adr_tmp +4'b100;
wb_len_tmp <= wb_len_tmp -1 ;
wb_tga_o <= axi_id;
wb_bte_o <= 2'b00; //burst
wb_cyc_o <= 1;
wb_tgc_o <= {axi_prot, axi_cache, axi_lock, wb_len_tmp };
wb_cti_o <= axi_wlast ? 3'b111 : 3'b000;
wb_stb_o <= 1;
 
wb_dat_o <= axi_wdata;
wb_tgd_o <= axi_wid;
wb_sel_o <= axi_wstrb;
end
endcase
end
end
 
assign WB_TX_IF.ADR_O = wb_adr_o;
assign WB_TX_IF.WE_O = wb_we_o;
assign WB_TX_IF.TGA_O = wb_tga_o;
assign WB_TX_IF.BTE_O = wb_bte_o;
assign WB_TX_IF.CYC_O = wb_cyc_o;
assign WB_TX_IF.TGC_O = wb_tgc_o;
assign WB_TX_IF.CTI_O = wb_cti_o;
assign WB_TX_IF.STB_O = wb_stb_o;
assign WB_TX_IF.DAT_O = wb_dat_o;
assign WB_TX_IF.TGD_O = wb_tgd_o;
assign WB_TX_IF.SEL_O = wb_sel_o;
 
endmodule
/wb2axi4/trunk/rtl/sync_double_ff.sv
0,0 → 1,30
module sync_doble_ff (
// *************************** Ports ********************************
DIN ,
DOUT ,
CLK ,
RESET_N
);
// ************************ Parameters ******************************
parameter DATA_W = 32 ;
 
// ********************** Inputs/Outputs ****************************
input wire [DATA_W-1:0] DIN ;
output reg [DATA_W-1:0] DOUT ;
input CLK ;
input RESET_N ;
 
// ************************** Regs ********************************
reg [DATA_W-1:0] dreg1 ;
always @(posedge CLK or negedge RESET_N)
begin
if (!RESET_N) {DOUT, dreg1} <= 0;
else {DOUT, dreg1} <= {dreg1, DIN};
end
 
endmodule // sync_doble_ff
//*****************************************************************************
 
/wb2axi4/trunk/rtl/ifaces/wishbone_if.sv
0,0 → 1,89
//Author : Alex Zhang (cgzhangwei@gmail.com)
//Date : March.05.2015
//Description: Wishbone B3 protocol interface
// TGC : {AWPROT,AWCACHE, AWLOCK} | {ARPROT, ARCACHE,ARLOCK}
// TGD : WID,
// TGA : AWID| ARID,
interface wishbone_if #(
WB_ADR_WIDTH = 32,
WB_BTE_WIDTH = 2 ,
WB_CIT_WIDTH = 3 ,
WB_DAT_WIDTH = 32,
WB_TGA_WIDTH = 8,
WB_TGD_WIDTH = 8,
WB_TGC_WIDTH = 4,
WB_SEL_WIDTH = 4
 
);
logic [WB_DAT_WIDTH -1 : 0] DAT_I;
logic [WB_DAT_WIDTH -1 : 0] DAT_O;
logic [WB_TGD_WIDTH -1 : 0] TGD_I;
logic [WB_TGD_WIDTH -1 : 0] TGD_O;
logic ACK_I;
logic [WB_ADR_WIDTH -1 : 0] ADR_O;
logic CYC_O;
logic ERR_I;
logic LOCK_O;
logic RTY_I;
logic [WB_SEL_WIDTH -1 : 0] SEL_O;
logic STB_O;
logic [WB_TGA_WIDTH -1 :0 ] TGA_O;
logic [WB_TGA_WIDTH -1 :0 ] TGC_O;
logic WE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_I;
logic [WB_CTI_WIDTH -1 :0 ] CTI_O;
logic [WB_CTI_WIDTH -1 :0 ] CTI_I;
 
 
logic ACK_O;
logic [WB_ADR_WIDTH -1 : 0] ADR_I;
logic CYC_I;
logic ERR_O;
logic LOCK_I;
logic RTY_O;
logic [WB_SEL_WIDTH -1 : 0] SEL_I;
logic [WB_TGA_WIDTH -1 :0 ] TGA_I;
logic [WB_TGA_WIDTH -1 :0 ] TGC_I;
logic WE_I;
 
modport master(
output ADR_O,
output TGA_O,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
output WE_O,
output SEL_O,
output STB_O,
input ACK_I,
output CYC_O,
input ERR_I,
output LOCK_O,
output BTE_O,
input RTY_I,
output TGC_O
);
 
modport slave(
output ADR_I,
output TGA_I,
input DAT_I,
input TGD_I,
output DAT_O,
output TGD_O,
output WE_I,
output SEL_I,
output STB_I,
input ACK_O,
output CYC_I,
input ERR_O,
output LOCK_I,
input BTE_I,
input RTY_O,
output TGC_I
);
 
 
endinterface
/wb2axi4/trunk/rtl/ifaces/axi_if.sv
0,0 → 1,147
interface axi_if
#(AXI_WID_WIDTH = 8,
AXI_ADDR_WIDTH = 32,
AXI_DATA_WIDTH = 32,
AXI_PROT_WIDTH = 3,
AXI_STB_WIDTH = 4,
AXI_LEN_W = 4,
AXI_ASIZE_W = 3,
AXI_ABURST_W = 2,
AXI_ALOCK_W = 2,
AXI_ACACHE_W = 4,
AXI_RESP_W = 2
)
();
 
//Write control channel signals
logic [AXI_WID_WIDTH - 1:0] AWID ;
logic [AXI_ADDR_WIDTH - 1:0] AWADDR ;
logic [AXI_LEN_W - 1:0] AWLEN ;
logic [AXI_ASIZE_W - 1:0] AWSIZE ;
logic [AXI_ABURST_W - 1:0] AWBURST ;
logic [AXI_ALOCK_W - 1:0] AWLOCK ;
logic [AXI_ACACHE_W - 1:0] AWCACHE ;
logic [AXI_PROT_WIDTH - 1:0] AWPROT ;
logic AWVALID ;
logic AWREADY ;
//write data channel signals
logic [AXI_WID_WIDTH - 1:0] WID ;
logic [AXI_DATA_WIDTH - 1:0] WDATA ;
logic [AXI_STB_WIDTH - 1:0] WSTRB ;
logic WLAST ;
logic WVALID ;
logic WREADY ;
//write response channel
logic [AXI_WID_WIDTH - 1:0] BID ;
logic [AXI_RESP_W - 1:0] BRESP ;
logic BVALID ;
logic BREADY ;
//Read control channel signals
logic [AXI_WID_WIDTH - 1:0] ARID ;
logic [AXI_ADDR_WIDTH - 1:0] ARADDR ;
logic [AXI_LEN_W - 1:0] ARLEN ;
logic [AXI_ASIZE_W - 1:0] ARSIZE ;
logic [AXI_ABURST_W - 1:0] ARBURST ;
logic [AXI_ALOCK_W - 1:0] ARLOCK ;
logic [AXI_ACACHE_W - 1:0] ARCACHE ;
logic [AXI_PROT_WIDTH - 1:0] ARPROT ;
logic ARVALID ;
logic ARREADY ;
//Read data channel signals
logic [AXI_WID_WIDTH - 1:0] RID ;
logic [AXI_DATA_WIDTH - 1:0] RDATA ;
logic [AXI_RESP_W - 1:0] RRESP ;
logic RLAST ;
logic RVALID ;
logic RREADY ;
 
modport initiator (
//Write control channel signals
output AWID ,
output AWADDR ,
output AWLEN ,
output AWSIZE ,
output AWBURST ,
output AWLOCK ,
output AWCACHE ,
output AWPROT ,
output AWVALID ,
input AWREADY ,
//write data channel signals
output WID ,
output WDATA ,
output WSTRB ,
output WLAST ,
output WVALID ,
input WREADY ,
//write response channel
input BID ,
input BRESP ,
input BVALID ,
output BREADY ,
//Read control channel signals
output ARID ,
output ARADDR ,
output ARLEN ,
output ARSIZE ,
output ARBURST ,
output ARLOCK ,
output ARCACHE ,
output ARPROT ,
output ARVALID ,
input ARREADY ,
//Read data channel signals
input RID ,
input RDATA ,
input RRESP ,
input RLAST ,
input RVALID ,
output RREADY
);
 
modport target (
//Write control channel signals
input AWID ,
input AWADDR ,
input AWLEN ,
input AWSIZE ,
input AWBURST ,
input AWLOCK ,
input AWCACHE ,
input AWPROT ,
input AWVALID ,
output AWREADY ,
//write data channel signals
input WID ,
input WDATA ,
input WSTRB ,
input WLAST ,
input WVALID ,
output WREADY ,
//write response channel
output BID ,
output BRESP ,
output BVALID ,
input BREADY ,
//Read control channel signals
input ARID ,
input ARADDR ,
input ARLEN ,
input ARSIZE ,
input ARBURST ,
input ARLOCK ,
input ARCACHE ,
input ARPROT ,
input ARVALID ,
output ARREADY ,
//Read data channel signals
output RID ,
output RDATA ,
output RRESP ,
output RLAST ,
output RVALID ,
input RREADY
);
 
endinterface
 
/wb2axi4/trunk/rtl/ifaces/sram_if.sv
0,0 → 1,35
interface sram_if
#(
DATA_W = 64,
ADDR_W = 13
)
();
 
logic rd_l ;
logic wr_l ;
logic [ADDR_W-1:0] rd_address ;
logic [ADDR_W-1:0] wr_address ;
logic [DATA_W-1:0] rdata ;
logic [DATA_W-1:0] wdata ;
 
modport initiator (
output rd_l ,
output wr_l ,
output rd_address ,
output wr_address ,
input rdata ,
output wdata
);
 
modport target (
input rd_l ,
input wr_l ,
input rd_address ,
input wr_address ,
output rdata ,
input wdata
);
 
endinterface
 
 

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