OpenCores
URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/trunk/rtl-model/defines.v
0,0 → 1,6
`include "rom_def.v"
 
`define IR_SIZE 36
`define MEM_OP 31
`define ADD_IP `IR_SIZE'bx__0__1__0__1__10_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
`define OP_NOP 8'h90
/trunk/rtl-model/regfile.v
0,0 → 1,63
`timescale 1ns/10ps
 
module regfile(a, b, c, cs, ip, d, s, flags, wr, wrfl, wrhi, clk, rst,
addr_a, addr_b, addr_c, addr_d, addr_s, iflags, word_op,
o_byte, c_byte, cx_zero);
// IO Ports
output [15:0] a, b, c, s;
output [15:0] cs;
input [3:0] addr_a, addr_b, addr_c, addr_d;
input [1:0] addr_s;
input [8:0] iflags;
input [31:0] d;
input wrfl, wrhi, word_op, clk, rst, o_byte, c_byte;
input wr;
output cx_zero;
output [15:0] ip;
output reg [8:0] flags;
 
// Net declarations
reg [15:0] r[15:0];
wire [7:0] a8, b8, c8;
 
// Assignments
assign a = (o_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
assign a8 = addr_a[2] ? r[addr_a[1:0]][15:8] : r[addr_a][7:0];
 
assign b = (o_byte & ~addr_b[3]) ? { {8{b8[7]}}, b8} : r[addr_b];
assign b8 = addr_b[2] ? r[addr_b[1:0]][15:8] : r[addr_b][7:0];
 
assign c = (c_byte & ~addr_c[3]) ? { {8{c8[7]}}, c8} : r[addr_c];
assign c8 = addr_c[2] ? r[addr_c[1:0]][15:8] : r[addr_c][7:0];
 
assign s = r[{2'b10,addr_s}];
 
assign cs = r[9];
assign cx_zero = (addr_d==4'd1) ? (d==16'd0) : (r[1]==16'd0);
 
assign ip = r[15];
 
// Behaviour
always @(posedge clk)
if (rst) begin
r[0] <= 16'd0; r[1] <= 16'd0;
r[2] <= 16'd0; r[3] <= 16'd0;
r[4] <= 16'd0; r[5] <= 16'd0;
r[6] <= 16'd0; r[7] <= 16'd0;
r[8] <= 16'd0; r[9] <= 16'hf000;
r[10] <= 16'd0; r[11] <= 16'd0;
r[12] <= 16'd0; r[13] <= 16'd0;
r[14] <= 16'd0; r[15] <= 16'hfff0;
flags <= 9'd0;
end else
begin
if (wr) begin
if (word_op | addr_d[3:2]==2'b10)
r[addr_d] <= word_op ? d[15:0] : {{8{d[7]}},d[7:0]};
else if (addr_d[3]~^addr_d[2]) r[addr_d][7:0] <= d[7:0];
else r[{2'b0,addr_d[1:0]}][15:8] <= d[7:0];
end
if (wrfl) flags <= iflags;
if (wrhi) r[4'd2] <= d[31:16];
end
endmodule
/trunk/rtl-model/alu.v
0,0 → 1,406
`timescale 1ns/10ps
 
module alu(x, y, out, t, func, iflags, oflags, word_op, seg, off);
// IO ports
input [/* 31 */ 15:0] x;
input [15:0] y;
input [2:0] t, func;
input [15:0] iflags;
input word_op;
input [15:0] seg, off;
output [31:0] out;
output [8:0] oflags;
 
// Net declarations
wire [15:0] add /* adj, log, shi, rot */;
wire [8:0] othflags;
wire [19:0] oth;
// wire [31:0] cnv, mul;
// wire af_add, af_adj;
// wire cf_adj, cf_add, cf_mul, cf_log, cf_shi, cf_rot;
// wire of_adj, of_add, of_mul, of_log, of_shi, of_rot;
wire /* ofi, */ sfi, zfi, /* afi, */ pfi, cfi;
wire /* ofo, */ sfo, zfo, /* afo, */ pfo /*, cfo */;
wire flags_unchanged;
 
// Module instances
addsub ad0(x[15:0], y, add, func, word_op, cfi, /* cf_add */, /* af_add, */
/* of_add */);
/*
adj adj0(x[15:0], y, {cf_adj, adj}, func, afi, cfi, af_adj, of_adj);
conv cnv0(x[15:0], cnv, func[0]);
muldiv mul0(x, y, mul, func[1:0], word_op, cf_mul, of_mul);
bitlog lo0(x[15:0], y, log, func, cf_log, of_log);
shifts sh0(x[15:0], y, shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
rotat rot0(x[15:0], y, rot, func[1:0], word_op, cfi, cf_rot, of_rot);
*/
othop oth0(x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
 
mux8_16 m0(t, 16'd0/* adj */, add, 16'd0/* cnv[15:0] */,
16'd0 /* mul[15:0] */, 16'd0 /* log */, 16'd0 /* shi */,
16'd0 /* rot */, oth[15:0], out[15:0]);
mux8_16 m1(t, 16'd0, 16'd0, 16'd0 /* cnv[31:16] */, 16'd0 /* mul[31:16] */,
16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
// mux8_1 a1(t, cf_adj, cf_add, cfi, cf_mul, cf_log, cf_shi, cf_rot, 1'b0, cfo);
// mux8_1 a2(t, af_adj, af_add, afi, 1'b0, 1'b0, 1'b0, afi, 1'b0, afo);
// mux8_1 a3(t, of_adj, of_add, ofi, of_mul, of_log, of_shi, of_rot, 1'b0, ofo);
 
// Flags
assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
assign zfo = flags_unchanged ? zfi : (word_op ? ~|out[15:0] : ~|out[7:0]);
assign sfo = flags_unchanged ? sfi : (word_op ? out[15] : out[7]);
 
assign oflags = (t == 3'd7) ? othflags
: { 1'b0 /* ofo */, iflags[10:8], sfo, zfo, 1'b0 /* afo */,
pfo, 1'b0 /* cfo */ };
 
// assign ofi = iflags[11];
assign sfi = iflags[7];
assign zfi = iflags[6];
// assign afi = iflags[4];
assign pfi = iflags[2];
assign cfi = iflags[0];
 
assign flags_unchanged = (t == 4'd6 || t == 4'd2 || t == 4'd4 && func == 4'd1);
endmodule
 
module addsub(x, y, out, func, word_op, cfi, cfo, /* afo, */ ofo);
// IO ports
input [15:0] x, y;
input [2:0] func;
input cfi, word_op;
output cfo, /* afo, */ ofo;
output [15:0] out;
 
// Net declarations
wire [16:0] adc, add, ad8, dec, neg, sbb, sub, cmp;
// wire [4:0] tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7;
wire resta, bneg, bincdec, cfo8, cfo16, ofo8, ofo16, cfoneg8, cfoneg16;
// wire afo_adc, afo_add, afo_inc, afo_dec, afo_neg, afo_sbb, afo_sub, afo_cmp;
wire [16:0] out17;
 
// Module instances
mux8_17 m0(func, adc, add, ad8, dec, neg, sbb, sub, cmp, out17);
/* mux8_1 m1(func, afo_adc, afo_add, afo_inc, afo_dec,
afo_neg, afo_sbb, afo_sub, afo_cmp, afo); */
 
// Assignments
assign adc = x + y + cfi;
assign add = x + y;
assign ad8 = x + y[7:0];
assign dec = x - 8'b1;
assign neg = {x==16'd0 ? 1'b0 : 1'b1, -x};
assign sbb = x - y - cfi;
assign sub = x - y;
assign cmp = x - y;
/*
assign tmp0 = x[3:0] + y[3:0] + cfi;
assign tmp1 = x[3:0] + y[3:0];
assign tmp2 = x[3:0] + 4'b1;
assign tmp3 = x[3:0] - 4'b1;
assign tmp4 = -x[3:0];
assign tmp5 = x[3:0] - y[3:0] -cfi;
assign tmp6 = x[3:0] - y[3:0];
assign tmp7 = x[3:0] - y[3:0];
 
assign afo_adc = tmp0[4];
assign afo_add = tmp1[4];
assign afo_inc = tmp2[4];
assign afo_dec = tmp3[4];
assign afo_neg = tmp4[4];
assign afo_sbb = tmp5[4];
assign afo_sub = tmp6[4];
assign afo_cmp = tmp7[4];
*/
assign resta = (func > 3'd2);
assign bneg = (func == 3'd4);
assign ofo16 = resta ? ( bneg ? x[15] & out[15] :
(~x[15] & y[15] & out[15] | x[15] & ~y[15] & ~out[15]))
: (~x[15] & ~y[15] & out[15] | x[15] & y[15] & ~out[15]);
 
assign ofo8 = resta ? ( bneg ? x[7] & out[7] :
(~x[7] & y[7] & out[7] | x[7] & ~y[7] & ~out[7]))
: (~x[7] & ~y[7] & out[7] | x[7] & y[7] & ~out[7]);
 
assign cfoneg8 = x[7:0]!=8'd0;
assign cfoneg16 = x[15:0]!=16'd0;
assign bincdec = (func == 3'd2 || func == 3'd3);
assign cfo8 = bneg ? cfoneg8 : out17[8];
assign cfo16 = bneg ? cfoneg16 : out17[16];
assign out = out17[15:0];
assign cfo = bincdec ? cfi : (word_op ? cfo16 : cfo8);
assign ofo = word_op ? ofo16 : ofo8;
endmodule
 
/*
module adj(x, y, out, func, afi, cfi, afo, cfo);
// IO ports
input [15:0] x, y;
input [2:0] func;
input afi, cfi;
output afo, cfo;
output [16:0] out;
 
// Net declarations
wire [16:0] aaa, aad, aam, aas, daa, das, aad16;
wire [7:0] ala, als, alout;
wire alcnd;
 
// Module instances
mux8_17 m0(func, aaa, aad, aam, aas,
daa, das, {9'd0, y[7:0]}, {1'b0, y}, out);
// Assignments
assign aaa = afo ? { x[15:8] + 8'd1, (x[7:0] + 8'd6) & 8'h0f } : x;
assign aad16 = x[15:8] * 8'd10 + x[7:0];
assign aad = { 8'b0, aad16[7:0] };
assign aam = 16'd0; // FIXME: { x[7:0] / 8'd10, x[7:0] % 8'd10 };
assign aas = afo ? { x[15:8] - 8'd1, (x[7:0] - 8'd6) & 8'h0f } : x;
 
assign ala = afo ? x[7:0] + 8'd6 : x[7:0];
assign als = afo ? x[7:0] - 8'd6 : x[7:0];
assign alout = (func == 3'd4) ? ala : als;
assign alcnd = (alout > 8'h9f) | cfi;
assign daa = alcnd ? { x[15:8], x[3:0] + 8'h60 } : { x[15:8], alout };
assign das = alcnd ? { x[15:8], x[3:0] - 8'h60 } : { x[15:8], alout };
 
assign afo = (x[3:0] > 4'd9) | afi;
assign cfo = func[2] ? alcnd : afo;
endmodule
 
module conv(x, out, func);
// IO ports
input [15:0] x;
input func; // type = 010 and func = 111 is reserved for INTO
output [31:0] out;
// Net declarations
wire [31:0] cbw, cwd;
wire [23:0] x7_24;
wire [15:0] x15_16;
 
// Assignments
assign x7_24 = { 24{x[7]} };
assign x15_16 = { 16{x[15]} };
assign cbw = { x7_24, x[7:0] };
assign cwd = { x15_16, x[7:0] };
assign out = func ? cwd : cbw;
endmodule
 
module muldiv(x, y, out, func, word_op, cfo, ofo);
// IO ports
input [31:0] x;
input [15:0] y;
input [1:0] func;
input word_op;
output [31:0] out;
output cfo, ofo;
 
// Net declarations
wire signed [31:0] x_s, imul, idiv32, mods32;
wire signed [15:0] y_s, idivr16, modsr16, idiv16, mods16;
wire signed [7:0] idivr8, modsr8;
wire [31:0] mul, div32, modu32, div, idiv;
wire [15:0] divr16, modur16, div16, modu16;
wire [7:0] divr8, modur8;
wire cfo8, cfo16;
 
// Module instantiations
mux4_32 m0(func, mul, imul, div, idiv, out);
 
// Assignments
assign x_s = x;
assign y_s = y;
assign mul = x[15:0] * y;
assign imul = x_s[15:0] * y_s;
 
assign div32 = x / y;
assign modu32 = x % y;
assign idiv32 = x_s / y_s;
assign mods32 = x_s % y_s;
assign divr16 = div32[15:0];
assign modur16 = modu32[15:0];
assign idivr16 = idiv32[15:0];
assign modsr16 = mods32[15:0];
 
assign div16 = x[15:0] / y[7:0];
assign modu16 = x[15:0] % y[7:0];
assign idiv16 = x_s[15:0] / y_s[7:0];
assign mods16 = x_s[15:0] % y_s[7:0];
assign divr8 = div16[7:0];
assign modur8 = modu16[7:0];
assign idivr8 = idiv16[7:0];
assign modsr8 = mods16[7:0];
 
assign div = word_op ? { modur16, divr16 } : { 16'd0, modur8, divr8 };
assign idiv = word_op ? { modsr16, idivr16 } : { 16'd0, modsr8, idivr8 };
 
assign cfo16 = (out[31:16] != { 16{out[15]} });
assign cfo8 = (out[15:8] != { 8{out[7]} });
assign cfo = word_op ? cfo16 : cfo8;
assign ofo = cfo;
endmodule
 
module bitlog(x, y, out, func, cfo, ofo);
// IO ports
input [15:0] x, y;
input [2:0] func;
output [15:0] out;
output cfo, ofo;
 
// Net declarations
wire [15:0] and_n, or_n, not_n, xor_n, test_n;
// Module instantiations
mux8_16 m0(func, and_n, or_n, not_n, xor_n, test_n, 16'd0, 16'd0, 16'd0, out);
 
// Assignments
assign and_n = x & y;
assign or_n = x | y;
assign not_n = ~x;
assign xor_n = x ^ y;
assign test_n = x & y;
 
assign cfo = 1'b0;
assign ofo = 1'b0;
endmodule
 
module shifts(x, y, out, func, word_op, cfi, ofi, cfo, ofo);
// IO ports
input [15:0] x, y;
input [1:0] func;
input cfi, ofi;
input word_op;
output [15:0] out;
output cfo, ofo;
 
// Net declarations
wire [15:0] sal_shl, sar, shr, sar16, shr16;
wire [7:0] sar8, shr8;
wire signed [15:0] x_s;
wire ofo_shl, ofo_sar, ofo_shr, ofo_o, cfo16, cfo8;
 
// Module instantiations
mux4_16 m0(func, sal_shl, sar, shr, 16'd0, out);
mux4_1 m1(func, ofo_shl, ofo_sar, ofo_shr, 1'b0, ofo_o);
 
// Assignments
assign x_s = x;
assign sal_shl = x << y[7:0];
assign sar16 = x_s >>> y[7:0];
assign shr16 = x >> y[7:0];
assign sar8 = x_s[7:0] >>> y[7:0];
assign shr8 = x[7:0] >> y[7:0];
assign shr = word_op ? shr16 : {8'd0, shr8};
assign sar = word_op ? sar16 : {8'd0, sar8};
 
assign cfo16 = (y == 16'd0) ? cfi :
( (func==2'd0) ? |(x & (16'h8000 >> (y-1))) : |(x & (16'h1 << (y-1))));
assign cfo8 = (y[7:0] == 8'd0) ? cfi :
( (func==2'd0) ? |(x[7:0] & (8'h80 >> (y-1)))
: |(x[7:0] & (8'h1 << (y-1))));
assign cfo = word_op ? cfo16 : cfo8;
assign ofo = (y == 16'd0) ? ofi : ofo_o;
assign ofo_shl = word_op ? (out[15] != cfo) : (out[7] != cfo);
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
endmodule
 
module rotat(x, y, out, func, word_op, cfi, cfo, ofo);
// IO ports
input [15:0] x, y;
input [1:0] func;
input cfi, word_op;
output [15:0] out;
output cfo;
output ofo;
 
// Net declarations
wire [15:0] rcl16, rcr16, rol16, ror16, rcl, rcr, rol, ror;
wire [7:0] yce16, ye16, yce8, ye8, rcl8, rcr8, rol8, ror8, yc16, yc8;
wire cfo_rcl, cfo_rcr, cfo_rol, cfo_ror;
 
// Module instantiations
mux4_16 m0(func, rcl, rcr, rol, ror, out);
mux4_1 m1(func, cfo_rcl, cfo_rcr, cfo_rol, cfo_ror, cfo);
 
// Assignments
assign yce16 = ye16; // FIXME: y[7:0] % 8'd17;
assign ye16 = y[7:0] % 8'd16;
assign rcl16 = yce16 ? (x << yce16 | cfi << (yce16-8'd1) | x >> (8'd17-yce16)) : x;
assign rcr16 = yce16 ? (x >> yce16 | cfi << (8'd16-yce16) | x << (8'd17-yce16)) : x;
assign rol16 = (x << ye16 | x >> (8'd16-ye16));
assign ror16 = (x >> ye16 | x << (8'd16-ye16));
 
assign yce8 = ye8; // FIXME: y[7:0] % 8'd9;
assign ye8 = y[7:0] % 8'd8;
assign rcl8 = yce8 ? (x[7:0] << yce8 | cfi << (yce8-8'd1) | x[7:0] >> (8'd9-yce8)) : x[7:0];
assign rcr8 = yce8 ? (x[7:0] >> yce8 | cfi << (8'd8-yce8) | x[7:0] << (9'd9-yce8)) : x[7:0];
assign rol8 = (x[7:0] << ye8 | x[7:0] >> (8'd8-ye8));
assign ror8 = (x[7:0] >> ye8 | x[7:0] << (8'd8-ye8));
 
assign rcl = word_op ? rcl16 : { 8'd0, rcl8 };
assign rcr = word_op ? rcr16 : { 8'd0, rcr8 };
assign rol = word_op ? rol16 : { 8'd0, rol8 };
assign ror = word_op ? ror16 : { 8'd0, ror8 };
 
// Carry
assign yc16 = (y[7:0]-8'd1)%8'd16;
assign yc8 = (y[7:0]-8'd1)%8'd8;
assign cfo_rcl = word_op ? (yce16==8'd0 ? cfi : x[16-yce16])
: (yce8==8'd0 ? cfi : x[8-yce8]);
assign cfo_rcr = word_op ? (yce16==8'd0 ? cfi : x[yce16-1])
: (yce8==8'd0 ? cfi : x[yce8-1]);
assign cfo_rol = word_op ? (y[7:0]==8'd0 ? cfi : x[15-yc16])
: (y[7:0]==8'd0 ? cfi : x[7-yc8]);
assign cfo_ror = word_op ? (y[7:0]==8'd0 ? cfi : x[yc16])
: (y[7:0]==8'd0 ? cfi : x[yc8]);
 
// Overflow
assign ofo = func[0] ? // right
(word_op ? out[15]^out[14] : out[7]^out[6])
: // left
(word_op ? cfo^out[15] : cfo^out[7]);
endmodule
*/
 
module othop (x, y, seg, off, iflags, func, word_op, out, oflags);
// IO ports
input [15:0] x, y, off, seg, iflags;
input [2:0] func;
input word_op;
output [19:0] out;
output [8:0] oflags;
 
// Net declarations
wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
wire [19:0] dcmp, dcmp2;
wire dfi;
 
// Module instantiations
mux8_16 m0(func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf,
intf, strf, out[15:0]);
assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
 
// Assignments
assign dcmp = (seg << 4) + deff;
assign dcmp2 = (seg << 4) + deff2;
assign deff = x + y + off;
assign deff2 = x + y + off + 16'd2;
assign outf = y;
assign clcm = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0}
: /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
: (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
: /* 0: cmc */ {iflags[15:1], ~iflags[0]});
assign setf = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1}
: /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
: (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
: /* 0: outf */ iflags);
 
assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
assign dfi = iflags[10];
assign strf = dfi ? (x - y) : (x + y);
 
assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
: { iflags[11:8], out[7:6], out[4], out[2], out[0] };
endmodule
/trunk/rtl-model/exec.v
0,0 → 1,81
`timescale 1ns/10ps
 
`include "defines.v"
 
module exec(ir, off, imm, cs, ip, of, zf, cx_zero, clk, rst,
memout, wr_data, addr, we, m_io, wr_cnd, byteop, mem_rdy);
// IO Ports
input [`IR_SIZE-1:0] ir;
input [15:0] off, imm;
input clk;
input rst;
input [15:0] memout;
input mem_rdy;
 
output [15:0] wr_data, ip;
output of;
output zf;
output cx_zero;
output we, m_io, byteop;
output [19:0] addr;
output [15:0] cs;
 
// Net declarations
wire [15:0] a, b, c, s, alu_iflags, omemalu, bus_b;
wire [31:0] aluout;
wire [3:0] addr_a, addr_b, addr_c, addr_d;
wire [2:0] t, func;
wire [1:0] addr_s;
wire wrfl, high, wr_mem, memalu, a_byte, c_byte;
wire wr, wr_reg, block;
/* wire */ output wr_cnd;
// wire jmp;
wire mem_op, b_imm;
wire [8:0] flags, iflags, oflags;
// wire [4:0] logic_flags;
 
// Module instances
alu alu0( /*{c,*/ a /*}*/, bus_b, aluout, t, func, alu_iflags, oflags,
~byteop, s, off);
regfile reg0( a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,
high, clk, rst, addr_a, addr_b, addr_c, addr_d, addr_s, iflags,
~byteop, a_byte, c_byte, cx_zero);
// jmp_cond jc0( logic_flags, addr_b, addr_c[0], c, jmp);
 
// Assignments
assign addr_s = ir[1:0];
assign addr_a = ir[5:2];
assign addr_b = ir[9:6];
assign addr_c = ir[13:10];
assign addr_d = ir[17:14];
assign wrfl = ir[18];
assign wr_mem = ir[19];
assign wr = ir[20];
assign wr_cnd = ir[21];
assign high = ir[22];
assign t = ir[25:23];
assign func = ir[28:26];
assign byteop = ir[29];
assign memalu = ir[30];
assign mem_op = ir[31];
assign m_io = ir[32];
assign b_imm = ir[33];
assign a_byte = ir[34];
assign c_byte = ir[35];
 
assign omemalu = memalu ? aluout[15:0] : memout;
assign bus_b = b_imm ? imm : b;
 
assign we = ~wr_mem;
assign addr = aluout[19:0];
assign wr_data = c;
assign wr_reg = (wr /* | (jmp & wr_cnd) */) && !block;
assign of = flags[8];
assign zf = flags[3];
assign block = mem_op && !mem_rdy;
 
assign iflags = oflags;
assign alu_iflags = { 4'b0, flags[8:3], 1'b0, flags[2], 1'b0, flags[1],
1'b1, flags[0] };
// assign logic_flags = { flags[8], flags[4], flags[3], flags[1], flags[0] };
endmodule
/trunk/rtl-model/cpu.v
0,0 → 1,37
`timescale 1ns/10ps
 
`include "defines.v"
 
module cpu(
input clk,
input rst,
input [15:0] rd_data,
output [15:0] wr_data,
output [19:0] addr,
output we,
output m_io,
output wr_cnd, // Stub
output byte_m,
output mem_op,
input mem_rdy
);
 
// Net declarations
wire [15:0] cs, ip;
wire [`IR_SIZE-1:0] ir;
wire [15:0] off, imm;
wire [19:0] addr_exec, addr_fetch;
wire byte_fetch, byte_exec, fetch_or_exec;
wire of, zf, cx_zero;
 
// Module instantiations
fetch fetch0(clk, rst, cs, ip, of, zf, cx_zero, rd_data, ir, off,
imm, addr_fetch, byte_fetch, fetch_or_exec, mem_rdy);
exec exec0(ir, off, imm, cs, ip, of, zf, cx_zero, clk, rst,
rd_data, wr_data, addr_exec, we, m_io, wr_cnd, byte_exec, mem_rdy);
 
// Assignments
assign addr = fetch_or_exec ? addr_exec : addr_fetch;
assign byte_m = fetch_or_exec ? byte_exec : byte_fetch;
assign mem_op = rst ? 1'b1 : ir[`MEM_OP];
endmodule
/trunk/rtl-model/fetch.v
0,0 → 1,1030
`timescale 1ns/10ps
 
`include "defines.v"
 
module fetch (
input clk,
input rst,
input [15:0] cs,
input [15:0] ip,
input of,
input zf,
input cx_zero,
input [15:0] data,
output [`IR_SIZE-1:0] ir,
output [15:0] off,
output [15:0] imm,
output [19:0] pc,
output bytefetch,
output fetch_or_exec,
input mem_rdy
);
 
// Registers, nets and parameters
parameter opcod_st = 3'h0;
parameter modrm_st = 3'h1;
parameter offse_st = 3'h2;
parameter immed_st = 3'h3;
parameter execu_st = 3'h4;
 
wire [`IR_SIZE-1:0] rom_ir;
wire [7:0] opcode, modrm;
wire exec_st, end_seq;
wire [15:0] imm_d;
wire [2:0] next_state;
wire prefix;
wire next_in_opco, next_in_exec;
wire block;
wire need_modrm, need_off, need_imm, off_size, imm_size;
 
reg [2:0] state;
reg [7:0] opcode_l, modrm_l;
reg [15:0] off_l, imm_l;
reg [1:0] pref_l;
 
// Module instantiation
decode decode0(opcode, modrm, off_l, imm_l, /* pref_l[1], */ clk, rst, block,
exec_st, need_modrm, need_off, need_imm, off_size, imm_size,
rom_ir, off, imm_d, end_seq);
next_or_not nn0(pref_l, opcode[7:1], cx_zero, zf, next_in_opco,
next_in_exec);
nstate ns0(state, prefix, need_modrm, need_off, need_imm, end_seq,
rom_ir[28:23], of, next_in_opco, next_in_exec, block,
next_state);
 
// Assignments
assign pc = (cs << 4) + ip;
 
assign ir = (state == execu_st) ? rom_ir : `ADD_IP;
assign opcode = (state == opcod_st) ? data[7:0] : opcode_l;
assign modrm = (state == modrm_st) ? data[7:0] : modrm_l;
assign fetch_or_exec = (state == execu_st);
assign bytefetch = (state == offse_st) ? ~off_size
: ((state == immed_st) ? ~imm_size : 1'b1);
assign exec_st = (state == execu_st);
assign imm = (state == execu_st) ? imm_d
: ((state == offse_st) & off_size
| (state == immed_st) & imm_size) ? 16'd2
: 16'd1;
assign prefix = (opcode[7:1]==7'b1111_001);
assign block = ir[`MEM_OP] && !mem_rdy;
 
// Behaviour
always @(posedge clk)
if (rst)
begin
state <= execu_st;
opcode_l <= `OP_NOP;
end
else if (!block)
case (next_state)
default: // opcode or prefix
begin
case (state)
opcod_st: pref_l <= prefix ? { 1'b1, opcode[0] } : 2'b0;
default: pref_l <= 2'b0;
endcase
state <= opcod_st;
off_l <= 16'd0;
end
 
modrm_st: // modrm
begin
opcode_l <= data[7:0];
state <= modrm_st;
end
 
offse_st: // offset
begin
case (state)
opcod_st: opcode_l <= data[7:0];
default: modrm_l <= data[7:0];
endcase
state <= offse_st;
end
 
immed_st: // immediate
begin
case (state)
opcod_st: opcode_l <= data[7:0];
modrm_st: modrm_l <= data[7:0];
default: off_l <= data;
endcase
state <= immed_st;
end
 
execu_st: // execute
begin
case (state)
opcod_st: opcode_l <= data[7:0];
modrm_st: modrm_l <= data[7:0];
offse_st: off_l <= data;
immed_st: imm_l <= data;
endcase
state <= execu_st;
end
endcase
endmodule
 
module nstate (
input [2:0] state,
input prefix,
input need_modrm,
input need_off,
input need_imm,
input end_seq,
input [5:0] ftype,
input of,
input next_in_opco,
input next_in_exec,
input block,
output [2:0] next_state
);
 
// Net declarations
parameter opcod_st = 3'h0;
parameter modrm_st = 3'h1;
parameter offse_st = 3'h2;
parameter immed_st = 3'h3;
parameter execu_st = 3'h4;
wire into, end_instr, end_into;
wire [2:0] n_state;
 
// Assignments
assign into = (ftype==6'b111_010);
assign end_into = into ? ~of : end_seq;
assign end_instr = end_into && !next_in_exec;
 
assign n_state = (state == opcod_st) ? (prefix ? opcod_st
: (next_in_opco ? opcod_st
: (need_modrm ? modrm_st
: (need_off ? offse_st
: (need_imm ? immed_st : execu_st)))))
: (state == modrm_st) ? (need_off ? offse_st
: (need_imm ? immed_st : execu_st))
: (state == offse_st) ? (need_imm ? immed_st : execu_st)
: (state == immed_st) ? (execu_st)
: (end_instr ? opcod_st : execu_st);
 
assign next_state = block ? state : n_state;
endmodule
 
module next_or_not (
input [1:0] prefix,
input [7:1] opcode,
input cx_zero,
input zf,
output next_in_opco,
output next_in_exec
);
 
// Net declarations
wire exit_z, cmp_sca, exit_rep, valid_ops;
 
// Assignments
assign cmp_sca = opcode[2] & opcode[1];
assign exit_z = prefix[0] ? /* repz */ (cmp_sca ? ~zf : 1'b0 )
: /* repnz */ (cmp_sca ? zf : 1'b0 );
assign exit_rep = cx_zero | exit_z;
assign valid_ops = (opcode[7:1]==7'b1010_010 // movs
|| opcode[7:1]==7'b1010_011 // cmps
|| opcode[7:1]==7'b1010_101 // stos
|| opcode[7:1]==7'b1010_110 // lods
|| opcode[7:1]==7'b1010_111); // scas
assign next_in_exec = prefix[1] && valid_ops && !exit_rep;
assign next_in_opco = prefix[1] && valid_ops && cx_zero;
endmodule
 
module decode (
input [7:0] opcode,
input [7:0] modrm,
input [15:0] off_i,
input [15:0] imm_i,
// input rep,
input clk,
input rst,
input block,
input exec_st,
 
output need_modrm,
output need_off,
output need_imm,
output off_size,
output imm_size,
 
output [`IR_SIZE-1:0] ir,
output [15:0] off_o,
output [15:0] imm_o,
output end_seq
);
 
// Net declarations
wire [`SEQ_ADDR_WIDTH-1:0] base_addr, seq_addr;
wire [`SEQ_DATA_WIDTH-2:0] micro_addr;
wire [3:0] src, dst, base, index;
wire [1:0] seg;
reg [`SEQ_ADDR_WIDTH-1:0] seq;
 
// Module instantiations
opcode_deco opcode_deco0 (opcode, modrm, /* rep, */ base_addr, need_modrm,
need_off, need_imm, off_size, imm_size, src, dst,
base, index, seg);
seq_rom seq_rom0 (seq_addr, {end_seq, micro_addr});
micro_data mdata0 (micro_addr, off_i, imm_i, src, dst, base, index, seg,
ir, off_o, imm_o);
 
// Assignments
assign seq_addr = base_addr + seq;
 
// Behaviour
always @(posedge clk)
if (rst) seq <= `SEQ_ADDR_WIDTH'd0;
else if (!block)
seq <= (exec_st && !end_seq && !rst) ? (seq + `SEQ_ADDR_WIDTH'd1)
: `SEQ_ADDR_WIDTH'd0;
 
endmodule
 
module opcode_deco (
input [7:0] opcode,
input [7:0] modrm,
// input rep,
 
output reg [`SEQ_ADDR_WIDTH-1:0] seq_addr,
output reg need_modrm,
output reg need_off,
output reg need_imm,
output reg off_size,
output reg imm_size,
 
output reg [3:0] src,
output reg [3:0] dst,
output [3:0] base,
output [3:0] index,
output [1:0] seg
);
 
// Net declarations
wire [1:0] mod;
wire [2:0] regm;
wire [2:0] rm;
wire d, b, sm, dm;
wire off_size_mod, need_off_mod;
wire [2:0] srcm, dstm;
 
// Module instantiations
memory_regs mr(rm, mod, base, index, seg);
 
// Assignments
assign mod = modrm[7:6];
assign regm = modrm[5:3];
assign rm = modrm[2:0];
assign d = opcode[1];
assign dstm = d ? regm : rm;
assign sm = d & (mod != 2'b11);
assign dm = ~d & (mod != 2'b11);
assign srcm = d ? rm : regm;
assign b = ~opcode[0];
assign off_size_mod = (base == 4'b1100 && index == 4'b1100) ? 1'b1 : mod[1];
assign need_off_mod = (base == 4'b1100 && index == 4'b1100) || ^mod;
 
// Behaviour
always @(opcode or dm or b or need_off_mod or srcm or sm or dstm
or off_size_mod or mod or rm or regm)
casex (opcode)
/*
8'b000x_x110: // push seg
begin
seq_addr <= `PUSHR;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
src <= { 2'b10, opcode[4:3] };
end
 
8'b000x_x111: // pop seg
begin
seq_addr <= `POPR;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
dst <= { 2'b10, opcode[4:3] };
end
 
8'b0101_0xxx: // push reg
begin
seq_addr <= `PUSHR;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
src <= { 1'b0, opcode[2:0] };
end
 
8'b0101_1xxx: // pop reg
begin
seq_addr <= `POPR;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
dst <= { 1'b0, opcode[2:0] };
end
 
8'b0111_xxxx: // jcc
begin
seq_addr <= `JCC;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
src <= { opcode[3:0] };
end
 
8'b1000_011x: // xchg
begin
seq_addr <= (mod==2'b11) ? (b ? `XCHRRB : `XCHRRW)
: (b ? `XCHRMB : `XCHRMW);
need_modrm <= 1'b1;
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
dst <= { 1'b0, dstm };
src <= { 1'b0, srcm };
end
*/
8'b1000_10xx: // mov: r->r, r->m, m->r
begin
if (dm) // r->m
begin
seq_addr <= b ? `MOVRMB : `MOVRMW;
need_off <= need_off_mod;
src <= { 1'b0, srcm };
dst <= 4'b0;
end
else if(sm) // m->r
begin
seq_addr <= b ? `MOVMRB : `MOVMRW;
need_off <= need_off_mod;
src <= 4'b0;
dst <= { 1'b0, dstm };
end
else // r->r
begin
seq_addr <= b ? `MOVRRB : `MOVRRW;
need_off <= 1'b0;
dst <= { 1'b0, dstm };
src <= { 1'b0, srcm };
end
need_imm <= 1'b0;
need_modrm <= 1'b1;
off_size <= off_size_mod;
imm_size <= 1'b0;
end
 
8'b1000_1100: // mov: s->m, s->r
begin
if (dm) // s->m
begin
seq_addr <= `MOVRMW;
need_off <= need_off_mod;
src <= { 1'b1, srcm };
dst <= 4'b0;
end
else // s->r
begin
seq_addr <= `MOVRRW;
need_off <= 1'b0;
src <= { 1'b1, srcm };
dst <= { 1'b0, dstm };
end
need_imm <= 1'b0;
need_modrm <= 1'b1;
off_size <= off_size_mod;
imm_size <= 1'b0;
end
/*
8'b1000_1101: // lea
begin
seq_addr <= `LEA;
need_modrm <= 1'b1;
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
src <= { 1'b0, srcm };
end
*/
8'b1000_1110: // mov: m->s, r->s
begin
if (sm) // m->s
begin
seq_addr <= `MOVMRW;
need_off <= need_off_mod;
src <= 4'b0;
dst <= { 1'b1, dstm };
end
else // r->s
begin
seq_addr <= `MOVRRW;
need_off <= 1'b0;
src <= { 1'b0, srcm };
dst <= { 1'b1, dstm };
end
need_modrm <= 1'b1;
off_size <= off_size_mod;
need_imm <= 1'b0;
imm_size <= 1'b0;
end
/*
8'b1000_1111: // pop mem or (pop reg non-standard)
begin
seq_addr <= (mod==2'b11) ? `POPR : `POPM;
need_modrm <= 1'b1;
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
dst <= { 1'b0, rm };
end
 
8'b1001_0000: // 90h: nop
begin
seq_addr <= `NOP;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1001_0xxx: // xchg acum
begin
seq_addr <= `XCHRRW;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
src <= 4'b0000;
dst <= { 1'b0, opcode[2:0] };
end
 
8'b1001_1010: // call different seg
begin
seq_addr <= `CALLF;
need_modrm <= 1'b0;
need_off <= 1'b1;
off_size <= 1'b1;
need_imm <= 1'b1;
imm_size <= 1'b1;
end
*/
8'b1001_1100: // pushf
begin
seq_addr <= `PUSHF;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
 
off_size <= 1'b0;
imm_size <= 1'b0;
 
src <= 4'b0;
dst <= 4'b0;
end
/*
8'b1001_1101: // popf
begin
seq_addr <= `POPF;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1001_1110: // sahf
begin
seq_addr <= `SAHF;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1001_1111: // lahf
begin
seq_addr <= `LAHF;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
*/
8'b1010_000x: // mov: m->a
begin
seq_addr <= b ? `MOVMAB : `MOVMAW;
need_modrm <= 1'b0;
need_off <= 1'b1;
need_imm <= 1'b0;
off_size <= 1'b1;
imm_size <= 1'b0;
 
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1010_001x: // mov: a->m
begin
seq_addr <= b ? `MOVAMB : `MOVAMW;
need_modrm <= 1'b0;
need_off <= 1'b1;
need_imm <= 1'b0;
off_size <= 1'b1;
imm_size <= 1'b0;
 
src <= 4'b0;
dst <= 4'b0;
end
/*
8'b1010_010x: // movs
begin
seq_addr <= rep ? (b ? `MOVSBR : `MOVSWR) : (b ? `MOVSB : `MOVSW);
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1010_011x: // cmps
begin
seq_addr <= rep ? (b ? `CMPSBR : `CMPSWR) : (b ? `CMPSB : `CMPSW);
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1010_101x: // stos
begin
seq_addr <= rep ? (b ? `STOSBR : `STOSWR) : (b ? `STOSB : `STOSW);
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1010_110x: // lods
begin
seq_addr <= rep ? (b ? `LODSBR : `LODSWR) : (b ? `LODSB : `LODSW);
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1010_111x: // scas
begin
seq_addr <= rep ? (b ? `SCASBR : `SCASWR) : (b ? `SCASB : `SCASW);
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
*/
8'b1011_xxxx: // mov: i->r
begin
seq_addr <= opcode[3] ? `MOVIRW : `MOVIRB;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= opcode[3];
 
src <= 4'b0;
dst <= { 1'b0, opcode[2:0] };
end
/*
8'b1100_0010: // ret near with value
begin
seq_addr <= `RETNV;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b1;
end
 
8'b1100_0011: // ret near
begin
seq_addr <= `RETN0;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1100_0100: // les
begin
seq_addr <= `LES;
need_modrm <= 1'b1;
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
src <= { 1'b0, srcm };
end
 
8'b1100_0101: // lds
begin
seq_addr <= `LDS;
need_modrm <= 1'b1;
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b0;
src <= { 1'b0, srcm };
end
*/
8'b1100_011x: // mov: i->m (or i->r non-standard)
begin
seq_addr <= (mod==2'b11) ? (b ? `MOVIRB : `MOVIRW)
: (b ? `MOVIMB : `MOVIMW);
need_modrm <= 1'b1;
need_off <= need_off_mod;
off_size <= off_size_mod;
need_imm <= 1'b1;
imm_size <= ~b;
 
src <= 4'b0;
dst <= { 1'b0, rm };
end
/*
8'b1100_1010: // ret far with value
begin
seq_addr <= `RETFV;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b1;
end
 
8'b1100_1011: // ret far
begin
seq_addr <= `RETF0;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1100_1100: // int 3
begin
seq_addr <= `INT3;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1100_1101: // int
begin
seq_addr <= `INT;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
end
 
8'b1100_1110: // into
begin
seq_addr <= `INTO;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1100_1111: // iret
begin
seq_addr <= `IRET;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1101_0111: // xlat
begin
seq_addr <= `XLAT;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1110_0000: // loopne
begin
seq_addr <= `LOOPNE;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
end
 
8'b1110_0001: // loope
begin
seq_addr <= `LOOPE;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
end
 
8'b1110_0010: // loop
begin
seq_addr <= `LOOP;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
end
 
8'b1110_0011: // jcxz
begin
seq_addr <= `JCXZ;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
end
 
8'b1110_010x: // in imm
begin
seq_addr <= b ? `INIB : `INIW;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
end
 
8'b1110_011x: // out imm
begin
seq_addr <= b ? `OUTIB : `OUTIW;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b0;
end
 
8'b1110_1000: // call same segment
begin
seq_addr <= `CALLN;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
imm_size <= 1'b1;
end
*/
8'b1110_10x1: // jmp direct
begin
seq_addr <= `JMPI;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b1;
off_size <= 1'b0;
imm_size <= ~opcode[1];
 
src <= 4'b0;
dst <= 4'b0;
end
 
8'b1110_1010: // jmp indirect different segment
begin
seq_addr <= `LJMPI;
need_modrm <= 1'b0;
need_off <= 1'b1;
off_size <= 1'b1;
need_imm <= 1'b1;
imm_size <= 1'b1;
 
src <= 4'b0;
dst <= 4'b0;
end
/*
8'b1110_110x: // in dx
begin
seq_addr <= b ? `INRB : `INRW;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1110_111x: // out dx
begin
seq_addr <= b ? `OUTRB : `OUTRW;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
*/
8'b1111_0100: // hlt
begin
seq_addr <= `HLT;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
 
src <= 4'b0;
dst <= 4'b0;
end
/*
8'b1111_0101: // cmc
begin
seq_addr <= `CMC;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1111_1000: // clc
begin
seq_addr <= `CLC;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1111_1001: // stc
begin
seq_addr <= `STC;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1111_1010: // cli
begin
seq_addr <= `CLI;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1111_1011: // sti
begin
seq_addr <= `STI;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1111_1100: // cld
begin
seq_addr <= `CLD;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
 
8'b1111_1101: // std
begin
seq_addr <= `STD;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
end
*/
8'b1111_1111:
begin
case (regm)
// 3'b010: seq_addr <= (mod==2'b11) ? `CALLNR : `CALLNM;
// 3'b011: seq_addr <= `CALLFM;
3'b100: seq_addr <= (mod==2'b11) ? `JMPR : `JMPM;
3'b101: seq_addr <= `LJMPM;
// 3'b110: seq_addr <= (mod==2'b11) ? `PUSHR : `PUSHM;
default: seq_addr <= `NOP;
endcase
need_modrm <= 1'b1;
need_off <= need_off_mod;
need_imm <= 1'b0;
off_size <= off_size_mod;
imm_size <= 1'b0;
 
src <= { 1'b0, rm };
dst <= 4'b0;
end
 
default: // nop
begin
seq_addr <= `NOP;
need_modrm <= 1'b0;
need_off <= 1'b0;
need_imm <= 1'b0;
off_size <= 1'b0;
imm_size <= 1'b0;
 
src <= 4'b0;
dst <= 4'b0;
end
 
endcase
 
endmodule
 
module memory_regs (
input [2:0] rm,
input [1:0] mod,
output reg [3:0] base,
output reg [3:0] index,
output reg [1:0] seg
);
 
// Behaviour
always @(rm or mod)
case (rm)
3'b000: begin base <= 4'b0011; index <= 4'b0110; seg <= 2'b11; end
3'b001: begin base <= 4'b0011; index <= 4'b0111; seg <= 2'b11; end
3'b010: begin base <= 4'b0101; index <= 4'b0110; seg <= 2'b10; end
3'b011: begin base <= 4'b0101; index <= 4'b0111; seg <= 2'b10; end
3'b100: begin base <= 4'b1100; index <= 4'b0110; seg <= 2'b11; end
3'b101: begin base <= 4'b1100; index <= 4'b0111; seg <= 2'b11; end
3'b110: begin base <= mod ? 4'b0101 : 4'b1100; index <= 4'b1100;
seg <= mod ? 2'b10 : 2'b11; end
3'b111: begin base <= 4'b0011; index <= 4'b1100; seg <= 2'b11; end
endcase
endmodule
 
module micro_data (
input [`MICRO_ADDR_WIDTH-1:0] n_micro,
input [15:0] off_i,
input [15:0] imm_i,
input [3:0] src,
input [3:0] dst,
input [3:0] base,
input [3:0] index,
input [1:0] seg,
output [`IR_SIZE-1:0] ir,
output [15:0] off_o,
output [15:0] imm_o
);
 
// Net declarations
wire [`MICRO_DATA_WIDTH-1:0] micro_o;
wire [16:0] high_ir;
wire var_s, var_off;
wire [1:0] var_a, var_b, var_c, var_d;
wire [2:0] var_imm;
 
wire [3:0] addr_a, addr_b, addr_c, addr_d;
wire [3:0] micro_a, micro_b, micro_c, micro_d;
wire [1:0] addr_s, micro_s;
 
// Module instantiations
micro_rom m0 (n_micro, micro_o);
 
// Assignments
assign micro_s = micro_o[1:0];
assign micro_a = micro_o[5:2];
assign micro_b = micro_o[9:6];
assign micro_c = micro_o[13:10];
assign micro_d = micro_o[17:14];
assign high_ir = micro_o[35:18];
assign var_s = micro_o[36];
assign var_a = micro_o[38:37];
assign var_b = micro_o[40:39];
assign var_c = micro_o[42:41];
assign var_d = micro_o[44:43];
assign var_off = micro_o[45];
assign var_imm = micro_o[48:46];
 
assign imm_o = var_imm == 3'd0 ? (16'h0000)
: (var_imm == 3'd1 ? (16'h0002)
: (var_imm == 3'd2 ? (16'h0004)
: (var_imm == 3'd3 ? off_i
: (var_imm == 3'd4 ? imm_i
: (var_imm == 3'd5 ? 16'hffff
: (var_imm == 3'd6 ? 16'b11 : 16'd1))))));
 
assign off_o = var_off ? off_i : 16'h0000;
 
assign addr_a = var_a == 2'd0 ? micro_a
: (var_a == 2'd1 ? base
: (var_a == 2'd2 ? dst : src ));
assign addr_b = var_b == 2'd0 ? micro_b
: (var_b == 2'd1 ? index : src);
assign addr_c = var_c == 2'd0 ? micro_c
: (var_c == 2'd1 ? dst : src);
assign addr_d = var_d == 2'd0 ? micro_d
: (var_d == 2'd1 ? dst : src);
assign addr_s = var_s ? seg : micro_s;
 
assign ir = { high_ir, addr_d, addr_c, addr_b, addr_a, addr_s };
endmodule
 
module micro_rom (
input [`MICRO_ADDR_WIDTH-1:0] addr,
output [`MICRO_DATA_WIDTH-1:0] q
);
 
// Registers, nets and parameters
reg [`MICRO_DATA_WIDTH-1:0] rom[0:2**`MICRO_ADDR_WIDTH-1];
 
// Assignments
assign q = rom[addr];
 
// Behaviour
initial $readmemb("/home/zeus/zet/rtl-model/micro_rom.dat", rom);
endmodule
 
module seq_rom (
input [`SEQ_ADDR_WIDTH-1:0] addr,
output [`SEQ_DATA_WIDTH-1:0] q
);
 
// Registers, nets and parameters
reg [`SEQ_DATA_WIDTH-1:0] rom[0:2**`SEQ_ADDR_WIDTH-1];
 
// Assignments
assign q = rom[addr];
 
// Behaviour
initial $readmemb("/home/zeus/zet/rtl-model/seq_rom.dat", rom);
endmodule
/trunk/rtl-model/jmp_cond.v
0,0 → 1,50
`timescale 1ns/10ps
 
module jmp_cond (
input [4:0] logic_flags,
input [3:0] cond,
input is_cx,
input [15:0] cx,
output reg jmp
);
 
// Net declarations
wire of, sf, zf, pf, cf;
wire cx_zero;
 
// Assignments
assign of = logic_flags[4];
assign sf = logic_flags[3];
assign zf = logic_flags[2];
assign pf = logic_flags[1];
assign cf = logic_flags[0];
assign cx_zero = ~(|cx);
 
// Behaviour
always @(cond or is_cx or cx_zero or zf or of or cf or sf or pf)
if (is_cx) case (cond)
4'b0000: jmp <= cx_zero; /* jcxz */
4'b0001: jmp <= ~cx_zero; /* loop */
4'b0010: jmp <= zf & ~cx_zero; /* loopz */
default: jmp <= ~zf & ~cx_zero; /* loopnz */
endcase
else case (cond)
4'b0000: jmp <= of;
4'b0001: jmp <= ~of;
4'b0010: jmp <= cf;
4'b0011: jmp <= ~cf;
4'b0100: jmp <= zf;
4'b0101: jmp <= ~zf;
4'b0110: jmp <= cf | zf;
4'b0111: jmp <= ~cf & ~zf;
 
4'b1000: jmp <= sf;
4'b1001: jmp <= ~sf;
4'b1010: jmp <= pf;
4'b1011: jmp <= ~pf;
4'b1100: jmp <= (sf ^ of);
4'b1101: jmp <= (sf ^~ of);
4'b1110: jmp <= zf | (sf ^ of);
4'b1111: jmp <= ~zf & (sf ^~ of);
endcase
endmodule
/trunk/rtl-model/util/primitives.v
0,0 → 1,169
//
// Multiplexor 8:1 de 16 bits d'amplada
//
module mux8_16(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [15:0] out;
 
reg [15:0] out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
 
 
//
// Multiplexor 8:1 de 8 bits d'amplada
//
/*
module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [7:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [7:0] out;
 
reg [7:0] out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
*/
//
// Multiplexor 8:1 de 17 bits d'amplada
//
module mux8_17(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input [16:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [16:0] out;
 
reg [16:0] out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
 
//
// Multiplexor 8:1 d'1 bit d'amplada
//
module mux8_1(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
input [2:0] sel;
input in0, in1, in2, in3, in4, in5, in6, in7;
output out;
 
reg out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
case(sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
endcase
endmodule
 
//
// Multiplexor 4:1 de 32 bits d'amplada
//
/*
module mux4_32(sel, in0, in1, in2, in3, out);
input [1:0] sel;
input [31:0] in0, in1, in2, in3;
output [31:0] out;
 
reg [31:0] out;
 
always @(sel or in0 or in1 or in2 or in3)
case(sel)
2'd0: out = in0;
2'd1: out = in1;
2'd2: out = in2;
2'd3: out = in3;
endcase
endmodule
*/
 
//
// Multiplexor 4:1 de 16 bits d'amplada
//
module mux4_16(sel, in0, in1, in2, in3, out);
input [1:0] sel;
input [15:0] in0, in1, in2, in3;
output [15:0] out;
 
reg [15:0] out;
 
always @(sel or in0 or in1 or in2 or in3)
case(sel)
2'd0: out = in0;
2'd1: out = in1;
2'd2: out = in2;
2'd3: out = in3;
endcase
endmodule
 
//
// Multiplexor 2:1 de 8 bits d'amplada
//
module mux2_8(sel, in0, in1, out);
input sel;
input [7:0] in0, in1;
output [7:0] out;
 
reg [7:0] out;
 
always @(sel or in0 or in1)
case(sel)
1'd0: out = in0;
1'd1: out = in1;
endcase
endmodule
 
//
// Multiplexor 4:1 de 1 bits d'amplada
//
module mux4_1(sel, in0, in1, in2, in3, out);
input [1:0] sel;
input in0, in1, in2, in3;
output out;
 
reg out;
 
always @(sel or in0 or in1 or in2 or in3)
case(sel)
2'd0: out = in0;
2'd1: out = in1;
2'd2: out = in2;
2'd3: out = in3;
endcase
endmodule
/trunk/files.txt
0,0 → 1,33
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_s3_dqs_iob.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_data_read_controller_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_ddr2_dm_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_1.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_clk_dcm.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_rd_gray_ctr.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_data_write_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_controller_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_data_path_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_dqs_delay.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_s3_ddr_iob.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_iobs_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_iobs_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_tap_dly_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_fifo_0_wr_en_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_fifo_1_wr_en_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_data_path_rst.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_controller_iobs_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_infrastructure.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_cal_ctl_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_data_path_iobs_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_top_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_top_0.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_cal_top.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_wr_gray_ctr.v
impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4_data_read_0.v
impl/spartan3an-sk/sim/ddr2sdram/ddr2_parameters.vh
impl/spartan3an-sk/sim/ddr2sdram/ddr2.v
impl/spartan3an-sk/sim/ddr2sdram/glbl.v
impl/spartan3an-sk/sim/flash-prom/m29dw323d.vhd
impl/spartan3an-sk/sim/flash-prom/utility_pack.vhd
impl/spartan3an-sk/sim/flash-prom/generic_data.vhd
/trunk/impl/spartan3an-sk/ise/netgen/par/tb.do
0,0 → 1,55
vdel -all -lib work
vlib work
 
# Hardware part
 
vlog -lint -work work zet_soc_timesim.v
 
# Simulation
 
vcom -lint -work work ../../../sim/flash-prom/generic_data.vhd ../../../sim/flash-prom/test_stub.vhd ../../../sim/flash-prom/utility_pack.vhd ../../../sim/flash-prom/m29dw323d.vhd
vlog -lint -work work +incdir+../../../rtl ../../../sim/board.v
 
 
vmap simprims /home/zeus/opt/xilinx92i/modelsim/verilog/simprims
vsim -L /home/zeus/opt/xilinx92i/modelsim/verilog/simprims -t ps work.board work.glbl
onerror {resume}
add wave -divider Clocks
add wave -radix hexadecimal /board/fpga0/cpu_clk
# add wave -radix hexadecimal /board/ddr_clk
add wave -radix hexadecimal /board/fpga0/mem_rst
add wave -divider Memory
# add wave -radix hexadecimal /board/rst
add wave -radix hexadecimal /fpga0/addr
add wave -radix hexadecimal /fpga0/wr_data
add wave -radix hexadecimal /fpga0/we
add wave -radix hexadecimal /fpga0/byte_m
add wave -radix hexadecimal /fpga0/rd_data
add wave -radix hexadecimal /fpga0/ready
add wave -divider CPU
# add wave -radix hexadecimal /fpga0/cpu0/cs
# add wave -radix hexadecimal /fpga0/cpu0/ip
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/fetch_or_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_fetch
add wave -radix hexadecimal /fpga0/cpu0/fetch0/state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/next_state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/block
# add wave -radix hexadecimal /fpga0/cpu0/fetch0/opcode
add wave -divider Flash
add wave -radix hexadecimal /board/NF_WE
add wave -radix hexadecimal /board/NF_CE
add wave -radix hexadecimal /board/NF_OE
add wave -radix hexadecimal /board/NF_BYTE
add wave -radix hexadecimal /board/NF_RP
add wave -radix hexadecimal /board/NF_A
add wave -radix hexadecimal /board/NF_D
add wave -divider Memory
add wave -radix hexadecimal -r /fpga0/mem_ctrlr_0/*
# add wave -divider VDU
# add wave -radix hexadecimal /fpga0/vdu0/*
# add wave -divider ddr2
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/sdram0/*
# add wave -divider Flash
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/flash0/*
/trunk/impl/spartan3an-sk/ise/netgen/synthesis/tb.do
0,0 → 1,56
vdel -all -lib work
vlib work
 
# Hardware part
 
vlog -lint -work work zet_soc_synthesis.v
 
# Simulation
 
vcom -lint -work work ../../../sim/flash-prom/generic_data.vhd ../../../sim/flash-prom/test_stub.vhd ../../../sim/flash-prom/utility_pack.vhd ../../../sim/flash-prom/m29dw323d.vhd
vlog -lint -work work +incdir+../../../rtl ../../../sim/board.v
 
 
vmap unisims /home/zeus/opt/xilinx92i/modelsim/verilog/unisims
vsim -L /home/zeus/opt/xilinx92i/modelsim/verilog/unisims -t ps work.board work.glbl
onerror {resume}
add wave -divider Clocks
add wave -radix hexadecimal /board/fpga0/cpu_clk
# add wave -radix hexadecimal /board/ddr_clk
add wave -radix hexadecimal /board/fpga0/mem_rst
add wave -divider Memory
# add wave -radix hexadecimal /board/rst
add wave -radix hexadecimal /fpga0/addr
add wave -radix hexadecimal /fpga0/wr_data
add wave -radix hexadecimal /fpga0/we
add wave -radix hexadecimal /fpga0/byte_m
add wave -radix hexadecimal /fpga0/rd_data
add wave -radix hexadecimal /fpga0/ready
add wave -divider CPU
# add wave -radix hexadecimal /fpga0/cpu0/cs
# add wave -radix hexadecimal /fpga0/cpu0/ip
add wave -radix hexadecimal /fpga0/cpu0/fetch0/decode0/seq_rom0/addr
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/fetch_or_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_fetch
add wave -radix hexadecimal /fpga0/cpu0/fetch0/state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/next_state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/block
# add wave -radix hexadecimal /fpga0/cpu0/fetch0/opcode
add wave -divider Flash
add wave -radix hexadecimal /board/NF_WE
add wave -radix hexadecimal /board/NF_CE
add wave -radix hexadecimal /board/NF_OE
add wave -radix hexadecimal /board/NF_BYTE
add wave -radix hexadecimal /board/NF_RP
add wave -radix hexadecimal /board/NF_A
add wave -radix hexadecimal /board/NF_D
add wave -divider Memory
add wave -radix hexadecimal -r /fpga0/mem_ctrlr_0/*
# add wave -divider VDU
# add wave -radix hexadecimal /fpga0/vdu0/*
# add wave -divider ddr2
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/sdram0/*
# add wave -divider Flash
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/flash0/*
/trunk/impl/spartan3an-sk/ise/netgen/map/tb.do
0,0 → 1,57
vdel -all -lib work
vlib work
 
# Hardware part
 
vlog -lint -work work zet_soc_map.v
 
# Simulation
 
vcom -lint -work work ../../../sim/flash-prom/generic_data.vhd ../../../sim/flash-prom/test_stub.vhd ../../../sim/flash-prom/utility_pack.vhd ../../../sim/flash-prom/m29dw323d.vhd
vlog -lint -work work +incdir+../../../rtl ../../../sim/board.v
 
 
vmap simprims /home/zeus/opt/xilinx92i/modelsim/verilog/simprims
vsim -L /home/zeus/opt/xilinx92i/modelsim/verilog/simprims -t ps work.board work.glbl
onerror {resume}
add wave -divider Clocks
add wave -radix hexadecimal /board/fpga0/cpu_clk
# add wave -radix hexadecimal /board/ddr_clk
add wave -radix hexadecimal /board/fpga0/mem_rst
add wave -divider Memory
# add wave -radix hexadecimal /board/rst
add wave -radix hexadecimal /fpga0/addr
add wave -radix hexadecimal /fpga0/wr_data
add wave -radix hexadecimal /fpga0/we
add wave -radix hexadecimal /fpga0/byte_m
add wave -radix hexadecimal /fpga0/rd_data
add wave -radix hexadecimal /fpga0/ready
add wave -divider CPU
# add wave -radix hexadecimal /fpga0/cpu0/cs
# add wave -radix hexadecimal /fpga0/cpu0/ip
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/fetch_or_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_fetch
add wave -radix hexadecimal /fpga0/cpu0/fetch0/state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/next_state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/block
# add wave -radix hexadecimal /fpga0/cpu0/fetch0/opcode
add wave -divider Flash
add wave -radix hexadecimal /board/NF_WE
add wave -radix hexadecimal /board/NF_CE
add wave -radix hexadecimal /board/NF_OE
add wave -radix hexadecimal /board/NF_BYTE
add wave -radix hexadecimal /board/NF_RP
add wave -radix hexadecimal /board/NF_A
add wave -radix hexadecimal /board/NF_D
add wave -divider Memory
add wave -radix hexadecimal -r /fpga0/mem_ctrlr_0/*
# add wave -divider VDU
# add wave -radix hexadecimal /fpga0/vdu0/*
# add wave -divider ddr2
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/sdram0/*
# add wave -divider Flash
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/flash0/*
 
run 1100ns
/trunk/impl/spartan3an-sk/ise/netgen/translate/tb.do
0,0 → 1,55
vdel -all -lib work
vlib work
 
# Hardware part
 
vlog -lint -work work zet_soc_translate.v
 
# Simulation
 
vcom -lint -work work ../../../sim/flash-prom/generic_data.vhd ../../../sim/flash-prom/test_stub.vhd ../../../sim/flash-prom/utility_pack.vhd ../../../sim/flash-prom/m29dw323d.vhd
vlog -lint -work work +incdir+../../../rtl ../../../sim/board.v
 
 
vmap simprims /home/zeus/opt/xilinx92i/modelsim/verilog/simprims
vsim -L /home/zeus/opt/xilinx92i/modelsim/verilog/simprims -t ps work.board work.glbl
onerror {resume}
add wave -divider Clocks
add wave -radix hexadecimal /board/fpga0/cpu_clk
# add wave -radix hexadecimal /board/ddr_clk
add wave -radix hexadecimal /board/fpga0/mem_rst
add wave -divider Memory
# add wave -radix hexadecimal /board/rst
add wave -radix hexadecimal /fpga0/addr
add wave -radix hexadecimal /fpga0/wr_data
add wave -radix hexadecimal /fpga0/we
add wave -radix hexadecimal /fpga0/byte_m
add wave -radix hexadecimal /fpga0/rd_data
add wave -radix hexadecimal /fpga0/ready
add wave -divider CPU
# add wave -radix hexadecimal /fpga0/cpu0/cs
# add wave -radix hexadecimal /fpga0/cpu0/ip
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/fetch_or_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_exec
add wave -radix hexadecimal /fpga0/cpu0/addr_fetch
add wave -radix hexadecimal /fpga0/cpu0/fetch0/state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/next_state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/block
# add wave -radix hexadecimal /fpga0/cpu0/fetch0/opcode
add wave -divider Flash
add wave -radix hexadecimal /board/NF_WE
add wave -radix hexadecimal /board/NF_CE
add wave -radix hexadecimal /board/NF_OE
add wave -radix hexadecimal /board/NF_BYTE
add wave -radix hexadecimal /board/NF_RP
add wave -radix hexadecimal /board/NF_A
add wave -radix hexadecimal /board/NF_D
add wave -divider Memory
add wave -radix hexadecimal -r /fpga0/mem_ctrlr_0/*
# add wave -divider VDU
# add wave -radix hexadecimal /fpga0/vdu0/*
# add wave -divider ddr2
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/sdram0/*
# add wave -divider Flash
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/flash0/*
/trunk/impl/spartan3an-sk/ise/zet_soc_import.tcl
0,0 → 1,1271
# ProjectNavigator SourceControl recreation script
#
# This script is text version of significant (but possibly not all)
# the information contained in the ISE project file. It is generated
# and used by the ProjectNavigator application's source control
# import feature.
#
# When using this script from the command line to recreate the ISE
# project, it should first be sourced from within an xtclsh shell.
# Next, the import procedure should be called to perform the import.
# When calling the import procedure, pass the new project directory
# and the source directory. If neither are specified, the current
# working directory is assumed for both.
#
# Internally this script has two file lists. One variable (import_files)
# has the set of files to copy into the project directory. The other
# variable (user_files) has the set of files to add into the project.
#
#
# This script is not intended for direct customer editing.
#
# Copyright 2006, Xilinx, Inc.
#
 
 
# Helper to copy files from the source staging area
# back into the destination work area.
# This proc will be call for each file copied.
# While not supported, one could do interesting things with this
# proc, since each file hits it.
proc CopyIn { srcfile work_area copy_option } {
set staging_area [pwd]
if { [ expr { [ file pathtype $srcfile ] == "absolute" || \
[string index $srcfile 0 ] == "/" || \
[string index $srcfile 1 ] == ":" } ] } {
set workfile $srcfile
} else {
set workfile [ file join $work_area $srcfile ]
}
if { $copy_option == "flatten" } {
set stagefile [ file join $staging_area [ file tail $srcfile ] ]
} elseif { [ file pathtype $srcfile ] != "relative" } {
set srcfile [ string map {: _} $srcfile ]
set stagefile [ file join $staging_area absolute $srcfile ]
} elseif { [ expr { $copy_option == "absremote" } && { [string equal -length 2 $srcfile ".." ] } ] } {
set stagefile [ file join $staging_area outside_relative [ string map {.. up} $srcfile ] ]
} else {
set srcfile [ string map {: _} $srcfile ]
set stagefile [ file join $staging_area $srcfile ]
}
 
set stagefile [ file normalize $stagefile ]
set workfile [ file normalize $workfile ]
 
if { [ file exists $stagefile ] } {
if { $stagefile != $workfile } {
file mkdir [ file dirname $workfile ]
file copy -force $stagefile $workfile
}
} else { WARN "\"$stagefile\" does not exist for import copy." }
}
 
proc ERR { msg } {
puts "ERROR: $msg"
}
 
proc WARN { msg } {
puts "WARNING: $msg"
}
 
proc INFO { msg } {
puts "$msg"
}
 
# Helper that returns 1 if the string is blank, otherwise 0.
proc IsBlank { str } {
if { [string length $str] == 0 } {
return 1
}
return 0
}
 
# Helper for determining whether a value is 'NULL'.
# Returns 1 if the value is 0; returns 0 if the value is anything else.
proc IsNull { val } {
if { $val == 0 } {
return 1
}
return 0
}
 
proc HandleException { script { msg "" } } {
set catch_result [catch {
uplevel 1 $script
} RESULT]
if {$catch_result} {
if {![IsBlank $msg]} {
ERR $msg
}
INFO "$RESULT"
INFO "$::errorInfo"
}
}
 
# These two procs help to load shared libraries in a platform
# independent way.
proc _LoadLibrary {name} {
set libExt [info sharedlibextension]
set libFullName "$name$libExt"
HandleException {
load $libFullName
} "A problem occured loading library $libFullName."
}
 
proc _LoadFactoryLibrary {Factory} {
HandleException {
Xilinx::Cit::FactoryLoad $Factory
} "A problem occured loading library $Factory."
}
 
_LoadLibrary libCit_CoreStub
_LoadLibrary libPrjrep_CommonStub
_LoadFactoryLibrary libPrjrep_Common
_LoadLibrary libDpm_SupportStub
_LoadLibrary libDpm_PnfStub
_LoadLibrary libDpm_DefnDataStub
_LoadLibrary libDpm_DesignDataStub
_LoadLibrary libDpm_HdlStub
_LoadLibrary libPrjrep_RepositoryStub
_LoadLibrary libCitI_CoreStub
_LoadLibrary libHdcI_HdcHDProjectStub
_LoadLibrary libTcltaskI_TaskStub
_LoadLibrary libCommonI_CommonStub
_LoadFactoryLibrary libTcltask_Helpers
_LoadFactoryLibrary libHdcC_HDProject
_LoadLibrary libHdcI_HdcContainerStub
 
# Helper to exectute code only when the (pointer) variable name is valid.
proc OnOkPtr { var_name script } {
if { [ uplevel info exists $var_name ] } {
upvar $var_name var
if { $var != 0 } { return [ uplevel $script ] }
}
}
 
# Helper to exectute code only when the (pointer) variable name is 0.
proc OnNullPtr { var_name script } {
if { [ uplevel info exists $var_name ] } {
upvar $var_name var
if { $var == 0 } { return [ uplevel $script ] }
}
}
 
# Helper to exectute code only when the value of variable name is 1.
proc OnSuccess { var_name script } {
if { $val != 0 } { return [ uplevel $script ] }
}
 
# Helper to exectute code only when the value of variable name is 0.
proc OnFail { val script } {
if { $val != 1 } { return [ uplevel $script ] }
}
 
# Helper to get a component interface.
proc GetInterface { iUnk id { name "" } } {
if {$iUnk == 0} { return 0 }
set iIface [ $iUnk GetInterface $id ]
OnNullPtr iIface {
if {![IsBlank $name]} {
ERR " Could not get the \"$name\" interface."
}
}
return $iIface
}
 
# Helper to create a component and return one of its interfaces.
proc CreateComponent { compId ifaceId { name "" } } {
set iUnk [ ::Xilinx::Cit::FactoryCreate $compId ]
set iIface [ GetInterface $iUnk $ifaceId ]
OnNullPtr iIface {
if {![IsBlank $name]} { ERR "Could not create a \"$name\" component." }
}
return $iIface
}
 
# Helper to release an object
proc Release { args } {
foreach iUnk $args {
set i_refcount [ GetInterface $iUnk $::xilinx::Prjrep::IRefCountID ]
OnNullPtr i_refcount { set i_refcount [ GetInterface $iUnk $::xilinx::CommonI::IRefCountID ] }
OnOkPtr i_refcount { $i_refcount Release }
}
}
 
# Helper to loop over IIterator based pointers.
proc ForEachIterEle { _ele_var_name _iter script } {
if {$_iter == 0} { return 0 }
upvar $_ele_var_name ele
for { $_iter First } { ![ $_iter IsEnd ] } { $_iter Next } {
set ele [ $_iter CurrentItem ]
set returned_val [ uplevel $script ]
}
}
 
# Helper to get the Tcl Project Manager, if possible.
proc GetTclProjectMgr { } {
set TclProjectMgrId "{7d528480-1196-4635-aba9-639446e4aa59}"
set iUnk [ Xilinx::CitP::CreateComponent $TclProjectMgrId ]
if {$iUnk == 0} { return 0 }
set iTclProjectMgr [ $iUnk GetInterface $::xilinx::TcltaskI::ITclProjectMgrID ]
OnNullPtr iTclProjectMgr {
ERR "Could not create a \"TclProjectMgr\" component."
}
return $iTclProjectMgr
}
 
# Helper to get the current Tcl Project, if one is open.
proc GetCurrentTclProject { } {
set iTclProject 0
set iTclProjectMgr [GetTclProjectMgr]
OnOkPtr iTclProjectMgr {
set errmsg ""
$iTclProjectMgr GetCurrentTclProject iTclProject errmsg
}
return $iTclProject
}
 
# Helper to get the current HDProject, if one is open.
proc GetCurrentHDProject { } {
set iHDProject 0
set iTclProjectMgr [GetTclProjectMgr]
set errmsg ""
OnOkPtr iTclProjectMgr { $iTclProjectMgr GetCurrentHDProject iHDProject errmsg }
OnNullPtr iHDProject {
ERR "Could not get the current HDProject."
}
return $iHDProject
}
 
# Helper to create a Project Helper.
proc GetProjectHelper { } {
set ProjectHelperID "{0725c3d2-5e9b-4383-a7b6-a80c932eac21}"
set iProjHelper [CreateComponent $ProjectHelperID $::xilinx::Dpm::IProjectHelperID "Project Helper"]
return $iProjHelper
}
 
# Helper to find out if a project is currently open.
# Returns 1 if a project is open, otherwise 0.
proc IsProjectOpen { } {
set iTclProject [GetCurrentTclProject]
set isOpen [expr {$iTclProject != 0}]
Release $iTclProject
return $isOpen
}
 
# Helper to return the lock file for the specified project if there is one.
# Returns an empty string if there is no lock file on the specified project,
# or there is no corresponding .ise file
# This assumes that the project_file is in the current directory.
# It also assumes project_file does not have a path.
proc GetProjectLockFile { project_file } {
if { ![ file isfile "$project_file" ] } {
return
}
INFO "Checking for a lock file for \"$project_file\"."
set lock_file "__ISE_repository_${project_file}_.lock"
if { [ file isfile "$lock_file" ] } {
return $lock_file
}
return
}
 
# Helper to back up the project file.
# This assumes that the project_file is in the current directory.
proc BackUpProject { project_file backup_file } {
if { ![ file isfile "$project_file" ] } {
WARN "Could not find \"$project_file\"; the project will not be backed up."
return 0
} else {
INFO "Backing up the project to \"$backup_file\"."
file copy -force "$project_file" "$backup_file"
}
return 1
}
 
# Helper to remove the project file so that a new project can be created
# in its place. Presumably the old project is corrupted and can no longer
# be opened.
proc RemoveProject { project_file } {
file delete -force "$project_file"
# Return failure if the project still exists.
if { [ file isfile "$project_file" ] } {
ERR "Could not remove \"$project_file\"; Unable to restore the project."
return 0
}
return 1
}
 
# Helper to open a project and return a project facilitator (pointer).
proc OpenFacilProject { project_name } {
# first make sure the tcl project mgr singleton exists
GetTclProjectMgr
# get a Project Helper and open the project.
set iProjHelper [GetProjectHelper]
if {$iProjHelper == 0} { return 0 }
set result [$iProjHelper Open $project_name]
OnFail $result {
if {$result == 576460769483292673} {
ERR "Could not open the project \"$project_name\" because it is locked."
} else {
ERR "Could not open the \"$project_name\" project."
}
Release $iProjHelper
set iProjHelper 0
}
return $iProjHelper
}
 
# Helper to close and release a project.
proc CloseFacilProject { iProjHelper } {
if {$iProjHelper == 0} { return }
$iProjHelper Close
Release $iProjHelper
}
 
# Helper to get the Project from the Project Helper.
# Clients must release this.
proc GetProject { iProjHelper } {
if {$iProjHelper == 0} { return 0 }
set dpm_project 0
$iProjHelper GetDpmProject dpm_project
set iProject [ GetInterface $dpm_project $xilinx::Dpm::IProjectID ]
OnNullPtr iProject {
ERR "Could not get the Project from the Project Helper."
}
return $iProject
}
 
# Helper to get the File Manager from the Project Helper.
# Clients must release this.
proc GetFileManager { iProjHelper } {
set iProject [GetProject $iProjHelper]
set iFileMgr [ GetInterface $iProject $xilinx::Dpm::IFileManagerID ]
OnNullPtr iFileMgr {
ERR "Could not get the File Manager from the Project Helper."
}
# Don't release the project here, clients will release it
# when they release its IFileManager interface.
return $iFileMgr
}
 
# Helper to get the Source Library Manager from the Project Helper.
# Clients must release this.
proc GetSourceLibraryManager { iProjHelper } {
set iProject [GetProject $iProjHelper]
set iSourceLibraryMgr [ GetInterface $iProject $xilinx::Dpm::ISourceLibraryManagerID ]
OnNullPtr iSourceLibraryMgr {
ERR "Could not get the Source Library Manager from the Project Helper."
}
# Don't release the project here, clients will release it
# when they release its IFileManager interface.
return $iSourceLibraryMgr
}
 
# Helper to get the ProjSrcHelper from the Project Helper.
# Clients must NOT release this.
proc GetProjSrcHelper { iProjHelper } {
set iSrcHelper [ GetInterface $iProjHelper $::xilinx::Dpm::IProjSrcHelperID IProjSrcHelper ]
OnNullPtr iSrcHelper {
ERR "Could not get the ProjSrcHelper from the Project Helper."
}
return $iSrcHelper
}
 
# Helper to get the ScratchPropertyManager from the Project Helper.
# Clients must NOT release this.
proc GetScratchPropertyManager { iProjHelper } {
set iPropTableFetch [ GetInterface $iProjHelper $xilinx::Dpm::IPropTableFetchID IPropTableFetch ]
set prop_table_comp 0
OnOkPtr iPropTableFetch {
$iPropTableFetch GetPropTable prop_table_comp
}
set iScratch [ GetInterface $prop_table_comp $xilinx::Dpm::IScratchPropertyManagerID ]
OnNullPtr iScratch {
ERR "Could not get the Scratch Property Manager from the Project Helper."
}
return $iScratch
}
 
# Helper to get the Design from the Project Helper.
# Clients must release this.
proc GetDesign { iProjHelper } {
set iProject [GetProject $iProjHelper]
set iDesign 0
OnOkPtr iProject { $iProject GetDesign iDesign }
OnNullPtr iDesign {
ERR "Could not get the Design from the Project Helper."
}
Release $iProject
return $iDesign
}
 
# Helper to get the Data Store from the Project Helper.
# Clients must NOT release this.
proc GetDataStore { iProjHelper } {
set iDesign [ GetDesign $iProjHelper]
set iDataStore 0
OnOkPtr iDesign { $iDesign GetDataStore iDataStore }
OnNullPtr iDataStore {
ERR "Could not get the Data Store from the Project Helper."
}
Release $iDesign
return $iDataStore
}
 
# Helper to get the View Manager from the Project Helper.
# Clients must NOT release this.
proc GetViewManager { iProjHelper } {
set iDesign [ GetDesign $iProjHelper]
set iViewMgr [ GetInterface $iDesign $xilinx::Dpm::IViewManagerID ]
OnNullPtr iViewMgr {
ERR "Could not get the View Manager from the Project Helper."
}
# Don't release the design here, clients will release it
# when they release its IViewManager interface.
return $iViewMgr
}
 
# Helper to get the Property Manager from the Project Helper.
# Clients must release this.
proc GetPropertyManager { iProjHelper } {
set iDesign [ GetDesign $iProjHelper]
set iPropMgr 0
OnOkPtr iDesign { $iDesign GetPropertyManager iPropMgr }
OnNullPtr iPropMgr {
ERR "Could not get the Property Manager from the Project Helper."
}
Release $iDesign
return $iPropMgr
}
 
# Helper to find a property template, based on prop_name
# Clients must NOT release this.
proc GetPropertyTemplate { iProjHelper prop_name } {
set iPropTempl 0
set iUnk 0
set iDefdataId 0
set iPropTemplStore 0
set iDataStore [GetDataStore $iProjHelper]
OnOkPtr iDataStore { $iDataStore GetComponentByName $prop_name iUnk }
OnOkPtr iUnk { set iDefdataId [ GetInterface $iUnk $xilinx::Dpm::IDefDataIdID IDefDataId ] }
OnOkPtr iDefdataId {
set iPropTemplStore [ GetInterface $iDataStore $xilinx::Dpm::IPropertyTemplateStoreID IPropertyTemplateStore ]
}
OnOkPtr iPropTemplStore { $iPropTemplStore GetPropertyTemplate $iDefdataId iPropTempl }
OnNullPtr iPropTempl {
WARN "Could not get the property template for \"$prop_name\"."
}
return $iPropTempl
}
 
# Helper to get a component's name.
proc GetName { iUnk } {
set name ""
set iName [ GetInterface $iUnk $xilinx::Prjrep::INameID IName ]
OnOkPtr iName { $iName GetName name }
return $name
}
 
# Helper to get the name of a view's type.
proc GetViewTypeName { iView } {
set typeName ""
set iType 0
set iDefdataType 0
OnOkPtr iView { $iView GetType iType }
OnOkPtr iType {
set iDefdataType [ GetInterface $iType $xilinx::Dpm::IDefDataIdID IDefDataId ]
}
OnOkPtr iDefdataType { $iDefdataType GetID typeName }
return $typeName
}
 
# Helper to find a view and return its context.
# Must clients release this?
proc GetViewContext { iProjHelper view_id view_name } {
# Simply return if the view_id or view_name is empty.
if { [IsBlank $view_id] || [IsBlank $view_name] } { return 0 }
set foundview 0
set viewiter 0
set iViewMgr [GetViewManager $iProjHelper]
OnOkPtr iViewMgr { $iViewMgr GetViews viewiter }
ForEachIterEle view $viewiter {
set typeName [GetViewTypeName $view]
set name [GetName $view]
if { [ string equal $name $view_name ] && [ string equal $view_id $typeName ] } {
set foundview $view
}
}
set context [ GetInterface $foundview $xilinx::Dpm::IPropertyContextID ]
OnNullPtr context {
WARN "Could not get the context for view \"$view_id\":\"$view_name\"."
}
return $context
}
 
# Helper to get a string property instance from the property manager.
proc GetStringPropertyInstance { iProjHelper simple_id } {
set iPropMgr [GetPropertyManager $iProjHelper]
if {$iPropMgr == 0} { return 0 }
set iPropInst 0
$iPropMgr GetStringProperty $simple_id iPropInst
OnNullPtr iPropInst { WARN "Could not get the string property instance $simple_id." }
Release $iPropMgr
return $iPropInst
}
 
# Helper to get a property instance from the property manager.
proc GetPropertyInstance { iProjHelper view_name view_id prop_name } {
set iPropInst 0
set iPropTempl [ GetPropertyTemplate $iProjHelper $prop_name ]
if {$iPropTempl == 0} { return 0 }
set context [ GetViewContext $iProjHelper $view_id $view_name ]
set iPropMgr [GetPropertyManager $iProjHelper]
if {$iPropMgr == 0} { return 0 }
$iPropMgr GetPropertyInstance $iPropTempl $context iPropInst
OnNullPtr iPropInst {
if { ![IsBlank $view_id] && ![IsBlank $view_name] } {
WARN "Could not get the context sensitive property instance $prop_name."
} else {
WARN "Could not get the property instance $prop_name."
}
}
Release $iPropMgr
return $iPropInst
}
 
# Helper to store properties back into the property manager.
proc RestoreProcessProperties { iProjHelper process_props } {
INFO "Restoring process properties"
foreach { unused view_name view_id simple_id prop_name prop_val } $process_props {
set iPropInst 0
if {![IsBlank $simple_id]} {
set iPropInst [ GetStringPropertyInstance $iProjHelper $simple_id ]
} else {
set iPropInst [ GetPropertyInstance $iProjHelper $view_name $view_id $prop_name ]
}
OnOkPtr iPropInst {
OnFail [ $iPropInst SetStringValue "$prop_val" ] {
WARN "Could not set the value of the $prop_name property to \"$prop_val\"."
}
}
Release $iPropInst
}
}
 
# Helper to recreate partitions from the variable name with
# a list of instance names.
proc RestorePartitions { namelist } {
INFO "Restoring partitions."
set iHDProject [ GetCurrentHDProject ]
OnOkPtr iHDProject {
foreach name $namelist {
set iPartition [ $iHDProject CreatePartition "$name" ]
}
}
}
 
# Helper to create and populate a library
#
proc CreateLibrary { iProjHelper libname filelist } {
 
set iLibMgr [ GetSourceLibraryManager $iProjHelper ]
set iFileMgr [ GetFileManager $iProjHelper ]
 
if {$iLibMgr == 0} { return 0 }
if {$iFileMgr == 0} { return 0 }
 
$iLibMgr CreateSourceLibrary "libname" ilib
 
OnOkPtr ilib {
foreach filename $filelist {
set argfile [ file normalize "$filename" ]
set found 0
set fileiter 0
$iFileMgr GetFiles fileiter
ForEachIterEle ifile $fileiter {
set path ""
set file ""
$ifile getPath path file
set currentfile [ file normalize [ file join "$path" "$file" ] ]
if { $currentfile == $argfile } {
set found 1
$ilib AddFile ifile
break
}
}
OnNullPtr found {
WARN "Could not add the file \"$filename\" to the library \"$libname\"."
}
}
}
}
 
# Helper to create source libraries and populate them.
proc RestoreSourceLibraries { iProjHelper libraries } {
INFO "Restoring source libraries."
foreach { libname filelist } $libraries {
CreateLibrary $iProjHelper "$libname" $filelist
}
}
 
# Helper to add user files to the project using the PnF.
proc AddUserFiles { iProjHelper files } {
INFO "Adding User files."
set iconflict 0
set iSrcHelper [ GetProjSrcHelper $iProjHelper ]
if {$iSrcHelper == 0} { return 0 }
foreach filename $files {
INFO "Adding the file \"$filename\" to the project."
set result [$iSrcHelper AddSourceFile "$filename" iconflict]
OnFail $result {
if {$result == 6} {
INFO "The file \"$filename\" is already in the project."
} else {
ERR "A problem occurred adding the file \"$filename\" to the project."
}
}
}
}
 
# Helper to add files to the project and set their origination.
# Valid origination values are:
# 0 - User
# 1 - Generated
# 2 - Imported
# Files of origination "User" are added through the facilitator,
# otherwise they are added directly to the File Manager.
proc AddImportedFiles { iProjHelper files origination } {
switch $origination {
0 { INFO "Adding User files." }
1 { INFO "Adding Generated files." }
2 { INFO "Adding Imported files." }
default {
ERR "Invalid parameter: origination was set to \"$origination\", but may only be 0, 1, or 2."
return 0
}
}
set iFileMgr [ GetFileManager $iProjHelper ]
if {$iFileMgr == 0} { return 0 }
foreach filename $files {
set file_type 0
set hdl_file 0
set result [$iFileMgr AddFile "$filename" $file_type hdl_file]
OnFail $result {
if {$result == 6} {
INFO "The file \"$filename\" is already in the project."
} elseif { $hdl_file == 0 } {
ERR "A problem occurred adding the file \"$filename\" to the project."
}
}
OnOkPtr hdl_file {
set ifile [ GetInterface $hdl_file $xilinx::Dpm::IFileID IFile ]
OnOkPtr ifile {
set result [ $ifile SetOrigination $origination ]
if {$result != 1} {
ERR "A problem occurred setting the origination of \"$filename\" to \"$origination\"."
}
Release $ifile
}
}
}
return 1
}
 
proc RestoreProjectSettings { iProjHelper project_settings } {
INFO "Restoring device settings"
set iScratch [GetScratchPropertyManager $iProjHelper]
set iPropIter 0
set iPropSet [ GetInterface $iScratch $xilinx::Dpm::IPropertyNodeSetID IPropertyNodeSet ]
OnOkPtr iPropSet {
$iPropSet GetIterator iPropIter
}
set index 0
set lastindex [llength $project_settings]
ForEachIterEle prop_node $iPropIter {
set prop_instance 0
$prop_node GetPropertyInstance prop_instance
if { $index < $lastindex } {
set argname [ lindex $project_settings $index ]
set argvalue [ lindex $project_settings [ expr $index + 1 ] ]
} else {
set argname {}
set argvalue {}
}
if { $prop_instance != 0 } {
set name {}
$prop_instance GetName name
if { [string equal $name $argname ] } {
$prop_instance SetStringValue $argvalue
incr index
incr index
}
}
Release $prop_instance
}
$iScratch Commit
# initialize
$iProjHelper Init
}
 
# Helper to load a source control configuration from a stream
# and then store it back into an ise file.
proc RestoreSourceControlOptions { prjfile istream } {
INFO "Restoring source control options"
set config_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlConfigurationCompID ]
OnOkPtr config_comp { set ipersist [ $config_comp GetInterface $xilinx::Prjrep::IPersistID ] }
OnOkPtr config_comp { set igetopts [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IGetOptionsID ] }
set helper_comp [::Xilinx::Cit::FactoryCreate $::xilinx::Dpm::SourceControlHelpCompID ]
OnOkPtr helper_comp { set ihelper [ $config_comp GetInterface $xilinx::Dpm::SrcCtrl::IHelperID ] }
OnOkPtr ipersist { $ipersist Load istream }
OnOkPtr ihelper { OnOkPtr igetopts { $ihelper SaveOptions $prjfile $igetopts } }
Release $helper_comp $config_comp
}
 
proc import { {working_area ""} {staging_area ""} { srcctrl_comp 0 } } {
set project_file "zet_soc.ise"
set old_working_dir [pwd]
# intialize the new project directory (work) and
# source control reference directory (staging) to
# current working directory, when not specified
if { $working_area == "" } { set working_area [pwd] }
if { $staging_area == "" } { set staging_area [pwd] }
set copy_option relative
set import_files {
"../../../../opt/altera7.1/modeltech/bin"
"../../../rtl-model/alu.v"
"../../../rtl-model/cpu.v"
"../../../rtl-model/defines.v"
"../../../rtl-model/exec.v"
"../../../rtl-model/fetch.v"
"../../../rtl-model/jmp_cond.v"
"../../../rtl-model/regfile.v"
"../../../rtl-model/rom_def.v"
"../../../rtl-model/util/primitives.v"
"../rtl/ddr2cntrl/ddr2sdram.v"
"../rtl/ddr2cntrl/vlog_xst_bl4.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_1.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_cal_ctl_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_cal_top.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_clk_dcm.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_controller_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_controller_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_path_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_path_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_path_rst.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_read_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_read_controller_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_write_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_ddr2_dm_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_dqs_delay.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_fifo_0_wr_en_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_fifo_1_wr_en_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_top_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_rd_gray_ctr.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_s3_ddr_iob.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_s3_dqs_iob.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_tap_dly_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_top_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_wr_gray_ctr.v"
"../rtl/flash-prom/flashcntrlr.v"
"../rtl/memory.v"
"../rtl/vga/char_rom_b16.v"
"../rtl/vga/ram2k_b16.v"
"../rtl/vga/ram2k_b16_attr.v"
"../rtl/vga/vdu.v"
"../rtl/zet_soc.v"
"xst"
"zet_soc.ucf"
"zet_soc_guide.ncd"}
INFO "Copying files from \"$staging_area\" to \"$working_area\""
# Must be in the staging directory before calling CopyIn.
cd [file normalize "$staging_area"]
foreach file $import_files {
CopyIn "$file" "$working_area" $copy_option
}
set iProjHelper 0
# Bail if a project currently open.
if {[IsProjectOpen]} {
ERR "The project must be closed before performing this operation."
return 0
}
# Must be in the working area (i.e. project directory) before calling recreating the project.
cd [file normalize "$working_area"]
INFO "Recreating project \"$project_file\"."
HandleException {
set iProjHelper [ OpenFacilProject "$project_file"]
} "A problem occurred while creating the project \"$project_file\"."
if {$iProjHelper == 0} {
cd "$old_working_dir"
return 0
}
set project_settings {
"PROP_DevFamily" "Spartan3A and Spartan3AN"
"PROP_DevDevice" "xc3s700an"
"PROP_DevPackage" "fgg484"
"PROP_DevSpeed" "-4"
"PROP_Top_Level_Module_Type" "HDL"
"PROP_Synthesis_Tool" "XST (VHDL/Verilog)"
"PROP_Simulator" "Modelsim-SE Verilog"
"PROP_PreferredLanguage" "Verilog"
"PROP_Enable_Message_Capture" "true"
"PROP_Enable_Message_Filtering" "false"
"PROP_Enable_Incremental_Messaging" "false"
}
 
HandleException {
RestoreProjectSettings $iProjHelper $project_settings
} "A problem occured while restoring project settings."
 
set user_files {
"../../../rtl-model/alu.v"
"../../../rtl-model/cpu.v"
"../../../rtl-model/defines.v"
"../../../rtl-model/exec.v"
"../../../rtl-model/fetch.v"
"../../../rtl-model/jmp_cond.v"
"../../../rtl-model/regfile.v"
"../../../rtl-model/rom_def.v"
"../../../rtl-model/util/primitives.v"
"../rtl/ddr2cntrl/ddr2sdram.v"
"../rtl/ddr2cntrl/vlog_xst_bl4.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_1.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_cal_ctl_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_cal_top.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_clk_dcm.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_controller_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_controller_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_path_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_path_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_path_rst.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_read_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_read_controller_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_data_write_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_ddr2_dm_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_dqs_delay.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_fifo_0_wr_en_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_fifo_1_wr_en_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_top_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_iobs_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_rd_gray_ctr.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_s3_ddr_iob.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_s3_dqs_iob.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_tap_dly_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_top_0.v"
"../rtl/ddr2cntrl/vlog_xst_bl4_wr_gray_ctr.v"
"../rtl/flash-prom/flashcntrlr.v"
"../rtl/memory.v"
"../rtl/vga/char_rom_b16.v"
"../rtl/vga/ram2k_b16.v"
"../rtl/vga/ram2k_b16_attr.v"
"../rtl/vga/vdu.v"
"../rtl/zet_soc.v"
"zet_soc.ucf"}
 
HandleException {
AddUserFiles $iProjHelper $user_files
} "A problem occured while restoring user files."
 
set imported_files {
"zet_soc_guide.ncd"}
 
set origination 2
 
HandleException {
AddImportedFiles $iProjHelper $imported_files $origination
} "A problem occured while restoring imported files."
 
set process_props {
"A" "" "" "" "PROPEXT_SynthMultStyle_virtex2" "Auto"
"A" "" "" "" "PROPEXT_xilxBitgCfg_Rate_spartan3a" "25"
"A" "" "" "" "PROPEXT_xilxMapGenInputK_virtex2" "4"
"A" "" "" "" "PROPEXT_xilxSynthAddBufg_spartan3e" "24"
"A" "" "" "" "PROPEXT_xilxSynthMaxFanout_virtex2" "500"
"A" "" "" "" "PROP_CompxlibOtherCompxlibOpts" ""
"A" "" "" "" "PROP_CompxlibOutputDir" "$XILINX/<language>/<simulator>"
"A" "" "" "" "PROP_CompxlibOverwriteLib" "Overwrite"
"A" "" "" "" "PROP_CompxlibSimPrimatives" "true"
"A" "" "" "" "PROP_CompxlibXlnxCoreLib" "true"
"A" "" "" "" "PROP_CurrentFloorplanFile" ""
"A" "" "" "" "PROP_DesignName" "zet_soc"
"A" "" "" "" "PROP_Dummy" "dum1"
"A" "" "" "" "PROP_Enable_Incremental_Messaging" "false"
"A" "" "" "" "PROP_Enable_Message_Capture" "true"
"A" "" "" "" "PROP_Enable_Message_Filtering" "false"
"A" "" "" "" "PROP_FitterReportFormat" "HTML"
"A" "" "" "" "PROP_FlowDebugLevel" "0"
"A" "" "" "" "PROP_ImpactProjectFile" ""
"A" "" "" "" "PROP_MSimSDFTimingToBeRead" "Setup Time"
"A" "" "" "" "PROP_ModelSimUseConfigName" "false"
"A" "" "" "" "PROP_Parse_Target" "synthesis"
"A" "" "" "" "PROP_PartitionCreateDelete" ""
"A" "" "" "" "PROP_PartitionForcePlacement" ""
"A" "" "" "" "PROP_PartitionForceSynth" ""
"A" "" "" "" "PROP_PartitionForceTranslate" ""
"A" "" "" "" "PROP_PostTrceFastPath" "false"
"A" "" "" "" "PROP_PreTrceFastPath" "false"
"A" "" "" "" "PROP_SimDo" "true"
"A" "" "" "" "PROP_SimModelGenerateTestbenchFile" "false"
"A" "" "" "" "PROP_SimModelInsertBuffersPulseSwallow" "false"
"A" "" "" "" "PROP_SimModelOtherNetgenOpts" ""
"A" "" "" "" "PROP_SimModelRetainHierarchy" "true"
"A" "" "" "" "PROP_SimUseCustom_behav" "false"
"A" "" "" "" "PROP_SimUseCustom_postMap" "false"
"A" "" "" "" "PROP_SimUseCustom_postPar" "false"
"A" "" "" "" "PROP_SimUseCustom_postXlate" "false"
"A" "" "" "" "PROP_SynthCaseImplStyle" "None"
"A" "" "" "" "PROP_SynthDecoderExtract" "true"
"A" "" "" "" "PROP_SynthEncoderExtract" "Yes"
"A" "" "" "" "PROP_SynthExtractMux" "Yes"
"A" "" "" "" "PROP_SynthExtractRAM" "true"
"A" "" "" "" "PROP_SynthExtractROM" "true"
"A" "" "" "" "PROP_SynthFsmEncode" "Auto"
"A" "" "" "" "PROP_SynthLogicalShifterExtract" "true"
"A" "" "" "" "PROP_SynthOpt" "Speed"
"A" "" "" "" "PROP_SynthOptEffort" "Normal"
"A" "" "" "" "PROP_SynthResSharing" "true"
"A" "" "" "" "PROP_SynthShiftRegExtract" "true"
"A" "" "" "" "PROP_SynthXORCollapse" "true"
"A" "" "" "" "PROP_Top_Level_Module_Type" "HDL"
"A" "" "" "" "PROP_UserConstraintEditorPreference" "Constraints Editor"
"A" "" "" "" "PROP_UserEditorCustomSetting" ""
"A" "" "" "" "PROP_UserEditorPreference" "ISE Text Editor"
"A" "" "" "" "PROP_XPowerOptInputTclScript" ""
"A" "" "" "" "PROP_XPowerOptLoadPCFFile" "Default"
"A" "" "" "" "PROP_XPowerOptLoadVCDFile" "Default"
"A" "" "" "" "PROP_XPowerOptLoadXMLFile" "Default"
"A" "" "" "" "PROP_XPowerOptOutputFile" "Default"
"A" "" "" "" "PROP_XPowerOptVerboseRpt" "false"
"A" "" "" "" "PROP_XPowerOtherXPowerOpts" ""
"A" "" "" "" "PROP_XplorerMode" "Off"
"A" "" "" "" "PROP_bitgen_otherCmdLineOptions" ""
"A" "" "" "" "PROP_ibiswriterShowAllModels" "false"
"A" "" "" "" "PROP_mapUseRLOCConstraints" "true"
"A" "" "" "" "PROP_map_otherCmdLineOptions" ""
"A" "" "" "" "PROP_mpprRsltToCopy" ""
"A" "" "" "" "PROP_mpprViewPadRptsForAllRslt" "true"
"A" "" "" "" "PROP_mpprViewParRptsForAllRslt" "true"
"A" "" "" "" "PROP_ngdbuildUseLOCConstraints" "true"
"A" "" "" "" "PROP_ngdbuild_otherCmdLineOptions" ""
"A" "" "" "" "PROP_parUseTimingConstraints" "true"
"A" "" "" "" "PROP_par_otherCmdLineOptions" ""
"A" "" "" "" "PROP_primeCorrelateOutput" "false"
"A" "" "" "" "PROP_primeFlatternOutputNetlist" "false"
"A" "" "" "" "PROP_primeTopLevelModule" ""
"A" "" "" "" "PROP_primetimeBlockRamData" ""
"A" "" "" "" "PROP_xilxBitgCfg_Code" "0xFFFFFFFF"
"A" "" "" "" "PROP_xilxBitgCfg_Done" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ASCIIFile" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BinaryFile" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_BitFile" "true"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_Compress" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_DRC" "true"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_EnableCRC" "true"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_IEEE1532File" "false"
"A" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack" "false"
"A" "" "" "" "PROP_xilxBitgCfg_Pgm" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_TCK" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_TDI" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_TDO" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_TMS" "Pull Up"
"A" "" "" "" "PROP_xilxBitgCfg_Unused" "Pull Down"
"A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration"
"A" "" "" "" "PROP_xilxBitgStart_Clk" "CCLK"
"A" "" "" "" "PROP_xilxBitgStart_Clk_Done" "Default (4)"
"A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false"
"A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)"
"A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)"
"A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "Default (6)"
"A" "" "" "" "PROP_xilxBitgStart_IntDone" "false"
"A" "" "" "" "PROP_xilxBitgSusWake_DriveAwakePin" "false"
"A" "" "" "" "PROP_xilxBitgSusWake_EnFilterOnInput" "true"
"A" "" "" "" "PROP_xilxBitgSusWake_EnGlblSetReset" "false"
"A" "" "" "" "PROP_xilxBitgSusWake_EnPwrOnResetDetect" "true"
"A" "" "" "" "PROP_xilxBitgSusWake_GTSCycle" "4"
"A" "" "" "" "PROP_xilxBitgSusWake_GWECycle" "5"
"A" "" "" "" "PROP_xilxBitgSusWake_WakeupClk" "Startup Clock"
"A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false"
"A" "" "" "" "PROP_xilxMapCoverMode" "Area"
"A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false"
"A" "" "" "" "PROP_xilxMapPackRegInto" "For Inputs and Outputs"
"A" "" "" "" "PROP_xilxMapReplicateLogic" "true"
"A" "" "" "" "PROP_xilxMapReportDetail" "false"
"A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false"
"A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "false"
"A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true"
"A" "" "" "" "PROP_xilxNgdbldIOPads" "false"
"A" "" "" "" "PROP_xilxNgdbldMacro" ""
"A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp"
"A" "" "" "" "PROP_xilxNgdbldPresHierarchy" "false"
"A" "" "" "" "PROP_xilxNgdbldUR" ""
"A" "" "" "" "PROP_xilxNgdbldUnexpBlks" "false"
"A" "" "" "" "PROP_xilxNgdbld_AUL" "false"
"A" "" "" "" "PROP_xilxPARplacerCostTable" "1"
"A" "" "" "" "PROP_xilxPARplacerEffortLevel" "None"
"A" "" "" "" "PROP_xilxPARrouterEffortLevel" "None"
"A" "" "" "" "PROP_xilxPARstrat" "Normal Place and Route"
"A" "" "" "" "PROP_xilxPARuseBondedIO" "false"
"A" "" "" "" "PROP_xilxPostTrceAdvAna" "false"
"A" "" "" "" "PROP_xilxPostTrceRpt" "Error Report"
"A" "" "" "" "PROP_xilxPostTrceRptLimit" "3"
"A" "" "" "" "PROP_xilxPostTrceStamp" ""
"A" "" "" "" "PROP_xilxPostTrceTSIFile" ""
"A" "" "" "" "PROP_xilxPostTrceUncovPath" ""
"A" "" "" "" "PROP_xilxPreTrceAdvAna" "false"
"A" "" "" "" "PROP_xilxPreTrceRpt" "Error Report"
"A" "" "" "" "PROP_xilxPreTrceRptLimit" "3"
"A" "" "" "" "PROP_xilxPreTrceUncovPath" ""
"A" "" "" "" "PROP_xilxSynthAddIObuf" "true"
"A" "" "" "" "PROP_xilxSynthGlobOpt" "AllClockNets"
"A" "" "" "" "PROP_xilxSynthKeepHierarchy" "No"
"A" "" "" "" "PROP_xilxSynthRegBalancing" "No"
"A" "" "" "" "PROP_xilxSynthRegDuplication" "true"
"A" "" "" "" "PROP_xstAsynToSync" "false"
"A" "" "" "" "PROP_xstAutoBRAMPacking" "false"
"A" "" "" "" "PROP_xstBRAMUtilRatio" "100"
"A" "" "" "" "PROP_xstBusDelimiter" "<>"
"A" "" "" "" "PROP_xstCase" "Maintain"
"A" "" "" "" "PROP_xstCoresSearchDir" ""
"A" "" "" "" "PROP_xstCrossClockAnalysis" "false"
"A" "" "" "" "PROP_xstEquivRegRemoval" "true"
"A" "" "" "" "PROP_xstFsmStyle" "LUT"
"A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes"
"A" "" "" "" "PROP_xstGenericsParameters" ""
"A" "" "" "" "PROP_xstHierarchySeparator" "/"
"A" "" "" "" "PROP_xstIniFile" ""
"A" "" "" "" "PROP_xstLibSearchOrder" ""
"A" "" "" "" "PROP_xstOptimizeInsPrimtives" "false"
"A" "" "" "" "PROP_xstPackIORegister" "Auto"
"A" "" "" "" "PROP_xstReadCores" "true"
"A" "" "" "" "PROP_xstSlicePacking" "true"
"A" "" "" "" "PROP_xstSliceUtilRatio" "100"
"A" "" "" "" "PROP_xstUseClockEnable" "Yes"
"A" "" "" "" "PROP_xstUseSyncReset" "Yes"
"A" "" "" "" "PROP_xstUseSyncSet" "Yes"
"A" "" "" "" "PROP_xstUseSynthConstFile" "true"
"A" "" "" "" "PROP_xstUserCompileList" ""
"A" "" "" "" "PROP_xstVeriIncludeDir_Global" ""
"A" "" "" "" "PROP_xstVerilog2001" "true"
"A" "" "" "" "PROP_xstVerilogMacros" ""
"A" "" "" "" "PROP_xstWorkDir" "./xst"
"A" "" "" "" "PROP_xstWriteTimingConstraints" "false"
"A" "" "" "" "PROP_xst_otherCmdLineOptions" ""
"A" "AutoGeneratedView" "VIEW_AbstractSimulation" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_AnalyzedDesign" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_AnnotatedPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_AnnotatedResultsModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_BehavioralSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_FPGAConfiguration" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_FPGAConfigureDevice" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_FPGAGeneratePROM" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Map" "" "PROP_SmartGuide" "false"
"A" "AutoGeneratedView" "VIEW_Map" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_Par" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_Post-MapPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-MapSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-ParSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-SynthesisAbstractSimulation" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_Post-TranslatePreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Post-TranslateSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_PreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Structural" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_TBWBehavioralSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-MapSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-ParSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPost-TranslateSimulationModelSim" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_TBWPreSimulation" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SmartGuide" "false"
"A" "AutoGeneratedView" "VIEW_Translation" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_UpdatedBitstream" "" "PROP_TopDesignUnit" ""
"A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_SmartGuide" "false"
"A" "AutoGeneratedView" "VIEW_XSTAbstractSynthesis" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "Module|zet_soc"
"A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" ""
"A" "VIEW_Initial" "VIEW_Initial" "" "PROP_TopDesignUnit" "Module|zet_soc"
"B" "" "" "" "PROP_AutoGenFile" "false"
"B" "" "" "" "PROP_DevFamily" "Spartan3A and Spartan3AN"
"B" "" "" "" "PROP_MapEffortLevel" "Medium"
"B" "" "" "" "PROP_MapLogicOptimization" "false"
"B" "" "" "" "PROP_MapPlacerCostTable" "1"
"B" "" "" "" "PROP_MapPowerReduction" "false"
"B" "" "" "" "PROP_MapRegDuplication" "false"
"B" "" "" "" "PROP_ModelSimConfigName" "Default"
"B" "" "" "" "PROP_ModelSimDataWin" "false"
"B" "" "" "" "PROP_ModelSimListWin" "false"
"B" "" "" "" "PROP_ModelSimProcWin" "false"
"B" "" "" "" "PROP_ModelSimSignalWin" "true"
"B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)"
"B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns"
"B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns"
"B" "" "" "" "PROP_ModelSimSourceWin" "false"
"B" "" "" "" "PROP_ModelSimStructWin" "true"
"B" "" "" "" "PROP_ModelSimUutInstName_postMap" "UUT"
"B" "" "" "" "PROP_ModelSimUutInstName_postPar" "UUT"
"B" "" "" "" "PROP_ModelSimVarsWin" "false"
"B" "" "" "" "PROP_ModelSimWaveWin" "true"
"B" "" "" "" "PROP_SimCustom_behav" ""
"B" "" "" "" "PROP_SimCustom_postMap" ""
"B" "" "" "" "PROP_SimCustom_postPar" ""
"B" "" "" "" "PROP_SimCustom_postXlate" ""
"B" "" "" "" "PROP_SimGenVcdFile" "false"
"B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT"
"B" "" "" "" "PROP_SimSyntax" "93"
"B" "" "" "" "PROP_SimUseExpDeclOnly" "true"
"B" "" "" "" "PROP_SimUserCompileList_behav" ""
"B" "" "" "" "PROP_Simulator" "Modelsim-SE Verilog"
"B" "" "" "" "PROP_SynthConstraintsFile" ""
"B" "" "" "" "PROP_SynthMuxStyle" "Auto"
"B" "" "" "" "PROP_SynthRAMStyle" "Auto"
"B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false"
"B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000"
"B" "" "" "" "PROP_XPowerOptUseTimeBased" "false"
"B" "" "" "" "PROP_XplorerEnableRetiming" "true"
"B" "" "" "" "PROP_XplorerNumIterations" "7"
"B" "" "" "" "PROP_XplorerOtherCmdLineOptions" ""
"B" "" "" "" "PROP_XplorerRunType" "Yes"
"B" "" "" "" "PROP_XplorerSearchPathForSource" ""
"B" "" "" "" "PROP_impactBaud" "None"
"B" "" "" "" "PROP_impactConfigMode" "None"
"B" "" "" "" "PROP_impactPort" "None"
"B" "" "" "" "PROP_mpprViewPadRptForSelRslt" ""
"B" "" "" "" "PROP_mpprViewParRptForSelRslt" ""
"B" "" "" "" "PROP_parGenAsyDlyRpt" "false"
"B" "" "" "" "PROP_parGenClkRegionRpt" "false"
"B" "" "" "" "PROP_parGenSimModel" "false"
"B" "" "" "" "PROP_parGenTimingRpt" "true"
"B" "" "" "" "PROP_parMpprNodelistFile" ""
"B" "" "" "" "PROP_parMpprParIterations" "3"
"B" "" "" "" "PROP_parMpprResultsDirectory" ""
"B" "" "" "" "PROP_parMpprResultsToSave" ""
"B" "" "" "" "PROP_parPowerReduction" "false"
"B" "" "" "" "PROP_vcom_otherCmdLineOptions" ""
"B" "" "" "" "PROP_vlog_otherCmdLineOptions" ""
"B" "" "" "" "PROP_vsim_otherCmdLineOptions" ""
"B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false"
"B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile" "false"
"B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile" "false"
"B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr" "false"
"B" "" "" "" "PROP_xilxMapPackfactor" "100"
"B" "" "" "" "PROP_xilxPAReffortLevel" "Standard"
"B" "" "" "" "PROP_xstMoveFirstFfStage" "true"
"B" "" "" "" "PROP_xstMoveLastFfStage" "true"
"B" "" "" "" "PROP_xstROMStyle" "Auto"
"B" "" "" "" "PROP_xstSafeImplement" "No"
"B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" ""
"B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" ""
"C" "" "" "" "PROP_AceActiveName" ""
"C" "" "" "" "PROP_CompxlibLang" "Verilog"
"C" "" "" "" "PROP_CompxlibSimPath" "/home/zeus/opt/altera7.1/modeltech/bin"
"C" "" "" "" "PROP_DevDevice" "xc3s700an"
"C" "" "" "" "PROP_DevFamilyPMName" "spartan3a"
"C" "" "" "" "PROP_MapExtraEffort" "None"
"C" "" "" "" "PROP_SimModelGenMultiHierFile" "false"
"C" "" "" "" "PROP_XPowerOptBaseTimeUnit" "ps"
"C" "" "" "" "PROP_XPowerOptNumberOfUnits" "1"
"C" "" "" "" "PROP_impactConfigFileName" ""
"C" "" "" "" "PROP_xilxPARextraEffortLevel" "None"
"D" "" "" "" "PROP_CompxlibUniSimLib" "true"
"D" "" "" "" "PROP_DevPackage" "fgg484"
"D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)"
"E" "" "" "" "PROP_DevSpeed" "-4"
"E" "" "" "" "PROP_PreferredLanguage" "Verilog"
"F" "" "" "" "PROP_ChangeDevSpeed" "-4"
"F" "" "" "" "PROP_SimModelTarget" "Verilog"
"F" "" "" "" "PROP_tbwTestbenchTargetLang" "Verilog"
"F" "" "" "" "PROP_xilxPostTrceSpeed" "-4"
"F" "" "" "" "PROP_xilxPreTrceSpeed" "-4"
"G" "" "" "" "PROP_PostSynthSimModelName" "zet_soc_synthesis.v"
"G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true"
"G" "" "" "" "PROP_SimModelGenArchOnly" "false"
"G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true"
"G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false"
"G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false"
"G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false"
"G" "" "" "" "PROP_SimModelNoEscapeSignal" "false"
"G" "" "" "" "PROP_SimModelOutputExtIdent" "false"
"G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure"
"G" "" "" "" "PROP_SimModelRenTopLevMod" ""
"G" "AutoGeneratedView" "VIEW_Map" "" "PROP_PostMapSimModelName" "zet_soc_map.v"
"G" "AutoGeneratedView" "VIEW_Par" "" "PROP_PostParSimModelName" "zet_soc_timesim.v"
"G" "AutoGeneratedView" "VIEW_Post-MapAbstractSimulation" "" "PROP_tbwPostMapTestbenchName" "zet_soc.map_tfw"
"G" "AutoGeneratedView" "VIEW_Post-ParAbstractSimulation" "" "PROP_tbwPostParTestbenchName" "zet_soc.timesim_tfw"
"G" "AutoGeneratedView" "VIEW_Post-TranslateAbstractSimulation" "" "PROP_tbwPostXlateTestbenchName" "zet_soc.translate_tfw"
"G" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_tbwPostMapTestbenchName" ""
"G" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_tbwPostParTestbenchName" ""
"G" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_tbwPostXlateTestbenchName" ""
"G" "AutoGeneratedView" "VIEW_Translation" "" "PROP_PostXlateSimModelName" "zet_soc_translate.v"
"H" "" "" "" "PROP_SimModelBringOutGsrNetAsAPort" "false"
"H" "" "" "" "PROP_SimModelBringOutGtsNetAsAPort" "false"
"H" "" "" "" "PROP_SimModelPathUsedInSdfAnn" "Default"
"H" "AutoGeneratedView" "VIEW_Map" "" "PROP_SimModelRenTopLevEntTo" "zet_soc"
"H" "AutoGeneratedView" "VIEW_Par" "" "PROP_SimModelRenTopLevEntTo" "zet_soc"
"H" "AutoGeneratedView" "VIEW_Structural" "" "PROP_SimModelRenTopLevEntTo" "zet_soc"
"H" "AutoGeneratedView" "VIEW_Translation" "" "PROP_SimModelRenTopLevEntTo" "zet_soc"
"I" "" "" "" "PROP_SimModelGsrPortName" "GSR_PORT"
"I" "" "" "" "PROP_SimModelGtsPortName" "GTS_PORT"
"I" "" "" "" "PROP_SimModelRocPulseWidth" "100"
"I" "" "" "" "PROP_SimModelTocPulseWidth" "0"}
 
HandleException {
RestoreProcessProperties $iProjHelper $process_props
} "A problem occured while restoring process properties."
 
# library names and their members
set libraries {
}
 
HandleException {
RestoreSourceLibraries $iProjHelper $libraries
} "A problem occured while restoring source libraries."
 
# partition names for recreation
set partition_names {
}
 
HandleException {
RestorePartitions $partition_names
} "A problem occured while restoring partitions."
 
set opts_stream [ [Xilinx::Cit::FactoryCreate $::xilinx::Dpm::StreamBufferCompID ] GetInterface $xilinx::Prjrep::IStreamID ]
$opts_stream WriteString "5"
$opts_stream WriteString "5"
$opts_stream WriteString "5"
$opts_stream WriteString "5"
$opts_stream WriteString "0"
$opts_stream WriteString "0"
$opts_stream WriteString "3"
$opts_stream WriteString "1"
$opts_stream WriteString "1"
$opts_stream WriteString "1"
$opts_stream WriteString "2"
$opts_stream WriteString "0"
$opts_stream WriteString "0"
$opts_stream WriteString "1"
RestoreSourceControlOptions "$project_file" $opts_stream
Release $opts_stream
if { $srcctrl_comp != 0 } {
set i_prjref [ $srcctrl_comp GetInterface $::xilinx::Dpm::IProjectHelperReferenceID ]
$i_prjref Set iProjHelper
} elseif {$iProjHelper != 0} {
$iProjHelper Close
}
Release $iProjHelper
# return back
cd $old_working_dir
}
 
/trunk/impl/spartan3an-sk/ise/zet_soc.ucf
0,0 → 1,101
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Wed August 30 15:11: 2006
##
##
############################################################################
## File name : mem_interface_top.ucf
##
## Generated by spartan3a released on April 03 2006
## Description : Constraints file
## targetted to xc3s700a-4 fg484
##
############################################################################
 
### Board contraints
NET "SYS_CLK" LOC = "E12" | IOSTANDARD = LVCMOS33 ; # | PERIOD = 20.000 ;
#OFFSET = IN 10.000 VALID 20.000 BEFORE "SYS_CLK" ;
#OFFSET = OUT 20.000 AFTER "SYS_CLK" ;
 
##############################################################################
# Parallel Flash (NF)
##############################################################################
 
NET "NF_CE" LOC = "W20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_BYTE" LOC = "Y21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_OE" LOC = "W19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_WE" LOC = "AA22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_RP" LOC = "R22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
 
NET "NF_A[1]" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[2]" LOC = "R19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[3]" LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[4]" LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[5]" LOC = "N21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[6]" LOC = "N20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[7]" LOC = "N19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[8]" LOC = "N18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[9]" LOC = "N17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[10]" LOC = "K22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[11]" LOC = "J22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[12]" LOC = "J21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[13]" LOC = "J20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[14]" LOC = "H22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[15]" LOC = "G22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[16]" LOC = "H21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[17]" LOC = "H20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[18]" LOC = "F22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[19]" LOC = "F21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[20]" LOC = "C22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "NF_A[21]" LOC = "C21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
# Note: NF_D<0> pin is shared with SPI_MISO pin which was previously declared.
NET "NF_D[0]" LOC = "AB20" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[1]" LOC = "Y17" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[2]" LOC = "AA17" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[3]" LOC = "U13" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[4]" LOC = "AB11" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[5]" LOC = "Y11" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[6]" LOC = "AB9" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[7]" LOC = "Y9" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[8]" LOC = "T20" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[9]" LOC = "W22" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[10]" LOC = "V22" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[11]" LOC = "U21" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[12]" LOC = "U22" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[13]" LOC = "T22" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[14]" LOC = "R21" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
NET "NF_D[15]" LOC = "T17" | IOSTANDARD = LVCMOS33 ; # | DRIVE = 8 | SLEW = SLOW ;
 
 
##############################################################################
# Directional Push-Buttons (BTN)
##############################################################################
 
NET "BTN_SOUTH" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
 
 
##############################################################################
# Video Output Port (VGA)
##############################################################################
 
NET "VGA_B" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "VGA_G" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "VGA_R" LOC = "C8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "C11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VSYNC" LOC = "B11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
 
##############################################################################
# Discrete Indicators (LED)
##############################################################################
 
NET "LED[0]" LOC = "R20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED[1]" LOC = "T19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
#NET "LED[2]" LOC = "U20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
#NET "LED[3]" LOC = "U19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
#NET "LED[4]" LOC = "V19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
#NET "LED[5]" LOC = "V20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
#NET "LED[6]" LOC = "Y22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
#NET "LED[7]" LOC = "W21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
 
/trunk/impl/spartan3an-sk/rtl/parameters.v
0,0 → 1,78
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: not supported by cvs2svn $
// \ \ Application : MIG
// / / Filename : vlog_xst_bl4_parameters_0.v
// /___/ /\ Date Last Modified : $Date: 2008-07-03 09:05:51 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
// Device : Spartan-3/3A
// Design Name : DDR2 SDRAM
// Purpose : This module has the parameters used in the design
///////////////////////////////////////////////////////////////////////////////
 
`define data_width 16
`define data_strobe_width 2
`define data_mask_width 2
`define clk_width 1
`define ReadEnable 1
`define cke_width 1
`define deep_memory 1
`define memory_width 8
`define registered 0
`define col_ap_width 11
`define DatabitsPerStrobe 8
`define DatabitsPerMask 8
`define no_of_CS 1
`define RESET 0
`define data_mask 1
`define write_pipe_itr 1
`define ecc_enable 0
`define ecc_width 0
`define dq_width 16
`define dm_width 2
`define dqs_width 2
`define write_pipeline 4
`define top_bottom 0
`define left_right 1
`define row_address 13
`define column_address 10
`define bank_address 2
`define spartan3a 1
`define burst_length 3'b010
`define burst_type 1'b0
`define cas_latency_value 3'b011
`define mode 1'b0
`define dll_rst 1'b1
`define write_recovery 3'b010
`define pd_mode 1'b0
`define load_mode_register 13'b0010100110010
`define outputs 1'b0
`define rdqs_ena 1'b0
`define dqs_n_ena 1'b0
`define ocd_operation 3'b000
`define odt_enable 2'b00
`define additive_latency_value 3'b000
`define op_drive_strength 1'b0
`define dll_ena 1'b0
`define ext_load_mode_register 13'b0000000000000
`define chip_address 1
`define reset_active_low 1'b0
`define rcd_count_value 3'b001
`define ras_count_value 4'b0101
`define mrd_count_value 1'b1
`define rp_count_value 3'b001
`define rfc_count_value 6'b001101
`define trtp_count_value 3'b000
`define twr_count_value 3'b010
`define twtr_count_value 3'b001
`define max_ref_width 11
`define max_ref_cnt 11'b10000000001
 
 
`timescale 1ns/100ps
/trunk/impl/spartan3an-sk/rtl/flash-prom/flashcntrlr.v
0,0 → 1,125
`timescale 1ns/100ps
 
module flash_prom_zet_cntrlr (
output NF_WE,
output NF_CE,
output NF_OE,
output NF_BYTE,
output [21:1] NF_A,
input [15:0] NF_D,
 
input cpu_clk,
input sys_clk,
input reset,
input [16:0] addr,
input byte_m,
output [15:0] rd_data,
input enable,
output ready
);
 
// Net and register declarations
wire [15:0] addr0, addr1;
reg [15:0] word0;
reg [7:0] word1;
wire [7:0] byte_l0, byte_l1, byte_h0;
wire a0;
wire sec_wrd;
reg old_clk, start_cmd;
reg [3:0] state, next_state;
reg eff_ready;
reg [15:0] nf_addr;
 
parameter word0_st = 4'd0;
parameter wait1 = 4'd1;
parameter wait2 = 4'd2;
parameter wait3 = 4'd3;
parameter word1_st = 4'd4;
parameter wait4 = 4'd5;
parameter wait5 = 4'd6;
parameter wait6 = 4'd7;
parameter rd_word1 = 4'd8;
parameter rd_done = 4'd9;
 
// Assignments
assign addr0 = addr[16:1];
assign addr1 = addr0 + 16'd1;
assign a0 = addr[0];
 
assign byte_l0 = word0[7:0];
assign byte_h0 = word0[15:8];
assign byte_l1 = word1;
 
assign rd_data = byte_m ? ( a0 ? { {8{byte_h0[7]}}, byte_h0 }
: { {8{byte_l0[7]}}, byte_l0 } )
: ( a0 ? { byte_l1, byte_h0 }
: word0 );
 
assign ready = (next_state==rd_done) || !enable;
assign sec_wrd = (!byte_m && a0);
 
assign NF_BYTE = 1'b1;
assign NF_WE = 1'b1;
assign NF_CE = 1'b0;
assign NF_OE = 1'b0;
assign NF_A = { 5'b0, nf_addr };
 
// word0 load logic
always @(posedge sys_clk)
if (reset) word0 <= 16'h0;
else if (state == wait3) word0 <= NF_D;
else word0 <= word0;
 
// word1 load logic
always @(posedge sys_clk)
if (reset) word1 <= 8'h0;
else if (state == wait6) word1 <= NF_D[7:0];
else word1 <= word1;
 
// nf_addr load logic
always @(posedge sys_clk)
if (reset) nf_addr <= 16'h0;
else if (start_cmd || state == rd_done) nf_addr <= addr0;
else if (state == wait3) nf_addr <= addr1;
else nf_addr <= nf_addr;
 
// Read sequence fsm
always @(state or reset or sec_wrd)
if (reset) next_state <= rd_done;
else
case (state)
word0_st: next_state <= wait1;
wait1: next_state <= wait2;
wait2: next_state <= wait3;
wait3: next_state <= word1_st;
word1_st: next_state <= sec_wrd ? wait4 : rd_done;
wait4: next_state <= wait5;
wait5: next_state <= wait6;
wait6: next_state <= rd_word1;
rd_word1: next_state <= rd_done;
default: next_state <= word0_st;
endcase
 
always @(posedge sys_clk)
if (reset) state <= rd_word1;
else begin
if (start_cmd) state <= word0_st;
else state <= (next_state==rd_done) ? state : next_state;
end
 
// start_cmd signal
always @(negedge sys_clk)
if (reset)
begin
old_clk <= 1'b0;
start_cmd <= 1'b0;
end
else
begin
if (cpu_clk && !old_clk && eff_ready && enable) start_cmd <= 1'b1;
else start_cmd <= 1'b0;
old_clk <= cpu_clk;
end
 
always @(posedge cpu_clk) eff_ready <= ready;
endmodule
/trunk/impl/spartan3an-sk/rtl/zet_soc.v
0,0 → 1,149
`timescale 1ns/100ps
 
module zet_soc (
// input DDR_CLK,
input SYS_CLK,
/*
inout [15:0] SD_DQ,
output [12:0] SD_A,
output [1:0] SD_BA,
output SD_CK_P,
output SD_CK_N,
output SD_CKE,
output SD_CS,
output SD_RAS,
output SD_CAS,
output SD_WE,
output SD_ODT,
output SD_UDM,
output SD_LDM,
inout SD_UDQS_P,
inout SD_LDQS_P,
inout SD_UDQS_N,
inout SD_LDQS_N,
input SD_LOOP_IN,
output SD_LOOP_OUT,
*/
input [15:0] NF_D,
output [21:1] NF_A,
output NF_WE,
output NF_CE,
output NF_OE,
output NF_BYTE,
output NF_RP,
 
input BTN_SOUTH,
 
output VGA_R,
output VGA_G,
output VGA_B,
output VGA_HSYNC,
output VGA_VSYNC,
 
output [1:0] LED
);
 
// Net declarations
wire cpu_clk;
wire mem_rst;
wire [19:0] addr;
wire [15:0] wr_data;
wire we, m_io;
wire byte_m;
wire [15:0] rd_data, vdu_data, mem_data /*, io_data */;
wire vdu_cs;
wire mem_op;
wire ready, mem_rdy, vdu_rdy;
wire wr_cnd; // Stub
// reg [15:0] io_reg;
 
// Module instantiation
memory mem_ctrlr_0 (
/*
.cntrl0_DDR2_DQ (SD_DQ),
.cntrl0_DDR2_A (SD_A),
.cntrl0_DDR2_BA (SD_BA),
.cntrl0_DDR2_CK (SD_CK_P),
.cntrl0_DDR2_CK_N (SD_CK_N),
.cntrl0_DDR2_CKE (SD_CKE),
.cntrl0_DDR2_CS_N (SD_CS),
.cntrl0_DDR2_RAS_N (SD_RAS),
.cntrl0_DDR2_CAS_N (SD_CAS),
.cntrl0_DDR2_WE_N (SD_WE),
.cntrl0_DDR2_ODT (SD_ODT),
.cntrl0_DDR2_DM ({SD_UDM, SD_LDM}),
.cntrl0_DDR2_DQS ({SD_UDQS_P, SD_LDQS_P}),
.cntrl0_DDR2_DQS_N ({SD_UDQS_N, SD_LDQS_N}),
.cntrl0_rst_dqs_div_in (SD_LOOP_IN), // loopback
.cntrl0_rst_dqs_div_out (SD_LOOP_OUT), // loopback
*/
.NF_WE (NF_WE),
.NF_CE (NF_CE),
.NF_OE (NF_OE),
.NF_BYTE (NF_BYTE),
.NF_A (NF_A),
.NF_D (NF_D),
 
// .ddr_clk (DDR_CLK),
.sys_clk (SYS_CLK),
.cpu_clk (cpu_clk),
.mem_rst (mem_rst),
.board_reset (BTN_SOUTH),
 
.addr (addr),
// .wr_data (wr_data),
// .we (we & ~m_io),
.byte_m (byte_m),
.rd_data (mem_data),
.mem_op (mem_op),
.ready (mem_rdy)
);
 
cpu cpu0 (
.clk (cpu_clk),
.rst (mem_rst),
.rd_data (rd_data),
.wr_data (wr_data),
.addr (addr),
.we (we),
.byte_m (byte_m),
.m_io (m_io),
.wr_cnd (wr_cnd), // Stub
.mem_op (mem_op),
.mem_rdy (ready)
);
 
vdu vdu0 (
.vga_red_o (VGA_R),
.vga_green_o (VGA_G),
.vga_blue_o (VGA_B),
.horiz_sync (VGA_HSYNC),
.vert_sync (VGA_VSYNC),
 
.vdu_clk_in (SYS_CLK), // 50MHz System clock
.cpu_clk_out (cpu_clk), // 12.5 MHz CPU Clock
.vdu_rst (BTN_SOUTH),
.vdu_cs (vdu_cs),
.vdu_we (we),
.byte_m (byte_m),
.vdu_addr (addr[11:0]),
.wr_data (wr_data),
.rd_data (vdu_data),
.ready (vdu_rdy)
);
 
// assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0;
assign vdu_cs = (addr[19:12]==16'hb8) && mem_op;
assign rd_data = /* m_io ? io_data : */ (vdu_cs ? vdu_data : mem_data);
assign ready = vdu_cs ? vdu_rdy : mem_rdy;
assign NF_RP = 1'b1;
assign LED = { wr_cnd, m_io };
 
// Behaviour
// IO Stub
/*
always @(posedge cpu_clk)
if (addr==20'hb7 & ~we & m_io)
io_reg <= byte_m ? { io_reg[15:8], wr_data[7:0] } : wr_data;
*/
endmodule
/trunk/impl/spartan3an-sk/rtl/memory.v
0,0 → 1,113
`timescale 1ns/10ps
 
module memory (
/*
inout [15:0] cntrl0_DDR2_DQ,
output [12:0] cntrl0_DDR2_A,
output [1:0] cntrl0_DDR2_BA,
output cntrl0_DDR2_CK,
output cntrl0_DDR2_CK_N,
output cntrl0_DDR2_CKE,
output cntrl0_DDR2_CS_N,
output cntrl0_DDR2_RAS_N,
output cntrl0_DDR2_CAS_N,
output cntrl0_DDR2_WE_N,
output cntrl0_DDR2_ODT,
output [1:0] cntrl0_DDR2_DM,
inout [1:0] cntrl0_DDR2_DQS,
inout [1:0] cntrl0_DDR2_DQS_N,
input cntrl0_rst_dqs_div_in, // loopback
output cntrl0_rst_dqs_div_out, // loopback
*/
output NF_WE,
output NF_CE,
output NF_OE,
output NF_BYTE,
output [21:1] NF_A,
input [15:0] NF_D,
 
// input ddr_clk,
input sys_clk,
input cpu_clk,
output mem_rst,
input board_reset,
 
input [19:0] addr,
// input [15:0] wr_data,
// input we,
input byte_m,
output [15:0] rd_data,
input mem_op,
output ready
);
 
// Net declarations
wire rom_area;
wire [15:0] rd_rom_data /*, rd_ram_data */;
wire [16:0] rom_addr;
wire rom_ready /*, ram_ready */;
wire rom_op /*, ram_op */;
 
// Module instantiations
flash_prom_zet_cntrlr flash0 (
.NF_WE (NF_WE),
.NF_CE (NF_CE),
.NF_OE (NF_OE),
.NF_BYTE (NF_BYTE),
.NF_A (NF_A),
.NF_D (NF_D),
 
.cpu_clk (cpu_clk),
.sys_clk (sys_clk),
.reset (mem_rst),
.addr (rom_addr),
.byte_m (byte_m),
.rd_data (rd_rom_data),
.enable (rom_op),
.ready (rom_ready)
);
/*
ddr2_sdram_zet_cntrlr sdram0 (
.cntrl0_DDR2_DQ (cntrl0_DDR2_DQ),
.cntrl0_DDR2_A (cntrl0_DDR2_A),
.cntrl0_DDR2_BA (cntrl0_DDR2_BA),
.cntrl0_DDR2_CK (cntrl0_DDR2_CK),
.cntrl0_DDR2_CK_N (cntrl0_DDR2_CK_N),
.cntrl0_DDR2_CKE (cntrl0_DDR2_CKE),
.cntrl0_DDR2_CS_N (cntrl0_DDR2_CS_N),
.cntrl0_DDR2_RAS_N (cntrl0_DDR2_RAS_N),
.cntrl0_DDR2_CAS_N (cntrl0_DDR2_CAS_N),
.cntrl0_DDR2_WE_N (cntrl0_DDR2_WE_N),
.cntrl0_DDR2_ODT (cntrl0_DDR2_ODT),
.cntrl0_DDR2_DM (cntrl0_DDR2_DM),
.cntrl0_DDR2_DQS (cntrl0_DDR2_DQS),
.cntrl0_DDR2_DQS_N (cntrl0_DDR2_DQS_N),
.cntrl0_rst_dqs_div_in (cntrl0_rst_dqs_div_in), // loopback
.cntrl0_rst_dqs_div_out (cntrl0_rst_dqs_div_out), // loopback
 
.board_reset (board_reset), // board reset
.sys_clk (ddr_clk),
.cpu_clk (cpu_clk),
.addr (addr),
.wr_data (wr_data),
.we (we),
.byte_m (byte_m),
.rd_data (rd_ram_data),
.mem_rst (mem_rst),
.enable (ram_op),
.ready (ram_ready)
);
*/
 
// Assignments
assign rom_area = (addr[19:16]==4'hf || addr[19:16]==4'hc);
assign rd_data = rom_area ? rd_rom_data : 16'h0 /* rd_ram_data */;
assign rom_addr[16] = (addr[19:16]==4'hf);
assign rom_addr[15:0] = addr;
assign ready = rom_area ? rom_ready : 1'b1 /* ram_ready */;
assign rom_op = rom_area && mem_op;
// assign ram_op = !rom_area && mem_op;
 
// stub
assign mem_rst = board_reset;
endmodule
/trunk/impl/spartan3an-sk/rtl/vga/ram2k_b16_attr.v
0,0 → 1,95
`timescale 1ns/10ps
 
module ram_2k_attr (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
 
// Net declarations
wire dp;
wire rw;
 
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (rw));
 
defparam ram.INIT_00 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_01 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_02 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_03 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_04 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_05 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_06 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_07 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_08 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_09 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_0F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_10 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_11 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_12 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_13 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_14 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_15 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_16 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_17 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_18 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_19 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_1F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_20 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_21 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_22 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_23 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_24 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_25 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_26 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_27 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_28 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_29 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_2F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_30 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_31 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_32 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_33 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_34 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_35 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_36 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_37 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_38 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_39 = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3A = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3B = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3C = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3D = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3E = 256'h0707070707070707070707070707070707070707070707070707070707070707;
defparam ram.INIT_3F = 256'h0707070707070707070707070707070707070707070707070707070707070707;
 
// Assignments
assign rw = ~we;
endmodule
/trunk/impl/spartan3an-sk/rtl/vga/vdu.v
0,0 → 1,397
// Video Display terminal
// John Kent
// 3th September 2004
// Assumes a pixel clock input of 50 MHz
// Generates a 12.5MHz CPU Clock output
//
// Display Format is:
// 80 characters across by 25 characters down.
// 8 horizonal pixels / character
// 16 vertical scan lines / character (2 scan lines/row)
`timescale 1ns/10ps
 
module vdu
(
input vdu_clk_in, // 50MHz System clock
output cpu_clk_out, // 6.25 MHz CPU Clock
input vdu_rst,
input vdu_cs,
input vdu_we,
input byte_m,
input [11:0] vdu_addr,
input [15:0] wr_data,
output reg [15:0] rd_data,
output ready,
 
output reg vga_red_o,
output reg vga_green_o,
output reg vga_blue_o,
output reg horiz_sync,
output reg vert_sync
);
 
// Net, registers and parameters
 
// Synchronization constants
parameter HOR_DISP_END = 10'd639; // Last horizontal pixel displayed
parameter HOR_SYNC_BEG = 10'd679; // Start of horizontal synch pulse
parameter HOR_SYNC_END = 10'd775; // End of Horizontal Synch pulse
parameter HOR_SCAN_END = 10'd799; // Last pixel in scan line
parameter HOR_DISP_CHR = 80; // Number of characters displayed per row
 
parameter VER_DISP_END = 9'd399; // last row displayed
parameter VER_SYNC_BEG = 9'd413; // start of vertical synch pulse
parameter VER_SYNC_END = 9'd414; // end of vertical synch pulse
parameter VER_SCAN_END = 9'd450; // Last scan row in the frame
parameter VER_DISP_CHR = 6'd25; // Number of character rows displayed
 
reg cursor_on_v;
reg cursor_on_h;
reg video_on_v;
reg video_on_h;
reg [9:0] h_count;
reg [8:0] v_count; // 0 to VER_SCAN_END
reg [22:0] blink_count;
 
// Character generator ROM
wire char_cs;
wire char_we;
wire [11:0] char_addr;
wire [7:0] char_data_in;
wire [7:0] char_data_out;
 
// Control registers
wire [6:0] reg_hcursor; // 80 columns
wire [4:0] reg_vcursor; // 25 rows
wire [4:0] reg_voffset; // 25 rows
 
// Video shift register
reg [7:0] vga_shift;
reg [2:0] vga_fg_colour;
reg [2:0] vga_bg_colour;
reg cursor_on;
wire cursor_on1;
reg video_on;
wire video_on1;
 
// vga character ram access bus
reg [6:0] col_addr; // 0 to 79
reg [4:0] row_addr; // 0 to 49 (25 * 2 -1)
reg [6:0] col1_addr; // 0 to 79
reg [4:0] row1_addr; // 0 to 49 (25 * 2 - 1)
reg [6:0] hor_addr; // 0 to 79
reg [6:0] ver_addr; // 0 to 124
reg vga0_we;
reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw;
reg vga1_we;
reg vga2_we;
reg buff_we;
reg [7:0] buff_data_in;
reg attr_we;
reg [7:0] attr_data_in;
reg [10:0] buff_addr;
reg [10:0] attr0_addr;
reg attr0_we;
reg [10:0] buff0_addr;
reg buff0_we;
reg [10:0] attr_addr;
wire vga_cs;
wire [7:0] vga_data_out;
wire [7:0] attr_data_out;
wire [10:0] vga_addr; // 2K byte character buffer
wire a0;
wire [10:0] vdu_addr1;
wire byte1;
wire [15:0] out_data;
wire [15:0] ext_attr, ext_buff;
wire fg_or_bg;
 
// Character write handshake signals
reg req_write; // request character write
reg req_read;
reg one_more_cycle;
 
// Clock divider
reg [1:0] clk_count;
wire vdu_clk;
 
// Module instantiation
char_rom vdu_char_rom (
.clk (vdu_clk),
.rst (vdu_rst),
.cs (char_cs),
.we (char_we),
.addr (char_addr),
.wdata (char_data_in),
.rdata (char_data_out)
);
 
ram_2k char_buff_ram (
.clk (vdu_clk),
.rst (vdu_rst),
.cs (vga_cs),
.we (buff_we),
.addr (buff_addr),
.wdata (buff_data_in),
.rdata (vga_data_out)
);
 
ram_2k_attr attr_buff_ram (
.clk (vdu_clk),
.rst (vdu_rst),
.cs (vga_cs),
.we (attr_we),
.addr (attr_addr),
.wdata (attr_data_in),
.rdata (attr_data_out)
);
 
BUFG vdu_clk_buffer (
.I (clk_count[0]),
.O (vdu_clk)
);
 
BUFG cpu_clk_buffer (
.I (clk_count[1]),
.O (cpu_clk_out)
);
 
// Assignments
assign video_on1 = video_on_h && video_on_v;
assign cursor_on1 = cursor_on_h && cursor_on_v;
assign char_cs = 1'b1;
assign char_we = 1'b1;
assign char_data_in = 8'b0;
assign char_addr = { vga_data_out, v_count[3:0] };
assign vga_addr = { 4'b0, hor_addr} + { ver_addr, 4'b0 };
assign a0 = vdu_addr[0];
assign vdu_addr1 = vdu_addr[11:1] + 11'd1;
assign byte1 = byte_m || (vdu_addr == 12'hfff);
assign ready = !req_write && !req_read;
assign out_data = a0 ? (byte_m ? ext_attr : {vga_data_out, attr_data_out} )
: (byte_m ? ext_buff : {attr_data_out, vga_data_out} );
assign ext_buff = { {8{vga_data_out[7]}}, vga_data_out };
assign ext_attr = { {8{attr_data_out[7]}}, attr_data_out };
 
assign vga_cs = 1'b1;
 
// Old control registers
assign reg_hcursor = 7'b0;
assign reg_vcursor = 5'd0;
assign reg_voffset = 5'd0;
 
assign fg_or_bg = vga_shift[7] ^ cursor_on;
 
// Behaviour
// vga clock generation
always @(negedge vdu_clk_in)
/* if (vdu_rst) clk_count <= 2'b00;
else */ clk_count <= clk_count + 2'b01;
 
// For simulation
initial clk_count <= 2'b00;
 
// CPU write interface
always @(negedge vdu_clk)
if (vdu_rst)
begin
attr0_addr <= 11'b0;
attr0_we <= 1'b1;
attr_data_in <= 8'h0;
buff0_addr <= 11'b0;
buff0_we <= 1'b1;
buff_data_in <= 8'h0;
end
else
begin
if (vdu_cs && ready)
begin
attr0_addr <= vdu_addr[11:1];
attr0_we <= vdu_we | (byte1 & ~a0);
attr_data_in <= a0 ? wr_data[7:0] : wr_data[15:8];
buff0_addr <= (a0 && !byte1) ? vdu_addr1 : vdu_addr[11:1];
buff0_we <= vdu_we | (byte1 & a0);
buff_data_in <= a0 ? wr_data[15:8] : wr_data[7:0];
end
end
 
always @(negedge cpu_clk_out)
if (vdu_rst)
begin
req_write <= 1'b0;
req_read <= 1'b0;
one_more_cycle <= 1'b0;
end
else
begin
if (vdu_cs && !vdu_we && ready) req_write <= 1'b1;
else if (req_write && !vga2_we) req_write <= 1'b0;
if (vdu_cs && vdu_we)
begin
if (ready)
begin
req_read <= 1'b1;
if (vga2_rw) one_more_cycle <= 1'b1;
else one_more_cycle <= 1'b0;
end
else
if (req_read && vga4_rw)
begin
if (one_more_cycle) one_more_cycle <= 1'b0;
else req_read <= 1'b0;
end
end
end
 
// Sync generation & timing process
// Generate horizontal and vertical timing signals for video signal
always @(negedge vdu_clk)
if (vdu_rst)
begin
h_count <= 10'b0;
horiz_sync <= 1'b1;
v_count <= 9'b0;
vert_sync <= 1'b1;
video_on_h <= 1'b1;
video_on_v <= 1'b1;
cursor_on_h <= 1'b0;
cursor_on_v <= 1'b0;
blink_count <= 22'b0;
end
else
begin
h_count <= (h_count==HOR_SCAN_END) ? 10'b0 : h_count + 10'b1;
horiz_sync <= (h_count==HOR_SYNC_BEG) ? 1'b0
: ((h_count==HOR_SYNC_END) ? 1'b1 : horiz_sync);
v_count <= (v_count==VER_SCAN_END && h_count==HOR_SCAN_END) ? 9'b0
: ((h_count==HOR_SYNC_END) ? v_count + 9'b1 : v_count);
vert_sync <= (v_count==VER_SYNC_BEG) ? 1'b0
: ((v_count==VER_SYNC_END) ? 1'b1 : vert_sync);
video_on_h <= (h_count==HOR_SCAN_END) ? 1'b1
: ((h_count==HOR_DISP_END) ? 1'b0 : video_on_h);
video_on_v <= (v_count==VER_SYNC_BEG) ? 1'b1
: ((v_count==VER_DISP_END) ? 1'b0 : video_on_v);
cursor_on_h <= (h_count[9:3] == reg_hcursor[6:0]);
cursor_on_v <= (v_count[8:4] == reg_vcursor[4:0]);
blink_count <= blink_count + 22'd1;
end
 
// Video memory access
always @(negedge vdu_clk)
if (vdu_rst)
begin
vga0_we <= 1'b0;
vga0_rw <= 1'b1;
row_addr <= 5'b0;
col_addr <= 7'b0;
 
vga1_we <= 1'b0;
vga1_rw <= 1'b1;
row1_addr <= 5'b0;
col1_addr <= 7'b0;
 
vga2_we <= 1'b0;
vga2_rw <= 1'b0;
vga3_rw <= 1'b0;
vga4_rw <= 1'b0;
ver_addr <= 7'b0;
hor_addr <= 7'b0;
 
buff_addr <= 10'b0;
attr_addr <= 10'b0;
buff_we <= 1'b1;
attr_we <= 1'b1;
 
rd_data <= 16'd0;
end
else
begin
// on h_count = 0 initiate character write
// all other cycles are reads
case (h_count[2:0])
3'b000: // pipeline character write
begin
vga0_we <= !req_write;
vga0_rw <= 1'b1;
end
default: // other 6 cycles free
begin
vga0_we <= 1'b1;
vga0_rw <= 1'b0;
col_addr <= h_count[9:3];
row_addr <= v_count[8:4] + reg_voffset[4:0];
end
endcase
 
// on vdu_clk + 1 round off row address
// row1_addr = (row_addr % 80)
vga1_we <= vga0_we;
vga1_rw <= vga0_rw;
row1_addr <= (row_addr < VER_DISP_CHR) ? row_addr
: row_addr - VER_DISP_CHR;
col1_addr <= col_addr;
 
// on vdu_clk + 2 calculate vertical address
// ver_addr = (row_addr % 80) x 5
vga2_we <= vga1_we;
vga2_rw <= vga1_rw;
ver_addr <= { 2'b00, row1_addr } + { row1_addr, 2'b00 }; // x5
hor_addr <= col1_addr;
 
// on vdu_clk + 3 calculate memory address
// vga_addr = (row_addr % 80) * 80 + hor_addr
buff_addr <= vga2_rw ? buff0_addr : vga_addr;
attr_addr <= vga2_rw ? attr0_addr : vga_addr;
buff_we <= vga2_rw ? (buff0_we | vga2_we) : 1'b1;
attr_we <= vga2_rw ? (attr0_we | vga2_we) : 1'b1;
vga3_rw <= vga2_rw;
 
rd_data <= vga3_rw ? out_data : rd_data;
vga4_rw <= vga3_rw;
end
 
// Video shift register
always @(negedge vdu_clk)
if (vdu_rst)
begin
video_on = 1'b0;
cursor_on = 1'b0;
vga_bg_colour = 3'b000;
vga_fg_colour = 3'b111;
vga_shift = 8'b00000000;
vga_red_o = 1'b0;
vga_green_o = 1'b0;
vga_blue_o = 1'b0;
end
else
begin
if (h_count[2:0] == 3'b000)
begin
video_on = video_on1;
cursor_on = (cursor_on1 | attr_data_out[3]) & blink_count[22];
vga_fg_colour = attr_data_out[2:0];
vga_bg_colour = attr_data_out[6:4];
if (!attr_data_out[7]) vga_shift = char_data_out;
else
case (v_count[3:2])
2'b00: vga_shift = { {4{vga_data_out[0]}}, {4{vga_data_out[1]}} };
2'b01: vga_shift = { {4{vga_data_out[2]}}, {4{vga_data_out[3]}} };
2'b10: vga_shift = { {4{vga_data_out[4]}}, {4{vga_data_out[5]}} };
default: vga_shift = { {4{vga_data_out[6]}}, {4{vga_data_out[7]}} };
endcase
end
else vga_shift = { vga_shift[6:0], 1'b0 };
 
//
// Colour mask is
// 7 6 5 4 3 2 1 0
// X BG BB BR X FG FB FR
//
vga_red_o = fg_or_bg ? video_on & vga_fg_colour[0]
: video_on & vga_bg_colour[0];
vga_green_o = fg_or_bg ? video_on & vga_fg_colour[1]
: video_on & vga_bg_colour[1];
vga_blue_o = fg_or_bg ? video_on & vga_fg_colour[2]
: video_on & vga_bg_colour[2];
end
endmodule
/trunk/impl/spartan3an-sk/rtl/vga/char_rom_b16.v
0,0 → 1,183
////////////////////////////////////////////////////////////////
//
// Character generator ROM
//
// 7 pixels x 11 rows x 128 characters.
//
// Last Updated
// 18th Oct 2004
// J. E. Kent.
////////////////////////////////////////////////////////////////
 
`timescale 1ns/10ps
 
module char_rom (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [11:0] addr;
output [7:0] rdata;
input [7:0] wdata;
 
// Net declarations
wire dp0, dp1;
wire rw;
wire [7:0] rdata1, rdata0;
 
// Module instantiations
RAMB16_S9 rom0 (.DO(rdata0),
.DOP (dp0),
.ADDR (addr[10:0]),
.CLK (clk),
.DI (wdata),
.DIP (dp0),
.EN (cs),
.SSR (rst),
.WE (rw));
 
RAMB16_S9 rom1 (.DO(rdata1),
.DOP (dp1),
.ADDR (addr[10:0]),
.CLK (clk),
.DI (wdata),
.DIP (dp1),
.EN (cs),
.SSR (rst),
.WE (rw));
 
defparam rom0.INIT_00 = 256'h000000007E818199A58181A5817E0000_00000000000000000000000000000000; // 01() 00( )
defparam rom0.INIT_01 = 256'h0000000010387CFEFEFEFE6C00000000_000000007EFFFFE7DBFFFFDBFF7E0000; // 03() 02()
defparam rom0.INIT_02 = 256'h000000003C1818E7E7E73C3C18000000_000000000010387CFE7C381000000000; // 05() 04()
defparam rom0.INIT_03 = 256'h000000000000183C3C18000000000000_000000003C18187EFFFF7E3C18000000; // 07() 06()
defparam rom0.INIT_04 = 256'h00000000003C664242663C0000000000_FFFFFFFFFFFFE7C3C3E7FFFFFFFFFFFF; // 09( ) 08()
defparam rom0.INIT_05 = 256'h0000000078CCCCCCCC781A0E061E0000_FFFFFFFFFFC399BDBD99C3FFFFFFFFFF; // 0b( ) 0a()
defparam rom0.INIT_06 = 256'h00000000E0F070303030303F333F0000_0000000018187E183C666666663C0000; // 0d() 0c( )
defparam rom0.INIT_07 = 256'h000000001818DB3CE73CDB1818000000_000000C0E6E767636363637F637F0000; // 0f() 0e()
defparam rom0.INIT_08 = 256'h0000000002060E1E3EFE3E1E0E060200_0000000080C0E0F0F8FEF8F0E0C08000; // 11() 10()
defparam rom0.INIT_09 = 256'h00000000666600666666666666660000_0000000000183C7E1818187E3C180000; // 13() 12()
defparam rom0.INIT_0A = 256'h0000007CC60C386CC6C66C3860C67C00_000000001B1B1B1B1B7BDBDBDB7F0000; // 15() 14()
defparam rom0.INIT_0B = 256'h000000007E183C7E1818187E3C180000_00000000FEFEFEFE0000000000000000; // 17() 16()
defparam rom0.INIT_0C = 256'h00000000183C7E181818181818180000_00000000181818181818187E3C180000; // 19() 18()
defparam rom0.INIT_0D = 256'h0000000000003060FE60300000000000_000000000000180CFE0C180000000000; // 1b() 1a()
defparam rom0.INIT_0E = 256'h000000000000286CFE6C280000000000_000000000000FEC0C0C0000000000000; // 1d() 1c()
defparam rom0.INIT_0F = 256'h00000000001038387C7CFEFE00000000_0000000000FEFE7C7C38381000000000; // 1f() 1e()
defparam rom0.INIT_10 = 256'h000000001818001818183C3C3C180000_00000000000000000000000000000000; // 21(!) 20( )
defparam rom0.INIT_11 = 256'h000000006C6CFE6C6C6CFE6C6C000000_00000000000000000000002466666600; // 23(#) 22(")
defparam rom0.INIT_12 = 256'h0000000086C66030180CC6C200000000_000018187CC68606067CC0C2C67C1818; // 25(%) 24($)
defparam rom0.INIT_13 = 256'h00000000000000000000006030303000_0000000076CCCCCCDC76386C6C380000; // 27(') 26(&)
defparam rom0.INIT_14 = 256'h0000000030180C0C0C0C0C0C18300000_000000000C18303030303030180C0000; // 29()) 28(()
defparam rom0.INIT_15 = 256'h00000000000018187E18180000000000_000000000000663CFF3C660000000000; // 2b(+) 2a(*)
defparam rom0.INIT_16 = 256'h0000000000000000FE00000000000000_00000030181818000000000000000000; // 2d(-) 2c(,)
defparam rom0.INIT_17 = 256'h0000000080C06030180C060200000000_00000000181800000000000000000000; // 2f(/) 2e(.)
defparam rom0.INIT_18 = 256'h000000007E1818181818187838180000_00000000386CC6C6D6D6C6C66C380000; // 31(1) 30(0)
defparam rom0.INIT_19 = 256'h000000007CC60606063C0606C67C0000_00000000FEC6C06030180C06C67C0000; // 33(3) 32(2)
defparam rom0.INIT_1A = 256'h000000007CC6060606FCC0C0C0FE0000_000000001E0C0C0CFECC6C3C1C0C0000; // 35(5) 34(4)
defparam rom0.INIT_1B = 256'h0000000030303030180C0606C6FE0000_000000007CC6C6C6C6FCC0C060380000; // 37(7) 36(6)
defparam rom0.INIT_1C = 256'h00000000780C0606067EC6C6C67C0000_000000007CC6C6C6C67CC6C6C67C0000; // 39(9) 38(8)
defparam rom0.INIT_1D = 256'h00000000301818000000181800000000_00000000001818000000181800000000; // 3b(;) 3a(:)
defparam rom0.INIT_1E = 256'h000000000000007E00007E0000000000_00000000060C18306030180C06000000; // 3d(=) 3c(<)
defparam rom0.INIT_1F = 256'h000000001818001818180CC6C67C0000_000000006030180C060C183060000000; // 3f(?) 3e(>)
defparam rom0.INIT_20 = 256'h00000000C6C6C6C6FEC6C66C38100000_000000007CC0DCDEDEDEC6C67C000000; // 41(A) 40(@)
defparam rom0.INIT_21 = 256'h000000003C66C2C0C0C0C0C2663C0000_00000000FC666666667C666666FC0000; // 43(C) 42(B)
defparam rom0.INIT_22 = 256'h00000000FE6662606878686266FE0000_00000000F86C6666666666666CF80000; // 45(E) 44(D)
defparam rom0.INIT_23 = 256'h000000003A66C6C6DEC0C0C2663C0000_00000000F06060606878686266FE0000; // 47(G) 46(F)
defparam rom0.INIT_24 = 256'h000000003C18181818181818183C0000_00000000C6C6C6C6C6FEC6C6C6C60000; // 49(I) 48(H)
defparam rom0.INIT_25 = 256'h00000000E666666C78786C6666E60000_0000000078CCCCCC0C0C0C0C0C1E0000; // 4b(K) 4a(J)
defparam rom0.INIT_26 = 256'h00000000C6C6C6C6C6D6FEFEEEC60000_00000000FE6662606060606060F00000; // 4d(M) 4c(L)
defparam rom0.INIT_27 = 256'h000000007CC6C6C6C6C6C6C6C67C0000_00000000C6C6C6C6CEDEFEF6E6C60000; // 4f(O) 4e(N)
defparam rom0.INIT_28 = 256'h00000E0C7CDED6C6C6C6C6C6C67C0000_00000000F0606060607C666666FC0000; // 51(Q) 50(P)
defparam rom0.INIT_29 = 256'h000000007CC6C6060C3860C6C67C0000_00000000E66666666C7C666666FC0000; // 53(S) 52(R)
defparam rom0.INIT_2A = 256'h000000007CC6C6C6C6C6C6C6C6C60000_000000003C1818181818185A7E7E0000; // 55(U) 54(T)
defparam rom0.INIT_2B = 256'h000000006CEEFED6D6D6C6C6C6C60000_0000000010386CC6C6C6C6C6C6C60000; // 57(W) 56(V)
defparam rom0.INIT_2C = 256'h000000003C181818183C666666660000_00000000C6C66C7C38387C6CC6C60000; // 59(Y) 58(X)
defparam rom0.INIT_2D = 256'h000000003C30303030303030303C0000_00000000FEC6C26030180C86C6FE0000; // 5b([) 5a(Z)
defparam rom0.INIT_2E = 256'h000000003C0C0C0C0C0C0C0C0C3C0000_0000000002060E1C3870E0C080000000; // 5d(]) 5c(\)
defparam rom0.INIT_2F = 256'h0000FF00000000000000000000000000_000000000000000000000000C66C3810; // 5f(_) 5e(^)
defparam rom0.INIT_30 = 256'h0000000076CCCCCC7C0C780000000000_00000000000000000000000000183030; // 61(a) 60(`)
defparam rom0.INIT_31 = 256'h000000007CC6C0C0C0C67C0000000000_000000007C666666666C786060E00000; // 63(c) 62(b)
defparam rom0.INIT_32 = 256'h000000007CC6C0C0FEC67C0000000000_0000000076CCCCCCCC6C3C0C0C1C0000; // 65(e) 64(d)
defparam rom0.INIT_33 = 256'h0078CC0C7CCCCCCCCCCC760000000000_00000000F060606060F060646C380000; // 67(g) 66(f)
defparam rom0.INIT_34 = 256'h000000003C1818181818380018180000_00000000E666666666766C6060E00000; // 69(i) 68(h)
defparam rom0.INIT_35 = 256'h00000000E6666C78786C666060E00000_003C66660606060606060E0006060000; // 6b(k) 6a(j)
defparam rom0.INIT_36 = 256'h00000000C6D6D6D6D6FEEC0000000000_000000003C1818181818181818380000; // 6d(m) 6c(l)
defparam rom0.INIT_37 = 256'h000000007CC6C6C6C6C67C0000000000_00000000666666666666DC0000000000; // 6f(o) 6e(n)
defparam rom0.INIT_38 = 256'h001E0C0C7CCCCCCCCCCC760000000000_00F060607C6666666666DC0000000000; // 71(q) 70(p)
defparam rom0.INIT_39 = 256'h000000007CC60C3860C67C0000000000_00000000F06060606676DC0000000000; // 73(s) 72(r)
defparam rom0.INIT_3A = 256'h0000000076CCCCCCCCCCCC0000000000_000000001C3630303030FC3030100000; // 75(u) 74(t)
defparam rom0.INIT_3B = 256'h000000006CFED6D6D6C6C60000000000_00000000183C66666666660000000000; // 77(w) 76(v)
defparam rom0.INIT_3C = 256'h00F80C067EC6C6C6C6C6C60000000000_00000000C66C3838386CC60000000000; // 79(y) 78(x)
defparam rom0.INIT_3D = 256'h000000000E18181818701818180E0000_00000000FEC6603018CCFE0000000000; // 7b({) 7a(z)
defparam rom0.INIT_3E = 256'h0000000070181818180E181818700000_00000000181818181800181818180000; // 7d(}) 7c(|)
defparam rom0.INIT_3F = 256'h0000000000FEC6C6C66C381000000000_000000000000000000000000DC760000; // 7f() 7e(~)
 
defparam rom1.INIT_00 = 256'h0000000076CCCCCCCCCCCC0000CC0000_00007C060C3C66C2C0C0C0C2663C0000; // 81(�) 80(�)
defparam rom1.INIT_01 = 256'h0000000076CCCCCC7C0C78006C381000_000000007CC6C0C0FEC67C0030180C00; // 83(�) 82(�)
defparam rom1.INIT_02 = 256'h0000000076CCCCCC7C0C780018306000_0000000076CCCCCC7C0C780000CC0000; // 85(�) 84(�)
defparam rom1.INIT_03 = 256'h0000003C060C3C666060663C00000000_0000000076CCCCCC7C0C7800386C3800; // 87(�) 86(�)
defparam rom1.INIT_04 = 256'h000000007CC6C0C0FEC67C0000C60000_000000007CC6C0C0FEC67C006C381000; // 89(�) 88(�)
defparam rom1.INIT_05 = 256'h000000003C1818181818380000660000_000000007CC6C0C0FEC67C0018306000; // 8b(�) 8a(�)
defparam rom1.INIT_06 = 256'h000000003C1818181818380018306000_000000003C18181818183800663C1800; // 8d(�) 8c(�)
defparam rom1.INIT_07 = 256'h00000000C6C6C6FEC6C66C3800386C38_00000000C6C6C6FEC6C66C381000C600; // 8f(�) 8e(�)
defparam rom1.INIT_08 = 256'h000000006ED8D87E3676CC0000000000_00000000FE6660607C6066FE00603018; // 91(�) 90(�)
defparam rom1.INIT_09 = 256'h000000007CC6C6C6C6C67C006C381000_00000000CECCCCCCCCFECCCC6C3E0000; // 93(�) 92(�)
defparam rom1.INIT_0A = 256'h000000007CC6C6C6C6C67C0018306000_000000007CC6C6C6C6C67C0000C60000; // 95(�) 94(�)
defparam rom1.INIT_0B = 256'h0000000076CCCCCCCCCCCC0018306000_0000000076CCCCCCCCCCCC00CC783000; // 97(�) 96(�)
defparam rom1.INIT_0C = 256'h000000007CC6C6C6C6C6C6C67C00C600_00780C067EC6C6C6C6C6C60000C60000; // 99(�) 98(�)
defparam rom1.INIT_0D = 256'h0000000018183C66606060663C181800_000000007CC6C6C6C6C6C6C6C600C600; // 9b(�) 9a(�)
defparam rom1.INIT_0E = 256'h000000001818187E187E183C66660000_00000000FCE660606060F060646C3800; // 9d(�) 9c(�)
defparam rom1.INIT_0F = 256'h000070D818181818187E1818181B0E00_00000000C6CCCCCCDECCC4F8CCCCF800; // 9f(�) 9e(�)
defparam rom1.INIT_10 = 256'h000000003C1818181818380030180C00_0000000076CCCCCC7C0C780060301800; // a1(�) a0(�)
defparam rom1.INIT_11 = 256'h0000000076CCCCCCCCCCCC0060301800_000000007CC6C6C6C6C67C0060301800; // a3(�) a2(�)
defparam rom1.INIT_12 = 256'h00000000C6C6C6CEDEFEF6E6C600DC76_00000000666666666666DC00DC760000; // a5(�) a4(�)
defparam rom1.INIT_13 = 256'h0000000000000000007C00386C6C3800_0000000000000000007E003E6C6C3C00; // a7(�) a6(�)
defparam rom1.INIT_14 = 256'h0000000000C0C0C0C0FE000000000000_000000007CC6C6C06030300030300000; // a9(�) a8(�)
defparam rom1.INIT_15 = 256'h00003E180C86DC603018CCC6C2C0C000_000000000006060606FE000000000000; // ab(�) aa(�)
defparam rom1.INIT_16 = 256'h00000000183C3C3C1818180018180000_000006063E9ECE663018CCC6C2C0C000; // ad(�) ac(�)
defparam rom1.INIT_17 = 256'h000000000000D86C366CD80000000000_000000000000366CD86C360000000000; // af(�) ae(�)
defparam rom1.INIT_18 = 256'hAA55AA55AA55AA55AA55AA55AA55AA55_44114411441144114411441144114411; // b1(�) b0(�)
defparam rom1.INIT_19 = 256'h18181818181818181818181818181818_77DD77DD77DD77DD77DD77DD77DD77DD; // b3(�) b2(�)
defparam rom1.INIT_1A = 256'h1818181818181818F818F81818181818_1818181818181818F818181818181818; // b5(�) b4(�)
defparam rom1.INIT_1B = 256'h3636363636363636FE00000000000000_3636363636363636F636363636363636; // b7(�) b6(�)
defparam rom1.INIT_1C = 256'h3636363636363636F606F63636363636_1818181818181818F818F80000000000; // b9(�) b8(�)
defparam rom1.INIT_1D = 256'h3636363636363636F606FE0000000000_36363636363636363636363636363636; // bb(�) ba(�)
defparam rom1.INIT_1E = 256'h0000000000000000FE36363636363636_0000000000000000FE06F63636363636; // bd(�) bc(�)
defparam rom1.INIT_1F = 256'h1818181818181818F800000000000000_0000000000000000F818F81818181818; // bf(�) be(�)
defparam rom1.INIT_20 = 256'h0000000000000000FF18181818181818_00000000000000001F18181818181818; // c1(�) c0(�)
defparam rom1.INIT_21 = 256'h18181818181818181F18181818181818_1818181818181818FF00000000000000; // c3(�) c2(�)
defparam rom1.INIT_22 = 256'h1818181818181818FF18181818181818_0000000000000000FF00000000000000; // c5(�) c4(�)
defparam rom1.INIT_23 = 256'h36363636363636363736363636363636_18181818181818181F181F1818181818; // c7(�) c6(�)
defparam rom1.INIT_24 = 256'h363636363636363637303F0000000000_00000000000000003F30373636363636; // c9(�) c8(�)
defparam rom1.INIT_25 = 256'h3636363636363636F700FF0000000000_0000000000000000FF00F73636363636; // cb(�) ca(�)
defparam rom1.INIT_26 = 256'h0000000000000000FF00FF0000000000_36363636363636363730373636363636; // cd(�) cc(�)
defparam rom1.INIT_27 = 256'h0000000000000000FF00FF1818181818_3636363636363636F700F73636363636; // cf(�) ce(�)
defparam rom1.INIT_28 = 256'h1818181818181818FF00FF0000000000_0000000000000000FF36363636363636; // d1(�) d0(�)
defparam rom1.INIT_29 = 256'h00000000000000003F36363636363636_3636363636363636FF00000000000000; // d3(�) d2(�)
defparam rom1.INIT_2A = 256'h18181818181818181F181F0000000000_00000000000000001F181F1818181818; // d5(�) d4(�)
defparam rom1.INIT_2B = 256'h3636363636363636FF36363636363636_36363636363636363F00000000000000; // d7(�) d6(�)
defparam rom1.INIT_2C = 256'h0000000000000000F818181818181818_1818181818181818FF18FF1818181818; // d9(�) d8(�)
defparam rom1.INIT_2D = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF_18181818181818181F00000000000000; // db(�) da(�)
defparam rom1.INIT_2E = 256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0_FFFFFFFFFFFFFFFFFF00000000000000; // dd(�) dc(�)
defparam rom1.INIT_2F = 256'h000000000000000000FFFFFFFFFFFFFF_0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F; // df(�) de(�)
defparam rom1.INIT_30 = 256'h00000000CCC6C6C6CCD8CCCCCC780000_0000000076DCD8D8D8DC760000000000; // e1(�) e0(�)
defparam rom1.INIT_31 = 256'h000000006C6C6C6C6C6C6CFE00000000_00000000C0C0C0C0C0C0C0C6C6FE0000; // e3(�) e2(�)
defparam rom1.INIT_32 = 256'h0000000070D8D8D8D8D87E0000000000_00000000FEC66030183060C6FE000000; // e5(�) e4(�)
defparam rom1.INIT_33 = 256'h00000000181818181818DC7600000000_000000C060607C666666666600000000; // e7(�) e6(�)
defparam rom1.INIT_34 = 256'h00000000386CC6C6FEC6C66C38000000_000000007E183C6666663C187E000000; // e9(�) e8(�)
defparam rom1.INIT_35 = 256'h000000003C666666663E0C18301E0000_00000000EE6C6C6C6CC6C6C66C380000; // eb(�) ea(�)
defparam rom1.INIT_36 = 256'h00000000C0607EF3DBDB7E0603000000_0000000000007EDBDBDB7E0000000000; // ed(�) ec(�)
defparam rom1.INIT_37 = 256'h00000000C6C6C6C6C6C6C6C67C000000_000000001C306060607C6060301C0000; // ef(�) ee(�)
defparam rom1.INIT_38 = 256'h00000000FF000018187E181800000000_0000000000FE0000FE0000FE00000000; // f1(�) f0(�)
defparam rom1.INIT_39 = 256'h000000007E000C18306030180C000000_000000007E0030180C060C1830000000; // f3(�) f2(�)
defparam rom1.INIT_3A = 256'h0000000070D8D8D81818181818181818_18181818181818181818181B1B0E0000; // f5(�) f4(�)
defparam rom1.INIT_3B = 256'h000000000000DC7600DC760000000000_00000000001818007E00181800000000; // f7(�) f6(�)
defparam rom1.INIT_3C = 256'h00000000000000181800000000000000_0000000000000000000000386C6C3800; // f9(�) f8(�)
defparam rom1.INIT_3D = 256'h000000001C3C6C6CEC0C0C0C0C0C0F00_00000000000000180000000000000000; // fb(�) fa(�)
defparam rom1.INIT_3E = 256'h000000000000000000F8C86030D87000_0000000000000000006C6C6C6C6CD800; // fd(�) fc(�)
defparam rom1.INIT_3F = 256'h00000000000000000000000000000000_00000000007C7C7C7C7C7C7C00000000; // ff(�) fe(�)
 
// Assignments
assign rw = ~we;
assign rdata = addr[11] ? rdata1 : rdata0;
endmodule
/trunk/impl/spartan3an-sk/rtl/vga/ram2k_b16.v
0,0 → 1,32
`timescale 1ns/10ps
 
module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
 
// Net declarations
wire dp;
wire rw;
 
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (rw));
 
defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
// Assignments
assign rw = ~we;
endmodule
/trunk/impl/spartan3an-sk/rtl/ddr2cntrl/ddr2sdram.v
0,0 → 1,381
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: not supported by cvs2svn $
// \ \ Application : MIG
// / / Filename : vlog_xst_bl4_main_0.v
// /___/ /\ Date Last Modified : $Date: 2008-07-03 09:06:01 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
// Device : Spartan-3/3A
// Design Name : DDR2 SDRAM
// Purpose : This modules has the instantiation for top and test_bench
// modules.
///////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns/100ps
`include "parameters.v"
 
module ddr2_sdram_zet_cntrlr
(
inout [15:0] cntrl0_DDR2_DQ,
output [12:0] cntrl0_DDR2_A,
output [1:0] cntrl0_DDR2_BA,
output cntrl0_DDR2_CK,
output cntrl0_DDR2_CK_N,
output cntrl0_DDR2_CKE,
output cntrl0_DDR2_CS_N,
output cntrl0_DDR2_RAS_N,
output cntrl0_DDR2_CAS_N,
output cntrl0_DDR2_WE_N,
output cntrl0_DDR2_ODT,
output [1:0] cntrl0_DDR2_DM,
inout [1:0] cntrl0_DDR2_DQS,
inout [1:0] cntrl0_DDR2_DQS_N,
input sys_clk, // 133Mhz
input cntrl0_rst_dqs_div_in, // loopback
output cntrl0_rst_dqs_div_out, // loopback
input board_reset, // board reset
 
input cpu_clk,
input [19:0] addr,
input [15:0] wr_data,
input we,
input byte_m,
output reg [15:0] rd_data,
output reg mem_rst,
input enable,
output ready
);
 
// Net declarations
wire auto_ref_req;
wire clk_int;
wire sys_rst90;
wire sys_rst180;
wire clk90_int;
wire burst_done_val1;
wire init_val1;
wire ar_done_val1;
wire user_ack1;
wire user_data_val1;
wire [((`data_width*2)-1):0] user_output_data;
wire [((`row_address +
`col_ap_width + `bank_address)-1):0] usr_addr1, usr_addr2;
wire [3:0] user_cmd1;
wire [((`data_width*2)-1):0] usr_data1, usr_data2;
wire [((`data_mask_width*2)-1):0] usr_mask1;
wire [19:0] addr1;
 
wire sys_rst;
wire [7:0] byte_h, byte_l;
wire col_grp_ch;
wire row_change;
 
reg old_clk, start_cmd;
reg [3:0] rd_state, next_rd_state, wr_state, next_wr_state;
reg [1:0] data_state, next_data_state;
reg [1:0] init_state, next_init_state;
reg burst_rd, burst_wr;
reg [3:0] u_cmd_rd, u_cmd_wr, u_cmd_init;
wire [((`row_address +
`col_ap_width + `bank_address)-1):0] u1_address;
reg [((`row_address +
`col_ap_width + `bank_address)-1):0] u1_read;
reg [((`row_address +
`col_ap_width + `bank_address)-1):0] u1_write;
reg [((`data_width*2)-1):0] u1_data_i;
reg [((`data_mask_width*2)-1):0] u1_data_m;
reg row_rd_pass, row_wr_pass;
reg eff_ready;
 
parameter nop_cmd = 4'h0;
parameter init_cmd = 4'h2;
parameter write_cmd = 4'h4;
parameter read_cmd = 4'h6;
 
parameter write_st = 4'd0;
parameter read_st = 4'd0;
parameter wait_ack = 4'd1;
parameter wait_addr1 = 4'd2;
parameter wait_addr2 = 4'd3;
parameter snd_addr1 = 4'd4;
parameter snd_addr2 = 4'd5;
parameter snd_burst1 = 4'd6;
parameter snd_burst2 = 4'd7;
parameter end_burst = 4'd8;
parameter nop_op = 4'd9;
parameter wait_nack = 4'd10;
parameter wr_done = 4'd11;
parameter wait_data = 4'd10;
parameter read_data1 = 4'd11;
parameter wait_data2 = 4'd12;
parameter read_data2 = 4'd13;
parameter wait_rd_nack = 4'd14;
parameter rd_done = 4'd15;
 
parameter init_st = 2'd0;
parameter nop_init = 2'd1;
parameter init_done = 2'd2;
 
parameter snd_word1 = 2'd0;
parameter snd_word2 = 2'd1;
parameter snd_word3 = 2'd2;
parameter snd_word4 = 2'd3;
 
// Module instantiations
vlog_xst_bl4 cntrl0
(
.cntrl0_DDR2_DQ (cntrl0_DDR2_DQ),
.cntrl0_DDR2_A (cntrl0_DDR2_A),
.cntrl0_DDR2_BA (cntrl0_DDR2_BA),
.cntrl0_DDR2_CK (cntrl0_DDR2_CK),
.cntrl0_DDR2_CK_N (cntrl0_DDR2_CK_N),
.cntrl0_DDR2_CKE (cntrl0_DDR2_CKE),
.cntrl0_DDR2_CS_N (cntrl0_DDR2_CS_N),
.cntrl0_DDR2_RAS_N (cntrl0_DDR2_RAS_N),
.cntrl0_DDR2_CAS_N (cntrl0_DDR2_CAS_N),
.cntrl0_DDR2_WE_N (cntrl0_DDR2_WE_N),
.cntrl0_DDR2_ODT (cntrl0_DDR2_ODT),
.cntrl0_DDR2_DM (cntrl0_DDR2_DM),
.cntrl0_DDR2_DQS (cntrl0_DDR2_DQS),
.cntrl0_DDR2_DQS_N (cntrl0_DDR2_DQS_N),
.SYS_CLK (sys_clk),
.cntrl0_rst_dqs_div_in (cntrl0_rst_dqs_div_in),
.cntrl0_rst_dqs_div_out (cntrl0_rst_dqs_div_out),
.reset_in_n (board_reset),
 
.auto_ref_req (auto_ref_req), // output from controller
.clk_0 (clk_int), // from DCM
.sys_rst90 (sys_rst90), // from DCM
.sys_rst180 (sys_rst180), // from DCM
.clk90_0 (clk90_int), // from DCM
.burst_done_val1 (burst_done_val1), // input to controller
.init_val1 (init_val1), // output from controller
.ar_done_val1 (ar_done_val1), // output from controller
.user_ack1 (user_ack1), // output from controller
.user_data_val1 (user_data_val1), // output from controller
.user_output_data (user_output_data),// output from controller
.u1_address (u1_address), // input to controller
.user_cmd1 (user_cmd1), // input to controller
.u1_data_i (u1_data_i), // input to controller
.u1_data_m (u1_data_m) // input to controller
);
 
// Assignments
assign sys_rst = sys_rst90 | sys_rst180;
assign usr_addr1 = { 3'b0, addr[19:10], 1'b0, addr[9:0], 2'b00 };
assign addr1 = addr + 20'd1;
assign usr_addr2 = { 3'b0, addr1[19:10], 1'b0, addr1[9:0], 2'b00 };
 
assign usr_mask1 = (byte_m || col_grp_ch) ? 4'b1011 : 4'b1010;
assign usr_data1 = { 8'b0, wr_data[7:0], 8'b0, wr_data[15:8] };
assign usr_data2 = { 8'b0, wr_data[15:8], 16'b0 };
 
assign burst_done_val1 = we ? burst_rd : burst_wr;
assign user_cmd1 = mem_rst ? u_cmd_init : (we ? u_cmd_rd : u_cmd_wr);
assign byte_h = user_output_data[7:0];
assign byte_l = user_output_data[23:16];
assign col_grp_ch = (addr[1:0]==2'b11 && !byte_m && !row_change);
assign row_change = (addr1[10] ^ addr[10]) && !byte_m;
assign ready = (we ? (next_rd_state==rd_done)
: (next_wr_state==wr_done))
|| !enable;
assign u1_address = we ? u1_read : u1_write;
 
// Behaviour
// Write command
always @(wr_state or user_ack1 or mem_rst or usr_addr1 or usr_addr2
/* or row_wr_pass or col_grp_ch or next_wr_state or row_change */)
if (mem_rst)
begin
u_cmd_wr <= nop_cmd;
burst_wr <= 1'b0;
next_wr_state <= wr_done;
row_wr_pass <= 1'b0;
end
else
case (wr_state)
write_st: if (!user_ack1)
begin
u_cmd_wr <= write_cmd;
u1_write <= row_wr_pass ? usr_addr2 : usr_addr1;
next_wr_state <= wait_ack;
end else next_wr_state <= write_st;
wait_ack: if (user_ack1) next_wr_state <= wait_addr1;
wait_addr1: next_wr_state <= wait_addr2;
wait_addr2: next_wr_state <= col_grp_ch ? snd_addr1 : snd_burst1;
snd_addr1: begin u1_write <= usr_addr2; next_wr_state <= snd_addr2; end
snd_addr2: next_wr_state <= snd_burst1;
snd_burst1: begin burst_wr <= 1'b1; next_wr_state <= snd_burst2; end
snd_burst2: next_wr_state <= end_burst;
end_burst: begin burst_wr <= 1'b0; next_wr_state <= nop_op; end
nop_op: begin u_cmd_wr <= nop_cmd; next_wr_state <= wait_nack; end
wait_nack: if (!user_ack1 && next_wr_state==wait_nack)
begin
if (row_change && !row_wr_pass)
begin
next_wr_state <= write_st;
row_wr_pass <= 1'b1;
end
else
begin
next_wr_state <= wr_done;
row_wr_pass <= 1'b0;
end
end
default: next_wr_state <= write_st;
endcase
 
// Send data
always @(data_state or user_ack1 or usr_mask1 or usr_data1
/* or col_grp_ch or usr_data2 or mem_rst or row_change
or row_wr_pass or wr_state */)
if (mem_rst) next_data_state <= snd_word4;
else
case (data_state)
snd_word1: if (user_ack1)
begin
u1_data_m <= row_change ? 4'b1011 : usr_mask1;
u1_data_i <= row_wr_pass ? usr_data2 : usr_data1;
next_data_state <= snd_word2;
end
snd_word2: begin u1_data_m <= 4'b1111; next_data_state <= snd_word3; end
snd_word3:
begin
u1_data_m <= col_grp_ch ? 4'b1011 : 4'b1111;
u1_data_i <= usr_data2;
next_data_state <= snd_word4;
end
default:
begin
u1_data_m <= 4'b1111;
if (wr_state==wait_ack && user_ack1) next_data_state <= snd_word1;
end
endcase
 
// Read command
always @(rd_state or user_ack1 or user_data_val1 or mem_rst
/* or row_rd_pass or usr_addr2 or usr_addr1 or col_grp_ch or byte_m
or byte_l or byte_h or next_rd_state or row_change */)
if (mem_rst)
begin
u_cmd_rd <= nop_cmd;
burst_rd <= 1'b0;
next_rd_state <= rd_done;
row_rd_pass <= 1'b0;
end
else
case (rd_state)
read_st: if (!user_ack1)
begin
u_cmd_rd <= read_cmd;
u1_read <= row_rd_pass ? usr_addr2 : usr_addr1;
next_rd_state <= wait_ack;
end else next_rd_state <= read_st;
wait_ack: if (user_ack1) next_rd_state <= wait_addr1;
wait_addr1: next_rd_state <= wait_addr2;
wait_addr2: next_rd_state <= col_grp_ch ? snd_addr1 : snd_burst1;
snd_addr1: begin u1_read <= usr_addr2; next_rd_state <= snd_addr2; end
snd_addr2: next_rd_state <= snd_burst1;
snd_burst1: begin burst_rd <= 1'b1; next_rd_state <= snd_burst2; end
snd_burst2: next_rd_state <= end_burst;
end_burst: begin burst_rd <= 1'b0; next_rd_state <= nop_op; end
nop_op: begin u_cmd_rd <= nop_cmd; next_rd_state <= wait_data; end
wait_data: if (user_data_val1) next_rd_state <= read_data1;
read_data1:
begin
rd_data <= byte_m ? { {8{byte_l[7]}}, byte_l }
: row_rd_pass ? { byte_l, rd_data[7:0] } : { byte_h, byte_l };
next_rd_state <= col_grp_ch ? wait_data2 : wait_rd_nack;
end
wait_data2: next_rd_state <= read_data2;
read_data2:
begin
rd_data[15:8] <= byte_l;
next_rd_state <= wait_rd_nack;
end
wait_rd_nack: if (!user_ack1 && next_rd_state==wait_rd_nack)
begin
if (row_change && !row_rd_pass)
begin
next_rd_state <= read_st;
row_rd_pass <= 1'b1;
end
else
begin
next_rd_state <= rd_done;
row_rd_pass <= 1'b0;
end
end
default: next_rd_state <= read_st;
endcase
 
// Init command
always @(init_state or init_val1 or sys_rst)
if (sys_rst)
begin
u_cmd_init <= nop_cmd;
next_init_state <= init_st;
end
else
case (init_state)
init_st: begin u_cmd_init <= init_cmd; next_init_state <= nop_init; end
nop_init:
begin
u_cmd_init <= nop_cmd;
if (init_val1) next_init_state <= init_done;
end
default: next_init_state <= init_st;
endcase
 
always @(negedge clk_int)
if (sys_rst)
begin
init_state <= init_done;
wr_state <= wait_nack;
rd_state <= wait_rd_nack;
mem_rst <= 1'b1;
end
else
if (mem_rst)
begin
if (next_init_state==init_done) mem_rst <= 1'b0;
else init_state <= next_init_state;
end
else
if (start_cmd)
begin
if (we) rd_state <= read_st;
else wr_state <= write_st;
end
else
begin
if (we) rd_state <= (next_rd_state==rd_done) ? rd_state : next_rd_state;
else wr_state <= (next_wr_state==wr_done) ? wr_state : next_wr_state;
end
 
always @(posedge clk90_int)
if (sys_rst) data_state <= snd_word4;
else data_state <= next_data_state;
 
// start_cmd signal
always @(posedge clk_int)
if (mem_rst || !enable)
begin
old_clk <= 1'b0;
start_cmd <= 1'b0;
end
else
begin
if (cpu_clk && !old_clk && eff_ready) start_cmd <= 1'b1;
else start_cmd <= 1'b0;
old_clk <= cpu_clk;
end
always @(posedge cpu_clk) eff_ready <= ready;
endmodule
/trunk/impl/spartan3an-sk/rtl/ddr2cntrl/vlog_xst_bl4.v
0,0 → 1,116
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: not supported by cvs2svn $
// \ \ Application : MIG
// / / Filename : vlog_xst_bl4.v
// /___/ /\ Date Last Modified : $Date: 2008-07-03 09:06:01 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
// Device : Spartan-3/3A
// Design Name : DDR2 SDRAM
// Purpose : This module has the instantiations main and infrastructure_top
// modules
///////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns/100ps
module vlog_xst_bl4
(
inout [15:0] cntrl0_DDR2_DQ,
output [12:0] cntrl0_DDR2_A,
output [1:0] cntrl0_DDR2_BA,
output cntrl0_DDR2_CK,
output cntrl0_DDR2_CK_N,
output cntrl0_DDR2_CKE,
output cntrl0_DDR2_CS_N,
output cntrl0_DDR2_RAS_N,
output cntrl0_DDR2_CAS_N,
output cntrl0_DDR2_WE_N,
output cntrl0_DDR2_ODT,
output [1:0] cntrl0_DDR2_DM,
inout [1:0] cntrl0_DDR2_DQS,
inout [1:0] cntrl0_DDR2_DQS_N,
input SYS_CLK, // 133Mhz
input cntrl0_rst_dqs_div_in, // loopback
output cntrl0_rst_dqs_div_out, // loopback
input reset_in_n, // South Button
output auto_ref_req,
output clk_0,
output sys_rst90,
output sys_rst180,
output clk90_0,
input burst_done_val1,
output init_val1,
output ar_done_val1,
output user_ack1,
output user_data_val1,
output [31:0] user_output_data,
input [25:0] u1_address,
input [3:0] user_cmd1,
input [31:0] u1_data_i,
input [3:0] u1_data_m
);
 
wire wait_200us;
wire sys_rst;
wire [4:0] delay_sel_val;
 
vlog_xst_bl4_top_0 top0
(
.auto_ref_req (auto_ref_req),
.wait_200us (wait_200us),
.rst_dqs_div_in (cntrl0_rst_dqs_div_in),
.rst_dqs_div_out (cntrl0_rst_dqs_div_out),
.user_input_data (u1_data_i),
.user_data_mask(u1_data_m),
.user_output_data (user_output_data),
.user_data_valid (user_data_val1),
.user_input_address (u1_address[25:0]),
.user_command_register (user_cmd1),
.user_cmd_ack (user_ack1),
.burst_done (burst_done_val1),
.init_val (init_val1),
.ar_done (ar_done_val1),
.DDR2_DQS (cntrl0_DDR2_DQS),
.DDR2_DQS_N (cntrl0_DDR2_DQS_N),
.DDR2_DQ (cntrl0_DDR2_DQ),
.DDR2_CKE (cntrl0_DDR2_CKE),
.DDR2_CS_N (cntrl0_DDR2_CS_N),
.DDR2_RAS_N (cntrl0_DDR2_RAS_N),
.DDR2_CAS_N (cntrl0_DDR2_CAS_N),
.DDR2_WE_N (cntrl0_DDR2_WE_N),
.DDR2_DM (cntrl0_DDR2_DM),
 
.DDR2_ODT (cntrl0_DDR2_ODT),
.DDR2_BA (cntrl0_DDR2_BA),
.DDR2_A (cntrl0_DDR2_A),
.DDR2_CK (cntrl0_DDR2_CK),
.DDR2_CK_N (cntrl0_DDR2_CK_N),
.clk_int (clk_0),
.clk90_int (clk90_0),
.delay_sel_val (delay_sel_val),
.sys_rst (sys_rst),
.sys_rst90 (sys_rst90),
.sys_rst180 (sys_rst180)
);
 
 
vlog_xst_bl4_infrastructure_top infrastructure_top0
(
.SYS_CLK (SYS_CLK),
.reset_in_n (reset_in_n),
.wait_200us_rout (wait_200us),
.delay_sel_val1_val(delay_sel_val),
.sys_rst_val (sys_rst),
.sys_rst90_val (sys_rst90),
.clk_int_val (clk_0),
.clk90_int_val (clk90_0),
.sys_rst180_val (sys_rst180)
);
 
endmodule
/trunk/impl/spartan3an-sk/sim/memory_tb.v
0,0 → 1,336
 
`timescale 1ns/100ps
`include "parameters.v"
module memory_tb;
 
// Net and register declaration
reg ddr_clk, cpu_clk;
wire ddr_clkb;
reg rst;
 
reg [19:0] addr;
reg [15:0] wr_data;
reg we;
reg byte_m;
wire [15:0] rd_data;
wire mem_rst;
wire ready;
 
wire [`clk_width-1 : 0] ddr2_clk;
wire [`clk_width-1 : 0] ddr2_clkb;
 
wire [`data_strobe_width-1 : 0] ddr_dqs_fpga;
wire [`data_strobe_width-1 : 0] ddr_dqs_fpga_n;
wire [`data_strobe_width-1 : 0] ddr_dqs_sdram_n;
wire [`data_strobe_width-1 : 0] ddr_dqs_sdram;
wire [`data_width-1:0] ddr_dq_fpga;
wire [`data_width-1:0] ddr_dq_sdram;
wire [`row_address-1:0] ddr2_address;
wire [`cke_width-1 : 0]ddr2_cke;
wire [0 : 0]ddr2_csb;
wire ddr2_web;
wire ddr2_rasb;
wire ddr2_casb;
wire [`bank_address - 1:0] ddr2_ba;
wire ddr2_ODT;
 
wire [`data_mask_width-1:0] ddr2_dm;
wire [2:0] CMD;
reg enable_o;
reg enable;
 
wire rst_dqs_div_in;
wire rst_dqs_div_out;
 
wire NF_WE;
wire NF_CE;
wire NF_OE;
wire NF_BYTE;
wire [21:1] NF_A;
wire [15:0] NF_D;
 
reg sys_clk;
 
// Module instantiation
memory mem_ctrlr_0 (
.cntrl0_DDR2_DQ (ddr_dq_fpga),
.cntrl0_DDR2_A (ddr2_address),
.cntrl0_DDR2_BA (ddr2_ba),
.cntrl0_DDR2_CK (ddr2_clk),
.cntrl0_DDR2_CK_N (ddr2_clkb),
.cntrl0_DDR2_CKE (ddr2_cke),
.cntrl0_DDR2_CS_N (ddr2_csb),
.cntrl0_DDR2_RAS_N (ddr2_rasb),
.cntrl0_DDR2_CAS_N (ddr2_casb),
.cntrl0_DDR2_WE_N (ddr2_web),
.cntrl0_DDR2_ODT (ddr2_ODT),
.cntrl0_DDR2_DM (ddr2_dm),
.cntrl0_DDR2_DQS (ddr_dqs_fpga),
.cntrl0_DDR2_DQS_N (ddr_dqs_fpga_n),
.cntrl0_rst_dqs_div_in (rst_dqs_div_out), // loopback
.cntrl0_rst_dqs_div_out (rst_dqs_div_out), // loopback
.NF_WE (NF_WE),
.NF_CE (NF_CE),
.NF_OE (NF_OE),
.NF_BYTE (NF_BYTE),
.NF_A (NF_A),
.NF_D (NF_D),
 
.ddr_clk (ddr_clk),
.sys_clk (sys_clk),
.cpu_clk (cpu_clk),
.mem_rst (mem_rst),
.board_reset (rst),
 
.addr (addr),
.wr_data (wr_data),
.we (we),
.byte_m (byte_m),
.rd_data (rd_data),
.ready (ready)
);
 
ddr2 X16_0 (
.ck (ddr2_clk[0]),
.ck_n (ddr2_clkb[0]),
.cke (ddr2_cke),
.cs_n (ddr2_csb),
.ras_n (ddr2_rasb),
.cas_n (ddr2_casb),
.we_n (ddr2_web),
.dm_rdqs(ddr2_dm[1:0]),
.ba (ddr2_ba),
.addr (ddr2_address),
.dq (ddr_dq_sdram[15:0]),
.dqs (ddr_dqs_sdram[1:0]),
.dqs_n ( ddr_dqs_sdram_n[1:0]),
.rdqs_n (),
.odt (ddr2_ODT)
);
 
test_stub flash_rom0 (
.W_N (NF_WE),
.E_N (NF_CE),
.G_N (NF_OE),
.Byte_N (NF_BYTE),
.A (NF_A),
.DQ (NF_D[14:0]),
.DQ15A_1 (NF_D[15])
);
 
 
// Assignments
assign ddr_dqs_fpga = (enable == 1'b1) ? ddr_dqs_sdram : `data_strobe_width'hZ;
assign ddr_dq_fpga = ( enable == 1'b1) ? ddr_dq_sdram : `data_width'hZ;
 
assign ddr_dqs_sdram = (enable == 1'b0) ? ddr_dqs_fpga : `data_strobe_width'hZ;
assign ddr_dq_sdram = (enable == 1'b0) ? ddr_dq_fpga : `data_width'hZ;
 
assign ddr_dqs_fpga_n = (enable == 1'b1) ? ddr_dqs_sdram_n : `data_strobe_width'hZ;
assign ddr_dqs_sdram_n = (enable == 1'b0) ? ddr_dqs_fpga_n : `data_strobe_width'hZ;
 
assign CMD = {ddr2_rasb,ddr2_casb,ddr2_web};
assign ddr_clkb = ~ ddr_clk;
 
// Behaviour
initial enable = 1'b0;
 
// Clock Generation
initial
begin
ddr_clk <= 1'b1;
cpu_clk <= 1'b1;
sys_clk <= 1'b1;
end
 
// RESET Generation
initial
begin
rst = 1'b1;
we <= 1'b1;
# 37.593984962406 rst = 1'b0;
@(negedge mem_rst)
 
@(posedge cpu_clk)
addr <= 20'h18b2e;
byte_m <= 1'b0;
we <= 1'b0;
wr_data <= 16'h0cd3;
 
@(posedge cpu_clk)
addr <= 20'h18b2e;
byte_m <= 1'b0;
we <= 1'b0;
wr_data <= 16'h8cf1;
 
// Flash test
@(posedge cpu_clk)
addr <= 20'hf0011;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'hf0011;
byte_m <= 1'b1;
@(posedge cpu_clk)
addr <= 20'hf0010;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'hf0010;
byte_m <= 1'b1;
@(posedge cpu_clk)
addr <= 20'hf0013;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'hf0013;
byte_m <= 1'b1;
 
// RAM - write test
// Write - word in even address
@(posedge cpu_clk)
addr <= 20'h00004;
wr_data <= 16'h4321;
we <= 1'b0;
byte_m <= 1'b0;
// Write - byte in even address
@(posedge cpu_clk)
addr <= 20'h00006;
wr_data <= 16'h8765;
we <= 1'b0;
byte_m <= 1'b1;
// Write - word in odd address - without group/col change
@(posedge cpu_clk)
addr <= 20'h00009;
wr_data <= 16'h4321;
we <= 1'b0;
byte_m <= 1'b0;
// Write - byte in odd address - without group/col change
@(posedge cpu_clk)
addr <= 20'h0000b;
wr_data <= 16'h4321;
we <= 1'b0;
byte_m <= 1'b1;
 
// RAM - read test
// Read - word in even address
@(posedge cpu_clk)
addr <= 20'h00004;
we <= 1'b1;
byte_m <= 1'b0;
// Read - byte in odd address - without group/col change
@(posedge cpu_clk)
addr <= 20'h00005;
byte_m <= 1'b1;
// Read - word in odd address - without group/col change
@(posedge cpu_clk)
addr <= 20'h00005;
byte_m <= 1'b0;
// Read - word in even address
@(posedge cpu_clk)
addr <= 20'h00006;
byte_m <= 1'b0;
// Read - byte in even address
@(posedge cpu_clk)
addr <= 20'h00006;
byte_m <= 1'b1;
@(posedge cpu_clk)
addr <= 20'h00008;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'h0000a;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'h0000c;
byte_m <= 1'b0;
 
// Write - byte in odd address with group change
@(posedge cpu_clk)
addr <= 20'h00013;
byte_m <= 1'b1;
we <= 1'b0;
wr_data <= 16'h4321;
// Read - byte in odd address with group change
@(posedge cpu_clk)
addr <= 20'h00013;
we <= 1'b1;
byte_m <= 1'b1;
@(posedge cpu_clk)
addr <= 20'h00012;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'h00014;
byte_m <= 1'b0;
 
// Write - word in odd address with group change
@(posedge cpu_clk)
addr <= 20'h00017;
byte_m <= 1'b0;
we <= 1'b0;
wr_data <= 16'h4321;
// Read - word in odd address with group change
@(posedge cpu_clk)
addr <= 20'h00017;
byte_m <= 1'b0;
we <= 1'b1;
@(posedge cpu_clk)
addr <= 20'h00016;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'h00018;
byte_m <= 1'b0;
 
// Write - byte in odd address with col change
@(posedge cpu_clk)
addr <= 20'h003ff;
byte_m <= 1'b1;
we <= 1'b0;
wr_data <= 16'h4321;
// Read - byte in odd address with col change
@(posedge cpu_clk)
addr <= 20'h003ff;
byte_m <= 1'b1;
we <= 1'b1;
@(posedge cpu_clk)
addr <= 20'h003fe;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'h00400;
byte_m <= 1'b0;
 
// Write - word in odd address with col change
@(posedge cpu_clk)
addr <= 20'h007ff;
byte_m <= 1'b0;
we <= 1'b0;
wr_data <= 16'h4321;
// Read - word in odd address with col change
@(posedge cpu_clk)
@(posedge cpu_clk)
addr <= 20'h007ff;
byte_m <= 1'b0;
we <= 1'b1;
@(posedge cpu_clk)
@(posedge cpu_clk)
addr <= 20'h007fe;
byte_m <= 1'b0;
@(posedge cpu_clk)
addr <= 20'h00800;
byte_m <= 1'b0;
end
 
always @(posedge ddr_clk)
begin
if (CMD == 3'b100) // -- Write
enable_o <= 1'b0;
else if(CMD == 3'b101) // -- Read
enable_o <= 1'b1;
else
enable_o <= enable_o;
end
 
always @(posedge ddr_clk) enable <= enable_o;
 
always # 3.7593984962406 ddr_clk <= ~ ddr_clk; // 133 MHZ
always # 150 cpu_clk <= ~cpu_clk; // 3.33Mhz
always # 10.1 sys_clk <= ~sys_clk; // 50Mhz
endmodule
/trunk/impl/spartan3an-sk/sim/flash-prom/test_stub.vhd
0,0 → 1,77
 
 
library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
use work.generic_data.all;
 
entity test_stub is
 
port (
-- control pins
W_N : in std_logic;
E_N : in std_logic;
G_N : in std_logic;
Byte_N : in std_logic;
RP : in std_logic;
RB : out std_logic;
-- buses
A : in std_logic_vector(Addr_Bus_Dim - 1 downto 0);
DQ : inout std_logic_vector(Data_Bus_Dim - 2 downto 0);
-- other pins
DQ15A_1 : inout std_logic
);
 
end test_stub;
 
architecture arch_stim of test_stub is
 
Component M29DW323D
port
(
E_N, Byte_N, G_N, W_N : in std_logic;
A: in std_logic_vector(Addr_Bus_dim - 1 downto 0);
DQ: inout std_logic_vector(14 downto 0);
RP_N,Vcc, Vss, VppWP_N: in real;
RB: out std_logic;
DQ15A_1 : inout std_logic
);
end component;
 
signal RP_N: real := 3.0;
signal Vcc: real := 3.0;
signal Vss: real := 0.0;
signal VppWP_N: real := 3.0;
 
 
begin
 
 
mod_ule : M29DW323D
port map
(
Vcc => Vcc,
Vss => Vss,
VppWP_N => VppWP_N,
RP_N => RP_N,
W_N => W_N,
E_N => E_N,
G_N => G_N,
 
Byte_N => Byte_N,
RB => RB,
A => A,
DQ => DQ,
DQ15A_1 => DQ15A_1
);
 
reset_flash : process( RP, RP_N )
begin
if RP = '1' then
RP_N <= 3.0;
else RP_N <= 0.0;
end if;
end process;
 
end arch_stim; -- architecture body
/trunk/impl/spartan3an-sk/sim/modelsim/tb.do
0,0 → 1,47
vdel -all -lib work
vlib work
 
# Hardware part
 
vlog -lint -work work +incdir+../../rtl/ ../../rtl/ddr2cntrl/ddr2sdram.v ../../rtl/ddr2cntrl/vlog_xst_bl4.v ../../rtl/ddr2cntrl/vlog_xst_bl4_top_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_controller_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_data_path_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_data_read_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_rd_gray_ctr.v ../../rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_RAM8D_1.v ../../rtl/ddr2cntrl/vlog_xst_bl4_fifo_1_wr_en_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_data_read_controller_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_dqs_delay.v ../../rtl/ddr2cntrl/vlog_xst_bl4_fifo_0_wr_en_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_top_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_cal_top.v ../../rtl/ddr2cntrl/vlog_xst_bl4_tap_dly_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_cal_ctl_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_clk_dcm.v ../../rtl/ddr2cntrl/vlog_xst_bl4_wr_gray_ctr.v ../../rtl/ddr2cntrl/vlog_xst_bl4_data_write_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_data_path_rst.v ../../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure.v ../../rtl/ddr2cntrl/vlog_xst_bl4_iobs_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_infrastructure_iobs_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_controller_iobs_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_s3_dqs_iob.v ../../rtl/ddr2cntrl/vlog_xst_bl4_s3_ddr_iob.v ../../rtl/ddr2cntrl/vlog_xst_bl4_data_path_iobs_0.v ../../rtl/ddr2cntrl/vlog_xst_bl4_ddr2_dm_0.v
vlog -lint -work work ../../rtl/flash-prom/flashcntrlr.v
vlog -lint -work work ../../rtl/memory.v
 
vlog -lint -work work ../../rtl/vga/vdu.v ../../rtl/vga/char_rom_b16.v ../../rtl/vga/ram2k_b16_attr.v ../../rtl/vga/ram2k_b16.v
 
vlog -lint -work work +incdir+../../../../rtl-model ../../../../rtl-model/regfile.v ../../../../rtl-model/alu.v ../../../../rtl-model/cpu.v ../../../../rtl-model/exec.v ../../../../rtl-model/fetch.v ../../../../rtl-model/jmp_cond.v ../../../../rtl-model/util/primitives.v
 
# Simulation
 
vlog -lint -work work +incdir+../ddr2sdram/ ../ddr2sdram/glbl.v ../ddr2sdram/ddr2.v
vcom -lint -work work ../flash-prom/generic_data.vhd ../flash-prom/test_stub.vhd ../flash-prom/utility_pack.vhd ../flash-prom/m29dw323d.vhd
vlog -lint -work work +incdir+../../rtl ../board.v ../../rtl/zet_soc.v
 
 
vmap unisims /home/zeus/opt/xilinx92i/modelsim/verilog/unisims
vsim -novopt -L /home/zeus/opt/xilinx92i/modelsim/verilog/unisims -t ps work.board work.glbl
add wave -divider Clocks
add wave -radix hexadecimal /board/fpga0/cpu_clk
add wave -radix hexadecimal /board/fpga0/mem_rst
add wave -divider Memory
add wave -radix hexadecimal /board/rst
add wave -radix hexadecimal /fpga0/addr
add wave -radix hexadecimal /fpga0/wr_data
add wave -radix hexadecimal /fpga0/we
add wave -radix hexadecimal /fpga0/byte_m
add wave -radix hexadecimal /fpga0/rd_data
add wave -radix hexadecimal /fpga0/ready
add wave -divider CPU
add wave -radix hexadecimal /fpga0/cpu0/fetch0/decode0/seq_rom0/addr
add wave -radix hexadecimal /fpga0/cpu0/fetch0/decode0/seq_rom0/q
add wave -radix hexadecimal /fpga0/cpu0/fetch0/state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/next_state
add wave -radix hexadecimal /fpga0/cpu0/fetch0/block
add wave -radix hexadecimal /fpga0/cpu0/fetch0/opcode
add wave -radix hexadecimal /fpga0/cpu0/fetch_or_exec
add wave -divider VDU
add wave -radix hexadecimal /fpga0/vdu0/*
# add wave -divider ddr2
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/sdram0/*
# add wave -divider Flash
# add wave -radix hexadecimal /fpga0/mem_ctrlr_0/flash0/*
/trunk/impl/spartan3an-sk/sim/board.v
0,0 → 1,163
`timescale 1ns/100ps
`include "parameters.v"
module board;
 
// Net and register declaration
/*
wire [`clk_width-1 : 0] ddr2_clk;
wire [`clk_width-1 : 0] ddr2_clkb;
wire [`cke_width-1 : 0] ddr2_cke;
wire [0 : 0] ddr2_csb;
wire ddr2_web;
wire ddr2_rasb;
wire ddr2_casb;
wire [`data_mask_width-1:0] ddr2_dm;
wire [`bank_address - 1:0] ddr2_ba;
wire [`row_address-1:0] ddr2_address;
wire ddr2_ODT;
wire [`data_strobe_width-1 : 0] ddr_dqs_sdram;
wire [`data_width-1:0] ddr_dq_sdram;
wire [`data_strobe_width-1 : 0] ddr_dqs_sdram_n;
wire [`data_width-1:0] ddr_dq_fpga;
wire [`data_strobe_width-1 : 0] ddr_dqs_fpga;
wire rst_dqs_div_out;
wire [`data_strobe_width-1 : 0] ddr_dqs_fpga_n;
wire ddr_clkb;
*/
wire NF_WE;
wire NF_CE;
wire NF_OE;
wire NF_BYTE;
wire NF_RP;
wire [21:1] NF_A;
wire [15:0] NF_D;
 
wire vga_r, vga_g, vga_b, vga_hsync, vga_vsync;
wire [1:0] led;
 
reg sys_clk /*, ddr_clk */;
reg rst;
reg enable, enable_o;
// wire [2:0] CMD;
 
// Module instantiations
/*
ddr2 X16_0 (
.ck (ddr2_clk[0]),
.ck_n (ddr2_clkb[0]),
.cke (ddr2_cke),
.cs_n (ddr2_csb),
.ras_n (ddr2_rasb),
.cas_n (ddr2_casb),
.we_n (ddr2_web),
.dm_rdqs(ddr2_dm[1:0]),
.ba (ddr2_ba),
.addr (ddr2_address),
.dq (ddr_dq_sdram[15:0]),
.dqs (ddr_dqs_sdram[1:0]),
.dqs_n ( ddr_dqs_sdram_n[1:0]),
.rdqs_n (),
.odt (ddr2_ODT)
);
*/
test_stub flash_rom0 (
.W_N (NF_WE),
.E_N (NF_CE),
.G_N (NF_OE),
.Byte_N (NF_BYTE),
.RP (NF_RP),
.A (NF_A),
.DQ (NF_D[14:0]),
.DQ15A_1 (NF_D[15])
);
 
zet_soc fpga0 (
// .DDR_CLK (ddr_clk),
.SYS_CLK (sys_clk),
/*
.SD_DQ (ddr_dq_fpga),
.SD_A (ddr2_address),
.SD_BA (ddr2_ba),
.SD_CK_P (ddr2_clk),
.SD_CK_N (ddr2_clkb),
.SD_CKE (ddr2_cke),
.SD_CS (ddr2_csb),
.SD_RAS (ddr2_rasb),
.SD_CAS (ddr2_casb),
.SD_WE (ddr2_web),
.SD_ODT (ddr2_ODT),
.SD_UDM (ddr2_dm[1]),
.SD_LDM (ddr2_dm[0]),
.SD_UDQS_P (ddr_dqs_fpga[1]),
.SD_LDQS_P (ddr_dqs_fpga[0]),
.SD_UDQS_N (ddr_dqs_fpga_n[1]),
.SD_LDQS_N (ddr_dqs_fpga_n[0]),
.SD_LOOP_IN (rst_dqs_div_out),
.SD_LOOP_OUT (rst_dqs_div_out),
*/
.NF_D (NF_D),
.NF_A (NF_A),
.NF_WE (NF_WE),
.NF_CE (NF_CE),
.NF_OE (NF_OE),
.NF_BYTE (NF_BYTE),
.NF_RP (NF_RP),
 
.BTN_SOUTH (rst),
 
.VGA_R (vga_r),
.VGA_G (vga_g),
.VGA_B (vga_b),
.VGA_HSYNC (vga_hsync),
.VGA_VSYNC (vga_vsync),
 
.LED (led)
);
 
// Assignments
/*
assign ddr_dqs_fpga = (enable == 1'b1) ? ddr_dqs_sdram : `data_strobe_width'hZ;
assign ddr_dq_fpga = ( enable == 1'b1) ? ddr_dq_sdram : `data_width'hZ;
 
assign ddr_dqs_sdram = (enable == 1'b0) ? ddr_dqs_fpga : `data_strobe_width'hZ;
assign ddr_dq_sdram = (enable == 1'b0) ? ddr_dq_fpga : `data_width'hZ;
 
assign ddr_dqs_fpga_n = (enable == 1'b1) ? ddr_dqs_sdram_n : `data_strobe_width'hZ;
assign ddr_dqs_sdram_n = (enable == 1'b0) ? ddr_dqs_fpga_n : `data_strobe_width'hZ;
 
assign CMD = {ddr2_rasb,ddr2_casb,ddr2_web};
assign ddr_clkb = ~ddr_clk;
*/
// Behaviour
initial enable = 1'b0;
 
// Clock Generation
initial
begin
// ddr_clk <= 1'b1;
sys_clk <= 1'b1;
end
 
// RESET Generation
initial
begin
rst = 1'b0;
# 800 rst = 1'b1;
# 100 rst = 1'b0;
end
/*
always @(posedge ddr_clk)
begin
if (CMD == 3'b100) // -- Write
enable_o <= 1'b0;
else if(CMD == 3'b101) // -- Read
enable_o <= 1'b1;
else
enable_o <= enable_o;
end
 
always @(posedge ddr_clk) enable <= enable_o;
*/
// always # 3.7593984962406 ddr_clk <= ~ddr_clk; // 133 MHZ
always # 10 sys_clk <= ~sys_clk; // 50Mhz
endmodule
/trunk/impl/stratix2-nios2dk/zet/defines.v
0,0 → 1,2
`define IR_SIZE 34
`define ADD_IP `IR_SIZE'b0__1__1__0_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
/trunk/impl/stratix2-nios2dk/zet/regfile.v
0,0 → 1,55
module regfile(a, b, c, cs, d, s, oflags, wr, wrfl, wrhi, clk, boot,
addr_a, addr_b, addr_c, addr_d, addr_s, iflags, word_op, o_byte, c_byte);
// IO Ports
output [15:0] a, b, c, s, oflags;
output [15:0] cs;
input [3:0] addr_a, addr_b, addr_c, addr_d;
input [1:0] addr_s;
input [15:0] iflags;
input [31:0] d;
input wrfl, wrhi, word_op, clk, boot, o_byte, c_byte;
input [1:0] wr;
 
// Net declarations
reg [15:0] r[15:0];
reg [8:0] flags;
reg [4:0] i;
wire [7:0] a8, b8, c8;
wire [3:0] addr_a2, addr_b2, addr_c2;
 
// Assignments
assign a = (o_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
assign a8 = addr_a[2] ? r[addr_a2][15:8] : r[addr_a][7:0];
assign addr_a2 = {2'b0, addr_a[1:0]};
 
assign b = (o_byte & ~addr_b[3]) ? { {8{b8[7]}}, b8} : r[addr_b];
assign b8 = addr_b[2] ? r[addr_b2][15:8] : r[addr_b][7:0];
assign addr_b2 = {2'b0, addr_b[1:0]};
 
assign c = (c_byte & ~addr_c[3]) ? { {8{c8[7]}}, c8} : r[addr_c];
assign c8 = addr_c[2] ? r[addr_c2][15:8] : r[addr_c][7:0];
assign addr_c2 = {2'b0, addr_c[1:0]};
 
assign s = r[{2'b10,addr_s}];
assign oflags = { 4'd0, flags[8:3], 1'b0, flags[2], 1'b0,
flags[1], 1'b1, flags[0] };
 
assign cs = r[9];
 
// Behaviour
always @(posedge clk)
if (~boot) begin
for (i=5'd0; i<5'd16; i=i+5'd1) r[i] = 16'd0;
r[9][15:12] <= 4'hf;
r[15] <= 16'hfff0;
end else
begin
if (wr[0] & ( ~wr[1] | wr[1] & r[addr_c][0])) begin
if (word_op | addr_d[3:2]==2'b10) r[addr_d] <= d[15:0];
else if (addr_d[3]~^addr_d[2]) r[addr_d][7:0] <= d[7:0];
else r[{2'b0,addr_d[1:0]}][15:8] = d[7:0];
end
if (wrfl) flags <= { iflags[11:6], iflags[4], iflags[2], iflags[0] };
if (wrhi) r[4'd2] <= d[31:16];
end
endmodule
/trunk/impl/stratix2-nios2dk/zet/simulation/modelsim/gate.do
0,0 → 1,64
vlog -work work cpu_gate.v
vlog -work work idt71v416s10.v
vsim -L /home/zeus/zet/altera/zet/simulation/modelsim/verilog_libs/stratixii_ver -t ps work.cpu_gate
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave sim:/cpu_gate/clk_
add wave -noupdate -format Logic /cpu_gate/cpu0/\\pll0|altpll_component|_clk0\\
add wave -noupdate -format Logic /cpu_gate/cpu0/\\pll0|altpll_component|_locked\\
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/pc
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/state
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/opcode_r
add wave sim:/cpu_gate/cpu0/fetch0/ir
add wave sim:/cpu_gate/cpu0/fetch0/op0/ir0
add wave sim:/cpu_gate/cpu0/fetch0/op0/ir1
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[0][15]~regout\ , \r[0][14]~regout\ , \r[0][13]~regout\ , \r[0][12]~regout\ , \r[0][11]~regout\ , \r[0][10]~regout\ , \r[0][9]~regout\ , \r[0][8]~regout\ , \r[0][7]~regout\ , \r[0][6]~regout\ , \r[0][5]~regout\ , \r[0][4]~regout\ , \r[0][3]~regout\ , \r[0][2]~regout\ , \r[0][1]~regout\ , \r[0][0]~regout\ } )} ax
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[1][15]~regout\ , \r[1][14]~regout\ , \r[1][13]~regout\ , \r[1][12]~regout\ , \r[1][11]~regout\ , \r[1][10]~regout\ , \r[1][9]~regout\ , \r[1][8]~regout\ , \r[1][7]~regout\ , \r[1][6]~regout\ , \r[1][5]~regout\ , \r[1][4]~regout\ , \r[1][3]~regout\ , \r[1][2]~regout\ , \r[1][1]~regout\ , \r[1][0]~regout\ } )} cx
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[2][15]~regout\ , \r[2][14]~regout\ , \r[2][13]~regout\ , \r[2][12]~regout\ , \r[2][11]~regout\ , \r[2][10]~regout\ , \r[2][9]~regout\ , \r[2][8]~regout\ , \r[2][7]~regout\ , \r[2][6]~regout\ , \r[2][5]~regout\ , \r[2][4]~regout\ , \r[2][3]~regout\ , \r[2][2]~regout\ , \r[2][1]~regout\ , \r[2][0]~regout\ } )} dx
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[3][15]~regout\ , \r[3][14]~regout\ , \r[3][13]~regout\ , \r[3][12]~regout\ , \r[3][11]~regout\ , \r[3][10]~regout\ , \r[3][9]~regout\ , \r[3][8]~regout\ , \r[3][7]~regout\ , \r[3][6]~regout\ , \r[3][5]~regout\ , \r[3][4]~regout\ , \r[3][3]~regout\ , \r[3][2]~regout\ , \r[3][1]~regout\ , \r[3][0]~regout\ } )} bx
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[4][15]~regout\ , \r[4][14]~regout\ , \r[4][13]~regout\ , \r[4][12]~regout\ , \r[4][11]~regout\ , \r[4][10]~regout\ , \r[4][9]~regout\ , \r[4][8]~regout\ , \r[4][7]~regout\ , \r[4][6]~regout\ , \r[4][5]~regout\ , \r[4][4]~regout\ , \r[4][3]~regout\ , \r[4][2]~regout\ , \r[4][1]~regout\ , \r[4][0]~regout\ } )} sp
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[5][15]~regout\ , \r[5][14]~regout\ , \r[5][13]~regout\ , \r[5][12]~regout\ , \r[5][11]~regout\ , \r[5][10]~regout\ , \r[5][9]~regout\ , \r[5][8]~regout\ , \r[5][7]~regout\ , \r[5][6]~regout\ , \r[5][5]~regout\ , \r[5][4]~regout\ , \r[5][3]~regout\ , \r[5][2]~regout\ , \r[5][1]~regout\ , \r[5][0]~regout\ } )} bp
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[6][15]~regout\ , \r[6][14]~regout\ , \r[6][13]~regout\ , \r[6][12]~regout\ , \r[6][11]~regout\ , \r[6][10]~regout\ , \r[6][9]~regout\ , \r[6][8]~regout\ , \r[6][7]~regout\ , \r[6][6]~regout\ , \r[6][5]~regout\ , \r[6][4]~regout\ , \r[6][3]~regout\ , \r[6][2]~regout\ , \r[6][1]~regout\ , \r[6][0]~regout\ } )} si
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[7][15]~regout\ , \r[7][14]~regout\ , \r[7][13]~regout\ , \r[7][12]~regout\ , \r[7][11]~regout\ , \r[7][10]~regout\ , \r[7][9]~regout\ , \r[7][8]~regout\ , \r[7][7]~regout\ , \r[7][6]~regout\ , \r[7][5]~regout\ , \r[7][4]~regout\ , \r[7][3]~regout\ , \r[7][2]~regout\ , \r[7][1]~regout\ , \r[7][0]~regout\ } )} di
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[13][15]~regout\ , \r[13][14]~regout\ , \r[13][13]~regout\ , \r[13][12]~regout\ , \r[13][11]~regout\ , \r[13][10]~regout\ , \r[13][9]~regout\ , \r[13][8]~regout\ , \r[13][7]~regout\ , \r[13][6]~regout\ , \r[13][5]~regout\ , \r[13][4]~regout\ , \r[13][3]~regout\ , \r[13][2]~regout\ , \r[13][1]~regout\ , \r[13][0]~regout\ } )} rtmp
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[8][15]~regout\ , \r[8][14]~regout\ , \r[8][13]~regout\ , \r[8][12]~regout\ , \r[8][11]~regout\ , \r[8][10]~regout\ , \r[8][9]~regout\ , \r[8][8]~regout\ , \r[8][7]~regout\ , \r[8][6]~regout\ , \r[8][5]~regout\ , \r[8][4]~regout\ , \r[8][3]~regout\ , \r[8][2]~regout\ , \r[8][1]~regout\ , \r[8][0]~regout\ } )} es
quietly virtual signal -install /cpu_gate/cpu0/exec0/reg0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0/exec0/reg0 )&{\r[15][15]~regout\ , \r[15][14]~regout\ , \r[15][13]~regout\ , \r[15][12]~regout\ , \r[15][11]~regout\ , \r[15][10]~regout\ , \r[15][9]~regout\ , \r[15][8]~regout\ , \r[15][7]~regout\ , \r[15][6]~regout\ , \r[15][5]~regout\ , \r[15][4]~regout\ , \r[15][3]~regout\ , \r[15][2]~regout\ , \r[15][1]~regout\ , \r[15][0]~regout\ } )} ip
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/addr_
add wave -noupdate -format Logic /cpu_gate/cpu0/rble0_
add wave -noupdate -format Logic /cpu_gate/cpu0/rbhe0_
add wave -noupdate -format Logic /cpu_gate/cpu0/rble1_
add wave -noupdate -format Logic /cpu_gate/cpu0/rbhe1_
add wave -noupdate -format Logic -radix hexadecimal /cpu_gate/cpu0/data0_
add wave -noupdate -format Logic -radix hexadecimal /cpu_gate/cpu0/data1_
add wave -noupdate -format Logic /cpu_gate/cpu0/rwe_
add wave -noupdate -format Logic /cpu_gate/cpu0/roe_
add wave -noupdate -format Logic /cpu_gate/cpu0/roe_
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/ax
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/bx
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/cx
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/dx
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/sp
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/bp
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/si
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/di
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/rtmp
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/es
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/cs
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/exec0/reg0/ip
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {239876 ps} 0}
configure wave -namecolwidth 337
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
 
run 14us
/trunk/impl/stratix2-nios2dk/zet/simulation/modelsim/idt71v416s10.v
0,0 → 1,455
/****************************************************************************
* Copyright 1991,1992,1993,1998,1999 Integrated Device Technology Corp.
* All right reserved.
*
* This program is proprietary and confidential information of
* IDT Corp. and may be used and disclosed only as authorized
* in a license agreement controlling such use and disclosure.
*
* IDT reserves the right to make any changes to
* the product herein to improve function or design.
* IDT does not assume any liability arising out of
* the application or use of the product herein.
*
* WARNING: The unlicensed shipping, mailing, or carring of this
* technical data outside the United States, or the unlicensed
* disclosure, by whatever means, through visits abroad, or the
* unlicensed disclosure to foreign national in the United States,
* may violate the United States criminal law.
*
* File Name : idt71v416s10.v
* Function : 256Kx16-bit Asynchronous Static RAM
* Simulation Tool/Version : Verilog-XL 2.5
*
***************************************************************************/
 
/*******************************************************************************
* Module Name: idt71v416s10
* Description: 256Kx16 10ns Asynchronous Static RAM
* Revision : rev00
* Date : 06/08/99
* Notes : This model is believed to be functionally
* accurate. Please direct any inquiries to
* IDT SRAM Applications at: sramhelp@idt.com
*
*******************************************************************************/
`timescale 1ns/10ps
 
module idt71v416s10(data, addr, we_, oe_, cs_, ble_, bhe_);
inout [15:0] data;
input [17:0] addr;
input we_, oe_, cs_, bhe_, ble_;
 
//Read Cycle Parameters
parameter Taa = 10; // address access time
parameter Tacs = 10; // cs_ access time
parameter Tclz = 4; // cs_ to output low Z time
parameter Tchz = 5; // cs_ to output high Z time
parameter Toe = 5; // oe_ to output time
parameter Tohz = 5; // oe_ to output Z time
parameter Toh = 4; // data hold from adr change time
parameter Tbe = 5; // we_ to output valid time
 
//Write Cycle Parameters
parameter Taw = 8; // adr valid to end of write time
parameter Tcw = 8; // cs_ to end of write time
parameter Tbw = 8; // ble_/bhe_ to end of write time
parameter Tas = 0; // address set up time
parameter Twp = 8; // write pulse width min
parameter Tdw = 5; // data valid to end of writ time
parameter Tow = 3; // data act from end of writ time
parameter Twhz = 6; // we_ to output in high Z time
 
 
reg [7:0] mem1[0:262143];
reg [7:0] mem2[0:262143];
 
time adr_chng,da_chng,we_fall,we_rise,cs_fall,cs_rise;
time oe_fall,oe_rise,ble_fall,ble_rise,bhe_fall,bhe_rise;
 
wire [15:0] data_in;
reg [15:0] data_out;
reg [15:0] temp1,temp2,temp3;
reg outen, out_en, in_en;
 
 
initial
begin
in_en = 1'b1;
if (cs_)
out_en = 1'b0;
end
 
// input/output control logic
//---------------------------
assign data = out_en ? data_out : 'hzzzz;
assign data_in = in_en ? data : 'hzzzz;
 
// read access
//------------
always @(addr)
if (cs_==0 & we_==1) begin //read
fork
if(~ble_)
#Taa data_out[7:0] = mem1[addr];
else #Taa data_out[7:0] = 'hzz;
if(~bhe_)
#Taa data_out[15:8] = mem2[addr];
else #Taa data_out[15:8] = 'hzz;
join
end
always @(addr)
begin
adr_chng = $time;
 
outen = 1'b0;
#Toh out_en = outen;
 
//---------------------------------------------
if (cs_==0 & we_==1) //read
begin
if (oe_==0)
begin
outen = 1'b1;
out_en = 1'b1;
end
end
//---------------------------------------------
if (cs_==0 & we_==0) //write
begin
if (oe_==0)
begin
outen = 1'b0;
out_en = 1'b0;
temp1 = data_in;
fork
if(~ble_)
#Tdw mem1[addr] = temp1[7:0];
if(~bhe_)
#Tdw mem2[addr] = temp1[15:8];
join
end
else
begin
outen = 1'b0;
out_en = 1'b0;
temp1 = data_in;
fork
if(~ble_)
#(Tdw-Toh) mem1[addr] = temp1[7:0];
if(~bhe_)
#(Tdw-Toh) mem2[addr] = temp1[15:8];
join
end
 
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
end
end
 
always @(negedge cs_)
begin
cs_fall = $time;
 
if (cs_fall - adr_chng < Tas)
$display($time, " Adr setup time is not enough Tas");
 
if (we_==1 & oe_==0)
outen = 1'b1;
#Tclz out_en = outen;
 
if (we_==1) begin
fork
if(~ble_)
#(Tacs-Tclz) data_out[7:0] = mem1[addr];
else #(Tacs-Tclz) data_out[7:0] = 'hzz;
if(~bhe_)
#(Tacs-Tclz) data_out[15:8] = mem2[addr];
else #(Tacs-Tclz) data_out[15:8] = 'hzz;
join
end
 
if (we_==0)
begin
outen = 1'b0;
out_en = 1'b0;
temp2 = data_in;
fork
if(~ble_)
#Tdw mem1[addr] = temp2[7:0];
if(~bhe_)
#Tdw mem2[addr] = temp2[15:8];
join
end
end
 
always @(posedge cs_)
begin
cs_rise = $time;
 
if (we_==0)
begin
if (cs_rise - adr_chng < Taw)
begin
if(~ble_)
mem1[addr] = 8'hxx;
if(~bhe_)
mem2[addr] = 8'hxx;
$display($time, " Adr valid to end of write is not enough Taw");
end
 
if (cs_rise - cs_fall < Tcw)
begin
if(~ble_)
mem1[addr] = 8'hxx;
if(~bhe_)
mem2[addr] = 8'hxx;
$display($time, " cs_ to end of write is not enough Tcw");
end
 
if (cs_rise - da_chng < Tdw)
begin
if(~ble_)
mem1[addr] = 8'hxx;
if(~bhe_)
mem2[addr] = 8'hxx;
$display($time, " Data setup is not enough_1");
end
end
 
outen = 1'b0;
#Tchz out_en = outen;
end
 
always @(negedge oe_)
begin
oe_fall = $time;
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
 
if (we_==1 & cs_==0)
outen = 1'b1;
#Toe out_en = outen;
end
 
always @(posedge oe_)
begin
oe_rise = $time;
 
outen = 1'b0;
#Tohz out_en = outen;
end
 
// write to ram
//-------------
always @(negedge we_)
begin
we_fall = $time;
 
if (we_fall - adr_chng < Tas)
$display($time, " Address set-up to WE low is not enough");
 
if (cs_==0 & oe_==0)
begin
outen = 1'b0;
#Twhz out_en = outen;
temp3 = data_in;
fork
if(~ble_)
#Tdw mem1[addr] = temp3[7:0];
if(~bhe_)
#Tdw mem2[addr] = temp3[15:8];
join
 
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
end
 
if (cs_==0 & oe_==1)
begin
outen = 1'b0;
out_en = 1'b0;
temp3 = data_in;
fork
if(~ble_)
#Tdw mem1[addr] = temp3[7:0];
if(~bhe_)
#Tdw mem2[addr] = temp3[15:8];
join
 
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
end
end
 
always @(posedge we_)
begin
we_rise = $time;
 
if (cs_==0)
begin
if (we_rise - da_chng < Tdw)
begin
if(~ble_)
mem1[addr] = 8'hxx;
if(~bhe_)
mem2[addr] = 8'hxx;
$display($time, " Data setup is not enough_2");
end
if (we_rise - adr_chng < Taw)
begin
if(~ble_)
mem1[addr] = 8'hxx;
if(~bhe_)
mem2[addr] = 8'hxx;
$display($time, " Addr setup is not enough");
end
end
if (cs_==0 & oe_==0)
begin
if (we_rise - we_fall < (Twhz+Tdw) )
begin
if(~ble_)
mem1[addr] = 8'hxx;
if(~bhe_)
mem2[addr] = 8'hxx;
$display($time, " WE pulse width needs to be Twhz+Tdw");
end
 
outen = 1'b1;
#Tow out_en = outen;
end
if (cs_==0 & oe_==1)
begin
if (we_rise - we_fall < Twp)
begin
if(~ble_)
mem1[addr] = 8'hxx;
if(~bhe_)
mem2[addr] = 8'hxx;
$display($time, " WE pulse width needs to be Twp");
end
end
end
 
always @(negedge ble_)
begin
ble_fall = $time;
 
if (ble_fall - adr_chng < Tas)
$display($time, " Address set-up to BLE low is not enough");
 
if (we_==0 & cs_==0)
begin
outen = 1'b0;
out_en = outen;
temp3 = data_in;
 
#Tdw mem1[addr] = temp3[7:0];
 
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
end
end
 
always @(negedge bhe_)
begin
bhe_fall = $time;
 
if (bhe_fall - adr_chng < Tas)
$display($time, " Address set-up to BHE low is not enough");
 
if (we_==0 & cs_==0)
begin
outen = 1'b0;
out_en = outen;
temp3 = data_in;
 
#Tdw mem2[addr] = temp3[15:8];
 
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
end
end
 
always @(posedge ble_)
begin
ble_rise = $time;
 
if (we_==0 & cs_==0)
begin
 
if (ble_rise - ble_fall < Tbw)
begin
mem1[addr] = 8'hxx;
$display($time, " ble_ to end of write is not enough Tbw");
end
 
end
end
 
always @(posedge bhe_)
begin
bhe_rise = $time;
 
if (we_==0 & cs_==0)
begin
 
if (bhe_rise - bhe_fall < Tbw)
begin
mem2[addr] = 8'hxx;
$display($time, " bhe_ to end of write is not enough Tbw");
end
 
end
end
 
always @ (data)
begin
da_chng = $time;
 
if (we_==0 & cs_==0)
begin
fork
if(~ble_)
#Tdw mem1[addr] = data_in[7:0];
if(~bhe_)
#Tdw mem2[addr] = data_in[15:8];
join
 
if(~ble_)
data_out[7:0] = mem1[addr];
else data_out[7:0] = 'hzz;
if(~bhe_)
data_out[15:8] = mem2[addr];
else data_out[15:8] = 'hzz;
end
end
 
endmodule
/trunk/impl/stratix2-nios2dk/zet/simulation/modelsim/rtl.do
0,0 → 1,34
vlog -work work cpu_gate.v
vlog -work work idt71v416s10.v
vsim -L /home/zeus/zet/altera/zet/simulation/modelsim/verilog_libs/altera_mf_ver -L /home/zeus/zet/altera/zet/simulation/modelsim/verilog_libs/stratixii_ver -l msim_transcript -i -t ps work.cpu_gate
add wave sim:/cpu_gate/clk_
add wave sim:/cpu_gate/cpu0/clk
add wave sim:/cpu_gate/cpu0/boot
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/pc
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/state
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/opcode
add wave -radix hexadecimal sim:/cpu_gate/cpu0/rd_data
add wave sim:/cpu_gate/cpu0/fetch0/need_modrm
add wave sim:/cpu_gate/cpu0/fetch0/need_off
add wave sim:/cpu_gate/cpu0/fetch0/need_imm
add wave sim:/cpu_gate/cpu0/fetch0/ir
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/imm
add wave -radix hexadecimal sim:/cpu_gate/cpu0/fetch0/off
add wave -radix hexadecimal sim:/cpu_gate/addr_
add wave -radix hexadecimal sim:/cpu_gate/data0_
add wave -radix hexadecimal sim:/cpu_gate/data1_
add wave -radix hexadecimal sim:/cpu_gate/cpu0/mem0/state
add wave sim:/cpu_gate/cpu0/mem0/reset
add wave sim:/cpu_gate/rble0_
add wave sim:/cpu_gate/rbhe0_
add wave sim:/cpu_gate/rble1_
add wave sim:/cpu_gate/rbhe1_
add wave sim:/cpu_gate/roe_
add wave sim:/cpu_gate/rwe_
add wave -radix hexadecimal sim:/cpu_gate/cpu0/exec0/reg0/r\[15\]
add wave -radix hexadecimal sim:/cpu_gate/cpu0/exec0/reg0/d
add wave sim:/cpu_gate/cpu0/exec0/reg0/addr_a
add wave sim:/cpu_gate/cpu0/exec0/reg0/addr_d
add wave sim:/cpu_gate/cpu0/exec0/reg0/wr
 
run 35us
/trunk/impl/stratix2-nios2dk/zet/simulation/modelsim/gate-final.do
0,0 → 1,54
vlog -work work cpu_gate.v
vlog -work work idt71v416s10.v
vsim -L /home/zeus/zet/altera/zet/simulation/modelsim/verilog_libs/stratixii_ver -t ps work.cpu_gate
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave sim:/cpu_gate/clk_
add wave -noupdate -format Logic /cpu_gate/cpu0/\\pll0|altpll_component|_clk0\\
add wave -noupdate -format Logic /cpu_gate/cpu0/\\pll0|altpll_component|_locked\\
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[0][15]~regout\ , \exec0|reg0|r[0][14]~regout\ , \exec0|reg0|r[0][13]~regout\ , \exec0|reg0|r[0][12]~regout\ , \exec0|reg0|r[0][11]~regout\ , \exec0|reg0|r[0][10]~regout\ , \exec0|reg0|r[0][9]~regout\ , \exec0|reg0|r[0][8]~regout\ , \exec0|reg0|r[0][7]~regout\ , \exec0|reg0|r[0][6]~regout\ , \exec0|reg0|r[0][5]~regout\ , \exec0|reg0|r[0][4]~regout\ , \exec0|reg0|r[0][3]~regout\ , \exec0|reg0|r[0][2]~regout\ , \exec0|reg0|r[0][1]~regout\ , \exec0|reg0|r[0][0]~regout\ } )} ax
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[1][15]~regout\ , \exec0|reg0|r[1][14]~regout\ , \exec0|reg0|r[1][13]~regout\ , \exec0|reg0|r[1][12]~regout\ , \exec0|reg0|r[1][11]~regout\ , \exec0|reg0|r[1][10]~regout\ , \exec0|reg0|r[1][9]~regout\ , \exec0|reg0|r[1][8]~regout\ , \exec0|reg0|r[1][7]~regout\ , \exec0|reg0|r[1][6]~regout\ , \exec0|reg0|r[1][5]~regout\ , \exec0|reg0|r[1][4]~regout\ , \exec0|reg0|r[1][3]~regout\ , \exec0|reg0|r[1][2]~regout\ , \exec0|reg0|r[1][1]~regout\ , \exec0|reg0|r[1][0]~regout\ } )} cx
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[2][15]~regout\ , \exec0|reg0|r[2][14]~regout\ , \exec0|reg0|r[2][13]~regout\ , \exec0|reg0|r[2][12]~regout\ , \exec0|reg0|r[2][11]~regout\ , \exec0|reg0|r[2][10]~regout\ , \exec0|reg0|r[2][9]~regout\ , \exec0|reg0|r[2][8]~regout\ , \exec0|reg0|r[2][7]~regout\ , \exec0|reg0|r[2][6]~regout\ , \exec0|reg0|r[2][5]~regout\ , \exec0|reg0|r[2][4]~regout\ , \exec0|reg0|r[2][3]~regout\ , \exec0|reg0|r[2][2]~regout\ , \exec0|reg0|r[2][1]~regout\ , \exec0|reg0|r[2][0]~regout\ } )} dx
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[3][15]~regout\ , \exec0|reg0|r[3][14]~regout\ , \exec0|reg0|r[3][13]~regout\ , \exec0|reg0|r[3][12]~regout\ , \exec0|reg0|r[3][11]~regout\ , \exec0|reg0|r[3][10]~regout\ , \exec0|reg0|r[3][9]~regout\ , \exec0|reg0|r[3][8]~regout\ , \exec0|reg0|r[3][7]~regout\ , \exec0|reg0|r[3][6]~regout\ , \exec0|reg0|r[3][5]~regout\ , \exec0|reg0|r[3][4]~regout\ , \exec0|reg0|r[3][3]~regout\ , \exec0|reg0|r[3][2]~regout\ , \exec0|reg0|r[3][1]~regout\ , \exec0|reg0|r[3][0]~regout\ } )} bx
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[4][15]~regout\ , \exec0|reg0|r[4][14]~regout\ , \exec0|reg0|r[4][13]~regout\ , \exec0|reg0|r[4][12]~regout\ , \exec0|reg0|r[4][11]~regout\ , \exec0|reg0|r[4][10]~regout\ , \exec0|reg0|r[4][9]~regout\ , \exec0|reg0|r[4][8]~regout\ , \exec0|reg0|r[4][7]~regout\ , \exec0|reg0|r[4][6]~regout\ , \exec0|reg0|r[4][5]~regout\ , \exec0|reg0|r[4][4]~regout\ , \exec0|reg0|r[4][3]~regout\ , \exec0|reg0|r[4][2]~regout\ , \exec0|reg0|r[4][1]~regout\ , \exec0|reg0|r[4][0]~regout\ } )} sp
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[5][15]~regout\ , \exec0|reg0|r[5][14]~regout\ , \exec0|reg0|r[5][13]~regout\ , \exec0|reg0|r[5][12]~regout\ , \exec0|reg0|r[5][11]~regout\ , \exec0|reg0|r[5][10]~regout\ , \exec0|reg0|r[5][9]~regout\ , \exec0|reg0|r[5][8]~regout\ , \exec0|reg0|r[5][7]~regout\ , \exec0|reg0|r[5][6]~regout\ , \exec0|reg0|r[5][5]~regout\ , \exec0|reg0|r[5][4]~regout\ , \exec0|reg0|r[5][3]~regout\ , \exec0|reg0|r[5][2]~regout\ , \exec0|reg0|r[5][1]~regout\ , \exec0|reg0|r[5][0]~regout\ } )} bp
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[6][15]~regout\ , \exec0|reg0|r[6][14]~regout\ , \exec0|reg0|r[6][13]~regout\ , \exec0|reg0|r[6][12]~regout\ , \exec0|reg0|r[6][11]~regout\ , \exec0|reg0|r[6][10]~regout\ , \exec0|reg0|r[6][9]~regout\ , \exec0|reg0|r[6][8]~regout\ , \exec0|reg0|r[6][7]~regout\ , \exec0|reg0|r[6][6]~regout\ , \exec0|reg0|r[6][5]~regout\ , \exec0|reg0|r[6][4]~regout\ , \exec0|reg0|r[6][3]~regout\ , \exec0|reg0|r[6][2]~regout\ , \exec0|reg0|r[6][1]~regout\ , \exec0|reg0|r[6][0]~regout\ } )} si
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[7][15]~regout\ , \exec0|reg0|r[7][14]~regout\ , \exec0|reg0|r[7][13]~regout\ , \exec0|reg0|r[7][12]~regout\ , \exec0|reg0|r[7][11]~regout\ , \exec0|reg0|r[7][10]~regout\ , \exec0|reg0|r[7][9]~regout\ , \exec0|reg0|r[7][8]~regout\ , \exec0|reg0|r[7][7]~regout\ , \exec0|reg0|r[7][6]~regout\ , \exec0|reg0|r[7][5]~regout\ , \exec0|reg0|r[7][4]~regout\ , \exec0|reg0|r[7][3]~regout\ , \exec0|reg0|r[7][2]~regout\ , \exec0|reg0|r[7][1]~regout\ , \exec0|reg0|r[7][0]~regout\ } )} di
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[13][15]~regout\ , \exec0|reg0|r[13][14]~regout\ , \exec0|reg0|r[13][13]~regout\ , \exec0|reg0|r[13][12]~regout\ , \exec0|reg0|r[13][11]~regout\ , \exec0|reg0|r[13][10]~regout\ , \exec0|reg0|r[13][9]~regout\ , \exec0|reg0|r[13][8]~regout\ , \exec0|reg0|r[13][7]~regout\ , \exec0|reg0|r[13][6]~regout\ , \exec0|reg0|r[13][5]~regout\ , \exec0|reg0|r[13][4]~regout\ , \exec0|reg0|r[13][3]~regout\ , \exec0|reg0|r[13][2]~regout\ , \exec0|reg0|r[13][1]~regout\ , \exec0|reg0|r[13][0]~regout\ } )} rtmp
quietly virtual signal -install /cpu_gate/cpu0 { (concat_range (15 to 0) )( (context /cpu_gate/cpu0 )&{\exec0|reg0|r[15][15]~regout\ , \exec0|reg0|r[15][14]~regout\ , \exec0|reg0|r[15][13]~regout\ , \exec0|reg0|r[15][12]~regout\ , \exec0|reg0|r[15][11]~regout\ , \exec0|reg0|r[15][10]~regout\ , \exec0|reg0|r[15][9]~regout\ , \exec0|reg0|r[15][8]~regout\ , \exec0|reg0|r[15][7]~regout\ , \exec0|reg0|r[15][6]~regout\ , \exec0|reg0|r[15][5]~regout\ , \exec0|reg0|r[15][4]~regout\ , \exec0|reg0|r[15][3]~regout\ , \exec0|reg0|r[15][2]~regout\ , \exec0|reg0|r[15][1]~regout\ , \exec0|reg0|r[15][0]~regout\ } )} ip
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/addr_
add wave -noupdate -format Logic /cpu_gate/cpu0/rble0_
add wave -noupdate -format Logic /cpu_gate/cpu0/rbhe0_
add wave -noupdate -format Logic /cpu_gate/cpu0/rble1_
add wave -noupdate -format Logic /cpu_gate/cpu0/rbhe1_
add wave -noupdate -format Logic -radix hexadecimal /cpu_gate/cpu0/data0_
add wave -noupdate -format Logic -radix hexadecimal /cpu_gate/cpu0/data1_
add wave -noupdate -format Logic /cpu_gate/cpu0/rwe_
add wave -noupdate -format Logic /cpu_gate/cpu0/roe_
add wave -noupdate -format Logic /cpu_gate/cpu0/roe_
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/ax
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/bx
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/cx
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/dx
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/sp
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/bp
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/si
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/di
add wave -noupdate -format Literal -radix hexadecimal /cpu_gate/cpu0/rtmp
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {239876 ps} 0}
configure wave -namecolwidth 337
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
 
run 2420420ps
/trunk/impl/stratix2-nios2dk/zet/simulation/modelsim/cpu_gate.v
0,0 → 1,29
`timescale 10ns/100ps
 
module cpu_gate;
 
// Registers
reg clk_;
 
// Net declarations
wire roe_, rwe_, rcs_, rble0_, rbhe0_, rble1_, rbhe1_;
wire [17:0] addr_;
wire [15:0] data0_, data1_;
 
// Module instantiations
cpu cpu0(clk_, addr_, roe_, rwe_, rcs_,
data0_, data1_, rble0_, rbhe0_, rble1_, rbhe1_);
idt71v416s10 mem0(data0_, addr_, rwe_, roe_, rcs_, rble0_, rbhe0_);
idt71v416s10 mem1(data1_, addr_, rwe_, roe_, rcs_, rble1_, rbhe1_);
 
// Behavioral
initial clk_ <= 1'b0;
 
always #1 clk_ = ~clk_;
 
initial
begin
$readmemh("bios0.dat", mem1.mem1, 229376);
$readmemh("bios1.dat", mem1.mem2, 229376);
end
endmodule
/trunk/impl/stratix2-nios2dk/zet/simulation/modelsim/README
0,0 → 1,4
* Hay que añadir la siguiente línea al archivo "zet.vo" justo antes de la
* última línea del endmmodule:
 
defparam \pll0|altpll_component|pll .sim_gate_lock_device_behavior = "on";
/trunk/impl/stratix2-nios2dk/zet/zet.qpf
0,0 → 1,23
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
 
QUARTUS_VERSION = "7.1"
DATE = "17:12:56 August 13, 2007"
 
 
# Revisions
 
PROJECT_REVISION = "zet"
/trunk/impl/stratix2-nios2dk/zet/exec.v
0,0 → 1,55
`include "defines.v"
 
module exec(ir, off, imm, cs, a, clk, boot,
memout, wr_data, we, addr, byteop);
// IO Ports
input [`IR_SIZE-1:0] ir;
input [15:0] off, imm;
input clk;
input boot;
input [15:0] memout;
 
output [15:0] wr_data, a;
output we, byteop;
output [19:0] addr;
output [15:0] cs;
 
// Net declarations
wire [15:0] b, c, flags, s, oflags, omemalu, bus_b;
wire [31:0] aluout;
wire [3:0] addr_a, addr_b, addr_c, addr_d;
wire [2:0] t, func;
wire [1:0] addr_s;
wire wrfl, high, wr_mem, memalu, a_byte, c_byte;
wire [1:0] wr;
 
// Module instances
alu alu0( {c, a}, bus_b, aluout, t, func, flags, oflags, ~byteop, s, off);
regfile reg0( a, b, c, cs, {aluout[31:16], omemalu}, s, flags, wr, wrfl, high, clk, boot,
addr_a, addr_b, addr_c, addr_d, addr_s, oflags, ~byteop, a_byte, c_byte);
// Assignments
assign addr_s = ir[1:0];
assign addr_a = ir[5:2];
assign addr_b = ir[9:6];
assign addr_c = ir[13:10];
assign addr_d = ir[17:14];
assign wrfl = ir[18];
assign wr_mem = ir[19];
assign wr = ir[21:20];
assign high = ir[22];
assign t = ir[25:23];
assign func = ir[28:26];
assign byteop = ir[29];
assign memalu = ir[30];
assign b_imm = ir[31];
assign a_byte = ir[32];
assign c_byte = ir[33];
 
assign omemalu = memalu ? aluout[15:0] : memout;
assign bus_b = b_imm ? imm : b;
 
assign we = ~wr_mem;
assign addr = aluout[19:0];
assign wr_data = c;
endmodule
/trunk/impl/stratix2-nios2dk/zet/zet.qsf
0,0 → 1,112
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
# The default values for assignments are stored in the file
# alu_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
 
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
 
 
set_global_assignment -name DEVICE EP2S60F672C5ES
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name TOP_LEVEL_ENTITY cpu
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:12:56 AUGUST 13, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION OFF -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_location_assignment PIN_AF15 -to clk_
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_location_assignment PIN_U1 -to addr_[0]
set_location_assignment PIN_U2 -to addr_[1]
set_location_assignment PIN_V1 -to addr_[2]
set_location_assignment PIN_V2 -to addr_[3]
set_location_assignment PIN_W1 -to addr_[4]
set_location_assignment PIN_W2 -to addr_[5]
set_location_assignment PIN_Y1 -to addr_[6]
set_location_assignment PIN_Y2 -to addr_[7]
set_location_assignment PIN_AA1 -to addr_[8]
set_location_assignment PIN_AA2 -to addr_[9]
set_location_assignment PIN_AB1 -to addr_[10]
set_location_assignment PIN_AB2 -to addr_[11]
set_location_assignment PIN_W3 -to addr_[12]
set_location_assignment PIN_W4 -to addr_[13]
set_location_assignment PIN_Y3 -to addr_[14]
set_location_assignment PIN_Y4 -to addr_[15]
set_location_assignment PIN_AA3 -to addr_[16]
set_location_assignment PIN_AA4 -to addr_[17]
set_location_assignment PIN_J19 -to rcs_
set_location_assignment PIN_J22 -to roe_
set_location_assignment PIN_J21 -to rwe_
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_location_assignment PIN_V4 -to data0_[15]
set_location_assignment PIN_V3 -to data0_[14]
set_location_assignment PIN_T9 -to data0_[13]
set_location_assignment PIN_T8 -to data0_[12]
set_location_assignment PIN_U4 -to data0_[11]
set_location_assignment PIN_U3 -to data0_[10]
set_location_assignment PIN_T5 -to data0_[9]
set_location_assignment PIN_T4 -to data0_[8]
set_location_assignment PIN_F20 -to data0_[7]
set_location_assignment PIN_E20 -to data0_[6]
set_location_assignment PIN_D19 -to data0_[5]
set_location_assignment PIN_G19 -to data0_[4]
set_location_assignment PIN_D20 -to data0_[3]
set_location_assignment PIN_E19 -to data0_[2]
set_location_assignment PIN_G15 -to data0_[1]
set_location_assignment PIN_E16 -to data0_[0]
set_location_assignment PIN_K20 -to rble0_
set_location_assignment PIN_K19 -to rbhe0_
set_location_assignment PIN_AA6 -to data1_[15]
set_location_assignment PIN_AA5 -to data1_[14]
set_location_assignment PIN_W8 -to data1_[13]
set_location_assignment PIN_W7 -to data1_[12]
set_location_assignment PIN_W6 -to data1_[11]
set_location_assignment PIN_W5 -to data1_[10]
set_location_assignment PIN_V8 -to data1_[9]
set_location_assignment PIN_V7 -to data1_[8]
set_location_assignment PIN_V6 -to data1_[7]
set_location_assignment PIN_V5 -to data1_[6]
set_location_assignment PIN_U8 -to data1_[5]
set_location_assignment PIN_U7 -to data1_[4]
set_location_assignment PIN_T7 -to data1_[3]
set_location_assignment PIN_T6 -to data1_[2]
set_location_assignment PIN_U6 -to data1_[1]
set_location_assignment PIN_U5 -to data1_[0]
set_location_assignment PIN_K22 -to rble1_
set_location_assignment PIN_K21 -to rbhe1_
set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id "External Board Clock"
set_instance_assignment -name CLOCK_SETTINGS "External Board Clock" -to clk_
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name VERILOG_FILE ../../../rtl/util/primitives.v
set_global_assignment -name VERILOG_FILE ../../../rtl/zet/alu.v
set_global_assignment -name VERILOG_FILE fetch2.v
set_global_assignment -name VERILOG_FILE cpu.v
set_global_assignment -name VERILOG_FILE altpll0.v
set_global_assignment -name VERILOG_FILE memory.v
set_global_assignment -name VERILOG_FILE exec.v
set_global_assignment -name VERILOG_FILE regfile.v
/trunk/impl/stratix2-nios2dk/zet/cpu.v
0,0 → 1,35
`include "defines.v"
 
module cpu(clk_, addr_, roe_, rwe_, rcs_,
data0_, data1_, rble0_, rbhe0_, rble1_, rbhe1_);
// IO Ports
input clk_;
output [17:0] addr_;
inout [15:0] data0_, data1_;
output roe_, rwe_, rcs_, rble0_, rbhe0_, rble1_, rbhe1_;
 
// Net declarations
wire [15:0] cs, ip;
wire clk, boot;
wire [`IR_SIZE-1:0] ir;
wire [15:0] off, imm, data;
wire [19:0] addr, addr_exec, addr_fetch;
wire byte_fetch, byte_m, byte_exec, fetch_or_exec;
wire [15:0] rd_data, wr_data;
wire we, we_cpu;
 
// Instantiations
altpll0 pll0(clk_, clk, boot);
fetch fetch0(clk, boot, cs, ip, rd_data, ir, off, imm, addr_fetch,
byte_fetch, fetch_or_exec);
exec exec0(ir, off, imm, cs, ip, clk, boot,
rd_data, wr_data, we, addr_exec, byte_exec);
memory mem0( rd_data, wr_data, we_cpu, addr, byte_m, clk, clk_, boot,
addr_, roe_, rwe_, rcs_,
data0_, data1_, rble0_, rbhe0_, rble1_, rbhe1_);
 
// Assignments
assign addr = fetch_or_exec ? addr_exec : addr_fetch;
assign byte_m = fetch_or_exec ? byte_exec : byte_fetch;
assign we_cpu = fetch_or_exec ? we : 1'b1;
endmodule
/trunk/impl/stratix2-nios2dk/zet/altpll0.v
0,0 → 1,319
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: altpll0.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.1 Build 178 06/25/2007 SP 1 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpll0 (
inclk0,
c0,
locked);
 
input inclk0;
output c0;
output locked;
 
wire [5:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
 
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b1),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 10,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_counter = 20,
altpll_component.gate_lock_signal = "YES",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Stratix II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_enable0 = "PORT_UNUSED",
altpll_component.port_enable1 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.port_sclkout0 = "PORT_UNUSED",
altpll_component.port_sclkout1 = "PORT_UNUSED",
altpll_component.spread_frequency = 0,
altpll_component.valid_lock_multiplier = 1,
altpll_component.sim_gate_lock_device_behavior = "on";
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "20"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "150.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "20"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_syn.v TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
/trunk/impl/stratix2-nios2dk/zet/memory.v
0,0 → 1,91
module memory (rd_data, wr_data, we, addr_data, w_b, clk, clk2x, boot,
addr_, roe_, rwe_, rcs_,
data0_, data1_, rble0_, rbhe0_, rble1_, rbhe1_);
 
// IO Ports
input [15:0] wr_data;
input [19:0] addr_data;
input we; // Write enable: when 0 write to mem, 1 don't write
input w_b; // When 0, word operation, si vale 1 operación de byte
input clk, clk2x; // Los relojes
input boot;
 
// Salidas
output reg [15:0] rd_data; // Salida leída de memoria
output roe_, rcs_; // roe_: SRAM Output Enable
output reg rwe_; // rwe_: SRAM Write Enable
output rble0_, rbhe0_, rble1_, rbhe1_; // rcs_: SRAM Chip Select
// rble_: SRAM Byte Low Enable
// rbhe_: SRAM Byte High Enable
output reg [17:0] addr_; // addr_: la dirección física a los chips
// Pins de entrada/salida
inout [15:0] data0_, data1_; // data_: Datos de entrada/salida
 
// Net declarations
wire [15:0] rd, bhr, blr; // rd: word de SRAM
// bhr: Byte High RAM
// blr: Byte Low RAM
wire [15:0] rddata;
wire a0;
wire [15:0] wr;
wire [17:0] addr1;
reg [2:0] state;
reg reset;
reg rble, rbhe;
 
parameter state_0 = 3'd0;
parameter state_1 = 3'd1;
parameter state_2 = 3'd2;
parameter state_3 = 3'd3;
parameter state_4 = 3'd4;
parameter state_5 = 3'd5;
parameter state_6 = 3'd6;
parameter state_7 = 3'd7;
 
// Assignments
assign a0 = addr_data[0];
assign rd = addr_data[19] ? data1_ : data0_ ; // Word de SRAM
assign bhr = { {8{rd[15]}}, rd[15:8] };
assign blr = { {8{rd[7]}}, rd[7:0] };
 
assign roe_ = ~we;
assign rcs_ = 1'b0;
 
assign addr1 = addr_data[18:1] + 18'd1;
 
assign data0_ = we ? 16'hzzzz : wr;
assign data1_ = we ? 16'hzzzz : wr;
assign wr = a0 ? {wr_data[7:0],wr_data[15:8]} : wr_data;
 
assign rddata = w_b ? (a0 ? bhr:blr) : (a0 ? bhr:rd);
 
assign rble0_ = addr_data[19] | rble;
assign rbhe0_ = addr_data[19] | rbhe;
assign rble1_ = ~addr_data[19] | rble;
assign rbhe1_ = ~addr_data[19] | rbhe;
 
always @(posedge clk)
if (~boot) reset <= 1'b1;
else reset <= 1'b0;
 
always @(posedge clk2x)
begin
case (state)
state_0: begin rble <= ~we & a0; rbhe <= ~we & w_b & ~a0; state <= state_1; end
state_1: begin addr_ <= addr_data[18:1]; state <= state_2; end
state_2: begin rwe_ <= we; state <= state_3; end
state_3: begin if (~we) rwe_ <= 1'b1; else rd_data <= rddata; state <= state_4; end
state_4: begin if (~we & ~w_b & a0) begin rble <= 1'b0; rbhe <= 1'b1; end state <= state_5; end
state_5: begin addr_ <= addr1; state <= state_6; end
state_6: begin rwe_ <= we | w_b | ~a0; state <= state_7; end
default: begin
rwe_ <= 1'b1;
if (clk) state <= state_0;
addr_ <= 18'hz;
if(~w_b & a0) rd_data[15:8] <= blr[7:0];
end
endcase
if (reset) begin rwe_ <= 1'b1; state <= state_7; end
end
endmodule
/trunk/impl/stratix2-nios2dk/zet/fetch.v
0,0 → 1,288
`include "defines.v"
 
module fetch(clk, reset, cs, ip, data, ir, off, imm, pc, bytefetch, fetch_or_exec);
// IO ports
input clk, reset;
input [15:0] cs, ip;
input [15:0] data;
output [`IR_SIZE-1:0] ir;
output reg [15:0] off;
output [15:0] imm;
output [19:0] pc;
output bytefetch;
output fetch_or_exec;
 
// Registers
reg [3:0] state;
reg [7:0] opcode_r, modrm_r;
reg [15:0] off_m, imm_m, imm_r;
reg [`IR_SIZE-1:0] ir_r;
 
// Net declarations
wire [19:0] pc;
wire [7:0] opcode, modrm;
wire sm, dm, need_modrm, need_off, need_imm, off_size, imm_size;
wire [1:0] mod;
wire [2:0] regm;
wire [2:0] rm;
wire d;
wire [2:0] dst, src;
wire [3:0] base, index;
wire [`IR_SIZE-1:0] ir0, ir1, ir2, ir3;
wire [15:0] off0, off1, off2, off3;
wire [15:0] imm0, imm1, imm2, imm3;
wire [1:0] ninstrs; // Number of IRs
 
// Module instantiation
lookup_op op0(opcode, dst, sm, dm, src, base, index, 2'b11, off_m, mod, regm,
imm_m, need_off, off_size, need_imm, imm_size, need_modrm,
ir0, ir1, ir2, off0, off1, off2, imm0, imm1, imm2, ninstrs,
clk);
memory_regs mr(rm, mod, base, index);
 
// Assignments
assign pc = (cs << 4) + ip;
assign mod = modrm[7:6];
assign regm = modrm[5:3];
assign rm = modrm[2:0];
assign d = opcode[1];
assign opcode = state ? opcode_r : data[7:0];
assign modrm = (state == 4'd1) ? data[7:0] : modrm_r;
assign fetch_or_exec = (state > 4'h3 && state != 4'h8);
 
assign dst = d ? regm : rm;
assign sm = d & (mod != 2'b11);
assign dm = ~d & (mod != 2'b11);
assign src = d ? rm : regm;
assign bytefetch = state[1] ? (state[0] ? ~imm_size : ~off_size) : 1'b1;
assign imm = (state < 4'h4) ?
(((state == 4'h2) & off_size | (state==4'h3) & imm_size) ? 16'd2 : 16'd1) : imm_r;
assign ir = (state < 4'h4) ? `ADD_IP : ir_r;
 
parameter state_0 = 4'h0;
parameter state_1 = 4'h1;
parameter state_2 = 4'h2;
parameter state_3 = 4'h3;
parameter state_4 = 4'h4;
parameter state_5 = 4'h5;
parameter state_6 = 4'h6;
parameter state_7 = 4'h7;
parameter state_8 = 4'h8;
 
// Behaviour
always @(posedge clk)
if (~reset) state <= state_7;
else
case (state)
 
state_0: // opcode fetch
begin
opcode_r <= data[7:0];
state <= need_modrm ? state_1 :
(need_off ? state_2 : need_imm ? state_3 : state_4);
off_m <= 16'h0;
end
 
state_1: // need modrm
begin
modrm_r <= data[7:0];
state <= need_off ? state_2 : (need_imm ? state_3 : state_4);
end
 
state_2: // need off
begin
off_m <= data;
state <= need_imm ? state_3 : state_4;
end
 
state_3: // need imm
begin
imm_m <= data;
state <= state_4;
end
 
state_4: // exec 1st IR
begin
ir_r <= ir0;
off <= off0;
imm_r <= imm0;
state <= (ninstrs == 2'd1) ? state_7 : state_5;
end
 
state_5: // exec 2nd IR
begin
ir_r <= ir1;
off <= off1;
imm_r <= imm1;
state <= (ninstrs == 2'd2) ? state_7 : state_6;
end
 
state_6: // exec 3rd IR
begin
ir_r <= ir2;
off <= off2;
imm_r <= imm2;
state <= state_7;
end
 
state_7: begin ir_r <= `IR_SIZE'h0; state <= state_8; end
state_8: state <= state_0;
default: begin ir_r <= `IR_SIZE'h0; state <= state_8; end
endcase
 
endmodule
 
module lookup_op (opcode, dst, sm, dm, src, base, index, seg, off, mod, regm, imm,
need_off, off_size, need_imm, imm_size, need_modrm,
ir0, ir1, ir2, off0, off1, off2, imm0, imm1, imm2, ninstrs,
clk);
// IO Ports
input [7:0] opcode;
input [2:0] dst; // destination register
input sm; // source in memory?
input dm; // dest in memory?
input [2:0] src; // source register
input [3:0] base, index; // for memory access
input [1:0] seg; // segment register for memory ops
input [15:0] off, imm; // offset and immediate operands
input [1:0] mod; // offset mode
input clk;
input [2:0] regm;
 
output reg need_off, need_imm, imm_size, need_modrm, off_size;
output [`IR_SIZE-1:0] ir0, ir1, ir2;
output [15:0] off0, off1, off2;
output [15:0] imm0, imm1, imm2;
 
reg [`IR_SIZE-1:0] irs[2:0]; // irs for the operation
reg [15:0] offs[2:0]; // offsets for the IRs
reg [15:0] imms[2:0]; // Immediates for the IRs
output reg [1:0] ninstrs; // Number of IRs
 
// Net declarations
wire off_size_mod, need_off_mod;
wire b;
 
// Assignments
assign off_size_mod = (base == 4'b1100 && index == 4'b1100) ? 1'b1 : mod[1];
assign need_off_mod = (base == 4'b1100 && index == 4'b1100) || ^mod;
 
assign ir0 = irs[0]; assign ir1 = irs[1]; assign ir2 = irs[2];
assign off0 = offs[0]; assign off1 = offs[1]; assign off2 = offs[2];
assign imm0 = imms[0]; assign imm1 = imms[1]; assign imm2 = imms[2];
 
assign b = ~opcode[0];
 
// Behaviour
always @(negedge clk)
casex (opcode)
// r->r, r->m, m->r s->m, s->r r->s, m->s
8'b1000_10xx, 8'b1000_1100, 8'b1000_1110: begin // mov
if (dm) begin // [byte bs, word cs] r->m, s->m
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { b, 1'b0, 1'b0, 1'bx, b & ~opcode[2], 3'b000, 3'b111, 1'b0, 2'b00, 1'b1, 1'b0, 4'bxxxx, opcode[2] & ~opcode[1], src, index, base, seg };
need_off <= need_off_mod;
end else if(sm) begin // [byte ds, word es] m->r, m->s
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { b, 1'b0, 1'b0, 1'b0, b & ~opcode[2], 3'b000, 3'b111, 1'b0, 2'b01, 1'b0, 1'b0, opcode[2] & opcode[1], dst, 4'bxxxx, index, base, seg };
need_off <= need_off_mod;
end else begin // [byte 9s, word as] r->r s->r r->s
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { 1'bx, b & ~opcode[2], 1'b1, 1'b1, b, 3'b001, 3'b001, 1'b0, 2'b01, 1'b0, 1'b0, opcode[2] & opcode[1], dst, 4'bxxxx, 4'bxxxx, opcode[2] & ~opcode[1], src, 2'bxx };
imms[0] <= 16'd0;
need_off <= 1'b0;
end
need_imm <= 1'b0; need_modrm <= 1'b1; off_size <= off_size_mod; offs[0] <= off; ninstrs <= 2'd1;
end
 
8'b1010_00xx: begin // mov
if (opcode[1]) // a->m [byte bs, word cs]
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { b, 1'b0, 1'b0, 1'bx, b, 3'b000, 3'b111, 1'b0, 2'b00, 1'b1, 1'b0, 4'bxxxx, 4'b0000, 4'b1100, 4'b1100, seg };
else // m->a [byte ds, word es]
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { b, 1'b0, 1'b0, 1'b0, b, 3'b000, 3'b111, 1'b0, 2'b01, 1'b0, 1'b0, 4'b0000, 4'bxxxx, 4'b1100, 4'b0000, seg };
 
need_off <= 1'b1; need_imm <= 1'b0; need_modrm <= 1'b0; off_size <= 1'b1; offs[0] <= off; ninstrs <= 2'd1;
end
 
8'b1011_xxxx: begin // mov [byte 13s, word 14s]
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { 1'bx, 1'bx, 1'b1, 1'b1, ~opcode[3], 3'b001, 3'b001, 1'b0, 2'b01, 1'b0, 1'b0, 1'b0, opcode[2:0], 4'bxxxx, 4'bxxxx, 4'b1100, 2'bxx };
imms[0] <= imm;
need_off <= 1'b0; need_imm <= 1'b1; imm_size <= opcode[3]; need_modrm <= 1'b0; off_size <= 1'bx;
ninstrs <= 2'd1;
end
 
8'b1100_011x: begin // mov [byte 15s, word 17s]
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { 1'bx, 1'bx, 1'b1, 1'b1, b, 3'b001, 3'b001, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1101, 4'bxxxx, 4'bxxxx, 4'b1100, 2'bxx };
irs[1] <= { 1'bx, 1'b0, 1'b0, 1'bx, b, 3'b000, 3'b111, 1'b0, 2'b00, 1'b1, 1'b0, 4'bxxxx, 4'b1101, index, base, seg };
imms[0] <= imm;
offs[1] <= off;
need_off <= need_off_mod; need_imm <= 1'b1; imm_size <= ~b; need_modrm <= 1'b1; off_size <= off_size_mod;
ninstrs <= 2'd2;
end
 
8'b1110_10x1: begin // jmp direct [off8 1s, off16 2s]
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { 1'bx, 1'b0, 1'b1, 1'b1, 1'b0, 3'b001, 3'b001, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1111, 4'bxxxx, 4'bxxxx, 4'b1111, 2'bxx };
imms[0] <= imm;
need_off <= 1'b0; need_imm <= 1'b1; imm_size <= ~opcode[1]; need_modrm <= 1'b0; off_size <= 1'bx;
ninstrs <= 2'd1;
end
 
8'b1110_1010: begin // jmp indirect different segment [5s]
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { 1'bx, 1'b0, 1'b1, 1'b1, 1'b0, 3'b001, 3'b001, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1001, 4'bxxxx, 4'bxxxx, 4'b1100, 2'bxx };
irs[1] <= { 1'bx, 1'b0, 1'b1, 1'b1, 1'b0, 3'b001, 3'b001, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1111, 4'bxxxx, 4'bxxxx, 4'b1100, 2'bxx };
imms[0] <= imm;
imms[1] <= off;
need_modrm <= 1'b0; need_off <= 1'b1; off_size <= 1'b1; need_imm <= 1'b1; imm_size <= 1'b1;
ninstrs <= 2'd2;
end
 
8'b1111_1111: begin
case (regm)
3'b100: begin // jmp indirect, same seg
if (mod==2'b11) begin // [3s]
irs[0] <= { 1'bx, 1'b0, 1'b1, 1'b1, 1'b0, 3'b001, 3'b001, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1111, 4'bxxxx, 4'bxxxx, 1'b0, src, 2'bxx };
imms[0] <= 16'd0;
end else // [4s]
irs[0] <= { 1'bx, 1'b0, 1'b0, 1'b0, 1'b0, 3'b000, 3'b111, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1111, 4'bxxxx, index, base, 2'b10 };
ninstrs <= 2'd1;
end
3'b101: begin // jmp indirect, different seg [7s]
// ac ab im ma by fun t wh wr wm wf ad_d ad_c ad_b ad_a s
irs[0] <= { 1'bx, 1'b0, 1'b0, 1'b0, 1'b0, 3'b000, 3'b111, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1111, 4'bxxxx, index, base, 2'b10 };
irs[1] <= { 1'bx, 1'b0, 1'b0, 1'b0, 1'b0, 3'b001, 3'b111, 1'b0, 2'b01, 1'b0, 1'b0, 4'b1001, 4'bxxxx, index, base, 2'b10 };
offs[1] <= off;
ninstrs <= 2'd2;
end
endcase
offs[0] <= off;
need_modrm <= 1'b1; need_off <= need_off_mod; off_size <= off_size_mod; need_imm <= 1'b0; imm_size <= 1'bx;
end
 
endcase
endmodule
 
module memory_regs(rm, mod, base, index);
// IO Ports
input [2:0] rm;
input [1:0] mod;
output reg [3:0] base, index;
 
// Behaviour
always @(rm or mod)
case (rm)
3'b000: begin base <= 4'b0011; index <= 4'b0110; end
3'b001: begin base <= 4'b0011; index <= 4'b0111; end
3'b010: begin base <= 4'b0101; index <= 4'b0110; end
3'b011: begin base <= 4'b0101; index <= 4'b0111; end
3'b100: begin base <= 4'b1100; index <= 4'b0110; end
3'b101: begin base <= 4'b1100; index <= 4'b0111; end
3'b110: begin base <= mod ? 4'b0101 : 4'b1100; index <= 4'b1100; end
3'b111: begin base <= 4'b0011; index <= 4'b1100; end
endcase
endmodule
/trunk/impl/stratix2-nios2dk/util/lcd_display.v
0,0 → 1,185
module lcd_display(f1, f2, m1, m2, go, busy, clk, boot, rs_, rw_, e_, db_);
// IO ports
input [63:0] f1, f2;
input [15:0] m1, m2;
input clk, boot, go;
output reg busy, rs_, rw_;
inout [7:0] db_;
output e_;
 
// Net declarations
reg [7:0] writedata, state;
reg [3:0] x;
wire [7:0] readdata;
wire [3:0] out_m1, out_m2;
wire b, mask1, mask2;
// Module instantiations
mux16_4 mux1(x, f1[63:60], f1[59:56], f1[55:52], f1[51:48], f1[47:44], f1[43:40],
f1[39:36], f1[35:32], f1[31:28], f1[27:24], f1[23:20], f1[19:16],
f1[15:12], f1[11:08], f1[07:04], f1[03:00], out_m1);
 
mux16_4 mux2(x, f2[63:60], f2[59:56], f2[55:52], f2[51:48], f2[47:44], f2[43:40],
f2[39:36], f2[35:32], f2[31:28], f2[27:24], f2[23:20], f2[19:16],
f2[15:12], f2[11:08], f2[07:04], f2[03:00], out_m2);
 
mux16_1 mux3(x, m1[15], m1[14], m1[13], m1[12], m1[11], m1[10], m1[9], m1[8],
m1[7], m1[6], m1[5], m1[4], m1[3], m1[2], m1[1], m1[0], mask1);
 
mux16_1 mux4(x, m2[15], m2[14], m2[13], m2[12], m2[11], m2[10], m2[9], m2[8],
m2[7], m2[6], m2[5], m2[4], m2[3], m2[2], m2[1], m2[0], mask2);
 
// Assignments
assign readdata = db_;
assign db_ = rw_ ? 8'bz : writedata;
assign e_ = clk;
assign b = readdata[7];
 
// Behavioral
always @(posedge clk)
if (~boot)
begin
state <= 8'd00;
rs_ <= 1'b0; // 0: Instruction reg (busy flag)
rw_ <= 1'b1; // 1: Read
busy <= 1'b1;
x <= 4'b0;
end
else
case (state)
8'd00: if (!b) state <= 8'd01;
 
// Establece el modo de operacion de 8 bits y selecciona
// el display de 2 lineas y caracteres de 5x8
8'd01: begin rs_ <= 1'b0; rw_ <= 1'b0; writedata <= 8'h38; state <= 8'd02; end
8'd02: begin rs_ <= 1'b0; rw_ <= 1'b1; state <= 8'd03; end
8'd03: if (!b) state <= 8'd04;
 
// Enciende el display y el cursor
8'd04: begin rs_ <= 1'b0; rw_ <= 1'b0; writedata <= 8'h0e; state <= 8'd05; end
8'd05: begin rs_ <= 1'b0; rw_ <= 1'b1; state <= 8'd06; end
8'd06: if (!b) state <= 8'd07;
 
// Establece el modo de autoincremento de direccion y mover el cursor a la derecha
8'd07: begin rs_ <= 1'b0; rw_ <= 1'b0; writedata <= 8'h06; state <= 8'd08; end
8'd08: begin rs_ <= 1'b0; rw_ <= 1'b1; state <= 8'd09; end
8'd09: if (!b) state <= 8'd10;
 
// Ya estamos listos
8'd10: begin busy <= 1'b0; state <= 8'd11; end
8'd11: if (go) state <= 8'd12;
 
// Desplaza el cursor a la posición original
8'd12: begin rs_ <= 1'b0; rw_ <= 1'b0; writedata <= 8'h02; state <= 8'd13; end
8'd13: begin rs_ <= 1'b0; rw_ <= 1'b1; state <= 8'd14; end
8'd14: if (!b) state <= 8'd15;
 
// Empezamos a trabajar: 1º enviamos la primera fila
8'd15: begin busy <= 1'b1; state <= 8'd16; end
 
8'd16: begin
rs_ <= 1'b1; rw_ <= 1'b0;
if (mask1) writedata <= itoa(out_m1);
else writedata <= 8'h20; // Espacio en blanco
x = x + 4'd1;
state <= 8'd17;
end
8'd17: begin rs_ <= 1'b0; rw_ <= 1'b1; state <= 8'd18; end
8'd18: if (!b) state <= 8'd19;
8'd19: if (x == 4'd00) state <= 8'd20; else state <= 8'd16;
 
// Movemos el cursor a la segunda fila
8'd20: begin rs_ <= 1'b0; rw_ <= 1'b0; writedata <= 8'hc0; state <= 8'd21; end
8'd21: begin rs_ <= 1'b0; rw_ <= 1'b1; state <= 8'd22; end
8'd22: if (!b) state <= 8'd23;
 
// Enviamos la segunda fila
8'd23: begin
rs_ <= 1'b1; rw_ <= 1'b0;
if (mask2) writedata <= itoa(out_m2);
else writedata <= 8'h20; // Espacio en blanco
x = x + 4'd1;
state <= 8'd24;
end
8'd24: begin rs_ <= 1'b0; rw_ <= 1'b1; state <= 8'd25; end
8'd25: if (!b) state <= 8'd26;
8'd26: if (x == 4'd00) state <= 8'd10; else state <= 8'd23;
endcase
 
// Pasa un entero de 4 bits a su carácter hexadecimal
function [7:0] itoa;
input [3:0] i;
begin
if (i < 8'd10) itoa = i + 8'h30;
else itoa = i + 8'h57;
end
endfunction
endmodule
 
//
// Multiplexor 16:1 de 4 bits d'amplada
//
module mux16_4(sel, in0, in1, in2, in3, in4, in5, in6, in7,
in8, in9, in10, in11, in12, in13, in14, in15, out);
input [3:0] sel;
input [3:0] in0, in1, in2, in3, in4, in5, in6, in7;
input [3:0] in8, in9, in10, in11, in12, in13, in14, in15;
output [3:0] out;
 
reg [3:0] out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7
or in8 or in9 or in10 or in11 or in12 or in13 or in14 or in15)
case(sel)
4'd00: out = in0;
4'd01: out = in1;
4'd02: out = in2;
4'd03: out = in3;
4'd04: out = in4;
4'd05: out = in5;
4'd06: out = in6;
4'd07: out = in7;
4'd08: out = in8;
4'd09: out = in9;
4'd10: out = in10;
4'd11: out = in11;
4'd12: out = in12;
4'd13: out = in13;
4'd14: out = in14;
4'd15: out = in15;
endcase
endmodule
 
//
// Multiplexor 16:1 d'1 bits d'amplada
//
module mux16_1(sel, in0, in1, in2, in3, in4, in5, in6, in7,
in8, in9, in10, in11, in12, in13, in14, in15, out);
input [3:0] sel;
input in0, in1, in2, in3, in4, in5, in6, in7;
input in8, in9, in10, in11, in12, in13, in14, in15;
output out;
 
reg out;
 
always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7
or in8 or in9 or in10 or in11 or in12 or in13 or in14 or in15)
case(sel)
4'd00: out = in0;
4'd01: out = in1;
4'd02: out = in2;
4'd03: out = in3;
4'd04: out = in4;
4'd05: out = in5;
4'd06: out = in6;
4'd07: out = in7;
4'd08: out = in8;
4'd09: out = in9;
4'd10: out = in10;
4'd11: out = in11;
4'd12: out = in12;
4'd13: out = in13;
4'd14: out = in14;
4'd15: out = in15;
endcase
endmodule
/trunk/tests/i86/04_jump1.s
0,0 → 1,213
# Jump instruction testbench 1
#
# At the end (6215ns in rtl-model, 287us in spartan3), %ax=0x1234
#
# ja/jnbe 1
# jae/jnb/jnc 2
# jb/jnae/jc 3
# jbe/jna 4
# je/jz 5
# jg/jnle 6
# jge/jnl 7
# jl/jnge 8
# jle/jng 9
# jne/jnz 10
# jno 11
# jnp/jpo 12
# jns 13
# jo 14
# jp/jpe 15
# js 16
#
.code16
start:
movw $0, %cx
movw $64, %bx
movw $0x1000, %sp
movw %sp, %ss
push %bx
jmp j00
 
# ja/jnbe
j00err:
jmp jerr
j00:
stc
ja j00err # (1)
clc
ja j01
 
# jae/jnb/jnc
j01err:
jmp jerr
j01:
stc
jae j01err # (2)
clc
jae j02
 
# jb/jnae/jc
j02err:
jmp jerr
j02:
jb j02err # (3)
stc
jb j03
 
# jbe/jna
j03err:
jmp jerr
j03:
clc
jbe j03err # (4)
popf
jbe j04
 
# je/jz
j04err:
jmp jerr
j04:
push %cx
popf
je j04err # (5)
push %bx
popf
je j05
 
# jg/jnle
j05err:
jmp jerr
j05:
movw $0x08c0, %dx
push %dx
popf
jg j05err # (6)
movw $0x0880, %dx
push %dx
popf
jg j06
 
# jge/jnl
j06err:
jmp jerr
j06:
movw $0x80, %dx
push %dx
popf
jge j06err # (7)
push %cx
popf
jge j07
 
# jl/jnge
j07err:
jmp jerr
j07:
jl j07err # (8)
movw $0x0800, %dx
push %dx
popf
jl j08
 
# jle/jng
j08err:
jmp jerr
j08:
push %cx
popf
jle j08err # (9)
push %bx
popf
jle j09
 
# jne/jnz
j09err:
jmp jerr
j09:
jne j09err # (10)
movw $0xcbf, %dx
push %dx
popf
jne j10
 
# jno
j10err:
jmp jerr
j10:
movw $0x0800, %dx
push %dx
popf
jno j10err # (11)
movw $0x6ff, %dx
push %dx
popf
jno j11
 
# jnp/jpo
j11err:
jmp jerr
j11:
movw $0x4, %dx
push %dx
popf
jnp j11err # (12)
push %cx
popf
jnp j12
 
# jns
j12err:
jmp jerr
j12:
movw $0xeff, %dx
push %dx
popf
jns j12err # (13)
push %cx
popf
jns j13
 
# jo
j13err:
jmp jerr
j13:
jo j13err # (14)
movw $0x800, %dx
push %dx
popf
jo j14
 
# jp/jpe
j14err:
jmp jerr
j14:
jp j14err # (15)
movw $0x804, %dx
push %dx
popf
jp j15
 
# js
j15err:
jmp jerr
j15:
js j15err # (16)
movw $0x884, %dx
push %dx
popf
js j16
jmp jerr
 
# All correct
j16:
movw $0x1234, %ax
hlt
 
.org 65520
jmp start
 
jerr:
hlt
 
.org 65535
.byte 0xff
/trunk/tests/i86/07_strings.s
0,0 → 1,115
# String instruction testbench
#
# At the end (3995ns in rtl-model, 276.1us in spartan3), %ax=0x1234
#
# cmpsb 1
# cmpsw 2
# lodsb 3
# lodsw 4
# movsb 5
# movsw 6
# scasb 7
# scasw 8
# stosb 9
# stosw 10
#
.code16
start:
movw $0xf000, %cx
movw %cx, %ds
movw %cx, %es
movw $0x1000, %si
movw $0x2001, %di
 
cmpsb # (1) flags=0x97 (SAPC)
pushf
ret
 
.org 0x46
cmpsb # (1) flags=0x82 (S)
pushf
ret
 
.org 0x82
cmpsb # (1) flags=0x812 (OA)
pushf
ret
 
.org 0x97
cmpsb # (1) flags=0x46 (ZP)
pushf
ret
 
.org 0x812
cmpsw # (2)
pushf
ret
 
.org 0x883
movb $0x10, %ah
std
lodsb # (3)
jmp *%ax
 
.org 0x1000
.byte 0x01,0xff,0xff,0x80
.word 0x0002
.byte 0xc2
 
.org 0x10c2
lodsw # (4)
jmp *%ax
 
.org 0x1300
movw %ax, (%di)
movw %dx, %es
scasw # (8)
jz stor
 
.org 0x1350
stor:
movb $0x80, %al
std
stosb # (9)
jmp *(%di)
 
.org 0x2001
.byte 0x02,0xff,0x01,0x01
.word 0x8001
 
.org 0x8013
movw $0xd000, %ax
stosw # (10)
jmp *2(%di)
 
.org 0x80c2
movw %cx, %ds
movsw # (6)
movw %dx, %ds
jmp *2(%di)
 
.org 0x80ff
movw $0x2002, %di
movw %cx, %es
cld
scasb # (7)
lahf
jmp *%ax
 
.org 0xc200
movw $0x1000, %dx
movw %dx, %es
movw $0xffff, %di
movsb # (5)
movw %dx, %ds
movb $0xc2, (%di)
jmp *(%di)
 
.org 0xd000
movw $0x1234, %ax
hlt
.org 65520
jmp start
 
.org 65535
.byte 0xff
/trunk/tests/i86/.bochsrc
0,0 → 1,18
romimage: file=bios.out
cpu: count=1, ips=10000000, reset_on_triple_fault=1
megs: 2
vgaromimage: file=$BXSHARE/VGABIOS-lgpl-latest
vga: extension=none
floppy_bootsig_check: disabled=0
log: bochsout.txt
panic: action=ask
error: action=report
info: action=report
debug: action=ignore
debugger_log: -
vga_update_interval: 300000
keyboard_serial_delay: 250
keyboard_paste_delay: 100000
mouse: enabled=1, type=imps2
private_colormap: enabled=0
keyboard_mapping: enabled=1, map=$BXSHARE/keymaps/x11-pc-es.map
/trunk/tests/i86/05_jump2.s
0,0 → 1,82
# Jump instruction testbench 2
#
# At the end (3535ns in rtl-model, 274.05us in spartan3), %ax=0x1234
#
# call 1 (direct same seg), 2 (indirect reg, same seg),
# 3 (indirect mem, same seg), 4 (direct diff seg),
# 5 (indirect mem, diff seg)
#
# loop 6
# loope/loopz 7
# loopne/loopnz 8
# ret 9 (same seg), 10 (same seg, value), 11 (diff seg),
# 12 (diff seg, value)
# jcxz 13
.code16
 
start:
movw $0xf000, %bx
movw %bx, %ds
movw $0x1290, %ax
 
movw $0x5, %cx
again:
push %cx
loop again # (6)
 
call *%ax # (2)
ret # (9)
 
.org 0x1290
ag2:
movw $0xffff, %cx
loope ag2 # (7) branch not taken
movw $64, %dx
push %dx
popf
loope cont # (7) branch taken
hlt
cont:
lcall $0xe342, $0xebe0 # (4)
jcxz cont # (13) branch not taken
movw $0, %cx
jcxz exit # (13) branch taken
hlt
exit:
ret $10 # (10)
 
.org 0x2000
call *(0x3000) # (3)
movw $0, %dx
push %dx
popf
hang:
movw $1, %cx
loopnz hang # (8) branch not taken
loopne cont1 # (8) branch taken
hlt
cont1:
lret # (11)
.org 0x3000
.word 0xfde0
.word 0x4000
.word 0xf000
 
.org 0x3200
movw $0x2ff0, %bx
movw $0x10, %si
push %dx
lcall *2(%bx,%si) # (5)
ret
 
.org 0x4000
lret $2 # (12)
 
.org 65520
movw $0x1000, %sp
movw %sp, %ss
call start # (1)
movw $0x1234, %ax
hlt
.org 65535
.byte 0xff
/trunk/tests/i86/06_interrupt.s
0,0 → 1,69
# Interrupt instruction testbench
#
# At the end (3737ns in rtl-model, 275.9us in spartan3),
# %ax=0x1234, %bx=0x0ed7
#
# int 1, 2 (int 3)
# into 3
# iret 4
#
.code16
start:
movw $0, %dx
movw %dx, %ds
movw $0x1000, %sp
movw %sp, %ss
movw $0xebe0, (52)
movw $0xe342, (54)
 
movw $0x0eff, %ax
push %ax
popf
 
int $13 # (1)
 
jmp *%ax
 
.org 0x0cd7
pushf
pop %bx
movw $0xebe0, (12)
movw $0xe342, (14)
 
int $3 # (2)
 
movw $0x3001, (16)
movw $0xf000, (18)
 
into # (3) branch taken
hlt
 
.org 0x2000
pushf
pop %ax
clc
iret # (4)
 
.org 0x3001
pop %cx
movw $0x4002, %cx
push %cx
iret
 
.org 0x4002
movw $0x4ff, %dx
push %dx
popf
movw $0x5000, (16)
 
into # (3) branch not taken
movw $0x1234, %ax
hlt
 
.org 0x5000
hlt
 
.org 65520
jmp start
.org 65535
.byte 0xff
/trunk/tests/i86/03_control.s
0,0 → 1,53
# Microprocessor control instruction test bench
#
# At the end (1355ns in rtl-model,262.4us in spartan3),
# %ax=0x08d6 and %bx=0x0603
#
# clc (1)
# cld (2)
# cli (3)
# cmc (4)
# hlt (5)
# nop (6)
# stc (7)
# std (8)
# sti (9)
#
.code16
start:
movw $0x1000, %ax
movw %ax, %ss
movw $0x1000, %sp
 
movw $0xfeff, %cx
push %cx
popf
 
clc # (1)
cld # (2)
cli # (3)
 
nop # (6)
 
pushf
pop %ax # %ax = 0x08d6
 
movw $0x1, %dx
push %dx
popf
 
cmc # (4)
stc # (7)
std # (8)
sti # (9)
 
pushf
pop %bx # %bx = 0x0603
 
hlt # (5)
 
.org 65520
jmp start
 
.org 65535
.byte 0xff
/trunk/tests/i86/addsub.s
0,0 → 1,207
.code16
a:
 
#
# ADC
#
# 1: A negativo, B positivo: A: ffff B: 0001, A+B=0, ZAPC
movw $0xffff,%ax
movw $1,%bx
adcw %bx,%ax
 
# 2: A negativo, B positivo, A+B < 16 bits: A: ffff B: ffff, C A+B=ffff SAPC
movw $0xffff,%ax
movw $0xffff,%bx
adcw %bx,%ax
 
# 3: A positivo, B positivo, A+B < 16 bits: A: 0001 B: 0002, A+B=3, P
movw $0x0001,%ax
movw $0x0002, %bx
adcw %bx,%ax
 
# 4: A pos, B pos, A+B = 16 bits: A: 7fff B: 0001, A+B=8000, OSAP
movw $0x7fff,%ax
movw $0x0001,%bx
adcw %bx,%ax
 
# 5: A neg, B neg, A+B = 16 bits: A: 8000 B: ffff, A+B=0fff OPC
movw $0x8000,%ax
movw $0xffff,%bx
adcw %bx,%ax
 
# 6: A aleat, B aleat: A: 1a62 B: ed8a, A+B=
movw $0x1a62,%ax
movw $0xed8a,%bx
adcw %bx,%ax
 
#
# ADD
#
# 7: A negativo, B positivo: A: ffff B: 0001, A+B=0, ZAPC
movw $0xffff,%ax
movw $1,%bx
addw %bx,%ax
 
# 8: A negativo, B positivo, A+B < 16 bits: A: ffff B: ffff, C A+B=ffff SAPC
movw $0xffff,%ax
movw $0xffff,%bx
addw %bx,%ax
 
# 9: A positivo, B positivo, A+B < 16 bits: A: 0001 B: 0002, A+B=3, P
movw $0x0001,%ax
movw $0x0002, %bx
addw %bx,%ax
 
# 10: A pos, B pos, A+B = 16 bits: A: 7fff B: 0001, A+B=8000, OSAP
movw $0x7fff,%ax
movw $0x0001,%bx
addw %bx,%ax
 
# 11: A neg, B neg, A+B = 16 bits: A: 8000 B: ffff, A+B=0fff OPC
movw $0x8000,%ax
movw $0xffff,%bx
addw %bx,%ax
 
# 12: A aleat, B aleat: A: 027f B: 846c, A+B=
movw $0x027f,%ax
movw $0x846c,%bx
addw %bx,%ax
 
#
# INC
#
# 13: A-, -1: A: ffff. Da carry, no debería cambiar el flag de C
movw $0xffff,%ax
incw %ax
 
# 14: A+: 7fff. Overflow
movw $0x7fff,%ax
incw %ax
 
# 15: A aleat. 4513
movw $0x4513,%ax
incw %ax
 
#
# DEC
#
# 16: A: 0000.
movw $0x0000,%ax
decw %ax
 
# 17: B: 8000. Underflow
movw $0x8000,%ax
decw %ax
 
# 18: A aleat. c7db
movw $0xc7db,%ax
decw %ax
 
#
# NEG
#
# 19: A: 0
movw $0x0000,%ax
negw %ax
 
# 20: A: 8000. Overflow
movw $0x8000,%ax
negw %ax
 
# 21: A aleat. fac4
movw $0xfac4,%ax
negw %ax
 
#
# SBB
#
# 22: A+, B+, A-B siempre será menor de 16 bits: A: 0001 B: 0002 A-B=ffff SAPC
movw $0x0001,%ax
movw $0x0002,%bx
sbbw %bx,%ax
 
# 23: A-, B-, A-B siempre será menor de 16 bits: A: ffff B: ffff A-B=0 ZP
movw $0xffff,%ax
movw $0xffff,%bx
sbbw %bx,%ax
 
# 24: A-, B+, A-B < 16 bits: A: ffff B:1 A-B=fffe S
movw $0xffff,%ax
movw $0x0001,%bx
sbbw %bx,%ax
 
# 25: A-, B+, A-B = 16 bits: A: 8000 B:1 A-B=7fff OAP
movw $0x8000,%ax
movw $0x0001,%bx
sbbw %bx,%ax
 
# 26: A aleat, B aleat, con carry: A: a627 B: 03c5, C A-B=
movw $0xa627,%ax
movw $0x03c5,%bx
stc
sbbw %bx,%ax
 
#
# SUB
#
# 27: A+, B+, A-B siempre será menor de 16 bits: A: 0001 B: 0002 A-B=ffff SAPC
movw $0x0001,%ax
movw $0x0002,%bx
subw %bx,%ax
 
# 28: A-, B-, A-B siempre será menor de 16 bits: A: ffff B: ffff A-B=0 ZP
movw $0xffff,%ax
movw $0xffff,%bx
subw %bx,%ax
 
# 29: A-, B+, A-B < 16 bits: A: ffff B:1 A-B=fffe S
movw $0xffff,%ax
movw $0x0001,%bx
subw %bx,%ax
 
# 30: A-, B+, A-B = 16 bits: A: 8000 B:1 A-B=7fff OAP
movw $0x8000,%ax
movw $0x0001,%bx
subw %bx,%ax
 
# 31: A aleat, B aleat, con carry: A: a627 B: 03c5, C A-B=
movw $0xa627,%ax
movw $0x03c5,%bx
stc
subw %bx,%ax
 
#
# CMP
#
# 32: A+, B+, A-B siempre será menor de 16 bits: A: 0001 B: 0002 A-B=ffff SAPC
movw $0x0001,%ax
movw $0x0002,%bx
cmpw %bx,%ax
 
# 33: A-, B-, A-B siempre será menor de 16 bits: A: ffff B: ffff A-B=0 ZP
movw $0xffff,%ax
movw $0xffff,%bx
cmpw %bx,%ax
 
# 34: A-, B+, A-B < 16 bits: A: ffff B:1 A-B=fffe S
movw $0xffff,%ax
movw $0x0001,%bx
cmpw %bx,%ax
 
# 35: A-, B+, A-B = 16 bits: A: 8000 B:1 A-B=7fff OAP
movw $0x8000,%ax
movw $0x0001,%bx
cmpw %bx,%ax
 
# 36: A aleat, B aleat, con carry: A: aa97 B: 3b46, C A-B=
movw $0xaa97,%ax
movw $0x3b46,%bx
stc
cmpw %bx,%ax
 
 
.org 65520
jmp a
 
.org 65535
.byte 0xff
/trunk/tests/i86/02_datatrnf.s
0,0 → 1,88
# Recursive testbench for transfer data instructions, except "mov"
# but ("jmp" & "mov" must work!!)
#
# At the end (3591ns in rtl-model, 274380ns in spartan3), %ax=0x8cf1
#
# sahf 1
# lahf 2
# lds 3
# lea 4
# les 5
# pop 6 (reg,non-st), 7 (seg), 8 (mem)
# popf 9
# push 10 (reg), 11 (seg), 12 (mem)
# pushf 13
# xchg 14 (reg-reg), 15 (reg-mem), 16 (reg-acum), 17 (reg-reg,byte)
# xlat 18
# in 19 (byte,imm) 20 (byte,dx) 21 (word,imm) 22 (word,dx)
# out 23 (byte,imm) 24 (byte,dx) 25 (word,imm) 26 (word,dx)
 
.code16
start:
movb $0xed, %ah
sahf # (1)
lahf # (2) Now %ah must have 0xc7
movb %ah, %al
outb %al, $0xb7 # (19)
movw $0xb7, %ax
movw %ax, %dx
movb $0xa5, %ah
inb %dx, %al # (24)
sahf
lahf # Now %ax must have 0x87c7
 
outw %ax, %dx # (22)
movw $0xf752, %ax
movw %ax, %bx
inw %dx, %ax # (26)
xchg %bx, %ax # (16)
movw %ax, %ds
lds 781(%bx), %si # (3) %ds=0x5678 and %si=0x1234
 
movw $-1, %bx
 
movw $0x1000, %ax
outw %ax, $0xb7 # (21)
 
movw $0x5798, %ax
movw %ax, %ss
movw $9, %sp
movw $0xabcd, %cx
push %cx # (10)
movw $0x8cf1, %cx
movw %cx, %es
push %es # (11)
popf # (9)
les -46(%bx,%si), %di # (5) %di=0x8cf1, %es=%0xabcd
lea -452(%bp,%di), %si # (4) %si=0x8b2d
pushf # (13)
inw $0xb7, %ax # (25)
movw %ax, %ds
pop 1(%si) # (8)
xchg 2(%bx,%si), %di # (15) %di=0x0cd3
push 2(%bx,%si) # (12)
pop %es # (7) %es=0x8cf1
pop %dx # (6)
push %dx
.byte 0x8f,0xc1 # (6) pop %cx (non-standard)
xchg %bx, %cx # (14) %bx=0xabcd, %cx=0xffff
movw %es, (%bx,%di)
movw $0xb800, %bx
movw $0xa0a1, %ax
xlat # (18) %al=0x8c
xchg %al, %ah # (17)
xlat # %ax=0x8cf1
movw $0xb7, %dx
outb %al, %dx # (20)
movb $0xff, %al
inb $0xb7, %al # (23) %ax=0x8cf1
 
.org 65520
jmp start
 
.org 65524
.word 0x1234
.word 0x5678
 
.org 65535
.byte 0xff
/trunk/tests/i86/09_vdu.s
0,0 → 1,13
.code16
start:
movw $0xb800, %dx
movw %dx, %ds
movw $0x034d, (4)
movw (1), %cx
hlt
 
.org 65520
jmp start
 
.org 65535
.byte 0xff
/trunk/tests/i86/01_jmpmov.s
0,0 → 1,66
# Prueba de todos los modos del mov y jmp
# At the end (2415ns in rtl-model, 274.3us in spartan3), %es = 0x4001
#
# mov: 1 (word), 2 (word), 3 (off, base+index+off), 4, 5 (off),
# 7 (byte,word), 8 (byte off), 9 (word base), 10 (byte,word),
# 11 (word off, byte base+index), 12 (imm,special)
# jmp: 1, 2, 3 (reg), 3 (mem base+index+off), 4, 5 (mem base+index+off)
.code16
start:
jmp b # (2) jmp
 
.org 14
b:
movw $0xf000, %bx # (10) mov word
movw %bx, %ds # (4) mov
movw (0xfff3), %ax # (2) mov word
jmp *%ax # (3) jmp reg
 
.org 0x1290
ljmp $0xe342, $0xebe0 # (4) jmp
 
.org 0x2000
movw $0x1000, %bx # (10) mov word
movw %bx, %ds # (4) mov
 
movb $0xfb, %ah # (10) mov byte
movb $0xe1, %al # (10) mov byte
movw %ax, (0x2501) # (1) mov word
 
movw $0x1001, (0x2600) # (11) mov word
movw (0x2600), %ss # (3) mov
 
movw %ss, (0x2601) # (5) mov
movb (0x2601), %dl # (8) mov byte
movb $0x00, %dh # (10) mov byte
movw %dx, %di # (7) mov word
 
movw $0x2506, %bp # (10) mov word
 
jmp *-22(%bp,%di) # (3) jmp mem
# m[0x12501] = 0xfbe1
.org 0x3001
.byte 0xc7,0xc0 # (12) movw $0x4001, %ax
.word 0x4001 # [not in a default codification]
movw $0x2501, %bx
movw %ax, (%bx) # (9) mov word
movw $2, %di
movb $0x00, (%bx,%di) # (11) mov byte
movb $4, %ch
movb %ch, %cl # (7) mov byte
movb $0, %ch
movw %cx, %si
movb $0xf0, -1(%bx,%si)
movw $0x3, %si
ljmp *-24(%bp,%si) # (5) jmp mem
 
.org 0x4001
movw -3(%bx,%si), %es
 
.org 65520
jmp start # (1) jmp
.word 0x1290
 
.org 65534
.word 0xffff
 
/trunk/tests/i86/Makefile
0,0 → 1,38
s3roms := $(patsubst %.s,%.s3rom,$(wildcard *.s))
rtlroms := $(patsubst %.s,%.rtlrom,$(wildcard *s))
all: $(s3roms) $(rtlroms)
 
# altera: ../../altera/zet/simulation/modelsim/bios0.dat ../../altera/zet/simulation/modelsim/bios1.dat
 
# ../../altera/zet/simulation/modelsim/bios0.dat: bios0.out
# hexdump -v -e '1/1 "%02X"' -e '"\n"' bios0.out > ../../altera/zet/simulation/modelsim/bios0.dat
 
#../../altera/zet/simulation/modelsim/bios1.dat: bios1.out
# hexdump -v -e '1/1 "%02X"' -e '"\n"' bios1.out > ../../altera/zet/simulation/modelsim/bios1.dat
 
#../../sim/bios.dat: bios.out
# hexdump -v -e '1/1 "%02X"' -e '"\n"' bios.out > ../../sim/bios.dat
# hexdump -v -e '1/2 "0x1%04_ax/%04x"' -e '"\n"' bios.out | awk -F/ '{printf "00%x/%s\n", rshift(strtonum($$1),1), $$2}' > ../../impl/spartan3an-sk/sim/flash-prom/memory_file
 
#$(BIOS): bios.out
# splitlh bios.out $(BIOS)
 
%.s3rom: %.out
hexdump -v -e '1/2 "0x1%04_ax/%04x"' -e '"\n"' $< | awk -F/ '{printf "00%x/%s\n", rshift(strtonum($$1),1), $$2}' > ../../impl/spartan3an-sk/sim/flash-prom/$@
 
%.mcs: %.out
echo :020000040001F9 > $@
hexdump -v -e '":20%04_ax00"' -e '32/1 "%02x"' -e '"00"' -e '"\n"' $< | tr a-z A-Z >> $@
echo :00000001FF >> $@
 
%.rtlrom: %.out
hexdump -v -e '1/1 "%02X"' -e '"\n"' $< > ../../sim/$@
 
%.out: %.o
objcopy -O binary -S $< $@
 
%.o: %.c
as $< -o $@
 
clean:
rm -f *.o *.out *.mcs ../../impl/spartan3an-sk/sim/flash-prom/*.s3rom ../../sim/*.rtlrom
/trunk/tests/i86/08_rep.s
0,0 → 1,281
# String repeating prefixes testbench
# At the end (12835ns in rtl-model, 319.5us in spartan3), %ax=0x1234
#
# rep, repz, repnz
 
.code16
start:
 
# Trivial cases. With %cx 0, nothing is executed
rep movsb
repz movsb
repnz movsb
rep cmpsb
repz cmpsb
repnz cmpsb
rep scasb
repz scasb
repnz scasb
rep lodsb
repz lodsb
repnz lodsb
rep stosb
repz stosb
repnz stosb
 
 
movw $0x40, %bx
push %bx
popf
 
# Now we have the zero flag set, nothing is executed because of %cx
 
rep movsb
repnz movsb
repz cmpsb
repnz cmpsb
repz scasb
repnz scasb
rep lodsb
repnz lodsb
rep stosb
repnz stosb
 
movw %di, %ax
movb $0x10, %ah
jmp *%ax # jump to 0xf1000
hlt
 
.org 0x102
jmp rep_stos_z
 
.org 0x607
jmp rep_lods_nz
 
.org 0x809
jmp rep_movs_nz
 
.org 0x0ffc
jmp cont_n5
.org 0x0ffe
jmp cont_n10
# Prefixes don't affect normal instructions
.org 0x1000
movw $0, %cx
.byte 0xf3
push %cx
jmp *%sp
 
cont_n10:
movw $0x110a, %cx
.byte 0xf3
push %cx
jmp *%sp
 
cont_n5:
jmp *%cx
 
.org 0x110a
movw $0x5, %cx
 
movw $0, %dx
push %dx
popf
.byte 0xf2
pop %cx
 
movw %cx, %ax
movb $0x20, %ah
jmp *%ax # jump to 0xf200a
 
.org 0x122c
jmp repz_cmps_nz
 
.org 0x122f
jmp repz_scas
 
# rep movs ZF=1
.org 0x200a
push %bx
popf
movw $2, %cx
movw $0x3000, %si
movw $0xf000, %ax
movw %ax, %ds
movw $0x1000, %ax
movw %ax, %es
movw $0x0000, %di
 
rep movsb
 
movw %ax, %ds
movw (0x0000), %ax
movw %di, %bp
movw %ax, (%bp,%si)
jcxz comp_disi
hlt
comp_disi:
jmp *(0x3004)
 
.org 0x3000
.byte 0x09,0x08,0x07,0x06,0x5,0x4,0x3,0x2,0x1,0xa,0xb,0xc,0xd
 
 
# rep movs ZF=0
rep_movs_nz:
movw $0xf000, %ax
movw %ax, %ds
movw $0x1, %cx
movw $0, %ax
pushw %ax
popf
 
rep movsw
 
movw $0x1000, %ax
movw %ax, %ds
movw (0x0002), %ax
movw %di, %bp
movw %ax, (%bp,%si)
jcxz movs_nz
hlt
movs_nz:
jmp *(0x3008)
 
# rep lods ZF=0
rep_lods_nz:
movw $0xf000, %ax
movw %ax, %ds
movw $0x3, %cx
rep lodsb
 
jmp *%ax
hlt
rep_lods_z:
# rep lods ZF=1
movw $0x40, %bx
push %bx
popf
movw $0xf000, %ax
movw %ax, %ds
movw $0x1, %cx
rep lodsw
jmp *%ax
 
# rep stos ZF=1
rep_stos_z:
movw $0x2, %cx
movw $0x4000, %ax
rep stosw
movw $0x1000, %ax
movw %ax, %ds
jmp *(0x0006)
hlt
 
.org 0x4000
# rep stos ZF=0
movw $0x0, %bx
push %bx
popf
movw $0x4, %cx
rep stosw
jcxz repz_cmps_z
hlt
 
# repz cmps ZF=1, but ZF=0 before %cx=0
repz_cmps_z:
movw $0x40, %bx
push %bx
popf
movw $0x1234, %cx
movw $0x3000, %si
movw $0, %di
movw $0xf000, %ax
movw %ax, %ds
repz cmpsb
 
jmp *%cx
 
# repz scas ZF=1, but ZF=0 before %cx=0
repz_scas:
movw $0x40, %bx
push %bx
popf
movw $0x0040, %ax
repz scasw
jmp *%cx
 
# repz cmps scas ZF=0, they do only one iteration
repz_cmps_nz:
movw $0x0607, %ax
movw $0x5004, %cx
repz cmpsw
repz scasw
movw $0x40, %bx
push %bx
popf
movw $0x3000, %si
movw $0x0, %di
# repnz cmps scas ZF=1, they do only one iteration
repnz cmpsw
repnz scasw
jmp *%cx
hlt
 
.org 0x5000
# repnz movs ZF=1 all iterations
repnz_movs:
movw $0x2, %cx
repnz movsb
jcxz repnz_lods
hlt
 
# repnz lods ZF=1 all iterations
repnz_lods:
movw $0x2, %cx
repnz lodsb
jcxz repnz_stos
hlt
 
# repnz stos ZF=1 all iterations
repnz_stos:
movw $0x2, %cx
repnz stosb
jcxz repnz_cmps
hlt
 
# repnz cmps ZF=0, but ZF=1 before %cx=0
repnz_cmps:
movw $0, %bx
push %bx
popf
movw $0x6023, %cx
std
movw $0x6, %di
movw $0x3006, %si
repnz cmpsw
 
# repnz scas ZF=0, but ZF=1 before %cx=0
movw $0x1000, %ax
movw $0, %bx
push %bx
popf
cld
repnz scasw
jmp *%cx
hlt
 
.org 0x601b
movw $0x1234, %ax
hlt
 
.org 0xf003
jmp rep_lods_z
 
.org 65520
movw $0x1000, %sp
movw %sp, %ss
jmp start
 
.org 65535
.byte 0xff
/trunk/doc/schematic.odg
0,0 → 1,75
 
+ùvQ"Š# +ºZu·ÂExôÕ¿|þ,aêï„ã~a9ΊÒÏvÌiœ ö‘=´~*ËM:M kÃS³TŽ/Ô¶Á_•ˆj2›ÉÅÓ‡jF³¿³ê;üQ +}JÍ{k9Ç„\Æ°˜Qlm ê¾¼D8þ“,p~"ûIÛÿ»*Êx±•:‚¯T=؉¥q&°–¢ŒÈFky ãhIæÔÂO +@Ý÷ Ã’6Bž¢ÝÕ»‰™±{«´ +VWÇÒÎ5=‰¿¥·œä­ÊªÈ¯LzØsSKÛMæ^¡è÷-IT´Ѽ$q¬§_aTû'?-øsœÀ$ƒ³%½V +墖xË~áú߈@ÑfÚL¶VÿmœcŒ0wÀÐ2Ëw7çybg¹Í  ƒÒÏ¢ö2¤…‘³»Ì3:ðs=´a¶ûÔfÌ~a±»ç¯&ÎP²PvÈ{ú¼g*¦çu=èñ„:À»Ñm¾ Ìš±Ã³Z^sg% Síô>˜é¤÷Á¢ß´»ú  +LõÁÑšo=*:íüŸž¿ì|¯òôÔd-0‘=D•q”*½—*Mq=ª4Ås]ž*Ò`˜]@cA¿õmNX§KO›®m;5ugÝõ-ŠÅÛi×Ó{„¥Û1–&qvÐPóœèß‚Øâ tk7z§[§“¢?}Å‹ÄŠ®UyÖQ#Œ#o ¶¿ÄþP¿ `MdØ' ÛSB¶Ï…쎈«/J®Y¤ðxoƒá“Q|ƒxEv;¡‰aßHDôL¼[EívPjWDmÜj‡‡ltâãF1g Ó¬÷ú«É)¢ooñqðÑí•ó¦í•¦µIíØöÊvW£·Vá$›Hwš­¢#Ú¢X@¿Î¦ø"öØŠ6ÞžQ[ßóË÷Ó§6x/ÎÐÎ Øÿç×)ÊòoZZOžJõN&ÕÅÄd +[qn´E_9 +°î/ê|UNÌ´K¹ªþ!£q¿H¦Mì·ÆªðKdõÈRõôPKàPÔ^fåJPK7 +styles.xmlí\_oÛ6ߧ04to²þØic/N±ÛÓ +hHÒÕÂúëóïöµõñö‡E$ÀóE‚Snç|ã|Æi>WÂ…U°tNQNòyŠœÏy0§NµÑÜԞ˩Ԉ|X_s©lZsüÈû ݆-ZöŸY*›Ö!C›¾ÆB05Í#Ú×ø1íˆÚM2ÄÉŽ1IïÖšólî8›Íf¼™Œ)[9Þl6s¤´r8¨ô²‚ÅR+ c1YîxcÏѺ 樯B×t)-’%f½¡Aí­jÆp*®ÈË~2mùõ°ê]«˜ƒ5b½óL*7SeöO•IhÚ&ˆ¯;Ö÷ÚùBùϧ?ê¼bIß¹„nª€‘¬w˜JÛ´§”V® +µÙ¥»¾ëNõÙÐÞTß0Â13ÔƒƒêŠƒ +qš´zž6~)_ŸwÔ Û‘$(%½¡ºFª–e±QŠouÝUåööFTÈvÙHþ_L°°~aŒn¬$ïüàͯôqa¹#w代‰«Æ!ûÆlOŒ­}÷«åÜÞ¨mâqYÔGj,Båva­ÊÖ$°´n†’cvÆ (Æ J$Š« +Nó ‰ã€„˜*Ugkd•jY‘¼‘Û/¬œ$YŒµ +=¤ИBÉ㬀H"ª<Ò(þ„2šÿü+áFÉèoÌÐ襹4¢P6ö +§‚_XŒ&(mhd„P#âHª§ËÉWÆŸf\ŽÅ(]hC8—-RÎÀŸßîÚ¦„”EésœÕOÈ·9ÇɾÏZ^{nh終 +¡Ì‡2 +½öÉ{mµ—ö»íÝqýmŽŽKV• ¥Ñ:î&UÉQ?¢]cŠkFçoñŸ¿DsêwÁé{ý1:®CÕ…38HÍ lúÆlÙðxè^¨¿¿Xè¦-wÿ‡M<Ñ£¼`¯±_M¶êØ«W5óQ_­jµk\¹ª­ŒÔ + EJxy$ô]¿m£;;_f.?Šo ‹/B¶h0WN»--xc)þüäZ-:ò«ã,ØVçŒ×zÊèQ9_ œßÔvý™ºWúÇ€B©•AFgˆ˜øQtg`˜íÂòwJؾ‚ÄÜK²% +îWŒ°üj¥–”…âä{ò +•Ó¹Z¥ A9—¹­¿©1‰!ñ^P6¿¸®‚³µËkûè¨Kqy·j)Êh|@£Üç¢xJ-g7J¬À¸™› ‡$ð¢†BZ—…:KëÖÛ¾®b‰êDößÁrû?PKBƒ¼ÃEPK7meta.xml”Ánœ0†ï} +„rcv“°©R[õPåÐä’KåسÔ)¶‘mºÛ>}±Yl«Š#ãoþùgƸ|8Ë6ú Æ +­ª§Ybš ÕTñóÓǤˆêw¥>Â5ë%(—Hp4R•%ãQ÷FM­°DQ –8FtjJ!Kš„BcäÜ +õ£Š¿;ׄN§SzÚ¥Ú4N'”³™ëzÓŠ3-ø +(0ÔiS?š‹®ÒüæY‰s´ŽëŒ~æÐ]‘I\ܼïEË“¾Ã%º %œ C‡Bôz}Ò~G_¨‘º…7}I½FGð5ôpê †}ŸdE‚‹§,'8#øþ’½æJÎÈÿK.ÿ¥¾#Ù ¾à,ÙRÕô´lòák8›C£]àCªIØ/Ö‚­ó‹»«ðÈöLÂá(ð(Dü†«ø³:êÇh –oÃvÛ°ýŒÍo„õ?ƒu‚°~õë.l¯\ßÞú´ºWè_¯LýPKxCYÑÈ£PK7Thumbnails/thumbnail.pngå–éS“‡Æ#^Š¨ ²EÅD–T! ŠÄ†EAÙ‚ …°$´–Ê¢(*[0’í+k©"[Xle#Þ€%4bØ—˜„4` Ôé‡ûÜowæ7óœ™ç3'ë;Vc3b3 Ó8éæê¹®u0Øئ¯Ö+™‰Û¬rÒõ¸wcNàqæŸ2Ä‘÷·/†!YúËŒÑäêGG¦›˜@q”Èb¯çt™ß¸ 9ïÌ×áZ>E臘9q©ìl•‘‡JfC¹Îì›v½á ®û¼ÞÆ%Y‹óÄçIèÔoµxù¨¼£ëcBs4Ì4|x',,4Îø_ÐU vuvúØ|+¡Ù ùjm¬¬ +iÓK·¾ñœSþh¹Ýv|‡Q4Oí!¼ôk®WݤÌà~ DwèÐøíËQ‘ýØ.^ÛÆzvæÈWÈl@XN|wOß…±M¶9E’ m1¹ÑÄD­E©dáPQ©ÌD¶Ð¶pl¥ã©Ù mŒúÛÅ„mf^Ö#ý#Ñ’Œ5ËÆ7[3c‘¿Ü/Œd,¿)yÅ\¢kª‹§¸ÏOÎ +Ö4]S¹¬(wd(‚§×HÖ0¨¿> áÎH”9sÕ–,MbÃg3òVÔænê9S,|ì‰ö"ùøG騌ïÿfOëZ—à‚s%’Þê.¥~~0¤òè`‡ãVrÇ'=Á*W(¶™®$÷qÔžOI/ÓxîXå*úèÔÔïÛdjEwéiÔÚúÉd­w?¡ýûX8ßFvxµô +ÀÒüc6_ÿR'qô ðv4CnèlÐÃøm2Nî¸=þ÷>ëhl=|·ã!ù¼ ×é=±3©§¥  £mic˜¹$]o–(8´@{)êÉ3«¶Su1šN¯WóyâØH Ê?æ‹æͧ5 +û˜¨ÄóÇ=®9Q/i‰óO ½hnì²±WU1SQoJ^x>Þ‘õÝwŠk±¬ª[dzŽ¿w*óª:ëQ•ÀþÐÂfÏ&‘¸[l¦{wï…/—(ŠÚ×XòÚeƒ?v# •ávZܦÃ[>š6€)Ó ¦ðmÔRo+ü«²ÙÙÊ«ËÒ©Å"·ËøO“²Æ-1s§†"r®ûùùõ„ñýˆÆÈùì\GGǸ~‡¥]LXæùÓ÷€0ó¼·ÎñÅc£YV?°rF\¶£uYMÁVˆ:í@ƒÓ*y¬Z<;ì\·ÞÔ$L¶x®1Ã1VË_єͺ +> ?=3§í*¬_ñ‘ôuFIãñܧ‹ý/Þ`’²’Ãc{+Ò4[–S¦¸8iã|}Æ õ4ûåš\mPd˜ÓèÌ”$izNLH<æ’Wƒ +ètl´žßÝɹ¥àA‰"ë”.Òp¼5fPY%"ï®ñD§ÇúôkB—C‡ÇdâÔ1ã-W MY[Ñ9NŸ•’Ÿêµv(9¡ÍÉ_Nú¬æ;ԧż’Ëâ–)wÐ{¿nŠþ'P¬´ÀzÊùÄ£ö~L£O„iFýlCt7Tn +÷2:€*į°EU|_€Z $iDÄ +ÞjÌjR”:í,e7…wrÈSíOÑÔ5°¨Í¬èÙa¾éÈìÜùÐ$5ÕÖ¦u|nZb_ +´—ØSÐjì.,vž=Ò€ líí jáu3oüAaRm4ç;ãZ3-„=zù]ùǯ\ös'/®ñháѺ‚=8»¦Z`Y7§‰ßL^=ÌÚfH.¹jدÃHýÑ×úí6³ £ˆIpNVV †ÎZ.FâZÒ +s ~†—Ÿ“ö¡;¯X÷͇9åú«¬Ø`ßB´@9*Ü_ÔÁ“˜>Íï3AUr¯|Ru‘˜Šôð„ýÈȱÑix+;柹#ç.ƒ#p©iz¡29;îçq7}ÎúàÎe5ö£ê³µâ×,¸8î¸f9Ë–Vã@ ºĹ¡ì=rµŒq¶Éï'ÕÂBs¿Ž®a3Ÿ_Ùêð]Ï€}…â7k'¼îÍo@ךI VùÑI¢eÙLajšU¶ßTÄó]¸O…Ï“'Oß¿m¸"þɺ¡»RúäÝx¯¾ÿ*‡¿ZÜ}ùŸ.Ãï?ªàþ4ôL ”b¦ö¼*îûc=.h¥8ðä ³`xhhÄÝÝ‹Ú˜KݤG; /U·.×Hòj<Ä*xµïû˜™™qzó­="Ê^“ò&Ó×ü|}é% /2±ÿ'v—áb—Zõ™š¾å =‚ÓJ;¤loGÚÙñ9Èl\5!n­ˆt­_Bh¦jLjåîo7ÆϜݱܜ¸0’’’ÒÙa»Ï5Ç[HÏc’êΛÉIuEW%¢îúÞ=IJ‹XQX÷ÉÁÁA‘lfW}ؘ¸Õò¾ç ¯œñ‰P‰DB(¡ácΧÿû4ôµgݹüu<œá¦¾óß=ùÿåõŒè—d🶖Òõ§vs­>|íoPKó ü= ; +PK7'Configurations2/accelerator/current.xmlPKPK7Configurations2/progressbar/PK7Configurations2/floater/PK7Configurations2/popupmenu/PK7Configurations2/menubar/PK7Configurations2/toolbar/PK7Configurations2/images/Bitmaps/PK7Configurations2/statusbar/PK7 settings.xmlåZ[S"9~ß_aQû°[[H£ã¬PÊVƒ€Ì ƒÜ} #dÌ¥+I‹Ì¯ß¤¡Q&moMÕò€Ø|ß¹õ9'Îþybôà¤"‚ŸçŠ‡^îx 0á“óÜpÐÈŸæþ©üv&îïIe,‚ˆ×yZ›%êÀl窼¸}ž‹$/ ¤ˆ*sÄ@•uP!ðÕ¶òúêrL¶¸òD 8ÏMµË…Âl6;œ +9)K¥R!¾»ZJP +ø±ÏUîU¿!ß´ñ{ ·TŸ£p ,K†ð]4+$'„«],ZF)Iì{›pØIñŠ|ƒ@7¤¹˜9KW˜§(eº4R—ˆc +ʧ34Ï0~mìšMúæY£»ÝãuJáHCWÐyl¶¶¹ }K—”˜Š'žcÞk©m®,\´ôGÍMíÛÄG +>~¨!ä2'\\=캽œf$/P ÷Ÿ\-.D2.Ý?3Âò÷ +äÒèý[‹*ÑFÑ…a¯½c¸òû‘àÏ%AA-«ø¡c7VÓÉHdºIYÌŽJípp`(ßµ±ŒÛwgÍ7Ò ¤¦ÎœØ‘îQDµ¡íë䆢xt²·wñBŽ ÆÀŸÝ—~¨×6-m”p¤XÚ +”«ï#Ë¿µÞwlO$hkŠ·DÝã¸Z… ávÀåŒPçøÕýióÜÛE +abÀœC|âfùK¤÷çjêZ-?ƒä¾2>ïF<ÐQVç®–Š'4U!(d3$^'¨¢à!‹Cê:Ç«ãîÔ$¦f3éŒÑD;¶{\ÆYÔrd2L9,z'«!wÌ0 ²µÓ€d"¿Í &‘:§WZpœn¦÷Ðê +Š$ ùÖjÙF»O͉g ÒÔ†ˆŽÓ„®i#&…Ó~ÄXVÉ5Ž¤ëQ¢7Ížf>Âl™Êi¿75±æÛƒ¢U4Q1Ë›FWÐȪ™Š2á©^±4ƒ$ÁÁre*š>èh³™|ùUÁÈ¿ü«àa:f£9º¹š /?…cÞ£ÁÄÿ%_C7´Ú½½ôÆ÷¯|öCªïOûæo›·>+‘^³áÝöý§¯ÝO¼»¯­RïhÝ}ýÞΫ×£nŽæ5V2÷GæsÃC7¥¨;ª>¼7¿½¡^uƒ&¥Áwï©ÆŠÓ€ápÌzSÄGßq³HÇüºtU›ÍÚ¾ºòÃo㣧ǀû^öDwÐò ÷÷qsttw3+­ßÇŒ~»x³­^÷êGë¨÷¦¸YÿXSì1’ö®ÏÕ“(Ð)ßj×7âsóQ¾Šõj±´àt‡Äõ9(†}Ž.ËF¤èj¤©v`‘jVµèZ¯’EÇõÏüz4­ÅÜiƒåÅU†­†’!­€‡:åÞµÕÉUÝ*ª>BØiEâJè’1eÞ5B +ùñÀr¨ú>MyÇ£sL˜“K|4H³c-2L€Þ‡mvÉnhC’Ïa\?7|Þ»wîS<½z‘ –>J•bœv‰»²Bô}D¢-dtÆc®ê}HaèÜ”?’³ {o²Áµ…I¾i¶2õÁ·# ›8My”¿‡<%76g•t¥nÿ+cÞÁŒÌçxÍKùçO\}PK2ÿ¯BNPK7Ÿ.Ä++mimetypePK7àPÔ^fåJ Qcontent.xmlPK7Bƒ¼ÃE +ðstyles.xmlPK7xCYÑÈ£ämeta.xmlPK7ó ü= ; +âThumbnails/thumbnail.pngPK7'=Configurations2/accelerator/current.xmlPK7”Configurations2/progressbar/PK7ÎConfigurations2/floater/PK7Configurations2/popupmenu/PK7<Configurations2/menubar/PK7rConfigurations2/toolbar/PK7¨Configurations2/images/Bitmaps/PK7åConfigurations2/statusbar/PK7äÅN×Ø% settings.xmlPK72ÿ¯BN/$META-INF/manifest.xmlPKî´% \ No newline at end of file
/trunk/doc/schema.svg
0,0 → 1,407
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://web.resource.org/cc/"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="210mm"
height="297mm"
id="svg2"
sodipodi:version="0.32"
inkscape:version="0.45.1"
sodipodi:docbase="/home/zeus/zet/doc"
sodipodi:docname="schema.svg"
inkscape:output_extension="org.inkscape.output.svg.inkscape">
<defs
id="defs4">
<marker
inkscape:stockid="TriangleInL"
orient="auto"
refY="0.0"
refX="0.0"
id="TriangleInL"
style="overflow:visible">
<path
id="path3269"
d="M 5.77,0.0 L -2.88,5.0 L -2.88,-5.0 L 5.77,0.0 z "
style="fill-rule:evenodd;stroke:#000000;stroke-width:1.0pt;marker-start:none"
transform="scale(-0.8)" />
</marker>
<marker
inkscape:stockid="TriangleOutL"
orient="auto"
refY="0.0"
refX="0.0"
id="TriangleOutL"
style="overflow:visible">
<path
id="path3278"
d="M 5.77,0.0 L -2.88,5.0 L -2.88,-5.0 L 5.77,0.0 z "
style="fill-rule:evenodd;stroke:#000000;stroke-width:1.0pt;marker-start:none"
transform="scale(0.8)" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="0.98994949"
inkscape:cx="367.26348"
inkscape:cy="583.32881"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showguides="true"
inkscape:guide-bbox="true"
inkscape:window-width="1202"
inkscape:window-height="1274"
inkscape:window-x="91"
inkscape:window-y="219">
<sodipodi:guide
orientation="vertical"
position="584.87833"
id="guide3227" />
</sodipodi:namedview>
<metadata
id="metadata7">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Capa 1"
inkscape:groupmode="layer"
id="layer1">
<g
id="g2178"
transform="translate(-62.629458,76.771593)">
<rect
ry="2.1464674"
rx="2.2749679"
y="353.18732"
x="447.3483"
height="154.85193"
width="227.58292"
id="rect2160"
style="fill:#5599ff;fill-opacity:0.35443037;stroke:#311b7d;stroke-width:0.70141107;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
<text
id="text2166"
y="442.86279"
x="515.59247"
style="font-size:38.65259171px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
xml:space="preserve"><tspan
y="442.86279"
x="515.59247"
id="tspan2168"
sodipodi:role="line">Exec</tspan></text>
</g>
<g
id="g2183"
transform="translate(-53.538085,117.1777)">
<rect
ry="3.1504831"
rx="3.1504831"
y="309.90005"
x="84.852814"
height="188.89853"
width="189.90868"
id="rect2162"
style="fill:#80ff80;fill-opacity:0.35443037;stroke:#311b7d;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
<text
id="text2170"
y="413.60669"
x="135.03027"
style="font-size:35.94897461px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
xml:space="preserve"><tspan
y="413.60669"
x="135.03027"
id="tspan2172"
sodipodi:role="line">Fetch</tspan></text>
</g>
<g
id="g2188"
transform="translate(58.588856,8.0812224)">
<rect
ry="3.1504831"
rx="3.1504831"
y="51.30101"
x="209.10158"
height="132.32999"
width="244.45691"
id="rect2164"
style="fill:#ffb380;fill-opacity:0.35443037;stroke:#311b7d;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
<text
id="text2174"
y="127.47702"
x="274.06076"
style="font-size:29.43220329px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
xml:space="preserve"><tspan
y="127.47702"
x="274.06076"
id="tspan2176"
sodipodi:role="line">Memory</tspan></text>
</g>
<path
style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
d="M 220.21325,468.49401 L 381.83766,468.49401"
id="path5323" />
<text
xml:space="preserve"
style="font-size:12px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="269.71072"
y="460.41278"
id="text5345"><tspan
sodipodi:role="line"
id="tspan5347"
x="269.71072"
y="460.41278">IR</tspan></text>
<path
id="path5349"
d="M 221.2234,495.76813 L 382.84781,495.76813"
style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
<path
style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
d="M 220.21325,522.0321 L 381.83766,522.0321"
id="path5351" />
<g
id="g5361"
transform="translate(-82.832509,44.446712)">
<rect
ry="3.1504831"
rx="3.1504831"
y="205.85434"
x="341.43155"
height="61.619305"
width="104.04572"
id="rect5353"
style="fill:#000080;fill-opacity:0.35443037;stroke:#311b7d;stroke-width:2;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" />
<path
id="path5357"
d="M 341.43156,265.45335 L 393.95949,205.85435"
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate" />
<path
id="path5359"
d="M 444.46712,267.47366 L 396.98995,204.8442"
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate" />
</g>
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate"
d="M 138.39089,428.08791 L 138.39089,372.52952 L 288.90362,372.52952 L 288.90362,310.91021"
id="path5370" />
<path
id="path5376"
d="M 494.88218,429.09806 L 494.88218,373.53967 L 327.38197,373.53967 L 327.38197,311.92036"
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2.10984731;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate" />
<text
xml:space="preserve"
style="font-size:12px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="171.72594"
y="358.38739"
id="text6347"><tspan
sodipodi:role="line"
id="tspan6349"
x="171.72594"
y="358.38739">addr</tspan></text>
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate"
d="M 56.568544,426.0676 L 56.568544,283.6361 L 258.59905,283.6361"
id="path6351" />
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate"
d="M 313.14729,250.30106 L 313.14729,195.75282"
id="path6353" />
<text
xml:space="preserve"
style="font-size:12px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="269.71072"
y="490.71738"
id="text6355"><tspan
sodipodi:role="line"
id="tspan6357"
x="269.71072"
y="490.71738">imm</tspan></text>
<text
xml:space="preserve"
style="font-size:12px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="269.04861"
y="516.98132"
id="text6359"><tspan
sodipodi:role="line"
id="tspan6361"
x="269.04861"
y="516.98132">off</tspan></text>
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate;marker-end:url(#TriangleOutL)"
d="M 511.13719,76.554821 L 573.76665,76.554821"
id="path2202" />
<path
id="path3177"
d="M 511.13719,99.78833 L 573.76665,99.78833"
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate;font-size:14" />
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="517.19812"
y="69.483749"
id="text3179"><tspan
sodipodi:role="line"
id="tspan3181"
x="517.19812"
y="69.483749">addr_</tspan></text>
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="518.20825"
y="93.727417"
id="text3183"><tspan
sodipodi:role="line"
id="tspan3185"
x="518.20825"
y="93.727417">data_</tspan></text>
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate;marker-end:url(#TriangleOutL)"
d="M 512.14734,127.06245 L 576.79711,127.06245"
id="path3193" />
<path
id="path3201"
d="M 512.14734,140.19443 L 576.79711,140.19443"
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate" />
<path
id="path3203"
d="M 512.14734,153.32642 L 576.79711,153.32642"
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate" />
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate"
d="M 512.14734,166.4584 L 576.79711,166.4584"
id="path3205" />
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="585.88849"
y="128.0726"
id="text3207"><tspan
sodipodi:role="line"
id="tspan3209"
x="585.88849"
y="128.0726">roe_</tspan></text>
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="584.87836"
y="143.22488"
id="text3211"><tspan
sodipodi:role="line"
id="tspan3213"
x="584.87836"
y="143.22488">rwe_</tspan></text>
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="584.8783"
y="157.36702"
id="text3215"><tspan
sodipodi:role="line"
id="tspan3217"
x="584.8783"
y="157.36702">rcs_</tspan></text>
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="584.87836"
y="171.50916"
id="text3219"><tspan
sodipodi:role="line"
id="tspan3221"
x="584.87836"
y="171.50916">rble_</tspan></text>
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="584.87836"
y="184.64114"
id="text3223"><tspan
sodipodi:role="line"
id="tspan3225"
x="584.87836"
y="184.64114">rbhe_</tspan></text>
<path
id="path3229"
d="M 512.14734,179.59038 L 576.79711,179.59038"
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;marker-end:url(#TriangleOutL);stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate" />
<path
sodipodi:type="star"
style="fill:#000080;fill-opacity:0.35443037;stroke:#311b7d;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
id="path3233"
sodipodi:sides="5"
sodipodi:cx="25.253815"
sodipodi:cy="125.04214"
sodipodi:r1="51.715469"
sodipodi:r2="25.857735"
sodipodi:arg1="1.354246"
sodipodi:arg2="1.9825646"
inkscape:flatsided="false"
inkscape:rounded="0"
inkscape:randomized="0"
d="M 36.365494,175.54976 L 14.904763,148.73854 L -19.348095,151.21769 L -0.48083773,122.5222 L -13.423361,90.71189 L 19.697977,99.788323 L 45.951916,77.649328 L 47.554771,111.95436 L 76.72312,130.08202 L 44.592401,142.20726 L 36.365494,175.54976 z "
transform="translate(102.02541,3.0304577)" />
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate;marker-end:url(#TriangleOutL)"
d="M 148.49242,80.595431 C 194.95944,9.8847528 266.68027,79.585279 266.68027,79.585279"
id="path3237" />
<path
style="opacity:1;color:#000000;fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;marker:none;marker-start:none;marker-mid:none;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;visibility:visible;display:inline;overflow:visible;enable-background:accumulate;marker-end:url(#TriangleOutL)"
d="M 178.797,133.12336 L 266.68027,133.12336"
id="path3239" />
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="191.92899"
y="41.199482"
id="text3241"><tspan
sodipodi:role="line"
id="tspan3243"
x="191.92899"
y="41.199482">clk2x</tspan></text>
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="199.00005"
y="127.06245"
id="text3245"><tspan
sodipodi:role="line"
id="tspan3247"
x="199.00005"
y="127.06245">clk</tspan></text>
<text
xml:space="preserve"
style="font-size:16px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="114.14724"
y="135.14368"
id="text3249"><tspan
sodipodi:role="line"
id="tspan3251"
x="114.14724"
y="135.14368">PLL</tspan></text>
<text
xml:space="preserve"
style="font-size:14px;font-style:normal;font-weight:normal;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Bitstream Vera Sans"
x="293.95438"
y="176.55992"
id="text3253"><tspan
sodipodi:role="line"
id="tspan3255"
x="293.95438"
y="176.55992">addr</tspan></text>
</g>
</svg>
/trunk/src/splitlh.c
0,0 → 1,47
#include <stdio.h>
#include <sys/stat.h>
#include <fcntl.h>
 
int main(int argc, char *argv[])
{
int fd, count, out0, out1;
char word[2];
 
if (argc != 4) fprintf(stderr, "Syntax: %s infile evenfile oddfile\n",
argv[0]);
fd=open(argv[1], O_RDONLY);
if(fd < 0)
{
fprintf(stderr, "Error opening file\n");
return 1;
}
 
out0 = open (argv[2], O_WRONLY|O_CREAT|O_TRUNC,
S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
if(out0 < 0)
{
fprintf(stderr, "Error creating even file\n");
return 2;
}
 
out1 = open (argv[3], O_WRONLY|O_CREAT|O_TRUNC,
S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
if(out1 < 0)
{
fprintf(stderr, "Error creating odd file\n");
return 3;
}
 
do {
count = read(fd, word, 2);
if (count > 0) write(out0, &word[0], 1);
if (count > 1) write(out1, &word[1], 1);
} while (count > 0);
 
close (fd);
close (out0);
close (out1);
return 0;
}
/trunk/src/Makefile
0,0 → 1,2
../bin/splitlh: splitlh.c
gcc -o ../bin/splitlh splitlh.c
/trunk/bin/tmproot.sh
0,0 → 1,6
#!/bin/bash
mkdir -p {doc,bin}
cd doc
wget -nc http://www.opencores.com/cvsweb.cgi/~checkout~/uart16550/doc/UART_spec.pdf
cd ..
gcc ../src/splitlh.c -o ./bin/splitlh
trunk/bin/tmproot.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bin/vdt2rom =================================================================== --- trunk/bin/vdt2rom (nonexistent) +++ trunk/bin/vdt2rom (revision 2) @@ -0,0 +1,10 @@ +#!/bin/bash +# +# USAGE: vdt2rom [-hex] file.vdt +# +if [ $# -eq 1 ] +then + sed -e 's/\/\/\(.\)*//' -e 's/_//g' -e 's/[xsdm]/0/g' -e '/^\([\ \t]\)*$/d' -e 's/\ //g' $1 +else + sed -e 's/\/\/\(.\)*//' -e 's/_//g' -e '/^\([\ \t]\)*$/d' -e 's/\ //g' $2 +fi
trunk/bin/vdt2rom Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bin/web2rom =================================================================== --- trunk/bin/web2rom (nonexistent) +++ trunk/bin/web2rom (revision 2) @@ -0,0 +1,110 @@ +#!/usr/bin/php +") break; + $arr3 = split("[ ]+", $arr2[$j]); + $instr[$arr3[0]]['micro'][]['code'] = $arr3[1]; + + if(isset($instr[$arr3[0]]['seq'])) $seq++; + else $instr[$arr3[0]]['seq'] = $seq++; + } + } + + // 2. Replace x/d/m/s by zeros and remove _ from instr + $micros = Array(); + + foreach ($instr as $key => $value) + { + for($i=0; $i $value) + for($i=0; $i $value) + fprintf ($fi, "`define $key\t$seq_addr_width'b%0${seq_addr_width}b\n", + $value['seq']); + fclose($fi); +?>
trunk/bin/web2rom Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/testbench.v =================================================================== --- trunk/sim/testbench.v (nonexistent) +++ trunk/sim/testbench.v (revision 2) @@ -0,0 +1,40 @@ +`timescale 10ns/100ps + +module testbench; + + // Net declarations + wire [15:0] rd_data; + wire [15:0] wr_data, mem_data, io_data; + wire [19:0] addr; + wire we; + wire m_io; + wire byte_m; + + reg clk, rst; + reg [15:0] io_reg; + + // Module instantiations + memory mem0 (clk, addr, wr_data, mem_data, we & ~m_io, byte_m); + cpu cpu0 (clk, rst, rd_data, wr_data, addr, we, m_io, byte_m,, 1'b1); + + // Assignments + assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0; + assign rd_data = m_io ? io_data : mem_data; + + // Behaviour + // IO Stub + always @(posedge clk) + if (addr==20'hb7 & ~we & m_io) + io_reg <= byte_m ? { io_reg[15:8], wr_data[7:0] } : wr_data; + + always #1 clk = ~clk; + + initial + begin + clk <= 1'b1; + rst <= 1'b0; + #5 rst <= 1'b1; + #2 rst <= 1'b0; + end + +endmodule Index: trunk/sim/modelsim/tb.do =================================================================== --- trunk/sim/modelsim/tb.do (nonexistent) +++ trunk/sim/modelsim/tb.do (revision 2) @@ -0,0 +1,29 @@ +vdel -all -lib work +vlib work +vlog -work work +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v +vlog -work work +incdir+.. ../memory.v ../testbench.v +vsim -novopt -t ns work.testbench +add wave /testbench/clk +add wave /testbench/rst +add wave -radix hexadecimal /testbench/cpu0/fetch0/pc +add wave -radix hexadecimal /testbench/cpu0/fetch0/state +add wave -radix hexadecimal /testbench/cpu0/fetch0/next_state +add wave -radix hexadecimal /testbench/cpu0/fetch0/opcode +add wave -radix hexadecimal /testbench/cpu0/fetch0/modrm +add wave /testbench/cpu0/fetch0/end_seq +add wave -radix hexadecimal sim:/testbench/rd_data +add wave -radix hexadecimal sim:/testbench/wr_data +add wave sim:/testbench/cpu0/fetch0/need_modrm +add wave sim:/testbench/cpu0/fetch0/need_off +add wave sim:/testbench/cpu0/fetch0/need_imm +add wave sim:/testbench/cpu0/fetch0/ir +add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/imm +add wave -radix hexadecimal sim:/testbench/cpu0/fetch0/off +add wave -radix hexadecimal sim:/testbench/addr +add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/r\[15\] +add wave -radix hexadecimal sim:/testbench/cpu0/exec0/reg0/d +add wave sim:/testbench/cpu0/exec0/reg0/addr_a +add wave sim:/testbench/cpu0/exec0/reg0/addr_d +add wave sim:/testbench/cpu0/exec0/reg0/wr +add wave sim:/testbench/we +add wave sim:/testbench/cpu0/fetch_or_exec \ No newline at end of file Index: trunk/sim/memory.v =================================================================== --- trunk/sim/memory.v (nonexistent) +++ trunk/sim/memory.v (revision 2) @@ -0,0 +1,28 @@ +`timescale 1ns/10ps + +module memory ( + input clk, + input [19:0] addr, + input [15:0] wr_data, + output [15:0] rd_data, + input we, + input byte_m + ); + + // Registers and nets + wire [19:0] addr1; + + reg [7:0] ram[2**20-1:0]; + + // Assignments + assign rd_data = byte_m ? { {8{ram[addr][7]}}, ram[addr]} + : {ram[addr1], ram[addr]}; + assign addr1 = addr + 20'd1; + + // Behaviour + always @(posedge clk) + if (~we) if (byte_m) ram[addr] <= wr_data[7:0]; + else { ram[addr1], ram[addr] } <= wr_data; + + initial $readmemh("/home/zeus/zet/sim/09_vdu.rtlrom", ram, 20'hf0000); +endmodule Index: trunk/uart16550/verilog/uart_regs.v =================================================================== --- trunk/uart16550/verilog/uart_regs.v (nonexistent) +++ trunk/uart16550/verilog/uart_regs.v (revision 2) @@ -0,0 +1,897 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_regs.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Registers of the uart 16550 core //// +//// //// +//// Known problems (limits): //// +//// Inserts 1 wait state in all WISHBONE transfers //// +//// //// +//// To Do: //// +//// Nothing or verification. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: (See log for the revision history //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.42 2004/11/22 09:21:59 igorm +// Timeout interrupt should be generated only when there is at least ony +// character in the fifo. +// +// Revision 1.41 2004/05/21 11:44:41 tadejm +// Added synchronizer flops for RX input. +// +// Revision 1.40 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.39 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.38 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.37 2001/12/27 13:24:09 mohor +// lsr[7] was not showing overrun errors. +// +// Revision 1.36 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.35 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.34 2001/12/19 07:33:54 mohor +// Synplicity was having troubles with the comment. +// +// Revision 1.33 2001/12/17 10:14:43 mohor +// Things related to msr register changed. After THRE IRQ occurs, and one +// character is written to the transmit fifo, the detection of the THRE bit in the +// LSR is delayed for one character time. +// +// Revision 1.32 2001/12/14 13:19:24 mohor +// MSR register fixed. +// +// Revision 1.31 2001/12/14 10:06:58 mohor +// After reset modem status register MSR should be reset. +// +// Revision 1.30 2001/12/13 10:09:13 mohor +// thre irq should be cleared only when being source of interrupt. +// +// Revision 1.29 2001/12/12 09:05:46 mohor +// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). +// +// Revision 1.28 2001/12/10 19:52:41 gorban +// Scratch register added +// +// Revision 1.27 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.26 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.25 2001/11/28 19:36:39 gorban +// Fixed: timeout and break didn't pay attention to current data format when counting time +// +// Revision 1.24 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.23 2001/11/12 21:57:29 gorban +// fixed more typo bugs +// +// Revision 1.22 2001/11/12 15:02:28 mohor +// lsr1r error fixed. +// +// Revision 1.21 2001/11/12 14:57:27 mohor +// ti_int_pnd error fixed. +// +// Revision 1.20 2001/11/12 14:50:27 mohor +// ti_int_d error fixed. +// +// Revision 1.19 2001/11/10 12:43:21 gorban +// Logic Synthesis bugs fixed. Some other minor changes +// +// Revision 1.18 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.17 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.16 2001/11/02 09:55:16 mohor +// no message +// +// Revision 1.15 2001/10/31 15:19:22 gorban +// Fixes to break and timeout conditions +// +// Revision 1.14 2001/10/29 17:00:46 gorban +// fixed parity sending and tx_fifo resets over- and underrun +// +// Revision 1.13 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.12 2001/10/19 16:21:40 gorban +// Changes data_out to be synchronous again as it should have been. +// +// Revision 1.11 2001/10/18 20:35:45 gorban +// small fix +// +// Revision 1.10 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.9 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.10 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.9 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.8 2001/05/29 20:05:04 gorban +// Fixed some bugs and synthesis problems. +// +// Revision 1.7 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.6 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.5 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +`define UART_DL1 7:0 +`define UART_DL2 15:8 + +module uart_regs (clk, + wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i, + +// additional signals + modem_inputs, + stx_pad_o, srx_pad_i, + +`ifdef DATA_BUS_WIDTH_8 +`else +// debug interface signals enabled +ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate, +`endif + rts_pad_o, dtr_pad_o, int_o +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + + ); + +input clk; +input wb_rst_i; +input [`UART_ADDR_WIDTH-1:0] wb_addr_i; +input [7:0] wb_dat_i; +output [7:0] wb_dat_o; +input wb_we_i; +input wb_re_i; + +output stx_pad_o; +input srx_pad_i; + +input [3:0] modem_inputs; +output rts_pad_o; +output dtr_pad_o; +output int_o; +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + +`ifdef DATA_BUS_WIDTH_8 +`else +// if 32-bit databus and debug interface are enabled +output [3:0] ier; +output [3:0] iir; +output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +output [4:0] mcr; +output [7:0] lcr; +output [7:0] msr; +output [7:0] lsr; +output [`UART_FIFO_COUNTER_W-1:0] rf_count; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; +output [2:0] tstate; +output [3:0] rstate; + +`endif + +wire [3:0] modem_inputs; +reg enable; +`ifdef UART_HAS_BAUDRATE_OUTPUT +assign baud_o = enable; // baud_o is actually the enable signal +`endif + + +wire stx_pad_o; // received from transmitter module +wire srx_pad_i; +wire srx_pad; + +reg [7:0] wb_dat_o; + +wire [`UART_ADDR_WIDTH-1:0] wb_addr_i; +wire [7:0] wb_dat_i; + + +reg [3:0] ier; +reg [3:0] iir; +reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +reg [4:0] mcr; +reg [7:0] lcr; +reg [7:0] msr; +reg [15:0] dl; // 32-bit divisor latch +reg [7:0] scratch; // UART scratch register +reg start_dlc; // activate dlc on writing to UART_DL1 +reg lsr_mask_d; // delay for lsr_mask condition +reg msi_reset; // reset MSR 4 lower bits indicator +//reg threi_clear; // THRE interrupt clear flag +reg [15:0] dlc; // 32-bit divisor latch counter +reg int_o; + +reg [3:0] trigger_level; // trigger level of the receiver FIFO +reg rx_reset; +reg tx_reset; + +wire dlab; // divisor latch access bit +wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits +wire loopback; // loopback bit (MCR bit 4) +wire cts, dsr, ri, dcd; // effective signals +wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback) +wire rts_pad_o, dtr_pad_o; // modem control outputs + +// LSR bits wires and regs +wire [7:0] lsr; +wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; +reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; +wire lsr_mask; // lsr_mask + +// +// ASSINGS +// + +assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; + +assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; +assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} + : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign dlab = lcr[`UART_LC_DL]; +assign loopback = mcr[4]; + +// assign modem outputs +assign rts_pad_o = mcr[`UART_MC_RTS]; +assign dtr_pad_o = mcr[`UART_MC_DTR]; + +// Interrupt signals +wire rls_int; // receiver line status interrupt +wire rda_int; // receiver data available interrupt +wire ti_int; // timeout indicator interrupt +wire thre_int; // transmitter holding register empty interrupt +wire ms_int; // modem status interrupt + +// FIFO signals +reg tf_push; +reg rf_pop; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_error_bit; // an error (parity or framing) is inside the fifo +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; +wire [2:0] tstate; +wire [3:0] rstate; +wire [9:0] counter_t; + +wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo. +reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle) +reg [7:0] block_value; // One character length minus stop bit + +// Transmitter Instance +wire serial_out; + +uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask); + + // Synchronizing and sampling serial RX input + uart_sync_flops i_uart_sync_flops + ( + .rst_i (wb_rst_i), + .clk_i (clk), + .stage1_rst_i (1'b0), + .stage1_clk_en_i (1'b1), + .async_dat_i (srx_pad_i), + .sync_dat_o (srx_pad) + ); + defparam i_uart_sync_flops.width = 1; + defparam i_uart_sync_flops.init_value = 1'b1; + +// handle loopback +wire serial_in = loopback ? serial_out : srx_pad; +assign stx_pad_o = loopback ? 1'b1 : serial_out; + +// Receiver Instance +uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + + +// Asynchronous reading here because the outputs are sampled in uart_wb.v file +always @(dl or dlab or ier or iir or scratch + or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading +begin + case (wb_addr_i) + `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; + `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier; + `UART_REG_II : wb_dat_o = {4'b1100,iir}; + `UART_REG_LC : wb_dat_o = lcr; + `UART_REG_LS : wb_dat_o = lsr; + `UART_REG_MS : wb_dat_o = msr; + `UART_REG_SR : wb_dat_o = scratch; + default: wb_dat_o = 8'b0; // ?? + endcase // case(wb_addr_i) +end // always @ (dl or dlab or ier or iir or scratch... + + +// rf_pop signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + rf_pop <= #1 0; + else + if (rf_pop) // restore the signal to 0 after one clock cycle + rf_pop <= #1 0; + else + if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab) + rf_pop <= #1 1; // advance read pointer +end + +wire lsr_mask_condition; +wire iir_read; +wire msr_read; +wire fifo_read; +wire fifo_write; + +assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab); +assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab); +assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab); +assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab); +assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab); + +// lsr_mask_d delayed signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + lsr_mask_d <= #1 0; + else // reset bits in the Line Status Register + lsr_mask_d <= #1 lsr_mask_condition; +end + +// lsr_mask is rise detected +assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; + +// msi_reset signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + msi_reset <= #1 1; + else + if (msi_reset) + msi_reset <= #1 0; + else + if (msr_read) + msi_reset <= #1 1; // reset bits in Modem Status Register +end + + +// +// WRITES AND RESETS // +// +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + lcr <= #1 8'b00000011; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_LC) + lcr <= #1 wb_dat_i; + +// Interrupt Enable Register or UART_DL2 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin + ier <= #1 4'b0000; // no interrupts after reset + dl[`UART_DL2] <= #1 8'b0; + end + else + if (wb_we_i && wb_addr_i==`UART_REG_IE) + if (dlab) + begin + dl[`UART_DL2] <= #1 wb_dat_i; + end + else + ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb + + +// FIFO Control Register and rx_reset, tx_reset signals +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + fcr <= #1 2'b11; + rx_reset <= #1 0; + tx_reset <= #1 0; + end else + if (wb_we_i && wb_addr_i==`UART_REG_FC) begin + fcr <= #1 wb_dat_i[7:6]; + rx_reset <= #1 wb_dat_i[1]; + tx_reset <= #1 wb_dat_i[2]; + end else begin + rx_reset <= #1 0; + tx_reset <= #1 0; + end + +// Modem Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + mcr <= #1 5'b0; + else + if (wb_we_i && wb_addr_i==`UART_REG_MC) + mcr <= #1 wb_dat_i[4:0]; + +// Scratch register +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + scratch <= #1 0; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_SR) + scratch <= #1 wb_dat_i; + +// TX_FIFO or UART_DL1 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin + dl[`UART_DL1] <= #1 8'b0; + tf_push <= #1 1'b0; + start_dlc <= #1 1'b0; + end + else + if (wb_we_i && wb_addr_i==`UART_REG_TR) + if (dlab) + begin + dl[`UART_DL1] <= #1 wb_dat_i; + start_dlc <= #1 1'b1; // enable DL counter + tf_push <= #1 1'b0; + end + else + begin + tf_push <= #1 1'b1; + start_dlc <= #1 1'b0; + end // else: !if(dlab) + else + begin + start_dlc <= #1 1'b0; + tf_push <= #1 1'b0; + end // else: !if(dlab) + +// Receiver FIFO trigger level selection logic (asynchronous mux) +always @(fcr) + case (fcr[`UART_FC_TL]) + 2'b00 : trigger_level = 1; + 2'b01 : trigger_level = 4; + 2'b10 : trigger_level = 8; + 2'b11 : trigger_level = 14; + endcase // case(fcr[`UART_FC_TL]) + +// +// STATUS REGISTERS // +// + +// Modem Status Register +reg [3:0] delayed_modem_signals; +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + msr <= #1 0; + delayed_modem_signals[3:0] <= #1 0; + end + else begin + msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 : + msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); + msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c}; + delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts}; + end +end + + +// Line Status Register + +// activation conditions +assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition +assign lsr1 = rf_overrun; // Receiver overrun error +assign lsr2 = rf_data_out[1]; // parity error bit +assign lsr3 = rf_data_out[0]; // framing error bit +assign lsr4 = rf_data_out[2]; // break error in the character +assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty +assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty +assign lsr7 = rf_error_bit | rf_overrun; + +// lsr bit0 (receiver data available) +reg lsr0_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0_d <= #1 0; + else lsr0_d <= #1 lsr0; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0r <= #1 0; + else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 1'b0 : // deassert condition + lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted + +// lsr bit 1 (receiver overrun) +reg lsr1_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1_d <= #1 0; + else lsr1_d <= #1 lsr1; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1r <= #1 0; + else lsr1r <= #1 lsr_mask ? 1'b0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise + +// lsr bit 2 (parity error) +reg lsr2_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2_d <= #1 0; + else lsr2_d <= #1 lsr2; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2r <= #1 0; + else lsr2r <= #1 lsr_mask ? 1'b0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise + +// lsr bit 3 (framing error) +reg lsr3_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3_d <= #1 0; + else lsr3_d <= #1 lsr3; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3r <= #1 0; + else lsr3r <= #1 lsr_mask ? 1'b0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise + +// lsr bit 4 (break indicator) +reg lsr4_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4_d <= #1 0; + else lsr4_d <= #1 lsr4; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4r <= #1 0; + else lsr4r <= #1 lsr_mask ? 1'b0 : lsr4r || (lsr4 && ~lsr4_d); + +// lsr bit 5 (transmitter fifo is empty) +reg lsr5_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5_d <= #1 1; + else lsr5_d <= #1 lsr5; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5r <= #1 1; + else lsr5r <= #1 (fifo_write) ? 1'b0 : lsr5r || (lsr5 && ~lsr5_d); + +// lsr bit 6 (transmitter empty indicator) +reg lsr6_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6_d <= #1 1; + else lsr6_d <= #1 lsr6; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6r <= #1 1; + else lsr6r <= #1 (fifo_write) ? 1'b0 : lsr6r || (lsr6 && ~lsr6_d); + +// lsr bit 7 (error in fifo) +reg lsr7_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7_d <= #1 0; + else lsr7_d <= #1 lsr7; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7r <= #1 0; + else lsr7r <= #1 lsr_mask ? 1'b0 : lsr7r || (lsr7 && ~lsr7_d); + +// Frequency divider +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + dlc <= #1 0; + else + if (start_dlc | ~ (|dlc)) + dlc <= #1 dl - 16'd1; // preset counter + else + dlc <= #1 dlc - 16'd1; // decrement counter +end + +// Enable signal generation logic +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + enable <= #1 1'b0; + else + if (|dl & ~(|dlc)) // dl>0 & dlc==0 + enable <= #1 1'b1; + else + enable <= #1 1'b0; +end + +// Delaying THRE status for one character cycle after a character is written to an empty fifo. +always @(lcr) + case (lcr[3:0]) + 4'b0000 : block_value = 95; // 6 bits + 4'b0100 : block_value = 103; // 6.5 bits + 4'b0001, 4'b1000 : block_value = 111; // 7 bits + 4'b1100 : block_value = 119; // 7.5 bits + 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits + 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits + 4'b1111 : block_value = 175; // 11 bits + endcase // case(lcr[3:0]) + +// Counting time of one character minus stop bit +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + block_cnt <= #1 8'd0; + else + if(lsr5r & fifo_write) // THRE bit set & write to fifo occured + block_cnt <= #1 block_value; + else + if (enable & block_cnt != 8'b0) // only work on enable times + block_cnt <= #1 block_cnt - 8'd1; // decrement break counter +end // always of break condition detection + +// Generating THRE status enable signal +assign thre_set_en = ~(|block_cnt); + + +// +// INTERRUPT LOGIC +// + +assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); +assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); +assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE]; +assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]); +assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); + +reg rls_int_d; +reg thre_int_d; +reg ms_int_d; +reg ti_int_d; +reg rda_int_d; + +// delay lines +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_d <= #1 0; + else rls_int_d <= #1 rls_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_d <= #1 0; + else rda_int_d <= #1 rda_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_d <= #1 0; + else thre_int_d <= #1 thre_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_d <= #1 0; + else ms_int_d <= #1 ms_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_d <= #1 0; + else ti_int_d <= #1 ti_int; + +// rise detection signals + +wire rls_int_rise; +wire thre_int_rise; +wire ms_int_rise; +wire ti_int_rise; +wire rda_int_rise; + +assign rda_int_rise = rda_int & ~rda_int_d; +assign rls_int_rise = rls_int & ~rls_int_d; +assign thre_int_rise = thre_int & ~thre_int_d; +assign ms_int_rise = ms_int & ~ms_int_d; +assign ti_int_rise = ti_int & ~ti_int_d; + +// interrupt pending flags +reg rls_int_pnd; +reg rda_int_pnd; +reg thre_int_pnd; +reg ms_int_pnd; +reg ti_int_pnd; + +// interrupt pending flags assignments +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_pnd <= #1 0; + else + rls_int_pnd <= #1 lsr_mask ? 1'b0 : // reset condition + rls_int_rise ? 1'b1 : // latch condition + rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_pnd <= #1 0; + else + rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 1'b0 : // reset condition + rda_int_rise ? 1'b1 : // latch condition + rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_pnd <= #1 0; + else + thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 1'b0 : + thre_int_rise ? 1'b1 : + thre_int_pnd && ier[`UART_IE_THRE]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_pnd <= #1 0; + else + ms_int_pnd <= #1 msr_read ? 1'b0 : + ms_int_rise ? 1'b1 : + ms_int_pnd && ier[`UART_IE_MS]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_pnd <= #1 0; + else + ti_int_pnd <= #1 fifo_read ? 1'b0 : + ti_int_rise ? 1'b1 : + ti_int_pnd && ier[`UART_IE_RDA]; +// end of pending flags + +// INT_O logic +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + int_o <= #1 1'b0; + else + int_o <= #1 + rls_int_pnd ? ~lsr_mask : + rda_int_pnd ? 1'b1 : + ti_int_pnd ? ~fifo_read : + thre_int_pnd ? !(fifo_write & iir_read) : + ms_int_pnd ? ~msr_read : + 1'b0; // if no interrupt are pending +end + + +// Interrupt Identification register +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + iir <= #1 1; + else + if (rls_int_pnd) // interrupt is pending + begin + iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value + iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending) + end else // the sequence of conditions determines priority of interrupt identification + if (rda_int) + begin + iir[`UART_II_II] <= #1 `UART_II_RDA; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (ti_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_TI; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (thre_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_THRE; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (ms_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_MS; + iir[`UART_II_IP] <= #1 1'b0; + end else // no interrupt is pending + begin + iir[`UART_II_II] <= #1 0; + iir[`UART_II_IP] <= #1 1'b1; + end +end + +endmodule Index: trunk/uart16550/verilog/uart_top.v =================================================================== --- trunk/uart16550/verilog/uart_top.v (nonexistent) +++ trunk/uart16550/verilog/uart_top.v (revision 2) @@ -0,0 +1,343 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_top.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core top level. //// +//// //// +//// Known problems (limits): //// +//// Note that transmitter and receiver instances are inside //// +//// the uart_regs.v file. //// +//// //// +//// To Do: //// +//// Nothing so far. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.19 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.18 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.17 2001/12/19 08:40:03 mohor +// Warnings fixed (unused signals removed). +// +// Revision 1.16 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.15 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.14 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.13 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.12 2001/08/25 15:46:19 gorban +// Modified port names again +// +// Revision 1.11 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.10 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_top ( + wb_clk_i, + + // Wishbone signals + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, + int_o, // interrupt request + + // UART signals + // serial input/output + stx_pad_o, srx_pad_i, + + // modem signals + rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + ); + +parameter uart_data_width = `UART_DATA_WIDTH; +parameter uart_addr_width = `UART_ADDR_WIDTH; + +input wb_clk_i; + +// WISHBONE interface +input wb_rst_i; +input [uart_addr_width-1:0] wb_adr_i; +input [uart_data_width-1:0] wb_dat_i; +output [uart_data_width-1:0] wb_dat_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +input [3:0] wb_sel_i; +output wb_ack_o; +output int_o; + +// UART signals +input srx_pad_i; +output stx_pad_o; +output rts_pad_o; +input cts_pad_i; +output dtr_pad_o; +input dsr_pad_i; +input ri_pad_i; +input dcd_pad_i; + +// optional baudrate output +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + + +wire stx_pad_o; +wire rts_pad_o; +wire dtr_pad_o; + +wire [uart_addr_width-1:0] wb_adr_i; +wire [uart_data_width-1:0] wb_dat_i; +wire [uart_data_width-1:0] wb_dat_o; + +wire [7:0] wb_dat8_i; // 8-bit internal data input +wire [7:0] wb_dat8_o; // 8-bit internal data output +wire [31:0] wb_dat32_o; // debug interface 32-bit output +wire [3:0] wb_sel_i; // WISHBONE select signal +wire [uart_addr_width-1:0] wb_adr_int; +wire we_o; // Write enable for registers +wire re_o; // Read enable for registers +// +// MODULE INSTANCES +// + +`ifdef DATA_BUS_WIDTH_8 +`else +// debug interface wires +wire [3:0] ier; +wire [3:0] iir; +wire [1:0] fcr; +wire [4:0] mcr; +wire [7:0] lcr; +wire [7:0] msr; +wire [7:0] lsr; +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; +wire [2:0] tstate; +wire [3:0] rstate; +`endif + +`ifdef DATA_BUS_WIDTH_8 +//// WISHBONE interface module +uart_wb wb_interface( + .clk( wb_clk_i ), + .wb_rst_i( wb_rst_i ), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_dat8_i(wb_dat8_i), + .wb_dat8_o(wb_dat8_o), + .wb_dat32_o(32'b0), + .wb_sel_i(4'b0), + .wb_we_i( wb_we_i ), + .wb_stb_i( wb_stb_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_ack_o( wb_ack_o ), + .wb_adr_i(wb_adr_i), + .wb_adr_int(wb_adr_int), + .we_o( we_o ), + .re_o(re_o) + ); +`else +uart_wb wb_interface( + .clk( wb_clk_i ), + .wb_rst_i( wb_rst_i ), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_dat8_i(wb_dat8_i), + .wb_dat8_o(wb_dat8_o), + .wb_sel_i(wb_sel_i), + .wb_dat32_o(wb_dat32_o), + .wb_we_i( wb_we_i ), + .wb_stb_i( wb_stb_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_ack_o( wb_ack_o ), + .wb_adr_i(wb_adr_i), + .wb_adr_int(wb_adr_int), + .we_o( we_o ), + .re_o(re_o) + ); +`endif + +// Registers +uart_regs regs( + .clk( wb_clk_i ), + .wb_rst_i( wb_rst_i ), + .wb_addr_i( wb_adr_int ), + .wb_dat_i( wb_dat8_i ), + .wb_dat_o( wb_dat8_o ), + .wb_we_i( we_o ), + .wb_re_i(re_o), + .modem_inputs( {cts_pad_i, dsr_pad_i, + ri_pad_i, dcd_pad_i} ), + .stx_pad_o( stx_pad_o ), + .srx_pad_i( srx_pad_i ), +`ifdef DATA_BUS_WIDTH_8 +`else +// debug interface signals enabled +.ier(ier), +.iir(iir), +.fcr(fcr), +.mcr(mcr), +.lcr(lcr), +.msr(msr), +.lsr(lsr), +.rf_count(rf_count), +.tf_count(tf_count), +.tstate(tstate), +.rstate(rstate), +`endif + .rts_pad_o( rts_pad_o ), + .dtr_pad_o( dtr_pad_o ), + .int_o( int_o ) +`ifdef UART_HAS_BAUDRATE_OUTPUT + , .baud_o(baud_o) +`endif + +); + +`ifdef DATA_BUS_WIDTH_8 +`else +uart_debug_if dbg(/*AUTOINST*/ + // Outputs + .wb_dat32_o (wb_dat32_o[31:0]), + // Inputs + .wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]), + .ier (ier[3:0]), + .iir (iir[3:0]), + .fcr (fcr[1:0]), + .mcr (mcr[4:0]), + .lcr (lcr[7:0]), + .msr (msr[7:0]), + .lsr (lsr[7:0]), + .rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]), + .tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]), + .tstate (tstate[2:0]), + .rstate (rstate[3:0])); +`endif +/* +initial +begin + `ifdef DATA_BUS_WIDTH_8 + $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n"); + `else + $display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n"); + `endif + `ifdef UART_HAS_BAUDRATE_OUTPUT + $display("(%m) UART INFO: Has baudrate output\n"); + `else + $display("(%m) UART INFO: Doesn't have baudrate output\n"); + `endif +end +*/ +endmodule + + Index: trunk/uart16550/verilog/raminfr.v =================================================================== --- trunk/uart16550/verilog/raminfr.v (nonexistent) +++ trunk/uart16550/verilog/raminfr.v (revision 2) @@ -0,0 +1,114 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// raminfr.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Inferrable Distributed RAM for FIFOs //// +//// //// +//// Known problems (limits): //// +//// None . //// +//// //// +//// To Do: //// +//// Nothing so far. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2002/07/22 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// + +//Following is the Verilog code for a dual-port RAM with asynchronous read. +module raminfr + (clk, we, a, dpra, di, dpo); + +parameter addr_width = 4; +parameter data_width = 8; +parameter depth = 16; + +input clk; +input we; +input [addr_width-1:0] a; +input [addr_width-1:0] dpra; +input [data_width-1:0] di; +//output [data_width-1:0] spo; +output [data_width-1:0] dpo; +reg [data_width-1:0] ram [depth-1:0]; + +wire [data_width-1:0] dpo; +wire [data_width-1:0] di; +wire [addr_width-1:0] a; +wire [addr_width-1:0] dpra; + + always @(posedge clk) begin + if (we) + ram[a] <= di; + end +// assign spo = ram[a]; + assign dpo = ram[dpra]; +endmodule + Index: trunk/uart16550/verilog/uart_debug_if.v =================================================================== --- trunk/uart16550/verilog/uart_debug_if.v (nonexistent) +++ trunk/uart16550/verilog/uart_debug_if.v (revision 2) @@ -0,0 +1,129 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_debug_if.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core debug interface. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2001/12/02 //// +//// (See log for the revision history) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.4 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.3 2001/12/19 08:40:03 mohor +// Warnings fixed (unused signals removed). +// +// Revision 1.2 2001/12/12 22:17:30 gorban +// some synthesis bugs fixed +// +// Revision 1.1 2001/12/04 21:14:16 gorban +// committed the debug interface file +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_debug_if (/*AUTOARG*/ +// Outputs +wb_dat32_o, +// Inputs +wb_adr_i, ier, iir, fcr, mcr, lcr, msr, +lsr, rf_count, tf_count, tstate, rstate +) ; + +input [`UART_ADDR_WIDTH-1:0] wb_adr_i; +output [31:0] wb_dat32_o; +input [3:0] ier; +input [3:0] iir; +input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +input [4:0] mcr; +input [7:0] lcr; +input [7:0] msr; +input [7:0] lsr; +input [`UART_FIFO_COUNTER_W-1:0] rf_count; +input [`UART_FIFO_COUNTER_W-1:0] tf_count; +input [2:0] tstate; +input [3:0] rstate; + + +wire [`UART_ADDR_WIDTH-1:0] wb_adr_i; +reg [31:0] wb_dat32_o; + +always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr + or rf_count or rstate or tf_count or tstate or wb_adr_i) + case (wb_adr_i) + // 8 + 8 + 4 + 4 + 8 + 5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr}; + // 5 + 2 + 5 + 4 + 5 + 3 + 5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate}; + default: wb_dat32_o = 0; + endcase // case(wb_adr_i) + +endmodule // uart_debug_if + Index: trunk/uart16550/verilog/uart_receiver.v =================================================================== --- trunk/uart16550/verilog/uart_receiver.v (nonexistent) +++ trunk/uart16550/verilog/uart_receiver.v (revision 2) @@ -0,0 +1,485 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_receiver.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.31 2004/06/18 14:46:15 tadejm +// Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. +// +// Revision 1.29 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.28 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.27 2001/12/30 20:39:13 mohor +// More than one character was stored in case of break. End of the break +// was not detected correctly. +// +// Revision 1.26 2001/12/20 13:28:27 mohor +// Missing declaration of rf_push_q fixed. +// +// Revision 1.25 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.24 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.23 2001/12/19 07:33:54 mohor +// Synplicity was having troubles with the comment. +// +// Revision 1.22 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.21 2001/12/13 10:31:16 mohor +// timeout irq must be set regardless of the rda irq (rda irq does not reset the +// timeout counter). +// +// Revision 1.20 2001/12/10 19:52:05 gorban +// Igor fixed break condition bugs +// +// Revision 1.19 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.18 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.17 2001/11/28 19:36:39 gorban +// Fixed: timeout and break didn't pay attention to current data format when counting time +// +// Revision 1.16 2001/11/27 22:17:09 gorban +// Fixed bug that prevented synthesis in uart_receiver.v +// +// Revision 1.15 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.14 2001/11/10 12:43:21 gorban +// Logic Synthesis bugs fixed. Some other minor changes +// +// Revision 1.13 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.12 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.11 2001/10/31 15:19:22 gorban +// Fixes to break and timeout conditions +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.6 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.5 2001/06/02 14:28:14 gorban +// Fixed receiver and transmitter. Major bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.1 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input rf_pop; +input srx_pad_i; +input enable; +input rx_reset; +input lsr_mask; + +output [9:0] counter_t; +output [`UART_FIFO_COUNTER_W-1:0] rf_count; +output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +output rf_overrun; +output rf_error_bit; +output [3:0] rstate; +output rf_push_pulse; + +reg [3:0] rstate; +reg [3:0] rcounter16; +reg [2:0] rbit_counter; +reg [7:0] rshift; // receiver shift register +reg rparity; // received parity +reg rparity_error; +reg rframing_error; // framing error flag +reg rbit_in; +reg rparity_xor; +reg [7:0] counter_b; // counts the 0 (low) signals +reg rf_push_q; + +// RX FIFO signals +reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_push_pulse; +reg rf_push; +wire rf_pop; +wire rf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire rf_error_bit; // an error (parity or framing) is inside the fifo +wire break_error = (counter_b == 0); + +// RX FIFO instance +uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .data_in( rf_data_in ), + .data_out( rf_data_out ), + .push( rf_push_pulse ), + .pop( rf_pop ), + .overrun( rf_overrun ), + .count( rf_count ), + .error_bit( rf_error_bit ), + .fifo_reset( rx_reset ), + .reset_status(lsr_mask) +); + +wire rcounter16_eq_7 = (rcounter16 == 4'd7); +wire rcounter16_eq_0 = (rcounter16 == 4'd0); +wire rcounter16_eq_1 = (rcounter16 == 4'd1); + +wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1; + +parameter sr_idle = 4'd0; +parameter sr_rec_start = 4'd1; +parameter sr_rec_bit = 4'd2; +parameter sr_rec_parity = 4'd3; +parameter sr_rec_stop = 4'd4; +parameter sr_check_parity = 4'd5; +parameter sr_rec_prepare = 4'd6; +parameter sr_end_bit = 4'd7; +parameter sr_ca_lc_parity = 4'd8; +parameter sr_wait1 = 4'd9; +parameter sr_push = 4'd10; + + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + rstate <= #1 sr_idle; + rbit_in <= #1 1'b0; + rcounter16 <= #1 0; + rbit_counter <= #1 0; + rparity_xor <= #1 1'b0; + rframing_error <= #1 1'b0; + rparity_error <= #1 1'b0; + rparity <= #1 1'b0; + rshift <= #1 0; + rf_push <= #1 1'b0; + rf_data_in <= #1 0; + end + else + if (enable) + begin + case (rstate) + sr_idle : begin + rf_push <= #1 1'b0; + rf_data_in <= #1 0; + rcounter16 <= #1 4'b1110; + if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?) + begin + rstate <= #1 sr_rec_start; + end + end + sr_rec_start : begin + rf_push <= #1 1'b0; + if (rcounter16_eq_7) // check the pulse + if (srx_pad_i==1'b1) // no start bit + rstate <= #1 sr_idle; + else // start bit detected + rstate <= #1 sr_rec_prepare; + rcounter16 <= #1 rcounter16_minus_1; + end + sr_rec_prepare:begin + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : rbit_counter <= #1 3'b100; + 2'b01 : rbit_counter <= #1 3'b101; + 2'b10 : rbit_counter <= #1 3'b110; + 2'b11 : rbit_counter <= #1 3'b111; + endcase + if (rcounter16_eq_0) + begin + rstate <= #1 sr_rec_bit; + rcounter16 <= #1 4'b1110; + rshift <= #1 0; + end + else + rstate <= #1 sr_rec_prepare; + rcounter16 <= #1 rcounter16_minus_1; + end + sr_rec_bit : begin + if (rcounter16_eq_0) + rstate <= #1 sr_end_bit; + if (rcounter16_eq_7) // read the bit + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]}; + 2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]}; + 2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]}; + 2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]}; + endcase + rcounter16 <= #1 rcounter16_minus_1; + end + sr_end_bit : begin + if (rbit_counter==3'b0) // no more bits in word + if (lcr[`UART_LC_PE]) // choose state based on parity + rstate <= #1 sr_rec_parity; + else + begin + rstate <= #1 sr_rec_stop; + rparity_error <= #1 1'b0; // no parity - no error :) + end + else // else we have more bits to read + begin + rstate <= #1 sr_rec_bit; + rbit_counter <= #1 rbit_counter - 1'b1; + end + rcounter16 <= #1 4'b1110; + end + sr_rec_parity: begin + if (rcounter16_eq_7) // read the parity + begin + rparity <= #1 srx_pad_i; + rstate <= #1 sr_ca_lc_parity; + end + rcounter16 <= #1 rcounter16_minus_1; + end + sr_ca_lc_parity : begin // rcounter equals 6 + rcounter16 <= #1 rcounter16_minus_1; + rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data + rstate <= #1 sr_check_parity; + end + sr_check_parity: begin // rcounter equals 5 + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1 + 2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1 + 2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd + 2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0 + endcase + rcounter16 <= #1 rcounter16_minus_1; + rstate <= #1 sr_wait1; + end + sr_wait1 : if (rcounter16_eq_0) + begin + rstate <= #1 sr_rec_stop; + rcounter16 <= #1 4'b1110; + end + else + rcounter16 <= #1 rcounter16_minus_1; + sr_rec_stop : begin + if (rcounter16_eq_7) // read the parity + begin + rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit) + rstate <= #1 sr_push; + end + rcounter16 <= #1 rcounter16_minus_1; + end + sr_push : begin +/////////////////////////////////////// +// $display($time, ": received: %b", rf_data_in); + if(srx_pad_i | break_error) + begin + if(break_error) + rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO + else + rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= #1 1'b1; + rstate <= #1 sr_idle; + end + else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i + begin + rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= #1 1'b1; + rcounter16 <= #1 4'b1110; + rstate <= #1 sr_rec_start; + end + + end + default : rstate <= #1 sr_idle; + endcase + end // if (enable) +end // always of receiver + +always @ (posedge clk or posedge wb_rst_i) +begin + if(wb_rst_i) + rf_push_q <= 0; + else + rf_push_q <= #1 rf_push; +end + +assign rf_push_pulse = rf_push & ~rf_push_q; + + +// +// Break condition detection. +// Works in conjuction with the receiver state machine + +reg [9:0] toc_value; // value to be set to timeout counter + +always @(lcr) + case (lcr[3:0]) + 4'b0000 : toc_value = 447; // 7 bits + 4'b0100 : toc_value = 479; // 7.5 bits + 4'b0001, 4'b1000 : toc_value = 511; // 8 bits + 4'b1100 : toc_value = 543; // 8.5 bits + 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits + 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits + 4'b1111 : toc_value = 767; // 12 bits + endcase // case(lcr[3:0]) + +wire [7:0] brc_value; // value to be set to break counter +assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + counter_b <= #1 8'd159; + else + if (srx_pad_i) + counter_b <= #1 brc_value; // character time length - 1 + else + if(enable & counter_b != 8'b0) // only work on enable times break not reached. + counter_b <= #1 counter_b - 8'd1; // decrement break counter +end // always of break condition detection + +/// +/// Timeout condition detection +reg [9:0] counter_t; // counts the timeout condition clocks + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + counter_t <= #1 10'd639; // 10 bits for the default 8N1 + else + if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level + counter_t <= #1 toc_value; + else + if (enable && counter_t != 10'b0) // we don't want to underflow + counter_t <= #1 counter_t - 8'd1; +end + +endmodule Index: trunk/uart16550/verilog/uart_rfifo.v =================================================================== --- trunk/uart16550/verilog/uart_rfifo.v (nonexistent) +++ trunk/uart16550/verilog/uart_rfifo.v (revision 2) @@ -0,0 +1,323 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_rfifo.v (Modified from uart_fifo.v) //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver FIFO //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.4 2003/07/11 18:20:26 gorban +// added clearing the receiver fifo statuses on resets +// +// Revision 1.3 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.2 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.15 2001/12/18 09:01:07 mohor +// Bug that was entered in the last update fixed (rx state machine). +// +// Revision 1.14 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.13 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.12 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.11 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/24 08:48:10 mohor +// FIFO was not cleared after the data was read bug fixed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.3 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:48 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_rfifo (clk, + wb_rst_i, data_in, data_out, +// Control signals + push, // push strobe, active high + pop, // pop strobe, active high +// status signals + overrun, + count, + error_bit, + fifo_reset, + reset_status + ); + + +// FIFO parameters +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; +output error_bit; + +wire [fifo_width-1:0] data_out; +wire [7:0] data8_out; +// flags FIFO +reg [2:0] fifo[fifo_depth-1:0]; + +// FIFO pointers +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; + +wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; + +raminfr #(fifo_pointer_w,8,fifo_depth) rfifo + (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in[fifo_width-1:fifo_width-8]), + .dpo(data8_out) + ); + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + fifo[0] <= #1 0; + fifo[1] <= #1 0; + fifo[2] <= #1 0; + fifo[3] <= #1 0; + fifo[4] <= #1 0; + fifo[5] <= #1 0; + fifo[6] <= #1 0; + fifo[7] <= #1 0; + fifo[8] <= #1 0; + fifo[9] <= #1 0; + fifo[10] <= #1 0; + fifo[11] <= #1 0; + fifo[12] <= #1 0; + fifo[13] <= #1 0; + fifo[14] <= #1 0; + fifo[15] <= #1 0; + end + else + if (fifo_reset) begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + fifo[0] <= #1 0; + fifo[1] <= #1 0; + fifo[2] <= #1 0; + fifo[3] <= #1 0; + fifo[4] <= #1 0; + fifo[5] <= #1 0; + fifo[6] <= #1 0; + fifo[7] <= #1 0; + fifo[8] <= #1 0; + fifo[9] <= #1 0; + fifo[10] <= #1 0; + fifo[11] <= #1 0; + fifo[12] <= #1 0; + fifo[13] <= #1 0; + fifo[14] <= #1 0; + fifo[15] <= #1 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + fifo[bottom] <= #1 0; + bottom <= #1 bottom + 1'b1; + count <= #1 count - 1'b1; + end + 2'b11 : begin + bottom <= #1 bottom + 1'b1; + top <= #1 top_plus_1; + fifo[top] <= #1 data_in[2:0]; + end + default: ; + endcase + end +end // always + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + overrun <= #1 1'b0; + else + if(fifo_reset | reset_status) + overrun <= #1 1'b0; + else + if(push & ~pop & (count==fifo_depth)) + overrun <= #1 1'b1; +end // always + + +// please note though that data_out is only valid one clock after pop signal +assign data_out = {data8_out,fifo[bottom]}; + +// Additional logic for detection of error conditions (parity and framing) inside the FIFO +// for the Line Status Register bit 7 + +wire [2:0] word0 = fifo[0]; +wire [2:0] word1 = fifo[1]; +wire [2:0] word2 = fifo[2]; +wire [2:0] word3 = fifo[3]; +wire [2:0] word4 = fifo[4]; +wire [2:0] word5 = fifo[5]; +wire [2:0] word6 = fifo[6]; +wire [2:0] word7 = fifo[7]; + +wire [2:0] word8 = fifo[8]; +wire [2:0] word9 = fifo[9]; +wire [2:0] word10 = fifo[10]; +wire [2:0] word11 = fifo[11]; +wire [2:0] word12 = fifo[12]; +wire [2:0] word13 = fifo[13]; +wire [2:0] word14 = fifo[14]; +wire [2:0] word15 = fifo[15]; + +// a 1 is returned if any of the error bits in the fifo is 1 +assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | + word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | + word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | + word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); + +endmodule Index: trunk/uart16550/verilog/uart_tfifo.v =================================================================== --- trunk/uart16550/verilog/uart_tfifo.v (nonexistent) +++ trunk/uart16550/verilog/uart_tfifo.v (revision 2) @@ -0,0 +1,246 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_tfifo.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core transmitter FIFO //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.15 2001/12/18 09:01:07 mohor +// Bug that was entered in the last update fixed (rx state machine). +// +// Revision 1.14 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.13 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.12 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.11 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/24 08:48:10 mohor +// FIFO was not cleared after the data was read bug fixed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.3 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:48 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_tfifo (clk, + wb_rst_i, data_in, data_out, +// Control signals + push, // push strobe, active high + pop, // pop strobe, active high +// status signals + overrun, + count, + fifo_reset, + reset_status + ); + + +// FIFO parameters +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; + +wire [fifo_width-1:0] data_out; + +// FIFO pointers +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; +wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; + +raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo + (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in), + .dpo(data_out) + ); + + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + end + else + if (fifo_reset) begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + bottom <= #1 bottom + 1'b1; + count <= #1 count - 1'b1; + end + 2'b11 : begin + bottom <= #1 bottom + 1'b1; + top <= #1 top_plus_1; + end + default: ; + endcase + end +end // always + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + overrun <= #1 1'b0; + else + if(fifo_reset | reset_status) + overrun <= #1 1'b0; + else + if(push & (count==fifo_depth)) + overrun <= #1 1'b1; +end // always + +endmodule Index: trunk/uart16550/verilog/uart_wb.v =================================================================== --- trunk/uart16550/verilog/uart_wb.v (nonexistent) +++ trunk/uart16550/verilog/uart_wb.v (revision 2) @@ -0,0 +1,320 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_wb.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core WISHBONE interface. //// +//// //// +//// Known problems (limits): //// +//// Inserts one wait state on all transfers. //// +//// Note affected signals and the way they are affected. //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.17 2004/05/21 12:35:15 tadejm +// Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. +// +// Revision 1.16 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.15 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.12 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.11 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.10 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.9 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.8 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/21 19:12:01 gorban +// Corrected some Linter messages. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:13+02 jacob +// Initial revision +// +// + +// UART core WISHBONE interface +// +// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com) +// Company: Flextronics Semiconductor +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "uart_defines.v" + +module uart_wb (clk, wb_rst_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, + wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i, + we_o, re_o // Write and read enable output for the core +); + +input clk; + +// WISHBONE interface +input wb_rst_i; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +input [3:0] wb_sel_i; +input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line + +`ifdef DATA_BUS_WIDTH_8 +input [7:0] wb_dat_i; //input WISHBONE bus +output [7:0] wb_dat_o; +reg [7:0] wb_dat_o; +wire [7:0] wb_dat_i; +reg [7:0] wb_dat_is; +`else // for 32 data bus mode +input [31:0] wb_dat_i; //input WISHBONE bus +output [31:0] wb_dat_o; +reg [31:0] wb_dat_o; +wire [31:0] wb_dat_i; +reg [31:0] wb_dat_is; +`endif // !`ifdef DATA_BUS_WIDTH_8 + +output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus +input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o +output [7:0] wb_dat8_i; +input [31:0] wb_dat32_o; // 32 bit data output (for debug interface) +output wb_ack_o; +output we_o; +output re_o; + +wire we_o; +reg wb_ack_o; +reg [7:0] wb_dat8_i; +wire [7:0] wb_dat8_o; +wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus +reg [`UART_ADDR_WIDTH-1:0] wb_adr_is; +reg wb_we_is; +reg wb_cyc_is; +reg wb_stb_is; +reg [3:0] wb_sel_is; +wire [3:0] wb_sel_i; +reg wre ;// timing control signal for write or read enable + +// wb_ack_o FSM +reg [1:0] wbstate; +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + wb_ack_o <= #1 1'b0; + wbstate <= #1 0; + wre <= #1 1'b1; + end else + case (wbstate) + 0: begin + if (wb_stb_is & wb_cyc_is) begin + wre <= #1 0; + wbstate <= #1 1; + wb_ack_o <= #1 1; + end else begin + wre <= #1 1; + wb_ack_o <= #1 0; + end + end + 1: begin + wb_ack_o <= #1 0; + wbstate <= #1 2; + wre <= #1 0; + end + 2,3: begin + wb_ack_o <= #1 0; + wbstate <= #1 0; + wre <= #1 0; + end + endcase + +assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers +assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers + +// Sample input signals +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + wb_adr_is <= #1 0; + wb_we_is <= #1 0; + wb_cyc_is <= #1 0; + wb_stb_is <= #1 0; + wb_dat_is <= #1 0; + wb_sel_is <= #1 0; + end else begin + wb_adr_is <= #1 wb_adr_i; + wb_we_is <= #1 wb_we_i; + wb_cyc_is <= #1 wb_cyc_i; + wb_stb_is <= #1 wb_stb_i; + wb_dat_is <= #1 wb_dat_i; + wb_sel_is <= #1 wb_sel_i; + end + +`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 0; + else + wb_dat_o <= #1 wb_dat8_o; + +always @(wb_dat_is) + wb_dat8_i = wb_dat_is; + +assign wb_adr_int = wb_adr_is; + +`else // 32-bit bus +// put output to the correct byte in 32 bits using select line +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 0; + else if (re_o) + case (wb_sel_is) + 4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o}; + 4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0}; + 4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0}; + 4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0}; + 4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output + default: wb_dat_o <= #1 0; + endcase // case(wb_sel_i) + +reg [1:0] wb_adr_int_lsb; + +always @(wb_sel_is or wb_dat_is) +begin + case (wb_sel_is) + 4'b0001 : wb_dat8_i = wb_dat_is[7:0]; + 4'b0010 : wb_dat8_i = wb_dat_is[15:8]; + 4'b0100 : wb_dat8_i = wb_dat_is[23:16]; + 4'b1000 : wb_dat8_i = wb_dat_is[31:24]; + default : wb_dat8_i = wb_dat_is[7:0]; + endcase // case(wb_sel_i) + + `ifdef LITLE_ENDIAN + case (wb_sel_is) + 4'b0001 : wb_adr_int_lsb = 2'h0; + 4'b0010 : wb_adr_int_lsb = 2'h1; + 4'b0100 : wb_adr_int_lsb = 2'h2; + 4'b1000 : wb_adr_int_lsb = 2'h3; + default : wb_adr_int_lsb = 2'h0; + endcase // case(wb_sel_i) + `else + case (wb_sel_is) + 4'b0001 : wb_adr_int_lsb = 2'h3; + 4'b0010 : wb_adr_int_lsb = 2'h2; + 4'b0100 : wb_adr_int_lsb = 2'h1; + 4'b1000 : wb_adr_int_lsb = 2'h0; + default : wb_adr_int_lsb = 2'h0; + endcase // case(wb_sel_i) + `endif +end + +assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb}; + +`endif // !`ifdef DATA_BUS_WIDTH_8 + +endmodule + + + + + + + + + + Index: trunk/uart16550/verilog/timescale.v =================================================================== --- trunk/uart16550/verilog/timescale.v (nonexistent) +++ trunk/uart16550/verilog/timescale.v (revision 2) @@ -0,0 +1,64 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// timescale.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Defines of the Core //// +//// //// +//// Known problems (limits): //// +//// None //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// Timescale define + +`timescale 1ns/10ps Index: trunk/uart16550/verilog/uart_transmitter.v =================================================================== --- trunk/uart16550/verilog/uart_transmitter.v (nonexistent) +++ trunk/uart16550/verilog/uart_transmitter.v (revision 2) @@ -0,0 +1,354 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_transmitter.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core transmitter logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.19 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.18 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2002/01/08 11:29:40 mohor +// tf_pop was too wide. Now it is only 1 clk cycle width. +// +// Revision 1.15 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.14 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.13 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.12 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.11 2001/10/29 17:00:46 gorban +// fixed parity sending and tx_fifo resets over- and underrun +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.6 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.5 2001/06/02 14:28:14 gorban +// Fixed receiver and transmitter. Major bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.1 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input tf_push; +input [7:0] wb_dat_i; +input enable; +input tx_reset; +input lsr_mask; //reset of fifo +output stx_pad_o; +output [2:0] tstate; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; + +reg [2:0] tstate; +reg [4:0] counter; +reg [2:0] bit_counter; // counts the bits to be sent +reg [6:0] shift_out; // output shift register +reg stx_o_tmp; +reg parity_xor; // parity of the word +reg tf_pop; +reg bit_out; + +// TX FIFO instance +// +// Transmitter FIFO signals +wire [`UART_FIFO_WIDTH-1:0] tf_data_in; +wire [`UART_FIFO_WIDTH-1:0] tf_data_out; +wire tf_push; +wire tf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; + +assign tf_data_in = wb_dat_i; + +uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .data_in( tf_data_in ), + .data_out( tf_data_out ), + .push( tf_push ), + .pop( tf_pop ), + .overrun( tf_overrun ), + .count( tf_count ), + .fifo_reset( tx_reset ), + .reset_status(lsr_mask) +); + +// TRANSMITTER FINAL STATE MACHINE + +parameter s_idle = 3'd0; +parameter s_send_start = 3'd1; +parameter s_send_byte = 3'd2; +parameter s_send_parity = 3'd3; +parameter s_send_stop = 3'd4; +parameter s_pop_byte = 3'd5; + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + tstate <= #1 s_idle; + stx_o_tmp <= #1 1'b1; + counter <= #1 5'b0; + shift_out <= #1 7'b0; + bit_out <= #1 1'b0; + parity_xor <= #1 1'b0; + tf_pop <= #1 1'b0; + bit_counter <= #1 3'b0; + end + else + if (enable) + begin + case (tstate) + s_idle : if (~|tf_count) // if tf_count==0 + begin + tstate <= #1 s_idle; + stx_o_tmp <= #1 1'b1; + end + else + begin + tf_pop <= #1 1'b0; + stx_o_tmp <= #1 1'b1; + tstate <= #1 s_pop_byte; + end + s_pop_byte : begin + tf_pop <= #1 1'b1; + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : begin + bit_counter <= #1 3'b100; + parity_xor <= #1 ^tf_data_out[4:0]; + end + 2'b01 : begin + bit_counter <= #1 3'b101; + parity_xor <= #1 ^tf_data_out[5:0]; + end + 2'b10 : begin + bit_counter <= #1 3'b110; + parity_xor <= #1 ^tf_data_out[6:0]; + end + 2'b11 : begin + bit_counter <= #1 3'b111; + parity_xor <= #1 ^tf_data_out[7:0]; + end + endcase + {shift_out[6:0], bit_out} <= #1 tf_data_out; + tstate <= #1 s_send_start; + end + s_send_start : begin + tf_pop <= #1 1'b0; + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= #1 0; + tstate <= #1 s_send_byte; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 1'b0; + end + s_send_byte : begin + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + if (bit_counter > 3'b0) + begin + bit_counter <= #1 bit_counter - 1'b1; + {shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]}; + tstate <= #1 s_send_byte; + end + else // end of byte + if (~lcr[`UART_LC_PE]) + begin + tstate <= #1 s_send_stop; + end + else + begin + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: bit_out <= #1 ~parity_xor; + 2'b01: bit_out <= #1 1'b1; + 2'b10: bit_out <= #1 parity_xor; + 2'b11: bit_out <= #1 1'b0; + endcase + tstate <= #1 s_send_parity; + end + counter <= #1 0; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 bit_out; // set output pin + end + s_send_parity : begin + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= #1 4'b0; + tstate <= #1 s_send_stop; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 bit_out; + end + s_send_stop : begin + if (~|counter) + begin + casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) + 3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor + 3'b100: counter <= #1 5'b10101; // 1.5 stop bit + default: counter <= #1 5'b11101; // 2 stop bits + endcase + end + else + if (counter == 5'b00001) + begin + counter <= #1 0; + tstate <= #1 s_idle; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 1'b1; + end + + default : // should never get here + tstate <= #1 s_idle; + endcase + end // end if enable + else + tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width +end // transmitter logic + +assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition + +endmodule Index: trunk/uart16550/verilog/uart_defines.v =================================================================== --- trunk/uart16550/verilog/uart_defines.v (nonexistent) +++ trunk/uart16550/verilog/uart_defines.v (revision 2) @@ -0,0 +1,250 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_defines.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Defines of the Core //// +//// //// +//// Known problems (limits): //// +//// None //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.14 2003/09/12 07:26:58 dries +// adjusted comment + define +// +// Revision 1.13 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.12 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.10 2001/12/11 08:55:40 mohor +// Scratch register define added. +// +// Revision 1.9 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.8 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.7 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.6 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.5 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.4 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.3 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// remove comments to restore to use the new version with 8 data bit interface +// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place +// also, in 8-bit version there'll be no debugging features included +// CAUTION: doesn't work with current version of OR1200 +//`define DATA_BUS_WIDTH_8 + +`ifdef DATA_BUS_WIDTH_8 + `define UART_ADDR_WIDTH 3 + `define UART_DATA_WIDTH 8 +`else + `define UART_ADDR_WIDTH 5 + `define UART_DATA_WIDTH 32 +`endif + +// Uncomment this if you want your UART to have +// 16xBaudrate output port. +// If defined, the enable signal will be used to drive baudrate_o signal +// It's frequency is 16xbaudrate + +// `define UART_HAS_BAUDRATE_OUTPUT + +// Register addresses +`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer +`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter +`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable +`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification +`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control +`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control +`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control +`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status +`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status +`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register +`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2) +`define UART_REG_DL2 `UART_ADDR_WIDTH'd1 + +// Interrupt Enable register bits +`define UART_IE_RDA 0 // Received Data available interrupt +`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt +`define UART_IE_RLS 2 // Receiver Line Status Interrupt +`define UART_IE_MS 3 // Modem Status Interrupt + +// Interrupt Identification register bits +`define UART_II_IP 0 // Interrupt pending when 0 +`define UART_II_II 3:1 // Interrupt identification + +// Interrupt identification values for bits 3:1 +`define UART_II_RLS 3'b011 // Receiver Line Status +`define UART_II_RDA 3'b010 // Receiver Data available +`define UART_II_TI 3'b110 // Timeout Indication +`define UART_II_THRE 3'b001 // Transmitter Holding Register empty +`define UART_II_MS 3'b000 // Modem Status + +// FIFO Control Register bits +`define UART_FC_TL 1:0 // Trigger level + +// FIFO trigger level values +`define UART_FC_1 2'b00 +`define UART_FC_4 2'b01 +`define UART_FC_8 2'b10 +`define UART_FC_14 2'b11 + +// Line Control register bits +`define UART_LC_BITS 1:0 // bits in character +`define UART_LC_SB 2 // stop bits +`define UART_LC_PE 3 // parity enable +`define UART_LC_EP 4 // even parity +`define UART_LC_SP 5 // stick parity +`define UART_LC_BC 6 // Break control +`define UART_LC_DL 7 // Divisor Latch access bit + +// Modem Control register bits +`define UART_MC_DTR 0 +`define UART_MC_RTS 1 +`define UART_MC_OUT1 2 +`define UART_MC_OUT2 3 +`define UART_MC_LB 4 // Loopback mode + +// Line Status Register bits +`define UART_LS_DR 0 // Data ready +`define UART_LS_OE 1 // Overrun Error +`define UART_LS_PE 2 // Parity Error +`define UART_LS_FE 3 // Framing Error +`define UART_LS_BI 4 // Break interrupt +`define UART_LS_TFE 5 // Transmit FIFO is empty +`define UART_LS_TE 6 // Transmitter Empty indicator +`define UART_LS_EI 7 // Error indicator + +// Modem Status Register bits +`define UART_MS_DCTS 0 // Delta signals +`define UART_MS_DDSR 1 +`define UART_MS_TERI 2 +`define UART_MS_DDCD 3 +`define UART_MS_CCTS 4 // Complement signals +`define UART_MS_CDSR 5 +`define UART_MS_CRI 6 +`define UART_MS_CDCD 7 + +// FIFO parameter defines + +`define UART_FIFO_WIDTH 8 +`define UART_FIFO_DEPTH 16 +`define UART_FIFO_POINTER_W 4 +`define UART_FIFO_COUNTER_W 5 +// receiver fifo has width 11 because it has break, parity and framing error bits +`define UART_FIFO_REC_WIDTH 11 + + +`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded +`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register) +`define FAST_TEST 1 // 64/1024 packets are sent + +`define LITLE_ENDIAN 1 + + + + + Index: trunk/uart16550/verilog/uart_sync_flops.v =================================================================== --- trunk/uart16550/verilog/uart_sync_flops.v (nonexistent) +++ trunk/uart16550/verilog/uart_sync_flops.v (revision 2) @@ -0,0 +1,125 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_sync_flops.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - Andrej Erzen (andreje@flextronics.si) //// +//// - Tadej Markovic (tadejm@flextronics.si) //// +//// //// +//// Created: 2004/05/20 //// +//// Last Updated: 2004/05/20 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2004/05/21 11:43:25 tadejm +// Added to synchronize RX input to Wishbone clock. +// +// + + +`include "timescale.v" + + +module uart_sync_flops +( + // internal signals + rst_i, + clk_i, + stage1_rst_i, + stage1_clk_en_i, + async_dat_i, + sync_dat_o +); + +parameter Tp = 1; +parameter width = 1; +parameter init_value = 1'b0; + +input rst_i; // reset input +input clk_i; // clock input +input stage1_rst_i; // synchronous reset for stage 1 FF +input stage1_clk_en_i; // synchronous clock enable for stage 1 FF +input [width-1:0] async_dat_i; // asynchronous data input +output [width-1:0] sync_dat_o; // synchronous data output + + +// +// Interal signal declarations +// + +reg [width-1:0] sync_dat_o; +reg [width-1:0] flop_0; + + +// first stage +always @ (posedge clk_i or posedge rst_i) +begin + if (rst_i) + flop_0 <= #Tp {width{init_value}}; + else + flop_0 <= #Tp async_dat_i; +end + +// second stage +always @ (posedge clk_i or posedge rst_i) +begin + if (rst_i) + sync_dat_o <= #Tp {width{init_value}}; + else if (stage1_rst_i) + sync_dat_o <= #Tp {width{init_value}}; + else if (stage1_clk_en_i) + sync_dat_o <= #Tp flop_0; +end + +endmodule Index: trunk/uart16550/altera/uart16550.qpf =================================================================== --- trunk/uart16550/altera/uart16550.qpf (nonexistent) +++ trunk/uart16550/altera/uart16550.qpf (revision 2) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "7.1" +DATE = "00:20:04 August 27, 2007" + + +# Revisions + +PROJECT_REVISION = "uart_top" Index: trunk/uart16550/altera/simulation/modelsim/gate.do =================================================================== --- trunk/uart16550/altera/simulation/modelsim/gate.do (nonexistent) +++ trunk/uart16550/altera/simulation/modelsim/gate.do (revision 2) @@ -0,0 +1,8 @@ +vsim -L /home/zeus/zet/uart16550/rtl/altera/simulation/modelsim/verilog_libs/stratixii_ver -do uart_top_run_msim_gate_verilog.do -l msim_transcript -i -t ps work.uart_test +add wave sim:/uart_test/clk_ +add wave sim:/uart_test/stxo_ +add wave sim:/uart_test/led_ +add wave sim:/uart_test/\\pll0|altpll_component|_clk0\\ +add wave sim:/uart_test/\\pll0|altpll_component|_locked\\ +force -freeze sim:/uart_test/clk_ 1 0, 0 {10 ns} -r 20ns +run 50us \ No newline at end of file Index: trunk/uart16550/altera/uart_top.qsf =================================================================== --- trunk/uart16550/altera/uart_top.qsf (nonexistent) +++ trunk/uart16550/altera/uart_top.qsf (revision 2) @@ -0,0 +1,89 @@ +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# uart_top_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# uart_top_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name DEVICE EP2S60F672C5ES +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name TOP_LEVEL_ENTITY uart_test +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.1 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:20:04 AUGUST 27, 2007" +set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation +set_global_assignment -name VERILOG_FILE altpll0.v +set_global_assignment -name VERILOG_FILE uart_test.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_wb.v +set_global_assignment -name VERILOG_FILE ../verilog/timescale.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_debug_if.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_defines.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_receiver.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_regs.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_rfifo.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_sync_flops.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_tfifo.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_top.v +set_global_assignment -name VERILOG_FILE ../verilog/uart_transmitter.v +set_global_assignment -name VERILOG_FILE ../verilog/raminfr.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_location_assignment PIN_K8 -to stxo_ +set_location_assignment PIN_AF15 -to clk_ +set_global_assignment -name ENABLE_CLOCK_LATENCY ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name DEVICE_MIGRATION_LIST "EP2S60F672C5ES,EP2S60F672C5" +set_location_assignment PIN_AD26 -to led_[7] +set_location_assignment PIN_AD25 -to led_[6] +set_location_assignment PIN_AC25 -to led_[5] +set_location_assignment PIN_AC24 -to led_[4] +set_location_assignment PIN_AB24 -to led_[3] +set_location_assignment PIN_AB23 -to led_[2] +set_location_assignment PIN_AB26 -to led_[1] +set_location_assignment PIN_AB25 -to led_[0] +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" \ No newline at end of file Index: trunk/uart16550/altera/altpll0.v =================================================================== --- trunk/uart16550/altera/altpll0.v (nonexistent) +++ trunk/uart16550/altera/altpll0.v (revision 2) @@ -0,0 +1,318 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: altpll0.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 7.1 Build 178 06/25/2007 SP 1 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2007 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module altpll0 ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [5:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b1), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 50000000, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1843199, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.gate_lock_counter = 100, + altpll_component.gate_lock_signal = "YES", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Stratix II", + altpll_component.invalid_lock_multiplier = 5, + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_enable0 = "PORT_UNUSED", + altpll_component.port_enable1 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.port_sclkout0 = "PORT_UNUSED", + altpll_component.port_sclkout1 = "PORT_UNUSED", + altpll_component.spread_frequency = 0, + altpll_component.valid_lock_multiplier = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "100" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "150.000" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.84320000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50000000" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1843199" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "100" +// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE FALSE +// Retrieval info: LIB_FILE: altera_mf Index: trunk/uart16550/altera/uart_test.v =================================================================== --- trunk/uart16550/altera/uart_test.v (nonexistent) +++ trunk/uart16550/altera/uart_test.v (revision 2) @@ -0,0 +1,189 @@ +`include "../verilog/uart_defines.v" + +module uart_test(clk_, stxo_, led_); + // Module IO ports + input clk_; + output stxo_; + output reg [7:0] led_; + + // Net declarations + wire clk, boot; + reg [4:0] wb_adr_i; + reg [31:0] wb_dat_i; + wire [31:0] wb_dat_o; + reg [3:0] wb_sel_i; + wire wb_ack_o; + reg wb_rst_i, wb_we_i, wb_stb_i, wb_cyc_i; + + // Module instantiations + uart_top uart_snd(clk, + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, + wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, /* int_o */, + stxo_,, + /* rts_o */, 1'b1, /* dtr_o */, 1'b1, 1'b1, 1'b1); + altpll0 pll0(clk_, clk, boot); + + always @(posedge clk) + if (~boot) + begin + led_ <= 8'd1; + wb_rst_i <= 1'b1; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_sel_i <= 4'hx; + wb_we_i <= 1'hx; + end + else + case (led_) + 8'd01: begin wb_rst_i <= 1'b0; led_ <= 8'd02; end + + // wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0}); + 8'd02: begin + wb_adr_i <= `UART_REG_LC; + wb_dat_i <= {8'b10011011, 24'b0}; + wb_cyc_i <= 1'b1; + wb_stb_i <= 1'b1; + wb_we_i <= 1'b1; + wb_sel_i <= 4'b1000; + led_ <= 8'd03; + end + 8'd03: if (wb_ack_o) + begin + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_we_i <= 1'hx; + wb_sel_i <= 4'hx; + led_ <= 8'd04; + end + + // set dl to divide by 3 + // wbm.wb_wr1(`UART_REG_DL1,4'b0001, 32'd2); + 8'd04: begin + wb_adr_i <= `UART_REG_DL1; + wb_dat_i <= 32'd3; + wb_cyc_i <= 1'b1; + wb_stb_i <= 1'b1; + wb_we_i <= 1'b1; + wb_sel_i <= 4'b0001; + led_ <= 8'd05; + end + 8'd05: if (wb_ack_o) + begin + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_we_i <= 1'hx; + wb_sel_i <= 4'hx; + led_ <= 8'd06; + end + + // restore normal registers + // wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0}); + 8'd06: begin + wb_adr_i <= `UART_REG_LC; + wb_dat_i <= {8'b00011011, 24'b0}; + wb_cyc_i <= 1'b1; + wb_stb_i <= 1'b1; + wb_we_i <= 1'b1; + wb_sel_i <= 4'b1000; + led_ <= 8'd07; + end + 8'd07: if (wb_ack_o) + begin + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_we_i <= 1'hx; + wb_sel_i <= 4'hx; + led_ <= 8'd08; + end + + // wb_wr1(5'd0, 4'b1, 32'b10000001); + 8'd08: begin + wb_adr_i <= 5'd0; + wb_dat_i <= 32'h5a; + wb_cyc_i <= 1'b1; + wb_stb_i <= 1'b1; + wb_we_i <= 1'b1; + wb_sel_i <= 4'b1; + led_ <= 8'd09; + end + 8'd09: if (wb_ack_o) + begin + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_we_i <= 1'hx; + wb_sel_i <= 4'hx; + led_ <= 8'd10; + end + + // wb_wr1(5'd0, 4'b1, 32'b01000010); + 8'd10: begin + wb_adr_i <= 5'd0; + wb_dat_i <= 32'h65; + wb_cyc_i <= 1'b1; + wb_stb_i <= 1'b1; + wb_we_i <= 1'b1; + wb_sel_i <= 4'b1; + led_ <= 8'd11; + end + 8'd11: if (wb_ack_o) + begin + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_we_i <= 1'hx; + wb_sel_i <= 4'hx; + led_ <= 8'd12; + end + + 8'd12: begin + wb_adr_i <= 5'd0; + wb_dat_i <= 32'h75; + wb_cyc_i <= 1'b1; + wb_stb_i <= 1'b1; + wb_we_i <= 1'b1; + wb_sel_i <= 4'b1; + led_ <= 8'd13; + end + 8'd13: if (wb_ack_o) + begin + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_we_i <= 1'hx; + wb_sel_i <= 4'hx; + led_ <= 8'd14; + end + 8'd14: begin + wb_adr_i <= 5'd0; + wb_dat_i <= 32'h73; + wb_cyc_i <= 1'b1; + wb_stb_i <= 1'b1; + wb_we_i <= 1'b1; + wb_sel_i <= 4'b1; + led_ <= 8'd15; + end + 8'd15: if (wb_ack_o) + begin + wb_cyc_i <= 1'b0; + wb_stb_i <= 1'b0; + wb_adr_i <= 5'bxxxxx; + wb_dat_i <= 32'hxxxx_xxxx; + wb_we_i <= 1'hx; + wb_sel_i <= 4'hx; + led_ <= 8'd16; + end + endcase + +endmodule \ No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.