URL
https://opencores.org/ocsvn/3des_vhdl/3des_vhdl/trunk
Subversion Repositories 3des_vhdl
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- ↔ Reverse comparison
Rev 1 → Rev 2
/trunk/VHDL/s5_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s5_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s5_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s5_box; |
|
architecture Behavioral of s5_box is |
|
begin |
|
SPO <= "0010" when A = x"0" else |
"1110" when A = x"1" else |
"1100" when A = x"2" else |
"1011" when A = x"3" else |
"0100" when A = x"4" else |
"0010" when A = x"5" else |
"0001" when A = x"6" else |
"1100" when A = x"7" else |
"0111" when A = x"8" else |
"0100" when A = x"9" else |
"1010" when A = x"A" else |
"0111" when A = x"B" else |
"1011" when A = x"C" else |
"1101" when A = x"D" else |
"0110" when A = x"E" else |
"0001" when A = x"F" else |
"1000" when A = x"10" else |
"0101" when A = x"11" else |
"0101" when A = x"12" else |
"0000" when A = x"13" else |
"0011" when A = x"14" else |
"1111" when A = x"15" else |
"1111" when A = x"16" else |
"1010" when A = x"17" else |
"1101" when A = x"18" else |
"0011" when A = x"19" else |
"0000" when A = x"1A" else |
"1001" when A = x"1B" else |
"1110" when A = x"1C" else |
"1000" when A = x"1D" else |
"1001" when A = x"1E" else |
"0110" when A = x"1F" else |
"0100" when A = x"20" else |
"1011" when A = x"21" else |
"0010" when A = x"22" else |
"1000" when A = x"23" else |
"0001" when A = x"24" else |
"1100" when A = x"25" else |
"1011" when A = x"26" else |
"0111" when A = x"27" else |
"1010" when A = x"28" else |
"0001" when A = x"29" else |
"1101" when A = x"2A" else |
"1110" when A = x"2B" else |
"0111" when A = x"2C" else |
"0010" when A = x"2D" else |
"1000" when A = x"2E" else |
"1101" when A = x"2F" else |
"1111" when A = x"30" else |
"0110" when A = x"31" else |
"1001" when A = x"32" else |
"1111" when A = x"33" else |
"1100" when A = x"34" else |
"0000" when A = x"35" else |
"0101" when A = x"36" else |
"1001" when A = x"37" else |
"0110" when A = x"38" else |
"1010" when A = x"39" else |
"0011" when A = x"3A" else |
"0100" when A = x"3B" else |
"0000" when A = x"3C" else |
"0101" when A = x"3D" else |
"1110" when A = x"3E" else |
"0011" when A = x"3F" else |
"0011"; |
|
END Behavioral; |
/trunk/VHDL/add_key.vhd
0,0 → 1,103
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : add_key |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity add_key is |
port( |
x0_in: in std_logic_vector(0 to 5); |
x1_in: in std_logic_vector(0 to 5); |
x2_in: in std_logic_vector(0 to 5); |
x3_in: in std_logic_vector(0 to 5); |
x4_in: in std_logic_vector(0 to 5); |
x5_in: in std_logic_vector(0 to 5); |
x6_in: in std_logic_vector(0 to 5); |
x7_in: in std_logic_vector(0 to 5); |
key: in std_logic_vector(0 to 47); |
x0_out: out std_logic_vector(5 downto 0); |
x1_out: out std_logic_vector(5 downto 0); |
x2_out: out std_logic_vector(5 downto 0); |
x3_out: out std_logic_vector(5 downto 0); |
x4_out: out std_logic_vector(5 downto 0); |
x5_out: out std_logic_vector(5 downto 0); |
x6_out: out std_logic_vector(5 downto 0); |
x7_out: out std_logic_vector(5 downto 0) |
); |
end add_key; |
|
|
architecture Behavioral of add_key is |
begin |
|
x0_out <= x0_in xor key(0 to 5); |
x1_out <= x1_in xor key(6 to 11); |
x2_out <= x2_in xor key(12 to 17); |
x3_out <= x3_in xor key(18 to 23); |
x4_out <= x4_in xor key(24 to 29); |
x5_out <= x5_in xor key(30 to 35); |
x6_out <= x6_in xor key(36 to 41); |
x7_out <= x7_in xor key(42 to 47); |
|
end Behavioral; |
/trunk/VHDL/s6_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s6_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s6_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s6_box; |
|
architecture Behavioral of s6_box is |
|
begin |
|
SPO <= "1100" when A = x"0" else |
"1010" when A = x"1" else |
"0001" when A = x"2" else |
"1111" when A = x"3" else |
"1010" when A = x"4" else |
"0100" when A = x"5" else |
"1111" when A = x"6" else |
"0010" when A = x"7" else |
"1001" when A = x"8" else |
"0111" when A = x"9" else |
"0010" when A = x"A" else |
"1100" when A = x"B" else |
"0110" when A = x"C" else |
"1001" when A = x"D" else |
"1000" when A = x"E" else |
"0101" when A = x"F" else |
"0000" when A = x"10" else |
"0110" when A = x"11" else |
"1101" when A = x"12" else |
"0001" when A = x"13" else |
"0011" when A = x"14" else |
"1101" when A = x"15" else |
"0100" when A = x"16" else |
"1110" when A = x"17" else |
"1110" when A = x"18" else |
"0000" when A = x"19" else |
"0111" when A = x"1A" else |
"1011" when A = x"1B" else |
"0101" when A = x"1C" else |
"0011" when A = x"1D" else |
"1011" when A = x"1E" else |
"1000" when A = x"1F" else |
"1001" when A = x"20" else |
"0100" when A = x"21" else |
"1110" when A = x"22" else |
"0011" when A = x"23" else |
"1111" when A = x"24" else |
"0010" when A = x"25" else |
"0101" when A = x"26" else |
"1100" when A = x"27" else |
"0010" when A = x"28" else |
"1001" when A = x"29" else |
"1000" when A = x"2A" else |
"0101" when A = x"2B" else |
"1100" when A = x"2C" else |
"1111" when A = x"2D" else |
"0011" when A = x"2E" else |
"1010" when A = x"2F" else |
"0111" when A = x"30" else |
"1011" when A = x"31" else |
"0000" when A = x"32" else |
"1110" when A = x"33" else |
"0100" when A = x"34" else |
"0001" when A = x"35" else |
"1010" when A = x"36" else |
"0111" when A = x"37" else |
"0001" when A = x"38" else |
"0110" when A = x"39" else |
"1101" when A = x"3A" else |
"0000" when A = x"3B" else |
"1011" when A = x"3C" else |
"1000" when A = x"3D" else |
"0110" when A = x"3E" else |
"1101" when A = x"3F" else |
"1101"; |
|
END Behavioral; |
/trunk/VHDL/s7_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s7_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s7_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s7_box; |
|
architecture Behavioral of s7_box is |
|
begin |
|
SPO <= "0100" when A = x"0" else |
"1101" when A = x"1" else |
"1011" when A = x"2" else |
"0000" when A = x"3" else |
"0010" when A = x"4" else |
"1011" when A = x"5" else |
"1110" when A = x"6" else |
"0111" when A = x"7" else |
"1111" when A = x"8" else |
"0100" when A = x"9" else |
"0000" when A = x"A" else |
"1001" when A = x"B" else |
"1000" when A = x"C" else |
"0001" when A = x"D" else |
"1101" when A = x"E" else |
"1010" when A = x"F" else |
"0011" when A = x"10" else |
"1110" when A = x"11" else |
"1100" when A = x"12" else |
"0011" when A = x"13" else |
"1001" when A = x"14" else |
"0101" when A = x"15" else |
"0111" when A = x"16" else |
"1100" when A = x"17" else |
"0101" when A = x"18" else |
"0010" when A = x"19" else |
"1010" when A = x"1A" else |
"1111" when A = x"1B" else |
"0110" when A = x"1C" else |
"1000" when A = x"1D" else |
"0001" when A = x"1E" else |
"0110" when A = x"1F" else |
"0001" when A = x"20" else |
"0110" when A = x"21" else |
"0100" when A = x"22" else |
"1011" when A = x"23" else |
"1011" when A = x"24" else |
"1101" when A = x"25" else |
"1101" when A = x"26" else |
"1000" when A = x"27" else |
"1100" when A = x"28" else |
"0001" when A = x"29" else |
"0011" when A = x"2A" else |
"0100" when A = x"2B" else |
"0111" when A = x"2C" else |
"1010" when A = x"2D" else |
"1110" when A = x"2E" else |
"0111" when A = x"2F" else |
"1010" when A = x"30" else |
"1001" when A = x"31" else |
"1111" when A = x"32" else |
"0101" when A = x"33" else |
"0110" when A = x"34" else |
"0000" when A = x"35" else |
"1000" when A = x"36" else |
"1111" when A = x"37" else |
"0000" when A = x"38" else |
"1110" when A = x"39" else |
"0101" when A = x"3A" else |
"0010" when A = x"3B" else |
"1001" when A = x"3C" else |
"0011" when A = x"3D" else |
"0010" when A = x"3E" else |
"1100" when A = x"3F" else |
"1100"; |
|
END Behavioral; |
/trunk/VHDL/add_left.vhd
0,0 → 1,82
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : add_left |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity add_left is |
port( |
x_in: in std_logic_vector(0 to 31); |
left_in: in std_logic_vector(0 to 31); |
x_out: out std_logic_vector(0 to 31) |
); |
end add_left; |
|
architecture Behavioral of add_left is |
|
begin |
|
x_out <= x_in xor left_in; |
|
end Behavioral; |
/trunk/VHDL/s8_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s8_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s8_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s8_box; |
|
architecture Behavioral of s8_box is |
|
begin |
|
SPO <= "1101" when A = x"0" else |
"0001" when A = x"1" else |
"0010" when A = x"2" else |
"1111" when A = x"3" else |
"1000" when A = x"4" else |
"1101" when A = x"5" else |
"0100" when A = x"6" else |
"1000" when A = x"7" else |
"0110" when A = x"8" else |
"1010" when A = x"9" else |
"1111" when A = x"A" else |
"0011" when A = x"B" else |
"1011" when A = x"C" else |
"0111" when A = x"D" else |
"0001" when A = x"E" else |
"0100" when A = x"F" else |
"1010" when A = x"10" else |
"1100" when A = x"11" else |
"1001" when A = x"12" else |
"0101" when A = x"13" else |
"0011" when A = x"14" else |
"0110" when A = x"15" else |
"1110" when A = x"16" else |
"1011" when A = x"17" else |
"0101" when A = x"18" else |
"0000" when A = x"19" else |
"0000" when A = x"1A" else |
"1110" when A = x"1B" else |
"1100" when A = x"1C" else |
"1001" when A = x"1D" else |
"0111" when A = x"1E" else |
"0010" when A = x"1F" else |
"0111" when A = x"20" else |
"0010" when A = x"21" else |
"1011" when A = x"22" else |
"0001" when A = x"23" else |
"0100" when A = x"24" else |
"1110" when A = x"25" else |
"0001" when A = x"26" else |
"0111" when A = x"27" else |
"1001" when A = x"28" else |
"0100" when A = x"29" else |
"1100" when A = x"2A" else |
"1010" when A = x"2B" else |
"1110" when A = x"2C" else |
"1000" when A = x"2D" else |
"0010" when A = x"2E" else |
"1101" when A = x"2F" else |
"0000" when A = x"30" else |
"1111" when A = x"31" else |
"0110" when A = x"32" else |
"1100" when A = x"33" else |
"1010" when A = x"34" else |
"1001" when A = x"35" else |
"1101" when A = x"36" else |
"0000" when A = x"37" else |
"1111" when A = x"38" else |
"0011" when A = x"39" else |
"0011" when A = x"3A" else |
"0101" when A = x"3B" else |
"0101" when A = x"3C" else |
"0110" when A = x"3D" else |
"1000" when A = x"3E" else |
"1011" when A = x"3F" else |
"1011"; |
|
END Behavioral; |
/trunk/VHDL/key_schedule.vhd
0,0 → 1,256
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : key_schedule |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity key_schedule is |
port ( |
|
key_in: in std_logic_vector(0 to 63); -- key to be expanded |
|
-- interface signals for communication with DES |
KeySelect: in std_logic_vector(3 downto 0); -- selector for key |
key_out: out std_logic_vector(0 to 47); -- expaned key output |
key_ready: out std_logic; -- signal for DES that key has been expanded |
|
reset: in std_logic; -- reset |
clock: in std_logic -- master clock |
); |
end key_schedule; |
|
architecture Behavioral of key_schedule is |
|
-- |
-- Storage for expanded key |
-- |
signal K16, K1: std_logic_vector(0 to 47); |
signal K2, K3: std_logic_vector(0 to 47); |
signal K4, K5: std_logic_vector(0 to 47); |
signal K6, K7: std_logic_vector(0 to 47); |
signal K8, K9: std_logic_vector(0 to 47); |
signal K10, K11: std_logic_vector(0 to 47); |
signal K12, K13: std_logic_vector(0 to 47); |
signal K14, K15: std_logic_vector(0 to 47); |
|
begin |
|
|
-- |
-- Selector for expaned key |
-- |
key_out <= K1 when KeySelect = x"0" else |
K2 when KeySelect = x"1" else |
K3 when KeySelect = x"2" else |
K4 when KeySelect = x"3" else |
K5 when KeySelect = x"4" else |
K6 when KeySelect = x"5" else |
K7 when KeySelect = x"6" else |
K8 when KeySelect = x"7" else |
K9 when KeySelect = x"8" else |
K10 when KeySelect = x"9" else |
K11 when KeySelect = x"A" else |
K12 when KeySelect = x"B" else |
K13 when KeySelect = x"C" else |
K14 when KeySelect = x"D" else |
K15 when KeySelect = x"E" else |
K16; |
|
process (clock) |
begin |
|
-- |
-- input key will expaned and stored after rising edge of the first clock after mater reset. |
-- the keys are captured at a triple-des level |
-- |
if rising_edge(clock) then |
|
if reset = '1' then |
key_ready <= '0'; |
else |
|
-- |
-- key expansion from the input key |
-- |
K1 <= key_in(9) & key_in(50) & key_in(33) & key_in(59) & key_in(48) & key_in(16) & key_in(32) & key_in(56) & |
key_in(1) & key_in(8) & key_in(18) & key_in(41) & key_in(2) & key_in(34) & key_in(25) & key_in(24) & |
key_in(43) & key_in(57) & key_in(58) & key_in(0) & key_in(35) & key_in(26) & key_in(17) & key_in(40) & |
key_in(21) & key_in(27) & key_in(38) & key_in(53) & key_in(36) & key_in(3) & key_in(46) & key_in(29) & |
key_in(4) & key_in(52) & key_in(22) & key_in(28) & key_in(60) & key_in(20) & key_in(37) & key_in(62) & |
key_in(14) & key_in(19) & key_in(44) & key_in(13) & key_in(12) & key_in(61) & key_in(54) & key_in(30); |
|
K2 <= key_in(1) & key_in(42) & key_in(25) & key_in(51) & key_in(40) & key_in(8) & key_in(24) & key_in(48) & |
key_in(58) & key_in(0) & key_in(10) & key_in(33) & key_in(59) & key_in(26) & key_in(17) & key_in(16) & |
key_in(35) & key_in(49) & key_in(50) & key_in(57) & key_in(56) & key_in(18) & key_in(9) & key_in(32) & |
key_in(13) & key_in(19) & key_in(30) & key_in(45) & key_in(28) & key_in(62) & key_in(38) & key_in(21) & |
key_in(27) & key_in(44) & key_in(14) & key_in(20) & key_in(52) & key_in(12) & key_in(29) & key_in(54) & |
key_in(6) & key_in(11) & key_in(36) & key_in(5) & key_in(4) & key_in(53) & key_in(46) & key_in(22); |
|
K3 <= key_in(50) & key_in(26) & key_in(9) & key_in(35) & key_in(24) & key_in(57) & key_in(8) & key_in(32) & |
key_in(42) & key_in(49) & key_in(59) & key_in(17) & key_in(43) & key_in(10) & key_in(1) & key_in(0) & |
key_in(48) & key_in(33) & key_in(34) & key_in(41) & key_in(40) & key_in(2) & key_in(58) & key_in(16) & |
key_in(60) & key_in(3) & key_in(14) & key_in(29) & key_in(12) & key_in(46) & key_in(22) & key_in(5) & |
key_in(11) & key_in(28) & key_in(61) & key_in(4) & key_in(36) & key_in(27) & key_in(13) & key_in(38) & |
key_in(53) & key_in(62) & key_in(20) & key_in(52) & key_in(19) & key_in(37) & key_in(30) & key_in(6); |
|
K4 <= key_in(34) & key_in(10) & key_in(58) & key_in(48) & key_in(8) & key_in(41) & key_in(57) & key_in(16) & |
key_in(26) & key_in(33) & key_in(43) & key_in(1) & key_in(56) & key_in(59) & key_in(50) & key_in(49) & |
key_in(32) & key_in(17) & key_in(18) & key_in(25) & key_in(24) & key_in(51) & key_in(42) & key_in(0) & |
key_in(44) & key_in(54) & key_in(61) & key_in(13) & key_in(27) & key_in(30) & key_in(6) & key_in(52) & |
key_in(62) & key_in(12) & key_in(45) & key_in(19) & key_in(20) & key_in(11) & key_in(60) & key_in(22) & |
key_in(37) & key_in(46) & key_in(4) & key_in(36) & key_in(3) & key_in(21) & key_in(14) & key_in(53); |
|
K5 <= key_in(18) & key_in(59) & key_in(42) & key_in(32) & key_in(57) & key_in(25) & key_in(41) & key_in(0) & |
key_in(10) & key_in(17) & key_in(56) & key_in(50) & key_in(40) & key_in(43) & key_in(34) & key_in(33) & |
key_in(16) & key_in(1) & key_in(2) & key_in(9) & key_in(8) & key_in(35) & key_in(26) & key_in(49) & |
key_in(28) & key_in(38) & key_in(45) & key_in(60) & key_in(11) & key_in(14) & key_in(53) & key_in(36) & |
key_in(46) & key_in(27) & key_in(29) & key_in(3) & key_in(4) & key_in(62) & key_in(44) & key_in(6) & |
key_in(21) & key_in(30) & key_in(19) & key_in(20) & key_in(54) & key_in(5) & key_in(61) & key_in(37); |
|
K6 <= key_in(2) & key_in(43) & key_in(26) & key_in(16) & key_in(41) & key_in(9) & key_in(25) & key_in(49) & |
key_in(59) & key_in(1) & key_in(40) & key_in(34) & key_in(24) & key_in(56) & key_in(18) & key_in(17) & |
key_in(0) & key_in(50) & key_in(51) & key_in(58) & key_in(57) & key_in(48) & key_in(10) & key_in(33) & |
key_in(12) & key_in(22) & key_in(29) & key_in(44) & key_in(62) & key_in(61) & key_in(37) & key_in(20) & |
key_in(30) & key_in(11) & key_in(13) & key_in(54) & key_in(19) & key_in(46) & key_in(28) & key_in(53) & |
key_in(5) & key_in(14) & key_in(3) & key_in(4) & key_in(38) & key_in(52) & key_in(45) & key_in(21); |
|
K7 <= key_in(51) & key_in(56) & key_in(10) & key_in(0) & key_in(25) & key_in(58) & key_in(9) & key_in(33) & |
key_in(43) & key_in(50) & key_in(24) & key_in(18) & key_in(8) & key_in(40) & key_in(2) & key_in(1) & |
key_in(49) & key_in(34) & key_in(35) & key_in(42) & key_in(41) & key_in(32) & key_in(59) & key_in(17) & |
key_in(27) & key_in(6) & key_in(13) & key_in(28) & key_in(46) & key_in(45) & key_in(21) & key_in(4) & |
key_in(14) & key_in(62) & key_in(60) & key_in(38) & key_in(3) & key_in(30) & key_in(12) & key_in(37) & |
key_in(52) & key_in(61) & key_in(54) & key_in(19) & key_in(22) & key_in(36) & key_in(29) & key_in(5); |
|
K8 <= key_in(35) & key_in(40) & key_in(59) & key_in(49) & key_in(9) & key_in(42) & key_in(58) & key_in(17) & |
key_in(56) & key_in(34) & key_in(8) & key_in(2) & key_in(57) & key_in(24) & key_in(51) & key_in(50) & |
key_in(33) & key_in(18) & key_in(48) & key_in(26) & key_in(25) & key_in(16) & key_in(43) & key_in(1) & |
key_in(11) & key_in(53) & key_in(60) & key_in(12) & key_in(30) & key_in(29) & key_in(5) & key_in(19) & |
key_in(61) & key_in(46) & key_in(44) & key_in(22) & key_in(54) & key_in(14) & key_in(27) & key_in(21) & |
key_in(36) & key_in(45) & key_in(38) & key_in(3) & key_in(6) & key_in(20) & key_in(13) & key_in(52); |
|
K9 <= key_in(56) & key_in(32) & key_in(51) & key_in(41) & key_in(1) & key_in(34) & key_in(50) & key_in(9) & |
key_in(48) & key_in(26) & key_in(0) & key_in(59) & key_in(49) & key_in(16) & key_in(43) & key_in(42) & |
key_in(25) & key_in(10) & key_in(40) & key_in(18) & key_in(17) & key_in(8) & key_in(35) & key_in(58) & |
key_in(3) & key_in(45) & key_in(52) & key_in(4) & key_in(22) & key_in(21) & key_in(60) & key_in(11) & |
key_in(53) & key_in(38) & key_in(36) & key_in(14) & key_in(46) & key_in(6) & key_in(19) & key_in(13) & |
key_in(28) & key_in(37) & key_in(30) & key_in(62) & key_in(61) & key_in(12) & key_in(5) & key_in(44); |
|
K10 <= key_in(40) & key_in(16) & key_in(35) & key_in(25) & key_in(50) & key_in(18) & key_in(34) & key_in(58) & |
key_in(32) & key_in(10) & key_in(49) & key_in(43) & key_in(33) & key_in(0) & key_in(56) & key_in(26) & |
key_in(9) & key_in(59) & key_in(24) & key_in(2) & key_in(1) & key_in(57) & key_in(48) & key_in(42) & |
key_in(54) & key_in(29) & key_in(36) & key_in(19) & key_in(6) & key_in(5) & key_in(44) & key_in(62) & |
key_in(37) & key_in(22) & key_in(20) & key_in(61) & key_in(30) & key_in(53) & key_in(3) & key_in(60) & |
key_in(12) & key_in(21) & key_in(14) & key_in(46) & key_in(45) & key_in(27) & key_in(52) & key_in(28); |
|
K11 <= key_in(24) & key_in(0) & key_in(48) & key_in(9) & key_in(34) & key_in(2) & key_in(18) & key_in(42) & |
key_in(16) & key_in(59) & key_in(33) & key_in(56) & key_in(17) & key_in(49) & key_in(40) & key_in(10) & |
key_in(58) & key_in(43) & key_in(8) & key_in(51) & key_in(50) & key_in(41) & key_in(32) & key_in(26) & |
key_in(38) & key_in(13) & key_in(20) & key_in(3) & key_in(53) & key_in(52) & key_in(28) & key_in(46) & |
key_in(21) & key_in(6) & key_in(4) & key_in(45) & key_in(14) & key_in(37) & key_in(54) & key_in(44) & |
key_in(27) & key_in(5) & key_in(61) & key_in(30) & key_in(29) & key_in(11) & key_in(36) & key_in(12); |
|
K12 <= key_in(8) & key_in(49) & key_in(32) & key_in(58) & key_in(18) & key_in(51) & key_in(2) & key_in(26) & |
key_in(0) & key_in(43) & key_in(17) & key_in(40) & key_in(1) & key_in(33) & key_in(24) & key_in(59) & |
key_in(42) & key_in(56) & key_in(57) & key_in(35) & key_in(34) & key_in(25) & key_in(16) & key_in(10) & |
key_in(22) & key_in(60) & key_in(4) & key_in(54) & key_in(37) & key_in(36) & key_in(12) & key_in(30) & |
key_in(5) & key_in(53) & key_in(19) & key_in(29) & key_in(61) & key_in(21) & key_in(38) & key_in(28) & |
key_in(11) & key_in(52) & key_in(45) & key_in(14) & key_in(13) & key_in(62) & key_in(20) & key_in(27); |
|
K13 <= key_in(57) & key_in(33) & key_in(16) & key_in(42) & key_in(2) & key_in(35) & key_in(51) & key_in(10) & |
key_in(49) & key_in(56) & key_in(1) & key_in(24) & key_in(50) & key_in(17) & key_in(8) & key_in(43) & |
key_in(26) & key_in(40) & key_in(41) & key_in(48) & key_in(18) & key_in(9) & key_in(0) & key_in(59) & |
key_in(6) & key_in(44) & key_in(19) & key_in(38) & key_in(21) & key_in(20) & key_in(27) & key_in(14) & |
key_in(52) & key_in(37) & key_in(3) & key_in(13) & key_in(45) & key_in(5) & key_in(22) & key_in(12) & |
key_in(62) & key_in(36) & key_in(29) & key_in(61) & key_in(60) & key_in(46) & key_in(4) & key_in(11); |
|
K14 <= key_in(41) & key_in(17) & key_in(0) & key_in(26) & key_in(51) & key_in(48) & key_in(35) & key_in(59) & |
key_in(33) & key_in(40) & key_in(50) & key_in(8) & key_in(34) & key_in(1) & key_in(57) & key_in(56) & |
key_in(10) & key_in(24) & key_in(25) & key_in(32) & key_in(2) & key_in(58) & key_in(49) & key_in(43) & |
key_in(53) & key_in(28) & key_in(3) & key_in(22) & key_in(5) & key_in(4) & key_in(11) & key_in(61) & |
key_in(36) & key_in(21) & key_in(54) & key_in(60) & key_in(29) & key_in(52) & key_in(6) & key_in(27) & |
key_in(46) & key_in(20) & key_in(13) & key_in(45) & key_in(44) & key_in(30) & key_in(19) & key_in(62); |
|
K15 <= key_in(25) & key_in(1) & key_in(49) & key_in(10) & key_in(35) & key_in(32) & key_in(48) & key_in(43) & |
key_in(17) & key_in(24) & key_in(34) & key_in(57) & key_in(18) & key_in(50) & key_in(41) & key_in(40) & |
key_in(59) & key_in(8) & key_in(9) & key_in(16) & key_in(51) & key_in(42) & key_in(33) & key_in(56) & |
key_in(37) & key_in(12) & key_in(54) & key_in(6) & key_in(52) & key_in(19) & key_in(62) & key_in(45) & |
key_in(20) & key_in(5) & key_in(38) & key_in(44) & key_in(13) & key_in(36) & key_in(53) & key_in(11) & |
key_in(30) & key_in(4) & key_in(60) & key_in(29) & key_in(28) & key_in(14) & key_in(3) & key_in(46); |
|
K16 <= key_in(17) & key_in(58) & key_in(41) & key_in(2) & key_in(56) & key_in(24) & key_in(40) & key_in(35) & |
key_in(9) & key_in(16) & key_in(26) & key_in(49) & key_in(10) & key_in(42) & key_in(33) & key_in(32) & |
key_in(51) & key_in(0) & key_in(1) & key_in(8) & key_in(43) & key_in(34) & key_in(25) & key_in(48) & |
key_in(29) & key_in(4) & key_in(46) & key_in(61) & key_in(44) & key_in(11) & key_in(54) & key_in(37) & |
key_in(12) & key_in(60) & key_in(30) & key_in(36) & key_in(5) & key_in(28) & key_in(45) & key_in(3) & |
key_in(22) & key_in(27) & key_in(52) & key_in(21) & key_in(20) & key_in(6) & key_in(62) & key_in(38); |
|
key_ready <= '1'; |
|
end if; |
|
end if; |
end process; |
|
|
end Behavioral; |
/trunk/VHDL/p_box.vhd
0,0 → 1,96
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : p_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity p_box is |
port( |
x0_in: in std_logic_vector(3 downto 0); |
x1_in: in std_logic_vector(3 downto 0); |
x2_in: in std_logic_vector(3 downto 0); |
x3_in: in std_logic_vector(3 downto 0); |
x4_in: in std_logic_vector(3 downto 0); |
x5_in: in std_logic_vector(3 downto 0); |
x6_in: in std_logic_vector(3 downto 0); |
x7_in: in std_logic_vector(3 downto 0); |
x_out: out std_logic_vector(0 to 31) |
); |
end p_box; |
|
architecture Behavioral of p_box is |
|
signal x_in: std_logic_vector(0 to 31); |
|
begin |
|
x_in <= x0_in & x1_in & x2_in & x3_in & x4_in & x5_in & x6_in & x7_in; |
x_out <= x_in(15) & x_in(6) & x_in(19) & x_in(20) & x_in(28) & x_in(11) & |
x_in(27) & x_in(16) & x_in(0) & x_in(14) & x_in(22) & x_in(25) & |
x_in(4) & x_in(17) & x_in(30) & x_in(9) & x_in(1) & x_in(7) & |
x_in(23) & x_in(13) & x_in(31) & x_in(26) & x_in(2) & x_in(8) & |
x_in(18) & x_in(12) & x_in(29) & x_in(5) & x_in(21) & x_in(10) & |
x_in(3) & x_in(24); |
|
end Behavioral; |
/trunk/VHDL/s_box.vhd
0,0 → 1,197
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity s_box is |
port( |
block0_in: in std_logic_vector(5 downto 0); |
block1_in: in std_logic_vector(5 downto 0); |
block2_in: in std_logic_vector(5 downto 0); |
block3_in: in std_logic_vector(5 downto 0); |
block4_in: in std_logic_vector(5 downto 0); |
block5_in: in std_logic_vector(5 downto 0); |
block6_in: in std_logic_vector(5 downto 0); |
block7_in: in std_logic_vector(5 downto 0); |
x0_out: out std_logic_vector(3 downto 0); |
x1_out: out std_logic_vector(3 downto 0); |
x2_out: out std_logic_vector(3 downto 0); |
x3_out: out std_logic_vector(3 downto 0); |
x4_out: out std_logic_vector(3 downto 0); |
x5_out: out std_logic_vector(3 downto 0); |
x6_out: out std_logic_vector(3 downto 0); |
x7_out: out std_logic_vector(3 downto 0) |
); |
end s_box; |
|
architecture Behavioral of s_box is |
|
component s1_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
component s2_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
component s3_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
component s4_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
component s5_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
component s6_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
component s7_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
component s8_box |
port( |
a: in std_logic_VECTOR(5 downto 0); |
spo: out std_logic_VECTOR(3 downto 0) |
); |
end component; |
|
begin |
|
S1 : s1_box |
port map ( |
a => block0_in, |
spo => x0_out |
); |
|
S2 : s2_box |
port map ( |
a => block1_in, |
spo => x1_out |
); |
|
S3 : s3_box |
port map ( |
a => block2_in, |
spo => x2_out |
); |
|
S4 : s4_box |
port map ( |
a => block3_in, |
spo => x3_out |
); |
|
S5 : s5_box |
port map ( |
a => block4_in, |
spo => x4_out |
); |
|
S6 : s6_box |
port map ( |
a => block5_in, |
spo => x5_out |
); |
|
S7 : s7_box |
port map ( |
a => block6_in, |
spo => x6_out |
); |
|
S8 : s8_box |
port map ( |
a => block7_in, |
spo => x7_out |
); |
|
end Behavioral; |
/trunk/VHDL/block_top.vhd
0,0 → 1,295
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : block_top |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity block_top is |
port( |
-- |
-- input into top level block |
-- |
L_in: in std_logic_vector(0 to 31); |
R_in: in std_logic_vector(0 to 31); |
|
-- |
-- output from top level block |
-- |
L_out: out std_logic_vector(0 to 31); |
R_out: out std_logic_vector(0 to 31); |
|
-- |
-- expanded key from key block |
-- |
round_key_des: in std_logic_vector(0 to 47) -- current round key |
|
); |
end block_top; |
|
architecture Behavioral of block_top is |
-- |
-- DECLARATION OF MODULES IN THE BLOCK_TOP |
-- |
|
-- |
-- E _ E X P A N S I O N _ F U N C T I O N |
-- |
component e_expansion_function |
port( |
x_in: in std_logic_vector(0 to 31); |
block0_out: out std_logic_vector(0 to 5); |
block1_out: out std_logic_vector(0 to 5); |
block2_out: out std_logic_vector(0 to 5); |
block3_out: out std_logic_vector(0 to 5); |
block4_out: out std_logic_vector(0 to 5); |
block5_out: out std_logic_vector(0 to 5); |
block6_out: out std_logic_vector(0 to 5); |
block7_out: out std_logic_vector(0 to 5) |
); |
end component; |
|
-- |
-- A D D _ K E Y |
-- |
component add_key |
port( |
x0_in: in std_logic_vector(0 to 5); |
x1_in: in std_logic_vector(0 to 5); |
x2_in: in std_logic_vector(0 to 5); |
x3_in: in std_logic_vector(0 to 5); |
x4_in: in std_logic_vector(0 to 5); |
x5_in: in std_logic_vector(0 to 5); |
x6_in: in std_logic_vector(0 to 5); |
x7_in: in std_logic_vector(0 to 5); |
key: in std_logic_vector(0 to 47); |
x0_out: out std_logic_vector(5 downto 0); |
x1_out: out std_logic_vector(5 downto 0); |
x2_out: out std_logic_vector(5 downto 0); |
x3_out: out std_logic_vector(5 downto 0); |
x4_out: out std_logic_vector(5 downto 0); |
x5_out: out std_logic_vector(5 downto 0); |
x6_out: out std_logic_vector(5 downto 0); |
x7_out: out std_logic_vector(5 downto 0) |
); |
end component; |
|
-- |
-- S _ B O X |
-- |
component s_box |
port( |
block0_in: in std_logic_vector(5 downto 0); |
block1_in: in std_logic_vector(5 downto 0); |
block2_in: in std_logic_vector(5 downto 0); |
block3_in: in std_logic_vector(5 downto 0); |
block4_in: in std_logic_vector(5 downto 0); |
block5_in: in std_logic_vector(5 downto 0); |
block6_in: in std_logic_vector(5 downto 0); |
block7_in: in std_logic_vector(5 downto 0); |
x0_out: out std_logic_vector(3 downto 0); |
x1_out: out std_logic_vector(3 downto 0); |
x2_out: out std_logic_vector(3 downto 0); |
x3_out: out std_logic_vector(3 downto 0); |
x4_out: out std_logic_vector(3 downto 0); |
x5_out: out std_logic_vector(3 downto 0); |
x6_out: out std_logic_vector(3 downto 0); |
x7_out: out std_logic_vector(3 downto 0) |
); |
end component; |
|
-- |
-- P _ B O X |
-- |
component p_box |
port( |
x0_in: in std_logic_vector(3 downto 0); |
x1_in: in std_logic_vector(3 downto 0); |
x2_in: in std_logic_vector(3 downto 0); |
x3_in: in std_logic_vector(3 downto 0); |
x4_in: in std_logic_vector(3 downto 0); |
x5_in: in std_logic_vector(3 downto 0); |
x6_in: in std_logic_vector(3 downto 0); |
x7_in: in std_logic_vector(3 downto 0); |
x_out: out std_logic_vector(0 to 31) |
); |
end component; |
|
-- |
-- A D D _ L E F T |
-- |
component add_left |
port( |
x_in: in std_logic_vector(0 to 31); |
left_in: in std_logic_vector(0 to 31); |
x_out: out std_logic_vector(0 to 31) |
); |
end component; |
|
|
-- |
-- Signals that connects modules within block_top |
-- |
signal a0, a1, a2, a3, a4, a5, a6, a7: std_logic_vector(0 to 5); |
signal b0, b1, b2, b3, b4, b5, b6, b7: std_logic_vector(5 downto 0); |
signal c0, c1, c2, c3, c4, c5, c6, c7: std_logic_vector(3 downto 0); |
signal d0: std_logic_vector(0 to 31); |
signal R_out_internal: std_logic_vector(0 to 31); |
|
begin |
|
L_out <= R_in; |
R_out <= R_out_internal; |
|
-- |
-- INSTANTIATION OF E_EXPANSIONFUNCTION |
-- |
E_EXPANSIONFUNCTION : e_expansion_function |
port map ( |
x_in => R_in, |
block0_out => a0, |
block1_out => a1, |
block2_out => a2, |
block3_out => a3, |
block4_out => a4, |
block5_out => a5, |
block6_out => a6, |
block7_out => a7 |
); |
|
-- |
-- INSTANTIATION OF ADDKEY |
-- |
ADDKEY : add_key |
port map ( |
x0_in => a0, |
x1_in => a1, |
x2_in => a2, |
x3_in => a3, |
x4_in => a4, |
x5_in => a5, |
x6_in => a6, |
x7_in => a7, |
key => round_key_des, |
x0_out => b0, |
x1_out => b1, |
x2_out => b2, |
x3_out => b3, |
x4_out => b4, |
x5_out => b5, |
x6_out => b6, |
x7_out => b7 |
); |
|
-- |
-- INSTANTIATION OF SBOX |
-- |
SBOX : s_box |
port map ( |
block0_in => b0, |
block1_in => b1, |
block2_in => b2, |
block3_in => b3, |
block4_in => b4, |
block5_in => b5, |
block6_in => b6, |
block7_in => b7, |
x0_out => c0, |
x1_out => c1, |
x2_out => c2, |
x3_out => c3, |
x4_out => c4, |
x5_out => c5, |
x6_out => c6, |
x7_out => c7 |
); |
|
-- |
-- INSTANTIATION OF PBOX |
-- |
PBOX : p_box |
port map ( |
x0_in => c0, |
x1_in => c1, |
x2_in => c2, |
x3_in => c3, |
x4_in => c4, |
x5_in => c5, |
x6_in => c6, |
x7_in => c7, |
x_out => d0 |
); |
|
|
-- |
-- INSTANTIATION OF ADDLEFT |
-- |
ADDLEFT : add_left |
port map ( |
x_in => d0, |
left_in => L_in, |
x_out => R_out_internal |
); |
|
|
end Behavioral; |
/trunk/VHDL/e_expansion_function.vhd
0,0 → 1,95
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : e_expansion_function |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity e_expansion_function is |
port( |
x_in: in std_logic_vector(0 to 31); |
block0_out: out std_logic_vector(0 to 5); |
block1_out: out std_logic_vector(0 to 5); |
block2_out: out std_logic_vector(0 to 5); |
block3_out: out std_logic_vector(0 to 5); |
block4_out: out std_logic_vector(0 to 5); |
block5_out: out std_logic_vector(0 to 5); |
block6_out: out std_logic_vector(0 to 5); |
block7_out: out std_logic_vector(0 to 5) |
); |
end e_expansion_function; |
|
architecture Behavioral of e_expansion_function is |
|
begin |
|
block0_out <= x_in(31) & x_in(0) & x_in(1) & x_in(2) & x_in(3) & x_in(4); |
block1_out <= x_in(3) & x_in(4) & x_in(5) & x_in(6) & x_in(7) & x_in(8); |
block2_out <= x_in(7) & x_in(8) & x_in(9) & x_in(10) & x_in(11) & x_in(12); |
block3_out <= x_in(11) & x_in(12) & x_in(13) & x_in(14) & x_in(15) & x_in(16); |
block4_out <= x_in(15) & x_in(16) & x_in(17) & x_in(18) & x_in(19) & x_in(20); |
block5_out <= x_in(19) & x_in(20) & x_in(21) & x_in(22) & x_in(23) & x_in(24); |
block6_out <= x_in(23) & x_in(24) & x_in(25) & x_in(26) & x_in(27) & x_in(28); |
block7_out <= x_in(27) & x_in(28) & x_in(29) & x_in(30) & x_in(31) & x_in(0); |
|
end Behavioral; |
/trunk/VHDL/tdes_top.vhd
0,0 → 1,269
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
---------------------------------------------------------------------- |
-- |
-- Title : tdes_top |
-- Company : CoreTex Systems, LLC |
-- |
---------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity tdes_top is |
port( |
-- |
-- inputs for key expander |
-- |
key1_in: in std_logic_vector(0 to 63); |
key2_in: in std_logic_vector(0 to 63); |
key3_in: in std_logic_vector(0 to 63); |
|
-- |
-- function select |
-- |
function_select: in std_logic; -- active when encryption, inactive when decryption |
|
-- |
-- input into des_cipher_top |
-- |
data_in: in std_logic_vector(0 to 63); |
|
-- |
-- input into des_cipher_top |
-- |
data_out: out std_logic_vector(0 to 63); |
|
-- |
-- data interface to MCU |
-- |
lddata: in std_logic; -- active when data for loading is ready |
ldkey: in std_logic; -- active when key for loading is ready |
out_ready: out std_logic; -- active when encryption of data is done |
|
-- |
-- General clock and reset |
-- |
reset: in std_logic; |
clock: in std_logic |
); |
end tdes_top; |
|
architecture Behavioral of tdes_top is |
|
component des_cipher_top is |
port( |
-- |
-- inputs for key expander |
-- |
key_in: in std_logic_vector(0 to 63); -- interface to MCU |
--ldkey: in std_logic; -- active signal for loading keys |
|
-- |
-- function select |
-- |
function_select: in std_logic; -- active when encryption, inactive when decryption |
|
-- |
-- input into des_cipher_top |
-- |
data_in: in std_logic_vector(0 to 63); |
|
-- |
-- input into des_cipher_top |
-- |
data_out: out std_logic_vector(0 to 63); |
|
-- |
-- data interface to MCU |
-- |
lddata: in std_logic; -- active when data for loading is ready |
des_out_rdy: out std_logic; -- active when encryption of data is done |
|
-- |
-- General clock and reset |
-- |
reset: in std_logic; |
clock: in std_logic |
); |
end component; |
|
type statetype is (WaitKeyState, WaitDataState); |
signal nextstate: statetype; |
signal key1_in_internal: std_logic_vector(0 to 63); |
signal key2_in_internal: std_logic_vector(0 to 63); |
signal key3_in_internal: std_logic_vector(0 to 63); |
signal memkey1: std_logic_vector(0 to 63); |
signal memkey3: std_logic_vector(0 to 63); |
signal fsel_internal: std_logic; |
signal fsel_internal_inv: std_logic; |
signal des_out_rdy_internal: std_logic; |
signal des_out_rdy_internal1: std_logic; |
signal des_out_rdy_internal2: std_logic; |
signal data_in_internal: std_logic_vector(0 to 63); |
signal data_out_internal: std_logic_vector(0 to 63); |
signal data_out_internal1: std_logic_vector(0 to 63); |
signal data_out_internal2: std_logic_vector(0 to 63); |
signal lddata_internal: std_logic; |
|
begin |
|
process (clock) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
nextstate <= WaitKeyState; |
lddata_internal <= '0'; |
out_ready <= '0'; |
fsel_internal <= function_select; |
fsel_internal_inv <= not function_select; |
else |
data_out <= data_out_internal; |
out_ready <= des_out_rdy_internal; |
|
case nextstate is |
-- |
-- wait key state |
-- |
when WaitKeyState => |
-- wait until key is ready (as well as the function_select) |
if ldkey = '0' then |
nextstate <= WaitKeyState; |
else |
key1_in_internal <= key1_in; |
key2_in_internal <= key2_in; |
key3_in_internal <= key3_in; |
memkey1 <= key1_in; |
memkey3 <= key3_in; |
nextstate <= WaitDataState; |
end if; |
-- |
-- wait data state |
-- |
when WaitDataState => |
-- wait until data is ready to be loaded |
if lddata = '0' then |
nextstate <= WaitDataState; |
lddata_internal <= '0'; |
else |
lddata_internal <= '1'; |
if fsel_internal = '0' then |
key1_in_internal <= memkey3; |
key3_in_internal <= memkey1; |
end if; |
data_in_internal <= data_in; |
nextstate <= WaitDataState; |
end if; |
|
end case; |
end if; |
end if; |
end process; |
|
|
DESCIPHERTOP1: des_cipher_top |
port map ( |
key_in => key1_in_internal, -- interface to MCU |
|
function_select => fsel_internal, -- active when encryption, inactive when decryption |
|
data_in => data_in_internal, |
|
data_out => data_out_internal1, |
|
lddata => lddata_internal, -- active when data for loading is ready |
des_out_rdy => des_out_rdy_internal1, -- active when encryption of data is done |
|
reset => reset, |
clock => clock |
); |
|
DESCIPHERTOP2: des_cipher_top |
port map ( |
key_in => key2_in_internal, --subkey_in_internal, -- interface to MCU |
|
function_select => fsel_internal_inv, -- active when encryption, inactive when decryption |
|
data_in => data_out_internal1, |
|
data_out => data_out_internal2, |
|
lddata => des_out_rdy_internal1, -- active when data for loading is ready |
des_out_rdy => des_out_rdy_internal2, -- active when encryption of data is done |
|
reset => reset, |
clock => clock |
); |
|
DESCIPHERTOP3: des_cipher_top |
port map ( |
key_in => key3_in_internal, -- subkey_in_internal, -- interface to MCU |
|
function_select => fsel_internal, -- active when encryption, inactive when decryption |
|
data_in => data_out_internal2, |
|
data_out => data_out_internal, |
|
lddata => des_out_rdy_internal2, -- active when data for loading is ready |
des_out_rdy => des_out_rdy_internal, -- active when encryption of data is done |
|
reset => reset, |
clock => clock |
); |
|
end Behavioral; |
/trunk/VHDL/des_cipher_top.vhd
0,0 → 1,197
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : des_cipher_top |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity des_cipher_top is |
port( |
-- |
-- Core Interface |
-- |
key_in: in std_logic_vector(0 to 63); -- input for key |
--ldkey: in std_logic; -- signal for loading key |
function_select: in std_logic; -- function select: '1' = encryption, '0' = decryption |
|
data_in: in std_logic_vector(0 to 63); -- input for data |
|
data_out: out std_logic_vector(0 to 63); -- output for data |
|
lddata: in std_logic; -- data strobe (active high) |
core_busy: out std_logic; -- active high when encrypting/decryption data |
des_out_rdy: out std_logic; -- active high when encryption/decryption of data is done |
|
reset: in std_logic; -- active high |
clock: in std_logic -- master clock |
|
); |
end des_cipher_top; |
|
architecture Behavioral of des_cipher_top is |
|
-- |
-- |
-- |
component key_schedule is |
port ( |
-- Signals for loading key from external device |
key_in: in std_logic_vector(0 to 63); -- input for key |
|
-- signals for communication with des top |
KeySelect: in std_logic_vector(3 downto 0); -- selector for key |
key_out: out std_logic_vector(0 to 47); -- expaned key (depends on selector) |
key_ready: out std_logic; -- signal for the core that key has been expanded |
|
reset: in std_logic; -- active high |
clock: in std_logic -- master clock |
); |
end component; |
|
component des_top is |
port ( |
-- Main Data |
key_round_in: in std_logic_vector(0 to 47); |
data_in: in std_logic_vector(0 to 63); |
data_out: out std_logic_vector(0 to 63); |
|
-- Signals for communication with des |
KeySelect: inout std_logic_vector(3 downto 0); -- selector for key |
key_ready: in std_logic; -- signal for aes that key has been expanded |
data_ready: in std_logic; -- signal for aes that key has been expanded |
func_select: in std_logic; |
|
des_out_rdy: out std_logic; |
core_busy: out std_logic; |
|
reset: in std_logic; |
clock: in std_logic -- master clock |
); |
end component; |
|
signal key_select_internal: std_logic_vector(3 downto 0); |
signal key_round_internal: std_logic_vector(0 to 47); |
signal key_ready_internal: std_logic; |
signal data_in_internal: std_logic_vector(0 to 63); |
signal data_ready_internal: std_logic; |
|
begin |
|
process (clock) |
begin |
|
if rising_edge(clock) then |
|
if lddata = '1' then |
|
-- capute data from the bus |
data_in_internal <= data_in; -- register data from the bus |
data_ready_internal <= '1'; -- data has been loaded: continue with encryptio/decryption |
|
else |
|
data_ready_internal <= '0'; -- data is not loaded: wait for data |
|
end if; |
|
end if; |
end process; |
|
-- |
-- KEY EXPANDER AND DES CORE instantiation |
-- |
KEYSCHEDULE: key_schedule |
port map ( |
|
KeySelect => key_select_internal, |
key_in => key_in, |
|
key_out => key_round_internal, |
key_ready => key_ready_internal, |
|
reset => reset, |
clock => clock |
); |
|
DESTOP: des_top |
port map ( |
|
key_round_in => key_round_internal, |
|
data_in => data_in_internal, |
|
key_ready => key_ready_internal, |
data_ready => data_ready_internal, |
|
KeySelect => key_select_internal, |
|
func_select => function_select, |
|
data_out => data_out, |
core_busy => core_busy, |
des_out_rdy => des_out_rdy, |
|
reset => reset, |
clock => clock |
); |
|
end Behavioral; |
/trunk/VHDL/s1_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s1_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s1_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s1_box; |
|
architecture Behavioral of s1_box is |
|
begin |
|
SPO <= "1110" when A = x"0" else |
"0000" when A = x"1" else |
"0100" when A = x"2" else |
"1111" when A = x"3" else |
"1101" when A = x"4" else |
"0111" when A = x"5" else |
"0001" when A = x"6" else |
"0100" when A = x"7" else |
"0010" when A = x"8" else |
"1110" when A = x"9" else |
"1111" when A = x"A" else |
"0010" when A = x"B" else |
"1011" when A = x"C" else |
"1101" when A = x"D" else |
"1000" when A = x"E" else |
"0001" when A = x"F" else |
"0011" when A = x"10" else |
"1010" when A = x"11" else |
"1010" when A = x"12" else |
"0110" when A = x"13" else |
"0110" when A = x"14" else |
"1100" when A = x"15" else |
"1100" when A = x"16" else |
"1011" when A = x"17" else |
"0101" when A = x"18" else |
"1001" when A = x"19" else |
"1001" when A = x"1A" else |
"0101" when A = x"1B" else |
"0000" when A = x"1C" else |
"0011" when A = x"1D" else |
"0111" when A = x"1E" else |
"1000" when A = x"1F" else |
"0100" when A = x"20" else |
"1111" when A = x"21" else |
"0001" when A = x"22" else |
"1100" when A = x"23" else |
"1110" when A = x"24" else |
"1000" when A = x"25" else |
"1000" when A = x"26" else |
"0010" when A = x"27" else |
"1101" when A = x"28" else |
"0100" when A = x"29" else |
"0110" when A = x"2A" else |
"1001" when A = x"2B" else |
"0010" when A = x"2C" else |
"0001" when A = x"2D" else |
"1011" when A = x"2E" else |
"0111" when A = x"2F" else |
"1111" when A = x"30" else |
"0101" when A = x"31" else |
"1100" when A = x"32" else |
"1011" when A = x"33" else |
"1001" when A = x"34" else |
"0011" when A = x"35" else |
"0111" when A = x"36" else |
"1110" when A = x"37" else |
"0011" when A = x"38" else |
"1010" when A = x"39" else |
"1010" when A = x"3A" else |
"0000" when A = x"3B" else |
"0101" when A = x"3C" else |
"0110" when A = x"3D" else |
"0000" when A = x"3E" else |
"1101" when A = x"3F" else |
"1101"; |
|
END Behavioral; |
/trunk/VHDL/s2_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s2_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s2_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s2_box; |
|
architecture Behavioral of s2_box is |
|
begin |
|
SPO <= "1111" when A = x"0" else |
"0011" when A = x"1" else |
"0001" when A = x"2" else |
"1101" when A = x"3" else |
"1000" when A = x"4" else |
"0100" when A = x"5" else |
"1110" when A = x"6" else |
"0111" when A = x"7" else |
"0110" when A = x"8" else |
"1111" when A = x"9" else |
"1011" when A = x"A" else |
"0010" when A = x"B" else |
"0011" when A = x"C" else |
"1000" when A = x"D" else |
"0100" when A = x"E" else |
"1110" when A = x"F" else |
"1001" when A = x"10" else |
"1100" when A = x"11" else |
"0111" when A = x"12" else |
"0000" when A = x"13" else |
"0010" when A = x"14" else |
"0001" when A = x"15" else |
"1101" when A = x"16" else |
"1010" when A = x"17" else |
"1100" when A = x"18" else |
"0110" when A = x"19" else |
"0000" when A = x"1A" else |
"1001" when A = x"1B" else |
"0101" when A = x"1C" else |
"1011" when A = x"1D" else |
"1010" when A = x"1E" else |
"0101" when A = x"1F" else |
"0000" when A = x"20" else |
"1101" when A = x"21" else |
"1110" when A = x"22" else |
"1000" when A = x"23" else |
"0111" when A = x"24" else |
"1010" when A = x"25" else |
"1011" when A = x"26" else |
"0001" when A = x"27" else |
"1010" when A = x"28" else |
"0011" when A = x"29" else |
"0100" when A = x"2A" else |
"1111" when A = x"2B" else |
"1101" when A = x"2C" else |
"0100" when A = x"2D" else |
"0001" when A = x"2E" else |
"0010" when A = x"2F" else |
"0101" when A = x"30" else |
"1011" when A = x"31" else |
"1000" when A = x"32" else |
"0110" when A = x"33" else |
"1100" when A = x"34" else |
"0111" when A = x"35" else |
"0110" when A = x"36" else |
"1100" when A = x"37" else |
"1001" when A = x"38" else |
"0000" when A = x"39" else |
"0011" when A = x"3A" else |
"0101" when A = x"3B" else |
"0010" when A = x"3C" else |
"1110" when A = x"3D" else |
"1111" when A = x"3E" else |
"1001" when A = x"3F" else |
"1001"; |
|
END Behavioral; |
/trunk/VHDL/s3_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s3_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s3_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s3_box; |
|
architecture Behavioral of s3_box is |
|
begin |
|
SPO <= "1010" when A = x"0" else |
"1101" when A = x"1" else |
"0000" when A = x"2" else |
"0111" when A = x"3" else |
"1001" when A = x"4" else |
"0000" when A = x"5" else |
"1110" when A = x"6" else |
"1001" when A = x"7" else |
"0110" when A = x"8" else |
"0011" when A = x"9" else |
"0011" when A = x"A" else |
"0100" when A = x"B" else |
"1111" when A = x"C" else |
"0110" when A = x"D" else |
"0101" when A = x"E" else |
"1010" when A = x"F" else |
"0001" when A = x"10" else |
"0010" when A = x"11" else |
"1101" when A = x"12" else |
"1000" when A = x"13" else |
"1100" when A = x"14" else |
"0101" when A = x"15" else |
"0111" when A = x"16" else |
"1110" when A = x"17" else |
"1011" when A = x"18" else |
"1100" when A = x"19" else |
"0100" when A = x"1A" else |
"1011" when A = x"1B" else |
"0010" when A = x"1C" else |
"1111" when A = x"1D" else |
"1000" when A = x"1E" else |
"0001" when A = x"1F" else |
"1101" when A = x"20" else |
"0001" when A = x"21" else |
"0110" when A = x"22" else |
"1010" when A = x"23" else |
"0100" when A = x"24" else |
"1101" when A = x"25" else |
"1001" when A = x"26" else |
"0000" when A = x"27" else |
"1000" when A = x"28" else |
"0110" when A = x"29" else |
"1111" when A = x"2A" else |
"1001" when A = x"2B" else |
"0011" when A = x"2C" else |
"1000" when A = x"2D" else |
"0000" when A = x"2E" else |
"0111" when A = x"2F" else |
"1011" when A = x"30" else |
"0100" when A = x"31" else |
"0001" when A = x"32" else |
"1111" when A = x"33" else |
"0010" when A = x"34" else |
"1110" when A = x"35" else |
"1100" when A = x"36" else |
"0011" when A = x"37" else |
"0101" when A = x"38" else |
"1011" when A = x"39" else |
"1010" when A = x"3A" else |
"0101" when A = x"3B" else |
"1110" when A = x"3C" else |
"0010" when A = x"3D" else |
"0111" when A = x"3E" else |
"1100" when A = x"3F" else |
"1100"; |
|
END Behavioral; |
/trunk/VHDL/des_top.vhd
0,0 → 1,287
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : des_top |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity des_top is |
port ( |
|
-- input/output core signals |
key_round_in: in std_logic_vector(0 to 47); |
data_in: in std_logic_vector(0 to 63); |
data_out: out std_logic_vector(0 to 63); |
|
-- signals for communication with key expander module |
KeySelect: inout std_logic_vector(3 downto 0); -- selector for key |
key_ready: in std_logic; -- active high when key is ready |
data_ready: in std_logic; -- active high when data is ready |
func_select: in std_logic; -- encryption/decryption flag |
|
des_out_rdy: out std_logic; -- active high when decrypted/encrypted data are ready |
core_busy: out std_logic; -- active high when core is in process of encryption |
|
reset: in std_logic; -- master reset |
clock: in std_logic -- master clock |
); |
end des_top; |
|
architecture Behavioral of des_top is |
|
-- |
-- BLOCK_TOP entity performs encryption/deccryption operation. It uses expaned key for that process |
-- |
component block_top is |
port( |
L_in: in std_logic_vector(0 to 31); -- left permuted input |
R_in: in std_logic_vector(0 to 31); -- right permuted input |
|
L_out: out std_logic_vector(0 to 31); -- left permuted output |
R_out: out std_logic_vector(0 to 31); -- right permuted output |
|
round_key_des: in std_logic_vector(0 to 47) -- current round key |
|
); |
end component; |
|
-- |
-- Internal DES_TOP signals |
-- |
signal L_in_internal, R_in_internal: std_logic_vector(0 to 31); |
signal L_out_internal, R_out_internal: std_logic_vector(0 to 31); |
type statetype is (WaitKey, WaitData, InitialRound, RepeatRound, FinalRound); |
signal nextstate: statetype; |
signal RoundCounter: std_logic_vector(3 downto 0); |
|
begin |
|
-- |
-- Finite state machine |
-- |
process (clock) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
-- |
-- Reset all signal to inital values |
-- |
nextstate <= WaitKey; |
RoundCounter <= "0000"; |
core_busy <= '0'; -- core is in reset state: not busy |
des_out_rdy <= '0'; -- output data is not ready |
|
else |
|
case nextstate is |
|
-- |
-- WaitKey: wait for key to be expanded |
-- |
when WaitKey => |
|
-- wait until key has been expanded |
if key_ready = '0' then |
nextstate <= WaitKey; |
else |
nextstate <= WaitData; |
end if; |
|
core_busy <= '0'; -- core waits for the key: not busy |
des_out_rdy <= '0'; -- output data is not ready |
|
-- |
-- WaitData: waits for data until it is ready |
-- |
when WaitData => |
|
-- wait for data to be loaded in input registers |
if (data_ready = '0') then |
|
nextstate <= WaitData; |
|
else |
core_busy <= '1'; -- core is processing = busy |
|
L_in_internal <= data_in(57) & data_in(49) & data_in(41) & data_in(33) & data_in(25) & data_in(17) & |
data_in(9) & data_in(1) & data_in(59) & data_in(51) & data_in(43) & data_in(35) & |
data_in(27) & data_in(19) & data_in(11) & data_in(3) & data_in(61) & data_in(53) & |
data_in(45) & data_in(37) & data_in(29) & data_in(21) & data_in(13) & data_in(5) & |
data_in(63) & data_in(55) & data_in(47) & data_in(39) & data_in(31) & data_in(23) & |
data_in(15) & data_in(7); |
|
R_in_internal <= data_in(56) & data_in(48) & data_in(40) & data_in(32) & data_in(24) & data_in(16) & |
data_in(8) & data_in(0) & data_in(58) & data_in(50) & data_in(42) & data_in(34) & |
data_in(26) & data_in(18) & data_in(10) & data_in(2) & data_in(60) & data_in(52) & |
data_in(44) & data_in(36) & data_in(28) & data_in(20) & data_in(12) & data_in(4) & |
data_in(62) & data_in(54) & data_in(46) & data_in(38) & data_in(30) & data_in(22) & |
data_in(14) & data_in(6); |
|
nextstate <= InitialRound; |
|
-- function select (decrypting/encrypting) will determine key selection |
if func_select = '1' then |
KeySelect <= "0000"; |
else |
KeySelect <= "1111"; |
end if; |
|
end if; |
|
-- |
-- Initial State where input is equal to a block that we need to encode |
-- |
when InitialRound => |
|
L_in_internal <= L_out_internal; |
R_in_internal <= R_out_internal; |
|
-- fuction select determines direction of key selection |
if func_select = '1' then |
KeySelect <= KeySelect + '1'; |
else |
KeySelect <= KeySelect - '1'; |
end if; |
|
nextstate <= RepeatRound; |
|
-- |
-- Repeat Section, where input is output from prevous state |
-- |
when RepeatRound => |
|
L_in_internal <= L_out_internal; |
R_in_internal <= R_out_internal; |
|
-- fuction select determines direction of key selection |
if func_select = '1' then |
KeySelect <= KeySelect + '1'; |
else |
KeySelect <= KeySelect - '1'; |
end if; |
|
RoundCounter <= RoundCounter + '1'; |
|
-- if finished with all rounds, go to the final round |
if RoundCounter = x"E" then |
|
-- perform inverse initial permutation |
data_out <= L_out_internal(7) & R_out_internal(7) & L_out_internal(15) & R_out_internal(15) & |
L_out_internal(23) & R_out_internal(23) & L_out_internal(31) & R_out_internal(31) & |
L_out_internal(6) & R_out_internal(6) & L_out_internal(14) & R_out_internal(14) & |
L_out_internal(22) & R_out_internal(22) & L_out_internal(30) & R_out_internal(30) & |
L_out_internal(5) & R_out_internal(5) & L_out_internal(13) & R_out_internal(13) & |
L_out_internal(21) & R_out_internal(21) & L_out_internal(29) & R_out_internal(29) & |
L_out_internal(4) & R_out_internal(4) & L_out_internal(12) & R_out_internal(12) & |
L_out_internal(20) & R_out_internal(20) & L_out_internal(28) & R_out_internal(28) & |
L_out_internal(3) & R_out_internal(3) & L_out_internal(11) & R_out_internal(11) & |
L_out_internal(19) & R_out_internal(19) & L_out_internal(27) & R_out_internal(27) & |
L_out_internal(2) & R_out_internal(2) & L_out_internal(10) & R_out_internal(10) & |
L_out_internal(18) & R_out_internal(18) & L_out_internal(26) & R_out_internal(26) & |
L_out_internal(1) & R_out_internal(1) & L_out_internal(9) & R_out_internal(9) & |
L_out_internal(17) & R_out_internal(17) & L_out_internal(25) & R_out_internal(25) & |
L_out_internal(0) & R_out_internal(0) & L_out_internal(8) & R_out_internal(8) & |
L_out_internal(16) & R_out_internal(16) & L_out_internal(24) & R_out_internal(24); |
|
core_busy <= '0'; -- core is not busy |
des_out_rdy <= '1'; -- output data is ready |
nextstate <= FinalRound; |
|
else |
|
-- Continue with regular rounds |
nextstate <= RepeatRound; |
|
end if; |
|
-- |
-- Last round |
-- |
when FinalRound => |
|
RoundCounter <= "0000"; |
nextstate <= WaitKey; |
des_out_rdy <= '0'; -- deselect out data ready signal |
|
when others => |
-- should never happen |
end case; |
end if; |
end if; |
end process; |
|
-- |
-- Instantations |
-- |
BLOCKTOP: block_top |
port map ( |
L_in => L_in_internal, |
R_in => R_in_internal, |
|
round_key_des => key_round_in, |
|
L_out => L_out_internal, |
R_out => R_out_internal |
|
); |
|
end Behavioral; |
/trunk/VHDL/s4_box.vhd
0,0 → 1,144
--------------------------------------------------------------------- |
-- (c) Copyright 2006, CoreTex Systems, LLC -- |
-- www.coretexsys.com -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- |
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- |
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- |
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- |
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- |
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- |
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- |
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- |
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- |
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- |
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- |
-- POSSIBILITY OF SUCH DAMAGE. -- |
-- -- |
--------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
|
-- Poject structure: |
|
-- |- tdes_top.vhd |
-- | |
-- |- des_cipher_top.vhd |
-- |- des_top.vhd |
-- |- block_top.vhd |
-- |- add_key.vhd |
-- | |
-- |- add_left.vhd |
-- | |
-- |- e_expansion_function.vhd |
-- | |
-- |- p_box.vhd |
-- | |
-- |- s_box.vhd |
-- |- s1_box.vhd |
-- |- s2_box.vhd |
-- |- s3_box.vhd |
-- |- s4_box.vhd |
-- |- s5_box.vhd |
-- |- s6_box.vhd |
-- |- s7_box.vhd |
-- |- s8_box.vhd |
-- |- key_schedule.vhd |
|
---------------------------------------------------------------------- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : s4_box |
-- Company : CoreTex Systems, LLC |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY s4_box IS |
port ( |
A: IN std_logic_VECTOR(5 downto 0); |
SPO: OUT std_logic_VECTOR(3 downto 0)); |
END s4_box; |
|
architecture Behavioral of s4_box is |
|
begin |
|
SPO <= "0111" when A = x"0" else |
"1101" when A = x"1" else |
"1101" when A = x"2" else |
"1000" when A = x"3" else |
"1110" when A = x"4" else |
"1011" when A = x"5" else |
"0011" when A = x"6" else |
"0101" when A = x"7" else |
"0000" when A = x"8" else |
"0110" when A = x"9" else |
"0110" when A = x"A" else |
"1111" when A = x"B" else |
"1001" when A = x"C" else |
"0000" when A = x"D" else |
"1010" when A = x"E" else |
"0011" when A = x"F" else |
"0001" when A = x"10" else |
"0100" when A = x"11" else |
"0010" when A = x"12" else |
"0111" when A = x"13" else |
"1000" when A = x"14" else |
"0010" when A = x"15" else |
"0101" when A = x"16" else |
"1100" when A = x"17" else |
"1011" when A = x"18" else |
"0001" when A = x"19" else |
"1100" when A = x"1A" else |
"1010" when A = x"1B" else |
"0100" when A = x"1C" else |
"1110" when A = x"1D" else |
"1111" when A = x"1E" else |
"1001" when A = x"1F" else |
"1010" when A = x"20" else |
"0011" when A = x"21" else |
"0110" when A = x"22" else |
"1111" when A = x"23" else |
"1001" when A = x"24" else |
"0000" when A = x"25" else |
"0000" when A = x"26" else |
"0110" when A = x"27" else |
"1100" when A = x"28" else |
"1010" when A = x"29" else |
"1011" when A = x"2A" else |
"0001" when A = x"2B" else |
"0111" when A = x"2C" else |
"1101" when A = x"2D" else |
"1101" when A = x"2E" else |
"1000" when A = x"2F" else |
"1111" when A = x"30" else |
"1001" when A = x"31" else |
"0001" when A = x"32" else |
"0100" when A = x"33" else |
"0011" when A = x"34" else |
"0101" when A = x"35" else |
"1110" when A = x"36" else |
"1011" when A = x"37" else |
"0101" when A = x"38" else |
"1100" when A = x"39" else |
"0010" when A = x"3A" else |
"0111" when A = x"3B" else |
"1000" when A = x"3C" else |
"0010" when A = x"3D" else |
"0100" when A = x"3E" else |
"1110" when A = x"3F" else |
"1110"; |
|
END Behavioral; |