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URL https://opencores.org/ocsvn/ag_6502/ag_6502/trunk

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/ag_6502/trunk/ag_6502/states.v
0,0 → 1,337
// This file has been generated automatically
// by the GenStates tool
// Copyright (c) Oleg Odintsov
// This tool is a part of Agat hardware project
 
// Level of optimization: infinite
// Total number of actions: 82
wire E_AB__PC;
wire E_AB__EA;
wire E_AB__S;
wire E_PC__PC_1;
wire E_T__0;
wire E_N_Z__SB;
wire E_N_Z__RES;
wire E_N_Z__SB_RES;
wire E_C__RES;
wire E_V__RES;
wire E_V__SB_6_;
wire A_ALU_CF_0;
wire A_ALU_DF_0;
wire A_ALU_OP_ADC;
wire A_SB_0;
wire A_ALU_B_SB;
wire A_ALU_CF_1;
wire A_ALU_CF_ALUC;
wire A_ALU_B_NOTSB;
wire A_ALU_OP_ORA;
wire A_ALU_A_DB;
wire A_SB_X;
wire A_ALU_A_EAL;
wire A_SB_PCL;
wire A_SB_Y;
wire A_ALU_A_ALU;
wire A_ALU_A_S;
wire E_CF__IR_5_;
wire E_IF__IR_5_;
wire E_DF__IR_5_;
wire E_VF__0;
wire E_T__0IFNF__IR_5_;
wire E_T__0IFVF__IR_5_;
wire E_T__0IFCF__IR_5_;
wire E_T__0IFZF__IR_5_;
wire E_EA__DB;
wire E_EAL__DB;
wire E_PCL__RES;
wire E_T__0IF_C7F;
wire A_ALU_A_SIGN;
wire A_SB_PCH;
wire E_PCH__RES;
wire E_EAH__DB;
wire E_EAL__ALU;
wire E_T__T_1IF_ALUCZ;
wire E_EAH__ALU;
wire E_PCL__ALU;
wire A_SB_DB;
wire E_AC__SB;
wire A_ALU_A_AC;
wire E_AC__RES;
wire A_ALU_OP_AND;
wire A_ALU_OP_EOR;
wire A_ALU_A_X;
wire A_ALU_A_Y;
wire A_ALU_DF_D;
wire A_ALU_CF_C;
wire A_ALU_OP_ASL;
wire A_RW_W;
wire A_SB_ALU;
wire E_DB__SB;
wire A_ALU_OP_LSR;
wire A_ALU_OP_ROL;
wire A_ALU_OP_ROR;
wire A_SB_AC;
wire E_X__SB;
wire E_Y__SB;
wire A_SB_S;
wire E_S__SB;
wire E_PC__EA;
wire E_S__ALU;
wire A_SB_P;
wire E_P__SB;
wire E_X__RES;
wire E_Y__RES;
wire E_DB__ALU;
wire E_DB__PCH;
wire E_PCL__EAL;
wire E_DB__PCL;
wire E_DB__P;
wire E_P__DB;
wire E_PCL__DB;
 
// Actions assignments
 
// action: AB <= PC:
assign E_AB__PC = (!L[10] && ((!L[0] && ((!L[1] && ((!L[2] && ((!L[9] && (!L[3] || (L[3] && ((!L[4] && (!L[7] || ({L[7],L[8]} == 2'b10))) || (L[4] && ((!L[5] && ((!L[6] && (!L[8] || ({L[7],L[8]} == 2'b01))) || L[6])) || L[5])))))) || ({L[3],L[4],L[9]} == 3'b011))) || (L[2] && (!L[9] || ({L[3],L[8],L[9]} == 3'b101))))) || (L[1] && ((!L[9] && ((!L[2] && ((!L[8] && (({L[3],L[4],L[7]} == 3'b001) || L[3])) || ({L[3],L[4],L[7],L[8]} == 4'b0011))) || L[2])) || ({L[2],L[3],L[8],L[9]} == 4'b1101))))) || (L[0] && ((!L[9] && (!L[1] || (L[1] && ((!L[2] && (!L[3] || (L[3] && ((!L[4] && ((!L[5] && ((!L[6] && (!L[8] || ({L[7],L[8]} == 2'b01))) || L[6])) || L[5])) || L[4])))) || L[2])))) || (({L[3],L[8],L[9]} == 3'b101) && (({L[2],L[4]} == 2'b01) || L[2])))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[7],L[8],L[9],L[10]} == 10'b0000010101);
 
// action: AB <= EA:
assign E_AB__EA = (({L[9],L[10]} == 2'b01) && ((!L[2] && (({L[0],L[1],L[3],L[4],L[5],L[6],L[7],L[8]} == 8'b00000001) || (L[0] && (!L[3] || ({L[3],L[4],L[8]} == 3'b110))))) || (({L[2],L[3],L[8]} == 3'b110) && (({L[0],L[1],L[4],L[5],L[6],L[7]} == 6'b000110) || L[4])))) || (L[9] && ((!L[10] && ((({L[0],L[2]} == 2'b01) && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || ({L[3],L[8]} == 2'b11))) || (L[0] && ((!L[3] && ((!L[1] && (!L[2] || (L[2] && (({L[4],L[8]} == 2'b00) || L[4])))) || (L[1] && (!L[2] || (L[2] && (({L[4],L[8]} == 2'b00) || L[4])))))) || (({L[3],L[8]} == 2'b11) && (({L[2],L[4]} == 2'b01) || L[2])))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[10]} == 10'b0000000001)));
 
// action: AB <= S:
assign E_AB__S = (({L[0],L[1],L[2],L[3],L[4],L[7],L[9],L[10]} == 8'b00000001) && (!L[8] || ({L[5],L[6],L[8]} == 3'b011))) || (({L[0],L[1],L[2],L[4],L[7],L[9],L[10]} == 7'b0000010) && (!L[3] || (L[3] && (({L[5],L[8]} == 2'b00) || L[5]))));
 
// action: PC <= PC + 1:
assign E_PC__PC_1 = (!L[10] && ((!L[9] && ((!L[0] && ((!L[1] && ((!L[2] && (!L[8] || (({L[3],L[8]} == 2'b01) && ((!L[4] && (({L[5],L[6],L[7]} == 3'b100) || L[7])) || L[4])))) || L[2])) || (L[1] && ((!L[2] && ((!L[8] && (({L[3],L[4],L[7]} == 3'b001) || L[3])) || ({L[3],L[4],L[7],L[8]} == 4'b0011))) || L[2])))) || (L[0] && (!L[1] || (L[1] && ((!L[2] && (!L[3] || (L[3] && ((!L[4] && ((!L[5] && ((!L[6] && (!L[8] || ({L[7],L[8]} == 2'b01))) || L[6])) || L[5])) || L[4])))) || L[2])))))) || (({L[3],L[8],L[9]} == 3'b101) && (({L[0],L[2],L[4]} == 3'b101) || (L[2] && ((!L[0] && ((!L[1] && ((!L[4] && (!L[5] || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))) || L[4])) || L[1])) || L[0])))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000110101);
 
// action: T <= 0:
assign E_T__0 = (!L[0] && ((!L[1] && ((!L[2] && ((!L[10] && ((({L[3],L[8],L[9]} == 3'b101) && (({L[4],L[5],L[7]} == 3'b000) || (L[4] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))) || (L[8] && ((({L[7],L[9]} == 2'b01) && (({L[3],L[4],L[5]} == 3'b101) || ({L[3],L[4]} == 2'b01))) || (L[7] && ((!L[9] && (!L[4] || ({L[3],L[4],L[5],L[6]} == 4'b1100))) || ({L[3],L[4],L[9]} == 3'b011))))))) || (({L[3],L[4],L[7],L[10]} == 4'b0001) && (({L[5],L[6],L[8],L[9]} == 4'b0001) || (({L[8],L[9]} == 2'b10) && (({L[5],L[6]} == 2'b01) || L[5])))))) || (L[2] && ((({L[3],L[8],L[9],L[10]} == 4'b1001) && (({L[4],L[5],L[6],L[7]} == 4'b0110) || L[4])) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || (({L[3],L[8]} == 2'b11) && (!L[5] || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))))) || ({L[3],L[4],L[8]} == 3'b011))))))) || (L[1] && ((({L[2],L[8],L[9],L[10]} == 4'b0100) && (({L[3],L[4],L[7]} == 3'b001) || L[3])) || (L[2] && ((({L[6],L[7],L[9],L[10]} == 4'b0110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))) || (L[10] && ((!L[9] && ((!L[3] && ((({L[4],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[4],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[3] && (({L[4],L[6],L[7],L[8]} == 4'b1010) || (({L[4],L[8]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[3],L[4],L[8],L[9]} == 4'b1101) && (({L[6],L[7]} == 2'b00) || L[6])))))))))) || (L[0] && ((!L[9] && ((!L[2] && (({L[3],L[4],L[8],L[10]} == 4'b1101) || (L[8] && ((!L[4] && (({L[3],L[10]} == 2'b01) || ({L[3],L[10]} == 2'b10))) || ({L[3],L[4],L[10]} == 3'b011))))) || ({L[2],L[3],L[4],L[8],L[10]} == 5'b11101))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101)))));
 
// action: N,Z <= SB:
assign E_N_Z__SB = (({L[6],L[7]} == 2'b01) && ((({L[0],L[2],L[3],L[5],L[8],L[9],L[10]} == 7'b0010100) && (({L[1],L[4]} == 2'b01) || ({L[1],L[4]} == 2'b10))) || (L[5] && ((!L[9] && ((!L[2] && (({L[0],L[1],L[3],L[4],L[8],L[10]} == 6'b101101) || (L[8] && ((!L[10] && ((!L[4] && (({L[0],L[3]} == 2'b00) || L[3])) || ({L[0],L[1],L[3],L[4]} == 4'b0111))) || ({L[0],L[3],L[10]} == 3'b101))))) || ({L[2],L[3],L[4],L[8],L[10]} == 5'b11101))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101))))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010110110);
 
// action: N,Z <= RES:
assign E_N_Z__RES = (!L[9] && ((({L[2],L[4],L[8],L[10]} == 4'b0010) && (({L[0],L[1],L[3],L[6],L[7]} == 5'b00011) || (L[3] && ((!L[0] && ((({L[1],L[7]} == 2'b01) && (({L[5],L[6]} == 2'b00) || L[6])) || (L[1] && (!L[7] || ({L[5],L[6],L[7]} == 3'b011))))) || (L[0] && (({L[1],L[6],L[7]} == 3'b000) || (L[6] && (({L[1],L[5]} == 2'b00) || (L[5] && (({L[1],L[7]} == 2'b00) || L[7])))))))))) || (L[10] && ((({L[0],L[1],L[2]} == 3'b011) && ((({L[3],L[4],L[8]} == 3'b010) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[3] && ((({L[4],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[4],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[0],L[1]} == 2'b10) && ((({L[2],L[3],L[4],L[8]} == 4'b0001) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[4] && ((({L[2],L[3],L[8]} == 3'b001) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b10) && (({L[6],L[7]} == 2'b00) || L[6])))))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[1] && ((({L[0],L[4],L[6],L[7]} == 4'b0011) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (L[0] && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[3],L[4],L[8]} == 3'b011) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[0],L[1],L[3],L[4],L[8]} == 5'b01001) && (({L[6],L[7]} == 2'b00) || L[6]))));
 
// action: N,Z <= SB,RES:
assign E_N_Z__SB_RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00100100010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110100110);
 
// action: C <= RES:
assign E_C__RES = (({L[0],L[1],L[6],L[7]} == 4'b0100) && (({L[2],L[3],L[4],L[8],L[9],L[10]} == 6'b010100) || (L[2] && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110))))) || (L[6] && ((!L[9] && ((({L[2],L[4],L[8],L[10]} == 4'b0010) && (({L[0],L[1],L[3],L[7]} == 4'b0001) || (L[3] && (({L[0],L[1],L[7]} == 3'b010) || (L[0] && (({L[1],L[5],L[7]} == 3'b001) || (L[5] && (({L[1],L[7]} == 2'b00) || L[7])))))))) || (L[10] && ((({L[0],L[1],L[2],L[7]} == 4'b0110) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || (({L[0],L[1]} == 2'b10) && ((({L[2],L[3],L[4],L[8]} == 4'b0001) && (({L[5],L[7]} == 2'b01) || L[5])) || (L[4] && ((({L[2],L[3],L[8]} == 3'b001) && (({L[5],L[7]} == 2'b01) || L[5])) || (({L[3],L[8]} == 2'b10) && (({L[5],L[7]} == 2'b01) || L[5])))))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[1] && ((!L[4] && ((({L[0],L[5],L[7]} == 3'b110) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (L[7] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))))) || (({L[0],L[3],L[4],L[8]} == 4'b1011) && (({L[5],L[7]} == 2'b01) || L[5])))) || ({L[0],L[1],L[3],L[4],L[7],L[8]} == 6'b010001)))));
 
// action: V <= RES:
assign E_V__RES = (({L[0],L[5],L[6],L[9]} == 4'b1110) && ((!L[2] && (({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) || (L[8] && ((!L[4] && (({L[1],L[3],L[10]} == 3'b001) || (({L[3],L[10]} == 2'b10) && (({L[1],L[7]} == 2'b00) || L[7])))) || ({L[1],L[3],L[4],L[10]} == 4'b0011))))) || ({L[1],L[2],L[3],L[4],L[8],L[10]} == 6'b011101))) || (({L[0],L[1],L[2],L[5],L[6],L[9],L[10]} == 7'b1011110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)));
 
// action: V <= SB[6]:
assign E_V__SB_6_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00100100010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110100110);
 
// action: ALU_CF = 0:
assign A_ALU_CF_0 = (!L[10] && ((({L[2],L[3],L[8],L[9]} == 4'b0001) && (({L[0],L[1],L[4],L[6],L[7]} == 5'b00000) || (L[4] && (({L[0],L[1]} == 2'b00) || L[0])))) || (L[8] && ((!L[9] && ((!L[2] && ((({L[0],L[4],L[5]} == 3'b000) && (({L[1],L[3],L[6],L[7]} == 4'b0000) || (L[3] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || ({L[1],L[7]} == 2'b11))))))) || (L[0] && (({L[3],L[4]} == 2'b00) || ({L[3],L[4]} == 2'b11))))) || ({L[2],L[4]} == 2'b11))) || (({L[0],L[3],L[9]} == 3'b001) && ((({L[1],L[2]} == 2'b00) && (({L[4],L[6],L[7]} == 3'b000) || L[4])) || ({L[1],L[2],L[4],L[5],L[6],L[7]} == 6'b110011))))))) || (({L[0],L[1],L[2],L[5],L[6],L[7],L[9],L[10]} == 8'b01101101) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11)))));
 
// action: ALU_DF = 0:
assign A_ALU_DF_0 = (!L[9] && ((({L[8],L[10]} == 2'b01) && (({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7]} == 8'b00000000) || (L[6] && (({L[0],L[1],L[2],L[3],L[4],L[5],L[7]} == 7'b0000000) || (L[7] && (({L[0],L[1],L[2],L[3],L[4],L[5]} == 6'b100110) || (L[2] && (({L[0],L[1],L[3],L[4],L[5]} == 5'b10110) || (({L[0],L[1]} == 2'b01) && (({L[3],L[4]} == 2'b01) || ({L[3],L[4]} == 2'b10))))))))))) || (L[8] && ((!L[10] && ((!L[2] && ((({L[0],L[4]} == 2'b00) && ((({L[1],L[3]} == 2'b00) && (({L[5],L[6],L[7]} == 3'b000) || L[6])) || (L[3] && ((!L[5] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))) || (({L[1],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (L[0] && ((!L[1] && (!L[3] || (L[3] && (({L[4],L[5],L[6],L[7]} == 4'b0011) || L[4])))) || (L[1] && (({L[3],L[4]} == 2'b00) || L[4])))))) || ({L[2],L[4]} == 2'b11))) || (({L[6],L[7],L[10]} == 3'b111) && (({L[0],L[1],L[2],L[3],L[4],L[5]} == 6'b100000) || (L[4] && (({L[0],L[1],L[2],L[3],L[5]} == 5'b10000) || ({L[0],L[1],L[2],L[3]} == 4'b0111))))))))) || (({L[9],L[10]} == 2'b10) && ((!L[0] && ((({L[1],L[2],L[3]} == 3'b000) && ((({L[4],L[7]} == 2'b00) && (!L[5] || (L[5] && (!L[8] || ({L[6],L[8]} == 2'b01))))) || L[4])) || (L[2] && ((({L[3],L[4],L[6],L[7]} == 4'b0011) && (({L[1],L[8]} == 2'b00) || ({L[1],L[8]} == 2'b11))) || (L[3] && ((!L[8] && (({L[1],L[4],L[5],L[6],L[7]} == 5'b00110) || L[4])) || ({L[1],L[4],L[6],L[7],L[8]} == 5'b00111))))))) || (L[0] && ((!L[1] && ((!L[2] && (({L[3],L[4],L[8]} == 3'b000) || (L[4] && (!L[8] || ({L[3],L[8]} == 2'b01))))) || (L[2] && ((({L[3],L[5],L[6],L[7]} == 4'b0011) && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || (L[3] && (({L[4],L[5],L[6],L[7],L[8]} == 5'b00111) || ({L[4],L[8]} == 2'b10))))))) || (L[1] && (({L[2],L[3],L[4],L[8]} == 4'b0000) || (L[4] && ((!L[8] && (({L[2],L[3]} == 2'b00) || L[3])) || ({L[2],L[3],L[8]} == 3'b001)))))))));
 
// action: ALU_OP = ADC:
assign A_ALU_OP_ADC = (!L[9] && ((({L[8],L[10]} == 2'b01) && (({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7]} == 8'b00000000) || (L[6] && ((!L[1] && (({L[0],L[2],L[3],L[4],L[5],L[7]} == 6'b000000) || (({L[0],L[3],L[4]} == 3'b111) && (({L[5],L[7]} == 2'b01) || L[5])))) || (({L[0],L[1],L[2],L[7]} == 4'b0111) && (({L[3],L[4]} == 2'b01) || ({L[3],L[4]} == 2'b10))))))) || (L[8] && ((!L[2] && ((!L[10] && ((({L[0],L[4]} == 2'b00) && ((({L[1],L[3]} == 2'b00) && (({L[5],L[6],L[7]} == 3'b000) || L[6])) || (L[3] && ((!L[5] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))) || (({L[1],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (L[0] && ((!L[1] && (!L[3] || (L[3] && ((({L[4],L[6]} == 2'b01) && (({L[5],L[7]} == 2'b01) || L[5])) || L[4])))) || (L[1] && (!L[3] || (L[3] && (({L[4],L[5],L[6],L[7]} == 4'b0111) || L[4])))))))) || (({L[0],L[1],L[3],L[6],L[10]} == 5'b10011) && (({L[5],L[7]} == 2'b01) || L[5])))) || (({L[2],L[4]} == 2'b11) && (!L[10] || ({L[0],L[1],L[3],L[6],L[7],L[10]} == 6'b011111))))))) || (({L[9],L[10]} == 2'b10) && ((!L[0] && ((({L[1],L[2],L[3]} == 3'b000) && ((({L[4],L[7]} == 2'b00) && (!L[5] || (L[5] && (!L[8] || ({L[6],L[8]} == 2'b01))))) || L[4])) || (L[2] && ((({L[3],L[4],L[6],L[7]} == 4'b0011) && (({L[1],L[8]} == 2'b00) || ({L[1],L[8]} == 2'b11))) || (L[3] && ((!L[8] && (({L[1],L[4],L[5],L[6],L[7]} == 5'b00110) || L[4])) || ({L[1],L[4],L[6],L[7],L[8]} == 5'b00111))))))) || (L[0] && ((!L[1] && ((!L[2] && (({L[3],L[4],L[8]} == 3'b000) || (L[4] && (!L[8] || ({L[3],L[8]} == 2'b01))))) || (L[2] && (({L[3],L[4],L[6],L[8]} == 4'b1100) || (L[6] && ((!L[3] && ((({L[4],L[8]} == 2'b00) && (({L[5],L[7]} == 2'b01) || L[5])) || (({L[4],L[8]} == 2'b11) && (({L[5],L[7]} == 2'b01) || L[5])))) || (L[3] && ((({L[4],L[8]} == 2'b01) && (({L[5],L[7]} == 2'b01) || L[5])) || ({L[4],L[8]} == 2'b10))))))))) || (L[1] && (({L[2],L[3],L[4],L[8]} == 4'b0000) || (L[4] && ((!L[8] && (({L[2],L[3]} == 2'b00) || L[3])) || ({L[2],L[3],L[8]} == 3'b001)))))))));
 
// action: SB = 0:
assign A_SB_0 = (!L[10] && ((({L[2],L[8],L[9]} == 3'b010) && ((!L[3] && ((({L[0],L[1],L[4],L[7]} == 4'b0000) && (({L[5],L[6]} == 2'b00) || L[6])) || ({L[0],L[4]} == 2'b11))) || (({L[0],L[3],L[4]} == 3'b010) && ((!L[5] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))) || (({L[1],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (L[9] && ((!L[0] && (({L[1],L[2],L[3],L[4],L[7]} == 5'b00000) || (L[2] && ((({L[1],L[3]} == 2'b01) && ((!L[8] && (({L[4],L[5],L[6],L[7]} == 4'b0110) || L[4])) || ({L[4],L[5],L[6],L[7],L[8]} == 5'b01101))) || (L[1] && ((!L[3] && ((({L[6],L[7]} == 2'b00) && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || (L[6] && (({L[4],L[8]} == 2'b00) || (L[8] && (({L[4],L[7]} == 2'b01) || L[4])))))) || (L[3] && ((({L[4],L[8]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])) || ({L[4],L[8]} == 2'b10))))))))) || (L[0] && ((!L[2] && ((!L[3] && (!L[4] || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b110))) || ({L[2],L[3],L[4],L[8]} == 4'b1110))))))) || (({L[0],L[10]} == 2'b01) && ((!L[9] && ((({L[1],L[2],L[3],L[4],L[7]} == 5'b00000) && (!L[5] || (L[5] && (({L[6],L[8]} == 2'b01) || ({L[6],L[8]} == 2'b10))))) || (L[2] && (({L[1],L[3],L[4],L[5],L[6],L[7],L[8]} == 7'b0101100) || (L[1] && (({L[3],L[4],L[6],L[7],L[8]} == 5'b01110) || (L[3] && (({L[4],L[6],L[7],L[8]} == 4'b0110) || (L[4] && (({L[6],L[7],L[8]} == 3'b000) || (L[6] && (({L[7],L[8]} == 2'b00) || L[7])))))))))))) || ({L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9]} == 9'b000000001)));
 
// action: ALU_B = SB:
assign A_ALU_B_SB = (!L[0] && ((({L[1],L[2]} == 2'b00) && ((!L[4] && ((!L[7] && ((({L[3],L[5]} == 2'b00) && ((({L[6],L[10]} == 2'b01) && (!L[9] || ({L[8],L[9]} == 2'b01))) || (L[6] && ((!L[9] && (({L[8],L[10]} == 2'b01) || L[8])) || ({L[9],L[10]} == 2'b10))))) || (L[5] && ((!L[9] && (({L[3],L[6],L[8],L[10]} == 4'b0101) || (L[8] && ((!L[10] && (({L[3],L[6]} == 2'b01) || L[3])) || ({L[3],L[6],L[10]} == 3'b001))))) || ({L[3],L[6],L[9],L[10]} == 4'b0110))))) || ({L[3],L[6],L[7],L[8],L[9],L[10]} == 6'b111100))) || ({L[3],L[4],L[9],L[10]} == 4'b0110))) || (L[2] && ((!L[9] && ((({L[3],L[4],L[5],L[6],L[8],L[10]} == 6'b101101) && (({L[1],L[7]} == 2'b00) || ({L[1],L[7]} == 2'b11))) || (L[4] && (({L[1],L[8],L[10]} == 3'b010) || (L[1] && ((({L[8],L[10]} == 2'b01) && (({L[3],L[5],L[6],L[7]} == 4'b0111) || (L[3] && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[8] && (!L[10] || ({L[3],L[5],L[6],L[7],L[10]} == 5'b11111))))))))) || (({L[9],L[10]} == 2'b10) && ((!L[1] && (({L[3],L[4],L[5],L[6],L[7],L[8]} == 6'b001000) || (L[3] && ((!L[8] && (({L[4],L[5],L[6],L[7]} == 4'b0110) || L[4])) || ({L[4],L[5],L[7],L[8]} == 4'b0101))))) || (L[1] && ((!L[3] && ((({L[6],L[7]} == 2'b00) && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || (L[6] && (({L[4],L[8]} == 2'b00) || (L[8] && (({L[4],L[5],L[7]} == 3'b011) || L[4])))))) || (L[3] && ((({L[4],L[8]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])) || ({L[4],L[8]} == 2'b10))))))))))) || (L[0] && ((!L[10] && ((({L[8],L[9]} == 2'b01) && ((!L[3] && (!L[2] || ({L[1],L[2],L[4],L[7]} == 4'b0100))) || ({L[3],L[4]} == 2'b11))) || (L[8] && ((!L[1] && ((!L[2] && ((!L[9] && (!L[3] || (L[3] && (({L[4],L[7]} == 2'b00) || L[4])))) || ({L[3],L[9]} == 2'b01))) || (L[2] && (({L[3],L[4],L[7],L[9]} == 4'b1001) || (L[4] && (!L[9] || ({L[3],L[7],L[9]} == 3'b001))))))) || (L[1] && ((!L[3] && (({L[2],L[4]} == 2'b00) || (L[4] && (!L[9] || ({L[2],L[9]} == 2'b01))))) || ({L[3],L[4],L[9]} == 3'b110))))))) || (({L[1],L[7],L[9],L[10]} == 4'b0001) && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10)))))));
 
// action: ALU_CF = 1:
assign A_ALU_CF_1 = (!L[2] && ((!L[1] && ((!L[9] && ((!L[5] && ((!L[3] && (({L[0],L[4],L[7],L[8],L[10]} == 5'b00001) || (L[8] && (({L[0],L[4],L[6],L[10]} == 4'b0010) || (L[0] && (({L[4],L[6],L[7],L[10]} == 4'b0111) || (L[4] && (!L[10] || ({L[6],L[7],L[10]} == 3'b111))))))))) || (({L[3],L[6],L[7]} == 3'b111) && (({L[0],L[4],L[8],L[10]} == 4'b0010) || (L[0] && (({L[4],L[8],L[10]} == 3'b010) || ({L[4],L[8],L[10]} == 3'b101))))))) || (({L[5],L[8],L[10]} == 3'b110) && ((!L[3] && (({L[0],L[4],L[6]} == 3'b001) || ({L[0],L[4]} == 2'b11))) || (({L[0],L[3],L[4]} == 3'b010) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[3],L[4],L[9],L[10]} == 4'b0010) && ((!L[8] && (({L[0],L[6],L[7]} == 3'b010) || L[0])) || ({L[0],L[5],L[6],L[7],L[8]} == 5'b00101))))) || (({L[0],L[1],L[3],L[10]} == 4'b1100) && (({L[4],L[8],L[9]} == 3'b001) || ({L[4],L[8],L[9]} == 3'b110))))) || (({L[2],L[6]} == 2'b11) && (({L[0],L[1],L[3],L[4],L[5],L[7],L[8],L[9],L[10]} == 9'b001010010) || (L[7] && ((!L[1] && (({L[0],L[3],L[4],L[5],L[8],L[9],L[10]} == 7'b1110001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (!L[5] || ({L[0],L[5]} == 2'b01))) || (({L[3],L[8]} == 2'b11) && (!L[5] || ({L[0],L[5]} == 2'b01))))) || ({L[0],L[3],L[4],L[5],L[8]} == 5'b10101))))) || (({L[0],L[1],L[5]} == 3'b011) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)))))));
 
// action: ALU_CF = ALUC:
assign A_ALU_CF_ALUC = ({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b0111010) || (({L[0],L[4],L[9],L[10]} == 4'b1110) && ((!L[2] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))) || ({L[2],L[3],L[8]} == 3'b110)));
 
// action: ALU_B = NOT SB:
assign A_ALU_B_NOTSB = (({L[0],L[1],L[2],L[4],L[6],L[10]} == 6'b000000) && ((!L[7] && ((!L[5] && (({L[3],L[8],L[9]} == 3'b001) || (L[8] && (!L[9] || ({L[3],L[9]} == 2'b01))))) || ({L[3],L[5],L[9]} == 3'b011))) || ({L[3],L[5],L[7],L[8],L[9]} == 5'b10110))) || (L[6] && (({L[0],L[1],L[2],L[3],L[4],L[5],L[7],L[8],L[9],L[10]} == 10'b0001000100) || (L[7] && ((!L[9] && ((({L[2],L[4],L[8],L[10]} == 4'b0010) && (({L[0],L[1],L[3]} == 3'b000) || (L[3] && (({L[0],L[1],L[5]} == 3'b010) || (L[0] && (({L[1],L[5]} == 2'b00) || L[5])))))) || (L[10] && ((({L[0],L[1],L[2],L[5]} == 4'b0110) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || (({L[0],L[1]} == 2'b10) && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[1] && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[0],L[3],L[4],L[8]} == 4'b1011))) || ({L[0],L[1],L[3],L[4],L[5],L[8]} == 6'b010001)))))));
 
// action: ALU_OP = ORA:
assign A_ALU_OP_ORA = (!L[0] && ((({L[1],L[2],L[3],L[4],L[7]} == 5'b00000) && (({L[5],L[6],L[8],L[9],L[10]} == 5'b11110) || (L[10] && ((!L[9] && (({L[5],L[6],L[8]} == 3'b110) || (L[8] && (!L[6] || ({L[5],L[6]} == 2'b01))))) || ({L[5],L[6],L[8],L[9]} == 4'b0001))))) || (L[2] && ((({L[1],L[3],L[4],L[5],L[6],L[7]} == 6'b010110) && (({L[8],L[9],L[10]} == 3'b001) || ({L[8],L[9],L[10]} == 3'b110))) || (L[1] && ((({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[9],L[10]} == 2'b10) && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[3],L[4],L[8]} == 3'b011) && (({L[6],L[7]} == 2'b00) || L[6])))))))))) || (L[0] && ((!L[5] && ((!L[6] && ((!L[7] && ((!L[10] && ((!L[4] && (({L[1],L[2],L[3],L[8],L[9]} == 5'b01001) || (L[8] && ((!L[2] && (({L[1],L[3],L[9]} == 3'b010) || ({L[3],L[9]} == 2'b01))) || ({L[1],L[2],L[3],L[9]} == 4'b0111))))) || ({L[1],L[2],L[3],L[4],L[8],L[9]} == 6'b010111))) || (({L[1],L[9],L[10]} == 3'b001) && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || ({L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 7'b0001110))) || ({L[2],L[3],L[4],L[6],L[8],L[9],L[10]} == 7'b0001110))) || ({L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 7'b0001110)));
 
// action: ALU_A = DB:
assign A_ALU_A_DB = (!L[10] && ((({L[8],L[9]} == 2'b01) && ((({L[0],L[1],L[2],L[3],L[4]} == 5'b01100) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[4] && (({L[0],L[2],L[3]} == 3'b011) || (L[0] && (!L[2] || ({L[2],L[3]} == 2'b11))))))) || (L[8] && ((!L[0] && (({L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[9]} == 8'b00001101) || (L[2] && ((({L[3],L[4],L[9]} == 3'b101) && (({L[1],L[5],L[6],L[7]} == 4'b0110) || (L[1] && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[4] && (!L[9] || (({L[1],L[3],L[9]} == 3'b101) && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (L[0] && ((!L[2] && (!L[3] || ({L[3],L[4],L[9]} == 3'b110))) || ({L[2],L[4],L[9]} == 3'b110))))))) || (({L[0],L[10]} == 2'b01) && ((!L[9] && ((!L[7] && ((({L[1],L[4]} == 2'b00) && ((({L[2],L[3]} == 2'b00) && (({L[5],L[6],L[8]} == 3'b110) || (L[8] && (!L[6] || ({L[5],L[6]} == 2'b01))))) || ({L[2],L[3],L[5],L[6],L[8]} == 5'b11110))) || ({L[1],L[2],L[3],L[4],L[8]} == 5'b11110))) || ({L[1],L[2],L[3],L[4],L[6],L[7],L[8]} == 7'b1111110))) || ({L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9]} == 9'b000000001)));
 
// action: SB = X:
assign A_SB_X = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01100001010) || (({L[8],L[10]} == 2'b10) && ((!L[9] && ((!L[2] && ((!L[4] && (({L[0],L[1],L[3],L[5],L[6],L[7]} == 6'b011001) || ({L[0],L[3]} == 2'b10))) || ({L[0],L[1],L[3],L[4],L[5],L[6],L[7]} == 7'b0111001))) || (({L[2],L[4]} == 2'b11) && ((!L[0] && (!L[1] || (L[1] && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[0] && (!L[1] || (L[1] && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (({L[0],L[1],L[2],L[5],L[6],L[7],L[9]} == 7'b0110011) && (({L[3],L[4]} == 2'b01) || ({L[3],L[4]} == 2'b10)))));
 
// action: ALU_A = EAL:
assign A_ALU_A_EAL = (({L[0],L[1],L[2],L[3],L[8]} == 5'b00000) && (({L[4],L[5],L[6],L[7],L[9],L[10]} == 6'b000001) || ({L[4],L[9],L[10]} == 3'b110))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110110010);
 
// action: SB = PCL:
assign A_SB_PCL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100001) || ({L[0],L[1],L[2],L[3],L[4],L[8],L[9],L[10]} == 8'b00001010);
 
// action: SB = Y:
assign A_SB_Y = (({L[0],L[1],L[2],L[4],L[5],L[6],L[7],L[9],L[10]} == 9'b001000110) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (({L[4],L[10]} == 2'b10) && (({L[0],L[2],L[3],L[8],L[9]} == 5'b10001) || (L[8] && ((!L[9] && (({L[1],L[2],L[3],L[6],L[7]} == 5'b11001) || (L[3] && ((!L[2] && (({L[0],L[1],L[5],L[6],L[7]} == 5'b00001) || L[0])) || ({L[1],L[2],L[6],L[7]} == 4'b1101))))) || ({L[0],L[1],L[2],L[3],L[5],L[6],L[7],L[9]} == 8'b00100011)))));
 
// action: ALU_A = ALU:
assign A_ALU_A_ALU = (!L[3] && ((!L[4] && (({L[0],L[1],L[2],L[5],L[6],L[7],L[8],L[9],L[10]} == 9'b000010001) || (({L[9],L[10]} == 2'b10) && ((!L[2] && ((!L[8] && ((({L[0],L[1],L[7]} == 3'b000) && (({L[5],L[6]} == 2'b00) || L[6])) || L[0])) || (({L[0],L[1],L[7],L[8]} == 4'b0001) && (!L[6] || ({L[5],L[6]} == 2'b01))))) || (({L[0],L[1],L[2],L[8]} == 4'b0111) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[0],L[1],L[2],L[4],L[8],L[9],L[10]} == 7'b0111001) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[0],L[1],L[2],L[3],L[9],L[10]} == 6'b011101) && ((({L[4],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[4],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6]))));
 
// action: ALU_A = S:
assign A_ALU_A_S = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100010) || (({L[0],L[1],L[2],L[4],L[7],L[8],L[9],L[10]} == 8'b00000100) && ((!L[3] && (({L[5],L[6]} == 2'b00) || L[6])) || L[3]));
 
// action: CF <= IR[5]:
assign E_CF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011000010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011100010);
 
// action: IF <= IR[5]:
assign E_IF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011010010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011110010);
 
// action: DF <= IR[5]:
assign E_DF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011011010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011111010);
 
// action: VF <= 0:
assign E_VF__0 = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011101010);
 
// action: T <= 0 IF NF != IR[5]:
assign E_T__0IFNF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001000100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001100100);
 
// action: T <= 0 IF VF != IR[5]:
assign E_T__0IFVF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001010100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001110100);
 
// action: T <= 0 IF CF != IR[5]:
assign E_T__0IFCF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001001100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001101100);
 
// action: T <= 0 IF ZF == IR[5]:
assign E_T__0IFZF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001011100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001111100);
 
// action: EA <= DB:
assign E_EA__DB = ({L[0],L[2],L[3],L[8],L[9],L[10]} == 6'b010100) || ({L[0],L[3],L[8],L[9],L[10]} == 5'b10100);
 
// action: EAL <= DB:
assign E_EAL__DB = (({L[0],L[1],L[2],L[3],L[8],L[9],L[10]} == 7'b0000100) && (({L[4],L[5],L[6],L[7]} == 4'b0100) || L[4])) || (({L[3],L[8],L[9],L[10]} == 4'b1100) && (({L[0],L[2],L[4]} == 3'b101) || L[2]));
 
// action: PCL <= RES:
assign E_PCL__RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000110110) || ({L[0],L[1],L[2],L[3],L[4],L[8],L[9],L[10]} == 8'b00001010);
 
// action: T <= 0 IF_C7F:
assign E_T__0IF_C7F = ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000010010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000011010);
 
// action: ALU_A = SIGN:
assign A_ALU_A_SIGN = ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000010110) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000011110);
 
// action: SB = PCH:
assign A_SB_PCH = ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000010110) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000011110);
 
// action: PCH <= RES:
assign E_PCH__RES = (({L[0],L[1],L[2],L[3]} == 4'b0000) && ((!L[7] && (({L[4],L[8],L[9],L[10]} == 4'b1110) || (({L[4],L[10]} == 2'b01) && ((!L[9] && (({L[5],L[6],L[8]} == 3'b011) || (L[5] && (({L[6],L[8]} == 2'b01) || ({L[6],L[8]} == 2'b10))))) || ({L[5],L[6],L[8],L[9]} == 4'b0001))))) || ({L[4],L[7],L[8],L[9],L[10]} == 5'b11110))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110110001);
 
// action: EAH <= DB:
assign E_EAH__DB = (!L[8] && (({L[0],L[2],L[3],L[4],L[9],L[10]} == 6'b100001) || (({L[3],L[9],L[10]} == 3'b110) && (({L[0],L[2],L[4]} == 3'b101) || L[2])))) || ({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b1001110);
 
// action: EAL <= ALU:
assign E_EAL__ALU = (({L[2],L[3],L[4],L[9],L[10]} == 5'b00001) && (({L[0],L[1],L[5],L[6],L[7],L[8]} == 6'b000001) || ({L[0],L[8]} == 2'b10))) || (({L[9],L[10]} == 2'b10) && ((({L[0],L[2]} == 2'b01) && (({L[1],L[3],L[4],L[5],L[6],L[7],L[8]} == 7'b0101101) || ({L[4],L[8]} == 2'b10))) || (L[0] && ((!L[2] && (!L[3] || ({L[3],L[4],L[8]} == 3'b110))) || ({L[2],L[4],L[8]} == 3'b110)))));
 
// action: T <= T + 1 IF_ALUCZ:
assign E_T__T_1IF_ALUCZ = (({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b0111010) && ((({L[1],L[5]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[5] && ((!L[6] && (({L[1],L[7]} == 2'b00) || L[7])) || ({L[1],L[6]} == 2'b01))))) || (({L[0],L[4],L[9],L[10]} == 4'b1110) && ((!L[2] && ((({L[3],L[8]} == 2'b01) && (({L[1],L[7]} == 2'b00) || (L[7] && (({L[5],L[6]} == 2'b01) || L[5])))) || (({L[3],L[8]} == 2'b10) && (({L[1],L[7]} == 2'b00) || (L[7] && (({L[5],L[6]} == 2'b01) || L[5])))))) || (({L[2],L[3],L[8]} == 3'b110) && ((({L[1],L[5]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[5] && (({L[1],L[7]} == 2'b00) || L[7]))))));
 
// action: EAH <= ALU:
assign E_EAH__ALU = ({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b0111110) || (({L[0],L[4]} == 2'b11) && ((!L[2] && (({L[3],L[8],L[9],L[10]} == 4'b0001) || ({L[3],L[8],L[9],L[10]} == 4'b1110))) || ({L[2],L[3],L[8],L[9],L[10]} == 5'b11110)));
 
// action: PCL <= ALU:
assign E_PCL__ALU = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000011) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110110001);
 
// action: SB = DB:
assign A_SB_DB = (!L[1] && ((!L[9] && ((!L[2] && ((({L[0],L[3],L[4],L[7],L[8],L[10]} == 6'b000110) && (({L[5],L[6]} == 2'b01) || L[5])) || (L[0] && ((({L[3],L[4],L[8],L[10]} == 4'b1101) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])) || (L[8] && ((!L[4] && ((({L[3],L[10]} == 2'b01) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])) || (({L[3],L[10]} == 2'b10) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))) || (({L[3],L[4],L[10]} == 3'b011) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))))) || (({L[2],L[3],L[4],L[8],L[10]} == 5'b11101) && (({L[0],L[5],L[6],L[7]} == 4'b0101) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))) || (({L[9],L[10]} == 2'b10) && (({L[0],L[2],L[3],L[4],L[5],L[7],L[8]} == 7'b0010101) || (L[2] && ((!L[3] && ((({L[4],L[8]} == 2'b00) && ((!L[0] && (({L[5],L[6],L[7]} == 3'b011) || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))) || (({L[4],L[8]} == 2'b11) && (({L[0],L[5],L[6],L[7]} == 4'b0101) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))) || (({L[3],L[4],L[8]} == 3'b101) && ((!L[0] && (({L[5],L[6],L[7]} == 3'b011) || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))))))) || (({L[1],L[5],L[7]} == 3'b111) && ((!L[6] && ((({L[2],L[8],L[9]} == 3'b010) && (({L[0],L[3],L[4],L[10]} == 4'b0000) || (L[0] && ((!L[4] && (({L[3],L[10]} == 2'b01) || ({L[3],L[10]} == 2'b10))) || ({L[3],L[4],L[10]} == 3'b011))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101))))))) || ({L[0],L[2],L[3],L[4],L[6],L[8],L[9],L[10]} == 8'b10101100)));
 
// action: AC <= SB:
assign E_AC__SB = (({L[6],L[7]} == 2'b01) && ((({L[0],L[2],L[3],L[5],L[8],L[9],L[10]} == 7'b0010100) && (({L[1],L[4]} == 2'b01) || ({L[1],L[4]} == 2'b10))) || (({L[0],L[5]} == 2'b11) && ((!L[9] && ((!L[2] && (({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) || (L[8] && ((!L[4] && (({L[3],L[10]} == 2'b01) || ({L[3],L[10]} == 2'b10))) || ({L[3],L[4],L[10]} == 3'b011))))) || ({L[2],L[3],L[4],L[8],L[10]} == 5'b11101))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101))))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010110110);
 
// action: ALU_A = AC:
assign A_ALU_A_AC = (!L[1] && ((({L[0],L[2],L[4],L[5],L[6],L[7],L[9],L[10]} == 8'b01010010) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (L[0] && ((!L[9] && ((({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[10] && ((({L[2],L[3],L[4],L[8]} == 4'b0001) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[4] && ((({L[2],L[3],L[8]} == 3'b001) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b10) && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[3],L[4],L[8]} == 3'b011) && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (({L[1],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b1010100) && (({L[0],L[7]} == 2'b00) || ({L[0],L[5],L[6],L[7]} == 4'b1111)));
 
// action: AC <= RES:
assign E_AC__RES = ({L[0],L[1],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 9'b010100100) || (L[0] && ((!L[9] && ((!L[2] && ((({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))) || (L[8] && ((!L[4] && ((({L[1],L[3],L[10]} == 3'b001) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))) || (({L[3],L[10]} == 2'b10) && (({L[1],L[5],L[7]} == 3'b000) || (L[5] && (({L[1],L[6],L[7]} == 3'b000) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))))))) || (({L[1],L[3],L[4],L[10]} == 4'b0011) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))))))) || (({L[1],L[2],L[3],L[4],L[8],L[10]} == 6'b011101) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))))) || (({L[1],L[2],L[9],L[10]} == 4'b0110) && ((!L[4] && ((!L[7] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (({L[5],L[6],L[7]} == 3'b111) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))))) || (({L[3],L[4],L[8]} == 3'b011) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111)))))));
 
// action: ALU_OP = AND:
assign A_ALU_OP_AND = (({L[0],L[1],L[2],L[4],L[5],L[6],L[7],L[9],L[10]} == 9'b001010010) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (({L[0],L[1],L[5],L[6],L[7]} == 5'b10100) && ((!L[9] && (({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) || (L[10] && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)))));
 
// action: ALU_OP = EOR:
assign A_ALU_OP_EOR = (({L[0],L[1],L[5],L[6],L[7],L[9]} == 6'b100100) && (({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) || (L[10] && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || (({L[0],L[1],L[2],L[5],L[6],L[7],L[9],L[10]} == 8'b10101010) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)));
 
// action: ALU_A = X:
assign A_ALU_A_X = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010011100) || (({L[0],L[1],L[4],L[5],L[6],L[7],L[10]} == 7'b0001110) && (({L[2],L[3],L[8],L[9]} == 4'b1001) || (L[8] && (({L[2],L[3],L[9]} == 3'b000) || (L[3] && (({L[2],L[9]} == 2'b00) || ({L[2],L[9]} == 2'b11)))))));
 
// action: ALU_A = Y:
assign A_ALU_A_Y = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010001100) || (({L[0],L[1],L[4],L[5],L[6],L[7],L[10]} == 7'b0000110) && (({L[2],L[3],L[8],L[9]} == 4'b1001) || (L[8] && (({L[2],L[3],L[9]} == 3'b000) || (L[3] && (({L[2],L[9]} == 2'b00) || ({L[2],L[9]} == 2'b11)))))));
 
// action: ALU_DF = D:
assign A_ALU_DF_D = (({L[0],L[5],L[6],L[9]} == 4'b1110) && ((!L[2] && (({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) || (L[8] && ((!L[4] && (({L[1],L[3],L[10]} == 3'b001) || (({L[3],L[10]} == 2'b10) && (({L[1],L[7]} == 2'b00) || L[7])))) || ({L[1],L[3],L[4],L[10]} == 4'b0011))))) || ({L[1],L[2],L[3],L[4],L[8],L[10]} == 6'b011101))) || (({L[0],L[1],L[2],L[5],L[6],L[9],L[10]} == 7'b1011110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)));
 
// action: ALU_CF = C:
assign A_ALU_CF_C = (({L[0],L[1],L[5],L[6]} == 4'b1011) && ((!L[9] && (({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) || (L[10] && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))) || (L[1] && ((({L[0],L[7]} == 2'b00) && (({L[2],L[3],L[4],L[8],L[9],L[10]} == 6'b010100) || (L[2] && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110))))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b1010111100)));
 
// action: ALU_OP = ASL:
assign A_ALU_OP_ASL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010000100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011000) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: RW = W:
assign A_RW_W = (!L[1] && ((!L[6] && ((!L[5] && ((({L[0],L[2],L[4],L[7]} == 4'b0000) && ((!L[8] && (({L[3],L[9],L[10]} == 3'b001) || ({L[9],L[10]} == 2'b10))) || ({L[3],L[8],L[9],L[10]} == 4'b0110))) || (L[7] && ((({L[0],L[2],L[9],L[10]} == 4'b0110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))) || (L[0] && ((({L[2],L[9],L[10]} == 3'b001) && (({L[3],L[4],L[8]} == 3'b001) || (L[4] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))))))))) || (({L[0],L[2],L[3],L[4],L[5],L[7]} == 6'b000010) && (({L[8],L[9],L[10]} == 3'b001) || ({L[8],L[9],L[10]} == 3'b110))))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b0010010010))) || (({L[0],L[1],L[2]} == 3'b011) && ((({L[9],L[10]} == 2'b01) && ((({L[6],L[7]} == 2'b00) && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || (L[6] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))))) || (L[9] && ((!L[10] && ((!L[4] && (({L[3],L[5],L[6],L[7],L[8]} == 5'b00010) || (L[8] && ((!L[5] && ((!L[6] && (({L[3],L[7]} == 2'b00) || ({L[3],L[7]} == 2'b11))) || ({L[3],L[6]} == 2'b01))) || (({L[3],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || ({L[3],L[4],L[5],L[6],L[7],L[8]} == 6'b010011))) || (({L[3],L[4],L[8],L[10]} == 4'b1101) && (({L[6],L[7]} == 2'b00) || L[6]))))));
 
// action: SB = ALU:
assign A_SB_ALU = ({L[0],L[1],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 9'b011000110) || (({L[0],L[1],L[2],L[7],L[10]} == 5'b01101) && ((!L[9] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || ({L[3],L[4],L[8],L[9]} == 4'b1101)));
 
// action: DB <= SB:
assign E_DB__SB = (!L[1] && ((!L[5] && ((!L[6] && (({L[0],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 8'b00100010) || (L[7] && ((({L[0],L[2],L[9],L[10]} == 4'b0110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))) || (L[0] && ((({L[2],L[9],L[10]} == 3'b001) && (({L[3],L[4],L[8]} == 3'b001) || (L[4] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))))))))) || ({L[0],L[2],L[3],L[4],L[6],L[7],L[8],L[9],L[10]} == 9'b001010010))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b0000100001))) || (({L[0],L[1],L[2]} == 3'b011) && ((!L[7] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b00110) || (L[10] && ((!L[9] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || ({L[3],L[4],L[8],L[9]} == 4'b1101))))) || (({L[5],L[6],L[7],L[9],L[10]} == 5'b00110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)))));
 
// action: ALU_OP = LSR:
assign A_ALU_OP_LSR = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010010100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011010) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: ALU_OP = ROL:
assign A_ALU_OP_ROL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010100100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011100) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: ALU_OP = ROR:
assign A_ALU_OP_ROR = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010110100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011110) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: SB = AC:
assign A_SB_AC = (!L[1] && ((!L[5] && (({L[0],L[2],L[3],L[4],L[6],L[7],L[8],L[9],L[10]} == 9'b001010010) || (({L[0],L[6],L[7]} == 3'b101) && ((({L[2],L[9],L[10]} == 3'b001) && (({L[3],L[4],L[8]} == 3'b001) || (L[4] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))))))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b0010101100))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010101100);
 
// action: X <= SB:
assign E_X__SB = (({L[1],L[2],L[5],L[6],L[7],L[8],L[9]} == 7'b1010110) && ((!L[10] && (({L[0],L[3],L[4]} == 3'b000) || (L[3] && (!L[4] || ({L[0],L[4]} == 2'b01))))) || ({L[0],L[3],L[10]} == 3'b101))) || (({L[1],L[2],L[5],L[6],L[7]} == 5'b11101) && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101)))));
 
// action: Y <= SB:
assign E_Y__SB = (({L[0],L[1],L[5],L[6],L[7],L[10]} == 6'b001010) && ((!L[4] && (({L[2],L[3],L[8],L[9]} == 4'b1001) || (L[8] && (({L[2],L[3],L[9]} == 3'b000) || (L[3] && (({L[2],L[9]} == 2'b00) || ({L[2],L[9]} == 2'b11))))))) || ({L[2],L[3],L[4],L[8],L[9]} == 5'b10111))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00111101001);
 
// action: SB = S:
assign A_SB_S = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01011101100);
 
// action: S <= SB:
assign E_S__SB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01011001100);
 
// action: PC <= EA:
assign E_PC__EA = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110010110);
 
// action: S <= ALU:
assign E_S__ALU = (({L[0],L[1],L[2],L[4],L[7],L[8]} == 6'b000000) && ((({L[3],L[9],L[10]} == 3'b001) && (!L[6] || ({L[5],L[6]} == 2'b01))) || (({L[9],L[10]} == 2'b10) && ((!L[3] && (({L[5],L[6]} == 2'b00) || L[6])) || L[3])))) || ({L[0],L[1],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 9'b000000110);
 
// action: SB = P:
assign A_SB_P = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010000010);
 
// action: P <= SB:
assign E_P__SB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010100110);
 
// action: X <= RES:
assign E_X__RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010111100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010011100);
 
// action: Y <= RES:
assign E_Y__RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010001100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010011100);
 
// action: DB <= ALU:
assign E_DB__ALU = ({L[0],L[1],L[2],L[3],L[4],L[6],L[7],L[8],L[9],L[10]} == 10'b0110011110) || (({L[0],L[1],L[2],L[6],L[7],L[10]} == 6'b011111) && ((!L[9] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || ({L[3],L[4],L[8],L[9]} == 4'b1101)));
 
// action: DB <= PCH:
assign E_DB__PCH = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100110);
 
// action: PCL <= EAL:
assign E_PCL__EAL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100101);
 
// action: DB <= PCL:
assign E_DB__PCL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000110);
 
// action: DB <= P:
assign E_DB__P = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000001);
 
// action: P <= DB:
assign E_P__DB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000010110);
 
// action: PCL <= DB:
assign E_PCL__DB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000010001);
/ag_6502/trunk/ag_6502/ag_6502.v
0,0 → 1,344
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 10:50:36 02/15/2012
// Design Name:
// Module Name: ag_6502
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
// Specify following define to allow external
// clocking for phi1 and phi2
// In such case you may use ag6502_ext_clock module
// with baseclk frequency ~ 10 x phi_0
`define AG6502_EXTERNAL_CLOCK
 
 
`ifndef AG6502_EXTERNAL_CLOCK
module ag6502_clock(input phi_0, output phi_1, output phi_2);
wire phi_01;
not#3(phi_1,phi_0);
or(phi_01,~phi_0, phi_1);
not#1(phi_2, phi_01);
endmodule
 
 
`else
 
module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
parameter DELAY = 1; // delay in semi-waves of baseclk
initial phi_1 = 0;
integer cnt = 0;
always @(posedge baseclk) begin
if (phi_0 != phi_1) begin
if (!cnt) begin phi_1 <= ~phi_1; cnt <= DELAY; end
else cnt <= cnt - 1;
end
end
endmodule
 
// baseclk is used to simulate delays on a real hardware
module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
parameter DELAY1 = 3, DELAY2 = 1; // delays in semi-waves of baseclk
wire phi_1_neg, phi_01;
ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
assign phi_1 = ~phi_1_neg;
and(phi_01, phi_0, phi_1_neg);
ag6502_phase_shift#DELAY2 d2(baseclk, phi_01, phi_2);
endmodule
 
`endif
 
 
`define ALU_ORA 3'd0
`define ALU_AND 3'd1
`define ALU_EOR 3'd2
`define ALU_ADC 3'd3
`define ALU_ASL 3'd4
`define ALU_LSR 3'd5
`define ALU_ROL 3'd6
`define ALU_ROR 3'd7
 
 
module ag6502_decimal(ADD, D_IN, NEG, CORR);
input wire[4:0] ADD;
input wire D_IN, NEG;
output wire[4:0] CORR;
wire C9 = {ADD[4]^NEG, ADD[3:0]} > 5'd9;
assign CORR = D_IN?{C9^NEG, C9?ADD[3:0] + (NEG?4'd10:4'd6): ADD[3:0]}: ADD;
endmodule
 
 
module ag6502_alu(A, B, OP, NEG, C_IN, D_IN, R, C_OUT, V_OUT);
input wire[7:0] A, B;
input wire[2:0] OP;
input wire C_IN, D_IN, NEG;
output wire[7:0] R;
output wire C_OUT, V_OUT;
wire[4:0] ADD_L;
ag6502_decimal DL({1'b0, A[3:0]} + {1'b0, B[3:0]} + C_IN, D_IN, NEG, ADD_L);
wire CF_H = ADD_L[4];
 
wire[4:0] ADD_H;
ag6502_decimal DH({1'b0, A[7:4]} + {1'b0, B[7:4]} + CF_H, D_IN, NEG, ADD_H);
 
assign
{C_OUT,R} = (OP==`ALU_ORA)? A | B:
(OP==`ALU_AND)? A & B:
(OP==`ALU_EOR)? A ^ B:
(OP==`ALU_ADC)? {ADD_H, ADD_L[3:0]}:
(OP==`ALU_ASL)? {A[7], A[6:0], 1'b0}:
(OP==`ALU_LSR)? {A[0], 1'b0, A[7:1]}:
(OP==`ALU_ROL)? {A[7], A[6:0], C_IN}:
(OP==`ALU_ROR)? {A[0], C_IN, A[7:1]}:
8'bX;
assign V_OUT = (A[7] == B[7]) && (A[7] != R[7]);
endmodule
 
/*
System AB/DB discipline:
1. For CPU
Phi1 up => CPU set ab/db_out buses
Phi2 down => CPU reads data from db_in
2. For Memory / other devices
Phi2 up => perform read/write operation
*/
 
 
module ag6502(input phi_0,
`ifdef AG6502_EXTERNAL_CLOCK
input phi_1, input phi_2,
`else
output phi_1, output phi_2,
`endif
output reg[15:0] ab,
output wire read,
input[7:0] db_in, output reg[7:0] db_out,
input rdy,
input rst, input irq, input nmi,
input so,
output sync);
`ifndef AG6502_EXTERNAL_CLOCK
ag6502_clock cgen(phi_0, phi_1, phi_2);
`endif
 
reg rdyg = 1;
reg[2:0] T = 7;
reg[7:0] IR ='h18;
reg[15:0] PC = 0;
wire[7:0] PCH = PC[15:8], PCL = PC[7:0];
reg[7:0] EAL, EAH;
wire[15:0] EA = {EAH, EAL};
reg FLAG_C, FLAG_Z, FLAG_I, FLAG_D, FLAG_B, FLAG_V, FLAG_N;
reg[7:0] AC, X, Y, S = 0;
wire[7:0] P = {FLAG_N, FLAG_V, 1'b1, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C};
wire[7:0] SB;
wire[7:0] ALU_A, ALU_B;
wire[7:0] RES;
wire[2:0] ALU_OP;
reg[8:0] eALU; // with carry
wire[7:0] ALU = eALU;
wire ALU_CF = eALU[8];
wire CF_IN, DF_IN;
wire CF_OUT, VF_OUT;
reg so_prev = 0;
reg nmi_prev = 0;
wire irq_active = ~irq & ~FLAG_I;
wire nmi_active = ~nmi & nmi_prev;
wire int_active = irq_active | nmi_active;
wire rst_active = ~rst;
wire so_active = so & ~so_prev;
wire[1:0] vec_bits=
nmi_active?2'b01:
rst_active?2'b10:
2'b11;
wire[15:0] vec_addr = {{13{1'b1}}, vec_bits, 1'b0};
wire[7:0] IR_eff = int_active?8'b0:IR;
wire[10:0] L = {T, IR_eff};
`include "states.v"
assign read = ~A_RW_W;
assign sync = !T;
assign SB = A_SB_DB? db_in:
A_SB_AC? AC:
A_SB_X? X:
A_SB_Y? Y:
A_SB_S? S:
A_SB_P? P:
A_SB_ALU? ALU:
A_SB_0? 8'b0:
A_SB_PCH? PCH:
A_SB_PCL? PCL:
8'bX;
assign CF_IN = A_ALU_CF_0? 1'b0:
A_ALU_CF_1? 1'b1:
A_ALU_CF_ALUC? ALU_CF:
FLAG_C;
assign DF_IN = A_ALU_DF_D? FLAG_D: 1'b0;
assign ALU_A =
A_ALU_A_AC? AC:
A_ALU_A_X? X:
A_ALU_A_Y? Y:
A_ALU_A_DB? db_in:
A_ALU_A_EAL? EAL:
A_ALU_A_ALU? ALU:
A_ALU_A_S? S:
A_ALU_A_SIGN? (EAL[7]?8'b11111111:8'b00000001):
8'bX;
assign ALU_B = A_ALU_B_SB? SB:
A_ALU_B_NOTSB? ~SB:
8'bX;
 
assign ALU_OP = A_ALU_OP_ADC? `ALU_ADC:
A_ALU_OP_ORA? `ALU_ORA:
A_ALU_OP_EOR? `ALU_EOR:
A_ALU_OP_AND? `ALU_AND:
A_ALU_OP_ASL? `ALU_ASL:
A_ALU_OP_LSR? `ALU_LSR:
A_ALU_OP_ROL? `ALU_ROL:
A_ALU_OP_ROR? `ALU_ROR:
8'bX;
 
ag6502_alu alu(ALU_A, ALU_B, ALU_OP, A_ALU_B_NOTSB, CF_IN, DF_IN, RES, CF_OUT, VF_OUT);
always @(posedge phi_1) begin
if (E_AB__PC) ab <= PC;
else if (E_AB__EA) ab <= EA;
else if (E_AB__S) ab <= {8'b1, S};
 
if (E_DB__SB) db_out <= SB;
else if (E_DB__PCH) db_out <= PCH;
else if (E_DB__PCL) db_out <= PCL;
else if (E_DB__P) db_out <= P;
else if (E_DB__ALU) db_out <= ALU;
if (read) rdyg <= rdy;
end
 
 
wire cond;
assign cond =
E_T__0IFNF__IR_5_?(FLAG_N != IR[5]):
E_T__0IFVF__IR_5_?(FLAG_V != IR[5]):
E_T__0IFCF__IR_5_?(FLAG_C != IR[5]):
E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
E_T__0IF_C7F? CF_OUT == EAL[7]:
E_T__0;
always @(negedge phi_2) if (rdyg) begin
if (E_PC__PC_1) PC <= PC + 1;
else if (E_PC__EA) PC <= EA;
else begin
if (E_PCH__RES) PC[15:8] <= RES;
if (E_PCL__ALU) PC[7:0] <= ALU;
else if (E_PCL__RES) PC[7:0] <= RES;
else if (E_PCL__EAL) PC[7:0] <= EAL;
else if (E_PCL__DB) PC[7:0] <= db_in;
end
if (!T) begin
IR <= db_in;
if (!db_in) begin // BRK instruction
{EAH, EAL} <= vec_addr;
end
nmi_prev <= nmi;
end
if (E_N_Z__SB) begin FLAG_Z <= !SB; FLAG_N <= SB[7]; end
else if (E_N_Z__RES) begin FLAG_Z <= !RES; FLAG_N <= RES[7]; end
else if (E_N_Z__SB_RES) begin FLAG_Z <= !RES; FLAG_N <= SB[7]; end
if (E_C__RES) FLAG_C <= CF_OUT;
if (E_V__RES) FLAG_V <= VF_OUT;
else if (E_V__SB_6_) FLAG_V <= SB[6];
if (E_EAL__DB) EAL <= db_in;
else if (E_EAL__ALU) EAL <= ALU;
 
if (E_EA__DB) {EAH, EAL} <= { 8'b0, db_in };
else if (E_EAH__DB) EAH <= db_in;
else if (E_EAH__ALU) EAH <= ALU;
if (E_AC__SB) AC <= SB;
else if (E_AC__RES) AC <= RES;
if (E_S__ALU) S <= ALU;
if (E_X__SB) X <= SB;
else if (E_X__RES) X <= RES;
if (E_Y__SB) Y <= SB;
else if (E_Y__RES) Y <= RES;
if (E_S__SB) S <= SB;
if (E_P__SB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {SB[7], SB[6], SB[4], SB[3], SB[2], SB[1], SB[0]};
else if (E_P__DB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {db_in[7], db_in[6], db_in[4], db_in[3], db_in[2], db_in[1], db_in[0]};
if (E_CF__IR_5_) FLAG_C <= IR[5];
if (E_IF__IR_5_) FLAG_I <= IR[5];
if (E_DF__IR_5_) FLAG_D <= IR[5];
if (E_VF__0) FLAG_V <= 0;
else if (so_active) FLAG_V <= 1;
so_prev <= so;
eALU <= {CF_OUT, RES};
if (cond) begin
T <= 0;
if (!IR_eff) begin
FLAG_B <= !IR;
FLAG_I <= 1;
end
end else T <= T + ((E_T__T_1IF_ALUCZ && !ALU_CF)?2: 1);
 
if (rst_active) begin
T <= 1;
IR <= 0;
{EAH, EAL} <= vec_addr;
end
end
 
 
endmodule
 
/ag_6502/trunk/agat7/ag_main.v
0,0 → 1,135
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 15:09:47 01/19/2012
// Design Name:
// Module Name: ag_main
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module ROM2kx8(input[10:0] adr, input cs, output[7:0] DO);
reg[7:0] mem[0:2047];
assign DO = cs?mem[adr]:8'bZ;
initial begin
`include "monitor7.v"
end
endmodule
 
module ag_main(
input clk50,
input[3:0] btns,
output[7:0] leds,
output[3:0] controls,
output[4:0] vga_bus,
input[1:0] ps2_bus_in
);
 
// assign leds = 0;
// assign controls = 0;
// assign vga_bus = 0;
wire clk1, clk10;
clk_div#5 cd5(clk50, clk10);
clk_div#10 cd10(clk10, clk1);
 
wire clk_vram;
wire[13:0] AB2;
wire[15:0] DI2;
wire [15:0] AB; // address bus
wire [7:0] DI; // data in, read bus
wire [7:0] DO; // data out, write bus
wire read;
wire rom_cs, ram_cs;
wire phi_1, phi_2;
RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
clk_vram, AB2, 1, DI2);
ROM2kx8 rom1(AB[10:0], rom_cs, DI);
wire [3:0] AB_HH = AB[15:12];
wire [3:0] AB_HL = AB[11:8];
wire [3:0] AB_LH = AB[7:4];
wire [3:0] AB_LL = AB[3:0];
wire [7:0] AB_H = AB[15:8];
wire [7:0] AB_L = AB[7:0];
wire AB_CXXX = (AB_HH == 4'hC);
wire AB_FXXX = (AB_HH == 4'hF);
wire AB_C0XX = AB_CXXX && !AB_HL;
wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
assign ram_cs = !AB[15];
 
reg reset_auto = 1;
wire reset;
wire WE = ~read; // write enable
supply0 IRQ; // interrupt request
supply0 NMI; // non-maskable interrupt request
supply1 RDY; // Ready signal. Pauses CPU when RDY=0
supply1 SO; // Set Overflow, not used.
wire SYNC;
reg[7:0] vmode = 0;
wire[7:0] key_reg;
wire key_rus;
reg key_clear = 0;
wire key_rst, key_pause;
reg beep_reg = 0, tape_out_reg = 0;
 
assign reset = btns[0];
assign leds = AB[11:4];
assign controls = {1'b0, beep_reg ^ tape_out_reg, tape_out_reg, beep_reg};
 
ag_video video(clk50, vmode, clk_vram, AB2, DI2, vga_bus);
wire[1:0] ps2_bus;
signal_filter sf1(clk1, ps2_bus_in[0], ps2_bus[0]);
signal_filter sf2(clk1, ps2_bus_in[1], ps2_bus[1]);
 
 
ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
assign DI = (AB_C00X && !WE)?key_reg:8'bZ;
always @(posedge phi_2) begin
key_clear <= AB_C01X;
if (AB_C02X) tape_out_reg <= ~tape_out_reg;
if (AB_C03X) beep_reg <= ~beep_reg;
if (AB_C7XX) vmode <= AB_L;
end
always @(posedge vga_bus[0]) begin
reset_auto <= 0;
end
ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
RDY & ~key_pause, ~(reset | reset_auto | key_rst), ~IRQ, ~NMI, SO, SYNC);
 
endmodule
/ag_6502/trunk/agat7/clkdiv.v
0,0 → 1,37
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:20:37 02/23/2012
// Design Name:
// Module Name: clkdiv
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module clk_div(input clk, output clk1);
parameter divide = 16;
wire clk0;
 
DCM_SP #(
.CLKDV_DIVIDE(divide) // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
) DCM_SP_inst (
.CLKDV(clk1), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
.CLK0(clk0),
.CLKFB(clk0),
.RST(0)
);
 
endmodule
/ag_6502/trunk/agat7/chip1.ucf
0,0 → 1,62
 
 
NET "b1" LOC = D18;
NET "b2" LOC = K17;
 
NET "b1" PULLDOWN;
NET "b2" PULLDOWN;
 
NET "b1" CLOCK_DEDICATED_ROUTE = FALSE;
NET "b2" CLOCK_DEDICATED_ROUTE = FALSE;
NET "rot_a" CLOCK_DEDICATED_ROUTE = FALSE;
NET "rot_b" CLOCK_DEDICATED_ROUTE = FALSE;
NET "rot_center" CLOCK_DEDICATED_ROUTE = FALSE;
 
NET "clk" LOC = C9 | IOSTANDARD = "LVCMOS33";
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
//PIN "cpu1/cd5/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
NET "ROT_A" LOC = K18 | IOSTANDARD = "LVTTL" | PULLUP;
NET "ROT_B" LOC = G18 | IOSTANDARD = "LVTTL" | PULLUP;
NET "ROT_CENTER" LOC = V16 | IOSTANDARD = "LVTTL" | PULLDOWN;
 
NET "LED<7>" LOC = F9 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<6>" LOC = E9 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<5>" LOC = D11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<4>" LOC = C11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<3>" LOC = F11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<2>" LOC = E11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<1>" LOC = E12 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<0>" LOC = F12 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
 
NET "VGA_RED" LOC = H14 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_GREEN" LOC = H15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_BLUE" LOC = G15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_HSYNC" LOC = F15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_VSYNC" LOC = F14 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
 
NET "J4<0>" LOC = D7 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
NET "J4<1>" LOC = C7 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
NET "J4<2>" LOC = F8 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
NET "J4<3>" LOC = E8 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
#Created by Constraints Editor (xc3s500e-fg320-4) - 2012/01/19
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
 
#NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = T4 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "SPI_MISO" LOC = N10 | IOSTANDARD = "LVCMOS33";
NET "SPI_SCK" LOC = U16 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "DAC_CS" LOC = N8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "DAC_CLR" LOC = P8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
 
NET "spi_amp_cs" LOC = N7 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "spi_rom_cs" LOC = U3 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "platformflash_oe" LOC = T3 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "strataflash_oe" LOC = C18 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "strataflash_ce" LOC = D16 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "strataflash_we" LOC = D17 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "spi_adc_conv" LOC = P11 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
 
NET "PS2_CLK" LOC = G14 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
NET "PS2_DATA" LOC = G13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
NET "PS2_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
/ag_6502/trunk/agat7/ag_video.v
0,0 → 1,173
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 11:44:32 02/24/2012
// Design Name:
// Module Name: ag_video
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
module FONT_ROM(input[10:0] adr, input cs, output[7:0] DO);
reg[7:0] mem[0:2047];
assign DO = cs?mem[adr]:8'bZ;
initial begin
`include "agathe7.v"
end
endmodule
 
 
module ag_video(input clk50,
input[7:0] vmode,
output clk_vram,
output[13:0] AB2, input[15:0] DI2,
output[4:0] vga_bus);
parameter
HGR_WHITE = 4'b1111, // RGBX
HGR_BLACK = 4'b0000,
TEXT_COLOR= 4'b1111,
TEXT_BACK = 4'b0000;
wire clk25;
assign clk_vram = ~clk25;
wire[0:15] rDI2 = DI2;
// assign AB2 = 14'b0;
clk_div#2 cd2(clk50, clk25);
wire [9:0] hpos;
wire [8:0] vpos;
wire video_on;
reg[8:0] hpos1;
reg[7:0] vpos1;
wire[1:0] VTYPE = vmode[1:0];
// for 64K+ - variant
// wire[2:0] PAGE_ADDR = {vmode[6], vmode[6]? 1'b0: vmode[5], vmode[4]};
// for 32K-variant
wire[2:0] PAGE_ADDR = {0, vmode[5], vmode[4]};
wire[1:0] SUBPAGE_ADDR = vmode[3:2];
wire VTYPE_HGR = (VTYPE == 2'b11);
wire VTYPE_MGR = (VTYPE == 2'b01);
wire VTYPE_LGR = (VTYPE == 2'b00);
wire VTYPE_TXT = (VTYPE == 2'b10);
wire VTYPE_T32 = VTYPE_TXT && !vmode[7];
wire VTYPE_T64 = VTYPE_TXT && vmode[7];
wire VTYPE_T64_INV = VTYPE_T64 && !SUBPAGE_ADDR[0];
wire[13:0] HGR_ADDR = {PAGE_ADDR[1:0], vpos1, hpos1[8:5]};
wire[3:0] HGR_BITNO = hpos1[4:1];
wire HGR_BIT = rDI2[HGR_BITNO];
wire[3:0] HGR_COLOR = HGR_BIT? HGR_WHITE: HGR_BLACK;
 
wire[13:0] MGR_ADDR = {PAGE_ADDR[1:0], vpos1[7:1], hpos1[8:4]};
wire[1:0] MGR_BLOCKNO = hpos1[3:2];
 
wire[13:0] LGR_ADDR = {PAGE_ADDR[1:0], SUBPAGE_ADDR, vpos1[7:2], hpos1[8:5]};
wire[1:0] LGR_BLOCKNO = hpos1[4:3];
wire[1:0] GR_BLOCKNO = VTYPE_MGR?MGR_BLOCKNO:
LGR_BLOCKNO;
wire[3:0] GR_COLOR = (GR_BLOCKNO == 2'b00)? {DI2[12], DI2[13], DI2[14], DI2[15]}:
(GR_BLOCKNO == 2'b01)? {DI2[8], DI2[9], DI2[10], DI2[11]}:
(GR_BLOCKNO == 2'b10)? {DI2[4], DI2[5], DI2[6], DI2[7]}:
{DI2[0], DI2[1], DI2[2], DI2[3]};
 
wire[13:0] TEXT_ADDR = {PAGE_ADDR[1:0], SUBPAGE_ADDR, vpos1[7:3], hpos1[8:4]};
wire h_phase = hpos1[1:0]?0:1;
reg[0:0] h_cnt = 0;
wire[0:0] h_delay = h_phase?1'd1:1'd0;
wire v_phase = vpos1[2:0]?1:0;
reg[0:0] v_cnt = 0;
wire[0:0] v_delay = v_phase?1'd1:1'd0;
wire[7:0] font_char;
wire[2:0] font_y, font_x;
wire[10:0] font_ab = {font_char, font_y};
wire[0:7] font_db;
wire font_pix = font_db[font_x];
 
FONT_ROM font(font_ab, 1, font_db);
integer flash_cnt = 0;
reg flash_reg = 0;
wire inverse = VTYPE_T64?VTYPE_T64_INV:!{DI2[5],DI2[3]},
flash = VTYPE_T64?font_db[7]:!{DI2[5],~DI2[3]};
wire inv_mode = inverse || (flash && flash_reg);
 
assign font_x = VTYPE_T64?hpos1[2:0]:hpos1[3:1];
assign font_y = vpos1[2:0];
assign font_char = (VTYPE_T64 && hpos1[3])? DI2[7:0]: DI2[15:8];
wire[3:0] T_COLOR = VTYPE_T64? TEXT_COLOR: {DI2[0], DI2[1], DI2[2], DI2[4]};
 
assign AB2 = VTYPE_HGR? HGR_ADDR:
VTYPE_MGR? MGR_ADDR:
VTYPE_LGR? LGR_ADDR:
TEXT_ADDR;
wire[2:0] color = VTYPE_HGR? HGR_COLOR[3:1]:
(VTYPE_MGR | VTYPE_LGR)? GR_COLOR[3:1]:
((font_pix^inv_mode)?T_COLOR[3:1]: TEXT_BACK);
reg[2:0] color_reg;
always @(posedge clk25) begin
if (!vga_bus[1]) begin
hpos1 <= 0;
h_cnt <= 1;
end else if (video_on) begin
if (!h_cnt) begin
h_cnt <= h_delay;
hpos1 <= hpos1 + 1;
end else h_cnt <= h_cnt - 1;
end
end
always @(posedge clk25) color_reg <= color;
always @(posedge video_on) begin
if (!vpos) begin
vpos1 <= 0;
v_cnt <= 1;
end else begin
if (!v_cnt) begin
v_cnt <= v_delay;
vpos1 <= vpos1 + 1;
end else v_cnt <= v_cnt - 1;
end
end
always @(posedge vga_bus[0]) begin
if (flash_cnt) flash_cnt <= flash_cnt - 1;
else begin
flash_cnt <= 11;
flash_reg <= ~flash_reg;
end
end
assign {vga_bus[4], vga_bus[3], vga_bus[2]} = video_on?color_reg:3'b000;
video_counters cnt(clk25, vga_bus[0], vga_bus[1], video_on, hpos, vpos);
endmodule
/ag_6502/trunk/agat7/monitor7.v
0,0 → 1,2048
mem['h000] = 'h48;
mem['h001] = 'h4A;
mem['h002] = 'h4A;
mem['h003] = 'h4A;
mem['h004] = 'h4A;
mem['h005] = 'hA8;
mem['h006] = 'h68;
mem['h007] = 'h59;
mem['h008] = 'h19;
mem['h009] = 'hF8;
mem['h00A] = 'hC9;
mem['h00B] = 'hA0;
mem['h00C] = 'hB0;
mem['h00D] = 'h08;
mem['h00E] = 'hC9;
mem['h00F] = 'h90;
mem['h010] = 'h90;
mem['h011] = 'h04;
mem['h012] = 'hA8;
mem['h013] = 'hB9;
mem['h014] = 'h91;
mem['h015] = 'hF7;
mem['h016] = 'hA4;
mem['h017] = 'h24;
mem['h018] = 'h60;
mem['h019] = 'h80;
mem['h01A] = 'hB0;
mem['h01B] = 'hD0;
mem['h01C] = 'hD0;
mem['h01D] = 'hD0;
mem['h01E] = 'hE0;
mem['h01F] = 'hB0;
mem['h020] = 'hB0;
mem['h021] = 'h88;
mem['h022] = 'hA0;
mem['h023] = 'h8D;
mem['h024] = 'h93;
mem['h025] = 'h94;
mem['h026] = 'h98;
mem['h027] = 'h96;
mem['h028] = 'h97;
mem['h029] = 'h95;
mem['h02A] = 'h99;
mem['h02B] = 'h9A;
mem['h02C] = 'h9B;
mem['h02D] = 'h9C;
mem['h02E] = 'h9D;
mem['h02F] = 'h9E;
mem['h030] = 'h9B;
mem['h031] = 'h86;
mem['h032] = 'h2C;
mem['h033] = 'hBC;
mem['h034] = 'h5A;
mem['h035] = 'hF8;
mem['h036] = 'h0A;
mem['h037] = 'h0A;
mem['h038] = 'h48;
mem['h039] = 'h0A;
mem['h03A] = 'hC9;
mem['h03B] = 'hC0;
mem['h03C] = 'h90;
mem['h03D] = 'h02;
mem['h03E] = 'hE9;
mem['h03F] = 'h3F;
mem['h040] = 'h99;
mem['h041] = 'h00;
mem['h042] = 'h00;
mem['h043] = 'h7D;
mem['h044] = 'h56;
mem['h045] = 'hF8;
mem['h046] = 'h45;
mem['h047] = 'h1E;
mem['h048] = 'h29;
mem['h049] = 'hF8;
mem['h04A] = 'h45;
mem['h04B] = 'h1E;
mem['h04C] = 'h85;
mem['h04D] = 'h1E;
mem['h04E] = 'h68;
mem['h04F] = 'h65;
mem['h050] = 'h2C;
mem['h051] = 'hAA;
mem['h052] = 'h9D;
mem['h053] = 'h00;
mem['h054] = 'hC7;
mem['h055] = 'h60;
mem['h056] = 'h08;
mem['h057] = 'h20;
mem['h058] = 'h08;
mem['h059] = 'h20;
mem['h05A] = 'hD0;
mem['h05B] = 'hD0;
mem['h05C] = 'h19;
mem['h05D] = 'hD0;
mem['h05E] = 'h29;
mem['h05F] = 'h07;
mem['h060] = 'hA8;
mem['h061] = 'hB9;
mem['h062] = 'h69;
mem['h063] = 'hF8;
mem['h064] = 'hA8;
mem['h065] = 'h99;
mem['h066] = 'hF0;
mem['h067] = 'hC0;
mem['h068] = 'h60;
mem['h069] = 'h00;
mem['h06A] = 'h01;
mem['h06B] = 'h0A;
mem['h06C] = 'h0B;
mem['h06D] = 'h06;
mem['h06E] = 'h07;
mem['h06F] = 'h02;
mem['h070] = 'h03;
mem['h071] = 'hA6;
mem['h072] = 'h3A;
mem['h073] = 'hA4;
mem['h074] = 'h3B;
mem['h075] = 'h20;
mem['h076] = 'h7D;
mem['h077] = 'hFD;
mem['h078] = 'h20;
mem['h079] = 'h5A;
mem['h07A] = 'hFF;
mem['h07B] = 'hA1;
mem['h07C] = 'h3A;
mem['h07D] = 'hA8;
mem['h07E] = 'h4A;
mem['h07F] = 'h90;
mem['h080] = 'h09;
mem['h081] = 'h6A;
mem['h082] = 'hB0;
mem['h083] = 'h15;
mem['h084] = 'hC9;
mem['h085] = 'hA2;
mem['h086] = 'hF0;
mem['h087] = 'h11;
mem['h088] = 'h29;
mem['h089] = 'h87;
mem['h08A] = 'h4A;
mem['h08B] = 'hAA;
mem['h08C] = 'hBD;
mem['h08D] = 'h48;
mem['h08E] = 'hF9;
mem['h08F] = 'hB0;
mem['h090] = 'h04;
mem['h091] = 'h4A;
mem['h092] = 'h4A;
mem['h093] = 'h4A;
mem['h094] = 'h4A;
mem['h095] = 'h29;
mem['h096] = 'h0F;
mem['h097] = 'hD0;
mem['h098] = 'h04;
mem['h099] = 'hA0;
mem['h09A] = 'h80;
mem['h09B] = 'hA9;
mem['h09C] = 'h00;
mem['h09D] = 'hAA;
mem['h09E] = 'hBD;
mem['h09F] = 'h8C;
mem['h0A0] = 'hF9;
mem['h0A1] = 'h85;
mem['h0A2] = 'h2E;
mem['h0A3] = 'h29;
mem['h0A4] = 'h03;
mem['h0A5] = 'h85;
mem['h0A6] = 'h2F;
mem['h0A7] = 'h98;
mem['h0A8] = 'h29;
mem['h0A9] = 'h8F;
mem['h0AA] = 'hAA;
mem['h0AB] = 'h98;
mem['h0AC] = 'hA0;
mem['h0AD] = 'h03;
mem['h0AE] = 'hE0;
mem['h0AF] = 'h8A;
mem['h0B0] = 'hF0;
mem['h0B1] = 'h0B;
mem['h0B2] = 'h4A;
mem['h0B3] = 'h90;
mem['h0B4] = 'h08;
mem['h0B5] = 'h4A;
mem['h0B6] = 'h4A;
mem['h0B7] = 'h09;
mem['h0B8] = 'h20;
mem['h0B9] = 'h88;
mem['h0BA] = 'hD0;
mem['h0BB] = 'hFA;
mem['h0BC] = 'hC8;
mem['h0BD] = 'h88;
mem['h0BE] = 'hD0;
mem['h0BF] = 'hF2;
mem['h0C0] = 'h60;
mem['h0C1] = 'h20;
mem['h0C2] = 'h71;
mem['h0C3] = 'hF8;
mem['h0C4] = 'h48;
mem['h0C5] = 'hB1;
mem['h0C6] = 'h3A;
mem['h0C7] = 'h20;
mem['h0C8] = 'hC1;
mem['h0C9] = 'hFD;
mem['h0CA] = 'hA2;
mem['h0CB] = 'h01;
mem['h0CC] = 'h20;
mem['h0CD] = 'h5C;
mem['h0CE] = 'hFF;
mem['h0CF] = 'hC4;
mem['h0D0] = 'h2F;
mem['h0D1] = 'hC8;
mem['h0D2] = 'h90;
mem['h0D3] = 'hF1;
mem['h0D4] = 'hA2;
mem['h0D5] = 'h03;
mem['h0D6] = 'hC0;
mem['h0D7] = 'h04;
mem['h0D8] = 'h90;
mem['h0D9] = 'hF2;
mem['h0DA] = 'h68;
mem['h0DB] = 'hA8;
mem['h0DC] = 'hB9;
mem['h0DD] = 'hA6;
mem['h0DE] = 'hF9;
mem['h0DF] = 'h85;
mem['h0E0] = 'h2C;
mem['h0E1] = 'hB9;
mem['h0E2] = 'hE6;
mem['h0E3] = 'hF9;
mem['h0E4] = 'h85;
mem['h0E5] = 'h2D;
mem['h0E6] = 'hA9;
mem['h0E7] = 'h00;
mem['h0E8] = 'hA0;
mem['h0E9] = 'h05;
mem['h0EA] = 'h06;
mem['h0EB] = 'h2D;
mem['h0EC] = 'h26;
mem['h0ED] = 'h2C;
mem['h0EE] = 'h2A;
mem['h0EF] = 'h88;
mem['h0F0] = 'hD0;
mem['h0F1] = 'hF8;
mem['h0F2] = 'h69;
mem['h0F3] = 'hBF;
mem['h0F4] = 'h20;
mem['h0F5] = 'hD4;
mem['h0F6] = 'hFD;
mem['h0F7] = 'hCA;
mem['h0F8] = 'hD0;
mem['h0F9] = 'hEC;
mem['h0FA] = 'h20;
mem['h0FB] = 'h5A;
mem['h0FC] = 'hFF;
mem['h0FD] = 'hA4;
mem['h0FE] = 'h2F;
mem['h0FF] = 'hA2;
mem['h100] = 'h06;
mem['h101] = 'hE0;
mem['h102] = 'h03;
mem['h103] = 'hF0;
mem['h104] = 'h1C;
mem['h105] = 'h06;
mem['h106] = 'h2E;
mem['h107] = 'h90;
mem['h108] = 'h0E;
mem['h109] = 'hBD;
mem['h10A] = 'h99;
mem['h10B] = 'hF9;
mem['h10C] = 'h20;
mem['h10D] = 'hD4;
mem['h10E] = 'hFD;
mem['h10F] = 'hBD;
mem['h110] = 'h9F;
mem['h111] = 'hF9;
mem['h112] = 'hF0;
mem['h113] = 'h03;
mem['h114] = 'h20;
mem['h115] = 'hD4;
mem['h116] = 'hFD;
mem['h117] = 'hCA;
mem['h118] = 'hD0;
mem['h119] = 'hE7;
mem['h11A] = 'h60;
mem['h11B] = 'h88;
mem['h11C] = 'h30;
mem['h11D] = 'hE7;
mem['h11E] = 'h20;
mem['h11F] = 'hC1;
mem['h120] = 'hFD;
mem['h121] = 'hA5;
mem['h122] = 'h2E;
mem['h123] = 'hC9;
mem['h124] = 'hE8;
mem['h125] = 'hB1;
mem['h126] = 'h3A;
mem['h127] = 'h90;
mem['h128] = 'hF2;
mem['h129] = 'h20;
mem['h12A] = 'h3C;
mem['h12B] = 'hF9;
mem['h12C] = 'hAA;
mem['h12D] = 'hE8;
mem['h12E] = 'hD0;
mem['h12F] = 'h01;
mem['h130] = 'hC8;
mem['h131] = 'h98;
mem['h132] = 'h20;
mem['h133] = 'hC1;
mem['h134] = 'hFD;
mem['h135] = 'h8A;
mem['h136] = 'h4C;
mem['h137] = 'hC1;
mem['h138] = 'hFD;
mem['h139] = 'h38;
mem['h13A] = 'hA5;
mem['h13B] = 'h2F;
mem['h13C] = 'hA4;
mem['h13D] = 'h3B;
mem['h13E] = 'hAA;
mem['h13F] = 'h10;
mem['h140] = 'h01;
mem['h141] = 'h88;
mem['h142] = 'h65;
mem['h143] = 'h3A;
mem['h144] = 'h90;
mem['h145] = 'h01;
mem['h146] = 'hC8;
mem['h147] = 'h60;
mem['h148] = 'h40;
mem['h149] = 'h02;
mem['h14A] = 'h45;
mem['h14B] = 'h03;
mem['h14C] = 'hD0;
mem['h14D] = 'h08;
mem['h14E] = 'h40;
mem['h14F] = 'h09;
mem['h150] = 'h30;
mem['h151] = 'h22;
mem['h152] = 'h45;
mem['h153] = 'h33;
mem['h154] = 'hD0;
mem['h155] = 'h08;
mem['h156] = 'h40;
mem['h157] = 'h09;
mem['h158] = 'h40;
mem['h159] = 'h02;
mem['h15A] = 'h45;
mem['h15B] = 'h33;
mem['h15C] = 'hD0;
mem['h15D] = 'h08;
mem['h15E] = 'h40;
mem['h15F] = 'h09;
mem['h160] = 'h40;
mem['h161] = 'h02;
mem['h162] = 'h45;
mem['h163] = 'hB3;
mem['h164] = 'hD0;
mem['h165] = 'h08;
mem['h166] = 'h40;
mem['h167] = 'h09;
mem['h168] = 'h00;
mem['h169] = 'h22;
mem['h16A] = 'h44;
mem['h16B] = 'h33;
mem['h16C] = 'hD0;
mem['h16D] = 'h8C;
mem['h16E] = 'h44;
mem['h16F] = 'h00;
mem['h170] = 'h11;
mem['h171] = 'h22;
mem['h172] = 'h44;
mem['h173] = 'h33;
mem['h174] = 'hD0;
mem['h175] = 'h8C;
mem['h176] = 'h44;
mem['h177] = 'h9A;
mem['h178] = 'h10;
mem['h179] = 'h22;
mem['h17A] = 'h44;
mem['h17B] = 'h33;
mem['h17C] = 'hD0;
mem['h17D] = 'h08;
mem['h17E] = 'h40;
mem['h17F] = 'h09;
mem['h180] = 'h10;
mem['h181] = 'h22;
mem['h182] = 'h44;
mem['h183] = 'h33;
mem['h184] = 'hD0;
mem['h185] = 'h08;
mem['h186] = 'h40;
mem['h187] = 'h09;
mem['h188] = 'h62;
mem['h189] = 'h13;
mem['h18A] = 'h78;
mem['h18B] = 'hA9;
mem['h18C] = 'h00;
mem['h18D] = 'h21;
mem['h18E] = 'h81;
mem['h18F] = 'h82;
mem['h190] = 'h00;
mem['h191] = 'h00;
mem['h192] = 'h59;
mem['h193] = 'h4D;
mem['h194] = 'h91;
mem['h195] = 'h92;
mem['h196] = 'h86;
mem['h197] = 'h4A;
mem['h198] = 'h85;
mem['h199] = 'h9D;
mem['h19A] = 'hAC;
mem['h19B] = 'hA9;
mem['h19C] = 'hAC;
mem['h19D] = 'hA3;
mem['h19E] = 'hA8;
mem['h19F] = 'hA4;
mem['h1A0] = 'hD9;
mem['h1A1] = 'h00;
mem['h1A2] = 'hD8;
mem['h1A3] = 'hA4;
mem['h1A4] = 'hA4;
mem['h1A5] = 'h00;
mem['h1A6] = 'h1C;
mem['h1A7] = 'h8A;
mem['h1A8] = 'h1C;
mem['h1A9] = 'h23;
mem['h1AA] = 'h5D;
mem['h1AB] = 'h8B;
mem['h1AC] = 'h1B;
mem['h1AD] = 'hA1;
mem['h1AE] = 'h9D;
mem['h1AF] = 'h8A;
mem['h1B0] = 'h1D;
mem['h1B1] = 'h23;
mem['h1B2] = 'h9D;
mem['h1B3] = 'h8B;
mem['h1B4] = 'h1D;
mem['h1B5] = 'hA1;
mem['h1B6] = 'h00;
mem['h1B7] = 'h29;
mem['h1B8] = 'h19;
mem['h1B9] = 'hAE;
mem['h1BA] = 'h69;
mem['h1BB] = 'hA8;
mem['h1BC] = 'h19;
mem['h1BD] = 'h23;
mem['h1BE] = 'h24;
mem['h1BF] = 'h53;
mem['h1C0] = 'h1B;
mem['h1C1] = 'h23;
mem['h1C2] = 'h24;
mem['h1C3] = 'h53;
mem['h1C4] = 'h19;
mem['h1C5] = 'hA1;
mem['h1C6] = 'h00;
mem['h1C7] = 'h1A;
mem['h1C8] = 'h5B;
mem['h1C9] = 'h5B;
mem['h1CA] = 'hA5;
mem['h1CB] = 'h69;
mem['h1CC] = 'h24;
mem['h1CD] = 'h24;
mem['h1CE] = 'hAE;
mem['h1CF] = 'hAE;
mem['h1D0] = 'hA8;
mem['h1D1] = 'hAD;
mem['h1D2] = 'h29;
mem['h1D3] = 'h00;
mem['h1D4] = 'h7C;
mem['h1D5] = 'h00;
mem['h1D6] = 'h15;
mem['h1D7] = 'h9C;
mem['h1D8] = 'h6D;
mem['h1D9] = 'h9C;
mem['h1DA] = 'hA5;
mem['h1DB] = 'h69;
mem['h1DC] = 'h29;
mem['h1DD] = 'h53;
mem['h1DE] = 'h84;
mem['h1DF] = 'h13;
mem['h1E0] = 'h34;
mem['h1E1] = 'h11;
mem['h1E2] = 'hA5;
mem['h1E3] = 'h69;
mem['h1E4] = 'h23;
mem['h1E5] = 'hA0;
mem['h1E6] = 'hD8;
mem['h1E7] = 'h62;
mem['h1E8] = 'h5A;
mem['h1E9] = 'h48;
mem['h1EA] = 'h26;
mem['h1EB] = 'h62;
mem['h1EC] = 'h94;
mem['h1ED] = 'h88;
mem['h1EE] = 'h54;
mem['h1EF] = 'h44;
mem['h1F0] = 'hC8;
mem['h1F1] = 'h54;
mem['h1F2] = 'h68;
mem['h1F3] = 'h44;
mem['h1F4] = 'hE8;
mem['h1F5] = 'h94;
mem['h1F6] = 'h00;
mem['h1F7] = 'hB4;
mem['h1F8] = 'h08;
mem['h1F9] = 'h84;
mem['h1FA] = 'h74;
mem['h1FB] = 'hB4;
mem['h1FC] = 'h28;
mem['h1FD] = 'h6E;
mem['h1FE] = 'h74;
mem['h1FF] = 'hF4;
mem['h200] = 'hCC;
mem['h201] = 'h4A;
mem['h202] = 'h72;
mem['h203] = 'hF2;
mem['h204] = 'hA4;
mem['h205] = 'h8A;
mem['h206] = 'h00;
mem['h207] = 'hAA;
mem['h208] = 'hA2;
mem['h209] = 'hA2;
mem['h20A] = 'h74;
mem['h20B] = 'h74;
mem['h20C] = 'h74;
mem['h20D] = 'h72;
mem['h20E] = 'h44;
mem['h20F] = 'h68;
mem['h210] = 'hB2;
mem['h211] = 'h32;
mem['h212] = 'hB2;
mem['h213] = 'h00;
mem['h214] = 'h22;
mem['h215] = 'h00;
mem['h216] = 'h1A;
mem['h217] = 'h1A;
mem['h218] = 'h26;
mem['h219] = 'h26;
mem['h21A] = 'h72;
mem['h21B] = 'h72;
mem['h21C] = 'h88;
mem['h21D] = 'hC8;
mem['h21E] = 'hC4;
mem['h21F] = 'hCA;
mem['h220] = 'h26;
mem['h221] = 'h48;
mem['h222] = 'h44;
mem['h223] = 'h44;
mem['h224] = 'hA2;
mem['h225] = 'hC8;
mem['h226] = 'h85;
mem['h227] = 'h45;
mem['h228] = 'h68;
mem['h229] = 'h48;
mem['h22A] = 'h0A;
mem['h22B] = 'h0A;
mem['h22C] = 'h0A;
mem['h22D] = 'h30;
mem['h22E] = 'h03;
mem['h22F] = 'h6C;
mem['h230] = 'hFE;
mem['h231] = 'h03;
mem['h232] = 'h28;
mem['h233] = 'h20;
mem['h234] = 'h4D;
mem['h235] = 'hFF;
mem['h236] = 'h68;
mem['h237] = 'h85;
mem['h238] = 'h3A;
mem['h239] = 'h68;
mem['h23A] = 'h85;
mem['h23B] = 'h3B;
mem['h23C] = 'h6C;
mem['h23D] = 'hF0;
mem['h23E] = 'h03;
mem['h23F] = 'h20;
mem['h240] = 'h71;
mem['h241] = 'hF8;
mem['h242] = 'h20;
mem['h243] = 'hD0;
mem['h244] = 'hFA;
mem['h245] = 'h4C;
mem['h246] = 'h65;
mem['h247] = 'hFF;
mem['h248] = 'hD8;
mem['h249] = 'h20;
mem['h24A] = 'h7B;
mem['h24B] = 'hFE;
mem['h24C] = 'h20;
mem['h24D] = 'h3C;
mem['h24E] = 'hFB;
mem['h24F] = 'h20;
mem['h250] = 'h8A;
mem['h251] = 'hFE;
mem['h252] = 'h20;
mem['h253] = 'h80;
mem['h254] = 'hFE;
mem['h255] = 'h2C;
mem['h256] = 'h10;
mem['h257] = 'hC0;
mem['h258] = 'hD8;
mem['h259] = 'h20;
mem['h25A] = 'h3B;
mem['h25B] = 'hFF;
mem['h25C] = 'hAD;
mem['h25D] = 'hF3;
mem['h25E] = 'h03;
mem['h25F] = 'h49;
mem['h260] = 'hA5;
mem['h261] = 'hCD;
mem['h262] = 'hF4;
mem['h263] = 'h03;
mem['h264] = 'hD0;
mem['h265] = 'h1C;
mem['h266] = 'h20;
mem['h267] = 'h2E;
mem['h268] = 'hFB;
mem['h269] = 'hAD;
mem['h26A] = 'hF2;
mem['h26B] = 'h03;
mem['h26C] = 'hC9;
mem['h26D] = 'h69;
mem['h26E] = 'hD0;
mem['h26F] = 'h0F;
mem['h270] = 'hA9;
mem['h271] = 'hFF;
mem['h272] = 'hCD;
mem['h273] = 'hF3;
mem['h274] = 'h03;
mem['h275] = 'hD0;
mem['h276] = 'h08;
mem['h277] = 'hA0;
mem['h278] = 'h69;
mem['h279] = 'h8C;
mem['h27A] = 'hF2;
mem['h27B] = 'h03;
mem['h27C] = 'h4C;
mem['h27D] = 'h69;
mem['h27E] = 'hFF;
mem['h27F] = 'h6C;
mem['h280] = 'hF2;
mem['h281] = 'h03;
mem['h282] = 'h2C;
mem['h283] = 'hF1;
mem['h284] = 'hC0;
mem['h285] = 'hA0;
mem['h286] = 'h00;
mem['h287] = 'h84;
mem['h288] = 'h1E;
mem['h289] = 'hA9;
mem['h28A] = 'h0F;
mem['h28B] = 'hA2;
mem['h28C] = 'h02;
mem['h28D] = 'h20;
mem['h28E] = 'h31;
mem['h28F] = 'hF8;
mem['h290] = 'h20;
mem['h291] = 'h3B;
mem['h292] = 'hFC;
mem['h293] = 'hA0;
mem['h294] = 'h14;
mem['h295] = 'hB9;
mem['h296] = 'hFE;
mem['h297] = 'hFA;
mem['h298] = 'h99;
mem['h299] = 'h0F;
mem['h29A] = 'h78;
mem['h29B] = 'h88;
mem['h29C] = 'hD0;
mem['h29D] = 'hF7;
mem['h29E] = 'h2C;
mem['h29F] = 'hF0;
mem['h2A0] = 'hC0;
mem['h2A1] = 'hA2;
mem['h2A2] = 'h05;
mem['h2A3] = 'hBD;
mem['h2A4] = 'hF2;
mem['h2A5] = 'hFA;
mem['h2A6] = 'h9D;
mem['h2A7] = 'hEF;
mem['h2A8] = 'h03;
mem['h2A9] = 'hCA;
mem['h2AA] = 'hD0;
mem['h2AB] = 'hF7;
mem['h2AC] = 'hA9;
mem['h2AD] = 'hC7;
mem['h2AE] = 'h86;
mem['h2AF] = 'h00;
mem['h2B0] = 'h85;
mem['h2B1] = 'h01;
mem['h2B2] = 'hA0;
mem['h2B3] = 'h07;
mem['h2B4] = 'hC6;
mem['h2B5] = 'h01;
mem['h2B6] = 'hA5;
mem['h2B7] = 'h01;
mem['h2B8] = 'hC9;
mem['h2B9] = 'hC0;
mem['h2BA] = 'hF0;
mem['h2BB] = 'hBB;
mem['h2BC] = 'h8D;
mem['h2BD] = 'hF8;
mem['h2BE] = 'h07;
mem['h2BF] = 'hB1;
mem['h2C0] = 'h00;
mem['h2C1] = 'hD9;
mem['h2C2] = 'hF7;
mem['h2C3] = 'hFA;
mem['h2C4] = 'hD0;
mem['h2C5] = 'hEC;
mem['h2C6] = 'h88;
mem['h2C7] = 'h88;
mem['h2C8] = 'h10;
mem['h2C9] = 'hF5;
mem['h2CA] = 'h6C;
mem['h2CB] = 'h00;
mem['h2CC] = 'h00;
mem['h2CD] = 'h20;
mem['h2CE] = 'h75;
mem['h2CF] = 'hFD;
mem['h2D0] = 'hA9;
mem['h2D1] = 'h45;
mem['h2D2] = 'h85;
mem['h2D3] = 'h40;
mem['h2D4] = 'hA9;
mem['h2D5] = 'h00;
mem['h2D6] = 'h85;
mem['h2D7] = 'h41;
mem['h2D8] = 'hA2;
mem['h2D9] = 'hFB;
mem['h2DA] = 'hA9;
mem['h2DB] = 'hA0;
mem['h2DC] = 'h20;
mem['h2DD] = 'hD4;
mem['h2DE] = 'hFD;
mem['h2DF] = 'hBD;
mem['h2E0] = 'h18;
mem['h2E1] = 'hFA;
mem['h2E2] = 'h20;
mem['h2E3] = 'hD4;
mem['h2E4] = 'hFD;
mem['h2E5] = 'hA9;
mem['h2E6] = 'hBD;
mem['h2E7] = 'h20;
mem['h2E8] = 'hD4;
mem['h2E9] = 'hFD;
mem['h2EA] = 'hB5;
mem['h2EB] = 'h4A;
mem['h2EC] = 'h20;
mem['h2ED] = 'hC1;
mem['h2EE] = 'hFD;
mem['h2EF] = 'hE8;
mem['h2F0] = 'h30;
mem['h2F1] = 'hE8;
mem['h2F2] = 'h60;
mem['h2F3] = 'h3F;
mem['h2F4] = 'hFA;
mem['h2F5] = 'h69;
mem['h2F6] = 'hFF;
mem['h2F7] = 'h5A;
mem['h2F8] = 'h20;
mem['h2F9] = 'hFF;
mem['h2FA] = 'h00;
mem['h2FB] = 'hFF;
mem['h2FC] = 'h03;
mem['h2FD] = 'hFF;
mem['h2FE] = 'h3C;
mem['h2FF] = 'hAA;
mem['h300] = 'h2A;
mem['h301] = 'hAA;
mem['h302] = 'h2A;
mem['h303] = 'hA0;
mem['h304] = 'h2F;
mem['h305] = 'hE1;
mem['h306] = 'h29;
mem['h307] = 'hE7;
mem['h308] = 'h29;
mem['h309] = 'hE1;
mem['h30A] = 'h29;
mem['h30B] = 'hF4;
mem['h30C] = 'h29;
mem['h30D] = 'hA0;
mem['h30E] = 'h2F;
mem['h30F] = 'hAA;
mem['h310] = 'h2A;
mem['h311] = 'hAA;
mem['h312] = 'h2A;
mem['h313] = 'hC1;
mem['h314] = 'hD8;
mem['h315] = 'hD9;
mem['h316] = 'hD0;
mem['h317] = 'hD3;
mem['h318] = 'hAD;
mem['h319] = 'h70;
mem['h31A] = 'hC0;
mem['h31B] = 'hA0;
mem['h31C] = 'h00;
mem['h31D] = 'hEA;
mem['h31E] = 'hEA;
mem['h31F] = 'hBD;
mem['h320] = 'h64;
mem['h321] = 'hC0;
mem['h322] = 'h10;
mem['h323] = 'h07;
mem['h324] = 'hEA;
mem['h325] = 'hEA;
mem['h326] = 'hEA;
mem['h327] = 'hC8;
mem['h328] = 'hD0;
mem['h329] = 'hF5;
mem['h32A] = 'h88;
mem['h32B] = 'h60;
mem['h32C] = 'h10;
mem['h32D] = 'h08;
mem['h32E] = 'hA5;
mem['h32F] = 'h19;
mem['h330] = 'h4A;
mem['h331] = 'h90;
mem['h332] = 'h02;
mem['h333] = 'h69;
mem['h334] = 'h1F;
mem['h335] = 'h69;
mem['h336] = 'h02;
mem['h337] = 'hA8;
mem['h338] = 'h99;
mem['h339] = 'h00;
mem['h33A] = 'hC7;
mem['h33B] = 'h60;
mem['h33C] = 'hA9;
mem['h33D] = 'h00;
mem['h33E] = 'h85;
mem['h33F] = 'h48;
mem['h340] = 'h85;
mem['h341] = 'h22;
mem['h342] = 'hA9;
mem['h343] = 'h00;
mem['h344] = 'h85;
mem['h345] = 'h20;
mem['h346] = 'hA9;
mem['h347] = 'h40;
mem['h348] = 'h85;
mem['h349] = 'h21;
mem['h34A] = 'hA9;
mem['h34B] = 'h20;
mem['h34C] = 'h85;
mem['h34D] = 'h23;
mem['h34E] = 'hA9;
mem['h34F] = 'h1F;
mem['h350] = 'h85;
mem['h351] = 'h25;
mem['h352] = 'h4C;
mem['h353] = 'h2F;
mem['h354] = 'hFC;
mem['h355] = 'h20;
mem['h356] = 'h76;
mem['h357] = 'hFB;
mem['h358] = 'h20;
mem['h359] = 'h04;
mem['h35A] = 'hFD;
mem['h35B] = 'hC9;
mem['h35C] = 'h95;
mem['h35D] = 'hF0;
mem['h35E] = 'hF6;
mem['h35F] = 'hC9;
mem['h360] = 'h88;
mem['h361] = 'hF0;
mem['h362] = 'hF2;
mem['h363] = 'h20;
mem['h364] = 'h76;
mem['h365] = 'hFB;
mem['h366] = 'h20;
mem['h367] = 'h04;
mem['h368] = 'hFD;
mem['h369] = 'hC9;
mem['h36A] = 'h9B;
mem['h36B] = 'hF0;
mem['h36C] = 'hEB;
mem['h36D] = 'hC9;
mem['h36E] = 'h99;
mem['h36F] = 'hF0;
mem['h370] = 'hF2;
mem['h371] = 'hC9;
mem['h372] = 'h9A;
mem['h373] = 'hF0;
mem['h374] = 'hEE;
mem['h375] = 'h60;
mem['h376] = 'hC9;
mem['h377] = 'hA0;
mem['h378] = 'hB0;
mem['h379] = 'hFB;
mem['h37A] = 'h4C;
mem['h37B] = 'hD4;
mem['h37C] = 'hFD;
mem['h37D] = 'h85;
mem['h37E] = 'h29;
mem['h37F] = 'hA9;
mem['h380] = 'h00;
mem['h381] = 'h85;
mem['h382] = 'h28;
mem['h383] = 'h46;
mem['h384] = 'h29;
mem['h385] = 'h66;
mem['h386] = 'h28;
mem['h387] = 'h46;
mem['h388] = 'h29;
mem['h389] = 'h66;
mem['h38A] = 'h28;
mem['h38B] = 'hA5;
mem['h38C] = 'h19;
mem['h38D] = 'h29;
mem['h38E] = 'hF8;
mem['h38F] = 'h65;
mem['h390] = 'h29;
mem['h391] = 'h85;
mem['h392] = 'h29;
mem['h393] = 'h60;
mem['h394] = 'h38;
mem['h395] = 'h48;
mem['h396] = 'hE9;
mem['h397] = 'h01;
mem['h398] = 'hD0;
mem['h399] = 'hFC;
mem['h39A] = 'h68;
mem['h39B] = 'hE9;
mem['h39C] = 'h01;
mem['h39D] = 'hD0;
mem['h39E] = 'hF6;
mem['h39F] = 'h60;
mem['h3A0] = 'hE6;
mem['h3A1] = 'h42;
mem['h3A2] = 'hD0;
mem['h3A3] = 'h02;
mem['h3A4] = 'hE6;
mem['h3A5] = 'h43;
mem['h3A6] = 'hA5;
mem['h3A7] = 'h3C;
mem['h3A8] = 'hC5;
mem['h3A9] = 'h3E;
mem['h3AA] = 'hA5;
mem['h3AB] = 'h3D;
mem['h3AC] = 'hE5;
mem['h3AD] = 'h3F;
mem['h3AE] = 'hE6;
mem['h3AF] = 'h3C;
mem['h3B0] = 'hD0;
mem['h3B1] = 'h02;
mem['h3B2] = 'hE6;
mem['h3B3] = 'h3D;
mem['h3B4] = 'h60;
mem['h3B5] = 'h8D;
mem['h3B6] = 'h8A;
mem['h3B7] = 'h88;
mem['h3B8] = 'h95;
mem['h3B9] = 'h99;
mem['h3BA] = 'h9A;
mem['h3BB] = 'h8C;
mem['h3BC] = 'h9D;
mem['h3BD] = 'h9E;
mem['h3BE] = 'h87;
mem['h3BF] = 'h9C;
mem['h3C0] = 'h5B;
mem['h3C1] = 'h5B;
mem['h3C2] = 'h19;
mem['h3C3] = 'h0E;
mem['h3C4] = 'h27;
mem['h3C5] = 'h5F;
mem['h3C6] = 'h3B;
mem['h3C7] = 'h96;
mem['h3C8] = 'h45;
mem['h3C9] = 'hAE;
mem['h3CA] = 'hA7;
mem['h3CB] = 'hC9;
mem['h3CC] = 'h8D;
mem['h3CD] = 'hD0;
mem['h3CE] = 'h18;
mem['h3CF] = 'hAC;
mem['h3D0] = 'h00;
mem['h3D1] = 'hC0;
mem['h3D2] = 'h10;
mem['h3D3] = 'h13;
mem['h3D4] = 'h2C;
mem['h3D5] = 'h10;
mem['h3D6] = 'hC0;
mem['h3D7] = 'hC0;
mem['h3D8] = 'hA0;
mem['h3D9] = 'hD0;
mem['h3DA] = 'h0C;
mem['h3DB] = 'hAC;
mem['h3DC] = 'h00;
mem['h3DD] = 'hC0;
mem['h3DE] = 'h10;
mem['h3DF] = 'hFB;
mem['h3E0] = 'hC0;
mem['h3E1] = 'h83;
mem['h3E2] = 'hF0;
mem['h3E3] = 'h03;
mem['h3E4] = 'h2C;
mem['h3E5] = 'h10;
mem['h3E6] = 'hC0;
mem['h3E7] = 'hC9;
mem['h3E8] = 'hA0;
mem['h3E9] = 'hB0;
mem['h3EA] = 'h1A;
mem['h3EB] = 'hA8;
mem['h3EC] = 'h10;
mem['h3ED] = 'h17;
mem['h3EE] = 'hA0;
mem['h3EF] = 'h0A;
mem['h3F0] = 'hD9;
mem['h3F1] = 'hB5;
mem['h3F2] = 'hFB;
mem['h3F3] = 'hF0;
mem['h3F4] = 'h04;
mem['h3F5] = 'h88;
mem['h3F6] = 'h10;
mem['h3F7] = 'hF8;
mem['h3F8] = 'h60;
mem['h3F9] = 'hB9;
mem['h3FA] = 'hC0;
mem['h3FB] = 'hFB;
mem['h3FC] = 'h85;
mem['h3FD] = 'h2A;
mem['h3FE] = 'hA9;
mem['h3FF] = 'hFC;
mem['h400] = 'h85;
mem['h401] = 'h2B;
mem['h402] = 'h6C;
mem['h403] = 'h2A;
mem['h404] = 'h00;
mem['h405] = 'hA4;
mem['h406] = 'h24;
mem['h407] = 'h91;
mem['h408] = 'h28;
mem['h409] = 'hC8;
mem['h40A] = 'hA5;
mem['h40B] = 'h32;
mem['h40C] = 'h91;
mem['h40D] = 'h28;
mem['h40E] = 'hE6;
mem['h40F] = 'h24;
mem['h410] = 'hE6;
mem['h411] = 'h24;
mem['h412] = 'hA5;
mem['h413] = 'h24;
mem['h414] = 'hC5;
mem['h415] = 'h21;
mem['h416] = 'hB0;
mem['h417] = 'h43;
mem['h418] = 'h60;
mem['h419] = 'hC6;
mem['h41A] = 'h24;
mem['h41B] = 'hC6;
mem['h41C] = 'h24;
mem['h41D] = 'h10;
mem['h41E] = 'hF9;
mem['h41F] = 'hA5;
mem['h420] = 'h21;
mem['h421] = 'h85;
mem['h422] = 'h24;
mem['h423] = 'hC6;
mem['h424] = 'h24;
mem['h425] = 'hC6;
mem['h426] = 'h24;
mem['h427] = 'hA5;
mem['h428] = 'h22;
mem['h429] = 'hC5;
mem['h42A] = 'h25;
mem['h42B] = 'hB0;
mem['h42C] = 'h0D;
mem['h42D] = 'hC6;
mem['h42E] = 'h25;
mem['h42F] = 'hA5;
mem['h430] = 'h25;
mem['h431] = 'h20;
mem['h432] = 'h7D;
mem['h433] = 'hFB;
mem['h434] = 'hA5;
mem['h435] = 'h28;
mem['h436] = 'h65;
mem['h437] = 'h20;
mem['h438] = 'h85;
mem['h439] = 'h28;
mem['h43A] = 'h60;
mem['h43B] = 'hA5;
mem['h43C] = 'h22;
mem['h43D] = 'h85;
mem['h43E] = 'h25;
mem['h43F] = 'hA0;
mem['h440] = 'h00;
mem['h441] = 'h84;
mem['h442] = 'h24;
mem['h443] = 'hF0;
mem['h444] = 'h04;
mem['h445] = 'hA4;
mem['h446] = 'h24;
mem['h447] = 'hA5;
mem['h448] = 'h25;
mem['h449] = 'h48;
mem['h44A] = 'h20;
mem['h44B] = 'h31;
mem['h44C] = 'hFC;
mem['h44D] = 'h20;
mem['h44E] = 'h98;
mem['h44F] = 'hFC;
mem['h450] = 'hA0;
mem['h451] = 'h00;
mem['h452] = 'h68;
mem['h453] = 'h69;
mem['h454] = 'h00;
mem['h455] = 'hC5;
mem['h456] = 'h23;
mem['h457] = 'h90;
mem['h458] = 'hF0;
mem['h459] = 'hB0;
mem['h45A] = 'hD4;
mem['h45B] = 'hA9;
mem['h45C] = 'h00;
mem['h45D] = 'h85;
mem['h45E] = 'h24;
mem['h45F] = 'hE6;
mem['h460] = 'h25;
mem['h461] = 'hA5;
mem['h462] = 'h25;
mem['h463] = 'hC5;
mem['h464] = 'h23;
mem['h465] = 'h90;
mem['h466] = 'hCA;
mem['h467] = 'hC6;
mem['h468] = 'h25;
mem['h469] = 'hA5;
mem['h46A] = 'h22;
mem['h46B] = 'h48;
mem['h46C] = 'h20;
mem['h46D] = 'h31;
mem['h46E] = 'hFC;
mem['h46F] = 'hA5;
mem['h470] = 'h28;
mem['h471] = 'h85;
mem['h472] = 'h2A;
mem['h473] = 'hA5;
mem['h474] = 'h29;
mem['h475] = 'h85;
mem['h476] = 'h2B;
mem['h477] = 'hA4;
mem['h478] = 'h21;
mem['h479] = 'h88;
mem['h47A] = 'h68;
mem['h47B] = 'h69;
mem['h47C] = 'h01;
mem['h47D] = 'hC5;
mem['h47E] = 'h23;
mem['h47F] = 'hB0;
mem['h480] = 'h0D;
mem['h481] = 'h48;
mem['h482] = 'h20;
mem['h483] = 'h31;
mem['h484] = 'hFC;
mem['h485] = 'hB1;
mem['h486] = 'h28;
mem['h487] = 'h91;
mem['h488] = 'h2A;
mem['h489] = 'h88;
mem['h48A] = 'h10;
mem['h48B] = 'hF9;
mem['h48C] = 'h30;
mem['h48D] = 'hE1;
mem['h48E] = 'hA0;
mem['h48F] = 'h00;
mem['h490] = 'h20;
mem['h491] = 'h98;
mem['h492] = 'hFC;
mem['h493] = 'h4C;
mem['h494] = 'h2F;
mem['h495] = 'hFC;
mem['h496] = 'hA4;
mem['h497] = 'h24;
mem['h498] = 'hA9;
mem['h499] = 'hA0;
mem['h49A] = 'h91;
mem['h49B] = 'h28;
mem['h49C] = 'hC8;
mem['h49D] = 'hA5;
mem['h49E] = 'h32;
mem['h49F] = 'h91;
mem['h4A0] = 'h28;
mem['h4A1] = 'hC8;
mem['h4A2] = 'hC4;
mem['h4A3] = 'h21;
mem['h4A4] = 'h90;
mem['h4A5] = 'hF2;
mem['h4A6] = 'h60;
mem['h4A7] = 'hA5;
mem['h4A8] = 'h32;
mem['h4A9] = 'h49;
mem['h4AA] = 'h80;
mem['h4AB] = 'h85;
mem['h4AC] = 'h32;
mem['h4AD] = 'h60;
mem['h4AE] = 'hA9;
mem['h4AF] = 'h40;
mem['h4B0] = 'h20;
mem['h4B1] = 'h94;
mem['h4B2] = 'hFB;
mem['h4B3] = 'hA0;
mem['h4B4] = 'hC0;
mem['h4B5] = 'hA9;
mem['h4B6] = 'h0C;
mem['h4B7] = 'h20;
mem['h4B8] = 'h94;
mem['h4B9] = 'hFB;
mem['h4BA] = 'hAD;
mem['h4BB] = 'h30;
mem['h4BC] = 'hC0;
mem['h4BD] = 'h88;
mem['h4BE] = 'hD0;
mem['h4BF] = 'hF5;
mem['h4C0] = 'h60;
mem['h4C1] = 'hA0;
mem['h4C2] = 'h4B;
mem['h4C3] = 'h20;
mem['h4C4] = 'hD3;
mem['h4C5] = 'hFC;
mem['h4C6] = 'hD0;
mem['h4C7] = 'hF9;
mem['h4C8] = 'h69;
mem['h4C9] = 'hFE;
mem['h4CA] = 'hB0;
mem['h4CB] = 'hF5;
mem['h4CC] = 'hA0;
mem['h4CD] = 'h21;
mem['h4CE] = 'h20;
mem['h4CF] = 'hD3;
mem['h4D0] = 'hFC;
mem['h4D1] = 'hC8;
mem['h4D2] = 'hC8;
mem['h4D3] = 'h88;
mem['h4D4] = 'hD0;
mem['h4D5] = 'hFD;
mem['h4D6] = 'h90;
mem['h4D7] = 'h05;
mem['h4D8] = 'hA0;
mem['h4D9] = 'h32;
mem['h4DA] = 'h88;
mem['h4DB] = 'hD0;
mem['h4DC] = 'hFD;
mem['h4DD] = 'hAC;
mem['h4DE] = 'h20;
mem['h4DF] = 'hC0;
mem['h4E0] = 'hA0;
mem['h4E1] = 'h2C;
mem['h4E2] = 'hCA;
mem['h4E3] = 'h60;
mem['h4E4] = 'hA2;
mem['h4E5] = 'h08;
mem['h4E6] = 'h48;
mem['h4E7] = 'h20;
mem['h4E8] = 'hF2;
mem['h4E9] = 'hFC;
mem['h4EA] = 'h68;
mem['h4EB] = 'h2A;
mem['h4EC] = 'hA0;
mem['h4ED] = 'h3A;
mem['h4EE] = 'hCA;
mem['h4EF] = 'hD0;
mem['h4F0] = 'hF5;
mem['h4F1] = 'h60;
mem['h4F2] = 'h20;
mem['h4F3] = 'hF5;
mem['h4F4] = 'hFC;
mem['h4F5] = 'h88;
mem['h4F6] = 'hAD;
mem['h4F7] = 'h60;
mem['h4F8] = 'hC0;
mem['h4F9] = 'h45;
mem['h4FA] = 'h2F;
mem['h4FB] = 'h10;
mem['h4FC] = 'hF8;
mem['h4FD] = 'h45;
mem['h4FE] = 'h2F;
mem['h4FF] = 'h85;
mem['h500] = 'h2F;
mem['h501] = 'hC0;
mem['h502] = 'h80;
mem['h503] = 'h60;
mem['h504] = 'h6C;
mem['h505] = 'h38;
mem['h506] = 'h00;
mem['h507] = 'hA5;
mem['h508] = 'h19;
mem['h509] = 'h20;
mem['h50A] = 'h5E;
mem['h50B] = 'hF8;
mem['h50C] = 'hA4;
mem['h50D] = 'h24;
mem['h50E] = 'hB1;
mem['h50F] = 'h28;
mem['h510] = 'h85;
mem['h511] = 'h35;
mem['h512] = 'hC8;
mem['h513] = 'hB1;
mem['h514] = 'h28;
mem['h515] = 'h48;
mem['h516] = 'hA9;
mem['h517] = 'h0F;
mem['h518] = 'h91;
mem['h519] = 'h28;
mem['h51A] = 'h68;
mem['h51B] = 'hE6;
mem['h51C] = 'h4E;
mem['h51D] = 'hD0;
mem['h51E] = 'h02;
mem['h51F] = 'hE6;
mem['h520] = 'h4F;
mem['h521] = 'h2C;
mem['h522] = 'h00;
mem['h523] = 'hC0;
mem['h524] = 'h10;
mem['h525] = 'hF5;
mem['h526] = 'h91;
mem['h527] = 'h28;
mem['h528] = 'hA5;
mem['h529] = 'h1E;
mem['h52A] = 'h20;
mem['h52B] = 'h5E;
mem['h52C] = 'hF8;
mem['h52D] = 'hAD;
mem['h52E] = 'h00;
mem['h52F] = 'hC0;
mem['h530] = 'h09;
mem['h531] = 'h80;
mem['h532] = 'h2C;
mem['h533] = 'h10;
mem['h534] = 'hC0;
mem['h535] = 'hA4;
mem['h536] = 'h24;
mem['h537] = 'h60;
mem['h538] = 'h20;
mem['h539] = 'hD4;
mem['h53A] = 'hFD;
mem['h53B] = 'hC9;
mem['h53C] = 'h88;
mem['h53D] = 'hF0;
mem['h53E] = 'h1D;
mem['h53F] = 'hC9;
mem['h540] = 'h98;
mem['h541] = 'hF0;
mem['h542] = 'h0A;
mem['h543] = 'hE0;
mem['h544] = 'hF8;
mem['h545] = 'h90;
mem['h546] = 'h03;
mem['h547] = 'h20;
mem['h548] = 'h3B;
mem['h549] = 'hFF;
mem['h54A] = 'hE8;
mem['h54B] = 'hD0;
mem['h54C] = 'h13;
mem['h54D] = 'hA9;
mem['h54E] = 'hDC;
mem['h54F] = 'h20;
mem['h550] = 'hD4;
mem['h551] = 'hFD;
mem['h552] = 'h20;
mem['h553] = 'h75;
mem['h554] = 'hFD;
mem['h555] = 'hA5;
mem['h556] = 'h33;
mem['h557] = 'h20;
mem['h558] = 'hD4;
mem['h559] = 'hFD;
mem['h55A] = 'hA2;
mem['h55B] = 'h01;
mem['h55C] = 'h8A;
mem['h55D] = 'hF0;
mem['h55E] = 'hF3;
mem['h55F] = 'hCA;
mem['h560] = 'h20;
mem['h561] = 'h66;
mem['h562] = 'hFB;
mem['h563] = 'hC9;
mem['h564] = 'h95;
mem['h565] = 'hD0;
mem['h566] = 'h02;
mem['h567] = 'hA5;
mem['h568] = 'h35;
mem['h569] = 'h9D;
mem['h56A] = 'h00;
mem['h56B] = 'h02;
mem['h56C] = 'hC9;
mem['h56D] = 'h8D;
mem['h56E] = 'hD0;
mem['h56F] = 'hC8;
mem['h570] = 'hA9;
mem['h571] = 'h9D;
mem['h572] = 'h20;
mem['h573] = 'hD4;
mem['h574] = 'hFD;
mem['h575] = 'hA9;
mem['h576] = 'h8D;
mem['h577] = 'hD0;
mem['h578] = 'h5B;
mem['h579] = 'hA4;
mem['h57A] = 'h3D;
mem['h57B] = 'hA6;
mem['h57C] = 'h3C;
mem['h57D] = 'h20;
mem['h57E] = 'h75;
mem['h57F] = 'hFD;
mem['h580] = 'h20;
mem['h581] = 'h31;
mem['h582] = 'hF9;
mem['h583] = 'hA0;
mem['h584] = 'h00;
mem['h585] = 'hA9;
mem['h586] = 'hAD;
mem['h587] = 'h4C;
mem['h588] = 'hD4;
mem['h589] = 'hFD;
mem['h58A] = 'hA5;
mem['h58B] = 'h3C;
mem['h58C] = 'h09;
mem['h58D] = 'h07;
mem['h58E] = 'h85;
mem['h58F] = 'h3E;
mem['h590] = 'hA5;
mem['h591] = 'h3D;
mem['h592] = 'h85;
mem['h593] = 'h3F;
mem['h594] = 'hA5;
mem['h595] = 'h3C;
mem['h596] = 'h29;
mem['h597] = 'h07;
mem['h598] = 'hD0;
mem['h599] = 'h03;
mem['h59A] = 'h20;
mem['h59B] = 'h79;
mem['h59C] = 'hFD;
mem['h59D] = 'hA9;
mem['h59E] = 'hA0;
mem['h59F] = 'h20;
mem['h5A0] = 'hD4;
mem['h5A1] = 'hFD;
mem['h5A2] = 'hB1;
mem['h5A3] = 'h3C;
mem['h5A4] = 'h20;
mem['h5A5] = 'hC1;
mem['h5A6] = 'hFD;
mem['h5A7] = 'h20;
mem['h5A8] = 'hA6;
mem['h5A9] = 'hFB;
mem['h5AA] = 'h90;
mem['h5AB] = 'hE8;
mem['h5AC] = 'h60;
mem['h5AD] = 'h4A;
mem['h5AE] = 'h90;
mem['h5AF] = 'hEA;
mem['h5B0] = 'h4A;
mem['h5B1] = 'h4A;
mem['h5B2] = 'hA5;
mem['h5B3] = 'h3E;
mem['h5B4] = 'h90;
mem['h5B5] = 'h02;
mem['h5B6] = 'h49;
mem['h5B7] = 'hFF;
mem['h5B8] = 'h65;
mem['h5B9] = 'h3C;
mem['h5BA] = 'h48;
mem['h5BB] = 'hA9;
mem['h5BC] = 'hBD;
mem['h5BD] = 'h20;
mem['h5BE] = 'hD4;
mem['h5BF] = 'hFD;
mem['h5C0] = 'h68;
mem['h5C1] = 'h48;
mem['h5C2] = 'h4A;
mem['h5C3] = 'h4A;
mem['h5C4] = 'h4A;
mem['h5C5] = 'h4A;
mem['h5C6] = 'h20;
mem['h5C7] = 'hCC;
mem['h5C8] = 'hFD;
mem['h5C9] = 'h68;
mem['h5CA] = 'h29;
mem['h5CB] = 'h0F;
mem['h5CC] = 'h09;
mem['h5CD] = 'hB0;
mem['h5CE] = 'hC9;
mem['h5CF] = 'hBA;
mem['h5D0] = 'h90;
mem['h5D1] = 'h02;
mem['h5D2] = 'h69;
mem['h5D3] = 'h06;
mem['h5D4] = 'h6C;
mem['h5D5] = 'h36;
mem['h5D6] = 'h00;
mem['h5D7] = 'h84;
mem['h5D8] = 'h35;
mem['h5D9] = 'h48;
mem['h5DA] = 'hA5;
mem['h5DB] = 'h19;
mem['h5DC] = 'h20;
mem['h5DD] = 'h5E;
mem['h5DE] = 'hF8;
mem['h5DF] = 'h68;
mem['h5E0] = 'h48;
mem['h5E1] = 'hC9;
mem['h5E2] = 'hA0;
mem['h5E3] = 'h90;
mem['h5E4] = 'h06;
mem['h5E5] = 'h24;
mem['h5E6] = 'h32;
mem['h5E7] = 'h30;
mem['h5E8] = 'h02;
mem['h5E9] = 'h29;
mem['h5EA] = 'h7F;
mem['h5EB] = 'h20;
mem['h5EC] = 'hCB;
mem['h5ED] = 'hFB;
mem['h5EE] = 'hA5;
mem['h5EF] = 'h1E;
mem['h5F0] = 'h20;
mem['h5F1] = 'h5E;
mem['h5F2] = 'hF8;
mem['h5F3] = 'h68;
mem['h5F4] = 'hA4;
mem['h5F5] = 'h35;
mem['h5F6] = 'h60;
mem['h5F7] = 'h8A;
mem['h5F8] = 'hF0;
mem['h5F9] = 'h07;
mem['h5FA] = 'hB5;
mem['h5FB] = 'h3C;
mem['h5FC] = 'h95;
mem['h5FD] = 'h3A;
mem['h5FE] = 'hCA;
mem['h5FF] = 'h10;
mem['h600] = 'hF9;
mem['h601] = 'h60;
mem['h602] = 'hC6;
mem['h603] = 'h34;
mem['h604] = 'hF0;
mem['h605] = 'h84;
mem['h606] = 'hCA;
mem['h607] = 'hD0;
mem['h608] = 'h16;
mem['h609] = 'hC9;
mem['h60A] = 'hBA;
mem['h60B] = 'hD0;
mem['h60C] = 'hA0;
mem['h60D] = 'h85;
mem['h60E] = 'h31;
mem['h60F] = 'hA5;
mem['h610] = 'h3E;
mem['h611] = 'h91;
mem['h612] = 'h40;
mem['h613] = 'hE6;
mem['h614] = 'h40;
mem['h615] = 'hD0;
mem['h616] = 'h02;
mem['h617] = 'hE6;
mem['h618] = 'h41;
mem['h619] = 'h60;
mem['h61A] = 'hA4;
mem['h61B] = 'h34;
mem['h61C] = 'hB9;
mem['h61D] = 'hFF;
mem['h61E] = 'h01;
mem['h61F] = 'h85;
mem['h620] = 'h31;
mem['h621] = 'h60;
mem['h622] = 'hA2;
mem['h623] = 'h01;
mem['h624] = 'hB5;
mem['h625] = 'h3E;
mem['h626] = 'h95;
mem['h627] = 'h42;
mem['h628] = 'h95;
mem['h629] = 'h44;
mem['h62A] = 'hCA;
mem['h62B] = 'h10;
mem['h62C] = 'hF7;
mem['h62D] = 'h60;
mem['h62E] = 'hB1;
mem['h62F] = 'h3C;
mem['h630] = 'h91;
mem['h631] = 'h42;
mem['h632] = 'h20;
mem['h633] = 'hA0;
mem['h634] = 'hFB;
mem['h635] = 'h90;
mem['h636] = 'hF7;
mem['h637] = 'h60;
mem['h638] = 'hB1;
mem['h639] = 'h3C;
mem['h63A] = 'hD1;
mem['h63B] = 'h42;
mem['h63C] = 'hF0;
mem['h63D] = 'h1C;
mem['h63E] = 'h20;
mem['h63F] = 'h79;
mem['h640] = 'hFD;
mem['h641] = 'hB1;
mem['h642] = 'h3C;
mem['h643] = 'h20;
mem['h644] = 'hC1;
mem['h645] = 'hFD;
mem['h646] = 'hA9;
mem['h647] = 'hA0;
mem['h648] = 'h20;
mem['h649] = 'hD4;
mem['h64A] = 'hFD;
mem['h64B] = 'hA9;
mem['h64C] = 'hA8;
mem['h64D] = 'h20;
mem['h64E] = 'hD4;
mem['h64F] = 'hFD;
mem['h650] = 'hB1;
mem['h651] = 'h42;
mem['h652] = 'h20;
mem['h653] = 'hC1;
mem['h654] = 'hFD;
mem['h655] = 'hA9;
mem['h656] = 'hA9;
mem['h657] = 'h20;
mem['h658] = 'hD4;
mem['h659] = 'hFD;
mem['h65A] = 'h20;
mem['h65B] = 'hA0;
mem['h65C] = 'hFB;
mem['h65D] = 'h90;
mem['h65E] = 'hD9;
mem['h65F] = 'h60;
mem['h660] = 'h20;
mem['h661] = 'hF7;
mem['h662] = 'hFD;
mem['h663] = 'hA9;
mem['h664] = 'h1C;
mem['h665] = 'h48;
mem['h666] = 'h20;
mem['h667] = 'hC1;
mem['h668] = 'hF8;
mem['h669] = 'h20;
mem['h66A] = 'h39;
mem['h66B] = 'hF9;
mem['h66C] = 'h85;
mem['h66D] = 'h3A;
mem['h66E] = 'h84;
mem['h66F] = 'h3B;
mem['h670] = 'h68;
mem['h671] = 'h38;
mem['h672] = 'hE9;
mem['h673] = 'h01;
mem['h674] = 'hD0;
mem['h675] = 'hEF;
mem['h676] = 'h60;
mem['h677] = 'hA0;
mem['h678] = 'h87;
mem['h679] = 'hD0;
mem['h67A] = 'h02;
mem['h67B] = 'hA0;
mem['h67C] = 'hAF;
mem['h67D] = 'h84;
mem['h67E] = 'h32;
mem['h67F] = 'h60;
mem['h680] = 'hA9;
mem['h681] = 'h00;
mem['h682] = 'h85;
mem['h683] = 'h3E;
mem['h684] = 'hA2;
mem['h685] = 'h38;
mem['h686] = 'hA0;
mem['h687] = 'h07;
mem['h688] = 'hD0;
mem['h689] = 'h08;
mem['h68A] = 'hA9;
mem['h68B] = 'h00;
mem['h68C] = 'h85;
mem['h68D] = 'h3E;
mem['h68E] = 'hA2;
mem['h68F] = 'h36;
mem['h690] = 'hA0;
mem['h691] = 'hD7;
mem['h692] = 'hA5;
mem['h693] = 'h3E;
mem['h694] = 'h29;
mem['h695] = 'h0F;
mem['h696] = 'hF0;
mem['h697] = 'h06;
mem['h698] = 'h09;
mem['h699] = 'hC0;
mem['h69A] = 'hA0;
mem['h69B] = 'h00;
mem['h69C] = 'hF0;
mem['h69D] = 'h02;
mem['h69E] = 'hA9;
mem['h69F] = 'hFD;
mem['h6A0] = 'h94;
mem['h6A1] = 'h00;
mem['h6A2] = 'h95;
mem['h6A3] = 'h01;
mem['h6A4] = 'h60;
mem['h6A5] = 'h4C;
mem['h6A6] = 'h00;
mem['h6A7] = 'hE0;
mem['h6A8] = 'h4C;
mem['h6A9] = 'h03;
mem['h6AA] = 'hE0;
mem['h6AB] = 'h20;
mem['h6AC] = 'hF7;
mem['h6AD] = 'hFD;
mem['h6AE] = 'h20;
mem['h6AF] = 'h40;
mem['h6B0] = 'hFF;
mem['h6B1] = 'h6C;
mem['h6B2] = 'h3A;
mem['h6B3] = 'h00;
mem['h6B4] = 'h4C;
mem['h6B5] = 'hCD;
mem['h6B6] = 'hFA;
mem['h6B7] = 'h4C;
mem['h6B8] = 'hF8;
mem['h6B9] = 'h03;
mem['h6BA] = 'hA5;
mem['h6BB] = 'h3E;
mem['h6BC] = 'h29;
mem['h6BD] = 'h1F;
mem['h6BE] = 'hA2;
mem['h6BF] = 'h02;
mem['h6C0] = 'h4C;
mem['h6C1] = 'h31;
mem['h6C2] = 'hF8;
mem['h6C3] = 'hA5;
mem['h6C4] = 'h3E;
mem['h6C5] = 'h45;
mem['h6C6] = 'h32;
mem['h6C7] = 'h29;
mem['h6C8] = 'h07;
mem['h6C9] = 'h45;
mem['h6CA] = 'h32;
mem['h6CB] = 'h85;
mem['h6CC] = 'h32;
mem['h6CD] = 'h60;
mem['h6CE] = 'hA9;
mem['h6CF] = 'h40;
mem['h6D0] = 'h20;
mem['h6D1] = 'hC1;
mem['h6D2] = 'hFC;
mem['h6D3] = 'hA0;
mem['h6D4] = 'h27;
mem['h6D5] = 'hA2;
mem['h6D6] = 'h00;
mem['h6D7] = 'h41;
mem['h6D8] = 'h3C;
mem['h6D9] = 'h48;
mem['h6DA] = 'hA1;
mem['h6DB] = 'h3C;
mem['h6DC] = 'h20;
mem['h6DD] = 'hEE;
mem['h6DE] = 'hFE;
mem['h6DF] = 'h20;
mem['h6E0] = 'hA6;
mem['h6E1] = 'hFB;
mem['h6E2] = 'hA0;
mem['h6E3] = 'h1D;
mem['h6E4] = 'h68;
mem['h6E5] = 'h90;
mem['h6E6] = 'hEE;
mem['h6E7] = 'hA0;
mem['h6E8] = 'h22;
mem['h6E9] = 'h20;
mem['h6EA] = 'hEE;
mem['h6EB] = 'hFE;
mem['h6EC] = 'hF0;
mem['h6ED] = 'h4D;
mem['h6EE] = 'hA2;
mem['h6EF] = 'h10;
mem['h6F0] = 'h0A;
mem['h6F1] = 'h20;
mem['h6F2] = 'hCE;
mem['h6F3] = 'hFC;
mem['h6F4] = 'hD0;
mem['h6F5] = 'hFA;
mem['h6F6] = 'h60;
mem['h6F7] = 'h20;
mem['h6F8] = 'h02;
mem['h6F9] = 'hFE;
mem['h6FA] = 'h68;
mem['h6FB] = 'h68;
mem['h6FC] = 'hD0;
mem['h6FD] = 'h6B;
mem['h6FE] = 'h20;
mem['h6FF] = 'hF2;
mem['h700] = 'hFC;
mem['h701] = 'hA9;
mem['h702] = 'h16;
mem['h703] = 'h20;
mem['h704] = 'hC1;
mem['h705] = 'hFC;
mem['h706] = 'h85;
mem['h707] = 'h2E;
mem['h708] = 'h20;
mem['h709] = 'hF2;
mem['h70A] = 'hFC;
mem['h70B] = 'hA0;
mem['h70C] = 'h24;
mem['h70D] = 'h20;
mem['h70E] = 'hF5;
mem['h70F] = 'hFC;
mem['h710] = 'hB0;
mem['h711] = 'hF9;
mem['h712] = 'h20;
mem['h713] = 'hF5;
mem['h714] = 'hFC;
mem['h715] = 'hA0;
mem['h716] = 'h3B;
mem['h717] = 'h20;
mem['h718] = 'hE4;
mem['h719] = 'hFC;
mem['h71A] = 'h81;
mem['h71B] = 'h3C;
mem['h71C] = 'h45;
mem['h71D] = 'h2E;
mem['h71E] = 'h85;
mem['h71F] = 'h2E;
mem['h720] = 'h20;
mem['h721] = 'hA6;
mem['h722] = 'hFB;
mem['h723] = 'hA0;
mem['h724] = 'h35;
mem['h725] = 'h90;
mem['h726] = 'hF0;
mem['h727] = 'h20;
mem['h728] = 'hE4;
mem['h729] = 'hFC;
mem['h72A] = 'hC5;
mem['h72B] = 'h2E;
mem['h72C] = 'hF0;
mem['h72D] = 'h0D;
mem['h72E] = 'hA9;
mem['h72F] = 'hC5;
mem['h730] = 'h20;
mem['h731] = 'hD4;
mem['h732] = 'hFD;
mem['h733] = 'hA9;
mem['h734] = 'hD2;
mem['h735] = 'h20;
mem['h736] = 'hD4;
mem['h737] = 'hFD;
mem['h738] = 'h20;
mem['h739] = 'hD4;
mem['h73A] = 'hFD;
mem['h73B] = 'hA9;
mem['h73C] = 'h87;
mem['h73D] = 'h4C;
mem['h73E] = 'hD4;
mem['h73F] = 'hFD;
mem['h740] = 'hA5;
mem['h741] = 'h48;
mem['h742] = 'h48;
mem['h743] = 'hA5;
mem['h744] = 'h45;
mem['h745] = 'hA6;
mem['h746] = 'h46;
mem['h747] = 'hA4;
mem['h748] = 'h47;
mem['h749] = 'h28;
mem['h74A] = 'h60;
mem['h74B] = 'h85;
mem['h74C] = 'h45;
mem['h74D] = 'h86;
mem['h74E] = 'h46;
mem['h74F] = 'h84;
mem['h750] = 'h47;
mem['h751] = 'h08;
mem['h752] = 'h68;
mem['h753] = 'h85;
mem['h754] = 'h48;
mem['h755] = 'hBA;
mem['h756] = 'h86;
mem['h757] = 'h49;
mem['h758] = 'hD8;
mem['h759] = 'h60;
mem['h75A] = 'hA2;
mem['h75B] = 'h02;
mem['h75C] = 'hA9;
mem['h75D] = 'hA0;
mem['h75E] = 'h20;
mem['h75F] = 'hD4;
mem['h760] = 'hFD;
mem['h761] = 'hCA;
mem['h762] = 'hD0;
mem['h763] = 'hFA;
mem['h764] = 'h60;
mem['h765] = 'hD8;
mem['h766] = 'h20;
mem['h767] = 'h3B;
mem['h768] = 'hFF;
mem['h769] = 'hA9;
mem['h76A] = 'hAA;
mem['h76B] = 'h85;
mem['h76C] = 'h33;
mem['h76D] = 'h20;
mem['h76E] = 'h52;
mem['h76F] = 'hFD;
mem['h770] = 'h20;
mem['h771] = 'hC7;
mem['h772] = 'hFF;
mem['h773] = 'h20;
mem['h774] = 'hA7;
mem['h775] = 'hFF;
mem['h776] = 'h84;
mem['h777] = 'h34;
mem['h778] = 'hA0;
mem['h779] = 'h17;
mem['h77A] = 'h88;
mem['h77B] = 'h30;
mem['h77C] = 'hE8;
mem['h77D] = 'hD9;
mem['h77E] = 'hCC;
mem['h77F] = 'hFF;
mem['h780] = 'hD0;
mem['h781] = 'hF8;
mem['h782] = 'h20;
mem['h783] = 'hBE;
mem['h784] = 'hFF;
mem['h785] = 'hA4;
mem['h786] = 'h34;
mem['h787] = 'h4C;
mem['h788] = 'h73;
mem['h789] = 'hFF;
mem['h78A] = 'hA2;
mem['h78B] = 'h03;
mem['h78C] = 'h0A;
mem['h78D] = 'h0A;
mem['h78E] = 'h0A;
mem['h78F] = 'h0A;
mem['h790] = 'h0A;
mem['h791] = 'h26;
mem['h792] = 'h3E;
mem['h793] = 'h26;
mem['h794] = 'h3F;
mem['h795] = 'hCA;
mem['h796] = 'h10;
mem['h797] = 'hF8;
mem['h798] = 'hA5;
mem['h799] = 'h31;
mem['h79A] = 'hD0;
mem['h79B] = 'h06;
mem['h79C] = 'hB5;
mem['h79D] = 'h3F;
mem['h79E] = 'h95;
mem['h79F] = 'h3D;
mem['h7A0] = 'h95;
mem['h7A1] = 'h41;
mem['h7A2] = 'hE8;
mem['h7A3] = 'hF0;
mem['h7A4] = 'hF3;
mem['h7A5] = 'hD0;
mem['h7A6] = 'h06;
mem['h7A7] = 'hA2;
mem['h7A8] = 'h00;
mem['h7A9] = 'h86;
mem['h7AA] = 'h3E;
mem['h7AB] = 'h86;
mem['h7AC] = 'h3F;
mem['h7AD] = 'hB9;
mem['h7AE] = 'h00;
mem['h7AF] = 'h02;
mem['h7B0] = 'hC8;
mem['h7B1] = 'h49;
mem['h7B2] = 'hB0;
mem['h7B3] = 'hC9;
mem['h7B4] = 'h0A;
mem['h7B5] = 'h90;
mem['h7B6] = 'hD3;
mem['h7B7] = 'h69;
mem['h7B8] = 'h88;
mem['h7B9] = 'hC9;
mem['h7BA] = 'hFA;
mem['h7BB] = 'hB0;
mem['h7BC] = 'hCD;
mem['h7BD] = 'h60;
mem['h7BE] = 'hA9;
mem['h7BF] = 'hFE;
mem['h7C0] = 'h48;
mem['h7C1] = 'hB9;
mem['h7C2] = 'hE3;
mem['h7C3] = 'hFF;
mem['h7C4] = 'h48;
mem['h7C5] = 'hA5;
mem['h7C6] = 'h31;
mem['h7C7] = 'hA0;
mem['h7C8] = 'h00;
mem['h7C9] = 'h84;
mem['h7CA] = 'h31;
mem['h7CB] = 'h60;
mem['h7CC] = 'hBC;
mem['h7CD] = 'hB2;
mem['h7CE] = 'hBE;
mem['h7CF] = 'hEF;
mem['h7D0] = 'hE9;
mem['h7D1] = 'h08;
mem['h7D2] = 'hC2;
mem['h7D3] = 'hC8;
mem['h7D4] = 'hBB;
mem['h7D5] = 'hA6;
mem['h7D6] = 'hA4;
mem['h7D7] = 'h06;
mem['h7D8] = 'h95;
mem['h7D9] = 'h07;
mem['h7DA] = 'h02;
mem['h7DB] = 'h05;
mem['h7DC] = 'hF0;
mem['h7DD] = 'h00;
mem['h7DE] = 'hEB;
mem['h7DF] = 'h93;
mem['h7E0] = 'hA7;
mem['h7E1] = 'hC6;
mem['h7E2] = 'h99;
mem['h7E3] = 'hA7;
mem['h7E4] = 'hB6;
mem['h7E5] = 'hB3;
mem['h7E6] = 'h37;
mem['h7E7] = 'hB9;
mem['h7E8] = 'hC2;
mem['h7E9] = 'h83;
mem['h7EA] = 'h8D;
mem['h7EB] = 'hA4;
mem['h7EC] = 'h19;
mem['h7ED] = 'h19;
mem['h7EE] = 'h2D;
mem['h7EF] = 'h21;
mem['h7F0] = 'h7A;
mem['h7F1] = 'h76;
mem['h7F2] = 'h5F;
mem['h7F3] = 'hCD;
mem['h7F4] = 'hAA;
mem['h7F5] = 'hFD;
mem['h7F6] = 'h19;
mem['h7F7] = 'h19;
mem['h7F8] = 'hF6;
mem['h7F9] = 'h05;
mem['h7FA] = 'hFB;
mem['h7FB] = 'h03;
mem['h7FC] = 'h48;
mem['h7FD] = 'hFA;
mem['h7FE] = 'h26;
mem['h7FF] = 'hFA;
/ag_6502/trunk/agat7/agathe7.v
0,0 → 1,2048
mem['h000] = 'h00;
mem['h001] = 'h00;
mem['h002] = 'h00;
mem['h003] = 'h00;
mem['h004] = 'h00;
mem['h005] = 'h00;
mem['h006] = 'h00;
mem['h007] = 'h00;
mem['h008] = 'h00;
mem['h009] = 'h00;
mem['h00A] = 'h00;
mem['h00B] = 'h00;
mem['h00C] = 'h00;
mem['h00D] = 'h00;
mem['h00E] = 'h00;
mem['h00F] = 'h00;
mem['h010] = 'h00;
mem['h011] = 'h00;
mem['h012] = 'h00;
mem['h013] = 'h00;
mem['h014] = 'h00;
mem['h015] = 'h00;
mem['h016] = 'h00;
mem['h017] = 'h00;
mem['h018] = 'h00;
mem['h019] = 'h00;
mem['h01A] = 'h00;
mem['h01B] = 'h00;
mem['h01C] = 'h00;
mem['h01D] = 'h00;
mem['h01E] = 'h00;
mem['h01F] = 'h00;
mem['h020] = 'h00;
mem['h021] = 'h00;
mem['h022] = 'h00;
mem['h023] = 'h00;
mem['h024] = 'h00;
mem['h025] = 'h00;
mem['h026] = 'h00;
mem['h027] = 'h00;
mem['h028] = 'h00;
mem['h029] = 'h00;
mem['h02A] = 'h00;
mem['h02B] = 'h00;
mem['h02C] = 'h00;
mem['h02D] = 'h00;
mem['h02E] = 'h00;
mem['h02F] = 'h00;
mem['h030] = 'h00;
mem['h031] = 'h00;
mem['h032] = 'h00;
mem['h033] = 'h00;
mem['h034] = 'h00;
mem['h035] = 'h00;
mem['h036] = 'h00;
mem['h037] = 'h00;
mem['h038] = 'h00;
mem['h039] = 'h00;
mem['h03A] = 'h00;
mem['h03B] = 'h00;
mem['h03C] = 'h00;
mem['h03D] = 'h00;
mem['h03E] = 'h00;
mem['h03F] = 'h00;
mem['h040] = 'h00;
mem['h041] = 'h00;
mem['h042] = 'h00;
mem['h043] = 'h00;
mem['h044] = 'h00;
mem['h045] = 'h00;
mem['h046] = 'h00;
mem['h047] = 'h00;
mem['h048] = 'h00;
mem['h049] = 'h00;
mem['h04A] = 'h00;
mem['h04B] = 'h00;
mem['h04C] = 'h00;
mem['h04D] = 'h00;
mem['h04E] = 'h00;
mem['h04F] = 'h00;
mem['h050] = 'h00;
mem['h051] = 'h00;
mem['h052] = 'h00;
mem['h053] = 'h00;
mem['h054] = 'h00;
mem['h055] = 'h00;
mem['h056] = 'h00;
mem['h057] = 'h00;
mem['h058] = 'h00;
mem['h059] = 'h00;
mem['h05A] = 'h00;
mem['h05B] = 'h00;
mem['h05C] = 'h00;
mem['h05D] = 'h00;
mem['h05E] = 'h00;
mem['h05F] = 'h00;
mem['h060] = 'h00;
mem['h061] = 'h00;
mem['h062] = 'h00;
mem['h063] = 'h00;
mem['h064] = 'h00;
mem['h065] = 'h00;
mem['h066] = 'h00;
mem['h067] = 'h00;
mem['h068] = 'h00;
mem['h069] = 'h00;
mem['h06A] = 'h00;
mem['h06B] = 'h00;
mem['h06C] = 'h00;
mem['h06D] = 'h00;
mem['h06E] = 'h00;
mem['h06F] = 'h00;
mem['h070] = 'h00;
mem['h071] = 'h00;
mem['h072] = 'h00;
mem['h073] = 'h00;
mem['h074] = 'h00;
mem['h075] = 'h00;
mem['h076] = 'h00;
mem['h077] = 'h00;
mem['h078] = 'h00;
mem['h079] = 'h00;
mem['h07A] = 'h00;
mem['h07B] = 'h00;
mem['h07C] = 'h00;
mem['h07D] = 'h00;
mem['h07E] = 'h00;
mem['h07F] = 'h00;
mem['h080] = 'h00;
mem['h081] = 'h00;
mem['h082] = 'h00;
mem['h083] = 'h7C;
mem['h084] = 'h00;
mem['h085] = 'h00;
mem['h086] = 'h00;
mem['h087] = 'h00;
mem['h088] = 'h00;
mem['h089] = 'h00;
mem['h08A] = 'h00;
mem['h08B] = 'h7C;
mem['h08C] = 'h00;
mem['h08D] = 'h00;
mem['h08E] = 'h00;
mem['h08F] = 'h00;
mem['h090] = 'h00;
mem['h091] = 'h00;
mem['h092] = 'h00;
mem['h093] = 'hF0;
mem['h094] = 'h10;
mem['h095] = 'h10;
mem['h096] = 'h10;
mem['h097] = 'h10;
mem['h098] = 'h10;
mem['h099] = 'h10;
mem['h09A] = 'h10;
mem['h09B] = 'h10;
mem['h09C] = 'h10;
mem['h09D] = 'h10;
mem['h09E] = 'h10;
mem['h09F] = 'h10;
mem['h0A0] = 'h3C;
mem['h0A1] = 'h54;
mem['h0A2] = 'h54;
mem['h0A3] = 'h34;
mem['h0A4] = 'h14;
mem['h0A5] = 'h14;
mem['h0A6] = 'h14;
mem['h0A7] = 'h00;
mem['h0A8] = 'h00;
mem['h0A9] = 'h00;
mem['h0AA] = 'h08;
mem['h0AB] = 'hFC;
mem['h0AC] = 'h08;
mem['h0AD] = 'h00;
mem['h0AE] = 'h00;
mem['h0AF] = 'h00;
mem['h0B0] = 'h00;
mem['h0B1] = 'h00;
mem['h0B2] = 'h00;
mem['h0B3] = 'h00;
mem['h0B4] = 'h7C;
mem['h0B5] = 'h7C;
mem['h0B6] = 'h7C;
mem['h0B7] = 'h00;
mem['h0B8] = 'h10;
mem['h0B9] = 'h38;
mem['h0BA] = 'h10;
mem['h0BB] = 'h10;
mem['h0BC] = 'h38;
mem['h0BD] = 'h10;
mem['h0BE] = 'h7C;
mem['h0BF] = 'h00;
mem['h0C0] = 'h00;
mem['h0C1] = 'h10;
mem['h0C2] = 'h38;
mem['h0C3] = 'h10;
mem['h0C4] = 'h10;
mem['h0C5] = 'h10;
mem['h0C6] = 'h10;
mem['h0C7] = 'h10;
mem['h0C8] = 'h10;
mem['h0C9] = 'h10;
mem['h0CA] = 'h10;
mem['h0CB] = 'h10;
mem['h0CC] = 'h10;
mem['h0CD] = 'h38;
mem['h0CE] = 'h10;
mem['h0CF] = 'h00;
mem['h0D0] = 'h00;
mem['h0D1] = 'h00;
mem['h0D2] = 'h08;
mem['h0D3] = 'hFC;
mem['h0D4] = 'h08;
mem['h0D5] = 'h00;
mem['h0D6] = 'h00;
mem['h0D7] = 'h00;
mem['h0D8] = 'h00;
mem['h0D9] = 'h00;
mem['h0DA] = 'h00;
mem['h0DB] = 'h7C;
mem['h0DC] = 'h00;
mem['h0DD] = 'h00;
mem['h0DE] = 'h00;
mem['h0DF] = 'h00;
mem['h0E0] = 'h10;
mem['h0E1] = 'h10;
mem['h0E2] = 'h10;
mem['h0E3] = 'h10;
mem['h0E4] = 'h10;
mem['h0E5] = 'h10;
mem['h0E6] = 'h10;
mem['h0E7] = 'h10;
mem['h0E8] = 'h40;
mem['h0E9] = 'h40;
mem['h0EA] = 'h40;
mem['h0EB] = 'h40;
mem['h0EC] = 'h40;
mem['h0ED] = 'h40;
mem['h0EE] = 'h7C;
mem['h0EF] = 'h00;
mem['h0F0] = 'h00;
mem['h0F1] = 'h00;
mem['h0F2] = 'h00;
mem['h0F3] = 'h7C;
mem['h0F4] = 'h00;
mem['h0F5] = 'h00;
mem['h0F6] = 'h00;
mem['h0F7] = 'h00;
mem['h0F8] = 'h00;
mem['h0F9] = 'h00;
mem['h0FA] = 'h00;
mem['h0FB] = 'h7C;
mem['h0FC] = 'h00;
mem['h0FD] = 'h00;
mem['h0FE] = 'h00;
mem['h0FF] = 'h00;
mem['h100] = 'h00;
mem['h101] = 'h00;
mem['h102] = 'h00;
mem['h103] = 'h00;
mem['h104] = 'h00;
mem['h105] = 'h00;
mem['h106] = 'h00;
mem['h107] = 'h00;
mem['h108] = 'h10;
mem['h109] = 'h10;
mem['h10A] = 'h10;
mem['h10B] = 'h10;
mem['h10C] = 'h10;
mem['h10D] = 'h00;
mem['h10E] = 'h10;
mem['h10F] = 'h00;
mem['h110] = 'h28;
mem['h111] = 'h28;
mem['h112] = 'h28;
mem['h113] = 'h00;
mem['h114] = 'h00;
mem['h115] = 'h00;
mem['h116] = 'h00;
mem['h117] = 'h00;
mem['h118] = 'h28;
mem['h119] = 'h28;
mem['h11A] = 'h7C;
mem['h11B] = 'h28;
mem['h11C] = 'h7C;
mem['h11D] = 'h28;
mem['h11E] = 'h28;
mem['h11F] = 'h00;
mem['h120] = 'h44;
mem['h121] = 'h38;
mem['h122] = 'h44;
mem['h123] = 'h44;
mem['h124] = 'h44;
mem['h125] = 'h38;
mem['h126] = 'h44;
mem['h127] = 'h00;
mem['h128] = 'h60;
mem['h129] = 'h64;
mem['h12A] = 'h08;
mem['h12B] = 'h10;
mem['h12C] = 'h20;
mem['h12D] = 'h4C;
mem['h12E] = 'h0C;
mem['h12F] = 'h00;
mem['h130] = 'h20;
mem['h131] = 'h50;
mem['h132] = 'h50;
mem['h133] = 'h20;
mem['h134] = 'h54;
mem['h135] = 'h48;
mem['h136] = 'h34;
mem['h137] = 'h00;
mem['h138] = 'h10;
mem['h139] = 'h10;
mem['h13A] = 'h10;
mem['h13B] = 'h00;
mem['h13C] = 'h00;
mem['h13D] = 'h00;
mem['h13E] = 'h00;
mem['h13F] = 'h00;
mem['h140] = 'h08;
mem['h141] = 'h10;
mem['h142] = 'h20;
mem['h143] = 'h20;
mem['h144] = 'h20;
mem['h145] = 'h10;
mem['h146] = 'h08;
mem['h147] = 'h00;
mem['h148] = 'h20;
mem['h149] = 'h10;
mem['h14A] = 'h08;
mem['h14B] = 'h08;
mem['h14C] = 'h08;
mem['h14D] = 'h10;
mem['h14E] = 'h20;
mem['h14F] = 'h00;
mem['h150] = 'h10;
mem['h151] = 'h54;
mem['h152] = 'h38;
mem['h153] = 'h10;
mem['h154] = 'h38;
mem['h155] = 'h54;
mem['h156] = 'h10;
mem['h157] = 'h00;
mem['h158] = 'h00;
mem['h159] = 'h10;
mem['h15A] = 'h10;
mem['h15B] = 'h7C;
mem['h15C] = 'h10;
mem['h15D] = 'h10;
mem['h15E] = 'h00;
mem['h15F] = 'h00;
mem['h160] = 'h00;
mem['h161] = 'h00;
mem['h162] = 'h00;
mem['h163] = 'h30;
mem['h164] = 'h30;
mem['h165] = 'h10;
mem['h166] = 'h20;
mem['h167] = 'h00;
mem['h168] = 'h00;
mem['h169] = 'h00;
mem['h16A] = 'h00;
mem['h16B] = 'h7C;
mem['h16C] = 'h00;
mem['h16D] = 'h00;
mem['h16E] = 'h00;
mem['h16F] = 'h00;
mem['h170] = 'h00;
mem['h171] = 'h00;
mem['h172] = 'h00;
mem['h173] = 'h00;
mem['h174] = 'h00;
mem['h175] = 'h30;
mem['h176] = 'h30;
mem['h177] = 'h00;
mem['h178] = 'h00;
mem['h179] = 'h04;
mem['h17A] = 'h08;
mem['h17B] = 'h10;
mem['h17C] = 'h20;
mem['h17D] = 'h40;
mem['h17E] = 'h00;
mem['h17F] = 'h00;
mem['h180] = 'h38;
mem['h181] = 'h44;
mem['h182] = 'h4C;
mem['h183] = 'h54;
mem['h184] = 'h64;
mem['h185] = 'h44;
mem['h186] = 'h38;
mem['h187] = 'h00;
mem['h188] = 'h10;
mem['h189] = 'h30;
mem['h18A] = 'h10;
mem['h18B] = 'h10;
mem['h18C] = 'h10;
mem['h18D] = 'h10;
mem['h18E] = 'h38;
mem['h18F] = 'h00;
mem['h190] = 'h38;
mem['h191] = 'h44;
mem['h192] = 'h04;
mem['h193] = 'h08;
mem['h194] = 'h10;
mem['h195] = 'h20;
mem['h196] = 'h7C;
mem['h197] = 'h00;
mem['h198] = 'h7C;
mem['h199] = 'h04;
mem['h19A] = 'h08;
mem['h19B] = 'h18;
mem['h19C] = 'h04;
mem['h19D] = 'h44;
mem['h19E] = 'h38;
mem['h19F] = 'h00;
mem['h1A0] = 'h08;
mem['h1A1] = 'h18;
mem['h1A2] = 'h28;
mem['h1A3] = 'h48;
mem['h1A4] = 'h7C;
mem['h1A5] = 'h08;
mem['h1A6] = 'h08;
mem['h1A7] = 'h00;
mem['h1A8] = 'h7C;
mem['h1A9] = 'h40;
mem['h1AA] = 'h78;
mem['h1AB] = 'h04;
mem['h1AC] = 'h04;
mem['h1AD] = 'h44;
mem['h1AE] = 'h38;
mem['h1AF] = 'h00;
mem['h1B0] = 'h1C;
mem['h1B1] = 'h20;
mem['h1B2] = 'h40;
mem['h1B3] = 'h78;
mem['h1B4] = 'h44;
mem['h1B5] = 'h44;
mem['h1B6] = 'h38;
mem['h1B7] = 'h00;
mem['h1B8] = 'h7C;
mem['h1B9] = 'h04;
mem['h1BA] = 'h08;
mem['h1BB] = 'h10;
mem['h1BC] = 'h20;
mem['h1BD] = 'h20;
mem['h1BE] = 'h20;
mem['h1BF] = 'h00;
mem['h1C0] = 'h38;
mem['h1C1] = 'h44;
mem['h1C2] = 'h44;
mem['h1C3] = 'h38;
mem['h1C4] = 'h44;
mem['h1C5] = 'h44;
mem['h1C6] = 'h38;
mem['h1C7] = 'h00;
mem['h1C8] = 'h38;
mem['h1C9] = 'h44;
mem['h1CA] = 'h44;
mem['h1CB] = 'h3C;
mem['h1CC] = 'h04;
mem['h1CD] = 'h08;
mem['h1CE] = 'h70;
mem['h1CF] = 'h00;
mem['h1D0] = 'h00;
mem['h1D1] = 'h00;
mem['h1D2] = 'h18;
mem['h1D3] = 'h18;
mem['h1D4] = 'h00;
mem['h1D5] = 'h18;
mem['h1D6] = 'h18;
mem['h1D7] = 'h00;
mem['h1D8] = 'h18;
mem['h1D9] = 'h18;
mem['h1DA] = 'h00;
mem['h1DB] = 'h18;
mem['h1DC] = 'h18;
mem['h1DD] = 'h08;
mem['h1DE] = 'h10;
mem['h1DF] = 'h00;
mem['h1E0] = 'h04;
mem['h1E1] = 'h08;
mem['h1E2] = 'h10;
mem['h1E3] = 'h20;
mem['h1E4] = 'h10;
mem['h1E5] = 'h08;
mem['h1E6] = 'h04;
mem['h1E7] = 'h00;
mem['h1E8] = 'h00;
mem['h1E9] = 'h00;
mem['h1EA] = 'h7C;
mem['h1EB] = 'h00;
mem['h1EC] = 'h7C;
mem['h1ED] = 'h00;
mem['h1EE] = 'h00;
mem['h1EF] = 'h00;
mem['h1F0] = 'h20;
mem['h1F1] = 'h10;
mem['h1F2] = 'h08;
mem['h1F3] = 'h04;
mem['h1F4] = 'h08;
mem['h1F5] = 'h10;
mem['h1F6] = 'h20;
mem['h1F7] = 'h00;
mem['h1F8] = 'h38;
mem['h1F9] = 'h44;
mem['h1FA] = 'h08;
mem['h1FB] = 'h10;
mem['h1FC] = 'h10;
mem['h1FD] = 'h00;
mem['h1FE] = 'h10;
mem['h1FF] = 'h00;
mem['h200] = 'h38;
mem['h201] = 'h44;
mem['h202] = 'h5C;
mem['h203] = 'h54;
mem['h204] = 'h5C;
mem['h205] = 'h40;
mem['h206] = 'h3C;
mem['h207] = 'h00;
mem['h208] = 'h10;
mem['h209] = 'h28;
mem['h20A] = 'h44;
mem['h20B] = 'h44;
mem['h20C] = 'h7C;
mem['h20D] = 'h44;
mem['h20E] = 'h44;
mem['h20F] = 'h00;
mem['h210] = 'h78;
mem['h211] = 'h44;
mem['h212] = 'h44;
mem['h213] = 'h78;
mem['h214] = 'h44;
mem['h215] = 'h44;
mem['h216] = 'h78;
mem['h217] = 'h00;
mem['h218] = 'h38;
mem['h219] = 'h44;
mem['h21A] = 'h40;
mem['h21B] = 'h40;
mem['h21C] = 'h40;
mem['h21D] = 'h44;
mem['h21E] = 'h38;
mem['h21F] = 'h00;
mem['h220] = 'h78;
mem['h221] = 'h44;
mem['h222] = 'h44;
mem['h223] = 'h44;
mem['h224] = 'h44;
mem['h225] = 'h44;
mem['h226] = 'h78;
mem['h227] = 'h00;
mem['h228] = 'h7C;
mem['h229] = 'h40;
mem['h22A] = 'h40;
mem['h22B] = 'h78;
mem['h22C] = 'h40;
mem['h22D] = 'h40;
mem['h22E] = 'h7C;
mem['h22F] = 'h00;
mem['h230] = 'h7C;
mem['h231] = 'h40;
mem['h232] = 'h40;
mem['h233] = 'h78;
mem['h234] = 'h40;
mem['h235] = 'h40;
mem['h236] = 'h40;
mem['h237] = 'h00;
mem['h238] = 'h3C;
mem['h239] = 'h40;
mem['h23A] = 'h40;
mem['h23B] = 'h40;
mem['h23C] = 'h4C;
mem['h23D] = 'h44;
mem['h23E] = 'h3C;
mem['h23F] = 'h00;
mem['h240] = 'h44;
mem['h241] = 'h44;
mem['h242] = 'h44;
mem['h243] = 'h7C;
mem['h244] = 'h44;
mem['h245] = 'h44;
mem['h246] = 'h44;
mem['h247] = 'h00;
mem['h248] = 'h38;
mem['h249] = 'h10;
mem['h24A] = 'h10;
mem['h24B] = 'h10;
mem['h24C] = 'h10;
mem['h24D] = 'h10;
mem['h24E] = 'h38;
mem['h24F] = 'h00;
mem['h250] = 'h04;
mem['h251] = 'h04;
mem['h252] = 'h04;
mem['h253] = 'h04;
mem['h254] = 'h04;
mem['h255] = 'h44;
mem['h256] = 'h38;
mem['h257] = 'h00;
mem['h258] = 'h44;
mem['h259] = 'h48;
mem['h25A] = 'h50;
mem['h25B] = 'h60;
mem['h25C] = 'h50;
mem['h25D] = 'h48;
mem['h25E] = 'h44;
mem['h25F] = 'h00;
mem['h260] = 'h40;
mem['h261] = 'h40;
mem['h262] = 'h40;
mem['h263] = 'h40;
mem['h264] = 'h40;
mem['h265] = 'h40;
mem['h266] = 'h7C;
mem['h267] = 'h00;
mem['h268] = 'h44;
mem['h269] = 'h6C;
mem['h26A] = 'h54;
mem['h26B] = 'h54;
mem['h26C] = 'h44;
mem['h26D] = 'h44;
mem['h26E] = 'h44;
mem['h26F] = 'h00;
mem['h270] = 'h44;
mem['h271] = 'h44;
mem['h272] = 'h64;
mem['h273] = 'h54;
mem['h274] = 'h4C;
mem['h275] = 'h44;
mem['h276] = 'h44;
mem['h277] = 'h00;
mem['h278] = 'h38;
mem['h279] = 'h44;
mem['h27A] = 'h44;
mem['h27B] = 'h44;
mem['h27C] = 'h44;
mem['h27D] = 'h44;
mem['h27E] = 'h38;
mem['h27F] = 'h00;
mem['h280] = 'h78;
mem['h281] = 'h44;
mem['h282] = 'h44;
mem['h283] = 'h78;
mem['h284] = 'h40;
mem['h285] = 'h40;
mem['h286] = 'h40;
mem['h287] = 'h00;
mem['h288] = 'h38;
mem['h289] = 'h44;
mem['h28A] = 'h44;
mem['h28B] = 'h44;
mem['h28C] = 'h54;
mem['h28D] = 'h48;
mem['h28E] = 'h34;
mem['h28F] = 'h00;
mem['h290] = 'h78;
mem['h291] = 'h44;
mem['h292] = 'h44;
mem['h293] = 'h78;
mem['h294] = 'h50;
mem['h295] = 'h48;
mem['h296] = 'h44;
mem['h297] = 'h00;
mem['h298] = 'h38;
mem['h299] = 'h44;
mem['h29A] = 'h40;
mem['h29B] = 'h38;
mem['h29C] = 'h04;
mem['h29D] = 'h44;
mem['h29E] = 'h38;
mem['h29F] = 'h00;
mem['h2A0] = 'h7C;
mem['h2A1] = 'h10;
mem['h2A2] = 'h10;
mem['h2A3] = 'h10;
mem['h2A4] = 'h10;
mem['h2A5] = 'h10;
mem['h2A6] = 'h10;
mem['h2A7] = 'h00;
mem['h2A8] = 'h44;
mem['h2A9] = 'h44;
mem['h2AA] = 'h44;
mem['h2AB] = 'h44;
mem['h2AC] = 'h44;
mem['h2AD] = 'h44;
mem['h2AE] = 'h38;
mem['h2AF] = 'h00;
mem['h2B0] = 'h44;
mem['h2B1] = 'h44;
mem['h2B2] = 'h44;
mem['h2B3] = 'h44;
mem['h2B4] = 'h44;
mem['h2B5] = 'h28;
mem['h2B6] = 'h10;
mem['h2B7] = 'h00;
mem['h2B8] = 'h44;
mem['h2B9] = 'h44;
mem['h2BA] = 'h44;
mem['h2BB] = 'h54;
mem['h2BC] = 'h54;
mem['h2BD] = 'h6C;
mem['h2BE] = 'h44;
mem['h2BF] = 'h00;
mem['h2C0] = 'h44;
mem['h2C1] = 'h44;
mem['h2C2] = 'h28;
mem['h2C3] = 'h10;
mem['h2C4] = 'h28;
mem['h2C5] = 'h44;
mem['h2C6] = 'h44;
mem['h2C7] = 'h00;
mem['h2C8] = 'h44;
mem['h2C9] = 'h44;
mem['h2CA] = 'h28;
mem['h2CB] = 'h10;
mem['h2CC] = 'h10;
mem['h2CD] = 'h10;
mem['h2CE] = 'h10;
mem['h2CF] = 'h00;
mem['h2D0] = 'h7C;
mem['h2D1] = 'h04;
mem['h2D2] = 'h08;
mem['h2D3] = 'h10;
mem['h2D4] = 'h20;
mem['h2D5] = 'h40;
mem['h2D6] = 'h7C;
mem['h2D7] = 'h00;
mem['h2D8] = 'h7C;
mem['h2D9] = 'h60;
mem['h2DA] = 'h60;
mem['h2DB] = 'h60;
mem['h2DC] = 'h60;
mem['h2DD] = 'h60;
mem['h2DE] = 'h7C;
mem['h2DF] = 'h00;
mem['h2E0] = 'h00;
mem['h2E1] = 'h40;
mem['h2E2] = 'h20;
mem['h2E3] = 'h10;
mem['h2E4] = 'h08;
mem['h2E5] = 'h04;
mem['h2E6] = 'h00;
mem['h2E7] = 'h00;
mem['h2E8] = 'h7C;
mem['h2E9] = 'h0C;
mem['h2EA] = 'h0C;
mem['h2EB] = 'h0C;
mem['h2EC] = 'h0C;
mem['h2ED] = 'h0C;
mem['h2EE] = 'h7C;
mem['h2EF] = 'h00;
mem['h2F0] = 'h00;
mem['h2F1] = 'h10;
mem['h2F2] = 'h28;
mem['h2F3] = 'h44;
mem['h2F4] = 'h00;
mem['h2F5] = 'h00;
mem['h2F6] = 'h00;
mem['h2F7] = 'h00;
mem['h2F8] = 'h00;
mem['h2F9] = 'h00;
mem['h2FA] = 'h00;
mem['h2FB] = 'h00;
mem['h2FC] = 'h00;
mem['h2FD] = 'h00;
mem['h2FE] = 'h00;
mem['h2FF] = 'hFF;
mem['h300] = 'h5C;
mem['h301] = 'h54;
mem['h302] = 'h54;
mem['h303] = 'h74;
mem['h304] = 'h54;
mem['h305] = 'h54;
mem['h306] = 'h5C;
mem['h307] = 'h00;
mem['h308] = 'h38;
mem['h309] = 'h44;
mem['h30A] = 'h44;
mem['h30B] = 'h44;
mem['h30C] = 'h7C;
mem['h30D] = 'h44;
mem['h30E] = 'h44;
mem['h30F] = 'h00;
mem['h310] = 'h7C;
mem['h311] = 'h40;
mem['h312] = 'h40;
mem['h313] = 'h78;
mem['h314] = 'h44;
mem['h315] = 'h44;
mem['h316] = 'h78;
mem['h317] = 'h00;
mem['h318] = 'h48;
mem['h319] = 'h48;
mem['h31A] = 'h48;
mem['h31B] = 'h48;
mem['h31C] = 'h48;
mem['h31D] = 'h48;
mem['h31E] = 'h7C;
mem['h31F] = 'h04;
mem['h320] = 'h1C;
mem['h321] = 'h24;
mem['h322] = 'h24;
mem['h323] = 'h24;
mem['h324] = 'h24;
mem['h325] = 'h24;
mem['h326] = 'h7E;
mem['h327] = 'h42;
mem['h328] = 'h7C;
mem['h329] = 'h40;
mem['h32A] = 'h40;
mem['h32B] = 'h78;
mem['h32C] = 'h40;
mem['h32D] = 'h40;
mem['h32E] = 'h7C;
mem['h32F] = 'h00;
mem['h330] = 'h38;
mem['h331] = 'h54;
mem['h332] = 'h54;
mem['h333] = 'h54;
mem['h334] = 'h38;
mem['h335] = 'h10;
mem['h336] = 'h10;
mem['h337] = 'h00;
mem['h338] = 'h7C;
mem['h339] = 'h40;
mem['h33A] = 'h40;
mem['h33B] = 'h40;
mem['h33C] = 'h40;
mem['h33D] = 'h40;
mem['h33E] = 'h40;
mem['h33F] = 'h00;
mem['h340] = 'h44;
mem['h341] = 'h44;
mem['h342] = 'h28;
mem['h343] = 'h10;
mem['h344] = 'h28;
mem['h345] = 'h44;
mem['h346] = 'h44;
mem['h347] = 'h00;
mem['h348] = 'h44;
mem['h349] = 'h44;
mem['h34A] = 'h44;
mem['h34B] = 'h4C;
mem['h34C] = 'h54;
mem['h34D] = 'h64;
mem['h34E] = 'h44;
mem['h34F] = 'h00;
mem['h350] = 'h54;
mem['h351] = 'h54;
mem['h352] = 'h44;
mem['h353] = 'h4C;
mem['h354] = 'h54;
mem['h355] = 'h64;
mem['h356] = 'h44;
mem['h357] = 'h00;
mem['h358] = 'h44;
mem['h359] = 'h48;
mem['h35A] = 'h50;
mem['h35B] = 'h60;
mem['h35C] = 'h50;
mem['h35D] = 'h48;
mem['h35E] = 'h44;
mem['h35F] = 'h00;
mem['h360] = 'h0C;
mem['h361] = 'h14;
mem['h362] = 'h24;
mem['h363] = 'h24;
mem['h364] = 'h24;
mem['h365] = 'h24;
mem['h366] = 'h44;
mem['h367] = 'h00;
mem['h368] = 'h44;
mem['h369] = 'h6C;
mem['h36A] = 'h54;
mem['h36B] = 'h54;
mem['h36C] = 'h44;
mem['h36D] = 'h44;
mem['h36E] = 'h44;
mem['h36F] = 'h00;
mem['h370] = 'h44;
mem['h371] = 'h44;
mem['h372] = 'h44;
mem['h373] = 'h7C;
mem['h374] = 'h44;
mem['h375] = 'h44;
mem['h376] = 'h44;
mem['h377] = 'h00;
mem['h378] = 'h38;
mem['h379] = 'h44;
mem['h37A] = 'h44;
mem['h37B] = 'h44;
mem['h37C] = 'h44;
mem['h37D] = 'h44;
mem['h37E] = 'h38;
mem['h37F] = 'h00;
mem['h380] = 'h7C;
mem['h381] = 'h44;
mem['h382] = 'h44;
mem['h383] = 'h44;
mem['h384] = 'h44;
mem['h385] = 'h44;
mem['h386] = 'h44;
mem['h387] = 'h00;
mem['h388] = 'h3C;
mem['h389] = 'h44;
mem['h38A] = 'h44;
mem['h38B] = 'h3C;
mem['h38C] = 'h14;
mem['h38D] = 'h24;
mem['h38E] = 'h44;
mem['h38F] = 'h00;
mem['h390] = 'h78;
mem['h391] = 'h44;
mem['h392] = 'h44;
mem['h393] = 'h78;
mem['h394] = 'h40;
mem['h395] = 'h40;
mem['h396] = 'h40;
mem['h397] = 'h00;
mem['h398] = 'h38;
mem['h399] = 'h44;
mem['h39A] = 'h40;
mem['h39B] = 'h40;
mem['h39C] = 'h40;
mem['h39D] = 'h44;
mem['h39E] = 'h38;
mem['h39F] = 'h00;
mem['h3A0] = 'h7C;
mem['h3A1] = 'h10;
mem['h3A2] = 'h10;
mem['h3A3] = 'h10;
mem['h3A4] = 'h10;
mem['h3A5] = 'h10;
mem['h3A6] = 'h10;
mem['h3A7] = 'h00;
mem['h3A8] = 'h44;
mem['h3A9] = 'h44;
mem['h3AA] = 'h44;
mem['h3AB] = 'h3C;
mem['h3AC] = 'h04;
mem['h3AD] = 'h44;
mem['h3AE] = 'h38;
mem['h3AF] = 'h00;
mem['h3B0] = 'h54;
mem['h3B1] = 'h54;
mem['h3B2] = 'h54;
mem['h3B3] = 'h38;
mem['h3B4] = 'h54;
mem['h3B5] = 'h54;
mem['h3B6] = 'h54;
mem['h3B7] = 'h00;
mem['h3B8] = 'h78;
mem['h3B9] = 'h44;
mem['h3BA] = 'h44;
mem['h3BB] = 'h78;
mem['h3BC] = 'h44;
mem['h3BD] = 'h44;
mem['h3BE] = 'h78;
mem['h3BF] = 'h00;
mem['h3C0] = 'h40;
mem['h3C1] = 'h40;
mem['h3C2] = 'h40;
mem['h3C3] = 'h78;
mem['h3C4] = 'h44;
mem['h3C5] = 'h44;
mem['h3C6] = 'h78;
mem['h3C7] = 'h00;
mem['h3C8] = 'h44;
mem['h3C9] = 'h44;
mem['h3CA] = 'h44;
mem['h3CB] = 'h74;
mem['h3CC] = 'h54;
mem['h3CD] = 'h54;
mem['h3CE] = 'h74;
mem['h3CF] = 'h00;
mem['h3D0] = 'h38;
mem['h3D1] = 'h44;
mem['h3D2] = 'h04;
mem['h3D3] = 'h18;
mem['h3D4] = 'h04;
mem['h3D5] = 'h44;
mem['h3D6] = 'h38;
mem['h3D7] = 'h00;
mem['h3D8] = 'h54;
mem['h3D9] = 'h54;
mem['h3DA] = 'h54;
mem['h3DB] = 'h54;
mem['h3DC] = 'h54;
mem['h3DD] = 'h54;
mem['h3DE] = 'h7C;
mem['h3DF] = 'h00;
mem['h3E0] = 'h78;
mem['h3E1] = 'h04;
mem['h3E2] = 'h04;
mem['h3E3] = 'h3C;
mem['h3E4] = 'h04;
mem['h3E5] = 'h04;
mem['h3E6] = 'h78;
mem['h3E7] = 'h00;
mem['h3E8] = 'h54;
mem['h3E9] = 'h54;
mem['h3EA] = 'h54;
mem['h3EB] = 'h54;
mem['h3EC] = 'h54;
mem['h3ED] = 'h54;
mem['h3EE] = 'h7C;
mem['h3EF] = 'h04;
mem['h3F0] = 'h44;
mem['h3F1] = 'h44;
mem['h3F2] = 'h44;
mem['h3F3] = 'h3C;
mem['h3F4] = 'h04;
mem['h3F5] = 'h04;
mem['h3F6] = 'h04;
mem['h3F7] = 'h00;
mem['h3F8] = 'h60;
mem['h3F9] = 'h20;
mem['h3FA] = 'h20;
mem['h3FB] = 'h38;
mem['h3FC] = 'h24;
mem['h3FD] = 'h24;
mem['h3FE] = 'h38;
mem['h3FF] = 'h00;
mem['h400] = 'h00;
mem['h401] = 'h00;
mem['h402] = 'h00;
mem['h403] = 'h00;
mem['h404] = 'h00;
mem['h405] = 'h00;
mem['h406] = 'h00;
mem['h407] = 'h00;
mem['h408] = 'h00;
mem['h409] = 'h00;
mem['h40A] = 'h00;
mem['h40B] = 'h00;
mem['h40C] = 'h00;
mem['h40D] = 'h00;
mem['h40E] = 'h00;
mem['h40F] = 'h00;
mem['h410] = 'h00;
mem['h411] = 'h00;
mem['h412] = 'h00;
mem['h413] = 'h00;
mem['h414] = 'h00;
mem['h415] = 'h00;
mem['h416] = 'h00;
mem['h417] = 'h00;
mem['h418] = 'h00;
mem['h419] = 'h00;
mem['h41A] = 'h00;
mem['h41B] = 'h00;
mem['h41C] = 'h00;
mem['h41D] = 'h00;
mem['h41E] = 'h00;
mem['h41F] = 'h00;
mem['h420] = 'h00;
mem['h421] = 'h00;
mem['h422] = 'h00;
mem['h423] = 'h00;
mem['h424] = 'h00;
mem['h425] = 'h00;
mem['h426] = 'h00;
mem['h427] = 'h00;
mem['h428] = 'h00;
mem['h429] = 'h00;
mem['h42A] = 'h00;
mem['h42B] = 'h00;
mem['h42C] = 'h00;
mem['h42D] = 'h00;
mem['h42E] = 'h00;
mem['h42F] = 'h00;
mem['h430] = 'h00;
mem['h431] = 'h00;
mem['h432] = 'h00;
mem['h433] = 'h00;
mem['h434] = 'h00;
mem['h435] = 'h00;
mem['h436] = 'h00;
mem['h437] = 'h00;
mem['h438] = 'h00;
mem['h439] = 'h00;
mem['h43A] = 'h00;
mem['h43B] = 'h00;
mem['h43C] = 'h00;
mem['h43D] = 'h00;
mem['h43E] = 'h00;
mem['h43F] = 'h00;
mem['h440] = 'h00;
mem['h441] = 'h00;
mem['h442] = 'h00;
mem['h443] = 'h00;
mem['h444] = 'h00;
mem['h445] = 'h00;
mem['h446] = 'h00;
mem['h447] = 'h00;
mem['h448] = 'h00;
mem['h449] = 'h00;
mem['h44A] = 'h00;
mem['h44B] = 'h00;
mem['h44C] = 'h00;
mem['h44D] = 'h00;
mem['h44E] = 'h00;
mem['h44F] = 'h00;
mem['h450] = 'h00;
mem['h451] = 'h00;
mem['h452] = 'h00;
mem['h453] = 'h00;
mem['h454] = 'h00;
mem['h455] = 'h00;
mem['h456] = 'h00;
mem['h457] = 'h00;
mem['h458] = 'h00;
mem['h459] = 'h00;
mem['h45A] = 'h00;
mem['h45B] = 'h00;
mem['h45C] = 'h00;
mem['h45D] = 'h00;
mem['h45E] = 'h00;
mem['h45F] = 'h00;
mem['h460] = 'h00;
mem['h461] = 'h00;
mem['h462] = 'h00;
mem['h463] = 'h00;
mem['h464] = 'h00;
mem['h465] = 'h00;
mem['h466] = 'h00;
mem['h467] = 'h00;
mem['h468] = 'h00;
mem['h469] = 'h00;
mem['h46A] = 'h00;
mem['h46B] = 'h00;
mem['h46C] = 'h00;
mem['h46D] = 'h00;
mem['h46E] = 'h00;
mem['h46F] = 'h00;
mem['h470] = 'h00;
mem['h471] = 'h00;
mem['h472] = 'h00;
mem['h473] = 'h00;
mem['h474] = 'h00;
mem['h475] = 'h00;
mem['h476] = 'h00;
mem['h477] = 'h00;
mem['h478] = 'h00;
mem['h479] = 'h00;
mem['h47A] = 'h00;
mem['h47B] = 'h00;
mem['h47C] = 'h00;
mem['h47D] = 'h00;
mem['h47E] = 'h00;
mem['h47F] = 'h00;
mem['h480] = 'h00;
mem['h481] = 'h00;
mem['h482] = 'h00;
mem['h483] = 'h7C;
mem['h484] = 'h00;
mem['h485] = 'h00;
mem['h486] = 'h00;
mem['h487] = 'h00;
mem['h488] = 'h00;
mem['h489] = 'h00;
mem['h48A] = 'h00;
mem['h48B] = 'h7C;
mem['h48C] = 'h00;
mem['h48D] = 'h00;
mem['h48E] = 'h00;
mem['h48F] = 'h00;
mem['h490] = 'h00;
mem['h491] = 'h00;
mem['h492] = 'h00;
mem['h493] = 'hF0;
mem['h494] = 'h10;
mem['h495] = 'h10;
mem['h496] = 'h10;
mem['h497] = 'h10;
mem['h498] = 'h10;
mem['h499] = 'h10;
mem['h49A] = 'h10;
mem['h49B] = 'h10;
mem['h49C] = 'h10;
mem['h49D] = 'h10;
mem['h49E] = 'h10;
mem['h49F] = 'h10;
mem['h4A0] = 'h3C;
mem['h4A1] = 'h54;
mem['h4A2] = 'h54;
mem['h4A3] = 'h34;
mem['h4A4] = 'h14;
mem['h4A5] = 'h14;
mem['h4A6] = 'h14;
mem['h4A7] = 'h00;
mem['h4A8] = 'h00;
mem['h4A9] = 'h00;
mem['h4AA] = 'h08;
mem['h4AB] = 'hFC;
mem['h4AC] = 'h08;
mem['h4AD] = 'h00;
mem['h4AE] = 'h00;
mem['h4AF] = 'h00;
mem['h4B0] = 'h00;
mem['h4B1] = 'h00;
mem['h4B2] = 'h00;
mem['h4B3] = 'h00;
mem['h4B4] = 'h7C;
mem['h4B5] = 'h7C;
mem['h4B6] = 'h7C;
mem['h4B7] = 'h00;
mem['h4B8] = 'h10;
mem['h4B9] = 'h38;
mem['h4BA] = 'h10;
mem['h4BB] = 'h10;
mem['h4BC] = 'h38;
mem['h4BD] = 'h10;
mem['h4BE] = 'h7C;
mem['h4BF] = 'h00;
mem['h4C0] = 'h00;
mem['h4C1] = 'h10;
mem['h4C2] = 'h38;
mem['h4C3] = 'h10;
mem['h4C4] = 'h10;
mem['h4C5] = 'h10;
mem['h4C6] = 'h10;
mem['h4C7] = 'h10;
mem['h4C8] = 'h10;
mem['h4C9] = 'h10;
mem['h4CA] = 'h10;
mem['h4CB] = 'h10;
mem['h4CC] = 'h10;
mem['h4CD] = 'h38;
mem['h4CE] = 'h10;
mem['h4CF] = 'h00;
mem['h4D0] = 'h00;
mem['h4D1] = 'h00;
mem['h4D2] = 'h08;
mem['h4D3] = 'hFC;
mem['h4D4] = 'h08;
mem['h4D5] = 'h00;
mem['h4D6] = 'h00;
mem['h4D7] = 'h00;
mem['h4D8] = 'h00;
mem['h4D9] = 'h00;
mem['h4DA] = 'h00;
mem['h4DB] = 'h7C;
mem['h4DC] = 'h00;
mem['h4DD] = 'h00;
mem['h4DE] = 'h00;
mem['h4DF] = 'h00;
mem['h4E0] = 'h10;
mem['h4E1] = 'h10;
mem['h4E2] = 'h10;
mem['h4E3] = 'h10;
mem['h4E4] = 'h10;
mem['h4E5] = 'h10;
mem['h4E6] = 'h10;
mem['h4E7] = 'h10;
mem['h4E8] = 'h40;
mem['h4E9] = 'h40;
mem['h4EA] = 'h40;
mem['h4EB] = 'h40;
mem['h4EC] = 'h40;
mem['h4ED] = 'h40;
mem['h4EE] = 'h7C;
mem['h4EF] = 'h00;
mem['h4F0] = 'h00;
mem['h4F1] = 'h00;
mem['h4F2] = 'h00;
mem['h4F3] = 'h7C;
mem['h4F4] = 'h00;
mem['h4F5] = 'h00;
mem['h4F6] = 'h00;
mem['h4F7] = 'h00;
mem['h4F8] = 'h00;
mem['h4F9] = 'h00;
mem['h4FA] = 'h00;
mem['h4FB] = 'h7C;
mem['h4FC] = 'h00;
mem['h4FD] = 'h00;
mem['h4FE] = 'h00;
mem['h4FF] = 'h00;
mem['h500] = 'h00;
mem['h501] = 'h00;
mem['h502] = 'h00;
mem['h503] = 'h00;
mem['h504] = 'h00;
mem['h505] = 'h00;
mem['h506] = 'h00;
mem['h507] = 'h00;
mem['h508] = 'h10;
mem['h509] = 'h10;
mem['h50A] = 'h10;
mem['h50B] = 'h10;
mem['h50C] = 'h10;
mem['h50D] = 'h00;
mem['h50E] = 'h10;
mem['h50F] = 'h00;
mem['h510] = 'h28;
mem['h511] = 'h28;
mem['h512] = 'h28;
mem['h513] = 'h00;
mem['h514] = 'h00;
mem['h515] = 'h00;
mem['h516] = 'h00;
mem['h517] = 'h00;
mem['h518] = 'h28;
mem['h519] = 'h28;
mem['h51A] = 'h7C;
mem['h51B] = 'h28;
mem['h51C] = 'h7C;
mem['h51D] = 'h28;
mem['h51E] = 'h28;
mem['h51F] = 'h00;
mem['h520] = 'h44;
mem['h521] = 'h38;
mem['h522] = 'h44;
mem['h523] = 'h44;
mem['h524] = 'h44;
mem['h525] = 'h38;
mem['h526] = 'h44;
mem['h527] = 'h00;
mem['h528] = 'h60;
mem['h529] = 'h64;
mem['h52A] = 'h08;
mem['h52B] = 'h10;
mem['h52C] = 'h20;
mem['h52D] = 'h4C;
mem['h52E] = 'h0C;
mem['h52F] = 'h00;
mem['h530] = 'h20;
mem['h531] = 'h50;
mem['h532] = 'h50;
mem['h533] = 'h20;
mem['h534] = 'h54;
mem['h535] = 'h48;
mem['h536] = 'h34;
mem['h537] = 'h00;
mem['h538] = 'h10;
mem['h539] = 'h10;
mem['h53A] = 'h10;
mem['h53B] = 'h00;
mem['h53C] = 'h00;
mem['h53D] = 'h00;
mem['h53E] = 'h00;
mem['h53F] = 'h00;
mem['h540] = 'h08;
mem['h541] = 'h10;
mem['h542] = 'h20;
mem['h543] = 'h20;
mem['h544] = 'h20;
mem['h545] = 'h10;
mem['h546] = 'h08;
mem['h547] = 'h00;
mem['h548] = 'h20;
mem['h549] = 'h10;
mem['h54A] = 'h08;
mem['h54B] = 'h08;
mem['h54C] = 'h08;
mem['h54D] = 'h10;
mem['h54E] = 'h20;
mem['h54F] = 'h00;
mem['h550] = 'h10;
mem['h551] = 'h54;
mem['h552] = 'h38;
mem['h553] = 'h10;
mem['h554] = 'h38;
mem['h555] = 'h54;
mem['h556] = 'h10;
mem['h557] = 'h00;
mem['h558] = 'h00;
mem['h559] = 'h10;
mem['h55A] = 'h10;
mem['h55B] = 'h7C;
mem['h55C] = 'h10;
mem['h55D] = 'h10;
mem['h55E] = 'h00;
mem['h55F] = 'h00;
mem['h560] = 'h00;
mem['h561] = 'h00;
mem['h562] = 'h00;
mem['h563] = 'h30;
mem['h564] = 'h30;
mem['h565] = 'h10;
mem['h566] = 'h20;
mem['h567] = 'h00;
mem['h568] = 'h00;
mem['h569] = 'h00;
mem['h56A] = 'h00;
mem['h56B] = 'h7C;
mem['h56C] = 'h00;
mem['h56D] = 'h00;
mem['h56E] = 'h00;
mem['h56F] = 'h00;
mem['h570] = 'h00;
mem['h571] = 'h00;
mem['h572] = 'h00;
mem['h573] = 'h00;
mem['h574] = 'h00;
mem['h575] = 'h30;
mem['h576] = 'h30;
mem['h577] = 'h00;
mem['h578] = 'h00;
mem['h579] = 'h04;
mem['h57A] = 'h08;
mem['h57B] = 'h10;
mem['h57C] = 'h20;
mem['h57D] = 'h40;
mem['h57E] = 'h00;
mem['h57F] = 'h00;
mem['h580] = 'h38;
mem['h581] = 'h44;
mem['h582] = 'h4C;
mem['h583] = 'h54;
mem['h584] = 'h64;
mem['h585] = 'h44;
mem['h586] = 'h38;
mem['h587] = 'h00;
mem['h588] = 'h10;
mem['h589] = 'h30;
mem['h58A] = 'h10;
mem['h58B] = 'h10;
mem['h58C] = 'h10;
mem['h58D] = 'h10;
mem['h58E] = 'h38;
mem['h58F] = 'h00;
mem['h590] = 'h38;
mem['h591] = 'h44;
mem['h592] = 'h04;
mem['h593] = 'h08;
mem['h594] = 'h10;
mem['h595] = 'h20;
mem['h596] = 'h7C;
mem['h597] = 'h00;
mem['h598] = 'h7C;
mem['h599] = 'h04;
mem['h59A] = 'h08;
mem['h59B] = 'h18;
mem['h59C] = 'h04;
mem['h59D] = 'h44;
mem['h59E] = 'h38;
mem['h59F] = 'h00;
mem['h5A0] = 'h08;
mem['h5A1] = 'h18;
mem['h5A2] = 'h28;
mem['h5A3] = 'h48;
mem['h5A4] = 'h7C;
mem['h5A5] = 'h08;
mem['h5A6] = 'h08;
mem['h5A7] = 'h00;
mem['h5A8] = 'h7C;
mem['h5A9] = 'h40;
mem['h5AA] = 'h78;
mem['h5AB] = 'h04;
mem['h5AC] = 'h04;
mem['h5AD] = 'h44;
mem['h5AE] = 'h38;
mem['h5AF] = 'h00;
mem['h5B0] = 'h1C;
mem['h5B1] = 'h20;
mem['h5B2] = 'h40;
mem['h5B3] = 'h78;
mem['h5B4] = 'h44;
mem['h5B5] = 'h44;
mem['h5B6] = 'h38;
mem['h5B7] = 'h00;
mem['h5B8] = 'h7C;
mem['h5B9] = 'h04;
mem['h5BA] = 'h08;
mem['h5BB] = 'h10;
mem['h5BC] = 'h20;
mem['h5BD] = 'h20;
mem['h5BE] = 'h20;
mem['h5BF] = 'h00;
mem['h5C0] = 'h38;
mem['h5C1] = 'h44;
mem['h5C2] = 'h44;
mem['h5C3] = 'h38;
mem['h5C4] = 'h44;
mem['h5C5] = 'h44;
mem['h5C6] = 'h38;
mem['h5C7] = 'h00;
mem['h5C8] = 'h38;
mem['h5C9] = 'h44;
mem['h5CA] = 'h44;
mem['h5CB] = 'h3C;
mem['h5CC] = 'h04;
mem['h5CD] = 'h08;
mem['h5CE] = 'h70;
mem['h5CF] = 'h00;
mem['h5D0] = 'h00;
mem['h5D1] = 'h00;
mem['h5D2] = 'h18;
mem['h5D3] = 'h18;
mem['h5D4] = 'h00;
mem['h5D5] = 'h18;
mem['h5D6] = 'h18;
mem['h5D7] = 'h00;
mem['h5D8] = 'h18;
mem['h5D9] = 'h18;
mem['h5DA] = 'h00;
mem['h5DB] = 'h18;
mem['h5DC] = 'h18;
mem['h5DD] = 'h08;
mem['h5DE] = 'h10;
mem['h5DF] = 'h00;
mem['h5E0] = 'h04;
mem['h5E1] = 'h08;
mem['h5E2] = 'h10;
mem['h5E3] = 'h20;
mem['h5E4] = 'h10;
mem['h5E5] = 'h08;
mem['h5E6] = 'h04;
mem['h5E7] = 'h00;
mem['h5E8] = 'h00;
mem['h5E9] = 'h00;
mem['h5EA] = 'h7C;
mem['h5EB] = 'h00;
mem['h5EC] = 'h7C;
mem['h5ED] = 'h00;
mem['h5EE] = 'h00;
mem['h5EF] = 'h00;
mem['h5F0] = 'h20;
mem['h5F1] = 'h10;
mem['h5F2] = 'h08;
mem['h5F3] = 'h04;
mem['h5F4] = 'h08;
mem['h5F5] = 'h10;
mem['h5F6] = 'h20;
mem['h5F7] = 'h00;
mem['h5F8] = 'h38;
mem['h5F9] = 'h44;
mem['h5FA] = 'h08;
mem['h5FB] = 'h10;
mem['h5FC] = 'h10;
mem['h5FD] = 'h00;
mem['h5FE] = 'h10;
mem['h5FF] = 'h00;
mem['h600] = 'h38;
mem['h601] = 'h44;
mem['h602] = 'h5C;
mem['h603] = 'h54;
mem['h604] = 'h5C;
mem['h605] = 'h40;
mem['h606] = 'h3C;
mem['h607] = 'h00;
mem['h608] = 'h10;
mem['h609] = 'h28;
mem['h60A] = 'h44;
mem['h60B] = 'h44;
mem['h60C] = 'h7C;
mem['h60D] = 'h44;
mem['h60E] = 'h44;
mem['h60F] = 'h00;
mem['h610] = 'h78;
mem['h611] = 'h44;
mem['h612] = 'h44;
mem['h613] = 'h78;
mem['h614] = 'h44;
mem['h615] = 'h44;
mem['h616] = 'h78;
mem['h617] = 'h00;
mem['h618] = 'h38;
mem['h619] = 'h44;
mem['h61A] = 'h40;
mem['h61B] = 'h40;
mem['h61C] = 'h40;
mem['h61D] = 'h44;
mem['h61E] = 'h38;
mem['h61F] = 'h00;
mem['h620] = 'h78;
mem['h621] = 'h44;
mem['h622] = 'h44;
mem['h623] = 'h44;
mem['h624] = 'h44;
mem['h625] = 'h44;
mem['h626] = 'h78;
mem['h627] = 'h00;
mem['h628] = 'h7C;
mem['h629] = 'h40;
mem['h62A] = 'h40;
mem['h62B] = 'h78;
mem['h62C] = 'h40;
mem['h62D] = 'h40;
mem['h62E] = 'h7C;
mem['h62F] = 'h00;
mem['h630] = 'h7C;
mem['h631] = 'h40;
mem['h632] = 'h40;
mem['h633] = 'h78;
mem['h634] = 'h40;
mem['h635] = 'h40;
mem['h636] = 'h40;
mem['h637] = 'h00;
mem['h638] = 'h3C;
mem['h639] = 'h40;
mem['h63A] = 'h40;
mem['h63B] = 'h40;
mem['h63C] = 'h4C;
mem['h63D] = 'h44;
mem['h63E] = 'h3C;
mem['h63F] = 'h00;
mem['h640] = 'h44;
mem['h641] = 'h44;
mem['h642] = 'h44;
mem['h643] = 'h7C;
mem['h644] = 'h44;
mem['h645] = 'h44;
mem['h646] = 'h44;
mem['h647] = 'h00;
mem['h648] = 'h38;
mem['h649] = 'h10;
mem['h64A] = 'h10;
mem['h64B] = 'h10;
mem['h64C] = 'h10;
mem['h64D] = 'h10;
mem['h64E] = 'h38;
mem['h64F] = 'h00;
mem['h650] = 'h04;
mem['h651] = 'h04;
mem['h652] = 'h04;
mem['h653] = 'h04;
mem['h654] = 'h04;
mem['h655] = 'h44;
mem['h656] = 'h38;
mem['h657] = 'h00;
mem['h658] = 'h44;
mem['h659] = 'h48;
mem['h65A] = 'h50;
mem['h65B] = 'h60;
mem['h65C] = 'h50;
mem['h65D] = 'h48;
mem['h65E] = 'h44;
mem['h65F] = 'h00;
mem['h660] = 'h40;
mem['h661] = 'h40;
mem['h662] = 'h40;
mem['h663] = 'h40;
mem['h664] = 'h40;
mem['h665] = 'h40;
mem['h666] = 'h7C;
mem['h667] = 'h00;
mem['h668] = 'h44;
mem['h669] = 'h6C;
mem['h66A] = 'h54;
mem['h66B] = 'h54;
mem['h66C] = 'h44;
mem['h66D] = 'h44;
mem['h66E] = 'h44;
mem['h66F] = 'h00;
mem['h670] = 'h44;
mem['h671] = 'h44;
mem['h672] = 'h64;
mem['h673] = 'h54;
mem['h674] = 'h4C;
mem['h675] = 'h44;
mem['h676] = 'h44;
mem['h677] = 'h00;
mem['h678] = 'h38;
mem['h679] = 'h44;
mem['h67A] = 'h44;
mem['h67B] = 'h44;
mem['h67C] = 'h44;
mem['h67D] = 'h44;
mem['h67E] = 'h38;
mem['h67F] = 'h00;
mem['h680] = 'h78;
mem['h681] = 'h44;
mem['h682] = 'h44;
mem['h683] = 'h78;
mem['h684] = 'h40;
mem['h685] = 'h40;
mem['h686] = 'h40;
mem['h687] = 'h00;
mem['h688] = 'h38;
mem['h689] = 'h44;
mem['h68A] = 'h44;
mem['h68B] = 'h44;
mem['h68C] = 'h54;
mem['h68D] = 'h48;
mem['h68E] = 'h34;
mem['h68F] = 'h00;
mem['h690] = 'h78;
mem['h691] = 'h44;
mem['h692] = 'h44;
mem['h693] = 'h78;
mem['h694] = 'h50;
mem['h695] = 'h48;
mem['h696] = 'h44;
mem['h697] = 'h00;
mem['h698] = 'h38;
mem['h699] = 'h44;
mem['h69A] = 'h40;
mem['h69B] = 'h38;
mem['h69C] = 'h04;
mem['h69D] = 'h44;
mem['h69E] = 'h38;
mem['h69F] = 'h00;
mem['h6A0] = 'h7C;
mem['h6A1] = 'h10;
mem['h6A2] = 'h10;
mem['h6A3] = 'h10;
mem['h6A4] = 'h10;
mem['h6A5] = 'h10;
mem['h6A6] = 'h10;
mem['h6A7] = 'h00;
mem['h6A8] = 'h44;
mem['h6A9] = 'h44;
mem['h6AA] = 'h44;
mem['h6AB] = 'h44;
mem['h6AC] = 'h44;
mem['h6AD] = 'h44;
mem['h6AE] = 'h38;
mem['h6AF] = 'h00;
mem['h6B0] = 'h44;
mem['h6B1] = 'h44;
mem['h6B2] = 'h44;
mem['h6B3] = 'h44;
mem['h6B4] = 'h44;
mem['h6B5] = 'h28;
mem['h6B6] = 'h10;
mem['h6B7] = 'h00;
mem['h6B8] = 'h44;
mem['h6B9] = 'h44;
mem['h6BA] = 'h44;
mem['h6BB] = 'h54;
mem['h6BC] = 'h54;
mem['h6BD] = 'h6C;
mem['h6BE] = 'h44;
mem['h6BF] = 'h00;
mem['h6C0] = 'h44;
mem['h6C1] = 'h44;
mem['h6C2] = 'h28;
mem['h6C3] = 'h10;
mem['h6C4] = 'h28;
mem['h6C5] = 'h44;
mem['h6C6] = 'h44;
mem['h6C7] = 'h00;
mem['h6C8] = 'h44;
mem['h6C9] = 'h44;
mem['h6CA] = 'h28;
mem['h6CB] = 'h10;
mem['h6CC] = 'h10;
mem['h6CD] = 'h10;
mem['h6CE] = 'h10;
mem['h6CF] = 'h00;
mem['h6D0] = 'h7C;
mem['h6D1] = 'h04;
mem['h6D2] = 'h08;
mem['h6D3] = 'h10;
mem['h6D4] = 'h20;
mem['h6D5] = 'h40;
mem['h6D6] = 'h7C;
mem['h6D7] = 'h00;
mem['h6D8] = 'h7C;
mem['h6D9] = 'h60;
mem['h6DA] = 'h60;
mem['h6DB] = 'h60;
mem['h6DC] = 'h60;
mem['h6DD] = 'h60;
mem['h6DE] = 'h7C;
mem['h6DF] = 'h00;
mem['h6E0] = 'h00;
mem['h6E1] = 'h40;
mem['h6E2] = 'h20;
mem['h6E3] = 'h10;
mem['h6E4] = 'h08;
mem['h6E5] = 'h04;
mem['h6E6] = 'h00;
mem['h6E7] = 'h00;
mem['h6E8] = 'h7C;
mem['h6E9] = 'h0C;
mem['h6EA] = 'h0C;
mem['h6EB] = 'h0C;
mem['h6EC] = 'h0C;
mem['h6ED] = 'h0C;
mem['h6EE] = 'h7C;
mem['h6EF] = 'h00;
mem['h6F0] = 'h00;
mem['h6F1] = 'h10;
mem['h6F2] = 'h28;
mem['h6F3] = 'h44;
mem['h6F4] = 'h00;
mem['h6F5] = 'h00;
mem['h6F6] = 'h00;
mem['h6F7] = 'h00;
mem['h6F8] = 'h00;
mem['h6F9] = 'h00;
mem['h6FA] = 'h00;
mem['h6FB] = 'h00;
mem['h6FC] = 'h00;
mem['h6FD] = 'h00;
mem['h6FE] = 'h00;
mem['h6FF] = 'hFF;
mem['h700] = 'h5C;
mem['h701] = 'h54;
mem['h702] = 'h54;
mem['h703] = 'h74;
mem['h704] = 'h54;
mem['h705] = 'h54;
mem['h706] = 'h5C;
mem['h707] = 'h00;
mem['h708] = 'h38;
mem['h709] = 'h44;
mem['h70A] = 'h44;
mem['h70B] = 'h44;
mem['h70C] = 'h7C;
mem['h70D] = 'h44;
mem['h70E] = 'h44;
mem['h70F] = 'h00;
mem['h710] = 'h7C;
mem['h711] = 'h40;
mem['h712] = 'h40;
mem['h713] = 'h78;
mem['h714] = 'h44;
mem['h715] = 'h44;
mem['h716] = 'h78;
mem['h717] = 'h00;
mem['h718] = 'h48;
mem['h719] = 'h48;
mem['h71A] = 'h48;
mem['h71B] = 'h48;
mem['h71C] = 'h48;
mem['h71D] = 'h48;
mem['h71E] = 'h7C;
mem['h71F] = 'h04;
mem['h720] = 'h1C;
mem['h721] = 'h24;
mem['h722] = 'h24;
mem['h723] = 'h24;
mem['h724] = 'h24;
mem['h725] = 'h24;
mem['h726] = 'h7E;
mem['h727] = 'h42;
mem['h728] = 'h7C;
mem['h729] = 'h40;
mem['h72A] = 'h40;
mem['h72B] = 'h78;
mem['h72C] = 'h40;
mem['h72D] = 'h40;
mem['h72E] = 'h7C;
mem['h72F] = 'h00;
mem['h730] = 'h38;
mem['h731] = 'h54;
mem['h732] = 'h54;
mem['h733] = 'h54;
mem['h734] = 'h38;
mem['h735] = 'h10;
mem['h736] = 'h10;
mem['h737] = 'h00;
mem['h738] = 'h7C;
mem['h739] = 'h40;
mem['h73A] = 'h40;
mem['h73B] = 'h40;
mem['h73C] = 'h40;
mem['h73D] = 'h40;
mem['h73E] = 'h40;
mem['h73F] = 'h00;
mem['h740] = 'h44;
mem['h741] = 'h44;
mem['h742] = 'h28;
mem['h743] = 'h10;
mem['h744] = 'h28;
mem['h745] = 'h44;
mem['h746] = 'h44;
mem['h747] = 'h00;
mem['h748] = 'h44;
mem['h749] = 'h44;
mem['h74A] = 'h44;
mem['h74B] = 'h4C;
mem['h74C] = 'h54;
mem['h74D] = 'h64;
mem['h74E] = 'h44;
mem['h74F] = 'h00;
mem['h750] = 'h54;
mem['h751] = 'h54;
mem['h752] = 'h44;
mem['h753] = 'h4C;
mem['h754] = 'h54;
mem['h755] = 'h64;
mem['h756] = 'h44;
mem['h757] = 'h00;
mem['h758] = 'h44;
mem['h759] = 'h48;
mem['h75A] = 'h50;
mem['h75B] = 'h60;
mem['h75C] = 'h50;
mem['h75D] = 'h48;
mem['h75E] = 'h44;
mem['h75F] = 'h00;
mem['h760] = 'h0C;
mem['h761] = 'h14;
mem['h762] = 'h24;
mem['h763] = 'h24;
mem['h764] = 'h24;
mem['h765] = 'h24;
mem['h766] = 'h44;
mem['h767] = 'h00;
mem['h768] = 'h44;
mem['h769] = 'h6C;
mem['h76A] = 'h54;
mem['h76B] = 'h54;
mem['h76C] = 'h44;
mem['h76D] = 'h44;
mem['h76E] = 'h44;
mem['h76F] = 'h00;
mem['h770] = 'h44;
mem['h771] = 'h44;
mem['h772] = 'h44;
mem['h773] = 'h7C;
mem['h774] = 'h44;
mem['h775] = 'h44;
mem['h776] = 'h44;
mem['h777] = 'h00;
mem['h778] = 'h38;
mem['h779] = 'h44;
mem['h77A] = 'h44;
mem['h77B] = 'h44;
mem['h77C] = 'h44;
mem['h77D] = 'h44;
mem['h77E] = 'h38;
mem['h77F] = 'h00;
mem['h780] = 'h7C;
mem['h781] = 'h44;
mem['h782] = 'h44;
mem['h783] = 'h44;
mem['h784] = 'h44;
mem['h785] = 'h44;
mem['h786] = 'h44;
mem['h787] = 'h00;
mem['h788] = 'h3C;
mem['h789] = 'h44;
mem['h78A] = 'h44;
mem['h78B] = 'h3C;
mem['h78C] = 'h14;
mem['h78D] = 'h24;
mem['h78E] = 'h44;
mem['h78F] = 'h00;
mem['h790] = 'h78;
mem['h791] = 'h44;
mem['h792] = 'h44;
mem['h793] = 'h78;
mem['h794] = 'h40;
mem['h795] = 'h40;
mem['h796] = 'h40;
mem['h797] = 'h00;
mem['h798] = 'h38;
mem['h799] = 'h44;
mem['h79A] = 'h40;
mem['h79B] = 'h40;
mem['h79C] = 'h40;
mem['h79D] = 'h44;
mem['h79E] = 'h38;
mem['h79F] = 'h00;
mem['h7A0] = 'h7C;
mem['h7A1] = 'h10;
mem['h7A2] = 'h10;
mem['h7A3] = 'h10;
mem['h7A4] = 'h10;
mem['h7A5] = 'h10;
mem['h7A6] = 'h10;
mem['h7A7] = 'h00;
mem['h7A8] = 'h44;
mem['h7A9] = 'h44;
mem['h7AA] = 'h44;
mem['h7AB] = 'h3C;
mem['h7AC] = 'h04;
mem['h7AD] = 'h44;
mem['h7AE] = 'h38;
mem['h7AF] = 'h00;
mem['h7B0] = 'h54;
mem['h7B1] = 'h54;
mem['h7B2] = 'h54;
mem['h7B3] = 'h38;
mem['h7B4] = 'h54;
mem['h7B5] = 'h54;
mem['h7B6] = 'h54;
mem['h7B7] = 'h00;
mem['h7B8] = 'h78;
mem['h7B9] = 'h44;
mem['h7BA] = 'h44;
mem['h7BB] = 'h78;
mem['h7BC] = 'h44;
mem['h7BD] = 'h44;
mem['h7BE] = 'h78;
mem['h7BF] = 'h00;
mem['h7C0] = 'h40;
mem['h7C1] = 'h40;
mem['h7C2] = 'h40;
mem['h7C3] = 'h78;
mem['h7C4] = 'h44;
mem['h7C5] = 'h44;
mem['h7C6] = 'h78;
mem['h7C7] = 'h00;
mem['h7C8] = 'h44;
mem['h7C9] = 'h44;
mem['h7CA] = 'h44;
mem['h7CB] = 'h74;
mem['h7CC] = 'h54;
mem['h7CD] = 'h54;
mem['h7CE] = 'h74;
mem['h7CF] = 'h00;
mem['h7D0] = 'h38;
mem['h7D1] = 'h44;
mem['h7D2] = 'h04;
mem['h7D3] = 'h18;
mem['h7D4] = 'h04;
mem['h7D5] = 'h44;
mem['h7D6] = 'h38;
mem['h7D7] = 'h00;
mem['h7D8] = 'h54;
mem['h7D9] = 'h54;
mem['h7DA] = 'h54;
mem['h7DB] = 'h54;
mem['h7DC] = 'h54;
mem['h7DD] = 'h54;
mem['h7DE] = 'h7C;
mem['h7DF] = 'h00;
mem['h7E0] = 'h78;
mem['h7E1] = 'h04;
mem['h7E2] = 'h04;
mem['h7E3] = 'h3C;
mem['h7E4] = 'h04;
mem['h7E5] = 'h04;
mem['h7E6] = 'h78;
mem['h7E7] = 'h00;
mem['h7E8] = 'h54;
mem['h7E9] = 'h54;
mem['h7EA] = 'h54;
mem['h7EB] = 'h54;
mem['h7EC] = 'h54;
mem['h7ED] = 'h54;
mem['h7EE] = 'h7C;
mem['h7EF] = 'h04;
mem['h7F0] = 'h44;
mem['h7F1] = 'h44;
mem['h7F2] = 'h44;
mem['h7F3] = 'h3C;
mem['h7F4] = 'h04;
mem['h7F5] = 'h04;
mem['h7F6] = 'h04;
mem['h7F7] = 'h00;
mem['h7F8] = 'h60;
mem['h7F9] = 'h20;
mem['h7FA] = 'h20;
mem['h7FB] = 'h38;
mem['h7FC] = 'h24;
mem['h7FD] = 'h24;
mem['h7FE] = 'h38;
mem['h7FF] = 'h00;
/ag_6502/trunk/agat7/ag_keyb.v
0,0 → 1,279
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 00:26:47 02/26/2012
// Design Name:
// Module Name: ag_keyb
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
module signal_filter(input clk, input in, output reg out);
always @(posedge clk) begin
out <= in;
end
endmodule
 
 
module ps2_keyb_driver(ps2_clk, ps2_data, ps2_code, ps2_up, ps2_ext, ps2_event);
input wire ps2_clk, ps2_data;
output reg[7:0] ps2_code = 0;
output reg ps2_up = 0, ps2_ext = 0, ps2_event = 0;
reg[10:0] shreg = 11'b11111111111;
wire[10:0] shnew = {ps2_data, shreg[10:1]};
wire start = shnew[0], stop = shnew[10], parity = shnew[9];
wire[7:0] data = shnew[8:1];
always @(negedge ps2_clk) begin
if (!start && stop && (parity == ~^data)) begin
if (data == 8'hE0) begin
ps2_ext <= 1;
end else if (data == 8'hF0) begin
ps2_up <= 1;
end else begin
ps2_code <= data;
ps2_event <= 1;
end
shreg <= 11'b11111111111;
end else begin
if (ps2_event) begin
ps2_up <= 0;
ps2_ext <= 0;
ps2_event <= 0;
end
shreg <= shnew;
end
end
endmodule
 
module ag_reg_decoder(keyb_in, shift, ctrl, keyb_out);
input wire[6:0] keyb_in;
input wire shift, ctrl;
output wire[6:0] keyb_out;
wire is_alpha = keyb_in[6] && !keyb_in[5];
wire is_digit = !keyb_in[6] && keyb_in[5] && keyb_in[3:0];
assign keyb_out =
is_alpha?
(shift?{1'b1,1'b1,keyb_in[4:0]}:
ctrl?{1'b0,1'b0,keyb_in[4:0]}:
keyb_in):
is_digit?
(shift?{1'b0,1'b1,~keyb_in[4],keyb_in[3:0]}:
keyb_in):
keyb_in;
endmodule
 
module ag_keyb_decoder(ps2_code, ps2_ext, shift, ctrl, alt, rus, keyb_code);
input wire[7:0] ps2_code;
input wire ps2_ext, shift, ctrl, alt, rus;
output wire[6:0] keyb_code;
reg[6:0] keyb_table[0:511]; // eng + rus
integer i;
wire[6:0] keyb_in;
assign keyb_in = keyb_table[{rus,ps2_code}];
ag_reg_decoder rd(keyb_in, shift, ctrl, keyb_code);
 
initial begin
for (i = 0; i < 512; i = i + 1) keyb_table[i] = 0;
// eng table
keyb_table['h15] = 'h51; // Q
keyb_table['h1D] = 'h57; // W
keyb_table['h24] = 'h45; // E
keyb_table['h2D] = 'h52; // R
keyb_table['h2C] = 'h54; // T
keyb_table['h35] = 'h59; // Y
keyb_table['h3C] = 'h55; // U
keyb_table['h43] = 'h49; // I
keyb_table['h44] = 'h4F; // O
keyb_table['h4D] = 'h50; // P
keyb_table['h54] = 'h5B; // {
keyb_table['h5B] = 'h5D; // }
keyb_table['h1C] = 'h41; // A
keyb_table['h1B] = 'h53; // S
keyb_table['h23] = 'h44; // D
keyb_table['h2B] = 'h46; // F
keyb_table['h34] = 'h47; // G
keyb_table['h33] = 'h48; // H
keyb_table['h3B] = 'h4A; // J
keyb_table['h42] = 'h4B; // K
keyb_table['h4B] = 'h4C; // L
keyb_table['h4C] = 'h2A; // :
keyb_table['h52] = 'h22; // "
keyb_table['h5D] = 'h5C; // \
keyb_table['h5A] = 'h0D; // enter
keyb_table['h1A] = 'h5A; // Z
keyb_table['h22] = 'h58; // X
keyb_table['h21] = 'h43; // C
keyb_table['h2A] = 'h56; // V
keyb_table['h32] = 'h42; // B
keyb_table['h31] = 'h4E; // N
keyb_table['h3A] = 'h4D; // M
keyb_table['h41] = 'h2C; // <
keyb_table['h49] = 'h2E; // >
keyb_table['h4A] = 'h2F; // ?
 
keyb_table['h05] = 'h04; // F1
keyb_table['h06] = 'h05; // F2
keyb_table['h04] = 'h06; // F3
 
keyb_table['h75] = 'h99; // UP
keyb_table['h74] = 'h95; // RIGHT
keyb_table['h6B] = 'h88; // LEFT
keyb_table['h66] = 'h88; // BS
keyb_table['h72] = 'h9A; // DOWN
keyb_table['h76] = 'h9B; // ESC
keyb_table['h29] = 'h20; // SPACE
keyb_table['h0E] = 'h00; // `
keyb_table['h16] = 'h31; // 1
keyb_table['h1E] = 'h32; // 2
keyb_table['h26] = 'h33; // 3
keyb_table['h25] = 'h34; // 4
keyb_table['h2E] = 'h35; // 5
keyb_table['h36] = 'h36; // 6
keyb_table['h3D] = 'h37; // 7
keyb_table['h3E] = 'h38; // 8
keyb_table['h46] = 'h39; // 9
keyb_table['h45] = 'h30; // 0
keyb_table['h4E] = 'h2D; // -
keyb_table['h55] = 'h3B; // =
 
// rus table + 100h
keyb_table['h115] = 'h4A; // Q
keyb_table['h11D] = 'h43; // W
keyb_table['h124] = 'h55; // E
keyb_table['h12D] = 'h4B; // R
keyb_table['h12C] = 'h45; // T
keyb_table['h135] = 'h4E; // Y
keyb_table['h13C] = 'h47; // U
keyb_table['h143] = 'h5B; // I
keyb_table['h144] = 'h5D; // O
keyb_table['h14D] = 'h5A; // P
keyb_table['h154] = 'h48; // {
keyb_table['h15B] = 'h3A; // }, check
keyb_table['h11C] = 'h46; // A
keyb_table['h11B] = 'h59; // S
keyb_table['h123] = 'h57; // D
keyb_table['h12B] = 'h41; // F
keyb_table['h134] = 'h50; // G
keyb_table['h133] = 'h52; // H
keyb_table['h13B] = 'h4F; // J
keyb_table['h142] = 'h4C; // K
keyb_table['h14B] = 'h44; // L
keyb_table['h14C] = 'h56; // :
keyb_table['h152] = 'h5C; // "
keyb_table['h15D] = 'h2B; // | -> .
keyb_table['h15A] = 'h0D; // enter
keyb_table['h11A] = 'h51; // Z
keyb_table['h122] = 'h5E; // X
keyb_table['h121] = 'h53; // C
keyb_table['h12A] = 'h4D; // V
keyb_table['h132] = 'h49; // B
keyb_table['h131] = 'h54; // N
keyb_table['h13A] = 'h58; // M
keyb_table['h141] = 'h42; // <
keyb_table['h149] = 'h2C; // >
keyb_table['h14A] = 'h2F; // ?
 
keyb_table['h105] = 'h04; // F1
keyb_table['h106] = 'h05; // F2
keyb_table['h104] = 'h06; // F3
 
keyb_table['h175] = 'h99; // UP
keyb_table['h174] = 'h95; // RIGHT
keyb_table['h16B] = 'h88; // LEFT
keyb_table['h166] = 'h88; // BS
keyb_table['h172] = 'h9A; // DOWN
keyb_table['h176] = 'h9B; // ESC
keyb_table['h129] = 'h20; // SPACE
keyb_table['h10E] = 'h00; // `
keyb_table['h116] = 'h31; // 1
keyb_table['h11E] = 'h32; // 2
keyb_table['h126] = 'h33; // 3
keyb_table['h125] = 'h34; // 4
keyb_table['h12E] = 'h35; // 5
keyb_table['h136] = 'h36; // 6
keyb_table['h13D] = 'h37; // 7
keyb_table['h13E] = 'h38; // 8
keyb_table['h146] = 'h39; // 9
keyb_table['h145] = 'h30; // 0
keyb_table['h14E] = 'h2D; // -
keyb_table['h155] = 'h3B; // =
end
endmodule
 
module ag_keyb(clk, ps2_bus, keyb_reg, keyb_clear, keyb_rus, keyb_rst, keyb_pause);
input clk;
input wire[1:0] ps2_bus;
output wire[7:0] keyb_reg;
input wire keyb_clear;
output wire keyb_rus;
output wire keyb_rst;
output wire keyb_pause;
wire ps2_clk, ps2_data;
assign {ps2_clk, ps2_data} = ps2_bus;
reg[7:0] keyb_code;
reg clr = 0, got = 0;
reg lshift = 0, rshift = 0, ctrl = 0, alt = 0, rus = 0, rst = 0, pause = 0;
wire[7:0] ps2_code;
wire ps2_up, ps2_ext, ps2_event;
assign keyb_reg = clr?0:keyb_code;
assign keyb_rus = rus;
assign keyb_rst = rst;
assign keyb_pause = pause;
wire[6:0] dec_code;
ps2_keyb_driver kd(ps2_clk, ps2_data, ps2_code, ps2_up, ps2_ext, ps2_event);
ag_keyb_decoder dec(ps2_code, ps2_ext, lshift | rshift, ctrl, alt, rus, dec_code);
always @(posedge clk) begin
if (keyb_clear) clr <= 1;
if (ps2_event && !got) begin
if (!ps2_up) begin
if (ps2_code == 8'h12 && ctrl) rus <= 0;
else if (ps2_code == 8'h14 && lshift) rus <= 0;
else if (ps2_code == 8'h59 && ctrl) rus <= 1;
else if (ps2_code == 8'h14 && rshift) rus <= 1;
clr <= 0;
keyb_code <= {|dec_code, dec_code};
end
if (ps2_code == 8'h12) lshift <= ~ps2_up;
else if (ps2_code == 8'h59) rshift <= ~ps2_up;
else if (ps2_code == 8'h14 || ps2_code == 8'h0D) ctrl <= ~ps2_up; // ctrl or tab
else if (ps2_code == 8'h11) alt <= ~ps2_up;
else if (ps2_code == 8'h7E) pause <= ~ps2_up;
if (ps2_code == 8'h76 && ctrl) rst <= ~ps2_up;
got <= 1;
end
if (!ps2_event) got <= 0;
end
endmodule
/ag_6502/trunk/agat7/states.v
0,0 → 1,337
// This file has been generated automatically
// by the GenStates tool
// Copyright (c) Oleg Odintsov
// This tool is a part of Agat hardware project
 
// Level of optimization: infinite
// Total number of actions: 82
wire E_AB__PC;
wire E_AB__EA;
wire E_AB__S;
wire E_PC__PC_1;
wire E_T__0;
wire E_N_Z__SB;
wire E_N_Z__RES;
wire E_N_Z__SB_RES;
wire E_C__RES;
wire E_V__RES;
wire E_V__SB_6_;
wire A_ALU_CF_0;
wire A_ALU_DF_0;
wire A_ALU_OP_ADC;
wire A_SB_0;
wire A_ALU_B_SB;
wire A_ALU_CF_1;
wire A_ALU_CF_ALUC;
wire A_ALU_B_NOTSB;
wire A_ALU_OP_ORA;
wire A_ALU_A_DB;
wire A_SB_X;
wire A_ALU_A_EAL;
wire A_SB_PCL;
wire A_SB_Y;
wire A_ALU_A_ALU;
wire A_ALU_A_S;
wire E_CF__IR_5_;
wire E_IF__IR_5_;
wire E_DF__IR_5_;
wire E_VF__0;
wire E_T__0IFNF__IR_5_;
wire E_T__0IFVF__IR_5_;
wire E_T__0IFCF__IR_5_;
wire E_T__0IFZF__IR_5_;
wire E_EA__DB;
wire E_EAL__DB;
wire E_PCL__RES;
wire E_T__0IF_C7F;
wire A_ALU_A_SIGN;
wire A_SB_PCH;
wire E_PCH__RES;
wire E_EAH__DB;
wire E_EAL__ALU;
wire E_T__T_1IF_ALUCZ;
wire E_EAH__ALU;
wire E_PCL__ALU;
wire A_SB_DB;
wire E_AC__SB;
wire A_ALU_A_AC;
wire E_AC__RES;
wire A_ALU_OP_AND;
wire A_ALU_OP_EOR;
wire A_ALU_A_X;
wire A_ALU_A_Y;
wire A_ALU_DF_D;
wire A_ALU_CF_C;
wire A_ALU_OP_ASL;
wire A_RW_W;
wire A_SB_ALU;
wire E_DB__SB;
wire A_ALU_OP_LSR;
wire A_ALU_OP_ROL;
wire A_ALU_OP_ROR;
wire A_SB_AC;
wire E_X__SB;
wire E_Y__SB;
wire A_SB_S;
wire E_S__SB;
wire E_PC__EA;
wire E_S__ALU;
wire A_SB_P;
wire E_P__SB;
wire E_X__RES;
wire E_Y__RES;
wire E_DB__ALU;
wire E_DB__PCH;
wire E_PCL__EAL;
wire E_DB__PCL;
wire E_DB__P;
wire E_P__DB;
wire E_PCL__DB;
 
// Actions assignments
 
// action: AB <= PC:
assign E_AB__PC = (!L[10] && ((!L[0] && ((!L[1] && ((!L[2] && ((!L[9] && (!L[3] || (L[3] && ((!L[4] && (!L[7] || ({L[7],L[8]} == 2'b10))) || (L[4] && ((!L[5] && ((!L[6] && (!L[8] || ({L[7],L[8]} == 2'b01))) || L[6])) || L[5])))))) || ({L[3],L[4],L[9]} == 3'b011))) || (L[2] && (!L[9] || ({L[3],L[8],L[9]} == 3'b101))))) || (L[1] && ((!L[9] && ((!L[2] && ((!L[8] && (({L[3],L[4],L[7]} == 3'b001) || L[3])) || ({L[3],L[4],L[7],L[8]} == 4'b0011))) || L[2])) || ({L[2],L[3],L[8],L[9]} == 4'b1101))))) || (L[0] && ((!L[9] && (!L[1] || (L[1] && ((!L[2] && (!L[3] || (L[3] && ((!L[4] && ((!L[5] && ((!L[6] && (!L[8] || ({L[7],L[8]} == 2'b01))) || L[6])) || L[5])) || L[4])))) || L[2])))) || (({L[3],L[8],L[9]} == 3'b101) && (({L[2],L[4]} == 2'b01) || L[2])))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[7],L[8],L[9],L[10]} == 10'b0000010101);
 
// action: AB <= EA:
assign E_AB__EA = (({L[9],L[10]} == 2'b01) && ((!L[2] && (({L[0],L[1],L[3],L[4],L[5],L[6],L[7],L[8]} == 8'b00000001) || (L[0] && (!L[3] || ({L[3],L[4],L[8]} == 3'b110))))) || (({L[2],L[3],L[8]} == 3'b110) && (({L[0],L[1],L[4],L[5],L[6],L[7]} == 6'b000110) || L[4])))) || (L[9] && ((!L[10] && ((({L[0],L[2]} == 2'b01) && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || ({L[3],L[8]} == 2'b11))) || (L[0] && ((!L[3] && ((!L[1] && (!L[2] || (L[2] && (({L[4],L[8]} == 2'b00) || L[4])))) || (L[1] && (!L[2] || (L[2] && (({L[4],L[8]} == 2'b00) || L[4])))))) || (({L[3],L[8]} == 2'b11) && (({L[2],L[4]} == 2'b01) || L[2])))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[10]} == 10'b0000000001)));
 
// action: AB <= S:
assign E_AB__S = (({L[0],L[1],L[2],L[3],L[4],L[7],L[9],L[10]} == 8'b00000001) && (!L[8] || ({L[5],L[6],L[8]} == 3'b011))) || (({L[0],L[1],L[2],L[4],L[7],L[9],L[10]} == 7'b0000010) && (!L[3] || (L[3] && (({L[5],L[8]} == 2'b00) || L[5]))));
 
// action: PC <= PC + 1:
assign E_PC__PC_1 = (!L[10] && ((!L[9] && ((!L[0] && ((!L[1] && ((!L[2] && (!L[8] || (({L[3],L[8]} == 2'b01) && ((!L[4] && (({L[5],L[6],L[7]} == 3'b100) || L[7])) || L[4])))) || L[2])) || (L[1] && ((!L[2] && ((!L[8] && (({L[3],L[4],L[7]} == 3'b001) || L[3])) || ({L[3],L[4],L[7],L[8]} == 4'b0011))) || L[2])))) || (L[0] && (!L[1] || (L[1] && ((!L[2] && (!L[3] || (L[3] && ((!L[4] && ((!L[5] && ((!L[6] && (!L[8] || ({L[7],L[8]} == 2'b01))) || L[6])) || L[5])) || L[4])))) || L[2])))))) || (({L[3],L[8],L[9]} == 3'b101) && (({L[0],L[2],L[4]} == 3'b101) || (L[2] && ((!L[0] && ((!L[1] && ((!L[4] && (!L[5] || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))) || L[4])) || L[1])) || L[0])))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000110101);
 
// action: T <= 0:
assign E_T__0 = (!L[0] && ((!L[1] && ((!L[2] && ((!L[10] && ((({L[3],L[8],L[9]} == 3'b101) && (({L[4],L[5],L[7]} == 3'b000) || (L[4] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))) || (L[8] && ((({L[7],L[9]} == 2'b01) && (({L[3],L[4],L[5]} == 3'b101) || ({L[3],L[4]} == 2'b01))) || (L[7] && ((!L[9] && (!L[4] || ({L[3],L[4],L[5],L[6]} == 4'b1100))) || ({L[3],L[4],L[9]} == 3'b011))))))) || (({L[3],L[4],L[7],L[10]} == 4'b0001) && (({L[5],L[6],L[8],L[9]} == 4'b0001) || (({L[8],L[9]} == 2'b10) && (({L[5],L[6]} == 2'b01) || L[5])))))) || (L[2] && ((({L[3],L[8],L[9],L[10]} == 4'b1001) && (({L[4],L[5],L[6],L[7]} == 4'b0110) || L[4])) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || (({L[3],L[8]} == 2'b11) && (!L[5] || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))))) || ({L[3],L[4],L[8]} == 3'b011))))))) || (L[1] && ((({L[2],L[8],L[9],L[10]} == 4'b0100) && (({L[3],L[4],L[7]} == 3'b001) || L[3])) || (L[2] && ((({L[6],L[7],L[9],L[10]} == 4'b0110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))) || (L[10] && ((!L[9] && ((!L[3] && ((({L[4],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[4],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[3] && (({L[4],L[6],L[7],L[8]} == 4'b1010) || (({L[4],L[8]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[3],L[4],L[8],L[9]} == 4'b1101) && (({L[6],L[7]} == 2'b00) || L[6])))))))))) || (L[0] && ((!L[9] && ((!L[2] && (({L[3],L[4],L[8],L[10]} == 4'b1101) || (L[8] && ((!L[4] && (({L[3],L[10]} == 2'b01) || ({L[3],L[10]} == 2'b10))) || ({L[3],L[4],L[10]} == 3'b011))))) || ({L[2],L[3],L[4],L[8],L[10]} == 5'b11101))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101)))));
 
// action: N,Z <= SB:
assign E_N_Z__SB = (({L[6],L[7]} == 2'b01) && ((({L[0],L[2],L[3],L[5],L[8],L[9],L[10]} == 7'b0010100) && (({L[1],L[4]} == 2'b01) || ({L[1],L[4]} == 2'b10))) || (L[5] && ((!L[9] && ((!L[2] && (({L[0],L[1],L[3],L[4],L[8],L[10]} == 6'b101101) || (L[8] && ((!L[10] && ((!L[4] && (({L[0],L[3]} == 2'b00) || L[3])) || ({L[0],L[1],L[3],L[4]} == 4'b0111))) || ({L[0],L[3],L[10]} == 3'b101))))) || ({L[2],L[3],L[4],L[8],L[10]} == 5'b11101))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101))))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010110110);
 
// action: N,Z <= RES:
assign E_N_Z__RES = (!L[9] && ((({L[2],L[4],L[8],L[10]} == 4'b0010) && (({L[0],L[1],L[3],L[6],L[7]} == 5'b00011) || (L[3] && ((!L[0] && ((({L[1],L[7]} == 2'b01) && (({L[5],L[6]} == 2'b00) || L[6])) || (L[1] && (!L[7] || ({L[5],L[6],L[7]} == 3'b011))))) || (L[0] && (({L[1],L[6],L[7]} == 3'b000) || (L[6] && (({L[1],L[5]} == 2'b00) || (L[5] && (({L[1],L[7]} == 2'b00) || L[7])))))))))) || (L[10] && ((({L[0],L[1],L[2]} == 3'b011) && ((({L[3],L[4],L[8]} == 3'b010) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[3] && ((({L[4],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[4],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[0],L[1]} == 2'b10) && ((({L[2],L[3],L[4],L[8]} == 4'b0001) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[4] && ((({L[2],L[3],L[8]} == 3'b001) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b10) && (({L[6],L[7]} == 2'b00) || L[6])))))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[1] && ((({L[0],L[4],L[6],L[7]} == 4'b0011) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (L[0] && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[3],L[4],L[8]} == 3'b011) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[0],L[1],L[3],L[4],L[8]} == 5'b01001) && (({L[6],L[7]} == 2'b00) || L[6]))));
 
// action: N,Z <= SB,RES:
assign E_N_Z__SB_RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00100100010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110100110);
 
// action: C <= RES:
assign E_C__RES = (({L[0],L[1],L[6],L[7]} == 4'b0100) && (({L[2],L[3],L[4],L[8],L[9],L[10]} == 6'b010100) || (L[2] && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110))))) || (L[6] && ((!L[9] && ((({L[2],L[4],L[8],L[10]} == 4'b0010) && (({L[0],L[1],L[3],L[7]} == 4'b0001) || (L[3] && (({L[0],L[1],L[7]} == 3'b010) || (L[0] && (({L[1],L[5],L[7]} == 3'b001) || (L[5] && (({L[1],L[7]} == 2'b00) || L[7])))))))) || (L[10] && ((({L[0],L[1],L[2],L[7]} == 4'b0110) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || (({L[0],L[1]} == 2'b10) && ((({L[2],L[3],L[4],L[8]} == 4'b0001) && (({L[5],L[7]} == 2'b01) || L[5])) || (L[4] && ((({L[2],L[3],L[8]} == 3'b001) && (({L[5],L[7]} == 2'b01) || L[5])) || (({L[3],L[8]} == 2'b10) && (({L[5],L[7]} == 2'b01) || L[5])))))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[1] && ((!L[4] && ((({L[0],L[5],L[7]} == 3'b110) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (L[7] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))))) || (({L[0],L[3],L[4],L[8]} == 4'b1011) && (({L[5],L[7]} == 2'b01) || L[5])))) || ({L[0],L[1],L[3],L[4],L[7],L[8]} == 6'b010001)))));
 
// action: V <= RES:
assign E_V__RES = (({L[0],L[5],L[6],L[9]} == 4'b1110) && ((!L[2] && (({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) || (L[8] && ((!L[4] && (({L[1],L[3],L[10]} == 3'b001) || (({L[3],L[10]} == 2'b10) && (({L[1],L[7]} == 2'b00) || L[7])))) || ({L[1],L[3],L[4],L[10]} == 4'b0011))))) || ({L[1],L[2],L[3],L[4],L[8],L[10]} == 6'b011101))) || (({L[0],L[1],L[2],L[5],L[6],L[9],L[10]} == 7'b1011110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)));
 
// action: V <= SB[6]:
assign E_V__SB_6_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00100100010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110100110);
 
// action: ALU_CF = 0:
assign A_ALU_CF_0 = (!L[10] && ((({L[2],L[3],L[8],L[9]} == 4'b0001) && (({L[0],L[1],L[4],L[6],L[7]} == 5'b00000) || (L[4] && (({L[0],L[1]} == 2'b00) || L[0])))) || (L[8] && ((!L[9] && ((!L[2] && ((({L[0],L[4],L[5]} == 3'b000) && (({L[1],L[3],L[6],L[7]} == 4'b0000) || (L[3] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || ({L[1],L[7]} == 2'b11))))))) || (L[0] && (({L[3],L[4]} == 2'b00) || ({L[3],L[4]} == 2'b11))))) || ({L[2],L[4]} == 2'b11))) || (({L[0],L[3],L[9]} == 3'b001) && ((({L[1],L[2]} == 2'b00) && (({L[4],L[6],L[7]} == 3'b000) || L[4])) || ({L[1],L[2],L[4],L[5],L[6],L[7]} == 6'b110011))))))) || (({L[0],L[1],L[2],L[5],L[6],L[7],L[9],L[10]} == 8'b01101101) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11)))));
 
// action: ALU_DF = 0:
assign A_ALU_DF_0 = (!L[9] && ((({L[8],L[10]} == 2'b01) && (({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7]} == 8'b00000000) || (L[6] && (({L[0],L[1],L[2],L[3],L[4],L[5],L[7]} == 7'b0000000) || (L[7] && (({L[0],L[1],L[2],L[3],L[4],L[5]} == 6'b100110) || (L[2] && (({L[0],L[1],L[3],L[4],L[5]} == 5'b10110) || (({L[0],L[1]} == 2'b01) && (({L[3],L[4]} == 2'b01) || ({L[3],L[4]} == 2'b10))))))))))) || (L[8] && ((!L[10] && ((!L[2] && ((({L[0],L[4]} == 2'b00) && ((({L[1],L[3]} == 2'b00) && (({L[5],L[6],L[7]} == 3'b000) || L[6])) || (L[3] && ((!L[5] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))) || (({L[1],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (L[0] && ((!L[1] && (!L[3] || (L[3] && (({L[4],L[5],L[6],L[7]} == 4'b0011) || L[4])))) || (L[1] && (({L[3],L[4]} == 2'b00) || L[4])))))) || ({L[2],L[4]} == 2'b11))) || (({L[6],L[7],L[10]} == 3'b111) && (({L[0],L[1],L[2],L[3],L[4],L[5]} == 6'b100000) || (L[4] && (({L[0],L[1],L[2],L[3],L[5]} == 5'b10000) || ({L[0],L[1],L[2],L[3]} == 4'b0111))))))))) || (({L[9],L[10]} == 2'b10) && ((!L[0] && ((({L[1],L[2],L[3]} == 3'b000) && ((({L[4],L[7]} == 2'b00) && (!L[5] || (L[5] && (!L[8] || ({L[6],L[8]} == 2'b01))))) || L[4])) || (L[2] && ((({L[3],L[4],L[6],L[7]} == 4'b0011) && (({L[1],L[8]} == 2'b00) || ({L[1],L[8]} == 2'b11))) || (L[3] && ((!L[8] && (({L[1],L[4],L[5],L[6],L[7]} == 5'b00110) || L[4])) || ({L[1],L[4],L[6],L[7],L[8]} == 5'b00111))))))) || (L[0] && ((!L[1] && ((!L[2] && (({L[3],L[4],L[8]} == 3'b000) || (L[4] && (!L[8] || ({L[3],L[8]} == 2'b01))))) || (L[2] && ((({L[3],L[5],L[6],L[7]} == 4'b0011) && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || (L[3] && (({L[4],L[5],L[6],L[7],L[8]} == 5'b00111) || ({L[4],L[8]} == 2'b10))))))) || (L[1] && (({L[2],L[3],L[4],L[8]} == 4'b0000) || (L[4] && ((!L[8] && (({L[2],L[3]} == 2'b00) || L[3])) || ({L[2],L[3],L[8]} == 3'b001)))))))));
 
// action: ALU_OP = ADC:
assign A_ALU_OP_ADC = (!L[9] && ((({L[8],L[10]} == 2'b01) && (({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7]} == 8'b00000000) || (L[6] && ((!L[1] && (({L[0],L[2],L[3],L[4],L[5],L[7]} == 6'b000000) || (({L[0],L[3],L[4]} == 3'b111) && (({L[5],L[7]} == 2'b01) || L[5])))) || (({L[0],L[1],L[2],L[7]} == 4'b0111) && (({L[3],L[4]} == 2'b01) || ({L[3],L[4]} == 2'b10))))))) || (L[8] && ((!L[2] && ((!L[10] && ((({L[0],L[4]} == 2'b00) && ((({L[1],L[3]} == 2'b00) && (({L[5],L[6],L[7]} == 3'b000) || L[6])) || (L[3] && ((!L[5] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))) || (({L[1],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (L[0] && ((!L[1] && (!L[3] || (L[3] && ((({L[4],L[6]} == 2'b01) && (({L[5],L[7]} == 2'b01) || L[5])) || L[4])))) || (L[1] && (!L[3] || (L[3] && (({L[4],L[5],L[6],L[7]} == 4'b0111) || L[4])))))))) || (({L[0],L[1],L[3],L[6],L[10]} == 5'b10011) && (({L[5],L[7]} == 2'b01) || L[5])))) || (({L[2],L[4]} == 2'b11) && (!L[10] || ({L[0],L[1],L[3],L[6],L[7],L[10]} == 6'b011111))))))) || (({L[9],L[10]} == 2'b10) && ((!L[0] && ((({L[1],L[2],L[3]} == 3'b000) && ((({L[4],L[7]} == 2'b00) && (!L[5] || (L[5] && (!L[8] || ({L[6],L[8]} == 2'b01))))) || L[4])) || (L[2] && ((({L[3],L[4],L[6],L[7]} == 4'b0011) && (({L[1],L[8]} == 2'b00) || ({L[1],L[8]} == 2'b11))) || (L[3] && ((!L[8] && (({L[1],L[4],L[5],L[6],L[7]} == 5'b00110) || L[4])) || ({L[1],L[4],L[6],L[7],L[8]} == 5'b00111))))))) || (L[0] && ((!L[1] && ((!L[2] && (({L[3],L[4],L[8]} == 3'b000) || (L[4] && (!L[8] || ({L[3],L[8]} == 2'b01))))) || (L[2] && (({L[3],L[4],L[6],L[8]} == 4'b1100) || (L[6] && ((!L[3] && ((({L[4],L[8]} == 2'b00) && (({L[5],L[7]} == 2'b01) || L[5])) || (({L[4],L[8]} == 2'b11) && (({L[5],L[7]} == 2'b01) || L[5])))) || (L[3] && ((({L[4],L[8]} == 2'b01) && (({L[5],L[7]} == 2'b01) || L[5])) || ({L[4],L[8]} == 2'b10))))))))) || (L[1] && (({L[2],L[3],L[4],L[8]} == 4'b0000) || (L[4] && ((!L[8] && (({L[2],L[3]} == 2'b00) || L[3])) || ({L[2],L[3],L[8]} == 3'b001)))))))));
 
// action: SB = 0:
assign A_SB_0 = (!L[10] && ((({L[2],L[8],L[9]} == 3'b010) && ((!L[3] && ((({L[0],L[1],L[4],L[7]} == 4'b0000) && (({L[5],L[6]} == 2'b00) || L[6])) || ({L[0],L[4]} == 2'b11))) || (({L[0],L[3],L[4]} == 3'b010) && ((!L[5] && (({L[1],L[6]} == 2'b00) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))) || (({L[1],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (L[9] && ((!L[0] && (({L[1],L[2],L[3],L[4],L[7]} == 5'b00000) || (L[2] && ((({L[1],L[3]} == 2'b01) && ((!L[8] && (({L[4],L[5],L[6],L[7]} == 4'b0110) || L[4])) || ({L[4],L[5],L[6],L[7],L[8]} == 5'b01101))) || (L[1] && ((!L[3] && ((({L[6],L[7]} == 2'b00) && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || (L[6] && (({L[4],L[8]} == 2'b00) || (L[8] && (({L[4],L[7]} == 2'b01) || L[4])))))) || (L[3] && ((({L[4],L[8]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])) || ({L[4],L[8]} == 2'b10))))))))) || (L[0] && ((!L[2] && ((!L[3] && (!L[4] || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b110))) || ({L[2],L[3],L[4],L[8]} == 4'b1110))))))) || (({L[0],L[10]} == 2'b01) && ((!L[9] && ((({L[1],L[2],L[3],L[4],L[7]} == 5'b00000) && (!L[5] || (L[5] && (({L[6],L[8]} == 2'b01) || ({L[6],L[8]} == 2'b10))))) || (L[2] && (({L[1],L[3],L[4],L[5],L[6],L[7],L[8]} == 7'b0101100) || (L[1] && (({L[3],L[4],L[6],L[7],L[8]} == 5'b01110) || (L[3] && (({L[4],L[6],L[7],L[8]} == 4'b0110) || (L[4] && (({L[6],L[7],L[8]} == 3'b000) || (L[6] && (({L[7],L[8]} == 2'b00) || L[7])))))))))))) || ({L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9]} == 9'b000000001)));
 
// action: ALU_B = SB:
assign A_ALU_B_SB = (!L[0] && ((({L[1],L[2]} == 2'b00) && ((!L[4] && ((!L[7] && ((({L[3],L[5]} == 2'b00) && ((({L[6],L[10]} == 2'b01) && (!L[9] || ({L[8],L[9]} == 2'b01))) || (L[6] && ((!L[9] && (({L[8],L[10]} == 2'b01) || L[8])) || ({L[9],L[10]} == 2'b10))))) || (L[5] && ((!L[9] && (({L[3],L[6],L[8],L[10]} == 4'b0101) || (L[8] && ((!L[10] && (({L[3],L[6]} == 2'b01) || L[3])) || ({L[3],L[6],L[10]} == 3'b001))))) || ({L[3],L[6],L[9],L[10]} == 4'b0110))))) || ({L[3],L[6],L[7],L[8],L[9],L[10]} == 6'b111100))) || ({L[3],L[4],L[9],L[10]} == 4'b0110))) || (L[2] && ((!L[9] && ((({L[3],L[4],L[5],L[6],L[8],L[10]} == 6'b101101) && (({L[1],L[7]} == 2'b00) || ({L[1],L[7]} == 2'b11))) || (L[4] && (({L[1],L[8],L[10]} == 3'b010) || (L[1] && ((({L[8],L[10]} == 2'b01) && (({L[3],L[5],L[6],L[7]} == 4'b0111) || (L[3] && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[8] && (!L[10] || ({L[3],L[5],L[6],L[7],L[10]} == 5'b11111))))))))) || (({L[9],L[10]} == 2'b10) && ((!L[1] && (({L[3],L[4],L[5],L[6],L[7],L[8]} == 6'b001000) || (L[3] && ((!L[8] && (({L[4],L[5],L[6],L[7]} == 4'b0110) || L[4])) || ({L[4],L[5],L[7],L[8]} == 4'b0101))))) || (L[1] && ((!L[3] && ((({L[6],L[7]} == 2'b00) && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || (L[6] && (({L[4],L[8]} == 2'b00) || (L[8] && (({L[4],L[5],L[7]} == 3'b011) || L[4])))))) || (L[3] && ((({L[4],L[8]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])) || ({L[4],L[8]} == 2'b10))))))))))) || (L[0] && ((!L[10] && ((({L[8],L[9]} == 2'b01) && ((!L[3] && (!L[2] || ({L[1],L[2],L[4],L[7]} == 4'b0100))) || ({L[3],L[4]} == 2'b11))) || (L[8] && ((!L[1] && ((!L[2] && ((!L[9] && (!L[3] || (L[3] && (({L[4],L[7]} == 2'b00) || L[4])))) || ({L[3],L[9]} == 2'b01))) || (L[2] && (({L[3],L[4],L[7],L[9]} == 4'b1001) || (L[4] && (!L[9] || ({L[3],L[7],L[9]} == 3'b001))))))) || (L[1] && ((!L[3] && (({L[2],L[4]} == 2'b00) || (L[4] && (!L[9] || ({L[2],L[9]} == 2'b01))))) || ({L[3],L[4],L[9]} == 3'b110))))))) || (({L[1],L[7],L[9],L[10]} == 4'b0001) && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10)))))));
 
// action: ALU_CF = 1:
assign A_ALU_CF_1 = (!L[2] && ((!L[1] && ((!L[9] && ((!L[5] && ((!L[3] && (({L[0],L[4],L[7],L[8],L[10]} == 5'b00001) || (L[8] && (({L[0],L[4],L[6],L[10]} == 4'b0010) || (L[0] && (({L[4],L[6],L[7],L[10]} == 4'b0111) || (L[4] && (!L[10] || ({L[6],L[7],L[10]} == 3'b111))))))))) || (({L[3],L[6],L[7]} == 3'b111) && (({L[0],L[4],L[8],L[10]} == 4'b0010) || (L[0] && (({L[4],L[8],L[10]} == 3'b010) || ({L[4],L[8],L[10]} == 3'b101))))))) || (({L[5],L[8],L[10]} == 3'b110) && ((!L[3] && (({L[0],L[4],L[6]} == 3'b001) || ({L[0],L[4]} == 2'b11))) || (({L[0],L[3],L[4]} == 3'b010) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[3],L[4],L[9],L[10]} == 4'b0010) && ((!L[8] && (({L[0],L[6],L[7]} == 3'b010) || L[0])) || ({L[0],L[5],L[6],L[7],L[8]} == 5'b00101))))) || (({L[0],L[1],L[3],L[10]} == 4'b1100) && (({L[4],L[8],L[9]} == 3'b001) || ({L[4],L[8],L[9]} == 3'b110))))) || (({L[2],L[6]} == 2'b11) && (({L[0],L[1],L[3],L[4],L[5],L[7],L[8],L[9],L[10]} == 9'b001010010) || (L[7] && ((!L[1] && (({L[0],L[3],L[4],L[5],L[8],L[9],L[10]} == 7'b1110001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (!L[5] || ({L[0],L[5]} == 2'b01))) || (({L[3],L[8]} == 2'b11) && (!L[5] || ({L[0],L[5]} == 2'b01))))) || ({L[0],L[3],L[4],L[5],L[8]} == 5'b10101))))) || (({L[0],L[1],L[5]} == 3'b011) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)))))));
 
// action: ALU_CF = ALUC:
assign A_ALU_CF_ALUC = ({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b0111010) || (({L[0],L[4],L[9],L[10]} == 4'b1110) && ((!L[2] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))) || ({L[2],L[3],L[8]} == 3'b110)));
 
// action: ALU_B = NOT SB:
assign A_ALU_B_NOTSB = (({L[0],L[1],L[2],L[4],L[6],L[10]} == 6'b000000) && ((!L[7] && ((!L[5] && (({L[3],L[8],L[9]} == 3'b001) || (L[8] && (!L[9] || ({L[3],L[9]} == 2'b01))))) || ({L[3],L[5],L[9]} == 3'b011))) || ({L[3],L[5],L[7],L[8],L[9]} == 5'b10110))) || (L[6] && (({L[0],L[1],L[2],L[3],L[4],L[5],L[7],L[8],L[9],L[10]} == 10'b0001000100) || (L[7] && ((!L[9] && ((({L[2],L[4],L[8],L[10]} == 4'b0010) && (({L[0],L[1],L[3]} == 3'b000) || (L[3] && (({L[0],L[1],L[5]} == 3'b010) || (L[0] && (({L[1],L[5]} == 2'b00) || L[5])))))) || (L[10] && ((({L[0],L[1],L[2],L[5]} == 4'b0110) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || (({L[0],L[1]} == 2'b10) && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[1] && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[0],L[3],L[4],L[8]} == 4'b1011))) || ({L[0],L[1],L[3],L[4],L[5],L[8]} == 6'b010001)))))));
 
// action: ALU_OP = ORA:
assign A_ALU_OP_ORA = (!L[0] && ((({L[1],L[2],L[3],L[4],L[7]} == 5'b00000) && (({L[5],L[6],L[8],L[9],L[10]} == 5'b11110) || (L[10] && ((!L[9] && (({L[5],L[6],L[8]} == 3'b110) || (L[8] && (!L[6] || ({L[5],L[6]} == 2'b01))))) || ({L[5],L[6],L[8],L[9]} == 4'b0001))))) || (L[2] && ((({L[1],L[3],L[4],L[5],L[6],L[7]} == 6'b010110) && (({L[8],L[9],L[10]} == 3'b001) || ({L[8],L[9],L[10]} == 3'b110))) || (L[1] && ((({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[9],L[10]} == 2'b10) && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[3],L[4],L[8]} == 3'b011) && (({L[6],L[7]} == 2'b00) || L[6])))))))))) || (L[0] && ((!L[5] && ((!L[6] && ((!L[7] && ((!L[10] && ((!L[4] && (({L[1],L[2],L[3],L[8],L[9]} == 5'b01001) || (L[8] && ((!L[2] && (({L[1],L[3],L[9]} == 3'b010) || ({L[3],L[9]} == 2'b01))) || ({L[1],L[2],L[3],L[9]} == 4'b0111))))) || ({L[1],L[2],L[3],L[4],L[8],L[9]} == 6'b010111))) || (({L[1],L[9],L[10]} == 3'b001) && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || ({L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 7'b0001110))) || ({L[2],L[3],L[4],L[6],L[8],L[9],L[10]} == 7'b0001110))) || ({L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 7'b0001110)));
 
// action: ALU_A = DB:
assign A_ALU_A_DB = (!L[10] && ((({L[8],L[9]} == 2'b01) && ((({L[0],L[1],L[2],L[3],L[4]} == 5'b01100) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[4] && (({L[0],L[2],L[3]} == 3'b011) || (L[0] && (!L[2] || ({L[2],L[3]} == 2'b11))))))) || (L[8] && ((!L[0] && (({L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[9]} == 8'b00001101) || (L[2] && ((({L[3],L[4],L[9]} == 3'b101) && (({L[1],L[5],L[6],L[7]} == 4'b0110) || (L[1] && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[4] && (!L[9] || (({L[1],L[3],L[9]} == 3'b101) && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (L[0] && ((!L[2] && (!L[3] || ({L[3],L[4],L[9]} == 3'b110))) || ({L[2],L[4],L[9]} == 3'b110))))))) || (({L[0],L[10]} == 2'b01) && ((!L[9] && ((!L[7] && ((({L[1],L[4]} == 2'b00) && ((({L[2],L[3]} == 2'b00) && (({L[5],L[6],L[8]} == 3'b110) || (L[8] && (!L[6] || ({L[5],L[6]} == 2'b01))))) || ({L[2],L[3],L[5],L[6],L[8]} == 5'b11110))) || ({L[1],L[2],L[3],L[4],L[8]} == 5'b11110))) || ({L[1],L[2],L[3],L[4],L[6],L[7],L[8]} == 7'b1111110))) || ({L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9]} == 9'b000000001)));
 
// action: SB = X:
assign A_SB_X = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01100001010) || (({L[8],L[10]} == 2'b10) && ((!L[9] && ((!L[2] && ((!L[4] && (({L[0],L[1],L[3],L[5],L[6],L[7]} == 6'b011001) || ({L[0],L[3]} == 2'b10))) || ({L[0],L[1],L[3],L[4],L[5],L[6],L[7]} == 7'b0111001))) || (({L[2],L[4]} == 2'b11) && ((!L[0] && (!L[1] || (L[1] && (({L[6],L[7]} == 2'b00) || L[6])))) || (L[0] && (!L[1] || (L[1] && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (({L[0],L[1],L[2],L[5],L[6],L[7],L[9]} == 7'b0110011) && (({L[3],L[4]} == 2'b01) || ({L[3],L[4]} == 2'b10)))));
 
// action: ALU_A = EAL:
assign A_ALU_A_EAL = (({L[0],L[1],L[2],L[3],L[8]} == 5'b00000) && (({L[4],L[5],L[6],L[7],L[9],L[10]} == 6'b000001) || ({L[4],L[9],L[10]} == 3'b110))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110110010);
 
// action: SB = PCL:
assign A_SB_PCL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100001) || ({L[0],L[1],L[2],L[3],L[4],L[8],L[9],L[10]} == 8'b00001010);
 
// action: SB = Y:
assign A_SB_Y = (({L[0],L[1],L[2],L[4],L[5],L[6],L[7],L[9],L[10]} == 9'b001000110) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (({L[4],L[10]} == 2'b10) && (({L[0],L[2],L[3],L[8],L[9]} == 5'b10001) || (L[8] && ((!L[9] && (({L[1],L[2],L[3],L[6],L[7]} == 5'b11001) || (L[3] && ((!L[2] && (({L[0],L[1],L[5],L[6],L[7]} == 5'b00001) || L[0])) || ({L[1],L[2],L[6],L[7]} == 4'b1101))))) || ({L[0],L[1],L[2],L[3],L[5],L[6],L[7],L[9]} == 8'b00100011)))));
 
// action: ALU_A = ALU:
assign A_ALU_A_ALU = (!L[3] && ((!L[4] && (({L[0],L[1],L[2],L[5],L[6],L[7],L[8],L[9],L[10]} == 9'b000010001) || (({L[9],L[10]} == 2'b10) && ((!L[2] && ((!L[8] && ((({L[0],L[1],L[7]} == 3'b000) && (({L[5],L[6]} == 2'b00) || L[6])) || L[0])) || (({L[0],L[1],L[7],L[8]} == 4'b0001) && (!L[6] || ({L[5],L[6]} == 2'b01))))) || (({L[0],L[1],L[2],L[8]} == 4'b0111) && (({L[6],L[7]} == 2'b00) || L[6])))))) || (({L[0],L[1],L[2],L[4],L[8],L[9],L[10]} == 7'b0111001) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[0],L[1],L[2],L[3],L[9],L[10]} == 6'b011101) && ((({L[4],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[4],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6]))));
 
// action: ALU_A = S:
assign A_ALU_A_S = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100010) || (({L[0],L[1],L[2],L[4],L[7],L[8],L[9],L[10]} == 8'b00000100) && ((!L[3] && (({L[5],L[6]} == 2'b00) || L[6])) || L[3]));
 
// action: CF <= IR[5]:
assign E_CF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011000010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011100010);
 
// action: IF <= IR[5]:
assign E_IF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011010010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011110010);
 
// action: DF <= IR[5]:
assign E_DF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011011010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011111010);
 
// action: VF <= 0:
assign E_VF__0 = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00011101010);
 
// action: T <= 0 IF NF != IR[5]:
assign E_T__0IFNF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001000100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001100100);
 
// action: T <= 0 IF VF != IR[5]:
assign E_T__0IFVF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001010100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001110100);
 
// action: T <= 0 IF CF != IR[5]:
assign E_T__0IFCF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001001100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001101100);
 
// action: T <= 0 IF ZF == IR[5]:
assign E_T__0IFZF__IR_5_ = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001011100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00001111100);
 
// action: EA <= DB:
assign E_EA__DB = ({L[0],L[2],L[3],L[8],L[9],L[10]} == 6'b010100) || ({L[0],L[3],L[8],L[9],L[10]} == 5'b10100);
 
// action: EAL <= DB:
assign E_EAL__DB = (({L[0],L[1],L[2],L[3],L[8],L[9],L[10]} == 7'b0000100) && (({L[4],L[5],L[6],L[7]} == 4'b0100) || L[4])) || (({L[3],L[8],L[9],L[10]} == 4'b1100) && (({L[0],L[2],L[4]} == 3'b101) || L[2]));
 
// action: PCL <= RES:
assign E_PCL__RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000110110) || ({L[0],L[1],L[2],L[3],L[4],L[8],L[9],L[10]} == 8'b00001010);
 
// action: T <= 0 IF_C7F:
assign E_T__0IF_C7F = ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000010010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000011010);
 
// action: ALU_A = SIGN:
assign A_ALU_A_SIGN = ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000010110) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000011110);
 
// action: SB = PCH:
assign A_SB_PCH = ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000010110) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[8],L[9],L[10]} == 9'b000011110);
 
// action: PCH <= RES:
assign E_PCH__RES = (({L[0],L[1],L[2],L[3]} == 4'b0000) && ((!L[7] && (({L[4],L[8],L[9],L[10]} == 4'b1110) || (({L[4],L[10]} == 2'b01) && ((!L[9] && (({L[5],L[6],L[8]} == 3'b011) || (L[5] && (({L[6],L[8]} == 2'b01) || ({L[6],L[8]} == 2'b10))))) || ({L[5],L[6],L[8],L[9]} == 4'b0001))))) || ({L[4],L[7],L[8],L[9],L[10]} == 5'b11110))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110110001);
 
// action: EAH <= DB:
assign E_EAH__DB = (!L[8] && (({L[0],L[2],L[3],L[4],L[9],L[10]} == 6'b100001) || (({L[3],L[9],L[10]} == 3'b110) && (({L[0],L[2],L[4]} == 3'b101) || L[2])))) || ({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b1001110);
 
// action: EAL <= ALU:
assign E_EAL__ALU = (({L[2],L[3],L[4],L[9],L[10]} == 5'b00001) && (({L[0],L[1],L[5],L[6],L[7],L[8]} == 6'b000001) || ({L[0],L[8]} == 2'b10))) || (({L[9],L[10]} == 2'b10) && ((({L[0],L[2]} == 2'b01) && (({L[1],L[3],L[4],L[5],L[6],L[7],L[8]} == 7'b0101101) || ({L[4],L[8]} == 2'b10))) || (L[0] && ((!L[2] && (!L[3] || ({L[3],L[4],L[8]} == 3'b110))) || ({L[2],L[4],L[8]} == 3'b110)))));
 
// action: T <= T + 1 IF_ALUCZ:
assign E_T__T_1IF_ALUCZ = (({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b0111010) && ((({L[1],L[5]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[5] && ((!L[6] && (({L[1],L[7]} == 2'b00) || L[7])) || ({L[1],L[6]} == 2'b01))))) || (({L[0],L[4],L[9],L[10]} == 4'b1110) && ((!L[2] && ((({L[3],L[8]} == 2'b01) && (({L[1],L[7]} == 2'b00) || (L[7] && (({L[5],L[6]} == 2'b01) || L[5])))) || (({L[3],L[8]} == 2'b10) && (({L[1],L[7]} == 2'b00) || (L[7] && (({L[5],L[6]} == 2'b01) || L[5])))))) || (({L[2],L[3],L[8]} == 3'b110) && ((({L[1],L[5]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[5] && (({L[1],L[7]} == 2'b00) || L[7]))))));
 
// action: EAH <= ALU:
assign E_EAH__ALU = ({L[0],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b0111110) || (({L[0],L[4]} == 2'b11) && ((!L[2] && (({L[3],L[8],L[9],L[10]} == 4'b0001) || ({L[3],L[8],L[9],L[10]} == 4'b1110))) || ({L[2],L[3],L[8],L[9],L[10]} == 5'b11110)));
 
// action: PCL <= ALU:
assign E_PCL__ALU = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000011) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110110001);
 
// action: SB = DB:
assign A_SB_DB = (!L[1] && ((!L[9] && ((!L[2] && ((({L[0],L[3],L[4],L[7],L[8],L[10]} == 6'b000110) && (({L[5],L[6]} == 2'b01) || L[5])) || (L[0] && ((({L[3],L[4],L[8],L[10]} == 4'b1101) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])) || (L[8] && ((!L[4] && ((({L[3],L[10]} == 2'b01) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])) || (({L[3],L[10]} == 2'b10) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))) || (({L[3],L[4],L[10]} == 3'b011) && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))))) || (({L[2],L[3],L[4],L[8],L[10]} == 5'b11101) && (({L[0],L[5],L[6],L[7]} == 4'b0101) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))) || (({L[9],L[10]} == 2'b10) && (({L[0],L[2],L[3],L[4],L[5],L[7],L[8]} == 7'b0010101) || (L[2] && ((!L[3] && ((({L[4],L[8]} == 2'b00) && ((!L[0] && (({L[5],L[6],L[7]} == 3'b011) || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))) || (({L[4],L[8]} == 2'b11) && (({L[0],L[5],L[6],L[7]} == 4'b0101) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))) || (({L[3],L[4],L[8]} == 3'b101) && ((!L[0] && (({L[5],L[6],L[7]} == 3'b011) || (L[5] && (({L[6],L[7]} == 2'b00) || L[7])))) || (L[0] && ((!L[5] && (({L[6],L[7]} == 2'b00) || L[6])) || L[5])))))))))) || (({L[1],L[5],L[7]} == 3'b111) && ((!L[6] && ((({L[2],L[8],L[9]} == 3'b010) && (({L[0],L[3],L[4],L[10]} == 4'b0000) || (L[0] && ((!L[4] && (({L[3],L[10]} == 2'b01) || ({L[3],L[10]} == 2'b10))) || ({L[3],L[4],L[10]} == 3'b011))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101))))))) || ({L[0],L[2],L[3],L[4],L[6],L[8],L[9],L[10]} == 8'b10101100)));
 
// action: AC <= SB:
assign E_AC__SB = (({L[6],L[7]} == 2'b01) && ((({L[0],L[2],L[3],L[5],L[8],L[9],L[10]} == 7'b0010100) && (({L[1],L[4]} == 2'b01) || ({L[1],L[4]} == 2'b10))) || (({L[0],L[5]} == 2'b11) && ((!L[9] && ((!L[2] && (({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) || (L[8] && ((!L[4] && (({L[3],L[10]} == 2'b01) || ({L[3],L[10]} == 2'b10))) || ({L[3],L[4],L[10]} == 3'b011))))) || ({L[2],L[3],L[4],L[8],L[10]} == 5'b11101))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101))))))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010110110);
 
// action: ALU_A = AC:
assign A_ALU_A_AC = (!L[1] && ((({L[0],L[2],L[4],L[5],L[6],L[7],L[9],L[10]} == 8'b01010010) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (L[0] && ((!L[9] && ((({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[10] && ((({L[2],L[3],L[4],L[8]} == 4'b0001) && (({L[6],L[7]} == 2'b00) || L[6])) || (L[4] && ((({L[2],L[3],L[8]} == 3'b001) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b10) && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[4] && ((({L[3],L[8]} == 2'b00) && (({L[6],L[7]} == 2'b00) || L[6])) || (({L[3],L[8]} == 2'b11) && (({L[6],L[7]} == 2'b00) || L[6])))) || (({L[3],L[4],L[8]} == 3'b011) && (({L[6],L[7]} == 2'b00) || L[6])))))))) || (({L[1],L[2],L[3],L[4],L[8],L[9],L[10]} == 7'b1010100) && (({L[0],L[7]} == 2'b00) || ({L[0],L[5],L[6],L[7]} == 4'b1111)));
 
// action: AC <= RES:
assign E_AC__RES = ({L[0],L[1],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 9'b010100100) || (L[0] && ((!L[9] && ((!L[2] && ((({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))) || (L[8] && ((!L[4] && ((({L[1],L[3],L[10]} == 3'b001) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))) || (({L[3],L[10]} == 2'b10) && (({L[1],L[5],L[7]} == 3'b000) || (L[5] && (({L[1],L[6],L[7]} == 3'b000) || (L[6] && (({L[1],L[7]} == 2'b00) || L[7])))))))) || (({L[1],L[3],L[4],L[10]} == 4'b0011) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))))))) || (({L[1],L[2],L[3],L[4],L[8],L[10]} == 6'b011101) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111))))) || (({L[1],L[2],L[9],L[10]} == 4'b0110) && ((!L[4] && ((!L[7] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (({L[5],L[6],L[7]} == 3'b111) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))))) || (({L[3],L[4],L[8]} == 3'b011) && (!L[7] || ({L[5],L[6],L[7]} == 3'b111)))))));
 
// action: ALU_OP = AND:
assign A_ALU_OP_AND = (({L[0],L[1],L[2],L[4],L[5],L[6],L[7],L[9],L[10]} == 9'b001010010) && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || (({L[0],L[1],L[5],L[6],L[7]} == 5'b10100) && ((!L[9] && (({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) || (L[10] && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)))));
 
// action: ALU_OP = EOR:
assign A_ALU_OP_EOR = (({L[0],L[1],L[5],L[6],L[7],L[9]} == 6'b100100) && (({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) || (L[10] && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || (({L[0],L[1],L[2],L[5],L[6],L[7],L[9],L[10]} == 8'b10101010) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)));
 
// action: ALU_A = X:
assign A_ALU_A_X = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010011100) || (({L[0],L[1],L[4],L[5],L[6],L[7],L[10]} == 7'b0001110) && (({L[2],L[3],L[8],L[9]} == 4'b1001) || (L[8] && (({L[2],L[3],L[9]} == 3'b000) || (L[3] && (({L[2],L[9]} == 2'b00) || ({L[2],L[9]} == 2'b11)))))));
 
// action: ALU_A = Y:
assign A_ALU_A_Y = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010001100) || (({L[0],L[1],L[4],L[5],L[6],L[7],L[10]} == 7'b0000110) && (({L[2],L[3],L[8],L[9]} == 4'b1001) || (L[8] && (({L[2],L[3],L[9]} == 3'b000) || (L[3] && (({L[2],L[9]} == 2'b00) || ({L[2],L[9]} == 2'b11)))))));
 
// action: ALU_DF = D:
assign A_ALU_DF_D = (({L[0],L[5],L[6],L[9]} == 4'b1110) && ((!L[2] && (({L[1],L[3],L[4],L[8],L[10]} == 5'b01101) || (L[8] && ((!L[4] && (({L[1],L[3],L[10]} == 3'b001) || (({L[3],L[10]} == 2'b10) && (({L[1],L[7]} == 2'b00) || L[7])))) || ({L[1],L[3],L[4],L[10]} == 4'b0011))))) || ({L[1],L[2],L[3],L[4],L[8],L[10]} == 6'b011101))) || (({L[0],L[1],L[2],L[5],L[6],L[9],L[10]} == 7'b1011110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)));
 
// action: ALU_CF = C:
assign A_ALU_CF_C = (({L[0],L[1],L[5],L[6]} == 4'b1011) && ((!L[9] && (({L[2],L[3],L[4],L[8],L[10]} == 5'b01010) || (L[10] && (({L[2],L[3],L[4],L[8]} == 4'b0001) || (L[4] && (({L[2],L[3],L[8]} == 3'b001) || ({L[3],L[8]} == 2'b10))))))) || (({L[2],L[9],L[10]} == 3'b110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))) || (L[1] && ((({L[0],L[7]} == 2'b00) && (({L[2],L[3],L[4],L[8],L[9],L[10]} == 6'b010100) || (L[2] && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110))))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b1010111100)));
 
// action: ALU_OP = ASL:
assign A_ALU_OP_ASL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010000100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011000) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: RW = W:
assign A_RW_W = (!L[1] && ((!L[6] && ((!L[5] && ((({L[0],L[2],L[4],L[7]} == 4'b0000) && ((!L[8] && (({L[3],L[9],L[10]} == 3'b001) || ({L[9],L[10]} == 2'b10))) || ({L[3],L[8],L[9],L[10]} == 4'b0110))) || (L[7] && ((({L[0],L[2],L[9],L[10]} == 4'b0110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))) || (L[0] && ((({L[2],L[9],L[10]} == 3'b001) && (({L[3],L[4],L[8]} == 3'b001) || (L[4] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))))))))) || (({L[0],L[2],L[3],L[4],L[5],L[7]} == 6'b000010) && (({L[8],L[9],L[10]} == 3'b001) || ({L[8],L[9],L[10]} == 3'b110))))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b0010010010))) || (({L[0],L[1],L[2]} == 3'b011) && ((({L[9],L[10]} == 2'b01) && ((({L[6],L[7]} == 2'b00) && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || (L[6] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))))) || (L[9] && ((!L[10] && ((!L[4] && (({L[3],L[5],L[6],L[7],L[8]} == 5'b00010) || (L[8] && ((!L[5] && ((!L[6] && (({L[3],L[7]} == 2'b00) || ({L[3],L[7]} == 2'b11))) || ({L[3],L[6]} == 2'b01))) || (({L[3],L[5]} == 2'b01) && (({L[6],L[7]} == 2'b00) || L[6])))))) || ({L[3],L[4],L[5],L[6],L[7],L[8]} == 6'b010011))) || (({L[3],L[4],L[8],L[10]} == 4'b1101) && (({L[6],L[7]} == 2'b00) || L[6]))))));
 
// action: SB = ALU:
assign A_SB_ALU = ({L[0],L[1],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 9'b011000110) || (({L[0],L[1],L[2],L[7],L[10]} == 5'b01101) && ((!L[9] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || ({L[3],L[4],L[8],L[9]} == 4'b1101)));
 
// action: DB <= SB:
assign E_DB__SB = (!L[1] && ((!L[5] && ((!L[6] && (({L[0],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 8'b00100010) || (L[7] && ((({L[0],L[2],L[9],L[10]} == 4'b0110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))) || (L[0] && ((({L[2],L[9],L[10]} == 3'b001) && (({L[3],L[4],L[8]} == 3'b001) || (L[4] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))))))))) || ({L[0],L[2],L[3],L[4],L[6],L[7],L[8],L[9],L[10]} == 9'b001010010))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b0000100001))) || (({L[0],L[1],L[2]} == 3'b011) && ((!L[7] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b00110) || (L[10] && ((!L[9] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || ({L[3],L[4],L[8],L[9]} == 4'b1101))))) || (({L[5],L[6],L[7],L[9],L[10]} == 5'b00110) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011)))));
 
// action: ALU_OP = LSR:
assign A_ALU_OP_LSR = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010010100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011010) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: ALU_OP = ROL:
assign A_ALU_OP_ROL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010100100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011100) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: ALU_OP = ROR:
assign A_ALU_OP_ROR = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010110100) || (({L[0],L[1],L[2],L[5],L[6],L[7]} == 6'b011110) && ((({L[9],L[10]} == 2'b01) && (({L[3],L[4],L[8]} == 3'b010) || (L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))))) || ({L[3],L[4],L[8],L[9],L[10]} == 5'b00110)));
 
// action: SB = AC:
assign A_SB_AC = (!L[1] && ((!L[5] && (({L[0],L[2],L[3],L[4],L[6],L[7],L[8],L[9],L[10]} == 9'b001010010) || (({L[0],L[6],L[7]} == 3'b101) && ((({L[2],L[9],L[10]} == 3'b001) && (({L[3],L[4],L[8]} == 3'b001) || (L[4] && (({L[3],L[8]} == 2'b01) || ({L[3],L[8]} == 2'b10))))) || (L[2] && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[4] && (({L[3],L[8]} == 2'b00) || ({L[3],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b011))))))))) || ({L[0],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 10'b0010101100))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010101100);
 
// action: X <= SB:
assign E_X__SB = (({L[1],L[2],L[5],L[6],L[7],L[8],L[9]} == 7'b1010110) && ((!L[10] && (({L[0],L[3],L[4]} == 3'b000) || (L[3] && (!L[4] || ({L[0],L[4]} == 2'b01))))) || ({L[0],L[3],L[10]} == 3'b101))) || (({L[1],L[2],L[5],L[6],L[7]} == 5'b11101) && (({L[3],L[4],L[8],L[9],L[10]} == 5'b11001) || (({L[9],L[10]} == 2'b10) && ((!L[3] && (({L[4],L[8]} == 2'b00) || ({L[4],L[8]} == 2'b11))) || ({L[3],L[4],L[8]} == 3'b101)))));
 
// action: Y <= SB:
assign E_Y__SB = (({L[0],L[1],L[5],L[6],L[7],L[10]} == 6'b001010) && ((!L[4] && (({L[2],L[3],L[8],L[9]} == 4'b1001) || (L[8] && (({L[2],L[3],L[9]} == 3'b000) || (L[3] && (({L[2],L[9]} == 2'b00) || ({L[2],L[9]} == 2'b11))))))) || ({L[2],L[3],L[4],L[8],L[9]} == 5'b10111))) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00111101001);
 
// action: SB = S:
assign A_SB_S = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01011101100);
 
// action: S <= SB:
assign E_S__SB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01011001100);
 
// action: PC <= EA:
assign E_PC__EA = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00110010110);
 
// action: S <= ALU:
assign E_S__ALU = (({L[0],L[1],L[2],L[4],L[7],L[8]} == 6'b000000) && ((({L[3],L[9],L[10]} == 3'b001) && (!L[6] || ({L[5],L[6]} == 2'b01))) || (({L[9],L[10]} == 2'b10) && ((!L[3] && (({L[5],L[6]} == 2'b00) || L[6])) || L[3])))) || ({L[0],L[1],L[2],L[3],L[4],L[7],L[8],L[9],L[10]} == 9'b000000110);
 
// action: SB = P:
assign A_SB_P = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010000010);
 
// action: P <= SB:
assign E_P__SB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010100110);
 
// action: X <= RES:
assign E_X__RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010111100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b01010011100);
 
// action: Y <= RES:
assign E_Y__RES = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010001100) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00010011100);
 
// action: DB <= ALU:
assign E_DB__ALU = ({L[0],L[1],L[2],L[3],L[4],L[6],L[7],L[8],L[9],L[10]} == 10'b0110011110) || (({L[0],L[1],L[2],L[6],L[7],L[10]} == 6'b011111) && ((!L[9] && ((!L[3] && (({L[4],L[8]} == 2'b00) || L[4])) || (L[3] && (({L[4],L[8]} == 2'b00) || L[8])))) || ({L[3],L[4],L[8],L[9]} == 4'b1101)));
 
// action: DB <= PCH:
assign E_DB__PCH = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000010) || ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100110);
 
// action: PCL <= EAL:
assign E_PCL__EAL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000100101);
 
// action: DB <= PCL:
assign E_DB__PCL = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000110);
 
// action: DB <= P:
assign E_DB__P = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000000001);
 
// action: P <= DB:
assign E_P__DB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000010110);
 
// action: PCL <= DB:
assign E_PCL__DB = ({L[0],L[1],L[2],L[3],L[4],L[5],L[6],L[7],L[8],L[9],L[10]} == 11'b00000010001);
/ag_6502/trunk/agat7/ag_6502.v
0,0 → 1,344
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 10:50:36 02/15/2012
// Design Name:
// Module Name: ag_6502
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
// Specify following define to allow external
// clocking for phi1 and phi2
// In such case you may use ag6502_ext_clock module
// with baseclk frequency ~ 10 x phi_0
`define AG6502_EXTERNAL_CLOCK
 
 
`ifndef AG6502_EXTERNAL_CLOCK
module ag6502_clock(input phi_0, output phi_1, output phi_2);
wire phi_01;
not#3(phi_1,phi_0);
or(phi_01,~phi_0, phi_1);
not#1(phi_2, phi_01);
endmodule
 
 
`else
 
module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
parameter DELAY = 1; // delay in semi-waves of baseclk
initial phi_1 = 0;
integer cnt = 0;
always @(posedge baseclk) begin
if (phi_0 != phi_1) begin
if (!cnt) begin phi_1 <= ~phi_1; cnt <= DELAY; end
else cnt <= cnt - 1;
end
end
endmodule
 
// baseclk is used to simulate delays on a real hardware
module ag6502_ext_clock(input baseclk, input phi_0, output phi_1, output phi_2);
parameter DELAY1 = 3, DELAY2 = 1; // delays in semi-waves of baseclk
wire phi_1_neg, phi_01;
ag6502_phase_shift#DELAY1 d1(baseclk, phi_0, phi_1_neg);
assign phi_1 = ~phi_1_neg;
and(phi_01, phi_0, phi_1_neg);
ag6502_phase_shift#DELAY2 d2(baseclk, phi_01, phi_2);
endmodule
 
`endif
 
 
`define ALU_ORA 3'd0
`define ALU_AND 3'd1
`define ALU_EOR 3'd2
`define ALU_ADC 3'd3
`define ALU_ASL 3'd4
`define ALU_LSR 3'd5
`define ALU_ROL 3'd6
`define ALU_ROR 3'd7
 
 
module ag6502_decimal(ADD, D_IN, NEG, CORR);
input wire[4:0] ADD;
input wire D_IN, NEG;
output wire[4:0] CORR;
wire C9 = {ADD[4]^NEG, ADD[3:0]} > 5'd9;
assign CORR = D_IN?{C9^NEG, C9?ADD[3:0] + (NEG?4'd10:4'd6): ADD[3:0]}: ADD;
endmodule
 
 
module ag6502_alu(A, B, OP, NEG, C_IN, D_IN, R, C_OUT, V_OUT);
input wire[7:0] A, B;
input wire[2:0] OP;
input wire C_IN, D_IN, NEG;
output wire[7:0] R;
output wire C_OUT, V_OUT;
wire[4:0] ADD_L;
ag6502_decimal DL({1'b0, A[3:0]} + {1'b0, B[3:0]} + C_IN, D_IN, NEG, ADD_L);
wire CF_H = ADD_L[4];
 
wire[4:0] ADD_H;
ag6502_decimal DH({1'b0, A[7:4]} + {1'b0, B[7:4]} + CF_H, D_IN, NEG, ADD_H);
 
assign
{C_OUT,R} = (OP==`ALU_ORA)? A | B:
(OP==`ALU_AND)? A & B:
(OP==`ALU_EOR)? A ^ B:
(OP==`ALU_ADC)? {ADD_H, ADD_L[3:0]}:
(OP==`ALU_ASL)? {A[7], A[6:0], 1'b0}:
(OP==`ALU_LSR)? {A[0], 1'b0, A[7:1]}:
(OP==`ALU_ROL)? {A[7], A[6:0], C_IN}:
(OP==`ALU_ROR)? {A[0], C_IN, A[7:1]}:
8'bX;
assign V_OUT = (A[7] == B[7]) && (A[7] != R[7]);
endmodule
 
/*
System AB/DB discipline:
1. For CPU
Phi1 up => CPU set ab/db_out buses
Phi2 down => CPU reads data from db_in
2. For Memory / other devices
Phi2 up => perform read/write operation
*/
 
 
module ag6502(input phi_0,
`ifdef AG6502_EXTERNAL_CLOCK
input phi_1, input phi_2,
`else
output phi_1, output phi_2,
`endif
output reg[15:0] ab,
output wire read,
input[7:0] db_in, output reg[7:0] db_out,
input rdy,
input rst, input irq, input nmi,
input so,
output sync);
`ifndef AG6502_EXTERNAL_CLOCK
ag6502_clock cgen(phi_0, phi_1, phi_2);
`endif
 
reg rdyg = 1;
reg[2:0] T = 7;
reg[7:0] IR ='h18;
reg[15:0] PC = 0;
wire[7:0] PCH = PC[15:8], PCL = PC[7:0];
reg[7:0] EAL, EAH;
wire[15:0] EA = {EAH, EAL};
reg FLAG_C, FLAG_Z, FLAG_I, FLAG_D, FLAG_B, FLAG_V, FLAG_N;
reg[7:0] AC, X, Y, S = 0;
wire[7:0] P = {FLAG_N, FLAG_V, 1'b1, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C};
wire[7:0] SB;
wire[7:0] ALU_A, ALU_B;
wire[7:0] RES;
wire[2:0] ALU_OP;
reg[8:0] eALU; // with carry
wire[7:0] ALU = eALU;
wire ALU_CF = eALU[8];
wire CF_IN, DF_IN;
wire CF_OUT, VF_OUT;
reg so_prev = 0;
reg nmi_prev = 0;
wire irq_active = ~irq & ~FLAG_I;
wire nmi_active = ~nmi & nmi_prev;
wire int_active = irq_active | nmi_active;
wire rst_active = ~rst;
wire so_active = so & ~so_prev;
wire[1:0] vec_bits=
nmi_active?2'b01:
rst_active?2'b10:
2'b11;
wire[15:0] vec_addr = {{13{1'b1}}, vec_bits, 1'b0};
wire[7:0] IR_eff = int_active?8'b0:IR;
wire[10:0] L = {T, IR_eff};
`include "states.v"
assign read = ~A_RW_W;
assign sync = !T;
assign SB = A_SB_DB? db_in:
A_SB_AC? AC:
A_SB_X? X:
A_SB_Y? Y:
A_SB_S? S:
A_SB_P? P:
A_SB_ALU? ALU:
A_SB_0? 8'b0:
A_SB_PCH? PCH:
A_SB_PCL? PCL:
8'bX;
assign CF_IN = A_ALU_CF_0? 1'b0:
A_ALU_CF_1? 1'b1:
A_ALU_CF_ALUC? ALU_CF:
FLAG_C;
assign DF_IN = A_ALU_DF_D? FLAG_D: 1'b0;
assign ALU_A =
A_ALU_A_AC? AC:
A_ALU_A_X? X:
A_ALU_A_Y? Y:
A_ALU_A_DB? db_in:
A_ALU_A_EAL? EAL:
A_ALU_A_ALU? ALU:
A_ALU_A_S? S:
A_ALU_A_SIGN? (EAL[7]?8'b11111111:8'b00000001):
8'bX;
assign ALU_B = A_ALU_B_SB? SB:
A_ALU_B_NOTSB? ~SB:
8'bX;
 
assign ALU_OP = A_ALU_OP_ADC? `ALU_ADC:
A_ALU_OP_ORA? `ALU_ORA:
A_ALU_OP_EOR? `ALU_EOR:
A_ALU_OP_AND? `ALU_AND:
A_ALU_OP_ASL? `ALU_ASL:
A_ALU_OP_LSR? `ALU_LSR:
A_ALU_OP_ROL? `ALU_ROL:
A_ALU_OP_ROR? `ALU_ROR:
8'bX;
 
ag6502_alu alu(ALU_A, ALU_B, ALU_OP, A_ALU_B_NOTSB, CF_IN, DF_IN, RES, CF_OUT, VF_OUT);
always @(posedge phi_1) begin
if (E_AB__PC) ab <= PC;
else if (E_AB__EA) ab <= EA;
else if (E_AB__S) ab <= {8'b1, S};
 
if (E_DB__SB) db_out <= SB;
else if (E_DB__PCH) db_out <= PCH;
else if (E_DB__PCL) db_out <= PCL;
else if (E_DB__P) db_out <= P;
else if (E_DB__ALU) db_out <= ALU;
if (read) rdyg <= rdy;
end
 
 
wire cond;
assign cond =
E_T__0IFNF__IR_5_?(FLAG_N != IR[5]):
E_T__0IFVF__IR_5_?(FLAG_V != IR[5]):
E_T__0IFCF__IR_5_?(FLAG_C != IR[5]):
E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
E_T__0IFZF__IR_5_?(FLAG_Z != IR[5]):
E_T__0IF_C7F? CF_OUT == EAL[7]:
E_T__0;
always @(negedge phi_2) if (rdyg) begin
if (E_PC__PC_1) PC <= PC + 1;
else if (E_PC__EA) PC <= EA;
else begin
if (E_PCH__RES) PC[15:8] <= RES;
if (E_PCL__ALU) PC[7:0] <= ALU;
else if (E_PCL__RES) PC[7:0] <= RES;
else if (E_PCL__EAL) PC[7:0] <= EAL;
else if (E_PCL__DB) PC[7:0] <= db_in;
end
if (!T) begin
IR <= db_in;
if (!db_in) begin // BRK instruction
{EAH, EAL} <= vec_addr;
end
nmi_prev <= nmi;
end
if (E_N_Z__SB) begin FLAG_Z <= !SB; FLAG_N <= SB[7]; end
else if (E_N_Z__RES) begin FLAG_Z <= !RES; FLAG_N <= RES[7]; end
else if (E_N_Z__SB_RES) begin FLAG_Z <= !RES; FLAG_N <= SB[7]; end
if (E_C__RES) FLAG_C <= CF_OUT;
if (E_V__RES) FLAG_V <= VF_OUT;
else if (E_V__SB_6_) FLAG_V <= SB[6];
if (E_EAL__DB) EAL <= db_in;
else if (E_EAL__ALU) EAL <= ALU;
 
if (E_EA__DB) {EAH, EAL} <= { 8'b0, db_in };
else if (E_EAH__DB) EAH <= db_in;
else if (E_EAH__ALU) EAH <= ALU;
if (E_AC__SB) AC <= SB;
else if (E_AC__RES) AC <= RES;
if (E_S__ALU) S <= ALU;
if (E_X__SB) X <= SB;
else if (E_X__RES) X <= RES;
if (E_Y__SB) Y <= SB;
else if (E_Y__RES) Y <= RES;
if (E_S__SB) S <= SB;
if (E_P__SB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {SB[7], SB[6], SB[4], SB[3], SB[2], SB[1], SB[0]};
else if (E_P__DB) {FLAG_N, FLAG_V, FLAG_B, FLAG_D, FLAG_I, FLAG_Z, FLAG_C} <= {db_in[7], db_in[6], db_in[4], db_in[3], db_in[2], db_in[1], db_in[0]};
if (E_CF__IR_5_) FLAG_C <= IR[5];
if (E_IF__IR_5_) FLAG_I <= IR[5];
if (E_DF__IR_5_) FLAG_D <= IR[5];
if (E_VF__0) FLAG_V <= 0;
else if (so_active) FLAG_V <= 1;
so_prev <= so;
eALU <= {CF_OUT, RES};
if (cond) begin
T <= 0;
if (!IR_eff) begin
FLAG_B <= !IR;
FLAG_I <= 1;
end
end else T <= T + ((E_T__T_1IF_ALUCZ && !ALU_CF)?2: 1);
 
if (rst_active) begin
T <= 1;
IR <= 0;
{EAH, EAL} <= vec_addr;
end
end
 
 
endmodule
 
/ag_6502/trunk/agat7/chip1.v
0,0 → 1,67
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 18:21:00 01/17/2012
// Design Name:
// Project Name: Agat Hardware Project
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
 
 
module chip1(
input clk,
input b1,
input b2,
input rot_a, rot_b, rot_center,
output[7:0] led,
output vga_red,
output vga_green,
output vga_blue,
output vga_hsync,
output vga_vsync,
output [3:0]j4,
input spi_miso, output spi_mosi, output spi_sck, output dac_cs, output dac_clr,
output spi_rom_cs,
output spi_amp_cs,
output spi_adc_conv,
output strataflash_oe,
output strataflash_ce,
output strataflash_we,
output platformflash_oe,
input ps2_clk,
input ps2_data
);
// access to DAC
assign spi_mosi = 0, spi_sck = 0, dac_cs = 0, dac_clr = 0;
// block other devices to access to DAC
assign spi_rom_cs = 1, spi_amp_cs = 1, spi_adc_conv = 0;
assign strataflash_oe = 1, strataflash_ce = 1, strataflash_we = 1;
assign platformflash_oe = 0;
 
wire[4:0] vga_bus;
assign {vga_red, vga_green, vga_blue, vga_hsync, vga_vsync} = vga_bus;
wire[1:0] ps2_bus = {ps2_clk, ps2_data};
// assign j4 = 0, vga_bus = 0;
wire[3:0] btns = {0, 0, b2, b1};
ag_main agate(clk, btns, led, j4, vga_bus, ps2_bus);
endmodule
/ag_6502/trunk/agat7/ag_ram.v
0,0 → 1,231
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Odintsov Oleg
//
// Create Date: 11:15:41 02/24/2012
// Design Name:
// Module Name: ag_ram
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
// Enable the following define to use synchronous memory instead of
// asynchronous (which has been used in real Agats).
// The use of the synchronous memory will improve hardware design on FPGA
`define AG_RAM_SYNCHRONOUS
 
 
`ifdef AG_RAM_SYNCHRONOUS
 
module RAM16Kx1(input CLK1, input[13:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[13:0] AB2, input CS2, output DO2);
 
wire DO1x, DO2x;
assign DO1 = CS1? DO1x: 1'bZ;
assign DO2 = CS2? DO2x: 1'bZ;
// RAMB16_S1_S1: 16k x 1 Dual-Port RAM
// Spartan-3E
// Xilinx HDL Language Template, version 13.3
 
RAMB16_S1_S1 #(
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
.INIT_B(1'b0), // Value of output RAM registers on Port B at startup
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
.SRVAL_B(1'b0), // Port B output value upon SSR assertion
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
 
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 4095
.INIT_00(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_01(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_02(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_03(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_04(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_05(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_06(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_07(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_08(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_09(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_0A(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_0B(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_0C(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_0D(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_0E(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_0F(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
// Address 4096 to 8191
.INIT_10(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_11(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_12(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_13(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_14(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_15(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_16(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_17(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_18(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_19(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_1A(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_1B(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_1C(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_1D(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_1E(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_1F(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
// Address 8192 to 12287
.INIT_20(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_21(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_22(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_23(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_24(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_25(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_26(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_27(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_28(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_29(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_2A(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_2B(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_2C(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_2D(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_2E(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_2F(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
// Address 12288 to 16383
.INIT_30(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_31(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_32(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_33(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_34(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_35(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_36(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_37(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_38(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_39(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_3A(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_3B(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_3C(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_3D(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_3E(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC),
.INIT_3F(256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC)
) RAMB16_S1_S1_inst (
.DOA(DO1x), // Port A 1-bit Data Output
.DOB(DO2x), // Port B 1-bit Data Output
.ADDRA(AB1), // Port A 14-bit Address Input
.ADDRB(AB2), // Port B 14-bit Address Input
.CLKA(CLK1), // Port A Clock
.CLKB(CLK2), // Port B Clock
.DIA(DI1), // Port A 1-bit Data Input
.DIB(1'bZ), // Port B 1-bit Data Input
.ENA(CS1), // Port A RAM Enable Input
.ENB(CS2), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(~READ), // Port A Write Enable Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
 
 
`else
 
module RAM1Kx1(input CLK1, input[9:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[9:0] AB2, input CS2, output DO2);
parameter FILL = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
reg mem[0:'h3FF];
integer i;
 
initial
for (i = 0; i < 'h400; i = i + 1)
mem[i] = (FILL&(256'b01<<(i&'hFF)))?1'b1:1'b0;
 
assign DO1 = (CS1 && READ)? mem[AB1]: 1'bZ;
assign DO2 = CS2? mem[AB2]: 1'bZ;
always @(posedge CLK1) if (CS1 && !READ) mem[AB1] <= DI1;
endmodule
 
 
 
module RAM16Kx1(input CLK1, input[13:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[13:0] AB2, input CS2, output DO2);
wire[3:0] SEL1 = AB1[13:10];
wire[3:0] SEL2 = AB2[13:10];
 
RAM1Kx1 ram0(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h0), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h0), DO2);
RAM1Kx1 ram1(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h1), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h1), DO2);
RAM1Kx1 ram2(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h2), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h2), DO2);
RAM1Kx1 ram3(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h3), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h3), DO2);
RAM1Kx1 ram4(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h4), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h4), DO2);
RAM1Kx1 ram5(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h5), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h5), DO2);
RAM1Kx1 ram6(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h6), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h6), DO2);
RAM1Kx1 ram7(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h7), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h7), DO2);
RAM1Kx1 ram8(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h8), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h8), DO2);
RAM1Kx1 ram9(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h9), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h9), DO2);
RAM1Kx1 ramA(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hA), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hA), DO2);
RAM1Kx1 ramB(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hB), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hB), DO2);
RAM1Kx1 ramC(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hC), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hC), DO2);
RAM1Kx1 ramD(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hD), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hD), DO2);
RAM1Kx1 ramE(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hE), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hE), DO2);
RAM1Kx1 ramF(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hF), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hF), DO2);
endmodule
 
`endif // synchronous
 
 
/*
Data bus for video controller:
A0=0, DO2: A0=1, DO2:
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Data bus for processor:
A0=0, DO1/DI1: A0=1, DO1/DI1:
07 06 05 04 03 02 01 00 07 06 05 04 03 02 01 00
*/
module RAM32Kx8x16(input CLK1, input[14:0] AB1, input CS1,
input READ, output[7:0] DO1, input[7:0] DI1,
input CLK2, input[13:0] AB2, input CS2, output[15:0] DO2);
wire[1:0] CSM = {(~AB1[0]) & CS1, AB1[0] & CS1}; // CS for modules
wire[13:0] AB1x = AB1[14:1];
RAM16Kx1 ram0(CLK1, AB1x, CSM[0], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[0]);
RAM16Kx1 ram1(CLK1, AB1x, CSM[0], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[1]);
RAM16Kx1 ram2(CLK1, AB1x, CSM[0], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[2]);
RAM16Kx1 ram3(CLK1, AB1x, CSM[0], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[3]);
RAM16Kx1 ram4(CLK1, AB1x, CSM[0], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[4]);
RAM16Kx1 ram5(CLK1, AB1x, CSM[0], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[5]);
RAM16Kx1 ram6(CLK1, AB1x, CSM[0], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[6]);
RAM16Kx1 ram7(CLK1, AB1x, CSM[0], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[7]);
RAM16Kx1 ram8(CLK1, AB1x, CSM[1], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[8]);
RAM16Kx1 ram9(CLK1, AB1x, CSM[1], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[9]);
RAM16Kx1 ramA(CLK1, AB1x, CSM[1], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[10]);
RAM16Kx1 ramB(CLK1, AB1x, CSM[1], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[11]);
RAM16Kx1 ramC(CLK1, AB1x, CSM[1], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[12]);
RAM16Kx1 ramD(CLK1, AB1x, CSM[1], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[13]);
RAM16Kx1 ramE(CLK1, AB1x, CSM[1], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[14]);
RAM16Kx1 ramF(CLK1, AB1x, CSM[1], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[15]);
endmodule
/ag_6502/trunk/agat7/agat7.xise
0,0 → 1,374
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="chip1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="chip1.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="videoctl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ag_main.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="ag_6502.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="clkdiv.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ag_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ag_video.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ag_keyb.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="states.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="monitor7.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="agathe7.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
 
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Port" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="test1.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3E Starter Board" xil_pn:valueState="non-default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|chip1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="chip1.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/chip1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instance Name for Simulation in Hardware" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="-loop_iteration_limit 16384" xil_pn:valueState="non-default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="chip1" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="chip1_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="chip1_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="chip1_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="chip1_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Re-Use Last Bitstream File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/chip1/agate/cpu/alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ag6502_alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ag6502_alu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Board for Hardware Co-Simulation" xil_pn:value="Spartan-3E MicroBlaze Development Kit (JTAG)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="chip1.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="D:/Xilinx/13.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="auto_project.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|ag6502_alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="test2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-17T18:20:35" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9CB31622BFF04E63BD87FD9353EBD727" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings>
<binding xil_pn:location="/chip1" xil_pn:name="chip1.ucf"/>
</bindings>
 
<libraries/>
 
</project>
/ag_6502/trunk/agat7/videoctl.v
0,0 → 1,68
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 20:41:53 01/18/2012
// Design Name:
// Module Name: videoctl
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module video_counters(
input clk,
output reg video_vsync = 1,
output reg video_hsync = 1,
output video_on,
output reg [10:1] hpos = 0,
output reg [9:1] vpos = 0);
integer hcnt = 0, vcnt = 0;
 
reg video_von = 0, video_hon = 0;
assign video_on = video_von & video_hon;
always @(posedge video_hsync) begin
vcnt <= vcnt + 1;
vpos <= video_von?vpos + 1: 0;
case (vcnt)
2: video_vsync = 1;
31: video_von = 1;
511: video_von = 0;
521: begin vcnt <=0; video_vsync = 0; end
endcase
end
 
always @(posedge clk) begin
if (!video_hon) hcnt <= hcnt - 1;
else hpos <= hpos + 1;
if (hpos == 639) video_hon <= 0;
if (hpos == 640) begin
if (!hcnt) begin
hcnt <= 96;
video_hsync <= 0;
hpos <= 0;
end
end else if (!hcnt) begin
if (!video_hsync) begin
video_hsync <= 1;
hcnt <= 48;
end else if (!video_hon) begin
video_hon <= 1;
hcnt <= 16;
end
end
end
endmodule
/ag_6502/trunk/genstates/states.txt
0,0 → 1,2032
% Common blocks
 
@READ_AT_PC:
(:1 AB <= PC
 
 
@SELECT_EA:
(:1 AB <= EA
@SELECT_S:
(:1 AB <= S
 
@READ_AT_EA:
(:1 @SELECT_EA
 
@INC_PC:
(:2 PC <= PC + 1
 
@FETCH:
(0:1 @READ_AT_PC
(0:2 @INC_PC
 
@ENDC:
(:2 T <= 0
 
@UNDOC:
@ENDC
 
@LOADNZ_SB:
(:2 N,Z <= SB
 
@LOADNZ_RES:
(:2 N,Z <= RES
 
@LOADNZ_SB_RES:
(:2 N,Z <= SB,RES
 
@LOADC_RES:
(:2 C <= RES
 
@LOADV_RES:
(:2 V <= RES
 
@LOADV_SB6:
(:2 V <= SB[6]
 
@ADD:
ALU_CF = 0
ALU_DF = 0
ALU_OP = ADC
 
@INC:
SB = 0
ALU_B = SB
ALU_CF = 1
ALU_DF = 0
ALU_OP = ADC
 
@INC_C:
SB = 0
ALU_B = SB
ALU_CF = ALUC
ALU_DF = 0
ALU_OP = ADC
 
@DEC:
SB = 0
ALU_B = NOT SB
ALU_CF = 0
ALU_DF = 0
ALU_OP = ADC
 
@COPY_ALU:
SB = 0
ALU_B = SB
ALU_OP = ORA
 
@ADD_DB_X:
ALU_A = DB
SB = X
ALU_B = SB
@ADD
 
@ADD_EAL_PCL:
ALU_A = EAL
SB = PCL
ALU_B = SB
@ADD
 
@COPY_DB:
ALU_A = DB
@COPY_ALU
 
@ADD_DB_Y:
ALU_A = DB
SB = Y
ALU_B = SB
@ADD
 
@INC_DB_C:
ALU_A = DB
@INC_C
 
@INC_DB:
ALU_A = DB
@INC
 
@INC_EAL:
ALU_A = EAL
@INC
 
@INC_ALU:
ALU_A = ALU
@INC
 
@DEC_ALU:
ALU_A = ALU
@DEC
 
@INC_S:
ALU_A = S
@INC
 
@DEC_S:
ALU_A = S
@DEC
 
@CF_OPERATE:
(1:1 @READ_AT_PC
(2:2 CF <= IR[5]
@ENDC
 
@IF_OPERATE:
(1:1 @READ_AT_PC
(2:2 IF <= IR[5]
@ENDC
 
@DF_OPERATE:
(1:1 @READ_AT_PC
(2:2 DF <= IR[5]
@ENDC
 
@VF_CLEAR:
(1:1 @READ_AT_PC
(2:2 VF <= 0
@ENDC
 
@NF_TEST:
T <= 0 IF NF != IR[5]
 
@VF_TEST:
T <= 0 IF VF != IR[5]
 
@CF_TEST:
T <= 0 IF CF != IR[5]
 
@ZF_TEST:
T <= 0 IF ZF == IR[5]
 
% Addressing modes
 
@IMM:
(1:1 @READ_AT_PC
(1:2 @INC_PC
 
@ZP:
(1:1 @READ_AT_PC
(1:2 EA <= DB
@INC_PC
(2:1 @SELECT_EA
 
@REL_READ:
(1:1 @READ_AT_PC
(1:2 @INC_PC
EAL <= DB
 
@REL_JUMP:
(2:1 @READ_AT_PC
@ADD_EAL_PCL
(2:2 PCL <= RES
T <= 0 IF_C7F
(3:1 @READ_AT_PC
ALU_A = SIGN
SB = PCH
ALU_B = SB
@ADD
(3:2 PCH <= RES
@ENDC
 
 
@ABS:
(1:1 @READ_AT_PC
(1:2 EAL <= DB
@INC_PC
(2:1 @READ_AT_PC
(2:2 EAH <= DB
@INC_PC
(3:1 @SELECT_EA
 
 
 
@INDX:
(1:1 @READ_AT_PC
@ADD_DB_X
(1:2 EA <= DB
@INC_PC
(2:1 @READ_AT_EA
@INC_ALU
(2:2 EAL <= ALU
(3:1 @READ_AT_EA
@COPY_DB
(3:2 EAL <= ALU
(4:1 @READ_AT_EA
(4:2 EAH <= DB
EAL <= ALU
(5:1 @SELECT_EA
 
@ABSX_READ:
(1:1 @READ_AT_PC
@ADD_DB_X
(1:2 EAL <= DB
@INC_PC
(2:1 @READ_AT_PC
@INC_DB_C
(2:2 EAH <= DB
EAL <= ALU
@INC_PC
T <= T + 1 IF_ALUCZ
(3:1 @READ_AT_EA
(3:2 EAH <= ALU
(4:1 @SELECT_EA
 
 
@ABSY_READ:
(1:1 @READ_AT_PC
@ADD_DB_Y
(1:2 EAL <= DB
@INC_PC
(2:1 @READ_AT_PC
@INC_DB_C
(2:2 EAH <= DB
EAL <= ALU
@INC_PC
T <= T + 1 IF_ALUCZ
(3:1 @READ_AT_EA
(3:2 EAH <= ALU
(4:1 @SELECT_EA
 
 
@ABSX_WRITE:
(1:1 @READ_AT_PC
@ADD_DB_X
(1:2 EAL <= DB
@INC_PC
(2:1 @READ_AT_PC
@INC_DB_C
(2:2 EAH <= DB
EAL <= ALU
@INC_PC
(3:1 @READ_AT_EA
(3:2 EAH <= ALU
(4:1 @SELECT_EA
 
 
@ABSY_WRITE:
(1:1 @READ_AT_PC
@ADD_DB_Y
(1:2 EAL <= DB
@INC_PC
(2:1 @READ_AT_PC
@INC_DB_C
(2:2 EAH <= DB
EAL <= ALU
@INC_PC
(3:1 @READ_AT_EA
(3:2 EAH <= ALU
(4:1 @SELECT_EA
 
 
@ZPX:
(1:1 @READ_AT_PC
@ADD_DB_X
(1:2 EA <= DB
@INC_PC
(2:1 @READ_AT_EA
(2:2 EAL <= ALU
(3:1 @SELECT_EA
 
@ZPY:
(1:1 @READ_AT_PC
@ADD_DB_Y
(1:2 EA <= DB
@INC_PC
(2:1 @READ_AT_EA
(2:2 EAL <= ALU
(3:1 @SELECT_EA
 
 
 
@INDY_READ:
(1:1 @READ_AT_PC
@INC_DB
(1:2 EA <= DB
@INC_PC
(2:1 @READ_AT_EA
@ADD_DB_Y
(2:2 EAL <= ALU
(3:1 @READ_AT_EA
@INC_DB_C
(3:2 EAH <= DB
EAL <= ALU
T <= T + 1 IF_ALUCZ
(4:1 @READ_AT_EA
(4:2 EAH <= ALU
(5:1 @SELECT_EA
 
 
 
@INDY_WRITE:
(1:1 @READ_AT_PC
@INC_DB
(1:2 EA <= DB
@INC_PC
(2:1 @READ_AT_EA
@ADD_DB_Y
(2:2 EAL <= ALU
(3:1 @READ_AT_EA
@INC_DB_C
(3:2 EAH <= DB
EAL <= ALU
(4:1 @READ_AT_EA
(4:2 EAH <= ALU
(5:1 @SELECT_EA
 
@IND_JMP:
(1:1 @READ_AT_PC
(1:2 EAL <= DB
@INC_PC
(2:1 @READ_AT_PC
@INC_EAL
(2:2 EAH <= DB
(3:1 @READ_AT_EA
@COPY_DB
(3:2 EAL <= ALU
(4:1 @READ_AT_EA
@COPY_DB
(4:2 PCH <= RES
PCL <= ALU
@ENDC
 
% Operations
 
@LDA:
(:1 SB = DB
(:2 AC <= SB
@LOADNZ_SB
@ENDC
 
@ORA:
(:1 SB = DB
ALU_A = AC
ALU_B = SB
ALU_OP = ORA
(:2 AC <= RES
@LOADNZ_RES
@ENDC
 
@AND:
(:1 SB = DB
ALU_A = AC
ALU_B = SB
ALU_OP = AND
(:2 AC <= RES
@LOADNZ_RES
@ENDC
 
@EOR:
(:1 SB = DB
ALU_A = AC
ALU_B = SB
ALU_OP = EOR
(:2 AC <= RES
@LOADNZ_RES
@ENDC
 
@CMP:
(:1 SB = DB
ALU_A = AC
ALU_B = NOT SB
ALU_DF = 0
ALU_CF = 1
ALU_OP = ADC
(:2 @LOADNZ_RES
@LOADC_RES
@ENDC
 
@BIT:
(:1 SB = DB
ALU_A = AC
ALU_B = SB
ALU_OP = AND
(:2 @LOADNZ_SB_RES
@LOADV_SB6
@ENDC
 
@CPX:
(:1 SB = DB
ALU_A = X
ALU_B = NOT SB
ALU_DF = 0
ALU_CF = 1
ALU_OP = ADC
(:2 @LOADNZ_RES
@LOADC_RES
@ENDC
 
@CPY:
(:1 SB = DB
ALU_A = Y
ALU_B = NOT SB
ALU_DF = 0
ALU_CF = 1
ALU_OP = ADC
(:2 @LOADNZ_RES
@LOADC_RES
@ENDC
 
@ADC:
(:1 SB = DB
ALU_A = AC
ALU_B = SB
ALU_DF = D
ALU_CF = C
ALU_OP = ADC
(:2 AC <= RES
@LOADNZ_RES
@LOADC_RES
@LOADV_RES
@ENDC
 
@SBC:
(:1 SB = DB
ALU_A = AC
ALU_B = NOT SB
ALU_DF = D
ALU_CF = C
ALU_OP = ADC
(:2 AC <= RES
@LOADNZ_RES
@LOADC_RES
@LOADV_RES
@ENDC
 
@ASL_A:
(1:1 ALU_A = AC
ALU_CF = C
ALU_OP = ASL
(:2 AC <= RES
@LOADNZ_RES
@LOADC_RES
@ENDC
 
@ASL_M:
(:1 @COPY_DB
(+:1 RW = W
SB = ALU
DB <= SB
ALU_A = ALU
ALU_CF = C
ALU_OP = ASL
(:2 @LOADNZ_RES
@LOADC_RES
(+:1 RW = W
SB = ALU
DB <= SB
(:2 @ENDC
 
@LSR_A:
(1:1 ALU_A = AC
ALU_CF = C
ALU_OP = LSR
(:2 AC <= RES
@LOADNZ_RES
@LOADC_RES
@ENDC
 
@LSR_M:
(:1 @COPY_DB
(+:1 RW = W
SB = ALU
DB <= SB
ALU_A = ALU
ALU_CF = C
ALU_OP = LSR
(:2 @LOADNZ_RES
@LOADC_RES
(+:1 RW = W
SB = ALU
DB <= SB
(:2 @ENDC
 
@ROL_A:
(1:1 ALU_A = AC
ALU_CF = C
ALU_OP = ROL
(:2 AC <= RES
@LOADNZ_RES
@LOADC_RES
@ENDC
 
@ROL_M:
(:1 @COPY_DB
(+:1 RW = W
SB = ALU
DB <= SB
ALU_A = ALU
ALU_CF = C
ALU_OP = ROL
(:2 @LOADNZ_RES
@LOADC_RES
(+:1 RW = W
SB = ALU
DB <= SB
(:2 @ENDC
 
@ROR_A:
(1:1 ALU_A = AC
ALU_CF = C
ALU_OP = ROR
(:2 AC <= RES
@LOADNZ_RES
@LOADC_RES
@ENDC
 
@ROR_M:
(:1 @COPY_DB
(+:1 RW = W
SB = ALU
DB <= SB
ALU_A = ALU
ALU_CF = C
ALU_OP = ROR
(:2 @LOADNZ_RES
@LOADC_RES
(+:1 RW = W
SB = ALU
DB <= SB
(:2 @ENDC
 
@STA:
(:1 RW = W
SB = AC
DB <= SB
(:2 @ENDC
 
@LDX:
(:1 SB = DB
(:2 X <= SB
@LOADNZ_SB
@ENDC
@STX:
(:1 RW = W
SB = X
DB <= SB
(:2 @ENDC
 
@LDY:
(:1 SB = DB
(:2 Y <= SB
@LOADNZ_SB
@ENDC
@STY:
(:1 RW = W
SB = Y
DB <= SB
(:2 @ENDC
 
 
@TAY:
(:1 SB = AC
(:2 Y <= SB
@LOADNZ_SB
@ENDC
 
@TYA:
(:1 SB = Y
(:2 AC <= SB
@LOADNZ_SB
@ENDC
 
@TAX:
(:1 SB = AC
(:2 X <= SB
@LOADNZ_SB
@ENDC
 
@TXA:
(:1 SB = X
(:2 AC <= SB
@LOADNZ_SB
@ENDC
 
@NOP:
(:2 @ENDC
 
@TSX:
(:1 SB = S
(:2 X <= SB
@LOADNZ_SB
@ENDC
 
@TXS:
(:1 SB = X
(:2 S <= SB
@ENDC
 
@JMP:
(:2 PC <= EA
@ENDC
 
@PUSH:
(1:1 @READ_AT_PC
@DEC_S
(2:1 @SELECT_S
DB <= SB
RW = W
(2:2 S <= ALU
 
@PULL:
(1:1 @READ_AT_PC
@INC_S
(2:1 @SELECT_S
(2:2 S <= ALU
(3:1 @SELECT_S
SB = DB
 
@PHA:
(1:1 @PUSH
(:1 SB = AC
@ENDC
 
@PHP:
(1:1 @PUSH
(:1 SB = P
@ENDC
 
@PLA:
(:1 @PULL
(:2 AC <= SB
@LOADNZ_SB
@ENDC
 
@PLP:
(:1 @PULL
(:2 P <= SB
@ENDC
 
@INX:
(:1 ALU_A = X
@INC
(:2 X <= RES
@LOADNZ_RES
@ENDC
 
@INY:
(:1 ALU_A = Y
@INC
(:2 Y <= RES
@LOADNZ_RES
@ENDC
 
@DEX:
(:1 ALU_A = X
@DEC
(:2 X <= RES
@LOADNZ_RES
@ENDC
 
@DEY:
(:1 ALU_A = Y
@DEC
(:2 Y <= RES
@LOADNZ_RES
@ENDC
 
 
@INC_M:
(:1 @COPY_DB
(+:1 RW = W
DB <= ALU
@INC_ALU
(:2 @LOADNZ_RES
(+:1 RW = W
DB <= ALU
(:2 @ENDC
 
@DEC_M:
(:1 @COPY_DB
(+:1 RW = W
DB <= ALU
@DEC_ALU
(:2 @LOADNZ_RES
(+:1 RW = W
DB <= ALU
(:2 @ENDC
 
@JSR_ABS:
(1:1 @READ_AT_PC
(1:2 EAL <= DB
@INC_PC
(2:1 @SELECT_S
@DEC_S
(3:1 @SELECT_S
RW = W
DB <= PCH
ALU_A = ALU
@DEC
(3:2 S <= ALU
(4:1 @SELECT_S
RW = W
SB = PCL
DB <= SB
(4:2 S <= ALU
(5:1 @READ_AT_PC
@COPY_DB
(5:2 PCH <= RES
PCL <= EAL
@ENDC
 
@BRK:
(1:1 @READ_AT_PC
@DEC_S
(2:1 @SELECT_S
ALU_A = ALU
@DEC
RW = W
DB <= PCH
(2:2 S <= ALU
(3:1 @SELECT_S
ALU_A = ALU
@DEC
RW = W
DB <= PCL
(3:2 S <= ALU
(4:1 @SELECT_S
RW = W
DB <= P
@INC_EAL
(4:2 S <= ALU
(5:1 @READ_AT_EA
@COPY_DB
(5:2 EAL <= ALU
(6:1 @READ_AT_EA
@COPY_DB
(6:2 PCH <= RES
PCL <= ALU
@ENDC
 
 
@RTS:
(1:1 @READ_AT_PC
@INC_S
(2:1 @SELECT_S
ALU_A = ALU
@INC
(2:2 S <= ALU
(3:1 @SELECT_S
@COPY_DB
(3:2 S <= ALU
PCL <= RES
(4:1 @SELECT_S
@COPY_DB
(4:2 PCH <= RES
(5:1 @READ_AT_PC
(5:2 @INC_PC
@ENDC
 
@RTI:
(1:1 @READ_AT_PC
@INC_S
(2:1 @SELECT_S
ALU_A = ALU
@INC
(2:2 S <= ALU
(3:1 @SELECT_S
ALU_A = ALU
@INC
(3:2 S <= ALU
P <= DB
(4:1 @SELECT_S
ALU_A = ALU
@INC
(4:2 PCL <= DB
S <= ALU
(5:1 @SELECT_S
@COPY_DB
(5:2 PCH <= RES
@ENDC
 
% Extra operations (incomplete)
 
@LAX:
(:1 SB = DB
(:2 AC <= SB
X <= SB
@LOADNZ_SB
@ENDC
 
 
% Real commands
 
#00: % BRK
(0: @FETCH
(1: @BRK
 
#01: % ORA (IND,X)
(0: @FETCH
(1: @INDX
@ORA
 
#03: % *SLO (IND,X) - incomplete
(0: @FETCH
(1: @INDX
@UNDOC
 
#04: % *NOP ZP
(0: @FETCH
(1: @ZP
@NOP
 
#05: % ORA ZP
(0: @FETCH
(1: @ZP
@ORA
 
#06: % ASL ZP
(0: @FETCH
(1: @ZP
@ASL_M
 
#07: % *SLO ZP - incomplete
(0: @FETCH
(1: @ZP
@UNDOC
 
 
#08: % PHP
(0: @FETCH
@PHP
 
#09: % ORA #IMM
(0: @FETCH
(1: @IMM
@ORA
 
#0A: % ASL A
(0: @FETCH
@ASL_A
 
#0B: % *ANC #IMM - incomplete
(0: @FETCH
(1: @IMM
@UNDOC
 
#0C: % *NOP ABS
(0: @FETCH
(1: @ABS
@NOP
 
#0D: % ORA ABS
(0: @FETCH
(1: @ABS
@ORA
 
#0E: % ASL ABS
(0: @FETCH
(1: @ABS
@ASL_M
 
#0F: % *SLO ABS - incomplete
(0: @FETCH
(1: @ABS
@UNDOC
 
#10: % BPL REL
(0: @FETCH
(1: @REL_READ
@NF_TEST
@REL_JUMP
 
#11: % ORA (IND),Y
(0: @FETCH
(1: @INDY_READ
@ORA
 
#13: % *SLO (IND),Y - incomplete
(0: @FETCH
(1: @INDY_WRITE
@UNDOC
 
#14: % *NOP ZP,X
(0: @FETCH
(1: @ZPX
@NOP
 
#15: % ORA ZP,X
(0: @FETCH
(1: @ZPX
@ORA
 
#16: % ASL ZP,X
(0: @FETCH
(1: @ZPX
@ASL_M
 
#17: % *SLO ZP,X - incomplete
(0: @FETCH
(1: @ZPX
@UNDOC
 
#18: % CLC
(0: @FETCH
@CF_OPERATE
 
 
#19: % ORA ABS,Y
(0: @FETCH
(1: @ABSY_READ
@ORA
 
#1A: % *NOP
(0: @FETCH
(1: @NOP
 
#1B: % *SLO ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_WRITE
@UNDOC
 
 
#1C: % *NOP ABS,X
(0: @FETCH
(1: @ABSX_READ
@NOP
 
#1D: % ORA ABS,X
(0: @FETCH
(1: @ABSX_READ
@ORA
 
 
#1E: % ASL ABS,X
(0: @FETCH
(1: @ABSX_WRITE
@ASL_M
 
#1F: % *SLO ABS,X - incomplete
(0: @FETCH
(1: @ABSX_WRITE
@UNDOC
 
#20: % JSR ABS
(0: @FETCH
(1: @JSR_ABS
 
#21: % AND (IND,X)
(0: @FETCH
(1: @INDX
@AND
 
#23: % *RLA (IND,X) - incomplete
(0: @FETCH
(1: @INDX
@UNDOC
 
#24: % BIT ZP
(0: @FETCH
(1: @ZP
@BIT
 
#25: % AND ZP
(0: @FETCH
(1: @ZP
@AND
 
#26: % ROL ZP
(0: @FETCH
(1: @ZP
@ROL_M
 
#27: % *RLA ZP - incomplete
(0: @FETCH
(1: @ZP
@UNDOC
 
 
#28: % PLP
(0: @FETCH
(1: @PLP
 
 
#29: % AND #IMM
(0: @FETCH
(1: @IMM
@AND
 
#2A: % ROL A
(0: @FETCH
@ROL_A
 
#2B: % *ANC #IMM - incomplete
(0: @FETCH
(1: @IMM
@UNDOC
 
#2C: % BIT ABS
(0: @FETCH
(1: @ABS
@BIT
 
#2D: % AND ABS
(0: @FETCH
(1: @ABS
@AND
 
#2E: % ROL ABS
(0: @FETCH
(1: @ABS
@ROL_M
 
#2F: % *RLA ABS - incomplete
(0: @FETCH
(1: @ABS
@UNDOC
 
#30: % BMI REL
(0: @FETCH
(1: @REL_READ
@NF_TEST
@REL_JUMP
 
#31: % AND (IND),Y
(0: @FETCH
(1: @INDY_READ
@AND
 
#33: % *RLA (IND),Y - incomplete
(0: @FETCH
(1: @INDY_WRITE
@UNDOC
 
 
#34: % *NOP ZP,X
(0: @FETCH
(1: @ZPX
@NOP
 
#35: % AND ZP,X
(0: @FETCH
(1: @ZPX
@AND
 
#36: % ROL ZP,X
(0: @FETCH
(1: @ZPX
@ROL_M
 
#37: % *RLA ZP,X - incomplete
(0: @FETCH
(1: @ZPX
@UNDOC
 
#38: % SEC
(0: @FETCH
@CF_OPERATE
 
#39: % AND ABS,Y
(0: @FETCH
(1: @ABSY_READ
@AND
 
#3A: % *NOP
(0: @FETCH
(1: @NOP
 
#3B: % *RLA ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_WRITE
@UNDOC
 
#3C: % *NOP ABS,X
(0: @FETCH
(1: @ABSX_READ
@NOP
 
#3D: % AND ABS,X
(0: @FETCH
(1: @ABSX_READ
@AND
 
#3E: % ROL ABS,X
(0: @FETCH
(1: @ABSX_WRITE
@ROL_M
 
#3F: % *RLA ABS,X - incomplete
(0: @FETCH
(1: @ABSX_WRITE
@UNDOC
 
 
#40: % RTI
(0: @FETCH
(1: @RTI
 
#41: % EOR (IND,X)
(0: @FETCH
(1: @INDX
@EOR
 
#43: % *SRE (IND,X) - incomplete
(0: @FETCH
(1: @INDX
@UNDOC
 
#44: % *NOP ZP
(0: @FETCH
(1: @ZP
@NOP
 
#45: % EOR ZP
(0: @FETCH
(1: @ZP
@EOR
 
#46: % LSR ZP
(0: @FETCH
(1: @ZP
@LSR_M
 
#47: % *SRE ZP - incomplete
(0: @FETCH
(1: @ZP
@UNDOC
 
#48: % PHA
(0: @FETCH
(1: @PHA
 
 
#49: % EOR #IMM
(0: @FETCH
(1: @IMM
@EOR
 
#4A: % LSR A
(0: @FETCH
@LSR_A
 
#4B: % *ALR #IMM - incomplete
(0: @FETCH
(1: @IMM
@UNDOC
 
#4C: % JMP ABS
(0: @FETCH
(1: @ABS
@JMP
 
#4D: % EOR ABS
(0: @FETCH
(1: @ABS
@EOR
 
#4E: % LSR ABS
(0: @FETCH
(1: @ABS
@LSR_M
 
#4F: % *SRE ABS - incomplete
(0: @FETCH
(1: @ABS
@UNDOC
 
#50: % BVC REL
(0: @FETCH
(1: @REL_READ
@VF_TEST
@REL_JUMP
 
#51: % EOR (IND),Y
(0: @FETCH
(1: @INDY_READ
@EOR
 
#53: % *SRE (IND),Y - incomplete
(0: @FETCH
(1: @INDY_WRITE
@UNDOC
 
#54: % *NOP ZP,X
(0: @FETCH
(1: @ZPX
@NOP
 
#55: % EOR ZP,X
(0: @FETCH
(1: @ZPX
@EOR
 
#56: % LSR ZP,X
(0: @FETCH
(1: @ZPX
@LSR_M
 
#57: % *SRE ZP,X - incomplete
(0: @FETCH
(1: @ZPX
@UNDOC
 
#58: % CLI
(0: @FETCH
@IF_OPERATE
 
#59: % EOR ABS,Y
(0: @FETCH
(1: @ABSY_READ
@EOR
 
#5A: % *NOP
(0: @FETCH
(1: @NOP
 
#5B: % *SRE ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_WRITE
@UNDOC
 
#5C: % *NOP ABS,X
(0: @FETCH
(1: @ABSX_READ
@NOP
 
#5D: % EOR ABS,X
(0: @FETCH
(1: @ABSX_READ
@EOR
 
#5E: % LSR ABS,X
(0: @FETCH
(1: @ABSX_WRITE
@LSR_M
 
#5F: % *SRE ABS,X - incomplete
(0: @FETCH
(1: @ABSX_WRITE
@UNDOC
 
 
 
#60: % RTS
(0: @FETCH
(1: @RTS
 
#61: % ADC (IND,X)
(0: @FETCH
(1: @INDX
@ADC
 
#63: % *RRA (IND,X) - incomplete
(0: @FETCH
(1: @INDX
@UNDOC
 
#64: % *NOP ZP
(0: @FETCH
(1: @ZP
@NOP
 
#65: % ADC ZP
(0: @FETCH
(1: @ZP
@ADC
 
#66: % ROR ZP
(0: @FETCH
(1: @ZP
@ROR_M
 
#67: % *RRA ZP - incomplete
(0: @FETCH
(1: @ZP
@UNDOC
 
#68: % PLA
(0: @FETCH
(1: @PLA
 
 
#69: % ADC #IMM
(0: @FETCH
(1: @IMM
@ADC
 
#6A: % ROR A
(0: @FETCH
@ROR_A
 
#6B: % *ARR #IMM - incomplete
(0: @FETCH
(1: @IMM
@UNDOC
 
#6C: % JMP (IND)
(0: @FETCH
(1: @IND_JMP
 
#6D: % ADC ABS
(0: @FETCH
(1: @ABS
@ADC
 
#6E: % ROR ABS
(0: @FETCH
(1: @ABS
@ROR_M
 
#6F: % *RRA ABS - uncomplete
(0: @FETCH
(1: @ABS
@UNDOC
 
#70: % BVS REL
(0: @FETCH
(1: @REL_READ
@VF_TEST
@REL_JUMP
 
#71: % ADC (IND),Y
(0: @FETCH
(1: @INDY_READ
@ADC
 
#73: % *RRA (IND),Y - incomplete
(0: @FETCH
(1: @INDY_WRITE
@UNDOC
 
#74: % *NOP ZP,X
(0: @FETCH
(1: @ZPX
@NOP
 
#75: % ADC ZP,X
(0: @FETCH
(1: @ZPX
@ADC
 
#76: % ROR ZP,X
(0: @FETCH
(1: @ZPX
@ROR_M
 
#77: % *RRA ZP,X - incomplete
(0: @FETCH
(1: @ZPX
@UNDOC
 
#78: % SEI
(0: @FETCH
@IF_OPERATE
 
 
#79: % ADC ABS,Y
(0: @FETCH
(1: @ABSY_READ
@ADC
 
#7A: % *NOP
(0: @FETCH
(1: @NOP
 
#7B: % *RRA ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_WRITE
@UNDOC
 
#7C: % *NOP ABS,X
(0: @FETCH
(1: @ABSX_READ
@NOP
 
#7D: % ADC ABS,X
(0: @FETCH
(1: @ABSX_READ
@ADC
 
#7E: % ROR ABS,X
(0: @FETCH
(1: @ABSX_WRITE
@ROR_M
 
#7F: % *RRA ABS,X - incomplete
(0: @FETCH
(1: @ABSX_WRITE
@UNDOC
 
 
#80: % *NOP #IMM
(0: @FETCH
(1: @IMM
@NOP
 
#81: % STA (IND,X)
(0: @FETCH
(1: @INDX
@STA
 
#82: % *NOP #IMM
(0: @FETCH
(1: @IMM
@NOP
 
#83: % *SAX (IND,X) - incomplete
(0: @FETCH
(1: @INDX
@UNDOC
 
#84: % STY ZP
(0: @FETCH
(1: @ZP
@STY
 
#85: % STA ZP
(0: @FETCH
(1: @ZP
@STA
 
#86: % STX ZP
(0: @FETCH
(1: @ZP
@STX
 
#87: % *SAX ZP - incomplete
(0: @FETCH
(1: @ZP
@UNDOC
 
#88: % DEY
(0: @FETCH
(1: @DEY
 
 
#89: % *NOP #IMM
(0: @FETCH
(1: @IMM
@NOP
 
#8A: % TXA
(0: @FETCH
(1: @TXA
 
#8B: % *XAA - incomplete
(0: @FETCH
(1: @UNDOC
 
#8C: % STY ABS
(0: @FETCH
(1: @ABS
@STY
 
#8D: % STA ABS
(0: @FETCH
(1: @ABS
@STA
 
#8E: % STX ABS
(0: @FETCH
(1: @ABS
@STX
 
#8F: % *SAX ABS - incomplete
(0: @FETCH
(1: @ABS
@UNDOC
 
#90: % BCC REL
(0: @FETCH
(1: @REL_READ
@CF_TEST
@REL_JUMP
 
#91: % STA (IND),Y
(0: @FETCH
(1: @INDY_WRITE
@STA
 
#93: % *SAX (IND),Y - incomplete
(0: @FETCH
(1: @INDY_WRITE
@UNDOC
 
#94: % STY ZP,X
(0: @FETCH
(1: @ZPX
@STY
 
#95: % STA ZP,X
(0: @FETCH
(1: @ZPX
@STA
 
#96: % STX ZP,Y
(0: @FETCH
(1: @ZPY
@STX
 
#97: % *SAX ZP,Y - incomplete
(0: @FETCH
(1: @ZPY
@UNDOC
 
#98: % TYA
(0: @FETCH
(1: @TYA
 
 
#99: % STA ABS,Y
(0: @FETCH
(1: @ABSY_WRITE
@STA
 
#9A: % TXS
(0: @FETCH
(1: @TXS
 
#9B: % *TAS ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_WRITE
@UNDOC
 
#9C: % *SHY ABS,X - incomplete
(0: @FETCH
(1: @ABSX_WRITE
@UNDOC
 
#9D: % STA ABS,X
(0: @FETCH
(1: @ABSX_WRITE
@STA
 
#9E: % *SHX ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_WRITE
@UNDOC
 
#9F: % *AHX ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_WRITE
@UNDOC
 
 
#A0: % LDY #IMM
(0: @FETCH
(1: @IMM
@LDY
 
#A1: % LDA (IND,X)
(0: @FETCH
(1: @INDX
@LDA
 
#A2: % LDX #IMM
(0: @FETCH
(1: @IMM
@LDX
 
#A3: % *LAX (IND,X)
(0: @FETCH
(1: @INDX
@LAX
 
#A4: % LDY ZP
(0: @FETCH
(1: @ZP
@LDY
 
#A5: % LDA ZP
(0: @FETCH
(1: @ZP
@LDA
 
#A6: % LDX ZP
(0: @FETCH
(1: @ZP
@LDX
 
#A7: % *LAX ZP
(0: @FETCH
(1: @ZP
@LAX
 
#A8: % TAY
(0: @FETCH
(1: @TAY
 
#A9: % LDA #IMM
(0: @FETCH
(1: @IMM
@LDA
 
#AA: % TAX
(0: @FETCH
(1: @TAX
 
#AB: % *LAX #IMM
(0: @FETCH
(1: @IMM
@LAX
 
 
 
#AC: % LDY ABS
(0: @FETCH
(1: @ABS
@LDY
 
#AD: % LDA ABS
(0: @FETCH
(1: @ABS
@LDA
 
#AE: % LDX ABS
(0: @FETCH
(1: @ABS
@LDX
 
#AF: % *LAX ABS
(0: @FETCH
(1: @ABS
@LAX
 
#B0: % BCS REL
(0: @FETCH
(1: @REL_READ
@CF_TEST
@REL_JUMP
 
 
#B1: % LDA (IND),Y
(0: @FETCH
(1: @INDY_READ
@LDA
 
#B3: % *LAX (IND),Y
(0: @FETCH
(1: @INDY_READ
@LAX
 
#B4: % LDY ZP,X
(0: @FETCH
(1: @ZPX
@LDY
 
#B5: % LDA ZP,X
(0: @FETCH
(1: @ZPX
@LDA
 
#B6: % LDX ZP,Y
(0: @FETCH
(1: @ZPY
@LDX
 
#B7: % *LAX ZP,Y
(0: @FETCH
(1: @ZPY
@LAX
 
#B8: % CLV
(0: @FETCH
@VF_CLEAR
 
#B9: % LDA ABS,Y
(0: @FETCH
(1: @ABSY_READ
@LDA
 
#BA: % TSX
(0: @FETCH
(1: @TSX
 
 
#BB: % *LAS ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_READ
@UNDOC
 
#BC: % LDY ABS,X
(0: @FETCH
(1: @ABSX_READ
@LDY
 
#BD: % LDA ABS,X
(0: @FETCH
(1: @ABSX_READ
@LDA
 
#BE: % LDX ABS,Y
(0: @FETCH
(1: @ABSY_READ
@LDX
 
#BF: % *LAX ABS,Y
(0: @FETCH
(1: @ABSY_READ
@LAX
 
 
 
 
#C0: % CPY #IMM
(0: @FETCH
(1: @IMM
@CPY
 
#C1: % CMP (IND,X)
(0: @FETCH
(1: @INDX
@CMP
 
#C2: % *NOP #IMM
(0: @FETCH
(1: @IMM
@NOP
 
#C3: % *DCP (IND,X) - incomplete
(0: @FETCH
(1: @INDX
@UNDOC
 
#C4: % CPY ZP
(0: @FETCH
(1: @ZP
@CPY
 
#C5: % CMP ZP
(0: @FETCH
(1: @ZP
@CMP
 
#C6: % DEC ZP
(0: @FETCH
(1: @ZP
@DEC_M
 
#C7: % *DCP ZP - incomplete
(0: @FETCH
(1: @ZP
@UNDOC
 
#C8: % INY
(0: @FETCH
(1: @INY
 
#C9: % CMP #IMM
(0: @FETCH
(1: @IMM
@CMP
 
#CA: % DEX
(0: @FETCH
(1: @DEX
 
#CB: % *AXS #IMM - incomplete
(0: @FETCH
(1: @IMM
@UNDOC
 
 
#CC: % CPY ABS
(0: @FETCH
(1: @ABS
@CPY
 
#CD: % CMP ABS
(0: @FETCH
(1: @ABS
@CMP
 
#CE: % DEC ABS
(0: @FETCH
(1: @ABS
@DEC_M
 
#CF: % *DCP ABS - incomplete
(0: @FETCH
(1: @ABS
@UNDOC
 
#D0: % BNE REL
(0: @FETCH
(1: @REL_READ
@ZF_TEST
@REL_JUMP
 
#D1: % CMP (IND),Y
(0: @FETCH
(1: @INDY_READ
@CMP
 
#D3: % *DCP (IND),Y - incomplete
(0: @FETCH
(1: @INDY_READ
@UNDOC
 
#D4: % *NOP ZP,X
(0: @FETCH
(1: @ZPX
@NOP
 
#D5: % CMP ZP,X
(0: @FETCH
(1: @ZPX
@CMP
 
#D6: % DEC ZP,X
(0: @FETCH
(1: @ZPX
@DEC_M
 
#D7: % *DCP ZP,X - incomplete
(0: @FETCH
(1: @ZPX
@UNDOC
 
#D8: % CLD
(0: @FETCH
@DF_OPERATE
 
#D9: % CMP ABS,Y
(0: @FETCH
(1: @ABSY_READ
@CMP
 
#DA: % *NOP
(0: @FETCH
(1: @NOP
 
#DB: % *DCP ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_READ
@UNDOC
 
#DC: % *NOP ABS,X
(0: @FETCH
(1: @ABSX_READ
@NOP
 
#DD: % CMP ABS,X
(0: @FETCH
(1: @ABSX_READ
@CMP
 
#DE: % DEC ABS,X
(0: @FETCH
(1: @ABSX_WRITE
@DEC_M
 
#DF: % *DCP ABS,X - incomplete
(0: @FETCH
(1: @ABSX_WRITE
@UNDOC
 
 
#E0: % CPX #IMM
(0: @FETCH
(1: @IMM
@CPX
 
#E1: % SBC (IND,X)
(0: @FETCH
(1: @INDX
@SBC
 
#E2: % *NOP #IMM
(0: @FETCH
(1: @IMM
@NOP
 
#E3: % *ISC (IND,X) - incomplete
(0: @FETCH
(1: @INDX
@UNDOC
 
 
#E4: % CPX ZP
(0: @FETCH
(1: @ZP
@CPX
 
#E5: % SBC ZP
(0: @FETCH
(1: @ZP
@SBC
 
#E6: % INC ZP
(0: @FETCH
(1: @ZP
@INC_M
 
#E7: % *ISC ZP - incomplete
(0: @FETCH
(1: @ZP
@UNDOC
 
#E8: % INX
(0: @FETCH
(1: @INX
 
#E9: % SBC #IMM
(0: @FETCH
(1: @IMM
@SBC
 
#EA: % NOP
(0: @FETCH
(1: @NOP
 
#EB: % *SBC #IMM
(0: @FETCH
(1: @IMM
@SBC
 
#EC: % CPX ABS
(0: @FETCH
(1: @ABS
@CPX
 
#ED: % SBC ABS
(0: @FETCH
(1: @ABS
@SBC
 
#EE: % INC ABS
(0: @FETCH
(1: @ABS
@INC_M
 
#EF: % *ISC ABS - incomplete
(0: @FETCH
(1: @ABS
@UNDOC
 
#F0: % BEQ REL
(0: @FETCH
(1: @REL_READ
@ZF_TEST
@REL_JUMP
 
#F1: % SBC (IND),Y
(0: @FETCH
(1: @INDY_READ
@SBC
 
#F3: % *ISC (IND),Y - incomplete
(0: @FETCH
(1: @INDY_READ
@UNDOC
 
#F4: % *NOP ZP,X
(0: @FETCH
(1: @ZPX
@NOP
 
 
#F5: % SBC ZP,X
(0: @FETCH
(1: @ZPX
@SBC
 
#F6: % INC ZP,X
(0: @FETCH
(1: @ZPX
@INC_M
 
#F7: % *ISC ZP,X - incomplete
(0: @FETCH
(1: @ZPX
@UNDOC
 
 
#F8: % SED
(0: @FETCH
@DF_OPERATE
 
 
#F9: % SBC ABS,Y
(0: @FETCH
(1: @ABSY_READ
@SBC
 
#FA: % *NOP
(0: @FETCH
(1: @NOP
 
#FB: % *ISC ABS,Y - incomplete
(0: @FETCH
(1: @ABSY_READ
@UNDOC
 
 
#FC: % *NOP ABS,X
(0: @FETCH
(1: @ABSX_READ
@NOP
 
#FD: % SBC ABS,X
(0: @FETCH
(1: @ABSX_READ
@SBC
 
#FE: % INC ABS,X
(0: @FETCH
(1: @ABSX_WRITE
@INC_M
 
#FF: % *ISC ABS,X - incomplete
(0: @FETCH
(1: @ABSX_READ
@UNDOC
/ag_6502/trunk/genstates/make.bat
0,0 → 1,2032
cl -D_CRT_SECURE_NO_DEPRECATE genstates.c
/ag_6502/trunk/genstates/genstates.c
0,0 → 1,1189
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <ctype.h>
 
 
#define ACTION_INVALID 0
#define ACTION_ASSIGN 1
#define ACTION_EXEC 2
 
 
int opt_level = 1; // 0 to allow verilog optimizer to produce better design,
// (-1) to do not even find common bits
 
struct STATE_ACTION
{
int atype;
const char*astr;
const char*astr_parsed; // w/o spaces, used to compare
};
 
#define TIME_ANY (-1)
#define TIME_INC (-2)
#define PHASE_ANY (-1)
 
#define NO_CODE (-1)
#define NO_MACROS (-1)
 
#define MIN_TIME 0
#define MAX_TIME 7
#define MIN_PHASE 1
#define MAX_PHASE 2
 
#define TIME_COUNT (MAX_TIME - MIN_TIME + 1)
 
struct STATE_ENTRY
{
int time, phase;
int action_id;
};
 
#define MAX_MACROS_SIZE 256
 
struct STATE_MACROS
{
const char*name;
int n_entries;
int entries[MAX_MACROS_SIZE];
};
 
#define MAX_CODE_SIZE 64
struct STATE_CODE
{
const char*comment;
int n_entries;
int entries[MAX_CODE_SIZE];
};
 
 
#define MAX_ACTIONS 8192
#define MAX_ENTRIES 8192
#define MAX_MACROSES 8192
#define MAX_CODES 512
 
#define MAX_STRING 1024
 
struct STATE_DATA
{
int n_actions, n_entries, n_macroses;
struct STATE_ACTION actions[MAX_ACTIONS];
struct STATE_ENTRY entries[MAX_ENTRIES];
struct STATE_MACROS macroses[MAX_MACROSES];
struct STATE_CODE codes[MAX_CODES];
 
int cur_time, cur_phase, cur_code, cur_macros;
};
 
static const char SPACES[] = " \t";
 
int get_action_code(const char*str)
{
return strstr(str, "<=")?ACTION_EXEC: ACTION_ASSIGN;
}
 
void clean_action(const char*str, char*buf)
{
for (; *str; ++str) if (!strchr(SPACES, *str)) *buf++ = *str;
*buf = 0;
}
 
void action_to_name(const char*str, char*buf)
{
for (; *str; ++str, ++buf) {
if (!isalnum(*str)) *buf = '_';
else *buf = *str;
}
*buf = 0;
}
 
int find_action(struct STATE_DATA*sd, const char*buf)
{
int i;
for (i = 0; i < sd->n_actions; ++i) {
if (!strcmp(sd->actions[i].astr_parsed, buf)) return i;
}
return -1;
}
 
int append_action(struct STATE_DATA*sd, const char*str)
{
char buf[MAX_STRING];
struct STATE_ACTION*a = sd->actions + sd->n_actions;
int r;
assert(sd->n_actions < MAX_ACTIONS);
clean_action(str, buf);
// puts(buf);
r = find_action(sd, buf);
if (r >= 0) return r;
a->atype = get_action_code(buf);
if (a->atype == ACTION_INVALID) {
fprintf(stderr, "invalid action: %s\n", str);
abort();
}
a->astr = _strdup(str);
a->astr_parsed = _strdup(buf);
return sd->n_actions++;
}
 
int find_entry(struct STATE_DATA*sd, int time, int phase, int action_id)
{
int i;
struct STATE_ENTRY*e = sd->entries;
for (i = 0; i < sd->n_entries; ++i, ++e) {
if (e->time == time && e->phase == phase && e->action_id == action_id) return i;
}
return -1;
}
 
int append_entry_copy(struct STATE_DATA*sd, int time, int phase, int action_id)
{
struct STATE_ENTRY*e = sd->entries + sd->n_entries;
int r;
r = find_entry(sd, time, phase, action_id);
if (r >= 0) return r;
assert(sd->n_entries < MAX_ENTRIES);
e->time = time;
e->phase = phase;
e->action_id = action_id;
return sd->n_entries++;
}
 
 
int append_entry(struct STATE_DATA*sd, int time, int phase, const char*str)
{
return append_entry_copy(sd, time, phase, append_action(sd, str));
}
 
int find_macros(struct STATE_DATA*sd, const char*name)
{
int i;
for (i = 0; i < sd->n_macroses; ++i) {
if (!strcmp(sd->macroses[i].name, name)) return i;
}
return -1;
}
 
int append_macros(struct STATE_DATA*sd, const char*name)
{
struct STATE_MACROS*m = sd->macroses + sd->n_macroses;
int r;
assert(sd->n_macroses < MAX_MACROSES);
r = find_macros(sd, name);
if (r >= 0) return r;
m->name = _strdup(name);
m->n_entries = 0;
return sd->n_macroses++;
}
 
int find_macros_entry(struct STATE_DATA*sd, int macro_id, int entry_id)
{
struct STATE_MACROS*m = sd->macroses + macro_id;
int i;
assert(macro_id >= 0 && macro_id < sd->n_macroses);
for (i = 0; i < m->n_entries; ++i) {
if (m->entries[i] == entry_id) return i;
}
return -1;
}
 
int append_macros_entry(struct STATE_DATA*sd, int macro_id, int entry_id)
{
struct STATE_MACROS*m = sd->macroses + macro_id;
int r;
// r = find_macros_entry(sd, macro_id, entry_id);
// if (r >= 0) return r;
assert(macro_id >= 0 && macro_id < sd->n_macroses);
assert(m->n_entries < MAX_MACROS_SIZE);
m->entries[m->n_entries++] = entry_id;
return m->n_entries - 1;
}
 
 
int append_code(struct STATE_DATA*sd, int value, const char*comment)
{
struct STATE_CODE*c = sd->codes + value;
assert(value >= 0 && value < MAX_CODES);
if (!c->comment) c->comment = comment?_strdup(comment):NULL;
else return -5;
return value;
}
 
 
int find_code_entry(struct STATE_DATA*sd, int code_id, int entry_id)
{
struct STATE_CODE*c = sd->codes + code_id;
int i;
assert(code_id >= 0 && code_id < MAX_CODES);
for (i = 0; i < c->n_entries; ++i) {
if (c->entries[i] == entry_id) return i;
}
return -1;
}
 
int append_code_entry(struct STATE_DATA*sd, int code_id, int entry_id)
{
struct STATE_CODE*c = sd->codes + code_id;
int r;
r = find_code_entry(sd, code_id, entry_id);
if (r >= 0) return r;
assert(code_id >= 0 && code_id < MAX_CODES);
assert(c->n_entries < MAX_CODE_SIZE);
c->entries[c->n_entries++] = entry_id;
return c->n_entries - 1;
}
 
int clear_data(struct STATE_DATA*sd)
{
memset(sd, 0, sizeof(*sd));
sd->cur_time = TIME_ANY;
sd->cur_phase = PHASE_ANY;
sd->cur_code = NO_CODE;
sd->cur_macros = NO_MACROS;
return 0;
}
 
int append_code_macros(struct STATE_DATA*sd, int code_id, int m_id)
{
struct STATE_MACROS*s = sd->macroses + m_id;
int i, r;
// printf("append_code_macros (%02X, %i): n_entries = %i\n", code_id, m_id, s->n_entries);
for (i = 0; i < s->n_entries; ++i) {
int e = s->entries[i];
int t = sd->entries[e].time;
int ph = sd->entries[e].phase;
if (t == TIME_INC) {
if (sd->cur_time == TIME_ANY) {
return -4;
}
t = sd->cur_time + 1;
}
if (t == TIME_ANY) t = sd->cur_time;
if (ph == PHASE_ANY) ph = sd->cur_phase;
if (t == TIME_ANY) return -1;
if (ph == PHASE_ANY) return -2;
sd->cur_time = t;
sd->cur_phase = ph;
r = append_code_entry(sd, code_id, append_entry_copy(sd, t, ph, sd->entries[e].action_id));
// printf("append_code_entry: %i: action_id = %i\n", r, sd->entries[e].action_id);
if (r < 0) return -3;
}
return 0;
}
 
int append_macros_macros(struct STATE_DATA*sd, int macro_id, int m_id)
{
struct STATE_MACROS*s = sd->macroses + m_id;
int i, r;
for (i = 0; i < s->n_entries; ++i) {
int e = s->entries[i];
int t = sd->entries[e].time;
int ph = sd->entries[e].phase;
if (t == TIME_ANY) t = sd->cur_time;
if (ph == PHASE_ANY) ph = sd->cur_phase;
sd->cur_time = t;
sd->cur_phase = ph;
r = append_macros_entry(sd, macro_id, append_entry_copy(sd, t, ph, sd->entries[e].action_id));
if (r < 0) return -3;
}
return 0;
}
 
 
int insert_macros(struct STATE_DATA*sd, const char*str)
{
int m_id, r;
m_id = find_macros(sd, str);
// printf("insert_macros: %s (%i)\n", str, m_id);
if (m_id < 0) {
fprintf(stderr, "error: unable to find macros: %s\n", str);
return 50;
}
if (sd->cur_code != NO_CODE) {
r = append_code_macros(sd, sd->cur_code, m_id);
} else {
r = append_macros_macros(sd, sd->cur_macros, m_id);
}
if (r < 0) {
fprintf(stderr, "error: unable to insert macros: %s: %i\n", str, r);
return 51;
}
return 0;
}
 
int parse_action(struct STATE_DATA*sd, char*str)
{
int e, r;
char*p;
p = strchr(str, '%');
if (p) *p = 0; // remove comment
// printf("action: %s\n", str);
if (sd->cur_code == NO_CODE && sd->cur_macros == NO_MACROS) {
fprintf(stderr, "error: no current macros or code in action: %s\n", str);
return 41;
}
if (str[0] == '@') return insert_macros(sd, str + 1);
if (sd->cur_code != NO_CODE && (sd->cur_time == TIME_ANY || sd->cur_phase == PHASE_ANY)) {
fprintf(stderr, "error: no current phase or time in action: %s\n", str);
return 42;
}
e = append_entry(sd, sd->cur_time, sd->cur_phase, str);
if (sd->cur_code != NO_CODE) {
r = append_code_entry(sd, sd->cur_code, e);
} else {
r = append_macros_entry(sd, sd->cur_macros, e);
}
if (r < 0) {
fprintf(stderr, "error: unable to append action: %s\n", str);
return 43;
}
return 0;
}
 
int parse_code(struct STATE_DATA*sd, char*str)
{
char*p, *c = NULL;
int v;
v = strtoul(str, &p, 16);
if (p[0] != ':') {
fprintf(stderr, "error: invalid code format: %s\n", str);
return 20;
}
++ p; p += strspn(p, SPACES);
if (p[0]) {
if (p[0] == '%') {
c = p + 1;
} else {
fprintf(stderr, "error: invalid code comment %s: %i\n", str, sd->cur_code);
return 22;
}
}
sd->cur_code = append_code(sd, v, c);
if (sd->cur_code < 0) {
fprintf(stderr, "error: unable to append code %s: %i\n", str, sd->cur_code);
return 21;
}
sd->cur_macros = NO_MACROS;
sd->cur_time = TIME_ANY;
sd->cur_phase = PHASE_ANY;
return 0;
}
 
int parse_macros(struct STATE_DATA*sd, char*str)
{
char*p = strchr(str, ':');
if (!p || p[1]) {
fprintf(stderr, "error: invalid macros format: %s\n", str);
return 30;
}
*p = 0;
sd->cur_macros = append_macros(sd, str);
if (sd->cur_macros < 0) {
fprintf(stderr, "error: unable to append macros %s: %i\n", str, sd->cur_macros);
return 31;
}
sd->cur_code = NO_CODE;
sd->cur_time = TIME_ANY;
sd->cur_phase = PHASE_ANY;
return 0;
}
 
int parse_place(struct STATE_DATA*sd, char*str)
{
int t, ph;
char*p, *s0 = str;
if (str[0] == '+' && str[1] == ':') {
if (sd->cur_time == TIME_ANY) {
if (sd->cur_code != NO_CODE) {
fprintf(stderr, "error: no current time for increment: %s\n", str);
return 14;
} else {
sd->cur_time = TIME_INC;
}
} else ++sd->cur_time;
++str;
}
if (str[0] != ':') {
t = strtoul(str, &p, 10);
if (*p != ':') {
fprintf(stderr, "error: invalid place format: %s\n", str);
return 10;
}
if (t < MIN_TIME || t > MAX_TIME) {
fprintf(stderr, "error: invalid time value: %i\n", t);
return 11;
}
sd->cur_time = t;
str = p;
}
++str;
if (!strchr(SPACES, str[0])) {
ph = strtoul(str, &p, 10);
if (!strchr(SPACES, *p)) {
fprintf(stderr, "error: invalid place format: %s\n", str);
return 12;
}
if (ph < MIN_PHASE || ph > MAX_PHASE) {
fprintf(stderr, "error: invalid phase value: %i\n", ph);
return 13;
}
sd->cur_phase = ph;
str = p;
}
++str;
return str - s0 + strspn(str, SPACES) + 1;
}
 
int parse_line(struct STATE_DATA*sd, char*str)
{
int n = strspn(str, SPACES), r;
if (!str[n]) return 0;
switch (str[0]) {
case '#':
return parse_code(sd, str + 1);
case '@':
return parse_macros(sd, str + 1);
case '(':
n = parse_place(sd, str + 1);
if (n < 0) return n;
case ' ': case '\t':
r = parse_action(sd, str + n);
if (sd->cur_time == TIME_INC) sd->cur_time = TIME_ANY;
return r;
case '%':
return 0; // comment
}
fprintf(stderr, "error: invalid string format: %s\n", str);
return 9;
}
 
int load_data(struct STATE_DATA*sd, const char*fname)
{
FILE*in;
int lno = 0;
int r = 0;
char buf[MAX_STRING];
 
in = fopen(fname, "rt");
if (!in) {
perror(fname);
return -1;
}
 
while (fgets(buf, sizeof(buf), in)) {
int l;
++ lno;
l = strlen(buf);
if (l && buf[l - 1] == '\n') buf[--l] = 0;
r = parse_line(sd, buf);
if (r) {
fprintf(stderr, "%s: error parsing line %i: %i\n", fname, lno, r);
break;
}
}
fclose(in);
return r;
}
 
int write_data(struct STATE_DATA*sd, const char*fname)
{
FILE*out;
int i, j, k, l, ct, cp;
out = fopen(fname, "wt");
if (!out) {
perror(fname);
return -1;
}
 
for (i = 0; i < MAX_CODES; ++i) {
struct STATE_CODE*c = sd->codes + i;
if (!c->n_entries) continue;
ct = TIME_ANY;
cp = PHASE_ANY;
if (c->comment) fprintf(out, "#%02X: %%%s\n", i, c->comment);
else fprintf(out, "#%02X:\n", i);
for (j = MIN_TIME; j <= MAX_TIME; ++j) {
for (k = MIN_PHASE; k <= MAX_PHASE; ++k) {
for (l = 0; l < c->n_entries; ++l) {
struct STATE_ENTRY*e = sd->entries + c->entries[l];
if (e->time != j || e->phase != k) continue;
if (ct != j || cp != k) {
fprintf(out, "(%i:%i", j, k);
ct = j;
cp = k;
}
fprintf(out, "\t%s\n", sd->actions[e->action_id].astr);
}
}
}
fprintf(out, "\n");
}
 
fclose(out);
return 0;
}
 
int validate_data(struct STATE_DATA*sd)
{
int i, j;
 
for (i = 0; i < MAX_CODES; ++i) {
struct STATE_CODE*c = sd->codes + i;
if (!c->n_entries) continue;
for (j = 0; j < c->n_entries; ++j) {
struct STATE_ENTRY*e = sd->entries + c->entries[j];
struct STATE_ACTION*a = sd->actions + e->action_id;
if (e->phase == 2 && a->atype == ACTION_ASSIGN) {
fprintf(stderr, "error: no assignments are valid in phase 2 for code %02X: %s\n",
i, a->astr);
return -10;
}
}
}
return 0;
}
 
 
int code_has_action(struct STATE_DATA*sd, int code_id, int time, int action_id)
{
struct STATE_CODE*c = sd->codes + code_id;
int i;
 
for (i = 0; i < c->n_entries; ++i) {
if (sd->entries[c->entries[i]].time == time && sd->entries[c->entries[i]].action_id == action_id) return 1;
}
return 0;
}
 
 
#define CODE_NONE 0
#define CODE_ACTION 1
 
#define BIT_COMMON 0
#define BIT_OTHER 1
 
#define N_BITS (8+3)
 
#define VBIT_0 0
#define VBIT_1 1
#define VBIT_UNKNOWN 2
#define VBIT_VAR 3
 
unsigned prepare_selector(int code, int time)
{
return code | (time << 8);
}
 
void print_selector(FILE*out, unsigned sel)
{
int k;
for (k = N_BITS - 1; k >= 0; --k, sel <<= 1) {
int c;
fputc((sel & (1<<(N_BITS - 1)))?'1': '0', out);
if (!(k & 7)) fputc(' ', out);
}
}
 
#define DEBUG 1
 
 
 
unsigned expand_common_bits(FILE*out, unsigned other_mask,
const unsigned other_codes[], int n_other,
int common_bit, int bit_val,
unsigned *mask, unsigned*val,
unsigned sel_mask, unsigned sel_val)
{
int i, j, c;
unsigned m, mc, vc, r;
char out_bits[N_BITS];
mc = 1 << common_bit;
vc = bit_val ? mc: 0;
other_mask &= ~mc;
memset(out_bits, VBIT_UNKNOWN, sizeof(out_bits));
for (j = 0; j < n_other; ++j) {
if ((other_codes[j] & sel_mask) != sel_val) continue;
if ((other_codes[j] & mc) != vc) continue;
for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (!(other_mask & m)) continue;
if (out_bits[i] == VBIT_VAR) continue;
// fprintf(out, "bits[%03X:%i] = %i (%i)\n", other_codes[j], i, out_bits[i], (other_codes[j] & m)?1:0);
if (other_codes[j] & m) {
if (out_bits[i] == VBIT_UNKNOWN)
out_bits[i] = VBIT_1;
else if (out_bits[i] != VBIT_1)
out_bits[i] = VBIT_VAR;
} else {
if (out_bits[i] == VBIT_UNKNOWN)
out_bits[i] = VBIT_0;
else if (out_bits[i] != VBIT_0)
out_bits[i] = VBIT_VAR;
}
}
}
*val = 0;
for (i = 0, r = 0, m = 1, c = 0; i < N_BITS; ++i, m <<= 1) {
if ((out_bits[i] == VBIT_1) || (out_bits[i] == VBIT_0)) {
r |= m;
if (out_bits[i] == VBIT_1) *val |= m;
++ c;
}
}
*mask = r;
return c;
}
 
int check_full_bits(FILE*out, unsigned other_mask,
const unsigned other_codes[], int n_other,
unsigned sel_mask, unsigned sel_val)
{
int i, j;
unsigned m;
int nv;
unsigned test_codes[MAX_CODES * TIME_COUNT];
int n_codes, f_codes;
 
 
/* fprintf(out, "****check_full_bits: other_mask = ");
print_selector(out, other_mask);
fprintf(out, ", sel_mask = ");
print_selector(out, sel_mask);
fprintf(out, ", sel_val = ");
print_selector(out, sel_val);
fprintf(out, "\n");*/
 
if (!other_mask) return 1;
 
 
for (i = 0, nv = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (other_mask & m) ++ nv;
}
assert(nv);
f_codes = 1 << nv;
 
for (j = 0, n_codes = 0; j < n_other; ++j) {
int f = 0;
unsigned oc;
if ((other_codes[j] & sel_mask) != sel_val) continue;
oc = other_codes[j] & other_mask;
for (i = 0; i < n_codes; ++i) {
if (test_codes[i] == oc) {
f = 1;
break;
}
}
if (f) continue;
/* fprintf(out,"uniq code: ");
print_selector(out, oc);
fprintf(out, "\n"); */
test_codes[n_codes++] = oc;
if (n_codes == f_codes) return 1;
}
return 0;
}
 
 
 
int find_common_bit(FILE*out, unsigned other_mask,
const unsigned other_codes[], int n_other,
unsigned sel_mask, unsigned sel_val,
int nn[2], unsigned mm[2], unsigned vv[2])
{
int counts[N_BITS][2];
unsigned masks[N_BITS][2];
unsigned vals[N_BITS][2];
// int fulls[N_BITS][2];
unsigned m, mv;
int i, j;
int max_count = -1;
int max_bit = -1;
 
memset(counts, 0, sizeof(counts));
 
// print available codes
/*
for (j = 0; j < n_other; ++j) {
if ((other_codes[j] & sel_mask) != sel_val) continue;
fprintf(out, "***code[%i]: ", j);
print_selector(out, other_codes[j]);
fprintf(out, "\n");
}
*/
// compute counts
/* for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (!(other_mask & m)) continue;
for (j = 0; j < n_other; ++j) {
if ((other_codes[j] & sel_mask) != sel_val) continue;
++ counts[i][(other_codes[j] & m)?1:0];
}
}
*/
 
for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (!(other_mask & m)) continue;
counts[i][0] = expand_common_bits(out, other_mask,
other_codes, n_other, i, 0,
masks[i] + 0, vals[i] + 0,
sel_mask, sel_val);
counts[i][1] = expand_common_bits(out, other_mask,
other_codes, n_other, i, 1,
masks[i] + 1, vals[i] + 1,
sel_mask, sel_val);
/* fulls[i][0] = check_full_bits(out,
other_mask & ~(masks[i][0] | m),
other_codes, n_other,
sel_mask | (masks[i][0] | m),
sel_val | (vals[i][0]));
fulls[i][1] = check_full_bits(out,
other_mask & ~(masks[i][1] | m),
other_codes, n_other,
sel_mask | (masks[i][1] | m),
sel_val | (vals[i][1] | m));*/
// fprintf(out, "counts[%i] = %i, %i (%i,%i)\n", i,
// counts[i][0], counts[i][1],
// fulls[i][0], fulls[i][1]);
}
 
for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (!(other_mask & m)) continue;
if (max_count < counts[i][0]) {
max_count = counts[i][0];
max_bit = i;
} else if (max_count < counts[i][1]) {
max_count = counts[i][1];
max_bit = i;
}
}
if (max_bit == -1) return -1;
 
// compute result counts
nn[0] = nn[1] = 0;
mv = 1 << max_bit;
for (j = 0; j < n_other; ++j) {
if ((other_codes[j] & sel_mask) != sel_val) continue;
if (other_codes[j] & mv) ++nn[1]; else ++nn[0];
}
 
// nn[0] = counts[max_bit][0];
// nn[1] = counts[max_bit][1];
 
mm[0] = masks[max_bit][0];
mm[1] = masks[max_bit][1];
 
vv[0] = vals[max_bit][0];
vv[1] = vals[max_bit][1];
 
 
 
 
// print counts
/* fprintf(out, "****Counts for mask (max_bit = %i): ", max_bit);
print_selector(out, other_mask);
fprintf(out, "\n");
for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (!(other_mask & m)) continue;
fprintf(out, "//\t\tbit %i: (%i, %i)\n", i, counts[i][0], counts[i][1]);
}*/
 
return max_bit;
}
 
 
int print_sel_bits(FILE*out, unsigned mask, unsigned val)
{
int nv, rv;
int i, iv, vv;
unsigned m;
for (i = 0, nv = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (mask & m) {
++ nv;
iv = i;
vv = (val & m)?1:0;
}
}
if (nv == 1) {
fprintf(out, "%sL[%i]", vv?"":"!", iv);
return 1;
}
fprintf(out, "({");
for (i = 0, rv = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (mask & m) {
if (rv) fprintf(out, ",");
fprintf(out, "L[%i]", i);
++ rv;
}
}
fprintf(out, "} == %i'b", nv);
for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (mask & m) {
fprintf(out, "%c", (val & m)?'1':'0');
}
}
fprintf(out, ")");
return nv;
 
}
 
void print_other(FILE*out, unsigned other_mask, const unsigned other_codes[], int n_other, unsigned sel_mask, unsigned sel_val)
{
int j, nn = 0;
for (j = 0; j < n_other; ++j) {
if ((other_codes[j] & sel_mask) != sel_val) continue;
// if (!nn) fprintf(out, "(");
if (nn) fprintf(out, " || ");
print_sel_bits(out, other_mask, other_codes[j]);
++nn;
}
// if (nn) fprintf(out, ")");
}
 
 
void recurse_other(FILE*out, unsigned other_mask, const unsigned other_codes[], int n_other, unsigned sel_mask, unsigned sel_val, int level)
{
int nn[2];
unsigned mm[2], vv[2];
unsigned cbm;
int cb;
unsigned sm0, sm1, sv0, sv1;
int cf0, cf1;
 
/* fprintf(out, "\n**recurse_other[%i]: n_other = %i, other_mask = ", level, n_other);
print_selector(out, other_mask);
fprintf(out, ", sel_mask = ");
print_selector(out, sel_mask);
fprintf(out, ", sel_val = ");
print_selector(out, sel_val);
fprintf(out, "\n");
*/
if (opt_level != -1 && level >= opt_level) {
print_other(out, other_mask, other_codes, n_other, sel_mask, sel_val);
return;
}
 
if (!other_mask) return;
 
 
cb = find_common_bit(out, other_mask, other_codes, n_other,
sel_mask, sel_val, nn, mm, vv);
if (cb == -1) exit(100);
cbm = 1<<cb;
// expand_common_bits(out, other_mask, other_codes, n_other, cb, 0, &m0, &v0, sel_mask, sel_val);
// expand_common_bits(out, other_mask, other_codes, n_other, cb, 1, &m1, &v1, sel_mask, sel_val);
/* fprintf(out, "** find_common_bit: %i: ", cb);
print_selector(out, mm[0]);
fprintf(out, ", ");
print_selector(out, mm[1]);
fprintf(out, "\n");
*/
if (cbm == other_mask && !mm[0] && !mm[1]) {
fprintf(out, "1'b1");
return;
}
mm[0] |= cbm;
mm[1] |= cbm;
vv[1] |= cbm;
 
sm0 = sel_mask | mm[0];
sm1 = sel_mask | mm[1];
 
sv0 = sel_val | vv[0];
sv1 = sel_val | vv[1];
 
cf0 = check_full_bits(out, other_mask & ~mm[0], other_codes, n_other, sm0, sv0);
cf1 = check_full_bits(out, other_mask & ~mm[1], other_codes, n_other, sm1, sv1);
 
// fprintf(out, "\nnn[0] = %i, nn[1] = %i, cf0 = %i, cf1 = %i\n", nn[0], nn[1], cf0, cf1);
 
if (nn[0]) {
if (!cf0 && nn[1]) {
fprintf(out, "(");
}
print_sel_bits(out, mm[0], vv[0]);
if (!cf0) {
fprintf(out, " && (");
recurse_other(out, other_mask & ~mm[0], other_codes, n_other, sm0, sv0, level + 1);
fprintf(out, ")");
if (nn[1]) fprintf(out, ")");
}
if (nn[1]) fprintf(out, " || ");
}
if (nn[1]) {
if (!cf1 && nn[0]) {
fprintf(out, "(");
}
print_sel_bits(out, mm[1], vv[1]);
if (!cf1) {
fprintf(out, " && (");
recurse_other(out, other_mask & ~mm[1], other_codes, n_other, sm1, sv1, level + 1);
fprintf(out, ")");
if (nn[0]) fprintf(out, ")");
}
}
}
 
int print_verilog_line(FILE*out, const char bits[N_BITS], const char vbits[N_BITS], const int codes[MAX_CODES][MAX_TIME-MIN_TIME + 1])
{
int i;
int n_bits[4] = {0, 0, 0, 0};
int common_vals[N_BITS], common_inds[N_BITS];
int other_inds[N_BITS];
unsigned other_mask = 0, m;
unsigned other_codes[MAX_CODES * TIME_COUNT];
int n_other;
for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
int n = n_bits[bits[i]] ++;
switch (bits[i]) {
case BIT_COMMON:
common_vals[n] = (vbits[i] == VBIT_0)?0:1;
common_inds[n] = i;
break;
case BIT_OTHER:
other_inds[n] = i;
other_mask |= m;
break;
}
}
 
// check for full other list
if (n_bits[BIT_OTHER]) {
int j, t;
n_other = 0;
for (j = 0; j < MAX_CODES; ++j) {
for (t = MIN_TIME; t <= MAX_TIME; ++t) {
unsigned int val = prepare_selector(j, t) & other_mask;
int r = -1;
if (codes[j][t] != CODE_ACTION) continue;
for (i = 0; i < n_other; ++i) {
if (other_codes[i] == val) { r = i; break; }
}
if (r == -1) other_codes[n_other++] = val;
}
}
// fprintf(out, "//\tn_other = %i (%i)\n", n_other, 1 << n_bits[BIT_OTHER]);
if (n_other == (1 << n_bits[BIT_OTHER])) n_bits[BIT_OTHER] = 0;
}
 
if (!n_bits[BIT_COMMON] && !n_bits[BIT_OTHER]) {
fprintf(out, "1'b1");
return 0;
}
if (n_bits[BIT_COMMON]) {
fprintf(out, "({");
for (i = 0; i < n_bits[BIT_COMMON]; ++i) {
fprintf(out, "L[%i]", common_inds[i]);
if (i < n_bits[BIT_COMMON] - 1) fprintf(out, ",");
}
fprintf(out, "} == %i'b", n_bits[BIT_COMMON]);
for (i = 0; i < n_bits[BIT_COMMON]; ++i) {
fprintf(out, "%i", common_vals[i]);
}
fprintf(out, ")");
if (n_bits[BIT_OTHER]) fprintf(out, " && (");
}
if (n_bits[BIT_OTHER]) {
// fprintf(out, "(");
recurse_other(out, other_mask, other_codes, n_other, 0, 0, 1);
// fprintf(out, ")");
}
if (n_bits[BIT_COMMON]) {
if (n_bits[BIT_OTHER]) fprintf(out, ")");
}
/* if (n_bits[BIT_OTHER]) {
int j, t;
fprintf(out, "(");
n_other = 0;
for (j = 0; j < MAX_CODES; ++j) {
for (t = MIN_TIME; t <= MAX_TIME; ++t) {
unsigned int val = prepare_selector(j, t) & other_mask;
int r = -1;
 
if (codes[j][t] != CODE_ACTION) continue;
 
for (i = 0; i < n_other; ++i) {
if (other_codes[i] == val) { r = i; break; }
}
if (r != -1) continue;
if (n_other) fprintf(out, " || ");
fprintf(out, "({");
for (i = 0; i < n_bits[BIT_OTHER]; ++i) {
fprintf(out, "L[%i]", other_inds[i]);
if (i < n_bits[BIT_OTHER] - 1) fprintf(out, ",");
}
fprintf(out, "} == %i'b", n_bits[BIT_OTHER]);
for (i = 0, m = 1; i < N_BITS; ++i, m <<= 1) {
if (other_mask & m) {
fprintf(out, "%i", (val&m)?1:0);
}
}
fprintf(out, ")");
other_codes[n_other++] = val;
}
}
fprintf(out, ")");
}*/
return 0;
}
 
 
int process_data(struct STATE_DATA*sd, const char*fname)
{
int i, j, k, l, t;
int r;
unsigned m;
FILE*out;
int codes[MAX_CODES][TIME_COUNT];
char bits[N_BITS];
char vbits[N_BITS];
out = fopen(fname, "wt");
if (!out) {
perror(fname);
return -1;
}
fprintf(out, "// This file has been generated automatically\n"
"//\tby the GenStates tool\n"
"// Copyright (c) Oleg Odintsov\n"
"// This tool is a part of Agat hardware project\n\n");
 
if (opt_level == -1) {
fprintf(out, "//\tLevel of optimization: infinite\n");
} else {
fprintf(out, "//\tLevel of optimization: %i\n", opt_level);
}
 
fprintf(out, "//\tTotal number of actions: %i\n", sd->n_actions);
for (i = 0; i < sd->n_actions; ++i) {
char name[MAX_STRING];
action_to_name(sd->actions[i].astr_parsed, name);
fprintf(out, "\twire %s%s;\n", (sd->actions[i].atype == ACTION_EXEC)?"E_": "A_", name);
}
fprintf(out, "\n//\tActions assignments\n");
// for all actions
for (i = 0; i < sd->n_actions; ++i) {
const char*p;
int n;
char name[MAX_STRING];
int n_active = 0;
#if DEBUG
fprintf(out, "\n//\taction: %s:\n", sd->actions[i].astr);
#endif
memset(codes, CODE_NONE, sizeof(codes));
// find codes with this action
for (j = 0; j < MAX_CODES; ++j) {
for (t = MIN_TIME; t <= MAX_TIME; ++t)
if (code_has_action(sd, j, t, i)) {
codes[j][t] = CODE_ACTION;
++ n_active;
/*#if DEBUG
fprintf(out, "//\t\t(%i, %02X: ", t, j);
print_selector(out, prepare_selector(j, t));
fprintf(out, ")\n");
#endif*/
}
}
if (!n_active) {
action_to_name(sd->actions[i].astr_parsed, name);
fprintf(out, "\tassign %s%s = 1'b0;\n", (sd->actions[i].atype == ACTION_EXEC)?"E_": "A_", name);
continue;
}
 
 
// Selecting common bits@action (BIT_COMMON)
if (opt_level == 1) {
memset(bits, BIT_COMMON, sizeof(bits));
memset(vbits, VBIT_UNKNOWN, sizeof(vbits));
for (j = 0; j < MAX_CODES; ++j) {
for (t = MIN_TIME; t <= MAX_TIME; ++t) {
unsigned int val = prepare_selector(j, t);
if (codes[j][t] != CODE_ACTION) continue;
for (k = 0, m = 1; k < N_BITS; ++k, m<<=1) {
if (bits[k] != BIT_COMMON) continue;
if (val & m) {
if (vbits[k] == VBIT_UNKNOWN)
vbits[k] = VBIT_1;
else if (vbits[k] != VBIT_1)
bits[k] = BIT_OTHER;
} else {
if (vbits[k] == VBIT_UNKNOWN)
vbits[k] = VBIT_0;
else if (vbits[k] != VBIT_0)
bits[k] = BIT_OTHER;
}
}
}
}
} else {
memset(bits, BIT_OTHER, sizeof(bits));
memset(vbits, VBIT_UNKNOWN, sizeof(vbits));
}
// debug print
/*
#if DEBUG
fprintf(out, "// %14s: ", sd->actions[i].astr);
for (k = N_BITS - 1; k >= 0; --k) {
int c;
if (bits[k] == BIT_COMMON) c = (vbits[k] == VBIT_0)?'0':(vbits[k] == VBIT_1)?'1':'2';
else c = '?';
fprintf(out, "%c", c);
if (!(k & 7)) fprintf(out, " ");
}
fprintf(out, "\n");
#endif
*/
// verilog output
action_to_name(sd->actions[i].astr_parsed, name);
fprintf(out, "\tassign %s%s = ", (sd->actions[i].atype == ACTION_EXEC)?"E_": "A_", name);
print_verilog_line(out, bits, vbits, codes);
fprintf(out, ";\n");
}
fclose(out);
return 0;
}
 
 
void print_help(const char*cmd)
{
printf("Use %s [-Olevel | -h] [states.txt] [states_out.txt] [states.v]\n"
"\t-h\tPrint this help;\n"
"\t-Olevel\tSpecify level of optimization (default is 1):\n"
"\t\t0 - no optimization\n"
"\t\t1 - just group common bits (default, best for hardware)\n"
"\t\t>1 - higher levels\n"
"\t\t-1 - infinite optimization (best for simulation).\n\n"
"Copyright (c) Odintsov Oleg, nnop@newmail.ru\n"
"This tool is a part of Agat hardware project.\n", cmd);
exit(100);
}
 
struct STATE_DATA sd;
 
int main(int argc, const char*argv[])
{
int r;
int s = 0;
if (argc > 1 && argv[1][0] == '-') {
switch (argv[1][1]) {
case '?': case 'h': case 'H': print_help(argv[0]);
case 'O':
opt_level = atoi(argv[1] + 2);
if (opt_level == -1) {
printf("level of optimization: infinite\n");
} else {
printf("level of optimization: %i\n", opt_level);
}
}
s = 1;
}
clear_data(&sd);
r = load_data(&sd, (argc > (s + 1))? argv[s + 1]: "states.txt");
if (r) return r;
r = validate_data(&sd);
if (r) return r;
r = write_data(&sd, (argc > (s + 2))? argv[s + 2]: "states_out.txt");
if (r) return r;
r = process_data(&sd, (argc > (s + 3))? argv[s + 3]: "states.v");
if (r) return r;
return 0;
}

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