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/trunk/rtl/dut.v
0,0 → 1,92
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//DUT
 
module DUT(dut_clk, dut_res, dut_stb,
dut_sel,
dut_data_in_0, dut_data_in_1, dut_data_in_2,
dut_data_valid_in,
dut_valid_0, dut_valid_1,
dut_out_0, dut_out_1,
dut_parity_0, dut_parity_1);
 
input dut_clk, dut_res, dut_stb;
input [1:0] dut_sel;
input [7:0] dut_data_in_0, dut_data_in_1, dut_data_in_2;
input dut_data_valid_in;
output dut_valid_0, dut_valid_1;
output [15:0] dut_out_0, dut_out_1;
output dut_parity_0, dut_parity_1;
 
wire [7:0] dut_data_out;
wire dut_data_valid_out;
wire dut_selector_alu_stb;
wire dut_alu_dmux_stb;
wire [15:0] dut_alu_result;
wire dut_parity;
wire dut_output_channel;
wire dut_parity_0, dut_parity_1;
 
//Modules' instantiations
 
SELECTOR selector(.clk(dut_clk), .res(dut_res), .stb(dut_stb),
.sel(dut_sel),
.data_in_0(dut_data_in_0), .data_in_1(dut_data_in_1), .data_in_2(dut_data_in_2),
.data_valid_in(dut_data_valid_in),
.data_out(dut_data_out), .data_valid_out(dut_data_valid_out),
.stb_out(dut_selector_alu_stb));
 
ALU alu(.clk(dut_clk), .res(dut_res), .alu_stb_in(dut_selector_alu_stb),
.alu_data_in(dut_data_out), .alu_data_valid_in(dut_data_valid_out),
.alu_result(dut_alu_result), .result_parity(dut_parity),
.output_channel(dut_output_channel),
.alu_stb_out(dut_alu_dmux_stb));
 
DMUX dmux(.clk(dut_clk), .res(dut_res), .dmux_stb_in(dut_alu_dmux_stb),
.alu_result(dut_alu_result), .result_parity(dut_parity),
.output_channel(dut_output_channel),
.valid_0(dut_valid_0), .valid_1(dut_valid_1),
.out_0(dut_out_0), .out_1(dut_out_1),
.parity_0(dut_parity_0), .parity_1(dut_parity_1));
 
endmodule
/trunk/rtl/dmux.v
0,0 → 1,118
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//DMUX
 
module DMUX(clk, res, dmux_stb_in,
alu_result, result_parity,
output_channel,
valid_0, valid_1,
out_0, out_1,
parity_0, parity_1);
 
input clk, res, dmux_stb_in;
input [15:0] alu_result;
input result_parity;
input output_channel;
output valid_0, valid_1;
output [15:0] out_0, out_1;
output parity_0, parity_1;
 
reg valid_0, valid_1;
reg [15:0] out_0, out_1;
reg parity_0, parity_1;
 
reg dmux_stb_in_was_1;
integer i;
 
always @ (posedge clk or posedge res)
begin
if(res)
begin
valid_0 = 0;
valid_1 = 0;
out_0 = 16'b0;
out_1 = 16'b0;
parity_0 = 0;
parity_1 = 0;
dmux_stb_in_was_1 = 0;
i = 0;
end
else
begin
if(valid_0 === 1)
valid_0 = 0;
if(valid_1 === 1)
valid_1 = 0;
end
end
 
always @ (posedge clk)
begin
if(dmux_stb_in === 1)
dmux_stb_in_was_1 = 1;
if(dmux_stb_in_was_1 === 1)
i = i + 1;
end
 
always @ (i)
if (i === 5)
begin
case(output_channel)
1'b0:
begin
out_0 = alu_result;
parity_0 = result_parity;
valid_0 = 1;
end
1'b1:
begin
out_1 = alu_result;
parity_1 = result_parity;
valid_1 = 1;
end
endcase
i = 0;
dmux_stb_in_was_1 = 0;
end
endmodule
/trunk/rtl/selector.v
0,0 → 1,88
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//SELECTOR
 
module SELECTOR(clk, res, stb,
sel,
data_in_0, data_in_1, data_in_2,
data_valid_in,
data_out, data_valid_out,
stb_out);
 
input clk, res, stb;
input [1:0] sel;
input [7:0] data_in_0, data_in_1, data_in_2;
input data_valid_in;
output [7:0] data_out;
output data_valid_out;
output stb_out;
 
reg [1:0] reg_sel;
reg [7:0] data_out;
reg data_valid_out;
reg stb_out;
 
always @ (posedge clk or posedge res)
begin
if(res)
begin
reg_sel = 1'b0;
data_out = 8'b0;
data_valid_out = 1'b0;
stb_out = 1'b0;
end
else
begin
if(stb)
reg_sel = sel;
case(reg_sel[1:0])
2'b00: data_out = data_in_0;
2'b01: data_out = data_in_1;
2'b10: data_out = data_in_2;
endcase
data_valid_out = data_valid_in;
stb_out = stb;
end
end
 
endmodule
/trunk/rtl/alu.v
0,0 → 1,379
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//ALU
 
module ALU(clk, res, alu_stb_in,
alu_data_in, alu_data_valid_in,
alu_result, result_parity,
output_channel,
alu_stb_out);
 
input clk, res, alu_stb_in;
input [7:0] alu_data_in;
input alu_data_valid_in;
output [15:0] alu_result;
output result_parity;
output output_channel;
output alu_stb_out;
 
reg [15:0] alu_result;
reg result_parity;
reg [3:0] operator_type;
reg [2:0] operator_symbol;
reg output_channel;
reg [7:0] alu_memory [0:15];
reg alu_stb_out;
 
integer i;
integer j;
reg executed_case_once;
always @ (posedge clk or posedge res)
if(res)
begin
alu_result = 16'b0;
result_parity = 1'b0;
operator_type = 4'b1111;
operator_symbol = 3'b111;
output_channel = 1'b0;
for(i = 0; i < 15; i = i + 1)
alu_memory[i] = 8'b0;
i = 0;
j = 0;
executed_case_once = 1'b0;
end
else
begin
if(alu_stb_in)
begin
operator_type = alu_data_in[7:4];
operator_symbol = alu_data_in[3:1];
output_channel = alu_data_in[0];
executed_case_once = 1'b0;
end
if((alu_data_valid_in) && (! alu_stb_in))
begin
alu_memory[i] = alu_data_in;
i = i + 1;
end
if((! alu_data_valid_in) && (! alu_stb_in) && (! executed_case_once))
begin
executed_case_once = 1'b1;
if(i !== 0)
for(j=i;j<16; j=j+1)
alu_memory[j] = 8'b0;
i = 0;
case (operator_type)
'd0: //Arithmetic
begin
$display("Arithmetic operator");
case(operator_symbol)
'd0: //Multiply
begin
alu_result = (alu_memory[0] * alu_memory[1]);
$display("OPERATION * (Multiply): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Divide
begin
alu_result = (alu_memory[0] / alu_memory[1]);
$display("OPERATION / (Divide): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Add
begin
alu_result = (alu_memory[0] + alu_memory[1]);
$display("OPERATION + (Add): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Substract
begin
alu_result = (alu_memory[0] - alu_memory[1]);
$display("OPERATION - (Substract): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd4: //Modulus
begin
alu_result = (alu_memory[0] % alu_memory[1]);
$display("OPERATION (Modulus): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd1: //Logical
begin
$display("Logical operator");
case(operator_symbol)
'd0: //Logical negation
begin
alu_result = (!alu_memory[0]);
$display("OPERATION ! (Logical negation): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd1: //Logical and
begin
alu_result = (alu_memory[0] && alu_memory[1]);
$display("OPERATION && (Logical and): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Logical or
begin
alu_result = (alu_memory[0] || alu_memory[1]);
$display("OPERATION || (Logical or): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd2: //Relational
begin
$display("Relational operator");
case(operator_symbol)
'd0: //Greater than
begin
alu_result = (alu_memory[0] > alu_memory[1]);
$display("OPERATION > (Greater than): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Less than
begin
alu_result = (alu_memory[0] < alu_memory[1]);
$display("OPERATION < (Less than): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Greater than or equal
begin
alu_result = (alu_memory[0] >= alu_memory[1]);
$display("OPERATION >= (Greater than or equal): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Less than or equal
begin
alu_result = (alu_memory[0] <= alu_memory[1]);
$display("OPERATION <= (Less than or equal): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd3: //Equality
begin
$display("Equality operator");
case(operator_symbol)
'd0: //Equality
begin
alu_result = (alu_memory[0] == alu_memory[1]);
$display("OPERATION == (Equality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Inequality
begin
alu_result = (alu_memory[0] != alu_memory[1]);
$display("OPERATION != (Inequality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Case equality
begin
alu_result = (alu_memory[0] === alu_memory[1]);
$display("OPERATION === (Case equality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Case inequality
begin
alu_result = (alu_memory[0] !== alu_memory[1]);
$display("OPERATION !== (Case inequality): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd4: //Bitwise
begin
$display("Bitwise operator");
case(operator_symbol)
'd0: //Bitwise negation
begin
alu_result = (~ alu_memory[0]);
$display("OPERATION ~ (Bitwise negation): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd1: //Bitwise and
begin
alu_result = (alu_memory[0] & alu_memory[1]);
$display("OPERATION & (Bitwise and): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd2: //Bitwise or
begin
alu_result = (alu_memory[0] | alu_memory[1]);
$display("OPERATION | (Bitwise or): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd3: //Bitwise xor
begin
alu_result = (alu_memory[0] ^ alu_memory[1]);
$display("OPERATION ^ (Bitwise xor): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd4: //Bitwise xnor (1st operator symbol)
begin
alu_result = (alu_memory[0] ^~ alu_memory[1]);
$display("OPERATION ^~ (Bitwise xnor (1st operator symbol)): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd5: //Bitwise xnor (2nd operator symbol)
begin
alu_result = (alu_memory[0] ~^ alu_memory[1]);
$display("OPERATION ~^ (Bitwise xnor (2nd operator symbol)): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd5: //Reduction
begin
$display("Reduction operator");
case(operator_symbol)
'd0: //Reduction and
begin
alu_result = (& alu_memory[0]);
$display("OPERATION & (Reduction and): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd1: //Reduction nand
begin
alu_result = (~& alu_memory[0]);
$display("OPERATION ~& (Reduction nand): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd2: //Reduction or
begin
alu_result = (| alu_memory[0]);
$display("OPERATION | (Reduction or): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd3: //Reduction nor
begin
alu_result = (~| alu_memory[0]);
$display("OPERATION ~| (Reduction nor): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd4: //Reduction xor
begin
alu_result = (^ alu_memory[0]);
$display("OPERATION ^ (Reduction xor): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd5: //Reduction xnor (1st operator symbol)
begin
alu_result = (^~ alu_memory[0]);
$display("OPERATION ^~ (Reduction xnor (1st operator symbol)): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
'd6: //Reduction xnor (2nd operator symbol)
begin
alu_result = (~^ alu_memory[0]);
$display("OPERATION ~^ (Reduction xnor (2nd operator symbol)): alu_memory[0]=%b, alu_result=%b",
alu_memory[0], alu_result);
end
endcase
end
'd6: //Shift
begin
$display("Shift operator");
case(operator_symbol)
'd0: //Right shift
begin
alu_result = (alu_memory[0] >> alu_memory[1]);
$display("OPERATION >> (Right shift): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
'd1: //Left shift
begin
alu_result = (alu_memory[0] << alu_memory[1]);
$display("OPERATION << (Left shift): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd7: //Concatenation
begin
//$display("Concatenation operator");
case(operator_symbol)
'd0: //Concatenation
begin
alu_result = {alu_memory[0], alu_memory[1]};
$display("OPERATION {} (Concatenation): alu_memory[0]=%b, alu_memory[1]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_result);
end
endcase
end
'd8: //Replication
begin
$display("Replication operator");
case(operator_symbol)
'd0: //Replication
begin
alu_result = { 2 {alu_memory[0]} };
$display("OPERATION { { } } (Replication): alu_memory[0]=%b - replicated twice: alu_result=%b",
alu_memory[0], alu_result);
end
endcase
end
'd9: //Conditional
begin
$display("Conditional operator");
case(operator_symbol)
'd0: //Conditional
begin
alu_result = (alu_memory[0] ? alu_memory[1] : alu_memory[2]);
$display("OPERATION ?: (Conditional): alu_memory[0]=%b, alu_memory[1]=%b, alu_memory[2]=%b, alu_result=%b",
alu_memory[0], alu_memory[1], alu_memory[2], alu_result);
end
endcase
end
endcase
result_parity = ^alu_result; //Parity = XOR of all result's bits
end
end
 
always @ (posedge clk)
alu_stb_out = alu_stb_in;
 
endmodule
/trunk/tests/random_test.v
0,0 → 1,199
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//TEST MODULE - RANDOM TEST
 
module proj_random_test;
reg CLK, RES, STB;
reg [1:0] SEL;
reg[7:0] DATA_IN_0, DATA_IN_1, DATA_IN_2;
reg [3:0] OPERATOR_TYPE;
reg [2:0] OPERATOR_SYMBOL;
reg OUTPUT_CHANNEL;
reg DATA_VALID_IN;
 
wire VALID_0, VALID_1;
wire [15:0] OUT_0, OUT_1;
wire PARITY_0, PARITY_1;
 
parameter NO_OF_TRANSACTIONS = 10;
integer i;
 
DUT dut(.dut_clk(CLK), .dut_res(RES), .dut_stb(STB),
.dut_sel(SEL),
.dut_data_in_0(DATA_IN_0), .dut_data_in_1(DATA_IN_1), .dut_data_in_2(DATA_IN_2),
.dut_data_valid_in(DATA_VALID_IN),
.dut_valid_0(VALID_0), .dut_valid_1(VALID_1),
.dut_out_0(OUT_0), .dut_out_1(OUT_1),
.dut_parity_0(PARITY_0), .dut_parity_1(PARITY_1));
 
initial
begin
CLK = 0;
forever #5 CLK = ~CLK;
end
 
initial
begin
RES = 0; STB = 0;
SEL = 2'b00;
DATA_VALID_IN = 0;
DATA_IN_0 = 10'b0; DATA_IN_1 = 10'b0; DATA_IN_2 = 10'b0;
end
 
initial
begin
$monitor($time, " CLK = %b, RES = %b, STB = %b, SEL = %b, DATA_IN_0 = %b, DATA_IN_1 = %b, DATA_IN_2 = %b, VALID_0 = %b, VALID_1 = %b, OUT_0 = %b, OUT_1 = %b, PARITY_0 = %b, PARITY_1 = %b",
CLK, RES, STB, SEL, DATA_IN_0, DATA_IN_1, DATA_IN_2, VALID_0, VALID_1, OUT_0, OUT_1, PARITY_0, PARITY_1);
#20 RES = 1;
#20 RES = 0;
for(i = 0; i < NO_OF_TRANSACTIONS; i = i + 1)
begin
 
#30 STB = 1;
$display("Transaction no: %0d", i);
DATA_VALID_IN = 1;
SEL = {$random} % 3;
OPERATOR_TYPE = {$random} % 10;
case(OPERATOR_TYPE)
'd0: //Arithmetic
OPERATOR_SYMBOL = {$random} % 5;
'd1: //Logical
OPERATOR_SYMBOL = {$random} % 3;
'd2: //Relational
OPERATOR_SYMBOL = {$random} % 4;
'd3: //Equality
OPERATOR_SYMBOL = {$random} % 4;
'd4: //Bitwise
OPERATOR_SYMBOL = {$random} % 6;
'd5: //Reduction
OPERATOR_SYMBOL = {$random} % 7;
'd6: //Shift
OPERATOR_SYMBOL = {$random} % 2;
'd7: //Concatenation
OPERATOR_SYMBOL = {$random} % 1; //or OPERATOR_SYMBOL = 0;
'd8: //Replication
OPERATOR_SYMBOL = {$random} % 1; //or OPERATOR_SYMBOL = 0;
'd9: //Conditional
OPERATOR_SYMBOL = {$random} % 1; //or OPERATOR_SYMBOL = 0;
endcase
OUTPUT_CHANNEL = {$random} % 2;
 
case(SEL[1:0])
2'b00: DATA_IN_0 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
2'b01: DATA_IN_1 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
2'b10: DATA_IN_2 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
endcase
 
#10 STB = 0;
 
//if at least only one operand is required - there always exists at least one operand
case(SEL[1:0])
2'b00: DATA_IN_0 = $random;
2'b01: DATA_IN_1 = $random;
2'b10: DATA_IN_2 = $random;
endcase
 
//if at least two operands are required
if((OPERATOR_TYPE === 'd0) || //Arithmetic
((OPERATOR_TYPE === 'd1) && (OPERATOR_SYMBOL >= 'd1) && (OPERATOR_SYMBOL <= 'd2)) || //Logical
(OPERATOR_TYPE === 'd2) || //Relational
(OPERATOR_TYPE === 'd3) || //Equality
((OPERATOR_TYPE === 'd4) && (OPERATOR_SYMBOL >= 'd1) && (OPERATOR_SYMBOL <= 'd5)) || //Bitwise
(OPERATOR_TYPE === 'd6) || //Shift
(OPERATOR_TYPE === 'd7) || //Concatenation
(OPERATOR_TYPE === 'd9)) //Conditional
begin
#10
case(SEL[1:0])
2'b00: DATA_IN_0 = $random;
2'b01: DATA_IN_1 = $random;
2'b10: DATA_IN_2 = $random;
endcase
end
 
//if three operands are required
if(OPERATOR_TYPE === 'd9) //Conditional
begin
#10
case(SEL[1:0])
2'b00: DATA_IN_0 = $random;
2'b01: DATA_IN_1 = $random;
2'b10: DATA_IN_2 = $random;
endcase
end
 
#10 DATA_VALID_IN = 0;
 
end
#50 $finish;
end
 
initial
begin
 
$shm_open("../run/waves/waves_random_test"); // Open database named "waves"
$shm_probe(proj_random_test, "AS"); // Record tb scope and all sub hierarchy
//<or> $shm_probe(proj_random_test.top, "A"); // Record only those signals at proj_random_test.top scope
/*
After your simulation run, you would invoke the waveform viewer with "simwave waves" or "simvision waves"
and all the signals you asked to be recorded should be present. You don't need the NC gui at all.
*/
end
 
/*
//for waveform viewing with GTKWave
initial
begin
$dumpfile ("proj_random_test.dump") ;
$dumpvars;
$dumpon;
//$dumpall;
end
*/
 
endmodule
/trunk/tests/directed_test.v
0,0 → 1,264
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//TEST MODULE - DIRECTED TEST
 
module proj_directed_test;
reg CLK, RES, STB;
reg [1:0] SEL;
reg[7:0] DATA_IN_0, DATA_IN_1, DATA_IN_2;
reg [3:0] OPERATOR_TYPE;
reg [2:0] OPERATOR_SYMBOL;
reg OUTPUT_CHANNEL;
reg DATA_VALID_IN;
 
wire VALID_0, VALID_1;
wire [15:0] OUT_0, OUT_1;
wire PARITY_0, PARITY_1;
 
DUT dut(.dut_clk(CLK), .dut_res(RES), .dut_stb(STB),
.dut_sel(SEL),
.dut_data_in_0(DATA_IN_0), .dut_data_in_1(DATA_IN_1), .dut_data_in_2(DATA_IN_2),
.dut_data_valid_in(DATA_VALID_IN),
.dut_valid_0(VALID_0), .dut_valid_1(VALID_1),
.dut_out_0(OUT_0), .dut_out_1(OUT_1),
.dut_parity_0(PARITY_0), .dut_parity_1(PARITY_1));
 
initial
begin
CLK = 0;
forever #5 CLK = ~CLK;
end
 
initial
begin
RES = 0; STB = 0;
DATA_VALID_IN = 0;
DATA_IN_0 = 10'b0; DATA_IN_1 = 10'b0; DATA_IN_2 = 10'b0;
end
 
initial
begin
$monitor($time, " CLK = %b, RES = %b, STB = %b, SEL = %b, DATA_IN_0 = %b, DATA_IN_1 = %b, DATA_IN_2 = %b, VALID_0 = %b, VALID_1 = %b, OUT_0 = %b, OUT_1 = %b, PARITY_0 = %b, PARITY_1 = %b",
CLK, RES, STB, SEL, DATA_IN_0, DATA_IN_1, DATA_IN_2, VALID_0, VALID_1, OUT_0, OUT_1, PARITY_0, PARITY_1);
#20 RES = 1;
#20 RES = 0;
//1st transaction
#20 STB = 1;
SEL = 2'b01;
DATA_VALID_IN = 1;
$display("\n-------------1st transaction-------------");
$display("-------------SEL = Ch 1, OPERATOR_TYPE = Arithmetic, OPERATOR_SYMBOL = Multiply, OUTPUT_CHANNEL = Ch 0-------------\n");
OPERATOR_TYPE = 4'd0;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd0;
DATA_IN_1 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_1 = 8'd2;
#10 DATA_IN_1 = 8'd4;
#10 DATA_VALID_IN = 0;
//2nd transaction
#32 STB = 1;
DATA_VALID_IN = 1;
$display("-------------2nd transaction-------------");
$display("-------------SEL = Ch 1, OPERATOR_TYPE = Arithmetic, OPERATOR_SYMBOL = Divide, OUTPUT_CHANNEL = Ch 1-------------\n");
OPERATOR_TYPE = 4'd0;
OPERATOR_SYMBOL = 3'd1;
OUTPUT_CHANNEL = 1'd1;
DATA_IN_1 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_1 = 8'd18;
#10 DATA_IN_1 = 8'd9;
#10 DATA_VALID_IN = 0;
 
//3rd transaction
#30 STB = 1;
SEL = 2'd0;
DATA_VALID_IN = 1;
$display("-------------3rd transaction-------------");
$display("-------------SEL = Ch 0, OPERATOR_TYPE = Arithmetic, OPERATOR_SYMBOL = Add, OUTPUT_CHANNEL = Ch 0-------------\n");
OPERATOR_TYPE = 4'd0;
OPERATOR_SYMBOL = 3'd2;
OUTPUT_CHANNEL = 1'd0;
DATA_IN_0 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_0 = 8'd15;
#10 DATA_IN_0 = 8'd10;
#10 DATA_VALID_IN = 0;
//4th transaction
#40 STB = 1;
SEL = 2'd2;
DATA_VALID_IN = 1;
$display("-------------4th transaction-------------");
$display("-------------SEL = Ch 2, OPERATOR_TYPE = Logical, OPERATOR_SYMBOL = Logical negation, OUTPUT_CHANNEL = Ch 1-------------\n");
OPERATOR_TYPE = 4'd1;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd1;
DATA_IN_2 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_2 = 8'd35;
#10 DATA_VALID_IN = 0;
//5th transaction
#30 STB = 1;
SEL = 2'd2;
DATA_VALID_IN = 1;
$display("-------------5th transaction-------------");
$display("-------------SEL = Ch 2, OPERATOR_TYPE = Bitwise, OPERATOR_SYMBOL = Bitwise negation, OUTPUT_CHANNEL = Ch 1-------------\n");
OPERATOR_TYPE = 4'd4;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd1;
DATA_IN_2 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_2 = 8'd21;
#10 DATA_VALID_IN = 0;
//6th transaction
#30 STB = 1;
SEL = 2'd0;
DATA_VALID_IN = 1;
$display("-------------6th transaction-------------");
$display("-------------SEL = Ch 0, OPERATOR_TYPE = Shift, OPERATOR_SYMBOL = Right shift, OUTPUT_CHANNEL = Ch 0-------------\n");
OPERATOR_TYPE = 4'd6;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd0;
DATA_IN_0 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_0 = 8'd16;
#10 DATA_IN_0 = 8'd2;
#10 DATA_VALID_IN = 0;
//7th transaction
#50 STB = 1;
SEL = 2'd2;
DATA_VALID_IN = 1;
$display("-------------7th transaction-------------");
$display("-------------SEL = Ch 2, OPERATOR_TYPE = Concatenation, OPERATOR_SYMBOL = Concatenation, OUTPUT_CHANNEL = Ch 1-------------\n");
OPERATOR_TYPE = 4'd7;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd1;
DATA_IN_2 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_2 = 8'd1;
#10 DATA_IN_2 = 8'd3;
#10 DATA_VALID_IN = 0;
 
//8th transaction
#30 STB = 1;
SEL = 2'd1;
DATA_VALID_IN = 1;
$display("-------------8th transaction-------------");
$display("-------------SEL = Ch 1, OPERATOR_TYPE = Replication, OPERATOR_SYMBOL = Replication, OUTPUT_CHANNEL = Ch 0-------------\n");
OPERATOR_TYPE = 4'd8;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd0;
DATA_IN_1 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_1 = 8'd14;
#10 DATA_VALID_IN = 0;
 
//9th transaction
#30 STB = 1;
SEL = 2'd0;
DATA_VALID_IN = 1;
$display("-------------9th transaction-------------");
$display("-------------SEL = Ch 0, OPERATOR_TYPE = Conditional, OPERATOR_SYMBOL = Conditional, OUTPUT_CHANNEL = Ch 0-------------\n");
OPERATOR_TYPE = 4'd9;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd0;
DATA_IN_0 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_0 = 8'd0;
#10 DATA_IN_0 = 8'd2;
#10 DATA_IN_0 = 8'd3;
#10 DATA_VALID_IN = 0;
 
/*
//10th transaction - reserved values: circuit behaviour is impredictible, reserved values must not be used
#40 STB = 1;
SEL = 2'd3;
DATA_VALID_IN = 1;
$display("\n-------------10th transaction - reserved values for SEL -------------");
$display("-------------SEL = Reserved ('d4), OPERATOR_TYPE = Reserved('d10), OPERATOR_SYMBOL = Reserved ('d0), OUTPUT_CHANNEL = Ch 0-------------\n");
OPERATOR_TYPE = 4'd10;
OPERATOR_SYMBOL = 3'd0;
OUTPUT_CHANNEL = 1'd0;
DATA_IN_0 = {OPERATOR_TYPE, OPERATOR_SYMBOL, OUTPUT_CHANNEL};
#10 STB = 0;
DATA_IN_0 = 8'hCC;
DATA_IN_1 = 8'hCC;
DATA_IN_2 = 8'hCC;
#10 DATA_VALID_IN = 0;
*/
#50 $finish;
end
 
initial
begin
 
$shm_open("../run/waves/waves_directed_test"); // Open database named "waves"
$shm_probe(proj_directed_test, "AS"); // Record tb scope and all sub hierarchy
//<or> $shm_probe(proj_directed_test.top, "A"); // Record only those signals at proj1_test.top scope
/*
After your simulation run, you would invoke the waveform viewer with "simwave waves" or "simvision waves"
and all the signals you asked to be recorded should be present. You don't need the NC gui at all.
*/
end
 
/*
//for waveform viewing - ICARUS VERILOG and GTKWave
initial
begin
$dumpfile ("proj_directed_test.dump") ;
$dumpvars;
$dumpon;
//$dumpall;
end
*/
 
endmodule
/trunk/tests/improved_test.v
0,0 → 1,149
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//TEST MODULE - IMPROVED TEST
 
module proj_improved_test;
 
wire test_clk, test_res, test_stb;
wire [1:0] test_sel;
wire [7:0] test_data_in_0, test_data_in_1, test_data_in_2;
wire test_data_valid_in;
wire test_valid_0, test_valid_1;
wire [15:0] test_out_0, test_out_1;
wire test_parity_0, test_parity_1;
wire [7:0] test_ic_data_0, test_ic_data_1, test_ic_data_2, test_ic_data_3;
wire [15:0] test_oc_data;
wire test_oc_parity;
wire [0:127] test_ic_data_collected, test_oc_data_collected;
 
//DUT instantiation
DUT dut(.dut_clk(test_clk), .dut_res(test_res), .dut_stb(test_stb),
.dut_sel(test_sel),
.dut_data_in_0(test_data_in_0), .dut_data_in_1(test_data_in_1), .dut_data_in_2(test_data_in_2),
.dut_data_valid_in(test_data_valid_in),
.dut_valid_0(test_valid_0), .dut_valid_1(test_valid_1),
.dut_out_0(test_out_0), .dut_out_1(test_out_1),
.dut_parity_0(test_parity_0), .dut_parity_1(test_parity_1));
 
//DUT VERIFICATION ENVIRONMENT
//Contains CLK generator, monitors, BFMs, collectors and the checker
//They are instantiated here, in the test module
 
//--------BFMs' instantiations--------
CLK_GEN clk_gen(.gen_clk(test_clk));
 
RES_BFM res_bfm(.bfm_res(test_res));
 
DATA_IN_BFM data_in_bfm(.bfm_stb(test_stb),
.bfm_sel(test_sel),
.bfm_data_in_0(test_data_in_0), .bfm_data_in_1(test_data_in_1), .bfm_data_in_2(test_data_in_2),
.bfm_data_valid_in(test_data_valid_in));
 
//--------Monitors' instantiations--------
CLK_MONITOR clk_monitor(.m_clk(test_clk));
 
RES_MONITOR res_monitor(.m_res(test_res));
 
STB_MONITOR stb_monitor(.m_clk(test_clk), .m_stb(test_stb));
 
SEL_MONITOR sel_monitor(.m_clk(test_clk), .m_stb(test_stb), .m_sel(test_sel));
 
DATA_IN_MONITOR data_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
.m_data_in_0(test_data_in_0), .m_data_in_1(test_data_in_1), .m_data_in_2(test_data_in_2));
 
DATA_VALID_IN_MONITOR data_valid_in_monitor(.m_clk(test_clk), .m_stb(test_stb),
.m_data_valid_in(test_data_valid_in));
 
VALID_MONITOR valid_monitor(.m_clk(test_clk), .m_res(test_res),
.m_valid_0(test_valid_0), .m_valid_1(test_valid_1));
 
DATA_OUT_MONITOR data_out_monitor(.m_clk(test_clk), .m_res(test_res),
.m_out_0(test_out_0), .m_out_1(test_out_1));
 
PARITY_MONITOR parity_monitor(.m_clk(test_clk), .m_res(test_res),
.m_parity_0(test_parity_0), .m_parity_1(test_parity_1));
 
//--------Collectors' instantiations--------
INPUT_COLLECTOR input_collector(.ic_clk(test_clk), .ic_res(test_res), .ic_stb(test_stb),
.ic_sel(test_sel),
.ic_data_in_0(test_data_in_0), .ic_data_in_1(test_data_in_1), .ic_data_in_2(test_data_in_2),
.ic_data_valid_in(test_data_valid_in),
.ic_data_out_0(test_ic_data_0), .ic_data_out_1(test_ic_data_1), .ic_data_out_2(test_ic_data_2), .ic_data_out_3(test_ic_data_3),
.ic_data_collected(test_ic_data_collected));
 
OUTPUT_COLLECTOR output_collector(.oc_clk(test_clk), .oc_res(test_res),
.oc_valid_0(test_valid_0), .oc_valid_1(test_valid_1),
.oc_out_0(test_out_0), .oc_out_1(test_out_1),
.oc_parity_0(test_parity_0), .oc_parity_1(test_parity_1),
.oc_data(test_oc_data),
.oc_parity(test_oc_parity),
.oc_data_collected(test_oc_data_collected));
 
//--------Checker's instantiation--------
CHECKER checker(.c_clk(test_clk), .c_res(test_res),
.ic_data_0(test_ic_data_0), .ic_data_1(test_ic_data_1), .ic_data_2(test_ic_data_2), .ic_data_3(test_ic_data_3),
.oc_data(test_oc_data),
.oc_parity(test_oc_parity),
.ic_data_collected(test_ic_data_collected),
.oc_data_collected(test_oc_data_collected));
 
//Waveform database
initial
begin
 
$shm_open("../run/waves/waves_improved_test"); // Open database named "waves"
$shm_probe(proj_improved_test, "AS"); // Record tb scope and all sub hierarchy
end
 
/*
//for waveform viewing with GTKWave
initial
begin
$dumpfile ("proj0.dump") ;
$dumpvars;
$dumpon;
//$dumpall;
end
*/
 
endmodule
/trunk/verif_env/checker/checker.v
0,0 → 1,387
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//CHECKER
 
module CHECKER(c_clk, c_res,
ic_data_0, ic_data_1, ic_data_2, ic_data_3,
oc_data,
oc_parity,
ic_data_collected,
oc_data_collected);
 
input c_clk, c_res;
input [7:0] ic_data_0, ic_data_1, ic_data_2, ic_data_3;
input [15:0] oc_data;
input oc_parity;
input [0:127] ic_data_collected, oc_data_collected;
 
integer i, j;
 
reg [15:0] checker_result;
reg checker_result_parity;
reg [3:0] checker_operator_type;
reg [2:0] checker_operator_symbol;
 
integer fh;
 
always @ (posedge c_clk or posedge c_res)
if(c_res)
begin
i = 0;
j = 0;
checker_result = 16'b0;
checker_result_parity = 1'b0;
checker_operator_type = 4'b1111;
checker_operator_symbol = 3'b111;
end
 
always @ (ic_data_collected[i])
if(ic_data_collected[i])
begin
#1
if(fh === 32'bx)
fh = $fopen("checker.out");
 
$fdisplay(fh, "%0d INFO: Collected IN transaction no %0d: ic_data_0 = %b, ic_data_1 = %b, ic_data_2 = %b, ic_data_3 = %b",
$time, i, ic_data_0, ic_data_1, ic_data_2, ic_data_3);
 
//calculate checker's alu result
checker_operator_type = ic_data_0[7:4];
checker_operator_symbol = ic_data_0[3:1];
 
case (checker_operator_type)
'd0: //Arithmetic
begin
$fdisplay(fh, "Arithmetic operator");
case(checker_operator_symbol)
'd0: //Multiply
begin
checker_result = (ic_data_1 * ic_data_2);
$fdisplay(fh, "OPERATION * (Multiply): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd1: //Divide
begin
checker_result = (ic_data_1 / ic_data_2);
$fdisplay(fh, "OPERATION / (Divide): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd2: //Add
begin
checker_result = (ic_data_1 + ic_data_2);
$fdisplay(fh, "OPERATION + (Add): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd3: //Substract
begin
checker_result = (ic_data_1 - ic_data_2);
$fdisplay(fh, "OPERATION - (Substract): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd4: //Modulus
begin
checker_result = (ic_data_1 % ic_data_2);
$fdisplay(fh, "OPERATION (Modulus): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
endcase
end
'd1: //Logical
begin
$fdisplay(fh, "Logical operator");
case(checker_operator_symbol)
'd0: //Logical negation
begin
checker_result = (!ic_data_1);
$fdisplay(fh, "OPERATION ! (Logical negation): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd1: //Logical and
begin
checker_result = (ic_data_1 && ic_data_2);
$fdisplay(fh, "OPERATION && (Logical and): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd2: //Logical or
begin
checker_result = (ic_data_1 || ic_data_2);
$fdisplay(fh, "OPERATION || (Logical or): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
endcase
end
'd2: //Relational
begin
$fdisplay(fh, "Relational operator");
case(checker_operator_symbol)
'd0: //Greater than
begin
checker_result = (ic_data_1 > ic_data_2);
$fdisplay(fh, "OPERATION > (Greater than): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd1: //Less than
begin
checker_result = (ic_data_1 < ic_data_2);
$fdisplay(fh, "OPERATION < (Less than): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd2: //Greater than or equal
begin
checker_result = (ic_data_1 >= ic_data_2);
$fdisplay(fh, "OPERATION >= (Greater than or equal): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd3: //Less than or equal
begin
checker_result = (ic_data_1 <= ic_data_2);
$fdisplay(fh, "OPERATION <= (Less than or equal): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
endcase
end
'd3: //Equality
begin
$fdisplay(fh, "Equality operator");
case(checker_operator_symbol)
'd0: //Equality
begin
checker_result = (ic_data_1 == ic_data_2);
$fdisplay(fh, "OPERATION == (Equality): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd1: //Inequality
begin
checker_result = (ic_data_1 != ic_data_2);
$fdisplay(fh, "OPERATION != (Inequality): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd2: //Case equality
begin
checker_result = (ic_data_1 === ic_data_2);
$fdisplay(fh, "OPERATION === (Case equality): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd3: //Case inequality
begin
checker_result = (ic_data_1 !== ic_data_2);
$fdisplay(fh, "OPERATION !== (Case inequality): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
endcase
end
'd4: //Bitwise
begin
$fdisplay(fh, "Bitwise operator");
case(checker_operator_symbol)
'd0: //Bitwise negation
begin
checker_result = (~ ic_data_1);
$fdisplay(fh, "OPERATION ~ (Bitwise negation): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd1: //Bitwise and
begin
checker_result = (ic_data_1 & ic_data_2);
$fdisplay(fh, "OPERATION & (Bitwise and): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd2: //Bitwise or
begin
checker_result = (ic_data_1 | ic_data_2);
$fdisplay(fh, "OPERATION | (Bitwise or): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd3: //Bitwise xor
begin
checker_result = (ic_data_1 ^ ic_data_2);
$fdisplay(fh, "OPERATION ^ (Bitwise xor): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd4: //Bitwise xnor (1st operator symbol)
begin
checker_result = (ic_data_1 ^~ ic_data_2);
$fdisplay(fh, "OPERATION ^~ (Bitwise xnor (1st operator symbol)): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd5: //Bitwise xnor (2nd operator symbol)
begin
checker_result = (ic_data_1 ~^ ic_data_2);
$fdisplay(fh, "OPERATION ~^ (Bitwise xnor (2nd operator symbol)): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
endcase
end
'd5: //Reduction
begin
$fdisplay(fh, "Reduction operator");
case(checker_operator_symbol)
'd0: //Reduction and
begin
checker_result = (& ic_data_1);
$fdisplay(fh, "OPERATION & (Reduction and): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd1: //Reduction nand
begin
checker_result = (~& ic_data_1);
$fdisplay(fh, "OPERATION ~& (Reduction nand): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd2: //Reduction or
begin
checker_result = (| ic_data_1);
$fdisplay(fh, "OPERATION | (Reduction or): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd3: //Reduction nor
begin
checker_result = (~| ic_data_1);
$fdisplay(fh, "OPERATION ~| (Reduction nor): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd4: //Reduction xor
begin
checker_result = (^ ic_data_1);
$fdisplay(fh, "OPERATION ^ (Reduction xor): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd5: //Reduction xnor (1st operator symbol)
begin
checker_result = (^~ ic_data_1);
$fdisplay(fh, "OPERATION ^~ (Reduction xnor (1st operator symbol)): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
'd6: //Reduction xnor (2nd operator symbol)
begin
checker_result = (~^ ic_data_1);
$fdisplay(fh, "OPERATION ~^ (Reduction xnor (2nd operator symbol)): ic_data_1 = %b, checker_result = %b",
ic_data_1, checker_result);
end
endcase
end
'd6: //Shift
begin
$fdisplay(fh, "Shift operator");
case(checker_operator_symbol)
'd0: //Right shift
begin
checker_result = (ic_data_1 >> ic_data_2);
$fdisplay(fh, "OPERATION >> (Right shift): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
'd1: //Left shift
begin
checker_result = (ic_data_1 << ic_data_2);
$fdisplay(fh, "OPERATION << (Left shift): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
endcase
end
'd7: //Concatenation
begin
$fdisplay(fh, "Concatenation operator");
case(checker_operator_symbol)
'd0: //Concatenation
begin
checker_result = {ic_data_1, ic_data_2};
$fdisplay(fh, "OPERATION {} (Concatenation): ic_data_1 = %b, ic_data_2 = %b, checker_result = %b",
ic_data_1, ic_data_2, checker_result);
end
endcase
end
'd8: //Replication
begin
$fdisplay(fh, "Replication operator");
case(checker_operator_symbol)
'd0: //Replication
begin
checker_result = { 2 {ic_data_1} };
$fdisplay(fh, "OPERATION { { } } (Replication): ic_data_1 = %b - replicated twice: checker_result = %b",
ic_data_1, checker_result);
end
endcase
end
'd9: //Conditional
begin
$fdisplay(fh, "Conditional operator");
case(checker_operator_symbol)
'd0: //Conditional
begin
checker_result = (ic_data_1 ? ic_data_2 : ic_data_3);
$fdisplay(fh, "OPERATION ?: (Conditional): ic_data_1 = %b, ic_data_2 = %b, ic_data_3=%b, checker_result = %b",
ic_data_1, ic_data_2, ic_data_3, checker_result);
end
endcase
end
endcase
checker_result_parity = ^checker_result; //Parity = XOR of all result's bits
i = i + 1;
//$fclose(fh);
end
 
always @ (oc_data_collected[j])
begin
if(oc_data_collected[j])
begin
$fdisplay(fh, "%0d INFO: Collected OUT transaction no %0d: %b", $time, j, oc_data);
//checker result
if(checker_result[15:0] === oc_data[15:0])
$fdisplay(fh, "%0d INFO: Calculus of data for transaction no. %0d match! (%b - %b)",
$time, j, checker_result[15:0], oc_data[15:0]);
else
$fdisplay(fh, "%0d ERROR: Calculus of data for transaction no. %0d DO NOT match! (%b - %b)",
$time, j, checker_result[15:0], oc_data[15:0]);
//checker parity
if(checker_result_parity === oc_parity)
$fdisplay(fh, "%0d INFO: Calculus of parity for transaction no. %0d match! (%b - %b)\n",
$time, j, checker_result_parity, oc_parity);
else
$fdisplay(fh, "%0d ERROR: Calculus of parity for transaction no. %0d DO NOT match! (%b - %b)\n",
$time, j, checker_result_parity, oc_parity);
j = j + 1;
end
end
 
endmodule
/trunk/verif_env/bfms/res_bfm.v
0,0 → 1,69
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------BFMs----------------
 
//RESET BFM
 
module RES_BFM(bfm_res);
output bfm_res;
 
reg bfm_res;
 
integer fh;
 
initial
begin
fh = $fopen("res_bfm.out");
 
$fmonitor(fh, "%0d INFO: bfm_res = %0b", $time, bfm_res);
bfm_res = 0;
#20 bfm_res = 1;
#20 bfm_res = 0;
#1
$fclose(fh);
end
 
endmodule
/trunk/verif_env/bfms/clk_gen.v
0,0 → 1,65
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------BFMs----------------
 
//CLK GENERATOR
 
module CLK_GEN(gen_clk);
output gen_clk;
 
reg gen_clk;
 
integer fh;
 
initial
begin
fh = $fopen("clk_gen.out");
 
$fdisplay(fh, "%0d INFO: Toggling CLK every 5 simulation seconds...", $time);
$fclose(fh);
gen_clk = 0;
forever #5 gen_clk = ~gen_clk;
end
 
endmodule
/trunk/verif_env/bfms/data_in_bfm.v
0,0 → 1,170
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------BFMs----------------
 
//DATA_IN BFM
 
module DATA_IN_BFM(bfm_stb, bfm_sel, bfm_data_in_0, bfm_data_in_1, bfm_data_in_2, bfm_data_valid_in);
output bfm_stb;
output [1:0] bfm_sel;
output [7:0] bfm_data_in_0, bfm_data_in_1, bfm_data_in_2;
output bfm_data_valid_in;
 
reg bfm_stb;
reg [1:0] bfm_sel;
reg[7:0] bfm_data_in_0, bfm_data_in_1, bfm_data_in_2;
reg bfm_data_valid_in;
 
reg [3:0] bfm_operator_type;
reg [2:0] bfm_operator_symbol;
reg bfm_output_channel;
 
parameter NO_OF_TRANSACTIONS = 10;
integer i;
 
integer fh;
 
initial
begin
fh = $fopen("data_in_bfm.out");
 
$fmonitor(fh, "%0d INFO: bfm_stb=%b, bfm_sel=%b, bfm_data_in_0=%b, bfm_data_in_1=%b, bfm_data_in_2=%b",
$time, bfm_stb, bfm_sel, bfm_data_in_0, bfm_data_in_1, bfm_data_in_2);
bfm_stb = 0;
bfm_sel = 2'b00;
bfm_data_valid_in = 0;
bfm_data_in_0 = 10'b0;
bfm_data_in_1 = 10'b0;
bfm_data_in_2 = 10'b0;
#50
 
for(i=0; i<NO_OF_TRANSACTIONS; i=i+1)
begin
 
#30 bfm_stb = 1;
$display("Transaction no: %0d", i);
bfm_data_valid_in = 1;
bfm_sel = {$random} % 3;
bfm_operator_type = {$random} % 10;
case(bfm_operator_type)
'd0: //Arithmetic
bfm_operator_symbol = {$random} % 5;
'd1: //Logical
bfm_operator_symbol = {$random} % 3;
'd2: //Relational
bfm_operator_symbol = {$random} % 4;
'd3: //Equality
bfm_operator_symbol = {$random} % 4;
'd4: //Bitwise
bfm_operator_symbol = {$random} % 6;
'd5: //Reduction
bfm_operator_symbol = {$random} % 7;
'd6: //Shift
bfm_operator_symbol = {$random} % 2;
'd7: //Concatenation
bfm_operator_symbol = {$random} % 1; //or bfm_operator_symbol = 0;
'd8: //Replication
bfm_operator_symbol = {$random} % 1; //or bfm_operator_symbol = 0;
'd9: //Conditional
bfm_operator_symbol = {$random} % 1; //or bfm_operator_symbol = 0;
endcase
bfm_output_channel = {$random} % 2;
 
case(bfm_sel[1:0])
2'b00: bfm_data_in_0 = {bfm_operator_type, bfm_operator_symbol, bfm_output_channel};
2'b01: bfm_data_in_1 = {bfm_operator_type, bfm_operator_symbol, bfm_output_channel};
2'b10: bfm_data_in_2 = {bfm_operator_type, bfm_operator_symbol, bfm_output_channel};
endcase
 
#10 bfm_stb = 0;
 
//if at least only one operand is required - there always exists at least one operand
case(bfm_sel[1:0])
2'b00: bfm_data_in_0 = $random;
2'b01: bfm_data_in_1 = $random;
2'b10: bfm_data_in_2 = $random;
endcase
 
//if at least two operands are required
if((bfm_operator_type === 'd0) || //Arithmetic
((bfm_operator_type === 'd1) && (bfm_operator_symbol >= 'd1) && (bfm_operator_symbol <= 'd2)) || //Logical
(bfm_operator_type === 'd2) || //Relational
(bfm_operator_type === 'd3) || //Equality
((bfm_operator_type === 'd4) && (bfm_operator_symbol >= 'd1) && (bfm_operator_symbol <= 'd5)) || //Bitwise
(bfm_operator_type === 'd6) || //Shift
(bfm_operator_type === 'd7) || //Concatenation
(bfm_operator_type === 'd9)) //Conditional
begin
#10
case(bfm_sel[1:0])
2'b00: bfm_data_in_0 = $random;
2'b01: bfm_data_in_1 = $random;
2'b10: bfm_data_in_2 = $random;
endcase
end
 
//if three operands are required
if(bfm_operator_type === 'd9) //Conditional
begin
#10
case(bfm_sel[1:0])
2'b00: bfm_data_in_0 = $random;
2'b01: bfm_data_in_1 = $random;
2'b10: bfm_data_in_2 = $random;
endcase
end
 
#10 bfm_data_valid_in = 0;
 
end
#100
$fclose(fh);
 
$finish;
end
 
endmodule
/trunk/verif_env/collectors/input_collector.v
0,0 → 1,141
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Collectors----------------
 
//INPUT COLLECTOR
 
module INPUT_COLLECTOR(ic_clk, ic_res, ic_stb,
ic_sel,
ic_data_in_0, ic_data_in_1, ic_data_in_2,
ic_data_valid_in,
ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3,
ic_data_collected);
 
input ic_clk, ic_res, ic_stb;
input [1:0] ic_sel;
input [7:0] ic_data_in_0, ic_data_in_1, ic_data_in_2;
input ic_data_valid_in;
output [7:0] ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3;
output [0:127] ic_data_collected;
 
reg ic_stb_was_1;
 
reg [7:0] ic_data_out_0, ic_data_out_1, ic_data_out_2, ic_data_out_3;
reg [0:127] ic_data_collected;
 
reg [7:0] ic_data[0:3];
integer i, j, k;
 
integer fh;
 
always @ (posedge ic_clk or posedge ic_res)
if(ic_res)
begin
ic_stb_was_1 = 0;
ic_data_out_0 = 0;
ic_data_out_1 = 0;
ic_data_out_2 = 0;
ic_data_out_3 = 0;
ic_data_collected = 0;
for(j = 0; j < 4; j = j + 1)
ic_data[j] = 0;
i = 0;
j = 0;
k = 0;
end
else
begin
if(ic_stb)
ic_stb_was_1 = 1;
if(ic_data_valid_in)
begin
case(ic_sel)
'd0: ic_data[k] = ic_data_in_0;
'd1: ic_data[k] = ic_data_in_1;
'd2: ic_data[k] = ic_data_in_2;
endcase
k = k + 1;
end
else
begin
if(ic_stb_was_1)
begin
k = 0;
for(j = 0; j < 4; j = j + 1)
case(j)
'd0: ic_data_out_0 = ic_data[j];
'd1: ic_data_out_1 = ic_data[j];
'd2: ic_data_out_2 = ic_data[j];
'd3: ic_data_out_3 = ic_data[j];
endcase
end
if(ic_stb_was_1)
begin
ic_data_collected[i] = 1;
i = i + 1;
ic_stb_was_1 = 0;
end
end
end
 
//Print INPUT COLLECTOR buffer contents
always @ (i)
begin
if(fh === 32'bx)
fh = $fopen("input_collector.out");
 
$fdisplay(fh, "%0d INFO: Input Transaction no: %0d", $time, i);
$fdisplay(fh, "%0d INFO: ic_data_out_0 = %b", $time, ic_data_out_0);
// split ic_data_out_0
$fdisplay(fh, "\tINFO: operator type = %0d", ic_data_out_0[7:4]);
$fdisplay(fh, "\tINFO: operator symbol = %0d", ic_data_out_0[3:1]);
$fdisplay(fh, "\tINFO: output channel = %0d", ic_data_out_0[0]);
//
$fdisplay(fh, "%0d INFO: ic_data_out_1 = %b", $time, ic_data_out_1);
$fdisplay(fh, "%0d INFO: ic_data_out_2 = %b", $time, ic_data_out_2);
$fdisplay(fh, "%0d INFO: ic_data_out_3 = %b\n", $time, ic_data_out_3);
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/collectors/output_collector.v
0,0 → 1,109
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Collectors----------------
 
//OUTPUT COLLECTOR
 
module OUTPUT_COLLECTOR(oc_clk, oc_res,
oc_valid_0, oc_valid_1,
oc_out_0, oc_out_1,
oc_parity_0, oc_parity_1,
oc_data,
oc_parity,
oc_data_collected);
 
input oc_clk, oc_res;
input oc_valid_0, oc_valid_1;
input [15:0] oc_out_0, oc_out_1;
input oc_parity_0, oc_parity_1;
output [15:0] oc_data;
output oc_parity;
output [0:127] oc_data_collected;
 
reg [15:0] oc_data;
reg oc_parity;
reg [0:127] oc_data_collected;
 
integer i;
integer fh;
 
always @ (posedge oc_clk or posedge oc_res)
if(oc_res)
begin
i = 0;
oc_data = 0;
oc_parity = 0;
oc_data_collected = 0;
end
else
begin
if(oc_valid_0)
begin
oc_data = oc_out_0;
oc_parity = oc_parity_0;
oc_data_collected[i] = 1;
i = i + 1;
end
if(oc_valid_1)
begin
oc_data = oc_out_1;
oc_parity = oc_parity_1;
oc_data_collected[i] = 1;
i = i + 1;
end
end
 
//Print OUTPUT COLLECTOR buffer contents
always @ (i)
begin
if(fh === 32'bx)
fh = $fopen("output_collector.out");
 
$fdisplay(fh, "%0d INFO: Output Transaction no: %0d", $time, i);
$fdisplay(fh, "%0d INFO: oc_data = %b", $time, oc_data);
$fdisplay(fh, "%0d INFO: oc_parity = %b\n", $time, oc_parity);
 
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/parity_monitor.v
0,0 → 1,75
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//PARITY MONITOR
 
module PARITY_MONITOR(m_clk, m_res, m_parity_0, m_parity_1);
input m_clk, m_res;
input m_parity_0, m_parity_1;
 
reg res_was_active;
 
integer fh0, fh1;
 
always @ (posedge m_clk)
if(m_res)
res_was_active = 1;
else
if(res_was_active)
begin
if(fh0 === 32'bx)
fh0 = $fopen("parity_0_monitor.out");
if(fh1 === 32'bx)
fh1 = $fopen("parity_1_monitor.out");
if ((m_parity_0 === 1'bx) || (m_parity_0 === 1'bz))
$fdisplay(fh0, "%0d ERROR: PARITY_0 doesn't have a valid value (%b)", $time, m_parity_0);
if ((m_parity_1 === 1'bx) || (m_parity_1 === 1'bz))
$fdisplay(fh1, " ERROR: PARITY_1 doesn't have a valid value (%b)", $time, m_parity_1);
//$fclose(fh0);
//$fclose(fh1);
end
 
endmodule
/trunk/verif_env/monitors/stb_monitor.v
0,0 → 1,64
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//STB MONITOR
 
module STB_MONITOR(m_clk, m_stb);
input m_clk;
input m_stb;
 
integer fh;
 
always @ (posedge m_clk)
begin
if(fh === 32'bx)
fh = $fopen("stb_monitor.out");
if ((m_stb === 1'bx) || (m_stb === 1'bz))
$fdisplay(fh, "%0d ERROR: STB doesn't have a valid value (%b)", $time, m_stb);
 
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/clk_monitor.v
0,0 → 1,64
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//CLK MONITOR
 
module CLK_MONITOR(m_clk);
input m_clk;
 
integer fh;
 
always
begin
#5
if(fh === 32'bx)
fh = $fopen("clk_monitor.out");
 
if ((m_clk === 1'bx) || (m_clk === 1'bz))
$fdisplay(fh, "%0d ERROR: CLK doesn't have a valid value (%b)", $time, m_clk);
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/res_monitor.v
0,0 → 1,64
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//RES MONITOR
 
module RES_MONITOR(m_res);
input m_res;
 
integer fh;
 
always
begin
#5
if(fh === 32'bx)
fh = $fopen("res_monitor.out");
if ((m_res === 1'bx) || (m_res === 1'bz))
$fdisplay(fh, "%0d ERROR: RES doesn't have a valid value (%b)", $time, m_res);
 
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/data_valid_in_monitor.v
0,0 → 1,65
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//DATA_VALID_IN MONITOR
 
module DATA_VALID_IN_MONITOR(m_clk, m_stb, m_data_valid_in);
input m_clk, m_stb;
input m_data_valid_in;
 
integer fh;
 
always @ (posedge m_clk)
if(m_stb)
begin
if(fh === 32'bx)
fh = $fopen("data_valid_in_monitor.out");
if ((m_data_valid_in === 1'bx) || (m_data_valid_in === 1'bz))
$fdisplay(fh, "%0d ERROR: DATA_VALID_IN doesn't have a valid value (%b)", $time, m_data_valid_in);
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/data_in_monitor.v
0,0 → 1,74
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//DATA_IN MONITOR
 
module DATA_IN_MONITOR(m_clk, m_stb, m_data_in_0, m_data_in_1, m_data_in_2);
input m_clk, m_stb;
input [7:0] m_data_in_0, m_data_in_1, m_data_in_2;
 
integer i;
 
integer fh;
 
always @ (posedge m_clk)
if(m_stb)
begin
if(fh === 32'bx)
fh = $fopen("data_in_monitor.out");
 
for (i = 0; i < 8; i = i + 1)
begin
if ((m_data_in_0[i] === 1'bx) || (m_data_in_0[i] === 1'bz))
$fdisplay(fh, "%0d ERROR: DATA_IN_0[%0d] doesn't have a valid value (%b)", $time, i, m_data_in_0[i]);
if ((m_data_in_1[i] === 1'bx) || (m_data_in_1[i] === 1'bz))
$fdisplay(fh, "%0d ERROR: DATA_IN_1[%0d] doesn't have a valid value (%b)", $time, i, m_data_in_1[i]);
if ((m_data_in_2[i] === 1'bx) || (m_data_in_2[i] === 1'bz))
$fdisplay(fh, "%0d ERROR: DATA_IN_2[%0d] doesn't have a valid value (%b)", $time, i, m_data_in_2[i]);
end
 
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/valid_monitor.v
0,0 → 1,72
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//VALID MONITOR
 
module VALID_MONITOR(m_clk, m_res, m_valid_0, m_valid_1);
input m_clk, m_res;
input m_valid_0, m_valid_1;
 
reg res_was_active;
 
integer fh;
 
always @ (posedge m_clk)
if(m_res)
res_was_active = 1;
else
if(res_was_active)
begin
if(fh === 32'bx)
fh = $fopen("valid_monitor.out");
if ((m_valid_0 === 1'bx) || (m_valid_0 === 1'bz))
$fdisplay(fh, "%0d ERROR: VALID_0 doesn't have a valid value (%b)", $time, m_valid_0);
if ((m_valid_1 === 1'bx) || (m_valid_1 === 1'bz))
$fdisplay(fh, "%0d ERROR: VALID_1 doesn't have a valid value (%b)", $time, m_valid_1);
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/data_out_monitor.v
0,0 → 1,76
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//DATA_OUT MONITOR
 
module DATA_OUT_MONITOR(m_clk, m_res, m_out_0, m_out_1);
input m_clk, m_res;
input [15:0] m_out_0, m_out_1;
 
reg res_was_active;
integer i;
 
integer fh;
 
always @ (posedge m_clk)
if(m_res)
res_was_active = 1;
else
if(res_was_active)
begin
if(fh === 32'bx)
fh = $fopen("data_out_monitor.out");
for (i = 0; i < 16; i = i + 1)
begin
if ((m_out_0[i] === 1'bx) || (m_out_0[i] === 1'bz))
$fdisplay(fh, "%0d ERROR: OUT_0[%0d] doesn't have a valid value (%b)", $time, i, m_out_0[i]);
if ((m_out_1[i] === 1'bx) || (m_out_1[i] === 1'bz))
$fdisplay(fh, "%0d ERROR: OUT_1[%0d] doesn't have a valid value (%b)", $time, i, m_out_1[i]);
end
//$fclose(fh);
end
 
endmodule
/trunk/verif_env/monitors/sel_monitor.v
0,0 → 1,70
/////////////////////////////////////////////////////////////////////
//// ////
//// This project has been provided to you on behalf of: ////
//// ////
//// S.C. ASICArt S.R.L. ////
//// www.asicart.com ////
//// eli_f@asicart.com ////
//// ////
//// Author: Dragos Constantin Doncean ////
//// Email: doncean@asicart.com ////
//// Mobile: +40-740-936997 ////
//// ////
//// Downloaded from: http://www.opencores.org/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2007 Dragos Constantin Doncean ////
//// www.asicart.com ////
//// doncean@asicart.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
 
//----------------Monitors----------------
 
//SEL MONITOR
 
module SEL_MONITOR(m_clk, m_stb, m_sel);
input m_clk, m_stb;
input [1:0] m_sel;
 
integer i;
 
integer fh;
 
always @ (posedge m_clk)
if(m_stb)
begin
if(fh === 32'bx)
fh = $fopen("sel_monitor.out");
if(m_sel === 2'b11)
$fdisplay(fh, "%0d ERROR: SEL = reserved value (%b)", $time, m_sel);
for (i = 0; i < 2; i = i + 1)
if ((m_sel[i] === 1'bx) || (m_sel[i] === 1'bz))
$fdisplay(fh, "%0d ERROR: SEL[%0d] doesn't have a valid value (%b)", $time, i, m_sel[i]);
//$fclose(fh);
end
 
endmodule
/trunk/run/res_bfm.out
0,0 → 1,3
0 INFO: bfm_res = 0
20 INFO: bfm_res = 1
40 INFO: bfm_res = 0
/trunk/run/clk_monitor.out --- trunk/run/data_in_bfm.out (nonexistent) +++ trunk/run/data_in_bfm.out (revision 2) @@ -0,0 +1,29 @@ +0 INFO: bfm_stb=0, bfm_sel=00, bfm_data_in_0=00000000, bfm_data_in_1=00000000, bfm_data_in_2=00000000 +80 INFO: bfm_stb=1, bfm_sel=10, bfm_data_in_0=00000000, bfm_data_in_1=00000000, bfm_data_in_2=01110001 +90 INFO: bfm_stb=0, bfm_sel=10, bfm_data_in_0=00000000, bfm_data_in_1=00000000, bfm_data_in_2=00001101 +100 INFO: bfm_stb=0, bfm_sel=10, bfm_data_in_0=00000000, bfm_data_in_1=00000000, bfm_data_in_2=10001101 +140 INFO: bfm_stb=1, bfm_sel=10, bfm_data_in_0=00000000, bfm_data_in_1=00000000, bfm_data_in_2=00100011 +150 INFO: bfm_stb=0, bfm_sel=10, bfm_data_in_0=00000000, bfm_data_in_1=00000000, bfm_data_in_2=01110110 +160 INFO: bfm_stb=0, bfm_sel=10, bfm_data_in_0=00000000, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +200 INFO: bfm_stb=1, bfm_sel=00, bfm_data_in_0=00100010, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +210 INFO: bfm_stb=0, bfm_sel=00, bfm_data_in_0=11000101, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +220 INFO: bfm_stb=0, bfm_sel=00, bfm_data_in_0=10101010, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +260 INFO: bfm_stb=1, bfm_sel=00, bfm_data_in_0=01011011, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +270 INFO: bfm_stb=0, bfm_sel=00, bfm_data_in_0=11110010, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +310 INFO: bfm_stb=1, bfm_sel=00, bfm_data_in_0=10000000, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +320 INFO: bfm_stb=0, bfm_sel=00, bfm_data_in_0=10111101, bfm_data_in_1=00000000, bfm_data_in_2=00111101 +360 INFO: bfm_stb=1, bfm_sel=01, bfm_data_in_0=10111101, bfm_data_in_1=10010000, bfm_data_in_2=00111101 +370 INFO: bfm_stb=0, bfm_sel=01, bfm_data_in_0=10111101, bfm_data_in_1=10000000, bfm_data_in_2=00111101 +380 INFO: bfm_stb=0, bfm_sel=01, bfm_data_in_0=10111101, bfm_data_in_1=00100000, bfm_data_in_2=00111101 +390 INFO: bfm_stb=0, bfm_sel=01, bfm_data_in_0=10111101, bfm_data_in_1=10101010, bfm_data_in_2=00111101 +430 INFO: bfm_stb=1, bfm_sel=00, bfm_data_in_0=00100111, bfm_data_in_1=10101010, bfm_data_in_2=00111101 +440 INFO: bfm_stb=0, bfm_sel=00, bfm_data_in_0=01010011, bfm_data_in_1=10101010, bfm_data_in_2=00111101 +450 INFO: bfm_stb=0, bfm_sel=00, bfm_data_in_0=01101011, bfm_data_in_1=10101010, bfm_data_in_2=00111101 +490 INFO: bfm_stb=1, bfm_sel=01, bfm_data_in_0=01101011, bfm_data_in_1=10000001, bfm_data_in_2=00111101 +500 INFO: bfm_stb=0, bfm_sel=01, bfm_data_in_0=01101011, bfm_data_in_1=11001111, bfm_data_in_2=00111101 +540 INFO: bfm_stb=1, bfm_sel=10, bfm_data_in_0=01101011, bfm_data_in_1=11001111, bfm_data_in_2=00000010 +550 INFO: bfm_stb=0, bfm_sel=10, bfm_data_in_0=01101011, bfm_data_in_1=11001111, bfm_data_in_2=11110010 +560 INFO: bfm_stb=0, bfm_sel=10, bfm_data_in_0=01101011, bfm_data_in_1=11001111, bfm_data_in_2=10001010 +600 INFO: bfm_stb=1, bfm_sel=01, bfm_data_in_0=01101011, bfm_data_in_1=01000101, bfm_data_in_2=10001010 +610 INFO: bfm_stb=0, bfm_sel=01, bfm_data_in_0=01101011, bfm_data_in_1=11101011, bfm_data_in_2=10001010 +620 INFO: bfm_stb=0, bfm_sel=01, bfm_data_in_0=01101011, bfm_data_in_1=10110110, bfm_data_in_2=10001010
/trunk/run/data_valid_in_monitor.out
/trunk/run/improved_test.log
0,0 → 1,58
 
Executing 'make TEST_TYPE=improved_test.v >> improved_test.log 2>&1'
 
v ../rtl/dut.v ../rtl/selector.v ../rtl/alu.v ../rtl/dmux.v ../verif_env/bfms/clk_gen.v ../verif_env/bfms/res_bfm.v ../verif_env/bfms/data_in_bfm.v ../verif_env/monitors/clk_monitor.v ../verif_env/monitors/res_monitor.v ../verif_env/monitors/stb_monitor.v ../verif_env/monitors/sel_monitor.v ../verif_env/monitors/data_valid_in_monitor.v ../verif_env/monitors/data_in_monitor.v ../verif_env/monitors/data_out_monitor.v ../verif_env/monitors/parity_monitor.v ../verif_env/monitors/valid_monitor.v ../verif_env/collectors/input_collector.v ../verif_env/collectors/output_collector.v ../verif_env/checker/checker.v ../tests/improved_test.v
 
Compiling source file "../rtl/dut.v"
Compiling source file "../rtl/selector.v"
Compiling source file "../rtl/alu.v"
Compiling source file "../rtl/dmux.v"
Compiling source file "../verif_env/bfms/clk_gen.v"
Compiling source file "../verif_env/bfms/res_bfm.v"
Compiling source file "../verif_env/bfms/data_in_bfm.v"
Compiling source file "../verif_env/monitors/clk_monitor.v"
Compiling source file "../verif_env/monitors/res_monitor.v"
Compiling source file "../verif_env/monitors/stb_monitor.v"
Compiling source file "../verif_env/monitors/sel_monitor.v"
Compiling source file "../verif_env/monitors/data_valid_in_monitor.v"
Compiling source file "../verif_env/monitors/data_in_monitor.v"
Compiling source file "../verif_env/monitors/data_out_monitor.v"
Compiling source file "../verif_env/monitors/parity_monitor.v"
Compiling source file "../verif_env/monitors/valid_monitor.v"
Compiling source file "../verif_env/collectors/input_collector.v"
Compiling source file "../verif_env/collectors/output_collector.v"
Compiling source file "../verif_env/checker/checker.v"
Compiling source file "../tests/improved_test.v"
Highest level modules:
proj_improved_test
 
Transaction no: 0
OPERATION {} (Concatenation): alu_memory[0]=00001101, alu_memory[1]=10001101, alu_result=0000110110001101
Transaction no: 1
Relational operator
OPERATION < (Less than): alu_memory[0]=01110110, alu_memory[1]=00111101, alu_result=0000000000000000
Transaction no: 2
Relational operator
OPERATION < (Less than): alu_memory[0]=11000101, alu_memory[1]=10101010, alu_result=0000000000000000
Transaction no: 3
Reduction operator
OPERATION ^~ (Reduction xnor (1st operator symbol)): alu_memory[0]=11110010, alu_result=0000000000000000
Transaction no: 4
Replication operator
OPERATION { { } } (Replication): alu_memory[0]=10111101 - replicated twice: alu_result=1011110110111101
Transaction no: 5
Conditional operator
OPERATION ?: (Conditional): alu_memory[0]=10000000, alu_memory[1]=00100000, alu_memory[2]=10101010, alu_result=0000000000100000
Transaction no: 6
Relational operator
OPERATION <= (Less than or equal): alu_memory[0]=01010011, alu_memory[1]=01101011, alu_result=0000000000000001
Transaction no: 7
Replication operator
OPERATION { { } } (Replication): alu_memory[0]=11001111 - replicated twice: alu_result=1100111111001111
Transaction no: 8
Arithmetic operator
OPERATION / (Divide): alu_memory[0]=11110010, alu_memory[1]=10001010, alu_result=0000000000000001
Transaction no: 9
Bitwise operator
OPERATION | (Bitwise or): alu_memory[0]=11101011, alu_memory[1]=10110110, alu_result=0000000011111111
L167 "../verif_env/bfms/data_in_bfm.v": $finish at simulation time 730
/trunk/run/parity_0_monitor.out
/trunk/run/stb_monitor.out
/trunk/run/clk_gen.out
0,0 → 1,58
0 INFO: Toggling CLK every 5 simulation seconds...
/trunk/run/checker.out
0,0 → 1,70
116 INFO: Collected IN transaction no 0: ic_data_0 = 01110001, ic_data_1 = 00001101, ic_data_2 = 10001101, ic_data_3 = 00000000
Concatenation operator
OPERATION {} (Concatenation): ic_data_1 = 00001101, ic_data_2 = 10001101, checker_result = 0000110110001101
155 INFO: Collected OUT transaction no 0: 0000110110001101
155 INFO: Calculus of data for transaction no. 0 match! (0000110110001101 - 0000110110001101)
155 INFO: Calculus of parity for transaction no. 0 match! (1 - 1)
 
176 INFO: Collected IN transaction no 1: ic_data_0 = 00100011, ic_data_1 = 01110110, ic_data_2 = 00111101, ic_data_3 = 00000000
Relational operator
OPERATION < (Less than): ic_data_1 = 01110110, ic_data_2 = 00111101, checker_result = 0000000000000000
215 INFO: Collected OUT transaction no 1: 0000000000000000
215 INFO: Calculus of data for transaction no. 1 match! (0000000000000000 - 0000000000000000)
215 INFO: Calculus of parity for transaction no. 1 match! (0 - 0)
 
236 INFO: Collected IN transaction no 2: ic_data_0 = 00100010, ic_data_1 = 11000101, ic_data_2 = 10101010, ic_data_3 = 00000000
Relational operator
OPERATION < (Less than): ic_data_1 = 11000101, ic_data_2 = 10101010, checker_result = 0000000000000000
275 INFO: Collected OUT transaction no 2: 0000000000000000
275 INFO: Calculus of data for transaction no. 2 match! (0000000000000000 - 0000000000000000)
275 INFO: Calculus of parity for transaction no. 2 match! (0 - 0)
 
286 INFO: Collected IN transaction no 3: ic_data_0 = 01011011, ic_data_1 = 11110010, ic_data_2 = 10101010, ic_data_3 = 00000000
Reduction operator
OPERATION ^~ (Reduction xnor (1st operator symbol)): ic_data_1 = 11110010, checker_result = 0000000000000000
335 INFO: Collected OUT transaction no 3: 0000000000000000
335 INFO: Calculus of data for transaction no. 3 match! (0000000000000000 - 0000000000000000)
335 INFO: Calculus of parity for transaction no. 3 match! (0 - 0)
 
336 INFO: Collected IN transaction no 4: ic_data_0 = 10000000, ic_data_1 = 10111101, ic_data_2 = 10101010, ic_data_3 = 00000000
Replication operator
OPERATION { { } } (Replication): ic_data_1 = 10111101 - replicated twice: checker_result = 1011110110111101
385 INFO: Collected OUT transaction no 4: 1011110110111101
385 INFO: Calculus of data for transaction no. 4 match! (1011110110111101 - 1011110110111101)
385 INFO: Calculus of parity for transaction no. 4 match! (0 - 0)
 
406 INFO: Collected IN transaction no 5: ic_data_0 = 10010000, ic_data_1 = 10000000, ic_data_2 = 00100000, ic_data_3 = 10101010
Conditional operator
OPERATION ?: (Conditional): ic_data_1 = 10000000, ic_data_2 = 00100000, ic_data_3=10101010, checker_result = 0000000000100000
435 INFO: Collected OUT transaction no 5: 0000000000100000
435 INFO: Calculus of data for transaction no. 5 match! (0000000000100000 - 0000000000100000)
435 INFO: Calculus of parity for transaction no. 5 match! (1 - 1)
 
466 INFO: Collected IN transaction no 6: ic_data_0 = 00100111, ic_data_1 = 01010011, ic_data_2 = 01101011, ic_data_3 = 10101010
Relational operator
OPERATION <= (Less than or equal): ic_data_1 = 01010011, ic_data_2 = 01101011, checker_result = 0000000000000001
505 INFO: Collected OUT transaction no 6: 0000000000000001
505 INFO: Calculus of data for transaction no. 6 match! (0000000000000001 - 0000000000000001)
505 INFO: Calculus of parity for transaction no. 6 match! (1 - 1)
 
516 INFO: Collected IN transaction no 7: ic_data_0 = 10000001, ic_data_1 = 11001111, ic_data_2 = 01101011, ic_data_3 = 10101010
Replication operator
OPERATION { { } } (Replication): ic_data_1 = 11001111 - replicated twice: checker_result = 1100111111001111
565 INFO: Collected OUT transaction no 7: 1100111111001111
565 INFO: Calculus of data for transaction no. 7 match! (1100111111001111 - 1100111111001111)
565 INFO: Calculus of parity for transaction no. 7 match! (0 - 0)
 
576 INFO: Collected IN transaction no 8: ic_data_0 = 00000010, ic_data_1 = 11110010, ic_data_2 = 10001010, ic_data_3 = 10101010
Arithmetic operator
OPERATION / (Divide): ic_data_1 = 11110010, ic_data_2 = 10001010, checker_result = 0000000000000001
615 INFO: Collected OUT transaction no 8: 0000000000000001
615 INFO: Calculus of data for transaction no. 8 match! (0000000000000001 - 0000000000000001)
615 INFO: Calculus of parity for transaction no. 8 match! (1 - 1)
 
636 INFO: Collected IN transaction no 9: ic_data_0 = 01000101, ic_data_1 = 11101011, ic_data_2 = 10110110, ic_data_3 = 10101010
Bitwise operator
OPERATION | (Bitwise or): ic_data_1 = 11101011, ic_data_2 = 10110110, checker_result = 0000000011111111
675 INFO: Collected OUT transaction no 9: 0000000011111111
675 INFO: Calculus of data for transaction no. 9 match! (0000000011111111 - 0000000011111111)
675 INFO: Calculus of parity for transaction no. 9 match! (0 - 0)
 
/trunk/run/input_collector.out
0,0 → 1,99
20 INFO: Input Transaction no: 0
20 INFO: ic_data_out_0 = 00000000
INFO: operator type = 0
INFO: operator symbol = 0
INFO: output channel = 0
20 INFO: ic_data_out_1 = 00000000
20 INFO: ic_data_out_2 = 00000000
20 INFO: ic_data_out_3 = 00000000
 
115 INFO: Input Transaction no: 1
115 INFO: ic_data_out_0 = 01110001
INFO: operator type = 7
INFO: operator symbol = 0
INFO: output channel = 1
115 INFO: ic_data_out_1 = 00001101
115 INFO: ic_data_out_2 = 10001101
115 INFO: ic_data_out_3 = 00000000
 
175 INFO: Input Transaction no: 2
175 INFO: ic_data_out_0 = 00100011
INFO: operator type = 2
INFO: operator symbol = 1
INFO: output channel = 1
175 INFO: ic_data_out_1 = 01110110
175 INFO: ic_data_out_2 = 00111101
175 INFO: ic_data_out_3 = 00000000
 
235 INFO: Input Transaction no: 3
235 INFO: ic_data_out_0 = 00100010
INFO: operator type = 2
INFO: operator symbol = 1
INFO: output channel = 0
235 INFO: ic_data_out_1 = 11000101
235 INFO: ic_data_out_2 = 10101010
235 INFO: ic_data_out_3 = 00000000
 
285 INFO: Input Transaction no: 4
285 INFO: ic_data_out_0 = 01011011
INFO: operator type = 5
INFO: operator symbol = 5
INFO: output channel = 1
285 INFO: ic_data_out_1 = 11110010
285 INFO: ic_data_out_2 = 10101010
285 INFO: ic_data_out_3 = 00000000
 
335 INFO: Input Transaction no: 5
335 INFO: ic_data_out_0 = 10000000
INFO: operator type = 8
INFO: operator symbol = 0
INFO: output channel = 0
335 INFO: ic_data_out_1 = 10111101
335 INFO: ic_data_out_2 = 10101010
335 INFO: ic_data_out_3 = 00000000
 
405 INFO: Input Transaction no: 6
405 INFO: ic_data_out_0 = 10010000
INFO: operator type = 9
INFO: operator symbol = 0
INFO: output channel = 0
405 INFO: ic_data_out_1 = 10000000
405 INFO: ic_data_out_2 = 00100000
405 INFO: ic_data_out_3 = 10101010
 
465 INFO: Input Transaction no: 7
465 INFO: ic_data_out_0 = 00100111
INFO: operator type = 2
INFO: operator symbol = 3
INFO: output channel = 1
465 INFO: ic_data_out_1 = 01010011
465 INFO: ic_data_out_2 = 01101011
465 INFO: ic_data_out_3 = 10101010
 
515 INFO: Input Transaction no: 8
515 INFO: ic_data_out_0 = 10000001
INFO: operator type = 8
INFO: operator symbol = 0
INFO: output channel = 1
515 INFO: ic_data_out_1 = 11001111
515 INFO: ic_data_out_2 = 01101011
515 INFO: ic_data_out_3 = 10101010
 
575 INFO: Input Transaction no: 9
575 INFO: ic_data_out_0 = 00000010
INFO: operator type = 0
INFO: operator symbol = 1
INFO: output channel = 0
575 INFO: ic_data_out_1 = 11110010
575 INFO: ic_data_out_2 = 10001010
575 INFO: ic_data_out_3 = 10101010
 
635 INFO: Input Transaction no: 10
635 INFO: ic_data_out_0 = 01000101
INFO: operator type = 4
INFO: operator symbol = 2
INFO: output channel = 1
635 INFO: ic_data_out_1 = 11101011
635 INFO: ic_data_out_2 = 10110110
635 INFO: ic_data_out_3 = 10101010
 
/trunk/run/valid_monitor.out
/trunk/run/output_collector.out
0,0 → 1,44
20 INFO: Output Transaction no: 0
20 INFO: oc_data = 0000000000000000
20 INFO: oc_parity = 0
 
155 INFO: Output Transaction no: 1
155 INFO: oc_data = 0000110110001101
155 INFO: oc_parity = 1
 
215 INFO: Output Transaction no: 2
215 INFO: oc_data = 0000000000000000
215 INFO: oc_parity = 0
 
275 INFO: Output Transaction no: 3
275 INFO: oc_data = 0000000000000000
275 INFO: oc_parity = 0
 
335 INFO: Output Transaction no: 4
335 INFO: oc_data = 0000000000000000
335 INFO: oc_parity = 0
 
385 INFO: Output Transaction no: 5
385 INFO: oc_data = 1011110110111101
385 INFO: oc_parity = 0
 
435 INFO: Output Transaction no: 6
435 INFO: oc_data = 0000000000100000
435 INFO: oc_parity = 1
 
505 INFO: Output Transaction no: 7
505 INFO: oc_data = 0000000000000001
505 INFO: oc_parity = 1
 
565 INFO: Output Transaction no: 8
565 INFO: oc_data = 1100111111001111
565 INFO: oc_parity = 0
 
615 INFO: Output Transaction no: 9
615 INFO: oc_data = 0000000000000001
615 INFO: oc_parity = 1
 
675 INFO: Output Transaction no: 10
675 INFO: oc_data = 0000000011111111
675 INFO: oc_parity = 0
 
/trunk/run/data_out_monitor.out Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/Design_and_verification_env.vsd
trunk/doc/Design_and_verification_env.vsd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/Line count =================================================================== --- trunk/doc/Line count (nonexistent) +++ trunk/doc/Line count (revision 2) @@ -0,0 +1,33 @@ +Comments: +- 24 * 42 = 1008 + +Total lines of code for each file: +97 +380 +119 +93 +89 +139 +265 +150 +200 +66 +171 +70 +388 +142 +110 +65 +75 +73 +65 +71 +65 +76 +66 +77 +--- +3112- +1008 +---- +2104 - effective code Index: trunk/doc/dmux.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/dmux.png =================================================================== --- trunk/doc/dmux.png (nonexistent) +++ trunk/doc/dmux.png (revision 2)
trunk/doc/dmux.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/Spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/Spec.pdf =================================================================== --- trunk/doc/Spec.pdf (nonexistent) +++ trunk/doc/Spec.pdf (revision 2)
trunk/doc/Spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/selector.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/selector.png =================================================================== --- trunk/doc/selector.png (nonexistent) +++ trunk/doc/selector.png (revision 2)
trunk/doc/selector.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/Design_and_verification_env.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/Design_and_verification_env.jpg =================================================================== --- trunk/doc/Design_and_verification_env.jpg (nonexistent) +++ trunk/doc/Design_and_verification_env.jpg (revision 2)
trunk/doc/Design_and_verification_env.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/alu.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/alu.png =================================================================== --- trunk/doc/alu.png (nonexistent) +++ trunk/doc/alu.png (revision 2)
trunk/doc/alu.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/ASICArt.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/ASICArt.jpg =================================================================== --- trunk/doc/ASICArt.jpg (nonexistent) +++ trunk/doc/ASICArt.jpg (revision 2)
trunk/doc/ASICArt.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/dut.vsd =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/dut.vsd =================================================================== --- trunk/doc/dut.vsd (nonexistent) +++ trunk/doc/dut.vsd (revision 2)
trunk/doc/dut.vsd Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/Spec.sxw =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/Spec.sxw =================================================================== --- trunk/doc/Spec.sxw (nonexistent) +++ trunk/doc/Spec.sxw (revision 2)
trunk/doc/Spec.sxw Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/dut.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/dut.jpg =================================================================== --- trunk/doc/dut.jpg (nonexistent) +++ trunk/doc/dut.jpg (revision 2)
trunk/doc/dut.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/Spec.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/Spec.doc =================================================================== --- trunk/doc/Spec.doc (nonexistent) +++ trunk/doc/Spec.doc (revision 2)
trunk/doc/Spec.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/scripts/RunTest.pl =================================================================== --- trunk/scripts/RunTest.pl (nonexistent) +++ trunk/scripts/RunTest.pl (revision 2) @@ -0,0 +1,138 @@ +#! /usr/bin/perl -w + + +#///////////////////////////////////////////////////////////////////// +#//// //// +#//// This project has been provided to you on behalf of: //// +#//// //// +#//// S.C. ASICArt S.R.L. //// +#//// www.asicart.com //// +#//// eli_f@asicart.com //// +#//// //// +#//// Author: Dragos Constantin Doncean //// +#//// Email: doncean@asicart.com //// +#//// Mobile: +40-740-936997 //// +#//// //// +#//// Downloaded from: http://www.opencores.org/ //// +#//// //// +#///////////////////////////////////////////////////////////////////// +#//// //// +#//// Copyright (C) 2007 Dragos Constantin Doncean //// +#//// www.asicart.com //// +#//// doncean@asicart.com //// +#//// //// +#//// This source file may be used and distributed without //// +#//// restriction provided that this copyright statement is not //// +#//// removed from the file and that any derivative work contains //// +#//// the original copyright notice and the associated disclaimer.//// +#//// //// +#//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +#//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +#//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +#//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +#//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +#//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +#//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +#//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +#//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +#//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +#//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +#//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +#//// POSSIBILITY OF SUCH DAMAGE. //// +#//// //// +#///////////////////////////////////////////////////////////////////// + + +use Getopt::Long; +use IO::Handle; + +###################################################################### +# the help print +###################################################################### +my $help = < [-help|-h] + [-log|-l ] + +The arguments meaning: +---------------------- + + - the test name (can be with or without the extention .vr) +[-help|-h] - print this help screen +[-log|-l ] - the test name + +EndHelp + +###################################################################### +# check the arguments +###################################################################### +$result = &GetOptions(\%optctl, "help|h", "log|l=s"); + +if($result == 0 || $#ARGV == -1 || defined($optctl{help})){ + print $help; + exit 0; +} + +$test_name = $ARGV[0]; +$test_name =~ s/\.v$//; +$test_file = "$test_name" . ".v"; + +unless (-e $test_file) { + die "\n Test file $test_file does not exist!!!\n" . + " exiting ...\n"; +} + +if(defined($optctl{"log"})){ + $log_file = $optctl{"log"}; +} +else{ + $log_file = $test_name . ".log"; +} + +###################################################################### +# open the log file, create cds.lib and hdl.var +###################################################################### +open (LOG_FILE, "> $log_file") or die " Can not open file $log_file\n\n"; +autoflush LOG_FILE; +SystemCmd("date"); +close (LOG_FILE); + +###################################################################### +# compile the test +###################################################################### +my $test_compile_cmd = "verilog -c $test_file"; +SystemCmd("$test_compile_cmd"); + +###################################################################### +# clean the test directory +###################################################################### +SystemCmd("make clean"); + +###################################################################### +# run the simulation +###################################################################### +my $sim_cmd = "make TEST_TYPE=$test_file"; +SystemCmd("$sim_cmd"); + +###################################################################### +# Execute system command +###################################################################### +sub SystemCmd # Arg: Command string +{ + my($command_line) = @_; + open (LOG_FILE, ">> $log_file") or die "Can not create $log_file file\n"; + autoflush LOG_FILE; + print LOG_FILE "\nExecuting '$command_line >> $log_file 2>&1'\n"; + close(LOG_FILE); + sleep 1; + system "$command_line >> $log_file 2>&1"; + my $rc = $?/256; + sleep 1; + open (LOG_FILE, ">> $log_file") or die "Can not create $log_file file\n"; + autoflush LOG_FILE; + if ($rc != 0) { + print LOG_FILE "\nWARNING: Return code of system command $command_line >> $log_file > 2>&1 = $rc != 0\n"; + } + close (LOG_FILE); + $rc; +}
trunk/scripts/RunTest.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sv_files/simvision_random_test.sv =================================================================== --- trunk/sv_files/simvision_random_test.sv (nonexistent) +++ trunk/sv_files/simvision_random_test.sv (revision 2) @@ -0,0 +1,295 @@ +# SimVision Command Script (Sat Jan 06 15:05:30 EET 2007) +# +# Version 05.50.s003 +# +# You can restore this configuration with: +# +# simvision -input simvision_ac.sv +# or +# simvision -input simvision_ac.sv database1 database2 ... +# + +# +# preferences +# +preferences set signal-type-colors { + group #0000FF + overlay #0000FF + input #FFFF00 + output #FFA500 + inout #00FFFF + internal #00FF00 + fiber #FF99FF + errorsignal #FF0000 + assertion #FF0000 + unknown #FFFFFF +} +preferences set sb-syntax-types { + {-name "VHDL/VHDL-AMS" -cleanname "vhdl" -extensions {.vhd .vhdl}} + {-name "Verilog/Verilog-AMS" -cleanname "verilog" -extensions {.v .vams .vms .va}} + {-name "C" -cleanname "c" -extensions {.c}} + {-name "C++" -cleanname "c++" -extensions {.h .hpp .cc .cpp .CC}} + {-name "SystemC" -cleanname "systemc" -extensions {.h .hpp .cc .cpp .CC}} +} +preferences set toolbar-Windows-SrcBrowser { + usual + hide icheck +} +preferences set key-bindings { + Edit>Undo "Ctrl+Z" + Edit>Redo "Ctrl+Y" + Edit>Copy "Ctrl+C" + Edit>Cut "Ctrl+X" + Edit>Paste "Ctrl+V" + Edit>Delete "Del" + Select>All "Ctrl+A" + Edit>Select>All "Ctrl+A" + Edit>SelectAll "Ctrl+A" + openDB "Ctrl+O" + Simulation>Run "F2" + Simulation>Next "F6" + Simulation>Step "F5" + #Schematic window + View>Zoom>Fit "Alt+=" + View>Zoom>In "Alt+I" + View>Zoom>Out "Alt+O" + #Waveform Window + View>Zoom>InX "Alt+I" + View>Zoom>OutX "Alt+O" + View>Zoom>FullX "Alt+=" + View>Zoom>InX_widget "I" + View>Zoom>OutX_widget "O" + View>Zoom>FullX_widget "=" + View>Zoom>FullY_widget "Y" + View>Zoom>Cursor-Baseline "Alt+Z" + View>Center "Alt+C" + View>ExpandSequenceTime>AtCursor "Alt+X" + View>CollapseSequenceTime>AtCursor "Alt+S" + Edit>Create>Group "Ctrl+G" + Edit>Ungroup "Ctrl+Shift+G" + Edit>Create>Marker "Ctrl+M" + Edit>Create>Condition "Ctrl+E" + Edit>Create>Bus "Ctrl+W" + Explore>NextEdge "Ctrl+]" + Explore>PreviousEdge "Ctrl+[" + ScrollRight "Right arrow" + ScrollLeft "Left arrow" + ScrollUp "Up arrow" + ScrollDown "Down arrow" + PageUp "PageUp" + PageDown "PageDown" + TopOfPage "Home" + BottomOfPage "End" +} +preferences set toolbar-Windows-WaveWindow { + usual + hide icheck + position -pos 3 +} +preferences set toolbar-Windows-WatchList { + usual + hide icheck +} + +# +# databases +# +database require waves -hints { + file ./waves/waves.trn + file /home/student/pvlsi/dragos/proj_new1/waves/waves.trn + file /home/student/pvlsi/dragos/proj_new1/waves_random_test/waves_random_test.trn +} + +# +# groups +# + +if {[catch {group new -name SELECTOR -overlay 0}] != ""} { + group using SELECTOR + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_random_test.dut.selector.clk \ + proj_random_test.dut.selector.res \ + proj_random_test.dut.selector.stb \ + proj_random_test.dut.selector.data_valid_in \ + {proj_random_test.dut.selector.sel[1:0]} \ + {proj_random_test.dut.selector.data_in_0[7:0]} \ + {proj_random_test.dut.selector.data_in_1[7:0]} \ + {proj_random_test.dut.selector.data_in_2[7:0]} \ + {proj_random_test.dut.selector.data_out[7:0]} \ + proj_random_test.dut.selector.data_valid_out \ + {proj_random_test.dut.selector.reg_sel[1:0]} \ + proj_random_test.dut.selector.stb_out + +if {[catch {group new -name ALU -overlay 0}] != ""} { + group using ALU + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_random_test.dut.alu.clk \ + proj_random_test.dut.alu.res \ + proj_random_test.dut.alu.alu_stb_in \ + proj_random_test.dut.alu.alu_data_valid_in \ + {proj_random_test.dut.alu.operator_type[3:0]} \ + {proj_random_test.dut.alu.operator_symbol[2:0]} \ + {proj_random_test.dut.alu.alu_data_in[7:0]} \ + {proj_random_test.dut.alu.alu_result[15:0]} \ + proj_random_test.dut.alu.result_parity \ + proj_random_test.dut.alu.output_channel \ + proj_random_test.dut.alu.alu_stb_out \ + proj_random_test.dut.alu.executed_case_once \ + proj_random_test.dut.alu.i \ + proj_random_test.dut.alu.j + +if {[catch {group new -name {Group 3} -overlay 0}] != ""} { + group using {Group 3} + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + {proj_random_test.dut.dmux.alu_result[15:0]} \ + proj_random_test.dut.dmux.clk \ + proj_random_test.dut.dmux.dmux_stb_in \ + {proj_random_test.dut.dmux.out_0[15:0]} \ + {proj_random_test.dut.dmux.out_1[15:0]} \ + proj_random_test.dut.dmux.output_channel \ + proj_random_test.dut.dmux.parity_0 \ + proj_random_test.dut.dmux.parity_1 \ + proj_random_test.dut.dmux.res \ + proj_random_test.dut.dmux.result_parity \ + proj_random_test.dut.dmux.valid_0 \ + proj_random_test.dut.dmux.valid_1 + +if {[catch {group new -name DMUX -overlay 0}] != ""} { + group using DMUX + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_random_test.dut.dmux.clk \ + proj_random_test.dut.dmux.res \ + proj_random_test.dut.dmux.dmux_stb_in \ + proj_random_test.dut.dmux.output_channel \ + {proj_random_test.dut.dmux.alu_result[15:0]} \ + proj_random_test.dut.dmux.result_parity \ + {proj_random_test.dut.dmux.out_0[15:0]} \ + {proj_random_test.dut.dmux.out_1[15:0]} \ + proj_random_test.dut.dmux.parity_0 \ + proj_random_test.dut.dmux.parity_1 \ + proj_random_test.dut.dmux.valid_0 \ + proj_random_test.dut.dmux.valid_1 + +# +# mmaps +# +mmap new -reuse -name {Boolean as Logic} -contents { +{%c=FALSE -edgepriority 1 -shape low} +{%c=TRUE -edgepriority 1 -shape high} +} +mmap new -reuse -name {Example Map} -contents { +{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus} +{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=* -label %x -linecolor gray -shape bus} +} + +# +# Design Browser windows +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1265x915+0+0}] != ""} { + window geometry "Design Browser 1" 1265x915+0+0 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope proj_random_test.dut.dmux +browser yview see proj_random_test.dut.dmux +browser timecontrol set -lock 0 + +# +# Waveform windows +# +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1278x915+0+0}] != ""} { + window geometry "Waveform 1" 1278x915+0+0 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 116 +cursor set -using TimeA -time 115ns +waveform baseline set -time 0 + +set groupId [waveform add -groups SELECTOR] +set glist [waveform hierarchy contents $groupId] +set id [lindex $glist 0] +foreach {name attrs} { + proj_random_test.dut.selector.clk {} + proj_random_test.dut.selector.res {} + proj_random_test.dut.selector.stb {} + proj_random_test.dut.selector.data_valid_in {} + proj_random_test.dut.selector.sel {} + proj_random_test.dut.selector.data_in_0 {} + proj_random_test.dut.selector.data_in_1 {} + proj_random_test.dut.selector.data_in_2 {-radix %x} + proj_random_test.dut.selector.data_out {-radix %x} + proj_random_test.dut.selector.data_valid_out {} + proj_random_test.dut.selector.reg_sel {} + proj_random_test.dut.selector.stb_out {} +} { + set expected [ join [waveform signals -format native $id] ] + if {[string equal $name $expected]} { + if {$attrs != ""} { + eval waveform format $id $attrs + } + set glist [lrange $glist 1 end] + set id [lindex $glist 0] + } +} + +set groupId [waveform add -groups ALU] +set glist [waveform hierarchy contents $groupId] +set id [lindex $glist 0] +foreach {name attrs} { + proj_random_test.dut.alu.clk {} + proj_random_test.dut.alu.res {} + proj_random_test.dut.alu.alu_stb_in {} + proj_random_test.dut.alu.alu_data_valid_in {} + proj_random_test.dut.alu.operator_type {} + proj_random_test.dut.alu.operator_symbol {} + proj_random_test.dut.alu.alu_data_in {-radix %x} + proj_random_test.dut.alu.alu_result {-radix %x} + proj_random_test.dut.alu.result_parity {} + proj_random_test.dut.alu.output_channel {} + proj_random_test.dut.alu.alu_stb_out {} + proj_random_test.dut.alu.executed_case_once {} + proj_random_test.dut.alu.i {} + proj_random_test.dut.alu.j {} +} { + set expected [ join [waveform signals -format native $id] ] + if {[string equal $name $expected]} { + if {$attrs != ""} { + eval waveform format $id $attrs + } + set glist [lrange $glist 1 end] + set id [lindex $glist 0] + } +} + +set groupId [waveform add -groups DMUX] + +set id [waveform add -signals [list proj_random_test.dut.dmux.i \ + proj_random_test.dut.dmux.dmux_stb_in_was_1 ]] + +waveform xview limits 0 200ns Index: trunk/sv_files/simvision_directed_test.sv =================================================================== --- trunk/sv_files/simvision_directed_test.sv (nonexistent) +++ trunk/sv_files/simvision_directed_test.sv (revision 2) @@ -0,0 +1,296 @@ +# SimVision Command Script (Sat Jan 06 15:05:30 EET 2007) +# +# Version 05.50.s003 +# +# You can restore this configuration with: +# +# simvision -input simvision_ac.sv +# or +# simvision -input simvision_ac.sv database1 database2 ... +# + +# +# preferences +# +preferences set signal-type-colors { + group #0000FF + overlay #0000FF + input #FFFF00 + output #FFA500 + inout #00FFFF + internal #00FF00 + fiber #FF99FF + errorsignal #FF0000 + assertion #FF0000 + unknown #FFFFFF +} +preferences set sb-syntax-types { + {-name "VHDL/VHDL-AMS" -cleanname "vhdl" -extensions {.vhd .vhdl}} + {-name "Verilog/Verilog-AMS" -cleanname "verilog" -extensions {.v .vams .vms .va}} + {-name "C" -cleanname "c" -extensions {.c}} + {-name "C++" -cleanname "c++" -extensions {.h .hpp .cc .cpp .CC}} + {-name "SystemC" -cleanname "systemc" -extensions {.h .hpp .cc .cpp .CC}} +} +preferences set toolbar-Windows-SrcBrowser { + usual + hide icheck +} +preferences set key-bindings { + Edit>Undo "Ctrl+Z" + Edit>Redo "Ctrl+Y" + Edit>Copy "Ctrl+C" + Edit>Cut "Ctrl+X" + Edit>Paste "Ctrl+V" + Edit>Delete "Del" + Select>All "Ctrl+A" + Edit>Select>All "Ctrl+A" + Edit>SelectAll "Ctrl+A" + openDB "Ctrl+O" + Simulation>Run "F2" + Simulation>Next "F6" + Simulation>Step "F5" + #Schematic window + View>Zoom>Fit "Alt+=" + View>Zoom>In "Alt+I" + View>Zoom>Out "Alt+O" + #Waveform Window + View>Zoom>InX "Alt+I" + View>Zoom>OutX "Alt+O" + View>Zoom>FullX "Alt+=" + View>Zoom>InX_widget "I" + View>Zoom>OutX_widget "O" + View>Zoom>FullX_widget "=" + View>Zoom>FullY_widget "Y" + View>Zoom>Cursor-Baseline "Alt+Z" + View>Center "Alt+C" + View>ExpandSequenceTime>AtCursor "Alt+X" + View>CollapseSequenceTime>AtCursor "Alt+S" + Edit>Create>Group "Ctrl+G" + Edit>Ungroup "Ctrl+Shift+G" + Edit>Create>Marker "Ctrl+M" + Edit>Create>Condition "Ctrl+E" + Edit>Create>Bus "Ctrl+W" + Explore>NextEdge "Ctrl+]" + Explore>PreviousEdge "Ctrl+[" + ScrollRight "Right arrow" + ScrollLeft "Left arrow" + ScrollUp "Up arrow" + ScrollDown "Down arrow" + PageUp "PageUp" + PageDown "PageDown" + TopOfPage "Home" + BottomOfPage "End" +} +preferences set toolbar-Windows-WaveWindow { + usual + hide icheck + position -pos 3 +} +preferences set toolbar-Windows-WatchList { + usual + hide icheck +} + +# +# databases +# +database require waves -hints { +# file ./waves/waves.trn +# file /home/student/pvlsi/dragos/proj_new1/waves/waves.trn +# file ./waves_directed_test/waves_directed_test.trn + file ../waves/waves_directed_test/waves_directed_test.trn +} + +# +# groups +# + +if {[catch {group new -name SELECTOR -overlay 0}] != ""} { + group using SELECTOR + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_directed_test.dut.selector.clk \ + proj_directed_test.dut.selector.res \ + proj_directed_test.dut.selector.stb \ + proj_directed_test.dut.selector.data_valid_in \ + {proj_directed_test.dut.selector.sel[1:0]} \ + {proj_directed_test.dut.selector.data_in_0[7:0]} \ + {proj_directed_test.dut.selector.data_in_1[7:0]} \ + {proj_directed_test.dut.selector.data_in_2[7:0]} \ + {proj_directed_test.dut.selector.data_out[7:0]} \ + proj_directed_test.dut.selector.data_valid_out \ + {proj_directed_test.dut.selector.reg_sel[1:0]} \ + proj_directed_test.dut.selector.stb_out + +if {[catch {group new -name ALU -overlay 0}] != ""} { + group using ALU + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_directed_test.dut.alu.clk \ + proj_directed_test.dut.alu.res \ + proj_directed_test.dut.alu.alu_stb_in \ + proj_directed_test.dut.alu.alu_data_valid_in \ + {proj_directed_test.dut.alu.operator_type[3:0]} \ + {proj_directed_test.dut.alu.operator_symbol[2:0]} \ + {proj_directed_test.dut.alu.alu_data_in[7:0]} \ + {proj_directed_test.dut.alu.alu_result[15:0]} \ + proj_directed_test.dut.alu.result_parity \ + proj_directed_test.dut.alu.output_channel \ + proj_directed_test.dut.alu.alu_stb_out \ + proj_directed_test.dut.alu.executed_case_once \ + proj_directed_test.dut.alu.i \ + proj_directed_test.dut.alu.j + +if {[catch {group new -name {Group 3} -overlay 0}] != ""} { + group using {Group 3} + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + {proj_directed_test.dut.dmux.alu_result[15:0]} \ + proj_directed_test.dut.dmux.clk \ + proj_directed_test.dut.dmux.dmux_stb_in \ + {proj_directed_test.dut.dmux.out_0[15:0]} \ + {proj_directed_test.dut.dmux.out_1[15:0]} \ + proj_directed_test.dut.dmux.output_channel \ + proj_directed_test.dut.dmux.parity_0 \ + proj_directed_test.dut.dmux.parity_1 \ + proj_directed_test.dut.dmux.res \ + proj_directed_test.dut.dmux.result_parity \ + proj_directed_test.dut.dmux.valid_0 \ + proj_directed_test.dut.dmux.valid_1 + +if {[catch {group new -name DMUX -overlay 0}] != ""} { + group using DMUX + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_directed_test.dut.dmux.clk \ + proj_directed_test.dut.dmux.res \ + proj_directed_test.dut.dmux.dmux_stb_in \ + proj_directed_test.dut.dmux.output_channel \ + {proj_directed_test.dut.dmux.alu_result[15:0]} \ + proj_directed_test.dut.dmux.result_parity \ + {proj_directed_test.dut.dmux.out_0[15:0]} \ + {proj_directed_test.dut.dmux.out_1[15:0]} \ + proj_directed_test.dut.dmux.parity_0 \ + proj_directed_test.dut.dmux.parity_1 \ + proj_directed_test.dut.dmux.valid_0 \ + proj_directed_test.dut.dmux.valid_1 + +# +# mmaps +# +mmap new -reuse -name {Boolean as Logic} -contents { +{%c=FALSE -edgepriority 1 -shape low} +{%c=TRUE -edgepriority 1 -shape high} +} +mmap new -reuse -name {Example Map} -contents { +{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus} +{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=* -label %x -linecolor gray -shape bus} +} + +# +# Design Browser windows +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1265x915+0+0}] != ""} { + window geometry "Design Browser 1" 1265x915+0+0 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope proj_directed_test.dut.dmux +browser yview see proj_directed_test.dut.dmux +browser timecontrol set -lock 0 + +# +# Waveform windows +# +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1278x915+0+0}] != ""} { + window geometry "Waveform 1" 1278x915+0+0 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 116 +cursor set -using TimeA -time 115ns +waveform baseline set -time 0 + +set groupId [waveform add -groups SELECTOR] +set glist [waveform hierarchy contents $groupId] +set id [lindex $glist 0] +foreach {name attrs} { + proj_directed_test.dut.selector.clk {} + proj_directed_test.dut.selector.res {} + proj_directed_test.dut.selector.stb {} + proj_directed_test.dut.selector.data_valid_in {} + proj_directed_test.dut.selector.sel {} + proj_directed_test.dut.selector.data_in_0 {} + proj_directed_test.dut.selector.data_in_1 {} + proj_directed_test.dut.selector.data_in_2 {-radix %x} + proj_directed_test.dut.selector.data_out {-radix %x} + proj_directed_test.dut.selector.data_valid_out {} + proj_directed_test.dut.selector.reg_sel {} + proj_directed_test.dut.selector.stb_out {} +} { + set expected [ join [waveform signals -format native $id] ] + if {[string equal $name $expected]} { + if {$attrs != ""} { + eval waveform format $id $attrs + } + set glist [lrange $glist 1 end] + set id [lindex $glist 0] + } +} + +set groupId [waveform add -groups ALU] +set glist [waveform hierarchy contents $groupId] +set id [lindex $glist 0] +foreach {name attrs} { + proj_directed_test.dut.alu.clk {} + proj_directed_test.dut.alu.res {} + proj_directed_test.dut.alu.alu_stb_in {} + proj_directed_test.dut.alu.alu_data_valid_in {} + proj_directed_test.dut.alu.operator_type {} + proj_directed_test.dut.alu.operator_symbol {} + proj_directed_test.dut.alu.alu_data_in {-radix %x} + proj_directed_test.dut.alu.alu_result {-radix %x} + proj_directed_test.dut.alu.result_parity {} + proj_directed_test.dut.alu.output_channel {} + proj_directed_test.dut.alu.alu_stb_out {} + proj_directed_test.dut.alu.executed_case_once {} + proj_directed_test.dut.alu.i {} + proj_directed_test.dut.alu.j {} +} { + set expected [ join [waveform signals -format native $id] ] + if {[string equal $name $expected]} { + if {$attrs != ""} { + eval waveform format $id $attrs + } + set glist [lrange $glist 1 end] + set id [lindex $glist 0] + } +} + +set groupId [waveform add -groups DMUX] + +set id [waveform add -signals [list proj_directed_test.dut.dmux.i \ + proj_directed_test.dut.dmux.dmux_stb_in_was_1 ]] + +waveform xview limits 0 200ns Index: trunk/sv_files/simvision_improved_test.sv =================================================================== --- trunk/sv_files/simvision_improved_test.sv (nonexistent) +++ trunk/sv_files/simvision_improved_test.sv (revision 2) @@ -0,0 +1,295 @@ +# SimVision Command Script (Sat Jan 06 15:05:30 EET 2007) +# +# Version 05.50.s003 +# +# You can restore this configuration with: +# +# simvision -input simvision_ac.sv +# or +# simvision -input simvision_ac.sv database1 database2 ... +# + +# +# preferences +# +preferences set signal-type-colors { + group #0000FF + overlay #0000FF + input #FFFF00 + output #FFA500 + inout #00FFFF + internal #00FF00 + fiber #FF99FF + errorsignal #FF0000 + assertion #FF0000 + unknown #FFFFFF +} +preferences set sb-syntax-types { + {-name "VHDL/VHDL-AMS" -cleanname "vhdl" -extensions {.vhd .vhdl}} + {-name "Verilog/Verilog-AMS" -cleanname "verilog" -extensions {.v .vams .vms .va}} + {-name "C" -cleanname "c" -extensions {.c}} + {-name "C++" -cleanname "c++" -extensions {.h .hpp .cc .cpp .CC}} + {-name "SystemC" -cleanname "systemc" -extensions {.h .hpp .cc .cpp .CC}} +} +preferences set toolbar-Windows-SrcBrowser { + usual + hide icheck +} +preferences set key-bindings { + Edit>Undo "Ctrl+Z" + Edit>Redo "Ctrl+Y" + Edit>Copy "Ctrl+C" + Edit>Cut "Ctrl+X" + Edit>Paste "Ctrl+V" + Edit>Delete "Del" + Select>All "Ctrl+A" + Edit>Select>All "Ctrl+A" + Edit>SelectAll "Ctrl+A" + openDB "Ctrl+O" + Simulation>Run "F2" + Simulation>Next "F6" + Simulation>Step "F5" + #Schematic window + View>Zoom>Fit "Alt+=" + View>Zoom>In "Alt+I" + View>Zoom>Out "Alt+O" + #Waveform Window + View>Zoom>InX "Alt+I" + View>Zoom>OutX "Alt+O" + View>Zoom>FullX "Alt+=" + View>Zoom>InX_widget "I" + View>Zoom>OutX_widget "O" + View>Zoom>FullX_widget "=" + View>Zoom>FullY_widget "Y" + View>Zoom>Cursor-Baseline "Alt+Z" + View>Center "Alt+C" + View>ExpandSequenceTime>AtCursor "Alt+X" + View>CollapseSequenceTime>AtCursor "Alt+S" + Edit>Create>Group "Ctrl+G" + Edit>Ungroup "Ctrl+Shift+G" + Edit>Create>Marker "Ctrl+M" + Edit>Create>Condition "Ctrl+E" + Edit>Create>Bus "Ctrl+W" + Explore>NextEdge "Ctrl+]" + Explore>PreviousEdge "Ctrl+[" + ScrollRight "Right arrow" + ScrollLeft "Left arrow" + ScrollUp "Up arrow" + ScrollDown "Down arrow" + PageUp "PageUp" + PageDown "PageDown" + TopOfPage "Home" + BottomOfPage "End" +} +preferences set toolbar-Windows-WaveWindow { + usual + hide icheck + position -pos 3 +} +preferences set toolbar-Windows-WatchList { + usual + hide icheck +} + +# +# databases +# +database require waves -hints { + file ./waves/waves.trn + file /home/student/pvlsi/dragos/proj_new1/waves/waves.trn + file /home/student/pvlsi/dragos/proj_new1/waves_improved_test/waves_improved_test.trn +} + +# +# groups +# + +if {[catch {group new -name SELECTOR -overlay 0}] != ""} { + group using SELECTOR + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_improved_test.dut.selector.clk \ + proj_improved_test.dut.selector.res \ + proj_improved_test.dut.selector.stb \ + proj_improved_test.dut.selector.data_valid_in \ + {proj_improved_test.dut.selector.sel[1:0]} \ + {proj_improved_test.dut.selector.data_in_0[7:0]} \ + {proj_improved_test.dut.selector.data_in_1[7:0]} \ + {proj_improved_test.dut.selector.data_in_2[7:0]} \ + {proj_improved_test.dut.selector.data_out[7:0]} \ + proj_improved_test.dut.selector.data_valid_out \ + {proj_improved_test.dut.selector.reg_sel[1:0]} \ + proj_improved_test.dut.selector.stb_out + +if {[catch {group new -name ALU -overlay 0}] != ""} { + group using ALU + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_improved_test.dut.alu.clk \ + proj_improved_test.dut.alu.res \ + proj_improved_test.dut.alu.alu_stb_in \ + proj_improved_test.dut.alu.alu_data_valid_in \ + {proj_improved_test.dut.alu.operator_type[3:0]} \ + {proj_improved_test.dut.alu.operator_symbol[2:0]} \ + {proj_improved_test.dut.alu.alu_data_in[7:0]} \ + {proj_improved_test.dut.alu.alu_result[15:0]} \ + proj_improved_test.dut.alu.result_parity \ + proj_improved_test.dut.alu.output_channel \ + proj_improved_test.dut.alu.alu_stb_out \ + proj_improved_test.dut.alu.executed_case_once \ + proj_improved_test.dut.alu.i \ + proj_improved_test.dut.alu.j + +if {[catch {group new -name {Group 3} -overlay 0}] != ""} { + group using {Group 3} + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + {proj_improved_test.dut.dmux.alu_result[15:0]} \ + proj_improved_test.dut.dmux.clk \ + proj_improved_test.dut.dmux.dmux_stb_in \ + {proj_improved_test.dut.dmux.out_0[15:0]} \ + {proj_improved_test.dut.dmux.out_1[15:0]} \ + proj_improved_test.dut.dmux.output_channel \ + proj_improved_test.dut.dmux.parity_0 \ + proj_improved_test.dut.dmux.parity_1 \ + proj_improved_test.dut.dmux.res \ + proj_improved_test.dut.dmux.result_parity \ + proj_improved_test.dut.dmux.valid_0 \ + proj_improved_test.dut.dmux.valid_1 + +if {[catch {group new -name DMUX -overlay 0}] != ""} { + group using DMUX + group set -overlay 0 + group set -comment {} + group clear 0 end +} +group insert \ + proj_improved_test.dut.dmux.clk \ + proj_improved_test.dut.dmux.res \ + proj_improved_test.dut.dmux.dmux_stb_in \ + proj_improved_test.dut.dmux.output_channel \ + {proj_improved_test.dut.dmux.alu_result[15:0]} \ + proj_improved_test.dut.dmux.result_parity \ + {proj_improved_test.dut.dmux.out_0[15:0]} \ + {proj_improved_test.dut.dmux.out_1[15:0]} \ + proj_improved_test.dut.dmux.parity_0 \ + proj_improved_test.dut.dmux.parity_1 \ + proj_improved_test.dut.dmux.valid_0 \ + proj_improved_test.dut.dmux.valid_1 + +# +# mmaps +# +mmap new -reuse -name {Boolean as Logic} -contents { +{%c=FALSE -edgepriority 1 -shape low} +{%c=TRUE -edgepriority 1 -shape high} +} +mmap new -reuse -name {Example Map} -contents { +{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus} +{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=* -label %x -linecolor gray -shape bus} +} + +# +# Design Browser windows +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1265x915+0+0}] != ""} { + window geometry "Design Browser 1" 1265x915+0+0 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope proj_improved_test.dut.dmux +browser yview see proj_improved_test.dut.dmux +browser timecontrol set -lock 0 + +# +# Waveform windows +# +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1278x915+0+0}] != ""} { + window geometry "Waveform 1" 1278x915+0+0 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 116 +cursor set -using TimeA -time 115ns +waveform baseline set -time 0 + +set groupId [waveform add -groups SELECTOR] +set glist [waveform hierarchy contents $groupId] +set id [lindex $glist 0] +foreach {name attrs} { + proj_improved_test.dut.selector.clk {} + proj_improved_test.dut.selector.res {} + proj_improved_test.dut.selector.stb {} + proj_improved_test.dut.selector.data_valid_in {} + proj_improved_test.dut.selector.sel {} + proj_improved_test.dut.selector.data_in_0 {} + proj_improved_test.dut.selector.data_in_1 {} + proj_improved_test.dut.selector.data_in_2 {-radix %x} + proj_improved_test.dut.selector.data_out {-radix %x} + proj_improved_test.dut.selector.data_valid_out {} + proj_improved_test.dut.selector.reg_sel {} + proj_improved_test.dut.selector.stb_out {} +} { + set expected [ join [waveform signals -format native $id] ] + if {[string equal $name $expected]} { + if {$attrs != ""} { + eval waveform format $id $attrs + } + set glist [lrange $glist 1 end] + set id [lindex $glist 0] + } +} + +set groupId [waveform add -groups ALU] +set glist [waveform hierarchy contents $groupId] +set id [lindex $glist 0] +foreach {name attrs} { + proj_improved_test.dut.alu.clk {} + proj_improved_test.dut.alu.res {} + proj_improved_test.dut.alu.alu_stb_in {} + proj_improved_test.dut.alu.alu_data_valid_in {} + proj_improved_test.dut.alu.operator_type {} + proj_improved_test.dut.alu.operator_symbol {} + proj_improved_test.dut.alu.alu_data_in {-radix %x} + proj_improved_test.dut.alu.alu_result {-radix %x} + proj_improved_test.dut.alu.result_parity {} + proj_improved_test.dut.alu.output_channel {} + proj_improved_test.dut.alu.alu_stb_out {} + proj_improved_test.dut.alu.executed_case_once {} + proj_improved_test.dut.alu.i {} + proj_improved_test.dut.alu.j {} +} { + set expected [ join [waveform signals -format native $id] ] + if {[string equal $name $expected]} { + if {$attrs != ""} { + eval waveform format $id $attrs + } + set glist [lrange $glist 1 end] + set id [lindex $glist 0] + } +} + +set groupId [waveform add -groups DMUX] + +set id [waveform add -signals [list proj_improved_test.dut.dmux.i \ + proj_improved_test.dut.dmux.dmux_stb_in_was_1 ]] + +waveform xview limits 0 200ns Index: trunk/makefile/Makefile =================================================================== --- trunk/makefile/Makefile (nonexistent) +++ trunk/makefile/Makefile (revision 2) @@ -0,0 +1,96 @@ +#///////////////////////////////////////////////////////////////////// +#//// //// +#//// This project has been provided to you on behalf of: //// +#//// //// +#//// S.C. ASICArt S.R.L. //// +#//// www.asicart.com //// +#//// eli_f@asicart.com //// +#//// //// +#//// Author: Dragos Constantin Doncean //// +#//// Email: doncean@asicart.com //// +#//// Mobile: +40-740-936997 //// +#//// //// +#//// Downloaded from: http://www.opencores.org/ //// +#//// //// +#///////////////////////////////////////////////////////////////////// +#//// //// +#//// Copyright (C) 2007 Dragos Constantin Doncean //// +#//// www.asicart.com //// +#//// doncean@asicart.com //// +#//// //// +#//// This source file may be used and distributed without //// +#//// restriction provided that this copyright statement is not //// +#//// removed from the file and that any derivative work contains //// +#//// the original copyright notice and the associated disclaimer.//// +#//// //// +#//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +#//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +#//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +#//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +#//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +#//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +#//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +#//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +#//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +#//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +#//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +#//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +#//// POSSIBILITY OF SUCH DAMAGE. //// +#//// //// +#///////////////////////////////////////////////////////////////////// + +all: sim + +_RTL_ = ../rtl/dut.v \ + ../rtl/selector.v \ + ../rtl/alu.v \ + ../rtl/dmux.v + +TEST_TYPE = + +ifeq ($(TEST_TYPE), improved_test.v) + +_TEST_ = ../tests/improved_test.v + +_BFMS_ = ../verif_env/bfms/clk_gen.v \ + ../verif_env/bfms/res_bfm.v \ + ../verif_env/bfms/data_in_bfm.v + +_MONITORS_ = ../verif_env/monitors/clk_monitor.v \ + ../verif_env/monitors/res_monitor.v \ + ../verif_env/monitors/stb_monitor.v \ + ../verif_env/monitors/sel_monitor.v \ + ../verif_env/monitors/data_valid_in_monitor.v \ + ../verif_env/monitors/data_in_monitor.v \ + ../verif_env/monitors/data_out_monitor.v \ + ../verif_env/monitors/parity_monitor.v \ + ../verif_env/monitors/valid_monitor.v + +_COLLECTORS_ = ../verif_env/collectors/input_collector.v \ + ../verif_env/collectors/output_collector.v + +_CHECKER_ = ../verif_env/checker/checker.v + +SOURCE_FILES = $(_RTL_) $(_BFMS_) $(_MONITORS_) $(_COLLECTORS_) $(_CHECKER_) $(_TEST_) + +endif + +ifeq ($(TEST_TYPE), directed_test.v) + _TEST_ = ../tests/directed_test.v + SOURCE_FILES = $(_RTL_) $(_TEST_) +endif + +ifeq ($(TEST_TYPE), random_test.v) + _TEST_ = ../tests/random_test.v + SOURCE_FILES = $(_RTL_) $(_TEST_) +endif + +RUN_COMMAND = verilog + +sim: + $(RUN_COMMAND) $(SOURCE_FILES) + +clean : + rm -f *.log + rm -f *.out + rm -rf waves/*

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