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/astron_pipeline/trunk/dp_pipeline.vhd
0,0 → 1,156
-------------------------------------------------------------------------------
--
-- Copyright (C) 2010
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
USE IEEE.std_logic_1164.all;
USE dp_pkg_lib.dp_stream_pkg.ALL;
 
-- Purpose:
-- Pipeline the source output by one cycle or by g_pipeline cycles.
-- Description:
-- The dp_pipeline instantiates 0:g_pipeline stages of dp_pipeline_one.
-- The dp_pipeline_one provides a single clock cycle delay of the source
-- output (i.e. sosi). The dp_pipeline_one holds valid sink input in case
-- src_in.ready goes low and makes src_out.valid high again when
-- src_in.ready goes high again, without the need for a valid sink input to
-- push this held data out.
-- The dp_pipeline delays the data, sop, eop by one cycle relative to the
-- valid. However the src_out.valid still has the same phase as the
-- snk_in.valid, because both valids depends on the same src_in.ready.
-- Therefore dp_pipeline cannot be used to delay the valid phase by one
-- cycle. Hence the may purpose of dp_pipeline is to register the sosi.
-- Remarks:
-- . Ready latency = 1
-- . Without flow control so when src_in.ready = '1' fixed, then the hold
-- logic in dp_pipeline becomes void and dp_pipeline then just pipelines the
-- snk_in sosi.
 
ENTITY dp_pipeline IS
GENERIC (
g_pipeline : NATURAL := 1 -- 0 for wires, > 0 for registers,
);
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
-- ST sink
snk_out : OUT t_dp_siso;
snk_in : IN t_dp_sosi;
-- ST source
src_in : IN t_dp_siso := c_dp_siso_rdy;
src_out : OUT t_dp_sosi
);
END dp_pipeline;
 
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
USE IEEE.std_logic_1164.all;
USE dp_pkg_lib.dp_stream_pkg.ALL;
 
ENTITY dp_pipeline_one IS
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
-- ST sink
snk_out : OUT t_dp_siso;
snk_in : IN t_dp_sosi;
-- ST source
src_in : IN t_dp_siso := c_dp_siso_rdy;
src_out : OUT t_dp_sosi
);
END dp_pipeline_one;
 
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
USE IEEE.std_logic_1164.all;
USE dp_pkg_lib.dp_stream_pkg.ALL;
 
ARCHITECTURE str OF dp_pipeline IS
 
SIGNAL snk_out_arr : t_dp_siso_arr(0 TO g_pipeline);
SIGNAL snk_in_arr : t_dp_sosi_arr(0 TO g_pipeline);
BEGIN
 
-- Input at index 0
snk_out <= snk_out_arr(0);
snk_in_arr(0) <= snk_in;
-- Output at index g_pipeline
snk_out_arr(g_pipeline) <= src_in;
src_out <= snk_in_arr(g_pipeline);
gen_p : FOR I IN 1 TO g_pipeline GENERATE
u_p : ENTITY work.dp_pipeline_one
PORT MAP (
rst => rst,
clk => clk,
-- ST sink
snk_out => snk_out_arr(I-1),
snk_in => snk_in_arr(I-1),
-- ST source
src_in => snk_out_arr(I),
src_out => snk_in_arr(I)
);
END GENERATE;
END str;
 
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_components_lib;
USE IEEE.std_logic_1164.all;
USE dp_pkg_lib.dp_stream_pkg.ALL;
 
ARCHITECTURE str OF dp_pipeline_one IS
 
SIGNAL nxt_src_out : t_dp_sosi;
SIGNAL i_src_out : t_dp_sosi;
BEGIN
 
src_out <= i_src_out;
 
-- Pipeline register
p_clk : PROCESS(rst, clk)
BEGIN
IF rst='1' THEN
i_src_out <= c_dp_sosi_rst;
ELSIF rising_edge(clk) THEN
i_src_out <= nxt_src_out;
END IF;
END PROCESS;
-- Input control
u_hold_input : ENTITY dp_components_lib.dp_hold_input
PORT MAP (
rst => rst,
clk => clk,
-- ST sink
snk_out => snk_out,
snk_in => snk_in,
-- ST source
src_in => src_in,
next_src_out => nxt_src_out,
pend_src_out => OPEN,
src_out_reg => i_src_out
);
END str;
astron_pipeline/trunk/dp_pipeline.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astron_pipeline/trunk/dp_pipeline_arr.vhd =================================================================== --- astron_pipeline/trunk/dp_pipeline_arr.vhd (nonexistent) +++ astron_pipeline/trunk/dp_pipeline_arr.vhd (revision 2) @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) +-- JIVE (Joint Institute for VLBI in Europe) +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_pkg_lib, dp_pkg_lib; +USE IEEE.std_logic_1164.all; +USE dp_pkg_lib.dp_stream_pkg.ALL; + +-- Purpose: +-- Pipeline array of g_nof_streams by g_pipeline cycles. +-- Description: +-- See dp_pipeline. + +ENTITY dp_pipeline_arr IS + GENERIC ( + g_nof_streams : NATURAL := 1; + g_pipeline : NATURAL := 1 -- 0 for wires, > 0 for registers, + ); + PORT ( + rst : IN STD_LOGIC; + clk : IN STD_LOGIC; + -- ST sink + snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0); + snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); + -- ST source + src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); + src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) + ); +END dp_pipeline_arr; + + +ARCHITECTURE str OF dp_pipeline_arr IS + +BEGIN + + gen_nof_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE + u_p : ENTITY work.dp_pipeline + GENERIC MAP ( + g_pipeline => g_pipeline + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => snk_out_arr(I), + snk_in => snk_in_arr(I), + -- ST source + src_in => src_in_arr(I), + src_out => src_out_arr(I) + ); + END GENERATE; + +END str;
astron_pipeline/trunk/dp_pipeline_arr.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astron_pipeline/trunk/dp_pipeline_ready.vhd =================================================================== --- astron_pipeline/trunk/dp_pipeline_ready.vhd (nonexistent) +++ astron_pipeline/trunk/dp_pipeline_ready.vhd (revision 2) @@ -0,0 +1,157 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2010 +-- ASTRON (Netherlands Institute for Radio Astronomy) +-- JIVE (Joint Institute for VLBI in Europe) +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_components_lib; +USE IEEE.std_logic_1164.all; +USE dp_pkg_lib.dp_stream_pkg.ALL; + +-- Purpose: +-- Pipeline the source input +-- Description: +-- This dp_pipeline_ready provides a single clock cycle delay of the source +-- input (i.e. siso). It does this by first going from RL = g_in_latency --> +-- 0 and then to RL = g_out_latency. +-- Data flow: +-- . out RL > in RL : incr(out RL - in RL) +-- . out RL <= in RL AND out RL = 0 : incr(1) --> adapt(out RL) +-- . out RL <= in RL AND out RL > 0 : adapt(0) --> incr(out RL) +-- Remark: +-- . The g_in_latency may be 0, but for g_in_latency=0 the sosi.ready acts +-- as an acknowledge and that could simply also be registered by the user. + +ENTITY dp_pipeline_ready IS + GENERIC ( + g_in_latency : NATURAL := 1; -- >= 0 + g_out_latency : NATURAL := 1 -- >= 0 + ); + PORT ( + rst : IN STD_LOGIC; + clk : IN STD_LOGIC; + -- ST sink + snk_out : OUT t_dp_siso; + snk_in : IN t_dp_sosi; + -- ST source + src_in : IN t_dp_siso; + src_out : OUT t_dp_sosi + ); +END dp_pipeline_ready; + + +ARCHITECTURE str OF dp_pipeline_ready IS + + SIGNAL internal_siso : t_dp_siso; + SIGNAL internal_sosi : t_dp_sosi; + +BEGIN + + gen_out_incr_rl : IF g_out_latency>g_in_latency GENERATE + -- Register siso by incrementing the input RL first + u_incr : ENTITY dp_components_lib.dp_latency_increase + GENERIC MAP ( + g_in_latency => g_in_latency, + g_incr_latency => g_out_latency-g_in_latency + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => snk_out, + snk_in => snk_in, + -- ST source + src_in => src_in, + src_out => src_out + ); + END GENERATE; + + gen_out_rl_0 : IF g_out_latency<=g_in_latency AND g_out_latency=0 GENERATE + -- Register siso by incrementing the input RL first + u_incr : ENTITY dp_components_lib.dp_latency_increase + GENERIC MAP ( + g_in_latency => g_in_latency, + g_incr_latency => 1 + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => snk_out, + snk_in => snk_in, + -- ST source + src_in => internal_siso, + src_out => internal_sosi + ); + + -- Input RL --> 0 + u_adapt : ENTITY dp_components_lib.dp_latency_adapter + GENERIC MAP ( + g_in_latency => g_in_latency+1, + g_out_latency => g_out_latency + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => internal_siso, + snk_in => internal_sosi, + -- ST source + src_in => src_in, + src_out => src_out + ); + END GENERATE; + + gen_out_rl : IF g_out_latency<=g_in_latency AND g_out_latency>0 GENERATE + -- First adapt the input RL --> 0 + u_adapt : ENTITY dp_components_lib.dp_latency_adapter + GENERIC MAP ( + g_in_latency => g_in_latency, + g_out_latency => 0 + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => snk_out, + snk_in => snk_in, + -- ST source + src_in => internal_siso, + src_out => internal_sosi + ); + + -- Register siso by incrementing the internal RL = 0 --> the output RL + u_incr : ENTITY dp_components_lib.dp_latency_increase + GENERIC MAP ( + g_in_latency => 0, + g_incr_latency => g_out_latency + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => internal_siso, + snk_in => internal_sosi, + -- ST source + src_in => src_in, + src_out => src_out + ); + END GENERATE; + +END str;
astron_pipeline/trunk/dp_pipeline_ready.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astron_pipeline/trunk/hdllib.cfg =================================================================== --- astron_pipeline/trunk/hdllib.cfg (nonexistent) +++ astron_pipeline/trunk/hdllib.cfg (revision 2) @@ -0,0 +1,26 @@ +hdl_lib_name = dp_pipeline +hdl_library_clause_name = dp_pipeline_lib +hdl_lib_uses_synth = common_pkg dp_pkg dp_components #common_mult #easics #mm +hdl_lib_uses_sim = +hdl_lib_technology = + +synth_files = + dp_pipeline.vhd + dp_pipeline_arr.vhd + dp_pipeline_ready.vhd + +test_bench_files = + + tb_dp_pipeline.vhd + tb_dp_pipeline_ready.vhd + tb_tb_dp_pipeline.vhd + tb_tb_dp_pipeline_ready.vhd + +regression_test_vhdl = + tb_tb_dp_pipeline.vhd + tb_tb_dp_pipeline_ready.vhd + +[modelsim_project_file] + + +[quartus_project_file]
astron_pipeline/trunk/hdllib.cfg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astron_pipeline/trunk/tb_dp_pipeline.vhd =================================================================== --- astron_pipeline/trunk/tb_dp_pipeline.vhd (nonexistent) +++ astron_pipeline/trunk/tb_dp_pipeline.vhd (revision 2) @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2010 +-- ASTRON (Netherlands Institute for Radio Astronomy) +-- JIVE (Joint Institute for VLBI in Europe) +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_pkg_lib, dp_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE dp_pkg_lib.dp_stream_pkg.ALL; +USE dp_pkg_lib.tb_dp_pkg.ALL; + +ENTITY tb_dp_pipeline IS + GENERIC ( + g_pipeline : NATURAL := 5 + ); +END tb_dp_pipeline; + + +ARCHITECTURE tb OF tb_dp_pipeline IS + + -- See tb_dp_pkg.vhd for explanation and run time + + -- DUT ready latency + CONSTANT c_dut_latency : NATURAL := 1; -- fixed 1 for dp_pipeline + CONSTANT c_tx_latency : NATURAL := c_dut_latency; -- TX ready latency of TB + CONSTANT c_tx_void : NATURAL := sel_a_b(c_tx_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_tx_latency=0 + CONSTANT c_tx_offset_sop : NATURAL := 3; + CONSTANT c_tx_period_sop : NATURAL := 7; -- sop in data valid cycle 3, 10, 17, ... + CONSTANT c_tx_offset_eop : NATURAL := 5; -- eop in data valid cycle 5, 12, 19, ... + CONSTANT c_tx_period_eop : NATURAL := c_tx_period_sop; + CONSTANT c_tx_offset_sync : NATURAL := 3; -- sync in data valid cycle 3, 20, 37, ... + CONSTANT c_tx_period_sync : NATURAL := 17; + CONSTANT c_rx_latency : NATURAL := c_dut_latency; -- RX ready latency from DUT + CONSTANT c_verify_en_wait : NATURAL := 4+g_pipeline; -- wait some cycles before asserting verify enable + + CONSTANT c_random_w : NATURAL := 19; + + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rst : STD_LOGIC; + SIGNAL sync : STD_LOGIC; + SIGNAL lfsr1 : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0'); + SIGNAL lfsr2 : STD_LOGIC_VECTOR(c_random_w DOWNTO 0) := (OTHERS=>'0'); + + SIGNAL cnt_dat : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0); + SIGNAL cnt_val : STD_LOGIC; + SIGNAL cnt_en : STD_LOGIC; + + SIGNAL tx_data : t_dp_data_arr(0 TO c_tx_latency + c_tx_void) := (OTHERS=>(OTHERS=>'0')); + SIGNAL tx_val : STD_LOGIC_VECTOR(0 TO c_tx_latency + c_tx_void) := (OTHERS=>'0'); + + SIGNAL in_ready : STD_LOGIC; + SIGNAL in_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := (OTHERS=>'0'); + SIGNAL in_sync : STD_LOGIC; + SIGNAL in_val : STD_LOGIC; + SIGNAL in_sop : STD_LOGIC; + SIGNAL in_eop : STD_LOGIC; + + SIGNAL in_siso : t_dp_siso; + SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst; + SIGNAL out_siso : t_dp_siso; + SIGNAL out_sosi : t_dp_sosi; + + SIGNAL out_ready : STD_LOGIC; + SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rx_latency); + SIGNAL out_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0); + SIGNAL out_sync : STD_LOGIC; + SIGNAL out_val : STD_LOGIC; + SIGNAL out_sop : STD_LOGIC; + SIGNAL out_eop : STD_LOGIC; + SIGNAL hold_out_sop : STD_LOGIC; + SIGNAL prev_out_data : STD_LOGIC_VECTOR(out_data'RANGE); + + SIGNAL state : t_dp_state_enum; + + SIGNAL verify_en : STD_LOGIC; + SIGNAL verify_done : STD_LOGIC; + + SIGNAL exp_data : STD_LOGIC_VECTOR(c_dp_data_w-1 DOWNTO 0) := TO_UVEC(sel_a_b(g_pipeline=0, 18953, 18952), c_dp_data_w); + +BEGIN + + clk <= NOT clk OR tb_end AFTER clk_period/2; + rst <= '1', '0' AFTER clk_period*7; + + -- Sync interval + proc_dp_sync_interval(clk, sync); + + -- Input data + cnt_val <= in_ready AND cnt_en; + + proc_dp_cnt_dat(rst, clk, cnt_val, cnt_dat); + proc_dp_tx_data(c_tx_latency, rst, clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val); + proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync); + proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop); + proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop); + + -- Stimuli control + proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_end, cnt_en); + proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready); + + -- Output verify + proc_dp_verify_en(c_verify_en_wait, rst, clk, sync, verify_en); + proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data); + proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val); + proc_dp_verify_sop_and_eop(c_rx_latency, FALSE, clk, out_val, out_val, out_sop, out_eop, hold_out_sop); -- Verify that sop and eop come in pairs, no check on valid between eop and sop + proc_dp_verify_ctrl(c_tx_offset_sync, c_tx_period_sync, "sync", clk, verify_en, out_data, out_val, out_sync); + proc_dp_verify_ctrl(c_tx_offset_sop, c_tx_period_sop, "sop", clk, verify_en, out_data, out_val, out_sop); + proc_dp_verify_ctrl(c_tx_offset_eop, c_tx_period_eop, "eop", clk, verify_en, out_data, out_val, out_eop); + + -- Check that the test has ran at all + proc_dp_verify_value(e_equal, clk, verify_done, exp_data, out_data); + + ------------------------------------------------------------------------------ + -- DUT dp_pipeline + ------------------------------------------------------------------------------ + + -- map sl, slv to record + in_ready <= in_siso.ready; -- SISO + in_sosi.data(c_dp_data_w-1 DOWNTO 0) <= in_data; -- SOSI + in_sosi.sync <= in_sync; + in_sosi.valid <= in_val; + in_sosi.sop <= in_sop; + in_sosi.eop <= in_eop; + + out_siso.ready <= out_ready; -- SISO + out_data <= out_sosi.data(c_dp_data_w-1 DOWNTO 0); -- SOSI + out_sync <= out_sosi.sync; + out_val <= out_sosi.valid; + out_sop <= out_sosi.sop; + out_eop <= out_sosi.eop; + + dut : ENTITY work.dp_pipeline + GENERIC MAP ( + g_pipeline => g_pipeline + ) + PORT MAP ( + rst => rst, + clk => clk, + snk_out => in_siso, -- OUT = request to upstream ST source + snk_in => in_sosi, + src_in => out_siso, -- IN = request from downstream ST sink + src_out => out_sosi + ); + +END tb;
astron_pipeline/trunk/tb_dp_pipeline.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astron_pipeline/trunk/tb_dp_pipeline_ready.vhd =================================================================== --- astron_pipeline/trunk/tb_dp_pipeline_ready.vhd (nonexistent) +++ astron_pipeline/trunk/tb_dp_pipeline_ready.vhd (revision 2) @@ -0,0 +1,223 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2011 +-- ASTRON (Netherlands Institute for Radio Astronomy) +-- JIVE (Joint Institute for VLBI in Europe) +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +------------------------------------------------------------------------------- + +-- Purpose: Verify dp_pipeline_ready for different RL +-- Description: +-- Usage: +-- > as 10 +-- > run -all -- signal tb_end will stop the simulation by stopping the clk +-- . The verify procedures check the correct output + +LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_components_lib; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE common_pkg_lib.common_pkg.ALL; +USE common_pkg_lib.common_lfsr_sequences_pkg.ALL; +USE common_pkg_lib.tb_common_pkg.ALL; +USE dp_pkg_lib.dp_stream_pkg.ALL; +USE dp_pkg_lib.tb_dp_pkg.ALL; + + +ENTITY tb_dp_pipeline_ready IS + GENERIC ( + g_in_en : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control + g_out_ready : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control + g_in_latency : NATURAL := 1; -- >= 0 + g_out_latency : NATURAL := 0; -- >= 0 + g_nof_repeat : NATURAL := 50 + ); +END tb_dp_pipeline_ready; + + +ARCHITECTURE tb OF tb_dp_pipeline_ready IS + CONSTANT c_data_w : NATURAL := 16; + CONSTANT c_rl : NATURAL := 1; + CONSTANT c_data_init : INTEGER := 0; + CONSTANT c_frame_len_init : NATURAL := 1; -- >= 1 + CONSTANT c_pulse_active : NATURAL := 1; + CONSTANT c_pulse_period : NATURAL := 7; + CONSTANT c_sync_period : NATURAL := 7; + CONSTANT c_sync_offset : NATURAL := 2; + + SIGNAL tb_end : STD_LOGIC := '0'; + SIGNAL clk : STD_LOGIC := '1'; + SIGNAL rst : STD_LOGIC := '1'; + + -- Flow control + SIGNAL random_0 : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences + SIGNAL random_1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences + SIGNAL pulse_0 : STD_LOGIC; + SIGNAL pulse_1 : STD_LOGIC; + SIGNAL pulse_en : STD_LOGIC := '1'; + + -- Stimuli + SIGNAL in_en : STD_LOGIC := '1'; + SIGNAL in_siso : t_dp_siso; + SIGNAL in_sosi : t_dp_sosi; + SIGNAL adapt_siso : t_dp_siso; + SIGNAL adapt_sosi : t_dp_sosi; + + SIGNAL out_siso : t_dp_siso := c_dp_siso_hold; -- ready='0', xon='1' + SIGNAL out_sosi : t_dp_sosi; + + -- Verification + SIGNAL verify_en : STD_LOGIC := '0'; + SIGNAL verify_done : STD_LOGIC := '0'; + SIGNAL count_eop : NATURAL := 0; + + SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO g_out_latency); + SIGNAL prev_out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := TO_SVEC(c_data_init-1, c_data_w); + SIGNAL out_bsn : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0); + SIGNAL out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0); + SIGNAL out_sync : STD_LOGIC; + SIGNAL out_val : STD_LOGIC; + SIGNAL out_sop : STD_LOGIC; + SIGNAL out_eop : STD_LOGIC; + SIGNAL hold_out_sop : STD_LOGIC; + SIGNAL expected_out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0); + +BEGIN + + clk <= (NOT clk) OR tb_end AFTER clk_period/2; + rst <= '1', '0' AFTER clk_period*7; + + random_0 <= func_common_random(random_0) WHEN rising_edge(clk); + random_1 <= func_common_random(random_1) WHEN rising_edge(clk); + + proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0); + proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period+1, '1', rst, clk, pulse_en, pulse_1); + + + ------------------------------------------------------------------------------ + -- STREAM CONTROL + ------------------------------------------------------------------------------ + + in_en <= '1' WHEN g_in_en=e_active ELSE + random_0(random_0'HIGH) WHEN g_in_en=e_random ELSE + pulse_0 WHEN g_in_en=e_pulse; + + out_siso.ready <= '1' WHEN g_out_ready=e_active ELSE + random_1(random_1'HIGH) WHEN g_out_ready=e_random ELSE + pulse_1 WHEN g_out_ready=e_pulse; + + + ------------------------------------------------------------------------------ + -- DATA GENERATION + ------------------------------------------------------------------------------ + + -- Generate data path input data + p_stimuli : PROCESS + VARIABLE v_data_init : NATURAL; + VARIABLE v_frame_len : NATURAL; + VARIABLE v_sync : STD_LOGIC; + BEGIN + v_data_init := c_data_init; + v_frame_len := c_frame_len_init; + in_sosi <= c_dp_sosi_rst; + proc_common_wait_until_low(clk, rst); + proc_common_wait_some_cycles(clk, 5); + + -- Begin of stimuli + FOR R IN 0 TO g_nof_repeat-1 LOOP + v_sync := sel_a_b(R MOD c_sync_period = c_sync_offset, '1', '0'); + proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data_init, 0, 0, v_frame_len, 0, 0, v_sync, TO_DP_BSN(R), clk, in_en, in_siso, in_sosi); + --proc_common_wait_some_cycles(clk, 10); + v_data_init := v_data_init + v_frame_len; + v_frame_len := v_frame_len + 1; + END LOOP; + + -- End of stimuli + expected_out_data <= TO_UVEC(v_data_init-1, c_data_w); + + proc_common_wait_until_high(clk, verify_done); + proc_common_wait_some_cycles(clk, 10); + tb_end <= '1'; + WAIT; + END PROCESS; + + -- proc_dp_gen_block_data() only supports RL=0 or 1, so use a latency adpater to support any g_in_latency + u_input_adapt : ENTITY dp_components_lib.dp_latency_adapter + GENERIC MAP ( + g_in_latency => c_rl, + g_out_latency => g_in_latency + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => in_siso, + snk_in => in_sosi, + -- ST source + src_in => adapt_siso, + src_out => adapt_sosi + ); + + + ------------------------------------------------------------------------------ + -- DATA VERIFICATION + ------------------------------------------------------------------------------ + + + -- Verification logistics + verify_en <= '1' WHEN rising_edge(clk) AND out_sosi.sop='1'; -- enable verify after first output sop + count_eop <= count_eop+1 WHEN rising_edge(clk) AND out_sosi.eop='1' AND((g_out_latency>0) OR + (g_out_latency=0 AND out_siso.ready='1')); -- count number of output eop + verify_done <= '1' WHEN rising_edge(clk) AND count_eop = g_nof_repeat; -- signal verify done after g_nof_repeat frames + + -- Actual verification of the output streams + proc_dp_verify_data("out_sosi.data", g_out_latency, clk, verify_en, out_siso.ready, out_sosi.valid, out_data, prev_out_data); -- Verify that the output is incrementing data, like the input stimuli + proc_dp_verify_valid(g_out_latency, clk, verify_en, out_siso.ready, prev_out_ready, out_sosi.valid); -- Verify that the output valid fits with the output ready latency + proc_dp_verify_sop_and_eop(g_out_latency, clk, out_siso.ready, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sop); -- Verify that sop and eop come in pairs + proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, prev_out_data); -- Verify that the stimuli have been applied at all + proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en, out_sosi.sync, out_sosi.sop, out_sosi.bsn); + + -- Monitoring + out_bsn <= out_sosi.bsn(c_data_w-1 DOWNTO 0); + out_data <= out_sosi.data(c_data_w-1 DOWNTO 0); + out_sync <= out_sosi.sync; + out_val <= out_sosi.valid; + out_sop <= out_sosi.sop; + out_eop <= out_sosi.eop; + + + ------------------------------------------------------------------------------ + -- DUT dp_pipeline_ready + ------------------------------------------------------------------------------ + + pipeline : ENTITY work.dp_pipeline_ready + GENERIC MAP ( + g_in_latency => g_in_latency, + g_out_latency => g_out_latency + ) + PORT MAP ( + rst => rst, + clk => clk, + -- ST sink + snk_out => adapt_siso, + snk_in => adapt_sosi, + -- ST source + src_in => out_siso, + src_out => out_sosi + ); + + +END tb;
astron_pipeline/trunk/tb_dp_pipeline_ready.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astron_pipeline/trunk/tb_tb_dp_pipeline.vhd =================================================================== --- astron_pipeline/trunk/tb_tb_dp_pipeline.vhd (nonexistent) +++ astron_pipeline/trunk/tb_tb_dp_pipeline.vhd (revision 2) @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2013 +-- ASTRON (Netherlands Institute for Radio Astronomy) +-- JIVE (Joint Institute for VLBI in Europe) +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +-- > as 3 +-- > run -all --> OK + +ENTITY tb_tb_dp_pipeline IS +END tb_tb_dp_pipeline; + + +ARCHITECTURE tb OF tb_tb_dp_pipeline IS + SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end' +BEGIN + + u_p0 : ENTITY work.tb_dp_pipeline GENERIC MAP (0); + u_p1 : ENTITY work.tb_dp_pipeline GENERIC MAP (1); + u_p2 : ENTITY work.tb_dp_pipeline GENERIC MAP (2); + u_p7 : ENTITY work.tb_dp_pipeline GENERIC MAP (7); + +END tb;
astron_pipeline/trunk/tb_tb_dp_pipeline.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: astron_pipeline/trunk/tb_tb_dp_pipeline_ready.vhd =================================================================== --- astron_pipeline/trunk/tb_tb_dp_pipeline_ready.vhd (nonexistent) +++ astron_pipeline/trunk/tb_tb_dp_pipeline_ready.vhd (revision 2) @@ -0,0 +1,66 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2010 +-- ASTRON (Netherlands Institute for Radio Astronomy) +-- JIVE (Joint Institute for VLBI in Europe) +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, dp_pkg_lib; +USE IEEE.std_logic_1164.ALL; +USE dp_pkg_lib.tb_dp_pkg.ALL; + + +-- > as 2 +-- > run -all --> OK + +ENTITY tb_tb_dp_pipeline_ready IS +END tb_tb_dp_pipeline_ready; + + +ARCHITECTURE tb OF tb_tb_dp_pipeline_ready IS + + CONSTANT c_nof_repeat : NATURAL := 50; + SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end' + +BEGIN + + -- in_en, src_in.ready, in_latency, out_latency, nof repeat, + -- Random flow control for different RL + u_rnd_rnd_0_0 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 0, 0, c_nof_repeat); + u_rnd_rnd_1_0 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 1, 0, c_nof_repeat); + u_rnd_rnd_0_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 0, 1, c_nof_repeat); + u_rnd_rnd_2_0 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 2, 0, c_nof_repeat); + u_rnd_rnd_0_2 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 0, 2, c_nof_repeat); + u_rnd_rnd_2_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 2, 1, c_nof_repeat); + u_rnd_rnd_1_2 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 1, 2, c_nof_repeat); + u_rnd_rnd_2_2 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 2, 2, c_nof_repeat); + + -- Other flow control for fixed RL + u_act_act_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_active, e_active, 1, 1, c_nof_repeat); + u_act_rnd_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_active, e_random, 1, 1, c_nof_repeat); + u_act_pls_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_active, e_pulse, 1, 1, c_nof_repeat); + + u_rnd_act_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_active, 1, 1, c_nof_repeat); + u_rnd_rnd_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_random, 1, 1, c_nof_repeat); + u_rnd_pls_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_random, e_pulse, 1, 1, c_nof_repeat); + + u_pls_act_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_pulse, e_active, 1, 1, c_nof_repeat); + u_pls_rnd_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_pulse, e_random, 1, 1, c_nof_repeat); + u_pls_pls_1_1 : ENTITY work.tb_dp_pipeline_ready GENERIC MAP (e_pulse, e_pulse, 1, 1, c_nof_repeat); + +END tb;
astron_pipeline/trunk/tb_tb_dp_pipeline_ready.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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