URL
https://opencores.org/ocsvn/astron_requantizer/astron_requantizer/trunk
Subversion Repositories astron_requantizer
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/astron_requantizer/trunk/common_requantize.vhd
0,0 → 1,140
------------------------------------------------------------------------------- |
-- |
-- Copyright (C) 2009 |
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> |
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
------------------------------------------------------------------------------- |
|
LIBRARY IEEE, common_pkg_lib; |
USE IEEE.std_logic_1164.ALL; |
USE IEEE.numeric_std.ALL; |
USE common_pkg_lib.common_pkg.ALL; |
|
-- Purpose: Requantize the input data to the output data width by removing |
-- LSbits and/or MSbits |
-- Description: |
-- |
-- . in_dat --> remove LSbits --> rem_dat --> remove MSbits --> shift left by c_gain_w --> out_dat |
-- |
-- . Remove LSBits by means of ROUND or TRUNCATE |
-- . Remove LSBits when c_lsb_w>0 |
-- |
-- . Remove MSBits by means of CLIP or WRAP |
-- . Remove MSbits when g_in_dat_w-c_lsb_w > g_out_dat_w: |
-- in_dat <---------------------g_in_dat_w---------------------> |
-- rem_dat <---------------------c_rem_dat_w-------><--c_lsb_w--> |
-- res_dat <-------------g_out_dat_w-------><--c_lsb_w--> |
-- |
-- . Extend MSbits when g_in_dat_w-c_lsb_w <= g_out_dat_w:: |
-- in_dat <-------------g_in_dat_w---------------------> |
-- rem_dat <-------------c_rem_dat_w-------><--c_lsb_w--> |
-- res_dat <---------------------g_out_dat_w-------><--c_lsb_w--> |
-- |
-- . Shift left res_dat before resizing to out_dat'LENGTH, which is useful to keep the res_dat in the MSbits when out_dat'LENGTH > g_out_dat_w |
-- gain_dat <-------g_out_dat_w-------><--c_gain_w--> |
-- |
-- Remarks: |
-- . It is not necessary to define g_msb_w, because the number of MSbits that |
-- need to be removed (or extended) follows from the other widths. |
|
ENTITY common_requantize IS |
GENERIC ( |
g_representation : STRING := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity) |
g_lsb_w : INTEGER := 4; -- when > 0, number of LSbits to remove from in_dat |
-- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH |
-- when 0 then no effect |
g_lsb_round : BOOLEAN := TRUE; -- when true ROUND else TRUNCATE the input LSbits |
g_lsb_round_clip : BOOLEAN := FALSE; -- when true round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding |
g_msb_clip : BOOLEAN := TRUE; -- when true CLIP else WRAP the input MSbits |
g_msb_clip_symmetric : BOOLEAN := FALSE; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm |
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric |
g_gain_w : NATURAL := 0; -- do not use, must be 0, use negative g_lsb_w instead |
g_pipeline_remove_lsb : NATURAL := 0; -- >= 0 |
g_pipeline_remove_msb : NATURAL := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output |
g_in_dat_w : NATURAL := 36; -- input data width |
g_out_dat_w : NATURAL := 18 -- output data width |
); |
PORT ( |
clk : IN STD_LOGIC; |
clken : IN STD_LOGIC := '1'; |
in_dat : IN STD_LOGIC_VECTOR; -- unconstrained slv to also support widths other than g_in_dat_w by only using [g_in_dat_w-1:0] from the in_dat slv |
out_dat : OUT STD_LOGIC_VECTOR; -- unconstrained slv to also support widths other then g_out_dat_w by resizing the result [g_out_dat_w-1:0] to the out_dat slv |
out_ovr : OUT STD_LOGIC -- out_ovr is '1' when the removal of MSbits causes clipping or wrapping |
); |
END; |
|
|
ARCHITECTURE str OF common_requantize IS |
|
-- Use c_lsb_w > 0 to remove LSBits and support c_lsb < 0 to shift in zero value LSbits as a gain |
CONSTANT c_lsb_w : NATURAL := sel_a_b(g_lsb_w > 0, g_lsb_w, 0); |
CONSTANT c_gain_w : NATURAL := sel_a_b(g_lsb_w < 0, -g_lsb_w, 0); |
|
CONSTANT c_rem_dat_w : NATURAL := g_in_dat_w-c_lsb_w; |
|
SIGNAL rem_dat : STD_LOGIC_VECTOR(c_rem_dat_w-1 DOWNTO 0); -- remaining in_dat after removing the c_lsb_w number of LSBits |
SIGNAL res_dat : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- resulting out_dat after removing the g_msb_w number of MSBits |
|
SIGNAL gain_dat : STD_LOGIC_VECTOR(g_out_dat_w+c_gain_w-1 DOWNTO 0) := (OTHERS=>'0'); -- fill extra LSBits with '0' instead of extending MSbits |
|
BEGIN |
|
ASSERT g_gain_w=0 REPORT "common_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w." SEVERITY FAILURE; |
|
-- Remove LSBits using ROUND or TRUNCATE |
u_remove_lsb : ENTITY work.common_round |
GENERIC MAP ( |
g_representation => g_representation, |
g_round => g_lsb_round, |
g_round_clip => g_lsb_round_clip, |
g_pipeline_input => 0, |
g_pipeline_output => g_pipeline_remove_lsb, |
g_in_dat_w => g_in_dat_w, |
g_out_dat_w => c_rem_dat_w |
) |
PORT MAP ( |
clk => clk, |
clken => clken, |
in_dat => in_dat(g_in_dat_w-1 DOWNTO 0), |
out_dat => rem_dat |
); |
|
-- Remove MSBits using CLIP or WRAP |
u_remove_msb : ENTITY work.common_resize |
GENERIC MAP ( |
g_representation => g_representation, |
g_pipeline_input => 0, |
g_pipeline_output => g_pipeline_remove_msb, |
g_clip => g_msb_clip, |
g_clip_symmetric => g_msb_clip_symmetric, |
g_in_dat_w => c_rem_dat_w, |
g_out_dat_w => g_out_dat_w |
) |
PORT MAP ( |
clk => clk, |
clken => clken, |
in_dat => rem_dat, |
out_dat => res_dat, |
out_ovr => out_ovr |
); |
|
-- Output gain |
gain_dat(g_out_dat_w+c_gain_w-1 DOWNTO c_gain_w) <= res_dat; |
|
out_dat <= RESIZE_SVEC(gain_dat, out_dat'LENGTH) WHEN g_representation="SIGNED" ELSE RESIZE_UVEC(gain_dat, out_dat'LENGTH); |
|
END str; |
astron_requantizer/trunk/common_requantize.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: astron_requantizer/trunk/common_resize.vhd
===================================================================
--- astron_requantizer/trunk/common_resize.vhd (nonexistent)
+++ astron_requantizer/trunk/common_resize.vhd (revision 2)
@@ -0,0 +1,138 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) "SIGNED",
+ g_pipeline => g_pipeline_input,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ PORT MAP (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => reg_dat
+ );
+
+ no_clip : IF c_clip=FALSE GENERATE
+ -- Note that g_pipeline_input=0 AND g_clip=FALSE is equivalent to using RESIZE_SVEC or RESIZE_UVEC directly.
+ gen_s : IF g_representation="SIGNED" GENERATE
+ -- If g_out_dat_w>g_in_dat_w then IEEE resize extends the sign bit,
+ -- else IEEE resize preserves the sign bit and keeps the low part.
+ wrap <= '1' WHEN SIGNED(reg_dat)>c_smax OR SIGNED(reg_dat)< c_smin_most ELSE '0';
+ res_dat <= RESIZE_SVEC(reg_dat, g_out_dat_w);
+ res_ovr <= wrap;
+ END GENERATE;
+
+ gen_u : IF g_representation="UNSIGNED" GENERATE
+ -- If g_out_dat_w>g_in_dat_w then IEEE resize sign extends with '0',
+ -- else IEEE resize keeps the low part.
+ wrap <= '1' WHEN UNSIGNED(reg_dat)>c_umax ELSE '0';
+ res_dat <= RESIZE_UVEC(reg_dat, g_out_dat_w);
+ res_ovr <= wrap;
+ END GENERATE;
+ END GENERATE;
+
+ gen_clip : IF c_clip=TRUE GENERATE
+ gen_s_clip : IF g_representation="SIGNED" GENERATE
+ clip <= '1' WHEN SIGNED(reg_dat)>c_smax OR SIGNED(reg_dat)< c_smin ELSE '0';
+ sign <= reg_dat(reg_dat'HIGH);
+ res_dat <= reg_dat(out_dat'RANGE) WHEN clip='0' ELSE STD_LOGIC_VECTOR( c_smax) WHEN sign='0' ELSE STD_LOGIC_VECTOR(c_smin);
+ res_ovr <= clip;
+ END GENERATE;
+
+ gen_u_clip : IF g_representation="UNSIGNED" GENERATE
+ clip <= '1' WHEN UNSIGNED(reg_dat)>c_umax ELSE '0';
+ res_dat <= reg_dat(out_dat'RANGE) WHEN clip='0' ELSE STD_LOGIC_VECTOR(c_umax);
+ res_ovr <= clip;
+ END GENERATE;
+ END GENERATE;
+
+ res_vec <= res_ovr & res_dat;
+
+ u_output_pipe : ENTITY common_components_lib.common_pipeline -- pipeline output
+ GENERIC MAP (
+ g_representation => "SIGNED",
+ g_pipeline => g_pipeline_output,
+ g_in_dat_w => g_out_dat_w+1,
+ g_out_dat_w => g_out_dat_w+1
+ )
+ PORT MAP (
+ clk => clk,
+ clken => clken,
+ in_dat => res_vec,
+ out_dat => out_vec
+ );
+
+ out_ovr <= out_vec(g_out_dat_w);
+ out_dat <= out_vec(g_out_dat_w-1 DOWNTO 0);
+
+END rtl;
astron_requantizer/trunk/common_resize.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: astron_requantizer/trunk/common_round.vhd
===================================================================
--- astron_requantizer/trunk/common_round.vhd (nonexistent)
+++ astron_requantizer/trunk/common_round.vhd (revision 2)
@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy)
astron_requantizer/trunk/common_round.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: astron_requantizer/trunk/dp_requantize.vhd
===================================================================
--- astron_requantizer/trunk/dp_requantize.vhd (nonexistent)
+++ astron_requantizer/trunk/dp_requantize.vhd (revision 2)
@@ -0,0 +1,186 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy)
astron_requantizer/trunk/dp_requantize.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: astron_requantizer/trunk/hdllib.cfg
===================================================================
--- astron_requantizer/trunk/hdllib.cfg (nonexistent)
+++ astron_requantizer/trunk/hdllib.cfg (revision 2)
@@ -0,0 +1,23 @@
+hdl_lib_name = dp_requantize
+hdl_library_clause_name = dp_requantize_lib
+hdl_lib_uses_synth = common_pkg common_components dp_pkg dp_pipeline common_requantize
+hdl_lib_uses_sim =
+hdl_lib_technology =
+
+synth_files =
+ common_round.vhd
+ common_resize.vhd
+ common_requantize.vhd
+
+ dp_requantize.vhd
+
+test_bench_files =
+
+
+regression_test_vhdl =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
astron_requantizer/trunk/hdllib.cfg
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property