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/cde/trunk/license/LICENSE-2.0.txt
0,0 → 1,202
 
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
 
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/cde/trunk/doc/index.html
0,0 → 1,59
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8">
<TITLE>start</TITLE>
<META NAME="GENERATOR" CONTENT="LibreOffice 3.6 (Linux)">
<META NAME="CREATED" CONTENT="0;0">
<META NAME="CHANGEDBY" CONTENT="Ouabache Designworks">
<META NAME="CHANGED" CONTENT="20130817;8220700">
<META NAME="KEYWORDS" CONTENT="start">
<META NAME="Info 3" CONTENT="">
<META NAME="Info 4" CONTENT="">
<META NAME="date" CONTENT="2008-01-08T12:01:41-0500">
<META NAME="robots" CONTENT="index,follow">
<META NAME="CHANGEDBY" CONTENT="Ouabache Designworks">
</HEAD>
<BODY LANG="en-US" DIR="LTR">
<DIV ID="toc__header" DIR="LTR">
<H1><A NAME="socgen ip"></A>CDE LIBRARY:
</H1>
<P>The Common Design Environment (CDE) is a library of verilog IP
modules for use in fpga and asic designs. One problem that we face
is that not all rtl code is synthesisable into all target processes.
The CDE project seeks to identify this problem code and provide
documented and functioning models for each case. A CDE module will
isolate the problem code inside a single module that can be easily
replaced when the design is targeted to a process that requires
substitution of custom hard macros. This can be done without
touching the users rtl code so that a single code base can support
both fpga and asic targets without modification.</P>
<P><BR><BR>
</P>
<P>CDE is part of the SOCEN design environment and uses IP-Xact
module descriptors. Documention is autogenerated and uses the gEDA
tool set.
</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
</DIV>
<DIV ID="toc__inside" DIR="LTR">
<UL>
<LI><P STYLE="margin-bottom: 0in"><A HREF="#IPModules">IP Modules</A></P>
<UL>
<LI><P><A HREF="../ip/pad/doc/html/component.html">IO Pads</A></P>
<LI><P><A HREF="../ip/sram/doc/html/component.html">Synchronous
Rams</A></P>
</UL>
</UL>
</DIV>
<P><BR><BR>
</P>
</BODY>
</HTML>
/cde/trunk/ip/sram/rtl/xml/sram_def.xml
0,0 → 1,205
<?xml version="1.0" encoding="UTF-8"?>
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xmlns:socgen="http://opencores.org"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>sram</spirit:name>
<spirit:version>def</spirit:version>
 
 
 
 
 
 
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<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
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<spirit:name>doc</spirit:name>
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<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
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<spirit:name>fs-sim</spirit:name>
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
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<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
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</spirit:fileSet>
 
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name>
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</spirit:component>
/cde/trunk/ip/sram/rtl/xml/sram_dp.xml
0,0 → 1,210
<?xml version="1.0" encoding="UTF-8"?>
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>sram</spirit:name>
<spirit:version>dp</spirit:version>
 
 
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>*simulation*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name><spirit:envIdentifier>*synthesis*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>lint</spirit:name><spirit:envIdentifier>lint</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>*documentation*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
</spirit:view>
 
 
 
 
 
</spirit:views>
 
 
 
<spirit:modelParameters>
 
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
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<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INIT_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INSTANCE_NAME</spirit:name><spirit:value>"U1"</spirit:value></spirit:modelParameter>
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<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
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<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
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<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
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<spirit:port><spirit:name>raddr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
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<spirit:wire><spirit:direction>in</spirit:direction>
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<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
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</spirit:model>
 
 
 
 
 
 
<spirit:fileSets>
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
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<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
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</spirit:fileSet>
 
 
 
 
 
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</spirit:component>
/cde/trunk/ip/sram/rtl/xml/sram_be.xml
0,0 → 1,199
<?xml version="1.0" encoding="UTF-8"?>
<!--
 
-->
<spirit:component
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>sram</spirit:name>
<spirit:version>be</spirit:version>
 
 
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
 
<spirit:view>
<spirit:name>sim</spirit:name><spirit:envIdentifier>*simulation*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
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<spirit:modelName></spirit:modelName>
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<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-lint</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
 
<spirit:view>
<spirit:name>doc</spirit:name>
<spirit:vendorExtensions>
<spirit:componentRef spirit:vendor="opencores.org"
spirit:library="Testbench"
spirit:name="toolflow"
spirit:version="documentation"/>
</spirit:vendorExtensions>
<spirit:envIdentifier>*documentation*</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
</spirit:view>
 
 
 
 
</spirit:views>
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INIT_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>INSTANCE_NAME</spirit:name><spirit:value>"U1"</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
 
<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>cs</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>wr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>rd</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>be</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>addr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
 
<spirit:port><spirit:name>wdata</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
<spirit:port><spirit:name>rdata</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>
 
 
 
</spirit:ports>
 
</spirit:model>
 
 
 
 
 
 
<spirit:fileSets>
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-lint</spirit:name>
 
 
<spirit:file>
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
 
</spirit:component>
/cde/trunk/ip/sram/rtl/verilog/sram_def.v
0,0 → 1,83
/**********************************************************************/
/* */
/* */
/* Copyright (c) 2012 Ouabache Design Works */
/* */
/* All Rights Reserved Worldwide */
/* */
/* Licensed under the Apache License,Version2.0 (the'License'); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in */
/* writing, software distributed under the License is */
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
/* OR CONDITIONS OF ANY KIND, either express or implied. */
/* See the License for the specific language governing */
/* permissions and limitations under the License. */
/**********************************************************************/
module
cde_sram_def
#( parameter
ADDR=10,
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire [ ADDR-1 : 0] addr,
input wire [ WIDTH-1 : 0] wdata,
output reg [ WIDTH-1 : 0] rdata);
// Memory Array
reg [WIDTH-1:0] mem[0:WORDS-1];
// If used as Rom then load a memory image at startup
initial
begin
if( INIT_FILE == "NONE")
begin
end
else
begin
$readmemh(INIT_FILE, mem);
end
end
 
// Write function
always@(posedge clk)
if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0];
generate
if( WRITETHRU)
begin
// Read function gets new data if also a write cycle
// latch the read addr for next cycle
reg [ADDR-1:0] l_raddr;
reg l_cycle;
 
always@(posedge clk)
begin
l_raddr <= addr;
l_cycle <= rd && cs ;
end
 
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [WIDTH-1:0] tmp_rdata;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
always@(*) rdata = tmp_rdata;
end
else
begin
// Read function gets old data if also a write cycle
always@(posedge clk)
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}];
else rdata <= DEFAULT;
end
endgenerate
endmodule
/cde/trunk/ip/sram/rtl/verilog/lint/sram_def.v
0,0 → 1,23
module
cde_sram_def
#( parameter
ADDR=10,
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire [ ADDR-1 : 0] addr,
input wire [ WIDTH-1 : 0] wdata,
output reg [ WIDTH-1 : 0] rdata);
// Simple loop back for linting and code coverage
always@(posedge clk)
if( rd && cs ) rdata <= wdata;
else rdata <= DEFAULT;
endmodule
/cde/trunk/ip/sram/rtl/verilog/lint/sram_dp.v
0,0 → 1,24
module
cde_sram_dp
#( parameter
ADDR=10,
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire [ ADDR-1 : 0] raddr,
input wire [ ADDR-1 : 0] waddr,
input wire [ WIDTH-1 : 0] wdata,
output reg [ WIDTH-1 : 0] rdata);
// Simple loop back for linting and code coverage
always@(posedge clk)
if( rd && cs ) rdata <= wdata;
else rdata <= DEFAULT;
endmodule
/cde/trunk/ip/sram/rtl/verilog/lint/sram_be.v
0,0 → 1,24
module
cde_sram_be
#( parameter
ADDR=10,
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
input wire be,
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire [ ADDR-1 : 0] addr,
input wire [ WIDTH-1 : 0] wdata,
output reg [ WIDTH-1 : 0] rdata);
// Simple loop back for linting and code coverage
always@(posedge clk)
if( rd && cs ) rdata <= wdata;
else rdata <= DEFAULT;
endmodule
/cde/trunk/ip/sram/rtl/verilog/sram_dp.v
0,0 → 1,84
/**********************************************************************/
/* */
/* */
/* Copyright (c) 2012 Ouabache Design Works */
/* */
/* All Rights Reserved Worldwide */
/* */
/* Licensed under the Apache License,Version2.0 (the'License'); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in */
/* writing, software distributed under the License is */
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
/* OR CONDITIONS OF ANY KIND, either express or implied. */
/* See the License for the specific language governing */
/* permissions and limitations under the License. */
/**********************************************************************/
module
cde_sram_dp
#( parameter
ADDR=10,
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire [ ADDR-1 : 0] raddr,
input wire [ ADDR-1 : 0] waddr,
input wire [ WIDTH-1 : 0] wdata,
output reg [ WIDTH-1 : 0] rdata);
// Memory Array
reg [WIDTH-1:0] mem[0:WORDS-1];
// If used as Rom then load a memory image at startup
initial
begin
if( INIT_FILE == "NONE")
begin
end
else
begin
$readmemh(INIT_FILE, mem);
end
end
 
// Write function
always@(posedge clk)
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0];
generate
if( WRITETHRU)
begin
// Read function gets new data if also a write cycle
// latch the read addr for next cycle
reg [ADDR-1:0] l_raddr;
reg l_cycle;
 
always@(posedge clk)
begin
l_raddr <= raddr;
l_cycle <= rd && cs ;
end
 
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [WIDTH-1:0] tmp_rdata;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
always@(*) rdata = tmp_rdata;
end
else
begin
// Read function gets old data if also a write cycle
always@(posedge clk)
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}];
else rdata <= DEFAULT;
end
endgenerate
endmodule
/cde/trunk/ip/sram/rtl/verilog/sram_be.v
0,0 → 1,88
/**********************************************************************/
/* */
/* */
/* Copyright (c) 2012 Ouabache Design Works */
/* */
/* All Rights Reserved Worldwide */
/* */
/* Licensed under the Apache License,Version2.0 (the'License'); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in */
/* writing, software distributed under the License is */
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
/* OR CONDITIONS OF ANY KIND, either express or implied. */
/* See the License for the specific language governing */
/* permissions and limitations under the License. */
/**********************************************************************/
module
cde_sram_be
#( parameter
ADDR=10,
WIDTH=8,
WORDS=1024,
WRITETHRU=0,
DEFAULT={WIDTH{1'b1}},
INIT_FILE="NONE",
INSTANCE_NAME="U1")
(
 
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire be,
input wire [ ADDR-1 : 0] addr,
input wire [ WIDTH-1 : 0] wdata,
output reg [ WIDTH-1 : 0] rdata);
// Memory Array
reg [WIDTH-1:0] mem[0:WORDS-1];
// If used as Rom then load a memory image at startup
initial
begin
if( INIT_FILE == "NONE")
begin
end
else
begin
$readmemh(INIT_FILE, mem);
end
end
 
// Write function
always@(posedge clk)
if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0];
generate
if( WRITETHRU)
begin
// Read function gets new data if also a write cycle
// latch the read addr for next cycle
reg [ADDR-1:0] l_raddr;
reg l_cycle;
 
always@(posedge clk)
begin
l_raddr <= addr;
l_cycle <= rd && cs ;
end
 
 
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [7:0] tmp_rdata;
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
always@(*) rdata = tmp_rdata;
end
else
begin
// Read function gets old data if also a write cycle
always@(posedge clk)
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}];
else rdata <= DEFAULT;
end
endgenerate
endmodule
/cde/trunk/ip/sram/componentCfg.xml
0,0 → 1,164
<?xml version="1.0" encoding="UTF-8"?>
<!--
 
-->
<socgen:componentConfiguration
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
<socgen:vendor>opencores.org</socgen:vendor>
<socgen:library>cde</socgen:library>
<socgen:component>sram</socgen:component>
 
 
<socgen:ip_name_depth>3</socgen:ip_name_depth>
<socgen:ip_name_vendor_sep>_</socgen:ip_name_vendor_sep>
<socgen:ip_name_library_sep>_</socgen:ip_name_library_sep>
<socgen:ip_name_version_sep>_</socgen:ip_name_version_sep>
<socgen:ip_name_base_macro>VARIANT</socgen:ip_name_base_macro>
 
 
 
<socgen:doc>
 
<socgen:library_path>/ip/sram/doc</socgen:library_path>
 
 
 
<socgen:versions>
 
<socgen:version>
<socgen:name>def</socgen:name>
<socgen:description>Synchronous one-port ram</socgen:description>
</socgen:version>
 
<socgen:version>
<socgen:name>dp</socgen:name>
<socgen:description>Synchronous two-port ram with seperate read/write ports</socgen:description>
</socgen:version>
 
<socgen:version>
<socgen:name>be</socgen:name>
<socgen:description>Synchronous one-port ram with byte enable</socgen:description>
</socgen:version>
 
 
 
</socgen:versions>
 
 
<socgen:parameters>
 
<socgen:parameter>
<socgen:name>ADDR</socgen:name>
<socgen:description>Number of address bits</socgen:description>
</socgen:parameter>
 
<socgen:parameter>
<socgen:name>WIDTH</socgen:name>
<socgen:description>Number of data bits</socgen:description>
</socgen:parameter>
 
<socgen:parameter>
<socgen:name>WORDS</socgen:name>
<socgen:description>Number of memory words. Must be fully addressable by ADDR address bits</socgen:description>
</socgen:parameter>
 
<socgen:parameter>
<socgen:name>WRITETHRU</socgen:name>
<socgen:description>If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new</socgen:description>
</socgen:parameter>
 
<socgen:parameter>
<socgen:name>DEFAULT</socgen:name>
<socgen:description>Output read value if cs and rd are not both active </socgen:description>
</socgen:parameter>
 
<socgen:parameter>
<socgen:name>INIT_FILE</socgen:name>
<socgen:description>Filename of memory image loaded at startup</socgen:description>
</socgen:parameter>
 
<socgen:parameter>
<socgen:name>INSTANCE_NAME</socgen:name>
<socgen:description>Instance name of sram. Only needed for asic tool flows</socgen:description>
</socgen:parameter>
 
 
 
</socgen:parameters>
 
 
 
<socgen:interfaces>
 
<socgen:interface>
<socgen:name>addr</socgen:name>
<socgen:description>Memory address bits</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>raddr</socgen:name>
<socgen:description>Memory read address bits</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>waddr</socgen:name>
<socgen:description>Memory write address bits</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>clk</socgen:name>
<socgen:description>Active high clock</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>cs</socgen:name>
<socgen:description>Active high chip select</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>rd</socgen:name>
<socgen:description>Active high read enable</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>wr</socgen:name>
<socgen:description>Active high write enable</socgen:description>
</socgen:interface>
 
 
<socgen:interface>
<socgen:name>be</socgen:name>
<socgen:description>Active high byte enable</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>rdata</socgen:name>
<socgen:description>read data out</socgen:description>
</socgen:interface>
 
<socgen:interface>
<socgen:name>wdata</socgen:name>
<socgen:description>write data in</socgen:description>
</socgen:interface>
 
 
</socgen:interfaces>
 
 
 
 
 
 
 
 
</socgen:doc>
 
 
 
 
 
</socgen:componentConfiguration>
 
/cde/trunk/ip/sram/doc/Geda/html/cde_sram_dp.html
0,0 → 1,233
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8">
<title>start</title>
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
<meta name="CREATED" content="0;0">
<meta name="CHANGED" content="20090513;8521600">
<meta name="KEYWORDS" content="start">
<meta name="Info 3" content="">
<meta name="Info 4" content="">
<meta name="date" content="2008-01-08T12:01:41-0500">
<meta name="robots" content="index,follow">
</head>
<body dir="ltr" lang="en-US">
<h1><a name="cde_sram_dp"></a>SOCGEN Datasheet:<br>
</h1>
<div id="toc__inside" dir="ltr">
<ul>
<li>
<p style="margin-bottom: 0in;"><a href="#cde_sram_dp">cde_sram_dp<br>
</a></p>
<br>
<br> Synchronous two-port ram with seperate read/write ports
<br>
<li>
<p><a href="../src/cde_sram_dp.v">SourceCode <br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Parameters">Parameters<br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Interface">Interface<br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Children">Children<br>
</a></p>
</li>
<li>
<p><a href="../../html/cde_sram_dp.html#TheoryofOperation">Theory of Operation<br>
</a></p>
</li>
</ul>
</li>
</ul>
</div>
<img style="width: 683px; height: 278px;" alt="" src="../png/cde_sram_dp_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
<br>
</b>
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Name<br> </td>
<td style="vertical-align: top;">default <br> </td>
<td style="vertical-align: top;">Description<br></td>
</tr>
<tr>
<td style="vertical-align: top;">ADDR<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of address bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WIDTH<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of data bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WORDS<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WRITETHRU<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">DEFAULT<br> </td>
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td>
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">INIT_FILE<br> </td>
<td style="vertical-align: top;">"NONE"<br> </td>
<td style="vertical-align: top;">Filename of memory image loaded at startup<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">INSTANCE_NAME<br> </td>
<td style="vertical-align: top;">"U1"<br> </td>
<td style="vertical-align: top;">Instance name of sram. Only needed for asic tool flows<br></td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<p><br>
</p>
<p><b><b><br>
</b></b></p>
<p><b><b><br>
<br>
</b></b></p>
<h2><b><b><a name="Interface"></a>Interface</b><b>&nbsp;<br>
</b></b></h2>
<p style="margin-bottom: 0in;"></p>
<br>
<br>
<br>
<table style="text-align: left; width: 640px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">NAME<br> </td>
<td style="vertical-align: top;">Type<br> </td>
<td style="vertical-align: top;">Description<br> </td>
</tr>
<tr>
<td style="vertical-align: top;">clk<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high clock<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cs<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high chip select<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">raddr[ADDR-1:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Memory read address bits<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">rd<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high read enable<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">rdata[WIDTH-1:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;">read data out<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">waddr[ADDR-1:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Memory write address bits<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">wdata[WIDTH-1:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">write data in<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">wr<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high write enable<br> </td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<h2><b><a name="Children"></a>Children<br></b></h2>
<b><br>
</b>
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Instance<br> </td>
<td style="vertical-align: top;">Vendor<br> </td>
<td style="vertical-align: top;">Library<br></td>
<td style="vertical-align: top;">Component<br></td>
<td style="vertical-align: top;">Version<br></td>
</tr>
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<br>
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/cde/trunk/ip/sram/doc/Geda/html/cde_sram_be.html
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8">
<title>start</title>
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
<meta name="CREATED" content="0;0">
<meta name="CHANGED" content="20090513;8521600">
<meta name="KEYWORDS" content="start">
<meta name="Info 3" content="">
<meta name="Info 4" content="">
<meta name="date" content="2008-01-08T12:01:41-0500">
<meta name="robots" content="index,follow">
</head>
<body dir="ltr" lang="en-US">
<h1><a name="cde_sram_be"></a>SOCGEN Datasheet:<br>
</h1>
<div id="toc__inside" dir="ltr">
<ul>
<li>
<p style="margin-bottom: 0in;"><a href="#cde_sram_be">cde_sram_be<br>
</a></p>
<br>
<br> Synchronous one-port ram with byte enable
<br>
<li>
<p><a href="../src/cde_sram_be.v">SourceCode <br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Parameters">Parameters<br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Interface">Interface<br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Children">Children<br>
</a></p>
</li>
<li>
<p><a href="../../html/cde_sram_be.html#TheoryofOperation">Theory of Operation<br>
</a></p>
</li>
</ul>
</li>
</ul>
</div>
<img style="width: 683px; height: 278px;" alt="" src="../png/cde_sram_be_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
<br>
</b>
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Name<br> </td>
<td style="vertical-align: top;">default <br> </td>
<td style="vertical-align: top;">Description<br></td>
</tr>
<tr>
<td style="vertical-align: top;">ADDR<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of address bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WIDTH<br> </td>
<td style="vertical-align: top;">8<br> </td>
<td style="vertical-align: top;">Number of data bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WORDS<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WRITETHRU<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">DEFAULT<br> </td>
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td>
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">INIT_FILE<br> </td>
<td style="vertical-align: top;">"NONE"<br> </td>
<td style="vertical-align: top;">Filename of memory image loaded at startup<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">INSTANCE_NAME<br> </td>
<td style="vertical-align: top;">"U1"<br> </td>
<td style="vertical-align: top;">Instance name of sram. Only needed for asic tool flows<br></td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<p><br>
</p>
<p><b><b><br>
</b></b></p>
<p><b><b><br>
<br>
</b></b></p>
<h2><b><b><a name="Interface"></a>Interface</b><b>&nbsp;<br>
</b></b></h2>
<p style="margin-bottom: 0in;"></p>
<br>
<br>
<br>
<table style="text-align: left; width: 640px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">NAME<br> </td>
<td style="vertical-align: top;">Type<br> </td>
<td style="vertical-align: top;">Description<br> </td>
</tr>
<tr>
<td style="vertical-align: top;">addr[ADDR-1:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Memory address bits<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">be<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high byte enable<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">clk<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high clock<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cs<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high chip select<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">rd<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high read enable<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">rdata[WIDTH-1:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;">read data out<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">wdata[WIDTH-1:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">write data in<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">wr<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high write enable<br> </td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<h2><b><a name="Children"></a>Children<br></b></h2>
<b><br>
</b>
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Instance<br> </td>
<td style="vertical-align: top;">Vendor<br> </td>
<td style="vertical-align: top;">Library<br></td>
<td style="vertical-align: top;">Component<br></td>
<td style="vertical-align: top;">Version<br></td>
</tr>
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<img style="width: 683px; height: 278px;" alt="" src="../png/cde_sram_be_sch.png"><br>
<b><br>
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/cde/trunk/ip/sram/doc/Geda/html/cde_sram_def.html
0,0 → 1,227
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html>
<head>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8">
<title>start</title>
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
<meta name="CREATED" content="0;0">
<meta name="CHANGED" content="20090513;8521600">
<meta name="KEYWORDS" content="start">
<meta name="Info 3" content="">
<meta name="Info 4" content="">
<meta name="date" content="2008-01-08T12:01:41-0500">
<meta name="robots" content="index,follow">
</head>
<body dir="ltr" lang="en-US">
<h1><a name="cde_sram_def"></a>SOCGEN Datasheet:<br>
</h1>
<div id="toc__inside" dir="ltr">
<ul>
<li>
<p style="margin-bottom: 0in;"><a href="#cde_sram_def">cde_sram_def<br>
</a></p>
<br>
<br> Synchronous one-port ram
<br>
<li>
<p><a href="../src/cde_sram_def.v">SourceCode <br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Parameters">Parameters<br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Interface">Interface<br>
</a></p>
</li>
<li>
<p style="margin-bottom: 0in;"><a href="#Children">Children<br>
</a></p>
</li>
<li>
<p><a href="../../html/cde_sram_def.html#TheoryofOperation">Theory of Operation<br>
</a></p>
</li>
</ul>
</li>
</ul>
</div>
<img style="width: 683px; height: 254px;" alt="" src="../png/cde_sram_def_sym.png"><br>
<b><br>
<h2><b><a name="Parameters"></a>Parameters<br></b></h2>
<b><br>
<br>
</b>
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Name<br> </td>
<td style="vertical-align: top;">default <br> </td>
<td style="vertical-align: top;">Description<br></td>
</tr>
<tr>
<td style="vertical-align: top;">ADDR<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of address bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WIDTH<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of data bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WORDS<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">WRITETHRU<br> </td>
<td style="vertical-align: top;">0<br> </td>
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">DEFAULT<br> </td>
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td>
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">INIT_FILE<br> </td>
<td style="vertical-align: top;">"NONE"<br> </td>
<td style="vertical-align: top;">Filename of memory image loaded at startup<br></td>
</tr>
 
<tr>
<td style="vertical-align: top;">INSTANCE_NAME<br> </td>
<td style="vertical-align: top;">"U1"<br> </td>
<td style="vertical-align: top;">Instance name of sram. Only needed for asic tool flows<br></td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<p><br>
</p>
<p><b><b><br>
</b></b></p>
<p><b><b><br>
<br>
</b></b></p>
<h2><b><b><a name="Interface"></a>Interface</b><b>&nbsp;<br>
</b></b></h2>
<p style="margin-bottom: 0in;"></p>
<br>
<br>
<br>
<table style="text-align: left; width: 640px; height: 120px;" border="8"
cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">NAME<br> </td>
<td style="vertical-align: top;">Type<br> </td>
<td style="vertical-align: top;">Description<br> </td>
</tr>
<tr>
<td style="vertical-align: top;">addr[ADDR-1:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Memory address bits<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">clk<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high clock<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">cs<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high chip select<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">rd<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high read enable<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">rdata[WIDTH-1:0 ]<br> </td>
<td style="vertical-align: top;">output<br> </td>
<td style="vertical-align: top;">read data out<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">wdata[WIDTH-1:0 ]<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">write data in<br> </td>
</tr>
 
<tr>
<td style="vertical-align: top;">wr<br> </td>
<td style="vertical-align: top;">input<br> </td>
<td style="vertical-align: top;">Active high write enable<br> </td>
</tr>
 
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<h2><b><a name="Children"></a>Children<br></b></h2>
<b><br>
</b>
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
<tbody>
<tr>
<td style="vertical-align: top;">Instance<br> </td>
<td style="vertical-align: top;">Vendor<br> </td>
<td style="vertical-align: top;">Library<br></td>
<td style="vertical-align: top;">Component<br></td>
<td style="vertical-align: top;">Version<br></td>
</tr>
</tbody>
</table>
<p><b><b><br>
</b></b></p>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<img style="width: 683px; height: 254px;" alt="" src="../png/cde_sram_def_sch.png"><br>
<b><br>
<br>
<br>
<br>
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cde/trunk/ip/sram/doc/Geda/png/cde_sram_be_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/sram/doc/Geda/src/cde_sram_def.v =================================================================== --- cde/trunk/ip/sram/doc/Geda/src/cde_sram_def.v (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/src/cde_sram_def.v (revision 2) @@ -0,0 +1,83 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + module + cde_sram_def + #( parameter + ADDR=10, + WIDTH=8, + WORDS=1024, + WRITETHRU=0, + DEFAULT={WIDTH{1'b1}}, + INIT_FILE="NONE", + INSTANCE_NAME="U1") + ( + input wire clk, + input wire cs, + input wire rd, + input wire wr, + input wire [ ADDR-1 : 0] addr, + input wire [ WIDTH-1 : 0] wdata, + output reg [ WIDTH-1 : 0] rdata); +// Memory Array +reg [WIDTH-1:0] mem[0:WORDS-1]; +// If used as Rom then load a memory image at startup +initial + begin + if( INIT_FILE == "NONE") + begin + end + else + begin + $readmemh(INIT_FILE, mem); + end + end + +// Write function +always@(posedge clk) + if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; +generate +if( WRITETHRU) + begin + // Read function gets new data if also a write cycle + // latch the read addr for next cycle + reg [ADDR-1:0] l_raddr; + reg l_cycle; + + always@(posedge clk) + begin + l_raddr <= addr; + l_cycle <= rd && cs ; + end + + // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block + wire [WIDTH-1:0] tmp_rdata; + assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; + always@(*) rdata = tmp_rdata; + end +else + begin + // Read function gets old data if also a write cycle + always@(posedge clk) + if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; + else rdata <= DEFAULT; + end +endgenerate + endmodule Index: cde/trunk/ip/sram/doc/Geda/src/cde_sram_dp.v =================================================================== --- cde/trunk/ip/sram/doc/Geda/src/cde_sram_dp.v (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/src/cde_sram_dp.v (revision 2) @@ -0,0 +1,84 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + module + cde_sram_dp + #( parameter + ADDR=10, + WIDTH=8, + WORDS=1024, + WRITETHRU=0, + DEFAULT={WIDTH{1'b1}}, + INIT_FILE="NONE", + INSTANCE_NAME="U1") + ( + input wire clk, + input wire cs, + input wire rd, + input wire wr, + input wire [ ADDR-1 : 0] raddr, + input wire [ ADDR-1 : 0] waddr, + input wire [ WIDTH-1 : 0] wdata, + output reg [ WIDTH-1 : 0] rdata); +// Memory Array +reg [WIDTH-1:0] mem[0:WORDS-1]; +// If used as Rom then load a memory image at startup +initial + begin + if( INIT_FILE == "NONE") + begin + end + else + begin + $readmemh(INIT_FILE, mem); + end + end + +// Write function +always@(posedge clk) + if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; +generate +if( WRITETHRU) + begin + // Read function gets new data if also a write cycle + // latch the read addr for next cycle + reg [ADDR-1:0] l_raddr; + reg l_cycle; + + always@(posedge clk) + begin + l_raddr <= raddr; + l_cycle <= rd && cs ; + end + + // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block + wire [WIDTH-1:0] tmp_rdata; + assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; + always@(*) rdata = tmp_rdata; + end +else + begin + // Read function gets old data if also a write cycle + always@(posedge clk) + if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; + else rdata <= DEFAULT; + end +endgenerate + endmodule Index: cde/trunk/ip/sram/doc/Geda/src/cde_sram_be.v =================================================================== --- cde/trunk/ip/sram/doc/Geda/src/cde_sram_be.v (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/src/cde_sram_be.v (revision 2) @@ -0,0 +1,88 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + module + cde_sram_be + #( parameter + ADDR=10, + WIDTH=8, + WORDS=1024, + WRITETHRU=0, + DEFAULT={WIDTH{1'b1}}, + INIT_FILE="NONE", + INSTANCE_NAME="U1") + ( + + input wire clk, + input wire cs, + input wire rd, + input wire wr, + input wire be, + + input wire [ ADDR-1 : 0] addr, + input wire [ WIDTH-1 : 0] wdata, + output reg [ WIDTH-1 : 0] rdata); +// Memory Array +reg [WIDTH-1:0] mem[0:WORDS-1]; +// If used as Rom then load a memory image at startup +initial + begin + if( INIT_FILE == "NONE") + begin + end + else + begin + $readmemh(INIT_FILE, mem); + end + end + +// Write function +always@(posedge clk) + if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; +generate +if( WRITETHRU) + begin + // Read function gets new data if also a write cycle + // latch the read addr for next cycle + reg [ADDR-1:0] l_raddr; + reg l_cycle; + + always@(posedge clk) + begin + l_raddr <= addr; + l_cycle <= rd && cs ; + end + + + // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block + + wire [7:0] tmp_rdata; + assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; + always@(*) rdata = tmp_rdata; + end +else + begin + // Read function gets old data if also a write cycle + always@(posedge clk) + if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; + else rdata <= DEFAULT; + end +endgenerate + endmodule Index: cde/trunk/ip/sram/doc/Geda/sym/cde_sram_def.sym =================================================================== --- cde/trunk/ip/sram/doc/Geda/sym/cde_sram_def.sym (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/sym/cde_sram_def.sym (revision 2) @@ -0,0 +1,55 @@ +v 20100214 1 +B 300 0 3600 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1650 5 10 1 1 0 0 1 1 +device=cde_sram_def +T 400 1850 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=wdata[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=addr[ADDR-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=wr +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=rd +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=cs +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 3900 200 4200 200 10 1 1 +{ +T 3800 200 5 10 1 1 0 7 1 1 +pinnumber=rdata[WIDTH-1:0] +T 3800 200 5 10 0 1 0 7 1 1 +pinseq=7 +} Index: cde/trunk/ip/sram/doc/Geda/sym/cde_sram_dp.sym =================================================================== --- cde/trunk/ip/sram/doc/Geda/sym/cde_sram_dp.sym (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/sym/cde_sram_dp.sym (revision 2) @@ -0,0 +1,62 @@ +v 20100214 1 +B 300 0 3600 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=cde_sram_dp +T 400 2050 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=wdata[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=waddr[ADDR-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 10 1 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=raddr[ADDR-1:0] +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=wr +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=rd +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=cs +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 3900 200 4200 200 10 1 1 +{ +T 3800 200 5 10 1 1 0 7 1 1 +pinnumber=rdata[WIDTH-1:0] +T 3800 200 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: cde/trunk/ip/sram/doc/Geda/sym/cde_sram_be.sym =================================================================== --- cde/trunk/ip/sram/doc/Geda/sym/cde_sram_be.sym (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/sym/cde_sram_be.sym (revision 2) @@ -0,0 +1,62 @@ +v 20100214 1 +B 300 0 3600 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 1850 5 10 1 1 0 0 1 1 +device=cde_sram_be +T 400 2050 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=wdata[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 10 1 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=addr[ADDR-1:0] +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 300 600 0 600 4 0 1 +{ +T 400 600 5 10 1 1 0 1 1 1 +pinnumber=wr +T 400 600 5 10 0 1 0 1 1 1 +pinseq=3 +} +P 300 800 0 800 4 0 1 +{ +T 400 800 5 10 1 1 0 1 1 1 +pinnumber=rd +T 400 800 5 10 0 1 0 1 1 1 +pinseq=4 +} +P 300 1000 0 1000 4 0 1 +{ +T 400 1000 5 10 1 1 0 1 1 1 +pinnumber=cs +T 400 1000 5 10 0 1 0 1 1 1 +pinseq=5 +} +P 300 1200 0 1200 4 0 1 +{ +T 400 1200 5 10 1 1 0 1 1 1 +pinnumber=clk +T 400 1200 5 10 0 1 0 1 1 1 +pinseq=6 +} +P 300 1400 0 1400 4 0 1 +{ +T 400 1400 5 10 1 1 0 1 1 1 +pinnumber=be +T 400 1400 5 10 0 1 0 1 1 1 +pinseq=7 +} +P 3900 200 4200 200 10 1 1 +{ +T 3800 200 5 10 1 1 0 7 1 1 +pinnumber=rdata[WIDTH-1:0] +T 3800 200 5 10 0 1 0 7 1 1 +pinseq=8 +} Index: cde/trunk/ip/sram/doc/Geda/sch/cde_sram_be.sch =================================================================== --- cde/trunk/ip/sram/doc/Geda/sch/cde_sram_be.sch (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/sch/cde_sram_be.sch (revision 2) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1800 300 1 0 0 in_port_v.sym +{ +T 1800 300 5 10 1 1 0 6 1 1 +refdes=wdata[WIDTH-1:0] +} +C 1800 700 1 0 0 in_port_v.sym +{ +T 1800 700 5 10 1 1 0 6 1 1 +refdes=addr[ADDR-1:0] +} +C 1800 1100 1 0 0 in_port.sym +{ +T 1800 1100 5 10 1 1 0 6 1 1 +refdes=wr +} +C 1800 1500 1 0 0 in_port.sym +{ +T 1800 1500 5 10 1 1 0 6 1 1 +refdes=rd +} +C 1800 1900 1 0 0 in_port.sym +{ +T 1800 1900 5 10 1 1 0 6 1 1 +refdes=cs +} +C 1800 2300 1 0 0 in_port.sym +{ +T 1800 2300 5 10 1 1 0 6 1 1 +refdes=clk +} +C 1800 2700 1 0 0 in_port.sym +{ +T 1800 2700 5 10 1 1 0 6 1 1 +refdes=be +} +C 4700 300 1 0 0 out_port_v.sym +{ +T 5700 300 5 10 1 1 0 0 1 1 +refdes=rdata[WIDTH-1:0] +} Index: cde/trunk/ip/sram/doc/Geda/sch/cde_sram_def.sch =================================================================== --- cde/trunk/ip/sram/doc/Geda/sch/cde_sram_def.sch (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/sch/cde_sram_def.sch (revision 2) @@ -0,0 +1,36 @@ +v 20100214 1 +C 1800 300 1 0 0 in_port_v.sym +{ +T 1800 300 5 10 1 1 0 6 1 1 +refdes=wdata[WIDTH-1:0] +} +C 1800 700 1 0 0 in_port_v.sym +{ +T 1800 700 5 10 1 1 0 6 1 1 +refdes=addr[ADDR-1:0] +} +C 1800 1100 1 0 0 in_port.sym +{ +T 1800 1100 5 10 1 1 0 6 1 1 +refdes=wr +} +C 1800 1500 1 0 0 in_port.sym +{ +T 1800 1500 5 10 1 1 0 6 1 1 +refdes=rd +} +C 1800 1900 1 0 0 in_port.sym +{ +T 1800 1900 5 10 1 1 0 6 1 1 +refdes=cs +} +C 1800 2300 1 0 0 in_port.sym +{ +T 1800 2300 5 10 1 1 0 6 1 1 +refdes=clk +} +C 4700 300 1 0 0 out_port_v.sym +{ +T 5700 300 5 10 1 1 0 0 1 1 +refdes=rdata[WIDTH-1:0] +} Index: cde/trunk/ip/sram/doc/Geda/sch/cde_sram_dp.sch =================================================================== --- cde/trunk/ip/sram/doc/Geda/sch/cde_sram_dp.sch (nonexistent) +++ cde/trunk/ip/sram/doc/Geda/sch/cde_sram_dp.sch (revision 2) @@ -0,0 +1,41 @@ +v 20100214 1 +C 1800 300 1 0 0 in_port_v.sym +{ +T 1800 300 5 10 1 1 0 6 1 1 +refdes=wdata[WIDTH-1:0] +} +C 1800 700 1 0 0 in_port_v.sym +{ +T 1800 700 5 10 1 1 0 6 1 1 +refdes=waddr[ADDR-1:0] +} +C 1800 1100 1 0 0 in_port_v.sym +{ +T 1800 1100 5 10 1 1 0 6 1 1 +refdes=raddr[ADDR-1:0] +} +C 1800 1500 1 0 0 in_port.sym +{ +T 1800 1500 5 10 1 1 0 6 1 1 +refdes=wr +} +C 1800 1900 1 0 0 in_port.sym +{ +T 1800 1900 5 10 1 1 0 6 1 1 +refdes=rd +} +C 1800 2300 1 0 0 in_port.sym +{ +T 1800 2300 5 10 1 1 0 6 1 1 +refdes=cs +} +C 1800 2700 1 0 0 in_port.sym +{ +T 1800 2700 5 10 1 1 0 6 1 1 +refdes=clk +} +C 4700 300 1 0 0 out_port_v.sym +{ +T 5700 300 5 10 1 1 0 0 1 1 +refdes=rdata[WIDTH-1:0] +} Index: cde/trunk/ip/sram/doc/gafrc =================================================================== --- cde/trunk/ip/sram/doc/gafrc (nonexistent) +++ cde/trunk/ip/sram/doc/gafrc (revision 2) @@ -0,0 +1,10 @@ +; -*-Scheme-*- +;;; +;;; Add the default component libraries +;;; + + + + +(component-library-search "./sym" "sym" ) + Index: cde/trunk/ip/sram/doc/html/cde_sram_dp.html =================================================================== --- cde/trunk/ip/sram/doc/html/cde_sram_dp.html (nonexistent) +++ cde/trunk/ip/sram/doc/html/cde_sram_dp.html (revision 2) @@ -0,0 +1,45 @@ + + + + + start + + + + + + + + + + + + +

SOCGEN Datasheet:

+ +



+

+

Theory of +Operation

+

The synchronous ram modules provide a variety of memory storage +options.
Both reads and writes are synchronous to the rising edge +of clk.
Memory may be initialized from a bit file and later +overwritten by memory writes.
If WRITETHRU is set to 1 then a +simultaneous read/write to the same address will read the new data. +
If set to 0 it will return the old.
Setting DEFAULT +determines the value of rdata when a read is not +occurring


















































































+

+ + \ No newline at end of file Index: cde/trunk/ip/sram/doc/html/component.html =================================================================== --- cde/trunk/ip/sram/doc/html/component.html (nonexistent) +++ cde/trunk/ip/sram/doc/html/component.html (revision 2) @@ -0,0 +1,44 @@ + + + + + start + + + + + + + + + + +
+

SOCGEN IP:
+

+
+
+ +
+
+

+ + Index: cde/trunk/ip/sram/doc/html/cde_sram_be.html =================================================================== --- cde/trunk/ip/sram/doc/html/cde_sram_be.html (nonexistent) +++ cde/trunk/ip/sram/doc/html/cde_sram_be.html (revision 2) @@ -0,0 +1,45 @@ + + + + + start + + + + + + + + + + + + +

SOCGEN Datasheet:

+ +



+

+

Theory of +Operation

+

The synchronous ram modules provide a variety of memory storage +options.
Both reads and writes are synchronous to the rising edge +of clk.
Memory may be initialized from a bit file and later +overwritten by memory writes.
If WRITETHRU is set to 1 then a +simultaneous read/write to the same address will read the new data. +
If set to 0 it will return the old.
Setting DEFAULT +determines the value of rdata when a read is not +occurring


















































































+

+ + \ No newline at end of file Index: cde/trunk/ip/sram/doc/html/cde_sram_def.html =================================================================== --- cde/trunk/ip/sram/doc/html/cde_sram_def.html (nonexistent) +++ cde/trunk/ip/sram/doc/html/cde_sram_def.html (revision 2) @@ -0,0 +1,45 @@ + + + + + start + + + + + + + + + + + + +

SOCGEN Datasheet:

+ +



+

+

Theory of +Operation

+

The synchronous ram modules provide a variety of memory storage +options.
Both reads and writes are synchronous to the rising edge +of clk.
Memory may be initialized from a bit file and later +overwritten by memory writes.
If WRITETHRU is set to 1 then a +simultaneous read/write to the same address will read the new data. +
If set to 0 it will return the old.
Setting DEFAULT +determines the value of rdata when a read is not +occurring


















































































+

+ + \ No newline at end of file Index: cde/trunk/ip/sram/doc/png/sram_timing.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/sram/doc/png/sram_timing.png =================================================================== --- cde/trunk/ip/sram/doc/png/sram_timing.png (nonexistent) +++ cde/trunk/ip/sram/doc/png/sram_timing.png (revision 2)
cde/trunk/ip/sram/doc/png/sram_timing.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/sram/doc/mk_png =================================================================== --- cde/trunk/ip/sram/doc/mk_png (nonexistent) +++ cde/trunk/ip/sram/doc/mk_png (revision 2) @@ -0,0 +1,2 @@ +mk_sch_png sram_timing; +
cde/trunk/ip/sram/doc/mk_png Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: cde/trunk/ip/sram/doc/sch/sram_timing.sch =================================================================== --- cde/trunk/ip/sram/doc/sch/sram_timing.sch (nonexistent) +++ cde/trunk/ip/sram/doc/sch/sram_timing.sch (revision 2) @@ -0,0 +1,93 @@ +v 20121203 2 +B 2800 600 4300 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 3000 2700 9 10 1 0 0 0 1 +addr +T 3100 3000 9 10 1 0 0 0 1 +clk +T 3200 2400 9 10 1 0 0 0 1 +cs +T 3200 2100 9 10 1 0 0 0 1 +wr +T 3200 1800 9 10 1 0 0 0 1 +rd +T 3200 1500 9 10 1 0 0 0 1 +be +T 3000 1200 9 10 1 0 0 0 1 +wdata +T 3100 900 9 10 1 0 0 0 1 +rdata +L 3600 3000 3700 3000 3 0 1 0 -1 -1 +L 3700 3000 3800 3200 3 0 1 0 -1 -1 +L 3800 3200 4100 3200 3 0 1 0 -1 -1 +L 4100 3200 4200 3000 3 0 1 0 -1 -1 +L 4200 3000 4500 3000 3 0 1 0 -1 -1 +L 4500 3000 4600 3200 3 0 1 0 -1 -1 +L 4600 3200 4900 3200 3 0 1 0 -1 -1 +L 4900 3200 5000 3000 3 0 1 0 -1 -1 +L 5000 3000 5300 3000 3 0 1 0 -1 -1 +L 5300 3000 5400 3200 3 0 1 0 -1 -1 +L 5400 3200 5700 3200 3 0 1 0 -1 -1 +L 5700 3200 5800 3000 3 0 1 0 -1 -1 +L 5800 3000 6100 3000 3 0 1 0 -1 -1 +L 6100 3000 6200 3200 3 0 1 0 -1 -1 +L 6200 3200 6500 3200 3 0 1 0 -1 -1 +L 3600 2700 4500 2700 3 0 1 0 -1 -1 +L 4500 2700 4600 2900 3 0 1 0 -1 -1 +L 4600 2900 5300 2900 3 0 1 0 -1 -1 +L 5300 2900 5400 2700 3 0 1 0 -1 -1 +L 5400 2700 6500 2700 3 0 1 0 -1 -1 +L 3600 2900 4500 2900 3 0 1 0 -1 -1 +L 4500 2900 4600 2700 3 0 1 0 -1 -1 +L 4600 2700 5300 2700 3 0 1 0 -1 -1 +L 5300 2700 5400 2900 3 0 1 0 -1 -1 +L 5400 2900 6500 2900 3 0 1 0 -1 -1 +L 3600 2400 4500 2400 3 0 1 0 -1 -1 +L 4500 2400 4600 2600 3 0 1 0 -1 -1 +L 4600 2600 5300 2600 3 0 1 0 -1 -1 +L 5300 2600 5400 2400 3 0 1 0 -1 -1 +L 5400 2400 6500 2400 3 0 1 0 -1 -1 +L 3600 2100 4500 2100 3 0 1 0 -1 -1 +L 4500 2100 4600 2300 3 0 1 0 -1 -1 +L 4600 2300 5300 2300 3 0 1 0 -1 -1 +L 5300 2300 5400 2100 3 0 1 0 -1 -1 +L 5400 2100 6500 2100 3 0 1 0 -1 -1 +L 3600 1800 4500 1800 3 0 1 0 -1 -1 +L 4500 1800 4600 2000 3 0 1 0 -1 -1 +L 4600 2000 5300 2000 3 0 1 0 -1 -1 +L 5300 2000 5400 1800 3 0 1 0 -1 -1 +L 5400 1800 6500 1800 3 0 1 0 -1 -1 +L 3600 1500 4500 1500 3 0 1 0 -1 -1 +L 4500 1500 4600 1700 3 0 1 0 -1 -1 +L 4600 1700 5300 1700 3 0 1 0 -1 -1 +L 5300 1700 5400 1500 3 0 1 0 -1 -1 +L 5400 1500 6500 1500 3 0 1 0 -1 -1 +L 3600 1200 4500 1200 3 0 1 0 -1 -1 +L 4500 1200 4600 1400 3 0 1 0 -1 -1 +L 4600 1400 5300 1400 3 0 1 0 -1 -1 +L 5300 1400 5400 1200 3 0 1 0 -1 -1 +L 5400 1200 6500 1200 3 0 1 0 -1 -1 +L 3600 1400 4500 1400 3 0 1 0 -1 -1 +L 4500 1400 4600 1200 3 0 1 0 -1 -1 +L 4600 1200 5300 1200 3 0 1 0 -1 -1 +L 5300 1200 5400 1400 3 0 1 0 -1 -1 +L 5400 1400 6500 1400 3 0 1 0 -1 -1 +L 3600 900 5300 900 3 0 1 0 -1 -1 +L 5300 900 5400 1100 3 0 1 0 -1 -1 +L 5400 1100 6100 1100 3 0 1 0 -1 -1 +L 6100 1100 6200 900 3 0 1 0 -1 -1 +L 6200 900 6500 900 3 0 1 0 -1 -1 +L 3600 1100 5300 1100 3 0 1 0 -1 -1 +L 5300 1100 5400 900 3 0 1 0 -1 -1 +L 5400 900 6100 900 3 0 1 0 -1 -1 +L 6100 900 6200 1100 3 0 1 0 -1 -1 +L 6200 1100 6500 1100 3 0 1 0 -1 -1 +T 4720 2740 9 10 1 0 0 0 1 +valid +T 4730 1250 9 10 1 0 0 0 1 +valid +T 5540 950 9 10 1 0 0 0 1 +valid +T 4100 940 9 10 1 0 0 0 1 +default +T 6310 950 9 10 1 0 0 0 1 +default Index: cde/trunk/ip/pad/rtl/xml/cde_pad_tri_dig.xml =================================================================== --- cde/trunk/ip/pad/rtl/xml/cde_pad_tri_dig.xml (nonexistent) +++ cde/trunk/ip/pad/rtl/xml/cde_pad_tri_dig.xml (revision 2) @@ -0,0 +1,177 @@ + + + + +opencores.org +cde +pad +tri_dig + + + + pad_ring + + + + + + PAD_out + PAD + + + + + + + + pad + + + + + + pad_out + pad_out + + + pad_oe + pad_oe + + + + + + + + + + + + + + sim*simulation* + Verilog + + + fs-sim + + + + + syn*synthesis* + Verilog + + + fs-syn + + + + + + doc + + + + *documentation* + Verilog + + + + + + + + + + +PAD +wire +inout + + +pad_out +wire +in + + +pad_oe +wire +in + + + + + + + + + + + + + + + + + + + + fs-sim + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + fs-syn + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + fs-lint + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + + + + + + + + Index: cde/trunk/ip/pad/rtl/xml/cde_pad_od_dig.xml =================================================================== --- cde/trunk/ip/pad/rtl/xml/cde_pad_od_dig.xml (nonexistent) +++ cde/trunk/ip/pad/rtl/xml/cde_pad_od_dig.xml (revision 2) @@ -0,0 +1,190 @@ + + + + +opencores.org +cde +pad +od_dig + + + + + + + + + pad_ring + + + + + + PAD_io + PAD + + + + + + + + pad + + + + + + pad_oe + pad_oe + + + pad_in + pad_in + + + + + + + + + + + + + + + + + + + + + + + + sim*simulation* + Verilog + + + fs-sim + + + + + syn*synthesis* + Verilog + + + fs-syn + + + + + + + doc + + + + *documentation* + Verilog + + + + + + + + + + +PAD +wire +inout + + +pad_in +wire +out + + +pad_oe +wire +in + + + + + + + + + + + + + + fs-sim + + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + fs-syn + + + dest_dir + ../verilog/syn/ + verilogSourcelibraryDir + + + + + + + + + + fs-lint + + dest_dir + ../verilog/syn/ + verilogSourcelibraryDir + + + + + + + + + + + + + + + + + + + Index: cde/trunk/ip/pad/rtl/xml/cde_pad_in_dig.xml =================================================================== --- cde/trunk/ip/pad/rtl/xml/cde_pad_in_dig.xml (nonexistent) +++ cde/trunk/ip/pad/rtl/xml/cde_pad_in_dig.xml (revision 2) @@ -0,0 +1,187 @@ + + + + +opencores.org +cde +pad +in_dig + + + + + + + pad_ring + + + + + + PAD_in + PAD + + + + + + + + + pad + + + + + + pad_in + pad_in + + + + + + + + + + + + + + + + + + + + + + + sim*simulation* + Verilog + + + fs-sim + + + + + syn*synthesis* + Verilog + + + fs-syn + + + + + doc + + + + *documentation* + Verilog + + + + + + +WIDTH1 + + + + + + +PAD +wire +in +WIDTH-10 + + +pad_in +wire +out +WIDTH-10 + + + + + + + + + + + + + + + + + + + + + fs-sim + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + fs-syn + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + + fs-lint + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + + + + + + + + + Index: cde/trunk/ip/pad/rtl/xml/cde_pad_se_dig.xml =================================================================== --- cde/trunk/ip/pad/rtl/xml/cde_pad_se_dig.xml (nonexistent) +++ cde/trunk/ip/pad/rtl/xml/cde_pad_se_dig.xml (revision 2) @@ -0,0 +1,204 @@ + + + + +opencores.org +cde +pad +se_dig + + + + + + pad_ring + + + + + + PAD_io + PAD + + + + + + + + + pad + + + + + + pad_out + pad_out + + + + pad_oe + pad_oe + + + pad_in + pad_in + + + + + + + + + + + + + + + + + sim*simulation* + Verilog + + + fs-sim + + + + + syn*synthesis* + Verilog + + + fs-syn + + + + + + doc + + + + *documentation* + Verilog + + + + + + + + +WIDTH1 + + + + + +PAD +wire +inout +WIDTH-10 + + +pad_in +wire +out +WIDTH-10 + + +pad_out +wire +in +WIDTH-10 + + +pad_oe +wire +in + + + + + + + + + + + + + + + + + + + + + fs-sim + + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + fs-syn + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + fs-lint + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + + + + + + + + + + Index: cde/trunk/ip/pad/rtl/xml/cde_pad_out_dig.xml =================================================================== --- cde/trunk/ip/pad/rtl/xml/cde_pad_out_dig.xml (nonexistent) +++ cde/trunk/ip/pad/rtl/xml/cde_pad_out_dig.xml (revision 2) @@ -0,0 +1,182 @@ + + + + +opencores.org +cde +pad +out_dig + + + + + + + + pad_ring + + + + + + PAD_out + PAD + + + + + + + + + pad + + + + + + pad_out + pad_out + + + + + + + + + + + + + + + + + + + + + sim*simulation* + Verilog + + + fs-sim + + + + + syn*synthesis* + Verilog + + + fs-syn + + + + + doc + + + + *documentation* + Verilog + + + + + + + + +WIDTH1 + + + + + +PAD +wire +out +WIDTH-10 + + +pad_out +wire +in +WIDTH-10 + + + + + + + + + + + + + + + + fs-sim + + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + fs-syn + + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + fs-lint + + dest_dir + ../verilog/ + verilogSourcelibraryDir + + + + + + + + + + + + + + + + + Index: cde/trunk/ip/pad/rtl/verilog/pad_in_dig.v =================================================================== --- cde/trunk/ip/pad/rtl/verilog/pad_in_dig.v (nonexistent) +++ cde/trunk/ip/pad/rtl/verilog/pad_in_dig.v (revision 2) @@ -0,0 +1,37 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + + +module +cde_pad_in_dig +#(parameter WIDTH=1) +( + +input wire [WIDTH-1:0] PAD, +output wire [WIDTH-1:0] pad_in + +); + +assign pad_in = PAD; + +endmodule + + Index: cde/trunk/ip/pad/rtl/verilog/pad_out_dig.v =================================================================== --- cde/trunk/ip/pad/rtl/verilog/pad_out_dig.v (nonexistent) +++ cde/trunk/ip/pad/rtl/verilog/pad_out_dig.v (revision 2) @@ -0,0 +1,36 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + +module +cde_pad_out_dig +#(parameter WIDTH=1) +( +output wire [WIDTH-1:0] PAD, +input wire [WIDTH-1:0] pad_out +); + +assign PAD = pad_out; + + + +endmodule + + Index: cde/trunk/ip/pad/rtl/verilog/pad_se_dig.v =================================================================== --- cde/trunk/ip/pad/rtl/verilog/pad_se_dig.v (nonexistent) +++ cde/trunk/ip/pad/rtl/verilog/pad_se_dig.v (revision 2) @@ -0,0 +1,41 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + +module +cde_pad_se_dig +#(parameter WIDTH=1) +( + +inout wire [WIDTH-1:0] PAD, +output wire [WIDTH-1:0] pad_in, +input wire [WIDTH-1:0] pad_out, +input wire pad_oe + +); + +assign pad_in = PAD; +assign PAD = pad_oe ? pad_out : {WIDTH{1'bz}}; + + + +endmodule + + Index: cde/trunk/ip/pad/rtl/verilog/syn/pad_od_dig.v =================================================================== --- cde/trunk/ip/pad/rtl/verilog/syn/pad_od_dig.v (nonexistent) +++ cde/trunk/ip/pad/rtl/verilog/syn/pad_od_dig.v (revision 2) @@ -0,0 +1,35 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ +module +cde_pad_od_dig( +inout wire PAD, +output wire pad_in, +input wire pad_oe +); + +assign pad_in = PAD; +assign PAD = pad_oe ? 1'b0 : 1'bz; + + + +endmodule + + Index: cde/trunk/ip/pad/rtl/verilog/pad_tri_dig.v =================================================================== --- cde/trunk/ip/pad/rtl/verilog/pad_tri_dig.v (nonexistent) +++ cde/trunk/ip/pad/rtl/verilog/pad_tri_dig.v (revision 2) @@ -0,0 +1,37 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + +module +cde_pad_tri_dig( + +inout wire PAD, +input wire pad_out, +input wire pad_oe + +); + +assign PAD = pad_oe ? pad_out : 1'bz; + + + +endmodule + + Index: cde/trunk/ip/pad/rtl/verilog/pad_od_dig.v =================================================================== --- cde/trunk/ip/pad/rtl/verilog/pad_od_dig.v (nonexistent) +++ cde/trunk/ip/pad/rtl/verilog/pad_od_dig.v (revision 2) @@ -0,0 +1,35 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ +module +cde_pad_od_dig( +inout wire PAD, +output wire pad_in, +input wire pad_oe +); + +assign pad_in = PAD; +assign PAD = pad_oe ? 1'b0 : 1'bz; + +pullup u0(PAD); + +endmodule + + Index: cde/trunk/ip/pad/componentCfg.xml =================================================================== --- cde/trunk/ip/pad/componentCfg.xml (nonexistent) +++ cde/trunk/ip/pad/componentCfg.xml (revision 2) @@ -0,0 +1,114 @@ + + + + +opencores.org +cde +pad + + +3 +_ +_ +_ +VARIANT + + + + + + +/ip/pad/doc + + + + + + se_dig + Single ended bidirectional digital pad + + + + in_dig + Single ended input digital pad + + + + out_dig + Single ended output digital pad + + + + + tri_dig + Single ended tristatable digital pad + + + + + od_dig + Single ended open drain digital pad + + + + + + + + + + + + + WIDTH + Width of pad + + + + + + + + + + + PAD + PCA Pad connection + + + + pad_oe + Active high tristate drive signal + + + + pad_out + Output signal + + + + pad_in + Input signal + + + + + + + + + + + + + + + + + + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_tri_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_tri_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_tri_dig.html (revision 2) @@ -0,0 +1,161 @@ + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+
+ + + + + + + + +
Name
default
Description
+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
PAD
inout
PCA Pad connection
pad_oe
input
Active high tristate drive signal
pad_out
input
Output signal
+


+

+

Children

+
+
+ + + + + + + + + + +
Instance
Vendor
Library
Component
Version
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+

+
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+
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+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_od_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_od_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_od_dig.html (revision 2) @@ -0,0 +1,161 @@ + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+
+ + + + + + + + +
Name
default
Description
+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
PAD
inout
PCA Pad connection
pad_in
output
Input signal
pad_oe
input
Active high tristate drive signal
+


+

+

Children

+
+
+ + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_in_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_in_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_in_dig.html (revision 2) @@ -0,0 +1,161 @@ + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+
+ + + + + + + + + + + + + + +
Name
default
Description
WIDTH
1
Width of pad
+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
PAD[WIDTH-1:0 ]
input
PCA Pad connection
pad_in[WIDTH-1:0 ]
output
Input signal
+


+

+

Children

+
+
+ + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
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+
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+
+
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+
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+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_out_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_out_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_out_dig.html (revision 2) @@ -0,0 +1,161 @@ + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+
+ + + + + + + + + + + + + + +
Name
default
Description
WIDTH
1
Width of pad
+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
PAD[WIDTH-1:0 ]
output
PCA Pad connection
pad_out[WIDTH-1:0 ]
input
Output signal
+


+

+

Children

+
+
+ + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
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+
+
+
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+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_se_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_se_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_se_dig.html (revision 2) @@ -0,0 +1,173 @@ + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
+

+
+ + + +
+
+
+

Parameters

+
+
+
+ + + + + + + + + + + + + + +
Name
default
Description
WIDTH
1
Width of pad
+


+

+


+

+


+

+


+
+

+

Interface 
+

+

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NAME
Type
Description
PAD[WIDTH-1:0 ]
inout
PCA Pad connection
pad_in[WIDTH-1:0 ]
output
Input signal
pad_oe
input
Active high tristate drive signal
pad_out[WIDTH-1:0 ]
input
Output signal
+


+

+

Children

+
+
+ + + + + + + + + + +
Instance
Vendor
Library
Component
Version
+


+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+ + Index: cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png (revision 2)
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cde/trunk/ip/pad/doc/Geda/png/cde_pad_tri_dig_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/Geda/src/cde_pad_tri_dig.v =================================================================== --- cde/trunk/ip/pad/doc/Geda/src/cde_pad_tri_dig.v (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/src/cde_pad_tri_dig.v (revision 2) @@ -0,0 +1,37 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + +module +cde_pad_tri_dig( + +inout wire PAD, +input wire pad_out, +input wire pad_oe + +); + +assign PAD = pad_oe ? pad_out : 1'bz; + + + +endmodule + + Index: cde/trunk/ip/pad/doc/Geda/src/cde_pad_od_dig.v =================================================================== --- cde/trunk/ip/pad/doc/Geda/src/cde_pad_od_dig.v (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/src/cde_pad_od_dig.v (revision 2) @@ -0,0 +1,35 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ +module +cde_pad_od_dig( +inout wire PAD, +output wire pad_in, +input wire pad_oe +); + +assign pad_in = PAD; +assign PAD = pad_oe ? 1'b0 : 1'bz; + +pullup u0(PAD); + +endmodule + + Index: cde/trunk/ip/pad/doc/Geda/src/cde_pad_in_dig.v =================================================================== --- cde/trunk/ip/pad/doc/Geda/src/cde_pad_in_dig.v (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/src/cde_pad_in_dig.v (revision 2) @@ -0,0 +1,37 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + + +module +cde_pad_in_dig +#(parameter WIDTH=1) +( + +input wire [WIDTH-1:0] PAD, +output wire [WIDTH-1:0] pad_in + +); + +assign pad_in = PAD; + +endmodule + + Index: cde/trunk/ip/pad/doc/Geda/src/cde_pad_se_dig.v =================================================================== --- cde/trunk/ip/pad/doc/Geda/src/cde_pad_se_dig.v (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/src/cde_pad_se_dig.v (revision 2) @@ -0,0 +1,41 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + +module +cde_pad_se_dig +#(parameter WIDTH=1) +( + +inout wire [WIDTH-1:0] PAD, +output wire [WIDTH-1:0] pad_in, +input wire [WIDTH-1:0] pad_out, +input wire pad_oe + +); + +assign pad_in = PAD; +assign PAD = pad_oe ? pad_out : {WIDTH{1'bz}}; + + + +endmodule + + Index: cde/trunk/ip/pad/doc/Geda/src/cde_pad_out_dig.v =================================================================== --- cde/trunk/ip/pad/doc/Geda/src/cde_pad_out_dig.v (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/src/cde_pad_out_dig.v (revision 2) @@ -0,0 +1,36 @@ +/**********************************************************************/ +/* */ +/* */ +/* Copyright (c) 2012 Ouabache Design Works */ +/* */ +/* All Rights Reserved Worldwide */ +/* */ +/* Licensed under the Apache License,Version2.0 (the'License'); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in */ +/* writing, software distributed under the License is */ +/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ +/* OR CONDITIONS OF ANY KIND, either express or implied. */ +/* See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/**********************************************************************/ + +module +cde_pad_out_dig +#(parameter WIDTH=1) +( +output wire [WIDTH-1:0] PAD, +input wire [WIDTH-1:0] pad_out +); + +assign PAD = pad_out; + + + +endmodule + + Index: cde/trunk/ip/pad/doc/Geda/sym/cde_pad_in_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/Geda/sym/cde_pad_in_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sym/cde_pad_in_dig.sym (revision 2) @@ -0,0 +1,20 @@ +v 20100214 1 +B 300 0 3500 500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 650 5 10 1 1 0 0 1 1 +device=cde_pad_in_dig +T 400 850 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=PAD[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 3800 200 4100 200 10 1 1 +{ +T 3700 200 5 10 1 1 0 7 1 1 +pinnumber=pad_in[WIDTH-1:0] +T 3700 200 5 10 0 1 0 7 1 1 +pinseq=2 +} Index: cde/trunk/ip/pad/doc/Geda/sym/cde_pad_out_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/Geda/sym/cde_pad_out_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sym/cde_pad_out_dig.sym (revision 2) @@ -0,0 +1,20 @@ +v 20100214 1 +B 300 0 3600 500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 650 5 10 1 1 0 0 1 1 +device=cde_pad_out_dig +T 400 850 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=pad_out[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 3900 200 4200 200 10 1 1 +{ +T 3800 200 5 10 1 1 0 7 1 1 +pinnumber=PAD[WIDTH-1:0] +T 3800 200 5 10 0 1 0 7 1 1 +pinseq=2 +} Index: cde/trunk/ip/pad/doc/Geda/sym/cde_pad_se_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/Geda/sym/cde_pad_se_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sym/cde_pad_se_dig.sym (revision 2) @@ -0,0 +1,34 @@ +v 20100214 1 +B 300 0 3900 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 850 5 10 1 1 0 0 1 1 +device=cde_pad_se_dig +T 400 1050 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 10 1 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=pad_out[WIDTH-1:0] +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=pad_oe +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 4200 200 4500 200 10 1 1 +{ +T 4100 200 5 10 1 1 0 7 1 1 +pinnumber=pad_in[WIDTH-1:0] +T 4100 200 5 10 0 1 0 7 1 1 +pinseq=3 +} +P 4200 400 4500 400 10 1 1 +{ +T 4100 400 5 10 1 1 0 7 1 1 +pinnumber=PAD[WIDTH-1:0] +T 4100 400 5 10 0 1 0 7 1 1 +pinseq=4 +} Index: cde/trunk/ip/pad/doc/Geda/sym/cde_pad_tri_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/Geda/sym/cde_pad_tri_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sym/cde_pad_tri_dig.sym (revision 2) @@ -0,0 +1,27 @@ +v 20100214 1 +B 300 0 1400 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 850 5 10 1 1 0 0 1 1 +device=cde_pad_tri_dig +T 400 1050 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=pad_out +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 300 400 0 400 4 0 1 +{ +T 400 400 5 10 1 1 0 1 1 1 +pinnumber=pad_oe +T 400 400 5 10 0 1 0 1 1 1 +pinseq=2 +} +P 1700 200 2000 200 4 0 1 +{ +T 1600 200 5 10 1 1 0 7 1 1 +pinnumber=PAD +T 1700 200 5 10 0 1 0 7 1 1 +pinseq=3 +} Index: cde/trunk/ip/pad/doc/Geda/sym/cde_pad_od_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/Geda/sym/cde_pad_od_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sym/cde_pad_od_dig.sym (revision 2) @@ -0,0 +1,27 @@ +v 20100214 1 +B 300 0 1600 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 850 5 10 1 1 0 0 1 1 +device=cde_pad_od_dig +T 400 1050 8 10 1 1 0 0 1 1 +refdes=U? +P 300 200 0 200 4 0 1 +{ +T 400 200 5 10 1 1 0 1 1 1 +pinnumber=pad_oe +T 400 200 5 10 0 1 0 1 1 1 +pinseq=1 +} +P 1900 200 2200 200 4 0 1 +{ +T 1800 200 5 10 1 1 0 7 1 1 +pinnumber=pad_in +T 1900 200 5 10 0 1 0 7 1 1 +pinseq=2 +} +P 1900 400 2200 400 4 0 1 +{ +T 1800 400 5 10 1 1 0 7 1 1 +pinnumber=PAD +T 1900 400 5 10 0 1 0 7 1 1 +pinseq=3 +} Index: cde/trunk/ip/pad/doc/Geda/sch/cde_pad_od_dig.sch =================================================================== --- cde/trunk/ip/pad/doc/Geda/sch/cde_pad_od_dig.sch (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sch/cde_pad_od_dig.sch (revision 2) @@ -0,0 +1,16 @@ +v 20100214 1 +C 800 300 1 0 0 in_port.sym +{ +T 800 300 5 10 1 1 0 6 1 1 +refdes=pad_oe +} +C 800 700 1 0 0 io_port.sym +{ +T 800 700 5 10 1 1 0 6 1 1 +refdes=PAD +} +C 2700 300 1 0 0 out_port.sym +{ +T 3700 300 5 10 1 1 0 0 1 1 +refdes=pad_in +} Index: cde/trunk/ip/pad/doc/Geda/sch/cde_pad_in_dig.sch =================================================================== --- cde/trunk/ip/pad/doc/Geda/sch/cde_pad_in_dig.sch (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sch/cde_pad_in_dig.sch (revision 2) @@ -0,0 +1,11 @@ +v 20100214 1 +C 1600 300 1 0 0 in_port_v.sym +{ +T 1600 300 5 10 1 1 0 6 1 1 +refdes=PAD[WIDTH-1:0] +} +C 4600 300 1 0 0 out_port_v.sym +{ +T 5600 300 5 10 1 1 0 0 1 1 +refdes=pad_in[WIDTH-1:0] +} Index: cde/trunk/ip/pad/doc/Geda/sch/cde_pad_se_dig.sch =================================================================== --- cde/trunk/ip/pad/doc/Geda/sch/cde_pad_se_dig.sch (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sch/cde_pad_se_dig.sch (revision 2) @@ -0,0 +1,21 @@ +v 20100214 1 +C 2000 300 1 0 0 in_port_v.sym +{ +T 2000 300 5 10 1 1 0 6 1 1 +refdes=pad_out[WIDTH-1:0] +} +C 2000 700 1 0 0 in_port.sym +{ +T 2000 700 5 10 1 1 0 6 1 1 +refdes=pad_oe +} +C 2000 1100 1 0 0 io_port_v.sym +{ +T 2000 1100 5 10 1 1 0 6 1 1 +refdes=PAD[WIDTH-1:0] +} +C 5000 300 1 0 0 out_port_v.sym +{ +T 6000 300 5 10 1 1 0 0 1 1 +refdes=pad_in[WIDTH-1:0] +} Index: cde/trunk/ip/pad/doc/Geda/sch/cde_pad_out_dig.sch =================================================================== --- cde/trunk/ip/pad/doc/Geda/sch/cde_pad_out_dig.sch (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sch/cde_pad_out_dig.sch (revision 2) @@ -0,0 +1,11 @@ +v 20100214 1 +C 2000 300 1 0 0 in_port_v.sym +{ +T 2000 300 5 10 1 1 0 6 1 1 +refdes=pad_out[WIDTH-1:0] +} +C 4700 300 1 0 0 out_port_v.sym +{ +T 5700 300 5 10 1 1 0 0 1 1 +refdes=PAD[WIDTH-1:0] +} Index: cde/trunk/ip/pad/doc/Geda/sch/cde_pad_tri_dig.sch =================================================================== --- cde/trunk/ip/pad/doc/Geda/sch/cde_pad_tri_dig.sch (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/sch/cde_pad_tri_dig.sch (revision 2) @@ -0,0 +1,16 @@ +v 20100214 1 +C 900 300 1 0 0 in_port.sym +{ +T 900 300 5 10 1 1 0 6 1 1 +refdes=pad_out +} +C 900 700 1 0 0 in_port.sym +{ +T 900 700 5 10 1 1 0 6 1 1 +refdes=pad_oe +} +C 900 1100 1 0 0 io_port.sym +{ +T 900 1100 5 10 1 1 0 6 1 1 +refdes=PAD +} Index: cde/trunk/ip/pad/doc/gafrc =================================================================== --- cde/trunk/ip/pad/doc/gafrc (nonexistent) +++ cde/trunk/ip/pad/doc/gafrc (revision 2) @@ -0,0 +1,10 @@ +; -*-Scheme-*- +;;; +;;; Add the default component libraries +;;; + + + + +(component-library-search "./sym" "sym" ) + Index: cde/trunk/ip/pad/doc/html/cde_pad_tri_dig.html =================================================================== --- cde/trunk/ip/pad/doc/html/cde_pad_tri_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/cde_pad_tri_dig.html (revision 2) @@ -0,0 +1,126 @@ + + + + + start + + + + + + + + + + +

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+ + Index: cde/trunk/ip/pad/doc/html/cde_pad_od_dig.html =================================================================== --- cde/trunk/ip/pad/doc/html/cde_pad_od_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/cde_pad_od_dig.html (revision 2) @@ -0,0 +1,126 @@ + + + + + start + + + + + + + + + + +

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SOCGEN Datasheet:
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Theory of Operation

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SOCGEN Datasheet:
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Theory of Operation

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+ + Index: cde/trunk/ip/pad/doc/html/cde_pad_se_dig.html =================================================================== --- cde/trunk/ip/pad/doc/html/cde_pad_se_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/cde_pad_se_dig.html (revision 2) @@ -0,0 +1,126 @@ + + + + + start + + + + + + + + + + +

SOCGEN Datasheet:
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Theory of Operation

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+ + Index: cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_tri_dig.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_tri_dig.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_tri_dig.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_tri_dig.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_tri_dig.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_in_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_in_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_in_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_in_dig_sym.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_in_dig_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_se_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_se_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_se_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_se_dig_sym.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_se_dig_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_out_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_out_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_out_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_out_dig_sym.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_out_dig_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_od_dig.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_od_dig.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_od_dig.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_od_dig.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_od_dig.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_in_dig.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_in_dig.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_in_dig.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_in_dig.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_in_dig.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_tri_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_tri_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_tri_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_tri_dig_sym.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_tri_dig_sym.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_se_dig.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_se_dig.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_se_dig.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_se_dig.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_se_dig.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/png/cde_pad_out_dig.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_out_dig.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_out_dig.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_out_dig.png (revision 2)
cde/trunk/ip/pad/doc/png/cde_pad_out_dig.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: cde/trunk/ip/pad/doc/sym/cde_pad_in_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/sym/cde_pad_in_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/sym/cde_pad_in_dig.sym (revision 2) @@ -0,0 +1,25 @@ +v 20110115 2 +T 1002 18 5 10 1 1 0 0 1 +device=cde_pad_in_dig +T 1200 800 5 10 1 1 0 6 1 +refdes=P? +B 1000 300 400 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 1100 400 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 1000 500 700 500 3 0 0 0 -1 -1 +L 300 500 700 300 3 0 0 0 -1 -1 +L 300 500 700 700 3 0 0 0 -1 -1 +L 700 700 700 300 3 0 0 0 -1 -1 +P 100 500 300 500 4 0 0 +{ +T -598 535 5 10 0 1 0 0 1 +pinnumber=PAD_IN +T 402 435 5 10 0 0 0 0 1 +pinseq=2 +} +P 1200 500 1210 500 1 0 0 +{ +T 1805 545 5 10 0 1 0 6 1 +pinnumber=PAD +T 1200 500 5 10 0 0 0 0 1 +pinseq=0 +} Index: cde/trunk/ip/pad/doc/sym/cde_pad_out_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/sym/cde_pad_out_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/sym/cde_pad_out_dig.sym (revision 2) @@ -0,0 +1,25 @@ +v 20110115 2 +P 0 600 200 600 4 0 0 +{ +T -798 635 5 10 0 1 0 0 1 +pinnumber=PAD_OUT +T 302 535 5 10 0 0 0 0 1 +pinseq=1 +} +T 902 118 5 10 1 1 0 0 1 +device=cde_pad_out_dig +T 1100 900 5 10 1 1 0 6 1 +refdes=P? +B 900 400 400 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 1000 500 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 600 600 200 800 3 0 0 0 -1 -1 +L 600 600 200 400 3 0 0 0 -1 -1 +L 200 800 200 400 3 0 0 0 -1 -1 +L 900 600 600 600 3 0 0 0 -1 -1 +P 1100 600 1110 600 1 0 0 +{ +T 1705 645 5 10 0 1 0 6 1 +pinnumber=PAD +T 1100 600 5 10 0 0 0 0 1 +pinseq=0 +} Index: cde/trunk/ip/pad/doc/sym/cde_pad_se_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/sym/cde_pad_se_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/sym/cde_pad_se_dig.sym (revision 2) @@ -0,0 +1,45 @@ +v 20110115 2 +P 0 600 200 600 4 0 0 +{ +T -798 635 5 10 0 1 0 0 1 +pinnumber=PAD_OUT +T 302 535 5 10 0 0 0 0 1 +pinseq=1 +} +P 0 1000 404 1000 4 0 0 +{ +T -798 1035 5 10 0 1 0 0 1 +pinnumber=PAD_OE +T 302 935 5 10 0 0 0 0 1 +pinseq=3 +} +T 902 118 5 10 1 1 0 0 1 +device=CDE_PAD_SE_DIG +T 1100 900 5 10 1 1 0 6 1 +refdes=P? +B 900 400 400 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 1000 500 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 600 600 200 800 3 0 0 0 -1 -1 +L 600 600 200 400 3 0 0 0 -1 -1 +L 200 800 200 400 3 0 0 0 -1 -1 +L 900 600 600 600 3 0 0 0 -1 -1 +L 400 700 400 1000 4 10 0 0 -1 -1 +L 200 200 600 0 3 0 0 0 -1 -1 +L 200 200 600 400 3 0 0 0 -1 -1 +L 600 400 600 0 3 0 0 0 -1 -1 +P 0 200 200 200 4 0 0 +{ +T -698 235 5 10 0 1 0 0 1 +pinnumber=PAD_IN +T 302 135 5 10 0 0 0 0 1 +pinseq=2 +} +L 600 200 700 200 3 0 0 0 -1 -1 +L 700 600 700 200 3 0 0 0 -1 -1 +P 1100 600 1110 600 1 1 0 +{ +T 1705 645 5 10 0 1 0 6 1 +pinnumber=PAD +T 1100 600 5 10 0 0 0 0 1 +pinseq=0 +} Index: cde/trunk/ip/pad/doc/sym/cde_pad_tri_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/sym/cde_pad_tri_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/sym/cde_pad_tri_dig.sym (revision 2) @@ -0,0 +1,33 @@ +v 20110115 2 +P 100 600 300 600 4 0 0 +{ +T -698 635 5 10 0 1 0 0 1 +pinnumber=PAD_OUT +T 402 535 5 10 0 0 0 0 1 +pinseq=1 +} +P 100 1000 504 1000 4 0 0 +{ +T -698 1035 5 10 0 1 0 0 1 +pinnumber=PAD_OE +T 402 935 5 10 0 0 0 0 1 +pinseq=3 +} +T 102 218 5 10 1 1 0 0 1 +device=cde_pad_tri_dig +T 1200 900 5 10 1 1 0 6 1 +refdes=P? +B 1000 400 400 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 1100 500 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 700 600 300 800 3 0 0 0 -1 -1 +L 700 600 300 400 3 0 0 0 -1 -1 +L 300 800 300 400 3 0 0 0 -1 -1 +L 1000 600 700 600 3 0 0 0 -1 -1 +L 500 700 500 1000 4 10 0 0 -1 -1 +P 1200 600 1210 600 1 0 0 +{ +T 1805 645 5 10 0 1 0 6 1 +pinnumber=PAD +T 1200 600 5 10 0 0 0 0 1 +pinseq=0 +} Index: cde/trunk/ip/pad/doc/sym/cde_pad_od_dig.sym =================================================================== --- cde/trunk/ip/pad/doc/sym/cde_pad_od_dig.sym (nonexistent) +++ cde/trunk/ip/pad/doc/sym/cde_pad_od_dig.sym (revision 2) @@ -0,0 +1,43 @@ +v 20110115 2 +P 100 1000 504 1000 4 0 0 +{ +T -698 1035 5 10 0 1 0 0 1 +pinnumber=PAD_OE +T 402 935 5 10 0 0 0 0 1 +pinseq=3 +} +T 1002 118 5 10 1 1 0 0 1 +device=cde_pad_od_dig +T 1200 900 5 10 1 1 0 6 1 +refdes=P? +B 1000 400 400 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 1100 500 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 700 600 300 800 3 0 0 0 -1 -1 +L 700 600 300 400 3 0 0 0 -1 -1 +L 300 800 300 400 3 0 0 0 -1 -1 +L 1000 600 700 600 3 0 0 0 -1 -1 +L 500 700 500 1000 4 10 0 0 -1 -1 +L 300 200 700 0 3 0 0 0 -1 -1 +L 300 200 700 400 3 0 0 0 -1 -1 +L 700 400 700 0 3 0 0 0 -1 -1 +P 100 200 300 200 4 0 0 +{ +T -598 235 5 10 0 1 0 0 1 +pinnumber=PAD_IN +T 402 135 5 10 0 0 0 0 1 +pinseq=2 +} +L 700 200 800 200 3 0 0 0 -1 -1 +L 800 600 800 200 3 0 0 0 -1 -1 +P 1200 600 1210 600 1 0 0 +{ +T 1805 645 5 10 0 1 0 6 1 +pinnumber=PAD +T 1200 600 5 10 0 0 0 0 1 +pinseq=0 +} +N 300 600 100 600 4 +{ +T 0 700 5 10 1 1 0 0 1 +netname=0 +} Index: cde/trunk/ip/pad/doc/mk_png =================================================================== --- cde/trunk/ip/pad/doc/mk_png (nonexistent) +++ cde/trunk/ip/pad/doc/mk_png (revision 2) @@ -0,0 +1,11 @@ +mk_sym_png cde_pad_out_dig; +mk_sym_png cde_pad_se_dig; +mk_sym_png cde_pad_tri_dig; +mk_sym_png cde_pad_in_dig; +mk_sym_png cde_pad_od_dig; +mk_sch_png cde_pad_od_dig_sym; +mk_sch_png cde_pad_se_dig_sym; +mk_sch_png cde_pad_in_dig_sym; +mk_sch_png cde_pad_out_dig_sym; +mk_sch_png cde_pad_tri_dig_sym; +
cde/trunk/ip/pad/doc/mk_png Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: cde/trunk/ip/pad/doc/sch/cde_pad_tri_dig_sym.sch =================================================================== --- cde/trunk/ip/pad/doc/sch/cde_pad_tri_dig_sym.sch (nonexistent) +++ cde/trunk/ip/pad/doc/sch/cde_pad_tri_dig_sym.sch (revision 2) @@ -0,0 +1,27 @@ +v 20110115 2 +C 4100 3000 1 0 0 in_port.sym +{ +T 4100 3000 5 10 1 1 0 6 1 +refdes=pad_oe +} +C 4100 2600 1 0 0 in_port.sym +{ +T 4100 2600 5 10 1 1 0 6 1 +refdes=pad_out +} +C 7900 2600 1 0 1 io_port_v.sym +{ +T 7900 2600 5 10 1 1 0 0 1 +refdes=PAD +} +N 5300 3100 5000 3100 4 +N 5300 2700 5000 2700 4 +U 6900 2700 6400 2700 10 0 +B 2800 600 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +C 5200 2100 1 0 0 cde_pad_tri_dig.sym +{ +T 5302 2318 5 10 1 1 0 0 1 +device=cde_pad_tri_dig +T 6400 3000 5 10 1 1 0 6 1 +refdes=P? +} Index: cde/trunk/ip/pad/doc/sch/cde_pad_od_dig_sym.sch =================================================================== --- cde/trunk/ip/pad/doc/sch/cde_pad_od_dig_sym.sch (nonexistent) +++ cde/trunk/ip/pad/doc/sch/cde_pad_od_dig_sym.sch (revision 2) @@ -0,0 +1,27 @@ +v 20110115 2 +C 4300 2900 1 0 0 in_port.sym +{ +T 4300 2900 5 10 1 1 0 6 1 +refdes=pad_oe +} +C 8100 2500 1 0 1 io_port_v.sym +{ +T 8100 2500 5 10 1 1 0 0 1 +refdes=PAD +} +C 5200 2100 1 0 1 out_port.sym +{ +T 4200 2100 5 10 1 1 0 6 1 +refdes=pad_in +} +N 5500 3000 5200 3000 4 +N 5500 2200 5200 2200 4 +U 7100 2600 6600 2600 10 0 +B 3000 500 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +C 5400 2000 1 0 0 cde_pad_od_dig.sym +{ +T 6402 2118 5 10 1 1 0 0 1 +device=cde_pad_od_dig +T 6600 2900 5 10 1 1 0 6 1 +refdes=P? +} Index: cde/trunk/ip/pad/doc/sch/cde_pad_in_dig_sym.sch =================================================================== --- cde/trunk/ip/pad/doc/sch/cde_pad_in_dig_sym.sch (nonexistent) +++ cde/trunk/ip/pad/doc/sch/cde_pad_in_dig_sym.sch (revision 2) @@ -0,0 +1,21 @@ +v 20110115 2 +C 7000 2500 1 0 1 io_port_v.sym +{ +T 7000 2500 5 10 1 1 0 0 1 +refdes=PAD +} +C 4100 2500 1 0 1 out_port.sym +{ +T 3100 2500 5 10 1 1 0 6 1 +refdes=pad_in +} +N 4400 2600 4100 2600 4 +U 6000 2600 5500 2600 10 0 +B 1900 500 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +C 4300 2100 1 0 0 cde_pad_in_dig.sym +{ +T 5302 2118 5 10 1 1 0 0 1 +device=cde_pad_in_dig +T 5500 2900 5 10 1 1 0 6 1 +refdes=P? +} Index: cde/trunk/ip/pad/doc/sch/cde_pad_out_dig_sym.sch =================================================================== --- cde/trunk/ip/pad/doc/sch/cde_pad_out_dig_sym.sch (nonexistent) +++ cde/trunk/ip/pad/doc/sch/cde_pad_out_dig_sym.sch (revision 2) @@ -0,0 +1,21 @@ +v 20110115 2 +C 4100 2600 1 0 0 in_port.sym +{ +T 4100 2600 5 10 1 1 0 6 1 +refdes=pad_out +} +C 7900 2600 1 0 1 io_port_v.sym +{ +T 7900 2600 5 10 1 1 0 0 1 +refdes=PAD +} +N 5300 2700 5000 2700 4 +U 6900 2700 6400 2700 10 0 +B 2800 600 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +C 5300 2100 1 0 0 cde_pad_out_dig.sym +{ +T 6202 2218 5 10 1 1 0 0 1 +device=cde_pad_out_dig +T 6400 3000 5 10 1 1 0 6 1 +refdes=P? +} Index: cde/trunk/ip/pad/doc/sch/cde_pad_se_dig_sym.sch =================================================================== --- cde/trunk/ip/pad/doc/sch/cde_pad_se_dig_sym.sch (nonexistent) +++ cde/trunk/ip/pad/doc/sch/cde_pad_se_dig_sym.sch (revision 2) @@ -0,0 +1,33 @@ +v 20110115 2 +C 4100 3000 1 0 0 in_port.sym +{ +T 4100 3000 5 10 1 1 0 6 1 +refdes=pad_oe +} +C 4100 2600 1 0 0 in_port.sym +{ +T 4100 2600 5 10 1 1 0 6 1 +refdes=pad_out +} +C 7900 2600 1 0 1 io_port_v.sym +{ +T 7900 2600 5 10 1 1 0 0 1 +refdes=PAD +} +C 5000 2200 1 0 1 out_port.sym +{ +T 4000 2200 5 10 1 1 0 6 1 +refdes=pad_in +} +C 5300 2100 1 0 0 cde_pad_se_dig.sym +{ +T 6202 2218 5 10 1 1 0 0 1 +device=cde_pad_se_dig +T 6400 3000 5 10 1 1 0 6 1 +refdes=P? +} +N 5300 3100 5000 3100 4 +N 5300 2700 5000 2700 4 +N 5300 2300 5000 2300 4 +U 6900 2700 6400 2700 10 0 +B 2800 600 6000 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 Index: cde/trunk/ReadMe.txt =================================================================== --- cde/trunk/ReadMe.txt (nonexistent) +++ cde/trunk/ReadMe.txt (revision 2) @@ -0,0 +1,3 @@ + + +Start with ./doc/index.html

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