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Apache License |
Version 2.0, January 2004 |
http://www.apache.org/licenses/ |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<HTML> |
<HEAD> |
<META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8"> |
<TITLE>start</TITLE> |
<META NAME="GENERATOR" CONTENT="LibreOffice 3.6 (Linux)"> |
<META NAME="CREATED" CONTENT="0;0"> |
<META NAME="CHANGEDBY" CONTENT="Ouabache Designworks"> |
<META NAME="CHANGED" CONTENT="20130817;8220700"> |
<META NAME="KEYWORDS" CONTENT="start"> |
<META NAME="Info 3" CONTENT=""> |
<META NAME="Info 4" CONTENT=""> |
<META NAME="date" CONTENT="2008-01-08T12:01:41-0500"> |
<META NAME="robots" CONTENT="index,follow"> |
<META NAME="CHANGEDBY" CONTENT="Ouabache Designworks"> |
</HEAD> |
<BODY LANG="en-US" DIR="LTR"> |
<DIV ID="toc__header" DIR="LTR"> |
<H1><A NAME="socgen ip"></A>CDE LIBRARY: |
</H1> |
<P>The Common Design Environment (CDE) is a library of verilog IP |
modules for use in fpga and asic designs. One problem that we face |
is that not all rtl code is synthesisable into all target processes. |
The CDE project seeks to identify this problem code and provide |
documented and functioning models for each case. A CDE module will |
isolate the problem code inside a single module that can be easily |
replaced when the design is targeted to a process that requires |
substitution of custom hard macros. This can be done without |
touching the users rtl code so that a single code base can support |
both fpga and asic targets without modification.</P> |
<P><BR><BR> |
</P> |
<P>CDE is part of the SOCEN design environment and uses IP-Xact |
module descriptors. Documention is autogenerated and uses the gEDA |
tool set. |
</P> |
<P><BR><BR> |
</P> |
<P><BR><BR> |
</P> |
<P><BR><BR> |
</P> |
<P><BR><BR> |
</P> |
</DIV> |
<DIV ID="toc__inside" DIR="LTR"> |
<UL> |
<LI><P STYLE="margin-bottom: 0in"><A HREF="#IPModules">IP Modules</A></P> |
<UL> |
<LI><P><A HREF="../ip/pad/doc/html/component.html">IO Pads</A></P> |
<LI><P><A HREF="../ip/sram/doc/html/component.html">Synchronous |
Rams</A></P> |
</UL> |
</UL> |
</DIV> |
<P><BR><BR> |
</P> |
</BODY> |
</HTML> |
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<spirit:name>fs-lint</spirit:name> |
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<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
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</spirit:fileSet> |
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</spirit:fileSets> |
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</spirit:component> |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
|
--> |
<spirit:component |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" |
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009 |
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd"> |
|
<spirit:vendor>opencores.org</spirit:vendor> |
<spirit:library>cde</spirit:library> |
<spirit:name>sram</spirit:name> |
<spirit:version>be</spirit:version> |
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<spirit:model> |
<spirit:views> |
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<spirit:view> |
<spirit:name>sim</spirit:name><spirit:envIdentifier>*simulation*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-sim</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
<spirit:view> |
<spirit:name>syn</spirit:name><spirit:envIdentifier>*synthesis*</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-syn</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
|
|
<spirit:view> |
<spirit:name>lint</spirit:name><spirit:envIdentifier>lint</spirit:envIdentifier> |
|
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
<spirit:fileSetRef> |
<spirit:localName>fs-lint</spirit:localName> |
</spirit:fileSetRef> |
</spirit:view> |
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<spirit:view> |
<spirit:name>doc</spirit:name> |
<spirit:vendorExtensions> |
<spirit:componentRef spirit:vendor="opencores.org" |
spirit:library="Testbench" |
spirit:name="toolflow" |
spirit:version="documentation"/> |
</spirit:vendorExtensions> |
<spirit:envIdentifier>*documentation*</spirit:envIdentifier> |
<spirit:language>Verilog</spirit:language> |
<spirit:modelName></spirit:modelName> |
</spirit:view> |
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</spirit:views> |
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<spirit:modelParameters> |
<spirit:modelParameter><spirit:name>ADDR</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>8</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WORDS</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>WRITETHRU</spirit:name><spirit:value>0</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>DEFAULT</spirit:name><spirit:value>{WIDTH{1'bx}}</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INIT_FILE</spirit:name><spirit:value>"NONE"</spirit:value></spirit:modelParameter> |
<spirit:modelParameter><spirit:name>INSTANCE_NAME</spirit:name><spirit:value>"U1"</spirit:value></spirit:modelParameter> |
</spirit:modelParameters> |
|
<spirit:ports> |
|
<spirit:port><spirit:name>clk</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>cs</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>wr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rd</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>be</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>addr</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>ADDR-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
|
<spirit:port><spirit:name>wdata</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>in</spirit:direction> |
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
|
<spirit:port><spirit:name>rdata</spirit:name> |
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>reg</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs> |
<spirit:wire><spirit:direction>out</spirit:direction> |
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire> |
</spirit:port> |
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</spirit:ports> |
|
</spirit:model> |
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<spirit:fileSets> |
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<spirit:fileSet> |
<spirit:name>fs-sim</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-syn</spirit:name> |
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
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|
</spirit:fileSet> |
|
|
<spirit:fileSet> |
<spirit:name>fs-lint</spirit:name> |
|
|
<spirit:file> |
<spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/lint/</spirit:name> |
<spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType> |
</spirit:file> |
|
</spirit:fileSet> |
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</spirit:fileSets> |
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</spirit:component> |
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
module |
cde_sram_def |
#( parameter |
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
input wire clk, |
input wire cs, |
input wire rd, |
input wire wr, |
input wire [ ADDR-1 : 0] addr, |
input wire [ WIDTH-1 : 0] wdata, |
output reg [ WIDTH-1 : 0] rdata); |
// Memory Array |
reg [WIDTH-1:0] mem[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
if( INIT_FILE == "NONE") |
begin |
end |
else |
begin |
$readmemh(INIT_FILE, mem); |
end |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
end |
endgenerate |
endmodule |
module |
cde_sram_def |
#( parameter |
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
input wire clk, |
input wire cs, |
input wire rd, |
input wire wr, |
input wire [ ADDR-1 : 0] addr, |
input wire [ WIDTH-1 : 0] wdata, |
output reg [ WIDTH-1 : 0] rdata); |
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
endmodule |
module |
cde_sram_dp |
#( parameter |
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
input wire clk, |
input wire cs, |
input wire rd, |
input wire wr, |
input wire [ ADDR-1 : 0] raddr, |
input wire [ ADDR-1 : 0] waddr, |
input wire [ WIDTH-1 : 0] wdata, |
output reg [ WIDTH-1 : 0] rdata); |
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
endmodule |
module |
cde_sram_be |
#( parameter |
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
input wire be, |
input wire clk, |
input wire cs, |
input wire rd, |
input wire wr, |
input wire [ ADDR-1 : 0] addr, |
input wire [ WIDTH-1 : 0] wdata, |
output reg [ WIDTH-1 : 0] rdata); |
// Simple loop back for linting and code coverage |
always@(posedge clk) |
if( rd && cs ) rdata <= wdata; |
else rdata <= DEFAULT; |
endmodule |
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
module |
cde_sram_dp |
#( parameter |
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
input wire clk, |
input wire cs, |
input wire rd, |
input wire wr, |
input wire [ ADDR-1 : 0] raddr, |
input wire [ ADDR-1 : 0] waddr, |
input wire [ WIDTH-1 : 0] wdata, |
output reg [ WIDTH-1 : 0] rdata); |
// Memory Array |
reg [WIDTH-1:0] mem[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
if( INIT_FILE == "NONE") |
begin |
end |
else |
begin |
$readmemh(INIT_FILE, mem); |
end |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= raddr; |
l_cycle <= rd && cs ; |
end |
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
wire [WIDTH-1:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
end |
endgenerate |
endmodule |
/**********************************************************************/ |
/* */ |
/* */ |
/* Copyright (c) 2012 Ouabache Design Works */ |
/* */ |
/* All Rights Reserved Worldwide */ |
/* */ |
/* Licensed under the Apache License,Version2.0 (the'License'); */ |
/* you may not use this file except in compliance with the License. */ |
/* You may obtain a copy of the License at */ |
/* */ |
/* http://www.apache.org/licenses/LICENSE-2.0 */ |
/* */ |
/* Unless required by applicable law or agreed to in */ |
/* writing, software distributed under the License is */ |
/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ |
/* OR CONDITIONS OF ANY KIND, either express or implied. */ |
/* See the License for the specific language governing */ |
/* permissions and limitations under the License. */ |
/**********************************************************************/ |
module |
cde_sram_be |
#( parameter |
ADDR=10, |
WIDTH=8, |
WORDS=1024, |
WRITETHRU=0, |
DEFAULT={WIDTH{1'b1}}, |
INIT_FILE="NONE", |
INSTANCE_NAME="U1") |
( |
|
input wire clk, |
input wire cs, |
input wire rd, |
input wire wr, |
input wire be, |
|
input wire [ ADDR-1 : 0] addr, |
input wire [ WIDTH-1 : 0] wdata, |
output reg [ WIDTH-1 : 0] rdata); |
// Memory Array |
reg [WIDTH-1:0] mem[0:WORDS-1]; |
// If used as Rom then load a memory image at startup |
initial |
begin |
if( INIT_FILE == "NONE") |
begin |
end |
else |
begin |
$readmemh(INIT_FILE, mem); |
end |
end |
|
// Write function |
always@(posedge clk) |
if( wr && cs && be ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
generate |
if( WRITETHRU) |
begin |
// Read function gets new data if also a write cycle |
// latch the read addr for next cycle |
reg [ADDR-1:0] l_raddr; |
reg l_cycle; |
|
always@(posedge clk) |
begin |
l_raddr <= addr; |
l_cycle <= rd && cs ; |
end |
|
|
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block |
|
wire [7:0] tmp_rdata; |
assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT; |
always@(*) rdata = tmp_rdata; |
end |
else |
begin |
// Read function gets old data if also a write cycle |
always@(posedge clk) |
if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}]; |
else rdata <= DEFAULT; |
end |
endgenerate |
endmodule |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- |
|
--> |
<socgen:componentConfiguration |
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" |
xmlns:socgen="http://opencores.org" |
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> |
|
<socgen:vendor>opencores.org</socgen:vendor> |
<socgen:library>cde</socgen:library> |
<socgen:component>sram</socgen:component> |
|
|
<socgen:ip_name_depth>3</socgen:ip_name_depth> |
<socgen:ip_name_vendor_sep>_</socgen:ip_name_vendor_sep> |
<socgen:ip_name_library_sep>_</socgen:ip_name_library_sep> |
<socgen:ip_name_version_sep>_</socgen:ip_name_version_sep> |
<socgen:ip_name_base_macro>VARIANT</socgen:ip_name_base_macro> |
|
|
|
<socgen:doc> |
|
<socgen:library_path>/ip/sram/doc</socgen:library_path> |
|
|
|
<socgen:versions> |
|
<socgen:version> |
<socgen:name>def</socgen:name> |
<socgen:description>Synchronous one-port ram</socgen:description> |
</socgen:version> |
|
<socgen:version> |
<socgen:name>dp</socgen:name> |
<socgen:description>Synchronous two-port ram with seperate read/write ports</socgen:description> |
</socgen:version> |
|
<socgen:version> |
<socgen:name>be</socgen:name> |
<socgen:description>Synchronous one-port ram with byte enable</socgen:description> |
</socgen:version> |
|
|
|
</socgen:versions> |
|
|
<socgen:parameters> |
|
<socgen:parameter> |
<socgen:name>ADDR</socgen:name> |
<socgen:description>Number of address bits</socgen:description> |
</socgen:parameter> |
|
<socgen:parameter> |
<socgen:name>WIDTH</socgen:name> |
<socgen:description>Number of data bits</socgen:description> |
</socgen:parameter> |
|
<socgen:parameter> |
<socgen:name>WORDS</socgen:name> |
<socgen:description>Number of memory words. Must be fully addressable by ADDR address bits</socgen:description> |
</socgen:parameter> |
|
<socgen:parameter> |
<socgen:name>WRITETHRU</socgen:name> |
<socgen:description>If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new</socgen:description> |
</socgen:parameter> |
|
<socgen:parameter> |
<socgen:name>DEFAULT</socgen:name> |
<socgen:description>Output read value if cs and rd are not both active </socgen:description> |
</socgen:parameter> |
|
<socgen:parameter> |
<socgen:name>INIT_FILE</socgen:name> |
<socgen:description>Filename of memory image loaded at startup</socgen:description> |
</socgen:parameter> |
|
<socgen:parameter> |
<socgen:name>INSTANCE_NAME</socgen:name> |
<socgen:description>Instance name of sram. Only needed for asic tool flows</socgen:description> |
</socgen:parameter> |
|
|
|
</socgen:parameters> |
|
|
|
<socgen:interfaces> |
|
<socgen:interface> |
<socgen:name>addr</socgen:name> |
<socgen:description>Memory address bits</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>raddr</socgen:name> |
<socgen:description>Memory read address bits</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>waddr</socgen:name> |
<socgen:description>Memory write address bits</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>clk</socgen:name> |
<socgen:description>Active high clock</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>cs</socgen:name> |
<socgen:description>Active high chip select</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>rd</socgen:name> |
<socgen:description>Active high read enable</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>wr</socgen:name> |
<socgen:description>Active high write enable</socgen:description> |
</socgen:interface> |
|
|
<socgen:interface> |
<socgen:name>be</socgen:name> |
<socgen:description>Active high byte enable</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>rdata</socgen:name> |
<socgen:description>read data out</socgen:description> |
</socgen:interface> |
|
<socgen:interface> |
<socgen:name>wdata</socgen:name> |
<socgen:description>write data in</socgen:description> |
</socgen:interface> |
|
|
</socgen:interfaces> |
|
|
|
|
|
|
|
|
</socgen:doc> |
|
|
|
|
|
</socgen:componentConfiguration> |
|
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<html> |
<head> |
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8"> |
<title>start</title> |
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)"> |
<meta name="CREATED" content="0;0"> |
<meta name="CHANGED" content="20090513;8521600"> |
<meta name="KEYWORDS" content="start"> |
<meta name="Info 3" content=""> |
<meta name="Info 4" content=""> |
<meta name="date" content="2008-01-08T12:01:41-0500"> |
<meta name="robots" content="index,follow"> |
</head> |
<body dir="ltr" lang="en-US"> |
<h1><a name="cde_sram_dp"></a>SOCGEN Datasheet:<br> |
</h1> |
<div id="toc__inside" dir="ltr"> |
<ul> |
<li> |
<p style="margin-bottom: 0in;"><a href="#cde_sram_dp">cde_sram_dp<br> |
</a></p> |
<br> |
<br> Synchronous two-port ram with seperate read/write ports |
<br> |
<li> |
<p><a href="../src/cde_sram_dp.v">SourceCode <br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Parameters">Parameters<br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Interface">Interface<br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Children">Children<br> |
</a></p> |
</li> |
<li> |
<p><a href="../../html/cde_sram_dp.html#TheoryofOperation">Theory of Operation<br> |
</a></p> |
</li> |
</ul> |
</li> |
</ul> |
</div> |
<img style="width: 683px; height: 278px;" alt="" src="../png/cde_sram_dp_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
<br> |
</b> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">Name<br> </td> |
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ADDR<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WIDTH<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of data bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WORDS<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">INIT_FILE<br> </td> |
<td style="vertical-align: top;">"NONE"<br> </td> |
<td style="vertical-align: top;">Filename of memory image loaded at startup<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">INSTANCE_NAME<br> </td> |
<td style="vertical-align: top;">"U1"<br> </td> |
<td style="vertical-align: top;">Instance name of sram. Only needed for asic tool flows<br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<p><br> |
</p> |
<p><b><b><br> |
</b></b></p> |
<p><b><b><br> |
<br> |
</b></b></p> |
<h2><b><b><a name="Interface"></a>Interface</b><b> <br> |
</b></b></h2> |
<p style="margin-bottom: 0in;"></p> |
<br> |
<br> |
<br> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" |
cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">NAME<br> </td> |
<td style="vertical-align: top;">Type<br> </td> |
<td style="vertical-align: top;">Description<br> </td> |
</tr> |
<tr> |
<td style="vertical-align: top;">clk<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high clock<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">cs<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high chip select<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">raddr[ADDR-1:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Memory read address bits<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rd<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high read enable<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rdata[WIDTH-1:0 ]<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;">read data out<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">waddr[ADDR-1:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Memory write address bits<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">wdata[WIDTH-1:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">write data in<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">wr<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high write enable<br> </td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<h2><b><a name="Children"></a>Children<br></b></h2> |
<b><br> |
</b> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">Instance<br> </td> |
<td style="vertical-align: top;">Vendor<br> </td> |
<td style="vertical-align: top;">Library<br></td> |
<td style="vertical-align: top;">Component<br></td> |
<td style="vertical-align: top;">Version<br></td> |
</tr> |
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<br> |
<br> |
<br> |
<br> |
<br> |
<br> |
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<img style="width: 683px; height: 278px;" alt="" src="../png/cde_sram_dp_sch.png"><br> |
<b><br> |
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</body> |
</html> |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<html> |
<head> |
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8"> |
<title>start</title> |
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)"> |
<meta name="CREATED" content="0;0"> |
<meta name="CHANGED" content="20090513;8521600"> |
<meta name="KEYWORDS" content="start"> |
<meta name="Info 3" content=""> |
<meta name="Info 4" content=""> |
<meta name="date" content="2008-01-08T12:01:41-0500"> |
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</head> |
<body dir="ltr" lang="en-US"> |
<h1><a name="cde_sram_be"></a>SOCGEN Datasheet:<br> |
</h1> |
<div id="toc__inside" dir="ltr"> |
<ul> |
<li> |
<p style="margin-bottom: 0in;"><a href="#cde_sram_be">cde_sram_be<br> |
</a></p> |
<br> |
<br> Synchronous one-port ram with byte enable |
<br> |
<li> |
<p><a href="../src/cde_sram_be.v">SourceCode <br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Parameters">Parameters<br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Interface">Interface<br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Children">Children<br> |
</a></p> |
</li> |
<li> |
<p><a href="../../html/cde_sram_be.html#TheoryofOperation">Theory of Operation<br> |
</a></p> |
</li> |
</ul> |
</li> |
</ul> |
</div> |
<img style="width: 683px; height: 278px;" alt="" src="../png/cde_sram_be_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
<br> |
</b> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">Name<br> </td> |
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ADDR<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WIDTH<br> </td> |
<td style="vertical-align: top;">8<br> </td> |
<td style="vertical-align: top;">Number of data bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WORDS<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">INIT_FILE<br> </td> |
<td style="vertical-align: top;">"NONE"<br> </td> |
<td style="vertical-align: top;">Filename of memory image loaded at startup<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">INSTANCE_NAME<br> </td> |
<td style="vertical-align: top;">"U1"<br> </td> |
<td style="vertical-align: top;">Instance name of sram. Only needed for asic tool flows<br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<p><br> |
</p> |
<p><b><b><br> |
</b></b></p> |
<p><b><b><br> |
<br> |
</b></b></p> |
<h2><b><b><a name="Interface"></a>Interface</b><b> <br> |
</b></b></h2> |
<p style="margin-bottom: 0in;"></p> |
<br> |
<br> |
<br> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" |
cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">NAME<br> </td> |
<td style="vertical-align: top;">Type<br> </td> |
<td style="vertical-align: top;">Description<br> </td> |
</tr> |
<tr> |
<td style="vertical-align: top;">addr[ADDR-1:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Memory address bits<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">be<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high byte enable<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">clk<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high clock<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">cs<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high chip select<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rd<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high read enable<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rdata[WIDTH-1:0 ]<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;">read data out<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">wdata[WIDTH-1:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">write data in<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">wr<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high write enable<br> </td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<h2><b><a name="Children"></a>Children<br></b></h2> |
<b><br> |
</b> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">Instance<br> </td> |
<td style="vertical-align: top;">Vendor<br> </td> |
<td style="vertical-align: top;">Library<br></td> |
<td style="vertical-align: top;">Component<br></td> |
<td style="vertical-align: top;">Version<br></td> |
</tr> |
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<br> |
<br> |
<br> |
<br> |
<br> |
<br> |
<br> |
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<img style="width: 683px; height: 278px;" alt="" src="../png/cde_sram_be_sch.png"><br> |
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</body> |
</html> |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> |
<html> |
<head> |
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8"> |
<title>start</title> |
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)"> |
<meta name="CREATED" content="0;0"> |
<meta name="CHANGED" content="20090513;8521600"> |
<meta name="KEYWORDS" content="start"> |
<meta name="Info 3" content=""> |
<meta name="Info 4" content=""> |
<meta name="date" content="2008-01-08T12:01:41-0500"> |
<meta name="robots" content="index,follow"> |
</head> |
<body dir="ltr" lang="en-US"> |
<h1><a name="cde_sram_def"></a>SOCGEN Datasheet:<br> |
</h1> |
<div id="toc__inside" dir="ltr"> |
<ul> |
<li> |
<p style="margin-bottom: 0in;"><a href="#cde_sram_def">cde_sram_def<br> |
</a></p> |
<br> |
<br> Synchronous one-port ram |
<br> |
<li> |
<p><a href="../src/cde_sram_def.v">SourceCode <br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Parameters">Parameters<br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Interface">Interface<br> |
</a></p> |
</li> |
<li> |
<p style="margin-bottom: 0in;"><a href="#Children">Children<br> |
</a></p> |
</li> |
<li> |
<p><a href="../../html/cde_sram_def.html#TheoryofOperation">Theory of Operation<br> |
</a></p> |
</li> |
</ul> |
</li> |
</ul> |
</div> |
<img style="width: 683px; height: 254px;" alt="" src="../png/cde_sram_def_sym.png"><br> |
<b><br> |
<h2><b><a name="Parameters"></a>Parameters<br></b></h2> |
<b><br> |
<br> |
</b> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">Name<br> </td> |
<td style="vertical-align: top;">default <br> </td> |
<td style="vertical-align: top;">Description<br></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">ADDR<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WIDTH<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of data bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WORDS<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">WRITETHRU<br> </td> |
<td style="vertical-align: top;">0<br> </td> |
<td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">DEFAULT<br> </td> |
<td style="vertical-align: top;">{WIDTH{1'bx}}<br> </td> |
<td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">INIT_FILE<br> </td> |
<td style="vertical-align: top;">"NONE"<br> </td> |
<td style="vertical-align: top;">Filename of memory image loaded at startup<br></td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">INSTANCE_NAME<br> </td> |
<td style="vertical-align: top;">"U1"<br> </td> |
<td style="vertical-align: top;">Instance name of sram. Only needed for asic tool flows<br></td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<p><br> |
</p> |
<p><b><b><br> |
</b></b></p> |
<p><b><b><br> |
<br> |
</b></b></p> |
<h2><b><b><a name="Interface"></a>Interface</b><b> <br> |
</b></b></h2> |
<p style="margin-bottom: 0in;"></p> |
<br> |
<br> |
<br> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" |
cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">NAME<br> </td> |
<td style="vertical-align: top;">Type<br> </td> |
<td style="vertical-align: top;">Description<br> </td> |
</tr> |
<tr> |
<td style="vertical-align: top;">addr[ADDR-1:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Memory address bits<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">clk<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high clock<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">cs<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high chip select<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rd<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high read enable<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">rdata[WIDTH-1:0 ]<br> </td> |
<td style="vertical-align: top;">output<br> </td> |
<td style="vertical-align: top;">read data out<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">wdata[WIDTH-1:0 ]<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">write data in<br> </td> |
</tr> |
|
<tr> |
<td style="vertical-align: top;">wr<br> </td> |
<td style="vertical-align: top;">input<br> </td> |
<td style="vertical-align: top;">Active high write enable<br> </td> |
</tr> |
|
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<h2><b><a name="Children"></a>Children<br></b></h2> |
<b><br> |
</b> |
<table style="text-align: left; width: 640px; height: 120px;" border="8" cellpadding="4" cellspacing="4"> |
<tbody> |
<tr> |
<td style="vertical-align: top;">Instance<br> </td> |
<td style="vertical-align: top;">Vendor<br> </td> |
<td style="vertical-align: top;">Library<br></td> |
<td style="vertical-align: top;">Component<br></td> |
<td style="vertical-align: top;">Version<br></td> |
</tr> |
</tbody> |
</table> |
<p><b><b><br> |
</b></b></p> |
<br> |
<br> |
<br> |
<br> |
<br> |
<br> |
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<br> |
<img style="width: 683px; height: 254px;" alt="" src="../png/cde_sram_def_sch.png"><br> |
<b><br> |
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SOCGEN Datasheet:
+-
+
+
+
Theory of +Operation
+The synchronous ram modules provide a variety of memory storage
+options.
Both reads and writes are synchronous to the rising edge
+of clk.
Memory may be initialized from a bit file and later
+overwritten by memory writes.
If WRITETHRU is set to 1 then a
+simultaneous read/write to the same address will read the new data.
+
If set to 0 it will return the old.
Setting DEFAULT
+determines the value of rdata when a read is not
+occurring
+
-
+
-
+
+
-
+
- + + + +
- + + + +
- + + +
+
+ + + Index: cde/trunk/ip/sram/doc/html/cde_sram_be.html =================================================================== --- cde/trunk/ip/sram/doc/html/cde_sram_be.html (nonexistent) +++ cde/trunk/ip/sram/doc/html/cde_sram_be.html (revision 2) @@ -0,0 +1,45 @@ + + + + +
SOCGEN Datasheet:
+-
+
+
+
Theory of +Operation
+The synchronous ram modules provide a variety of memory storage
+options.
Both reads and writes are synchronous to the rising edge
+of clk.
Memory may be initialized from a bit file and later
+overwritten by memory writes.
If WRITETHRU is set to 1 then a
+simultaneous read/write to the same address will read the new data.
+
If set to 0 it will return the old.
Setting DEFAULT
+determines the value of rdata when a read is not
+occurring
+
SOCGEN Datasheet:
+-
+
+
+
Theory of +Operation
+The synchronous ram modules provide a variety of memory storage
+options.
Both reads and writes are synchronous to the rising edge
+of clk.
Memory may be initialized from a bit file and later
+overwritten by memory writes.
If WRITETHRU is set to 1 then a
+simultaneous read/write to the same address will read the new data.
+
If set to 0 it will return the old.
Setting DEFAULT
+determines the value of rdata when a read is not
+occurring
+
SOCGEN Datasheet:
+
+ -
+
-
+
+
+
Single ended tristatable digital pad +
+ - + + +
- + + +
- + + +
- + + +
- + + +
+
+
Parameters
+ +
+ +
Name |
+ default |
+ Description |
+
+
+
+
+
+
Interface
+
+
+ +
+
+
NAME |
+ Type |
+ Description |
+
PAD |
+ inout |
+ PCA Pad connection |
+
pad_oe |
+ input |
+ Active high tristate drive signal |
+
pad_out |
+ input |
+ Output signal |
+
+
Children
+ + +
Instance |
+ Vendor |
+ Library |
+ Component |
+ Version |
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_od_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_od_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_od_dig.html (revision 2) @@ -0,0 +1,161 @@ + + + + +
SOCGEN Datasheet:
+
+ -
+
-
+
+
+
Single ended open drain digital pad +
+ - + + +
- + + +
- + + +
- + + +
- + + +
+
+
Parameters
+ +
+ +
Name |
+ default |
+ Description |
+
+
+
+
+
+
Interface
+
+
+ +
+
+
NAME |
+ Type |
+ Description |
+
PAD |
+ inout |
+ PCA Pad connection |
+
pad_in |
+ output |
+ Input signal |
+
pad_oe |
+ input |
+ Active high tristate drive signal |
+
+
Children
+ + +
Instance |
+ Vendor |
+ Library |
+ Component |
+ Version |
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_in_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_in_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_in_dig.html (revision 2) @@ -0,0 +1,161 @@ + + + + +
SOCGEN Datasheet:
+
+ -
+
-
+
+
+
Single ended input digital pad +
+ - + + +
- + + +
- + + +
- + + +
- + + +
+
+
Parameters
+ +
+ +
Name |
+ default |
+ Description |
+
WIDTH |
+ 1 |
+ Width of pad |
+
+
+
+
+
+
Interface
+
+
+ +
+
+
NAME |
+ Type |
+ Description |
+
PAD[WIDTH-1:0 ] |
+ input |
+ PCA Pad connection |
+
pad_in[WIDTH-1:0 ] |
+ output |
+ Input signal |
+
+
Children
+ + +
Instance |
+ Vendor |
+ Library |
+ Component |
+ Version |
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_out_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_out_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_out_dig.html (revision 2) @@ -0,0 +1,161 @@ + + + + +
SOCGEN Datasheet:
+
+ -
+
-
+
+
+
Single ended output digital pad +
+ - + + +
- + + +
- + + +
- + + +
- + + +
+
+
Parameters
+ +
+ +
Name |
+ default |
+ Description |
+
WIDTH |
+ 1 |
+ Width of pad |
+
+
+
+
+
+
Interface
+
+
+ +
+
+
NAME |
+ Type |
+ Description |
+
PAD[WIDTH-1:0 ] |
+ output |
+ PCA Pad connection |
+
pad_out[WIDTH-1:0 ] |
+ input |
+ Output signal |
+
+
Children
+ + +
Instance |
+ Vendor |
+ Library |
+ Component |
+ Version |
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/html/cde_pad_se_dig.html =================================================================== --- cde/trunk/ip/pad/doc/Geda/html/cde_pad_se_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/html/cde_pad_se_dig.html (revision 2) @@ -0,0 +1,173 @@ + + + + +
SOCGEN Datasheet:
+
+ -
+
-
+
+
+
Single ended bidirectional digital pad +
+ - + + +
- + + +
- + + +
- + + +
- + + +
+
+
Parameters
+ +
+ +
Name |
+ default |
+ Description |
+
WIDTH |
+ 1 |
+ Width of pad |
+
+
+
+
+
+
Interface
+
+
+ +
+
+
NAME |
+ Type |
+ Description |
+
PAD[WIDTH-1:0 ] |
+ inout |
+ PCA Pad connection |
+
pad_in[WIDTH-1:0 ] |
+ output |
+ Input signal |
+
pad_oe |
+ input |
+ Active high tristate drive signal |
+
pad_out[WIDTH-1:0 ] |
+ input |
+ Output signal |
+
+
Children
+ + +
Instance |
+ Vendor |
+ Library |
+ Component |
+ Version |
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/Geda/png/cde_pad_od_dig_sym.png (revision 2)
SOCGEN Datasheet:
+
+-
+
-
+
-
+
- + + +
+
+
+ +
+
+
+
+
+
+
Theory of Operation
++
+
+
+
+ +
+ + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/html/component.html =================================================================== --- cde/trunk/ip/pad/doc/html/component.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/component.html (revision 2) @@ -0,0 +1,49 @@ + + + + +
-
+
- + + + +
+ + + Index: cde/trunk/ip/pad/doc/html/cde_pad_od_dig.html =================================================================== --- cde/trunk/ip/pad/doc/html/cde_pad_od_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/cde_pad_od_dig.html (revision 2) @@ -0,0 +1,126 @@ + + + + +
SOCGEN Datasheet:
+
+-
+
-
+
-
+
- + + +
+
+
+ +
+
+
+
+
+
+
Theory of Operation
++
+
+
+
+ +
+ + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/html/cde_pad_in_dig.html =================================================================== --- cde/trunk/ip/pad/doc/html/cde_pad_in_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/cde_pad_in_dig.html (revision 2) @@ -0,0 +1,126 @@ + + + + +
SOCGEN Datasheet:
+
+-
+
-
+
-
+
- + + +
+
+
+ +
+
+
+
+
+
+
Theory of Operation
++
+
+
+
+ +
+ + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/html/cde_pad_out_dig.html =================================================================== --- cde/trunk/ip/pad/doc/html/cde_pad_out_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/cde_pad_out_dig.html (revision 2) @@ -0,0 +1,126 @@ + + + + +
SOCGEN Datasheet:
+
+-
+
-
+
-
+
- + + +
+
+
+ +
+
+
+
+
+
+
Theory of Operation
++
+
+
+
+ +
+ + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/html/cde_pad_se_dig.html =================================================================== --- cde/trunk/ip/pad/doc/html/cde_pad_se_dig.html (nonexistent) +++ cde/trunk/ip/pad/doc/html/cde_pad_se_dig.html (revision 2) @@ -0,0 +1,126 @@ + + + + +
SOCGEN Datasheet:
+
+-
+
-
+
-
+
- + + +
+
+
+ +
+
+
+
+
+
+
Theory of Operation
++
+
+
+
+ +
+ + +
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + Index: cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png =================================================================== --- cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png (nonexistent) +++ cde/trunk/ip/pad/doc/png/cde_pad_od_dig_sym.png (revision 2)