URL
https://opencores.org/ocsvn/darkriscv/darkriscv/trunk
Subversion Repositories darkriscv
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/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/README.md
0,0 → 1,23
## Aliexpress HPC 40GbE K420 |
|
The correct name for this board is "Kintex-7 HPC V2", but is more widely |
know as "Aliexpress HPC 40GbE K420" board, since there are lots of HPC |
boards in the Aliexpress site. In fact, this board is not manufactured |
anymore, as long the original store sadly disappeared after 7 good years! :( |
|
The board includes: |
|
- a XC7K420 FPGA w/ 910 pins |
- lots pf high-speed clocks: 100MHz, 125MHz, 133MHz and 156MHz |
- on-board USB/serial (CH340) |
- on-board SPI FLASH |
- on-board 2xSFP+ (for up to 2x10Gbps) |
- on-board 2xQSFP (for up to 2x40Gbps) |
- on-board dual-channel 1033MHz DDR3 |
- 16 LEDs |
- 2 swiches |
- 4 SMA connectors |
- SATA interface |
- PCIe 8x |
- 3x different JTAG connectors (you need an external JTAG adapter!) |
- support for darkriscv running at 220MHz! |
/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/darksocv.imp
0,0 → 1,7
setMode -bs |
setCable -port auto |
Identify -inferir |
identifyMPM |
assignFile -p 1 -file "../tmp/darksocv.bit" |
Program -p 1 |
quit |
/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/darksocv.mk
0,0 → 1,100
# |
# Copyright (c) 2018, Marcelo Samsoniuk |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions are met: |
# |
# * Redistributions of source code must retain the above copyright notice, this |
# list of conditions and the following disclaimer. |
# |
# * Redistributions in binary form must reproduce the above copyright notice, |
# this list of conditions and the following disclaimer in the documentation |
# and/or other materials provided with the distribution. |
# |
# * Neither the name of the copyright holder nor the names of its |
# contributors may be used to endorse or promote products derived from |
# this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
# ===8<--------------------------------------------------------- cut here! |
# |
# The general concept is based in the article: |
# |
# https://www.fpgarelated.com/showarticle/786.php |
# |
# However, since the ISE GUI itself creates a "darksocv.cmd_log" file with |
# all commands executed and the respective options, it is possible change |
# some options in the ISE and check the file in order to understand how |
# enable/disable the different options. |
# |
|
# board Aliexpress HPC 40GbE K420 |
BOARD = aliexpress_hpc40gbe_k420 |
DEVICE = xc7k420t-ffg901-2 |
|
ISE = ../boards/$(BOARD) |
RTL = ../rtl |
SRC = ../src |
TMP = ../tmp |
|
XST = $(ISE)/darksocv.xst |
SYR = $(TMP)/darksocv.syr |
UCF = $(ISE)/darksocv.ucf |
IMP = $(ISE)/darksocv.imp |
NGC = $(TMP)/darksocv.ngc |
NGD = $(TMP)/darksocv.ngd |
PCF = $(TMP)/darksocv.pcf |
NCD = $(TMP)/darksocv.ncd |
TWX = $(TMP)/darksocv.twx |
TWR = $(TMP)/darksocv.twr |
BIT = $(TMP)/darksocv.bit |
MAP = $(TMP)/darksocv_map.ncd |
UT = $(ISE)/darksocv.ut |
|
PRJS = $(ISE)/darksocv.prj |
RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v $(RTL)/config.vh |
|
ifdef HARVARD |
BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem |
else |
BOOT = $(SRC)/darksocv.mem |
endif |
|
IMP = $(ISE)/darksocv.imp |
|
default: all |
|
$(NGC): $(PRJS) $(BOOT) $(RTLS) |
cd $(TMP) && xst -intstyle ise -ifn $(XST) -ofn $(SYR) |
|
$(NGD): $(NGC) $(UCF) $(BOOT) $(RTLS) |
cd $(TMP) && ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc $(UCF) -p $(DEVICE) $(NGC) $(NGD) |
|
$(PCF): $(NGD) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && map -intstyle ise -p $(DEVICE) -w -logic_opt on -ol high -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -detail -ir off -ignore_keep_hierarchy -pr off -lc auto -power off -o $(MAP) $(NGD) $(PCF) |
|
$(NCD): $(PCF) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && par -w -intstyle ise -ol high -mt 2 $(MAP) $(NCD) $(PCF) |
cd $(TMP) && trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml $(TWX) $(NCD) -o $(TWR) $(PCF) |
|
$(BIT): $(UT) $(NCD) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && bitgen -intstyle ise -f $(UT) $(NCD) |
|
all: $(BIT) $(BOOT) $(UCF) $(RTLS) |
|
install: $(BIT) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && impact -batch $(IMP) |
|
clean: |
-rm -v $(TMP)/* |
/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/darksocv.prj
0,0 → 1,3
verilog work "../rtl/darkriscv.v" |
verilog work "../rtl/darksocv.v" |
verilog work "../rtl/darkuart.v" |
/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/darksocv.ucf
0,0 → 1,58
# Copyright (c) 2018, Marcelo Samsoniuk |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions are met: |
# |
# * Redistributions of source code must retain the above copyright notice, this |
# list of conditions and the following disclaimer. |
# |
# * Redistributions in binary form must reproduce the above copyright notice, |
# this list of conditions and the following disclaimer in the documentation |
# and/or other materials provided with the distribution. |
# |
# * Neither the name of the copyright holder nor the names of its |
# contributors may be used to endorse or promote products derived from |
# this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|
#NET "CLK" TNM_NET = CLK; |
|
# without cache controller |
#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; |
|
# with cache controller |
#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; |
|
# AliExpress HPC 40GbE K420 board |
|
NET XCLK LOC = U24 | IOSTANDARD = LVCMOS25 | PERIOD = 100MHz HIGH 50%; |
#NET XCLK LOC = K15 | PERIOD = 66MHz HIGH 50%; |
#NET XCLK LOC = V10 | PERIOD = 40MHz HIGH 50%; |
|
NET XRES LOC = A16 | IOSTANDARD = LVCMOS25 | PULLDOWN; |
|
NET UART_RXD LOC = D17 | IOSTANDARD = LVCMOS25 | PULLUP; |
NET UART_TXD LOC = D16 | IOSTANDARD = LVCMOS25; |
|
NET LED[3] LOC = A27 | IOSTANDARD = LVCMOS15; |
NET LED[2] LOC = E24 | IOSTANDARD = LVCMOS15; |
NET LED[1] LOC = G24 | IOSTANDARD = LVCMOS15; |
NET LED[0] LOC = H21 | IOSTANDARD = LVCMOS15; |
|
NET DEBUG[3] LOC = G27 | IOSTANDARD = LVCMOS15; # J4-1 |
NET DEBUG[2] LOC = H26 | IOSTANDARD = LVCMOS15; # J4-2 |
NET DEBUG[1] LOC = H25 | IOSTANDARD = LVCMOS15; # J4-3 |
NET DEBUG[0] LOC = H24 | IOSTANDARD = LVCMOS15; # J4-4 |
|
|
/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/darksocv.ut
0,0 → 1,39
-g UnconstrainedPins:Allow |
-w |
-g DebugBitstream:No |
-g Binary:no |
-g CRC:Enable |
-g ConfigRate:3 |
-g CclkPin:PullUp |
-g M0Pin:PullUp |
-g M1Pin:PullUp |
-g M2Pin:PullUp |
-g ProgPin:PullUp |
-g InitPin:Pullup |
-g TckPin:PullUp |
-g TdiPin:PullUp |
-g TdoPin:PullUp |
-g TmsPin:PullUp |
-g Disable_JTAG:No |
-g UnusedPin:PullDown |
-g UserID:0xFFFFFFFF |
-g ExtMasterCclk_en:Disable |
-g ConfigFallback:Disable |
-g BPI_page_size:1 |
-g BPI_sync_mode:Disable |
-g SPI_32bit_addr:No |
-g SPI_buswidth:1 |
-g SPI_Fall_Edge:No |
-g OverTempPowerDown:Disable |
-g USR_ACCESS:None |
-g JTAG_XADC:Enable |
-g DCIUpdateMode:AsRequired |
-g StartUpClk:CClk |
-g DONE_cycle:4 |
-g GTS_cycle:5 |
-g GWE_cycle:6 |
-g Match_cycle:Auto |
-g Security:None |
-g ICAP_select:Auto |
-g DonePipe:Yes |
-g Encrypt:No |
/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/darksocv.xise
0,0 → 1,382
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="../../rtl/darkriscv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="../../rtl/darksocv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="../../rtl/darkuart.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="../../sim/darksimv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/> |
</file> |
<file xil_pn:name="darksocv.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
</files> |
|
<properties> |
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc7k420t" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Module|darksocv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/darksocv.v" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/darksocv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="High" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="-g UnconstrainedPins:Allow" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="darksocv" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="ffg901" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="darksocv_map.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="darksocv_timesim.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="darksocv_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="darksocv_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/darksimv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.darksimv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.darksimv" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="ALIEXPRESS_HPC40GBE_K420=1" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="../../tmp" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|darksimv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="darkriscv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-24T20:01:44" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3E4CA3137C81E741F5DACA4F53F1B6A8" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="OutSideAbove" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings> |
<binding xil_pn:location="/darksocv" xil_pn:name="darksocv.ucf"/> |
</bindings> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
<file xil_pn:name="../../rtl/config.vh" xil_pn:type="FILE_VERILOG"/> |
</autoManagedFiles> |
|
</project> |
/darkriscv/trunk/boards/aliexpress_hpc40gbe_k420/darksocv.xst
0,0 → 1,55
set -tmpdir "../tmp" |
set -xsthdpdir "../tmp/" |
run |
-ifn ../boards/aliexpress_hpc40gbe_k420/darksocv.prj |
-ofn darksocv |
-ofmt NGC |
-p xc7k420t-2-ffg901 |
-top darksocv |
-opt_mode Speed |
-opt_level 2 |
-power NO |
-iuc NO |
-keep_hierarchy No |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-dsp_utilization_ratio 100 |
-lc Auto |
-reduce_control_sets Auto |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-shreg_extract YES |
-rom_style Auto |
-auto_bram_packing NO |
-resource_sharing YES |
-async_to_sync NO |
-shreg_min_size 2 |
-use_dsp48 Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 16 |
-register_duplication YES |
-register_balancing Yes |
-move_first_stage YES |
-move_last_stage YES |
-optimize_primitives NO |
-use_clock_enable Auto |
-use_sync_set Auto |
-use_sync_reset Auto |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
-define ALIEXPRESS_HPC40GBE_K420=1 |
/darkriscv/trunk/boards/avnet_microboard_lx9/README.md
0,0 → 1,17
## AVNET Microboard LX9 |
|
The old AVNET Microboard LX9 is my preferred development board because is |
small, easy to connect to the development environment and very complete, |
with integrated JTAG, USB/serial and Ethernet! |
|
The board includes: |
|
- a XC6SLX9 FPGA w/ 324 pins |
- lots of clocks: 40MHz, 66MHz and 100MHz |
- on-board USB/serial (CP2102) |
- on-board JTAG |
- on-board SPI FLASH |
- on-board 10/100Mbps ethernet PHY |
- on-board DDR |
- four LEDs |
- some few GPIO pins |
/darkriscv/trunk/boards/avnet_microboard_lx9/darksocv.imp
0,0 → 1,7
setMode -bs |
setCable -port auto |
Identify -inferir |
identifyMPM |
assignFile -p 1 -file "../tmp/darksocv.bit" |
Program -p 1 |
quit |
/darkriscv/trunk/boards/avnet_microboard_lx9/darksocv.mk
0,0 → 1,108
# |
# Copyright (c) 2018, Marcelo Samsoniuk |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions are met: |
# |
# * Redistributions of source code must retain the above copyright notice, this |
# list of conditions and the following disclaimer. |
# |
# * Redistributions in binary form must reproduce the above copyright notice, |
# this list of conditions and the following disclaimer in the documentation |
# and/or other materials provided with the distribution. |
# |
# * Neither the name of the copyright holder nor the names of its |
# contributors may be used to endorse or promote products derived from |
# this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
# ===8<--------------------------------------------------------- cut here! |
# |
# The general concept is based in the article: |
# |
# https://www.fpgarelated.com/showarticle/786.php |
# |
# However, since the ISE GUI itself creates a "darksocv.cmd_log" file with |
# all commands executed and the respective options, it is possible change |
# some options in the ISE and check the file in order to understand how |
# enable/disable the different options. |
# |
|
# board Avnet Microboard LX9 |
BOARD = avnet_microboard_lx9 |
DEVICE = xc6slx9-csg324-2 |
|
# board Xilinx AC701 A200 |
#BOARD = xilinx_ac701_a200 |
#DEVICE = xc7a200t-fbg676-2 |
|
# board QMTech SDRAM LX16 |
#BOARD = qmtech_sdram_lx16 |
#DEVICE = xc6slx16-ftg256-2 |
|
ISE = ../boards/$(BOARD) |
RTL = ../rtl |
SRC = ../src |
TMP = ../tmp |
|
XST = $(ISE)/darksocv.xst |
SYR = $(TMP)/darksocv.syr |
UCF = $(ISE)/darksocv.ucf |
IMP = $(ISE)/darksocv.imp |
NGC = $(TMP)/darksocv.ngc |
NGD = $(TMP)/darksocv.ngd |
PCF = $(TMP)/darksocv.pcf |
NCD = $(TMP)/darksocv.ncd |
TWX = $(TMP)/darksocv.twx |
TWR = $(TMP)/darksocv.twr |
BIT = $(TMP)/darksocv.bit |
MAP = $(TMP)/darksocv_map.ncd |
UT = $(ISE)/darksocv.ut |
|
PRJS = $(ISE)/darksocv.prj |
RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v $(RTL)/config.vh |
|
ifdef HARVARD |
BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem |
else |
BOOT = $(SRC)/darksocv.mem |
endif |
|
IMP = $(ISE)/darksocv.imp |
|
default: all |
|
$(NGC): $(PRJS) $(BOOT) $(RTLS) |
cd $(TMP) && xst -intstyle ise -ifn $(XST) -ofn $(SYR) |
|
$(NGD): $(NGC) $(UCF) $(BOOT) $(RTLS) |
cd $(TMP) && ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc $(UCF) -p $(DEVICE) $(NGC) $(NGD) |
|
$(PCF): $(NGD) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && map -intstyle ise -p $(DEVICE) -w -logic_opt on -ol high -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -detail -ir off -ignore_keep_hierarchy -pr off -lc auto -power off -o $(MAP) $(NGD) $(PCF) |
|
$(NCD): $(PCF) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && par -w -intstyle ise -ol high -mt 2 $(MAP) $(NCD) $(PCF) |
cd $(TMP) && trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml $(TWX) $(NCD) -o $(TWR) $(PCF) |
|
$(BIT): $(UT) $(NCD) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && bitgen -intstyle ise -f $(UT) $(NCD) |
|
all: $(BIT) $(BOOT) $(UCF) $(RTLS) |
|
install: $(BIT) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && impact -batch $(IMP) |
|
clean: |
-rm -v $(TMP)/* |
/darkriscv/trunk/boards/avnet_microboard_lx9/darksocv.prj
0,0 → 1,3
verilog work "../rtl/darkriscv.v" |
verilog work "../rtl/darksocv.v" |
verilog work "../rtl/darkuart.v" |
/darkriscv/trunk/boards/avnet_microboard_lx9/darksocv.ucf
0,0 → 1,56
# Copyright (c) 2018, Marcelo Samsoniuk |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions are met: |
# |
# * Redistributions of source code must retain the above copyright notice, this |
# list of conditions and the following disclaimer. |
# |
# * Redistributions in binary form must reproduce the above copyright notice, |
# this list of conditions and the following disclaimer in the documentation |
# and/or other materials provided with the distribution. |
# |
# * Neither the name of the copyright holder nor the names of its |
# contributors may be used to endorse or promote products derived from |
# this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|
#NET "CLK" TNM_NET = CLK; |
|
# without cache controller |
#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; |
|
# with cache controller |
#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; |
|
# AVNET board LX9 microboard |
|
NET XCLK LOC = C10 | PERIOD = 100MHz HIGH 50%; |
#NET XCLK LOC = K15 | PERIOD = 66MHz HIGH 50%; |
#NET XCLK LOC = V10 | PERIOD = 40MHz HIGH 50%; |
|
NET XRES LOC = V4 | PULLDOWN; |
|
NET UART_RXD LOC = R7; |
NET UART_TXD LOC = T7; |
|
NET LED[3] LOC = P4; |
NET LED[2] LOC = L6; |
NET LED[1] LOC = F5; |
NET LED[0] LOC = C2; |
|
NET DEBUG[3] LOC = H12; # J4-1 |
NET DEBUG[2] LOC = G13; # J4-2 |
NET DEBUG[1] LOC = E16; # J4-3 |
NET DEBUG[0] LOC = E18; # J4-4 |
/darkriscv/trunk/boards/avnet_microboard_lx9/darksocv.ut
0,0 → 1,30
-w |
-g DebugBitstream:No |
-g Binary:no |
-g CRC:Enable |
#-g Reset_on_err:No |
#-g ConfigRate:2 |
-g ProgPin:PullUp |
-g TckPin:PullUp |
-g TdiPin:PullUp |
-g TdoPin:PullUp |
-g TmsPin:PullUp |
-g UnusedPin:PullDown |
-g UserID:0xFFFFFFFF |
-g ExtMasterCclk_en:No |
-g SPI_buswidth:1 |
-g TIMER_CFG:0xFFFF |
-g multipin_wakeup:No |
-g StartUpClk:CClk |
-g DONE_cycle:4 |
-g GTS_cycle:5 |
-g GWE_cycle:6 |
-g LCK_cycle:NoWait |
-g Security:None |
-g DonePipe:Yes |
-g DriveDone:No |
-g en_sw_gsr:No |
-g drive_awake:No |
-g sw_clk:Startupclk |
-g sw_gwe_cycle:5 |
-g sw_gts_cycle:4 |
/darkriscv/trunk/boards/avnet_microboard_lx9/darksocv.xise
0,0 → 1,382
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="../../rtl/darkriscv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="../../rtl/darksocv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="../../rtl/darkuart.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="../../sim/darksimv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/> |
</file> |
<file xil_pn:name="darksocv.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
</files> |
|
<properties> |
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
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<property xil_pn:name="Implementation Top" xil_pn:value="Module|darksocv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/darksocv.v" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/darksocv" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
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<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
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<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="darksocv" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="darksocv_map.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="darksocv_timesim.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="darksocv_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="darksocv_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
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<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
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<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
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<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> |
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/darksimv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.darksimv" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
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<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
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<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="AVNET_MICROBOARD_LX9=1" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="../../tmp" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|darksimv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="darkriscv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-24T20:01:44" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3E4CA3137C81E741F5DACA4F53F1B6A8" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="OutSideAbove" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings> |
<binding xil_pn:location="/darksocv" xil_pn:name="darksocv.ucf"/> |
</bindings> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
<file xil_pn:name="../../rtl/config.vh" xil_pn:type="FILE_VERILOG"/> |
</autoManagedFiles> |
|
</project> |
/darkriscv/trunk/boards/avnet_microboard_lx9/darksocv.xst
0,0 → 1,53
set -tmpdir "../tmp" |
set -xsthdpdir "../tmp/" |
run |
-ifn ../boards/avnet_microboard_lx9/darksocv.prj |
-ofn darksocv |
-ofmt NGC |
-p xc6slx9-2-csg324 |
-top darksocv |
-opt_mode Speed |
-opt_level 1 |
-power NO |
-iuc NO |
-keep_hierarchy No |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-dsp_utilization_ratio 100 |
-lc Auto |
-reduce_control_sets Auto |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-shreg_extract YES |
-rom_style Auto |
-auto_bram_packing NO |
-resource_sharing YES |
-async_to_sync NO |
-shreg_min_size 2 |
-use_dsp48 Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 16 |
-register_duplication YES |
-register_balancing No |
-optimize_primitives NO |
-use_clock_enable Auto |
-use_sync_set Auto |
-use_sync_reset Auto |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
-define AVNET_MICROBOARD_LX9=1 |
/darkriscv/trunk/boards/digilent_spartan3_s200/README.md
0,0 → 1,21
## Digilent Spartan3 S200 |
|
The old Digilent Spartan3 S200 is a very popular development board based in |
the XC3S200 FPGA, which use the old, but popular LUT4 technology, and |
include lots of anscient peripherals, such as: |
|
- a XC3S200 FPGA w/ 256 pins |
- lots of clocks: 50MHz oscillator |
- socket for an extra oscillator |
- on-board RS232 converter *** |
- on-board VGA interface |
- on-board PS2 interface |
- on-board Xilinx Serial FLASH |
- on-board SRAM (static SRAM) |
- 4x 8-segment displays |
- 8 LEDs |
- 8 on/off switches |
- 4 switches |
- lots of GPIO pins |
|
*** note: due to the old RS232 nature, it is recommended use 9600bps! |
/darkriscv/trunk/boards/digilent_spartan3_s200/darksocv.imp
0,0 → 1,7
setMode -bs |
setCable -port auto |
Identify -inferir |
identifyMPM |
assignFile -p 1 -file "../tmp/darksocv.bit" |
Program -p 1 |
quit |
/darkriscv/trunk/boards/digilent_spartan3_s200/darksocv.mk
0,0 → 1,102
# |
# Copyright (c) 2018, Marcelo Samsoniuk |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions are met: |
# |
# * Redistributions of source code must retain the above copyright notice, this |
# list of conditions and the following disclaimer. |
# |
# * Redistributions in binary form must reproduce the above copyright notice, |
# this list of conditions and the following disclaimer in the documentation |
# and/or other materials provided with the distribution. |
# |
# * Neither the name of the copyright holder nor the names of its |
# contributors may be used to endorse or promote products derived from |
# this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
# |
# ===8<--------------------------------------------------------- cut here! |
# |
# The general concept is based in the article: |
# |
# https://www.fpgarelated.com/showarticle/786.php |
# |
# However, since the ISE GUI itself creates a "darksocv.cmd_log" file with |
# all commands executed and the respective options, it is possible change |
# some options in the ISE and check the file in order to understand how |
# enable/disable the different options. |
# |
|
# board Digilent Spartan-3 S200 |
BOARD = digilent_spartan3_s200 |
DEVICE = xc3s200-4-ft256 |
|
ISE = ../boards/$(BOARD) |
RTL = ../rtl |
SRC = ../src |
TMP = ../tmp |
|
XST = $(ISE)/darksocv.xst |
SYR = $(TMP)/darksocv.syr |
UCF = $(ISE)/darksocv.ucf |
IMP = $(ISE)/darksocv.imp |
NGC = $(TMP)/darksocv.ngc |
NGD = $(TMP)/darksocv.ngd |
PCF = $(TMP)/darksocv.pcf |
NCD = $(TMP)/darksocv.ncd |
TWX = $(TMP)/darksocv.twx |
TWR = $(TMP)/darksocv.twr |
BIT = $(TMP)/darksocv.bit |
MAP = $(TMP)/darksocv_map.ncd |
UT = $(ISE)/darksocv.ut |
|
PRJS = $(ISE)/darksocv.prj |
RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v $(RTL)/config.vh |
|
ifdef HARVARD |
BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem |
else |
BOOT = $(SRC)/darksocv.mem |
endif |
|
IMP = $(ISE)/darksocv.imp |
|
default: all |
|
$(NGC): $(PRJS) $(BOOT) $(RTLS) |
cd $(TMP) && xst -intstyle ise -ifn $(XST) -ofn $(SYR) |
|
$(NGD): $(NGC) $(UCF) $(BOOT) $(RTLS) |
cd $(TMP) && ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc $(UCF) -p $(DEVICE) $(NGC) $(NGD) |
|
$(PCF): $(NGD) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && map -intstyle ise -p $(DEVICE) -w -logic_opt on -ol high -t 1 -register_duplication on -r 4 -global_opt off -detail -ir off -ignore_keep_hierarchy -pr off -power off -o $(MAP) $(NGD) $(PCF) |
|
$(NCD): $(PCF) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && par -w -intstyle ise -ol high -mt 2 $(MAP) $(NCD) $(PCF) |
|
$(TWR): $(PCF) $(BOOT) $(UCF) $(RTLS) $(NCD) |
cd $(TMP) && trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml $(TWX) $(NCD) -o $(TWR) $(PCF) |
|
$(BIT): $(UT) $(NCD) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && bitgen -intstyle ise -f $(UT) $(NCD) |
|
all: $(BIT) $(BOOT) $(UCF) $(RTLS) |
|
install: $(BIT) $(BOOT) $(UCF) $(RTLS) |
cd $(TMP) && impact -batch $(IMP) |
|
clean: |
-rm -v $(TMP)/* |
/darkriscv/trunk/boards/digilent_spartan3_s200/darksocv.prj
0,0 → 1,3
verilog work "../rtl/darkriscv.v" |
verilog work "../rtl/darksocv.v" |
verilog work "../rtl/darkuart.v" |
/darkriscv/trunk/boards/digilent_spartan3_s200/darksocv.ucf
0,0 → 1,56
# Copyright (c) 2018, Marcelo Samsoniuk |
# All rights reserved. |
# |
# Redistribution and use in source and binary forms, with or without |
# modification, are permitted provided that the following conditions are met: |
# |
# * Redistributions of source code must retain the above copyright notice, this |
# list of conditions and the following disclaimer. |
# |
# * Redistributions in binary form must reproduce the above copyright notice, |
# this list of conditions and the following disclaimer in the documentation |
# and/or other materials provided with the distribution. |
# |
# * Neither the name of the copyright holder nor the names of its |
# contributors may be used to endorse or promote products derived from |
# this software without specific prior written permission. |
# |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|
#NET "CLK" TNM_NET = CLK; |
|
# without cache controller |
#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; |
|
# with cache controller |
#TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; |
|
# Digilent Spartan3 S200 |
|
NET XCLK LOC = T9 | PERIOD = 50MHz HIGH 50%; |
#NET XCLK LOC = K15 | PERIOD = 66MHz HIGH 50%; |
#NET XCLK LOC = V10 | PERIOD = 40MHz HIGH 50%; |
|
NET XRES LOC = M13 | PULLDOWN; |
|
NET UART_RXD LOC = T13 | PULLUP; |
NET UART_TXD LOC = R13; |
|
NET LED[3] LOC = K12; |
NET LED[2] LOC = P14; |
NET LED[1] LOC = L12; |
NET LED[0] LOC = N14; |
|
NET DEBUG[3] LOC = P13; # J4-1 |
NET DEBUG[2] LOC = N12; # J4-2 |
NET DEBUG[1] LOC = P12; # J4-3 |
NET DEBUG[0] LOC = P11; # J4-4 |
/darkriscv/trunk/boards/digilent_spartan3_s200/darksocv.ut
0,0 → 1,30
-w |
-g DebugBitstream:No |
-g Binary:no |
-g CRC:Enable |
#-g Reset_on_err:No |
#-g ConfigRate:2 |
-g ProgPin:PullUp |
-g TckPin:PullUp |
-g TdiPin:PullUp |
-g TdoPin:PullUp |
-g TmsPin:PullUp |
-g UnusedPin:PullDown |
-g UserID:0xFFFFFFFF |
#-g ExtMasterCclk_en:No |
#-g SPI_buswidth:1 |
#-g TIMER_CFG:0xFFFF |
#-g multipin_wakeup:No |
-g StartUpClk:CClk |
-g DONE_cycle:4 |
-g GTS_cycle:5 |
-g GWE_cycle:6 |
-g LCK_cycle:NoWait |
-g Security:None |
-g DonePipe:Yes |
-g DriveDone:No |
#-g en_sw_gsr:No |
#-g drive_awake:No |
#-g sw_clk:Startupclk |
#-g sw_gwe_cycle:5 |
#-g sw_gts_cycle:4 |
/darkriscv/trunk/boards/digilent_spartan3_s200/darksocv.xise
0,0 → 1,363
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="../../rtl/darkriscv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="../../rtl/darksocv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="../../rtl/darkuart.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="../../sim/darksimv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/> |
</file> |
<file xil_pn:name="darksocv.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
</files> |
|
<properties> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc3s200" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
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<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
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<property xil_pn:name="Implementation Top" xil_pn:value="Module|darksocv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/darksocv.v" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/darksocv" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
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<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
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<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
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<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
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<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="darksocv" xil_pn:valueState="default"/> |
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<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
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<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
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<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="darksocv_timesim.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="darksocv_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="darksocv_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
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<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> |
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/darksimv" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="DIGILENT_SPARTAN3_S200=1" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="../../tmp" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|darksimv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="darkriscv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-08-24T20:01:44" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3E4CA3137C81E741F5DACA4F53F1B6A8" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="OutSideAbove" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings> |
<binding xil_pn:location="/darksocv" xil_pn:name="darksocv.ucf"/> |
</bindings> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
<file xil_pn:name="../../rtl/config.vh" xil_pn:type="FILE_VERILOG"/> |
</autoManagedFiles> |
|
</project> |
/darkriscv/trunk/boards/digilent_spartan3_s200/darksocv.xst
0,0 → 1,57
set -tmpdir "../tmp" |
set -xsthdpdir "../tmp/" |
run |
-ifn ../boards/digilent_spartan3_s200/darksocv.prj |
-ifmt mixed |
-ofn darksocv |
-ofmt NGC |
-p xc3s200-4-ft256 |
-top darksocv |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-keep_hierarchy No |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-verilog2001 YES |
-define { DIGILENT_SPARTAN3_S200=1 } |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract Yes |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-auto_bram_packing NO |
-mux_extract Yes |
-resource_sharing YES |
-async_to_sync NO |
-mult_style Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 8 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Auto |
-use_sync_set Auto |
-use_sync_reset Auto |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
/darkriscv/trunk/boards/lattice_brevia2_xp2/.gitignore
0,0 → 1,34
.project |
.svproject |
syn_results |
archiv |
impl1 |
.recovery |
*_tcr.dir |
.*.ini |
*.asd |
*.asdb |
*.awb |
*.awc |
*.bak |
*.bak.* |
*.ccl |
*.cfg |
*.cmd |
*.cst |
*.htm |
*.html |
*.log |
*.rva |
*.rvs |
*.trc |
*.rvl |
*.ngd |
*.ngo |
*.tcl |
*.svf |
*.vhm |
*.xml |
*.zip |
*.vhd |
*~ |
/darkriscv/trunk/boards/lattice_brevia2_xp2/README.md
0,0 → 1,79
# Lattice XP2 Brevia 2 board |
|
## General information |
The Lattice Brevia 2 board is a small development board for the Lattice XP2 |
family of FPGAs. It has a Lattice LFXP2-5E-6 chip in a QFP 144-pin package and |
also includes the following peripherals: |
* An 1MBit SRAM - IDT71V124SA1 |
* 2MBit SPI flash - SST25VF020 |
* FT2232 for for FPGA programming/debugging and serial-to-USB on the second channel |
* 8 LEDs |
* 4 push-buttons and 4 microswitches |
* a 50MHz oscillator |
* Pin headers for all IOs |
|
The DarkRISCV/darksoc builds out-of-the box using Lattice Diamond command-line, |
taking about ~60% of the on-chip LUTs for the SoC demo. |
|
## Instructions |
Building and running the board has been tested on Linux only. You'll need the |
following software intalled on your system: |
- GNU make; Icarus Verilog; gtkwave if you want to examine the simulation output |
- Lattice Diamond installed and properly licensed. |
|
Once you have the above, edit the top-level Makefile and set |
``` |
BOARD = lattice_brevia2_xp2 |
``` |
While there, also make sure to correctly set the paths to your other tools, eg. |
CROSS, CCPATH, ICARUS |
|
Next check *boards/lattice_brevia2_xp2/darksocv.mk* and make sure that |
DIAMOND_PATH matches your environment. |
|
Finally, execute "make" in the top-level directory. First the Icarus simulation |
is executed and you should be greeted with the familiar logo. After that, the |
Lattice-specific build commences and if everything goes well, after a few pages |
of output, you should see |
``` |
Saving bit stream in "darksocv_impl1.jed". |
Total CPU Time: 3 secs |
Total REAL Time: 3 secs |
Peak Memory Usage: 1010572 MB |
cp lattice_brevia2_xp2/impl1/darksocv_impl1.jed ../tmp/darksocv.bit |
echo build ok. |
build ok. |
``` |
|
Program the board with the output JEDEC file (boards/lattice_brevia2_xp2/impl1/darksocv_impl1.jed) |
file, using either the GUI Lattice Programmer or the command-line prgrcmd utility |
``` |
LD_LIBRARY_PATH="/usr/local/diamond/3.11_x64/bin/lin64/:/usr/local/diamond/3.11_x64/ispfpga/bin/lin64/" |
/usr/local/diamond/3.11_x64/bin/lin64/pgrcmd -infile lattice_brevia2_xp2.xcf |
``` |
|
Connect a terminal emulator to the on-boards FT2232 second channel, for example: |
``` |
cu -l /dev/ttyUSB1 -s 115200 |
``` |
Reset the board and enjoy! |
|
|
|
|
Notes: |
* No effort has been made to optimize resource utilization |
* There are quite a lot of warnings during the build. No effort has been made |
to clear (or even understand) them. There are probably bugs hiding there |
as well. |
* The default 50MHz oscillator is used as the core clock. Using a PLL, the core |
could probably go faster, but this is outside the scope of the current work. |
* There seems to be an issue (race condition of sorts?) with the interaction |
UART/Timer/Threading. The sympthoms are either the simulation outputing '01' |
or nothing at all, the actual board doing the same, the actual board not |
being able to display board information (model, clock speed, etc) or the |
timer not working (i.e. board stalled after 'reboot'). The easiest |
work-around seems to be to remote the two ```putchar('0'+tmp);``` calls |
inside src/boot.c. Again, this is only a work-around and the problem could |
manifest at any point. |
|
/darkriscv/trunk/boards/lattice_brevia2_xp2/build.sh
0,0 → 1,14
#!/bin/sh |
|
# Simple script to invoke diamondc - the Lattice Diamond TCL console |
|
|
DIAMOND_PATH=/usr/local/diamond/3.11_x64 |
|
export TEMP=/tmp |
export LSC_INI_PATH="" |
export LSC_DIAMOND=true |
export TCL_LIBRARY=$DIAMOND_PATH/tcltk/lib/tcl8.5 |
export FOUNDRY=$DIAMOND_PATH/ispFPGA |
export PATH=$FOUNDRY/bin/lin64:"$PATH" |
$DIAMOND_PATH/bin/lin64/diamondc darksocv.tcl 2>&1 | tee darksocv_build.log |
darkriscv/trunk/boards/lattice_brevia2_xp2/build.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.ldf
===================================================================
--- darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.ldf (nonexistent)
+++ darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.ldf (revision 2)
@@ -0,0 +1,21 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.lpf
===================================================================
--- darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.lpf (nonexistent)
+++ darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.lpf (revision 2)
@@ -0,0 +1,27 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "DEBUG[0]" SITE "37" ;
+LOCATE COMP "DEBUG[1]" SITE "38" ;
+LOCATE COMP "DEBUG[2]" SITE "39" ;
+LOCATE COMP "DEBUG[3]" SITE "40" ;
+LOCATE COMP "LED[0]" SITE "43" ;
+LOCATE COMP "LED[1]" SITE "44" ;
+LOCATE COMP "LED[2]" SITE "45" ;
+LOCATE COMP "LED[3]" SITE "46" ;
+IOBUF PORT "DEBUG[0]" IO_TYPE=LVCMOS33 DRIVE=12 ;
+IOBUF PORT "DEBUG[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "DEBUG[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "DEBUG[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "UART_TXD" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "UART_TXD" SITE "109" ;
+LOCATE COMP "UART_RXD" SITE "110" ;
+IOBUF PORT "UART_RXD" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "XRES" SITE "19" ;
+IOBUF PORT "XRES" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "XCLK" SITE "21" ;
+IOBUF PORT "XCLK" IO_TYPE=LVCMOS33 ;
+
Index: darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.mk
===================================================================
--- darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.mk (nonexistent)
+++ darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.mk (revision 2)
@@ -0,0 +1,70 @@
+#
+# Copyright (c) 2020, Ivan Vasilev
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# ===8<--------------------------------------------------------- cut here!
+
+# board LatticeXP2 Brevia 2
+BOARD = lattice_brevia2_xp2
+DEVICE = LFXP2-5E-6TN144C
+DIAMOND_PATH=/usr/local/diamond/3.11_x64
+IMPL = impl1
+TMP = ../tmp
+
+
+# Expected by Lattice Diamond
+export TEMP=../tmp
+export LSC_INI_PATH=""
+export LSC_DIAMOND=true
+export TCL_LIBRARY=$(DIAMOND_PATH)/tcltk/lib/tcl8.5
+export FOUNDRY=$(DIAMOND_PATH)/ispFPGA
+export PATH:=$(FOUNDRY)/bin/lin64:${PATH}
+
+
+RTL = ../rtl
+SRC = ../src
+BIT = $(TMP)/darksocv.bit
+
+RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v $(RTL)/config.vh
+
+ifdef HARVARD
+ BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem
+else
+ BOOT = $(SRC)/darksocv.mem
+endif
+
+default: build
+
+$(BIT): $(BOOT) $(RTLS)
+ echo PATH: $$PATH
+ cd $(BOARD) && $(DIAMOND_PATH)/bin/lin64/diamondc darksocv.tcl 2>&1 | tee darksocv_build.log
+ cp $(BOARD)/$(IMPL)/darksocv_impl1.jed $(BIT)
+
+clean:
+ -rm -v $(TMP)/*
+ rm -rf $(BOARD)/$(IMPL)
Index: darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.tcl
===================================================================
--- darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.tcl (nonexistent)
+++ darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv.tcl (revision 2)
@@ -0,0 +1,8 @@
+prj_project open "darksocv.ldf"
+prj_run Synthesis -impl impl1
+prj_run Translate -impl impl1
+prj_run Map -impl impl1
+prj_run PAR -impl impl1
+prj_run PAR -impl impl1 -task PARTrace
+prj_run Export -impl impl1 -task Bitgen
+prj_project close
Index: darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv1.sty
===================================================================
--- darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv1.sty (nonexistent)
+++ darkriscv/trunk/boards/lattice_brevia2_xp2/darksocv1.sty (revision 2)
@@ -0,0 +1,204 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
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+
+
+
+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
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+
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+
+
+
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+
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+
+
+
+
+
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+
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+
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+
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+
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+
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+
+
+
+
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+
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+
+
Index: darkriscv/trunk/boards/lattice_brevia2_xp2/lattice_brevia2_xp2.xcf
===================================================================
--- darkriscv/trunk/boards/lattice_brevia2_xp2/lattice_brevia2_xp2.xcf (nonexistent)
+++ darkriscv/trunk/boards/lattice_brevia2_xp2/lattice_brevia2_xp2.xcf (revision 2)
@@ -0,0 +1,55 @@
+
+
+
+
+
+ JTAG
+
+
+ 1
+ Lattice
+ LatticeXP2
+ LFXP2-5E
+ 0x01299043
+ All
+ LFXP2-5E
+
+ 8
+ 11111111
+ 1
+ 0
+
+ ./impl1/darksocv_impl1.jed
+ 05/12/20 14:57:02
+ 0x7A90
+ FLASH Erase,Program,Verify
+
+
+
+
+ SEQUENTIAL
+ ENTIRED CHAIN
+ No Override
+ TLR
+ TLR
+
+ 1
+
+
+ USB2
+ FTUSB-0
+ LATTICE FTUSB INTERFACE CABLE A Location 0000 Serial LATTICE FTUSB INTERFACE CABLE A
+
+ TRST ABSENT;
+ ISPEN ABSENT;
+
+
+
Index: darkriscv/trunk/boards/piswords_rs485_lx9/README.md
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/README.md (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/README.md (revision 2)
@@ -0,0 +1,21 @@
+## PISWORDS RS485 LX9
+
+The Piswords RS485 LX9* is a very interesting chinese board that
+include lots of interesting features:
+
+- a XC6SLX9 FPGA w/ 144 pins (TQFP!)
+- 50MHz clock
+- RS232 serial
+- RS485 serial (of course)
+- 16MB SPI FLASH
+- eigth LEDs
+- four keys
+- lots of GPIO pins
+- 128-byte I2C EEPROM (I guess)
+
+As observed, the main board focus in around RS485 applications, where is
+possible connect multiple boards in the same network and control lots of
+IOs.
+
+*note: the boad in fact is named "core board" or "demo board", but for some
+unknown reason we know this board as "rs485 board" here.
Index: darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.imp
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.imp (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.imp (revision 2)
@@ -0,0 +1,7 @@
+setMode -bs
+setCable -port auto
+Identify -inferir
+identifyMPM
+assignFile -p 1 -file "../tmp/darksocv.bit"
+Program -p 1
+quit
Index: darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.mk
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.mk (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.mk (revision 2)
@@ -0,0 +1,100 @@
+#
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# ===8<--------------------------------------------------------- cut here!
+#
+# The general concept is based in the article:
+#
+# https://www.fpgarelated.com/showarticle/786.php
+#
+# However, since the ISE GUI itself creates a "darksocv.cmd_log" file with
+# all commands executed and the respective options, it is possible change
+# some options in the ISE and check the file in order to understand how
+# enable/disable the different options.
+#
+
+# board Piswords RS485 LX9
+BOARD = piswords_rs485_lx9
+DEVICE = xc6slx9-tqg144-2
+
+ISE = ../boards/$(BOARD)
+RTL = ../rtl
+SRC = ../src
+TMP = ../tmp
+
+XST = $(ISE)/darksocv.xst
+SYR = $(TMP)/darksocv.syr
+UCF = $(ISE)/darksocv.ucf
+IMP = $(ISE)/darksocv.imp
+NGC = $(TMP)/darksocv.ngc
+NGD = $(TMP)/darksocv.ngd
+PCF = $(TMP)/darksocv.pcf
+NCD = $(TMP)/darksocv.ncd
+TWX = $(TMP)/darksocv.twx
+TWR = $(TMP)/darksocv.twr
+BIT = $(TMP)/darksocv.bit
+MAP = $(TMP)/darksocv_map.ncd
+UT = $(ISE)/darksocv.ut
+
+PRJS = $(ISE)/darksocv.prj
+RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v $(RTL)/config.vh
+
+ifdef HARVARD
+ BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem
+else
+ BOOT = $(SRC)/darksocv.mem
+endif
+
+IMP = $(ISE)/darksocv.imp
+
+default: all
+
+$(NGC): $(PRJS) $(BOOT) $(RTLS)
+ cd $(TMP) && xst -intstyle ise -ifn $(XST) -ofn $(SYR)
+
+$(NGD): $(NGC) $(UCF) $(BOOT) $(RTLS)
+ cd $(TMP) && ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc $(UCF) -p $(DEVICE) $(NGC) $(NGD)
+
+$(PCF): $(NGD) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && map -intstyle ise -p $(DEVICE) -w -logic_opt on -ol high -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -detail -ir off -ignore_keep_hierarchy -pr off -lc auto -power off -o $(MAP) $(NGD) $(PCF)
+
+$(NCD): $(PCF) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && par -w -intstyle ise -ol high -mt 2 $(MAP) $(NCD) $(PCF)
+ cd $(TMP) && trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml $(TWX) $(NCD) -o $(TWR) $(PCF)
+
+$(BIT): $(UT) $(NCD) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && bitgen -intstyle ise -f $(UT) $(NCD)
+
+all: $(BIT) $(BOOT) $(UCF) $(RTLS)
+
+install: $(BIT) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && impact -batch $(IMP)
+
+clean:
+ -rm -v $(TMP)/*
Index: darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.prj
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.prj (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.prj (revision 2)
@@ -0,0 +1,3 @@
+verilog work "../rtl/darkriscv.v"
+verilog work "../rtl/darksocv.v"
+verilog work "../rtl/darkuart.v"
Index: darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.ucf
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.ucf (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.ucf (revision 2)
@@ -0,0 +1,45 @@
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# Piswords RS485 LX9
+
+NET XCLK LOC = P55 | PERIOD = 50MHz HIGH 50%;
+NET XRES LOC = P44 | PULLDOWN;
+
+NET UART_RXD LOC = P47;
+NET UART_TXD LOC = P48;
+
+NET LED[3] LOC = P61; # LED8
+NET LED[2] LOC = P62; # LED7
+NET LED[1] LOC = P66; # LED6
+NET LED[0] LOC = P67; # LED5
+
+NET DEBUG[3] LOC = P112; # P2-39
+NET DEBUG[2] LOC = P115; # P2-37
+NET DEBUG[1] LOC = P117; # P2-35
+NET DEBUG[0] LOC = P119; # P2-33
Index: darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.ut
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.ut (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.ut (revision 2)
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+#-g Reset_on_err:No
+#-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
Index: darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.xise
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.xise (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.xise (revision 2)
@@ -0,0 +1,382 @@
+
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Index: darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.xst
===================================================================
--- darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.xst (nonexistent)
+++ darkriscv/trunk/boards/piswords_rs485_lx9/darksocv.xst (revision 2)
@@ -0,0 +1,53 @@
+set -tmpdir "../tmp"
+set -xsthdpdir "../tmp/"
+run
+-ifn ../boards/piswords_rs485_lx9/darksocv.prj
+-ofn darksocv
+-ofmt NGC
+-p xc6slx9-2-tqg144
+-top darksocv
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+-define PISWORDS_RS485_LX9=1
\ No newline at end of file
Index: darkriscv/trunk/boards/qmtech_artix7_a35/darksocv.xdc
===================================================================
--- darkriscv/trunk/boards/qmtech_artix7_a35/darksocv.xdc (nonexistent)
+++ darkriscv/trunk/boards/qmtech_artix7_a35/darksocv.xdc (revision 2)
@@ -0,0 +1,22 @@
+# QMTech Spartan-7 board
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+set_property -dict { PACKAGE_PIN N11 IOSTANDARD LVCMOS33 } [get_ports { XCLK }];
+create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports { XCLK }];
+
+set_property -dict { PACKAGE_PIN K5 IOSTANDARD LVCMOS33 } [get_ports { XRES }];
+
+set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD }];
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }];
+
+set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }];
+set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }];
+set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }];
+set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }];
+
+set_property -dict { PACKAGE_PIN N4 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[3] }];
+set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[2] }];
+set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[1] }];
+set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[0] }];
Index: darkriscv/trunk/boards/qmtech_artix7_a35/darksocv.xpr
===================================================================
--- darkriscv/trunk/boards/qmtech_artix7_a35/darksocv.xpr (nonexistent)
+++ darkriscv/trunk/boards/qmtech_artix7_a35/darksocv.xpr (revision 2)
@@ -0,0 +1,206 @@
+
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+ Vivado Synthesis Defaults
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+ Default settings for Implementation.
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Index: darkriscv/trunk/boards/qmtech_sdram_lx16/README.md
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/README.md (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/README.md (revision 2)
@@ -0,0 +1,32 @@
+## QMTech SDRAM LX16
+
+Although the QMTech SDRAM LX16 lacks on-board JTAG and USB/serial, it is a
+very cheap and interesting board. In fact, is so cheap that is possible buy
+lots of boards and connect them via high-speed links! :)
+
+With an external Xilinx JTAG cable and an external USB/serial converter, the
+board works very well and provides lots of IO pins.
+
+The board includes:
+
+- a XC6SLX16 FPGA w/ 256 pins
+- 50MHz clock
+- on-board SPI FLASH
+- on-board SDRAM (classical MT48LC16M16A2
+- two LEDs
+- lots and lots of GPIO pins
+
+As long the QMTech SDRAM LX16 is compatible with the QMTech development kit
+based in the Artix-7, I managed to adapt the board and use the same
+peripherals:
+
+- USB/serial
+- GMII PHY
+- VGA interface
+- more LEDs
+- more switchs
+- more GPIOs
+
+Currently, only the USB/serial adapter is supported.
+
+
Index: darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.imp
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.imp (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.imp (revision 2)
@@ -0,0 +1,7 @@
+setMode -bs
+setCable -port auto
+Identify -inferir
+identifyMPM
+assignFile -p 1 -file "../tmp/darksocv.bit"
+Program -p 1
+quit
Index: darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.mk
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.mk (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.mk (revision 2)
@@ -0,0 +1,108 @@
+#
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# ===8<--------------------------------------------------------- cut here!
+#
+# The general concept is based in the article:
+#
+# https://www.fpgarelated.com/showarticle/786.php
+#
+# However, since the ISE GUI itself creates a "darksocv.cmd_log" file with
+# all commands executed and the respective options, it is possible change
+# some options in the ISE and check the file in order to understand how
+# enable/disable the different options.
+#
+
+# board Avnet Microboard LX9
+#BOARD = avnet_microboard_lx9
+#DEVICE = xc6slx9-csg324-2
+
+# board Xilinx AC701 A200
+#BOARD = xilinx_ac701_a200
+#DEVICE = xc7a200t-fbg676-2
+
+# board QMTech SDRAM LX16
+BOARD = qmtech_sdram_lx16
+DEVICE = xc6slx16-ftg256-2
+
+ISE = ../boards/$(BOARD)
+RTL = ../rtl
+SRC = ../src
+TMP = ../tmp
+
+XST = $(ISE)/darksocv.xst
+SYR = $(TMP)/darksocv.syr
+UCF = $(ISE)/darksocv.ucf
+IMP = $(ISE)/darksocv.imp
+NGC = $(TMP)/darksocv.ngc
+NGD = $(TMP)/darksocv.ngd
+PCF = $(TMP)/darksocv.pcf
+NCD = $(TMP)/darksocv.ncd
+TWX = $(TMP)/darksocv.twx
+TWR = $(TMP)/darksocv.twr
+BIT = $(TMP)/darksocv.bit
+MAP = $(TMP)/darksocv_map.ncd
+UT = $(ISE)/darksocv.ut
+
+PRJS = $(ISE)/darksocv.prj
+RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v
+
+ifdef HARVARD
+ BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem
+else
+ BOOT = $(SRC)/darksocv.mem
+endif
+
+IMP = $(ISE)/darksocv.imp
+
+default: all
+
+$(NGC): $(PRJS) $(BOOT) $(RTLS)
+ cd $(TMP) && xst -intstyle ise -ifn $(XST) -ofn $(SYR)
+
+$(NGD): $(NGC) $(UCF) $(BOOT) $(RTLS)
+ cd $(TMP) && ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc $(UCF) -p $(DEVICE) $(NGC) $(NGD)
+
+$(PCF): $(NGD) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && map -intstyle ise -p $(DEVICE) -w -logic_opt on -ol high -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -detail -ir off -ignore_keep_hierarchy -pr off -lc auto -power off -o $(MAP) $(NGD) $(PCF)
+
+$(NCD): $(PCF) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && par -w -intstyle ise -ol high -mt 2 $(MAP) $(NCD) $(PCF)
+ cd $(TMP) && trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml $(TWX) $(NCD) -o $(TWR) $(PCF)
+
+$(BIT): $(UT) $(NCD) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && bitgen -intstyle ise -f $(UT) $(NCD)
+
+all: $(BIT) $(BOOT) $(UCF) $(RTLS)
+
+install: $(BIT) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && impact -batch $(IMP)
+
+clean:
+ -rm -v $(TMP)/*
Index: darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.prj
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.prj (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.prj (revision 2)
@@ -0,0 +1,3 @@
+verilog work "../rtl/darkriscv.v"
+verilog work "../rtl/darksocv.v"
+verilog work "../rtl/darkuart.v"
Index: darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.ucf
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.ucf (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.ucf (revision 2)
@@ -0,0 +1,47 @@
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# QMtech SDRAM/LX16 board
+
+NET XCLK LOC = A10 | PERIOD = 50MHz HIGH 50%;
+NET XRES LOC = T8 | PULLUP;
+
+NET LED[3] LOC = B12;
+NET LED[2] LOC = C11;
+NET LED[1] LOC = T9; # board led
+NET LED[0] LOC = R9; # board led
+
+# QMtech expansion board -> connector -> SDRAM/LX16 board
+
+NET UART_RXD LOC = E16; # F22 -> J2-15 -> E15
+NET UART_TXD LOC = E15; # G22 -> J2-16 -> E16
+
+NET DEBUG[3] LOC = L14; # P23 -> J2-40 -> L14
+NET DEBUG[2] LOC = L16; # P24 -> J2-39 -> L16
+NET DEBUG[1] LOC = K16; # N21 -> J2-38 -> K16
+NET DEBUG[0] LOC = K15; # N22 -> J2-37 -> K15
Index: darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.ut
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.ut (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.ut (revision 2)
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+#-g Reset_on_err:No
+#-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
Index: darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.xise
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.xise (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.xise (revision 2)
@@ -0,0 +1,381 @@
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Index: darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.xst
===================================================================
--- darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.xst (nonexistent)
+++ darkriscv/trunk/boards/qmtech_sdram_lx16/darksocv.xst (revision 2)
@@ -0,0 +1,53 @@
+set -tmpdir "../tmp"
+set -xsthdpdir "../tmp/"
+run
+-ifn ../boards/qmtech_sdram_lx16/darksocv.prj
+-ofn darksocv
+-ofmt NGC
+-p xc6slx16-2-ftg256
+-top darksocv
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+-define QMTECH_SDRAM_LX16=1
\ No newline at end of file
Index: darkriscv/trunk/boards/qmtech_spartan7_s15/darksocv.xdc
===================================================================
--- darkriscv/trunk/boards/qmtech_spartan7_s15/darksocv.xdc (nonexistent)
+++ darkriscv/trunk/boards/qmtech_spartan7_s15/darksocv.xdc (revision 2)
@@ -0,0 +1,22 @@
+# QMTech Spartan-7 board
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS33 } [get_ports { XCLK }];
+create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports { XCLK }];
+
+set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { XRES }];
+
+set_property -dict { PACKAGE_PIN N4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD }];
+set_property -dict { PACKAGE_PIN P5 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }];
+
+set_property -dict { PACKAGE_PIN E4 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }];
+set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }];
+set_property -dict { PACKAGE_PIN L5 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }];
+set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }];
+
+set_property -dict { PACKAGE_PIN B5 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[3] }];
+set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[2] }];
+set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[1] }];
+set_property -dict { PACKAGE_PIN A2 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[0] }];
Index: darkriscv/trunk/boards/qmtech_spartan7_s15/darksocv.xpr
===================================================================
--- darkriscv/trunk/boards/qmtech_spartan7_s15/darksocv.xpr (nonexistent)
+++ darkriscv/trunk/boards/qmtech_spartan7_s15/darksocv.xpr (revision 2)
@@ -0,0 +1,198 @@
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Index: darkriscv/trunk/boards/xilinx_ac701_a200/README.md
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/README.md (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/README.md (revision 2)
@@ -0,0 +1,18 @@
+## Xilinx AC701 A200
+
+The AC701 from Xilinx is a very complete and expensive board based in the
+Artix-7 A200. Unfortunately, the board was not mine and I borrowed from a
+friend for a short time only in order to make a quick test, in a way that
+the DarkRISCV worked at 90MHz in the board. Later, after the board was
+already returned, I made a better clock scheme in order to generate 180MHz
+and the image was built w/ a timing score zero, which means that the build
+is probably working, althrough there is no way to test it at this moment.
+
+The board includes:
+
+- a XC7A200 FPGA w/ 676 pins
+- lots of clock references, but I found only the 90MHz clock
+- on-board SPI FLASH
+- on-board DDR3
+- on-board 1Gbps PHY
+- lots and lots of other features!
Index: darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.imp
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.imp (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.imp (revision 2)
@@ -0,0 +1,7 @@
+setMode -bs
+setCable -port auto
+Identify -inferir
+identifyMPM
+assignFile -p 1 -file "../tmp/darksocv.bit"
+Program -p 1
+quit
Index: darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.mk
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.mk (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.mk (revision 2)
@@ -0,0 +1,108 @@
+#
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# ===8<--------------------------------------------------------- cut here!
+#
+# The general concept is based in the article:
+#
+# https://www.fpgarelated.com/showarticle/786.php
+#
+# However, since the ISE GUI itself creates a "darksocv.cmd_log" file with
+# all commands executed and the respective options, it is possible change
+# some options in the ISE and check the file in order to understand how
+# enable/disable the different options.
+#
+
+# board Avnet Microboard LX9
+#BOARD = avnet_microboard_lx9
+#DEVICE = xc6slx9-csg324-2
+
+# board Xilinx AC701 A200
+BOARD = xilinx_ac701_a200
+DEVICE = xc7a200t-fbg676-2
+
+# board QMTech SDRAM LX16
+#BOARD = qmtech_sdram_lx16
+#DEVICE = xc6slx16-ftg256-2
+
+ISE = ../boards/$(BOARD)
+RTL = ../rtl
+SRC = ../src
+TMP = ../tmp
+
+XST = $(ISE)/darksocv.xst
+SYR = $(TMP)/darksocv.syr
+UCF = $(ISE)/darksocv.ucf
+IMP = $(ISE)/darksocv.imp
+NGC = $(TMP)/darksocv.ngc
+NGD = $(TMP)/darksocv.ngd
+PCF = $(TMP)/darksocv.pcf
+NCD = $(TMP)/darksocv.ncd
+TWX = $(TMP)/darksocv.twx
+TWR = $(TMP)/darksocv.twr
+BIT = $(TMP)/darksocv.bit
+MAP = $(TMP)/darksocv_map.ncd
+UT = $(ISE)/darksocv.ut
+
+PRJS = $(ISE)/darksocv.prj
+RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v
+
+ifdef HARVARD
+ BOOT = $(SRC)/darksocv.rom $(SRC)/darksocv.ram.mem
+else
+ BOOT = $(SRC)/darksocv.mem.mem
+endif
+
+IMP = $(ISE)/darksocv.imp
+
+default: all
+
+$(NGC): $(PRJS) $(BOOT) $(RTLS)
+ cd $(TMP) && xst -intstyle ise -ifn $(XST) -ofn $(SYR)
+
+$(NGD): $(NGC) $(UCF) $(BOOT) $(RTLS)
+ cd $(TMP) && ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc $(UCF) -p $(DEVICE) $(NGC) $(NGD)
+
+$(PCF): $(NGD) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && map -intstyle ise -p $(DEVICE) -w -logic_opt on -ol high -t 1 -xt 0 -register_duplication on -r 4 -global_opt off -mt 2 -detail -ir off -ignore_keep_hierarchy -pr off -lc auto -power off -o $(MAP) $(NGD) $(PCF)
+
+$(NCD): $(PCF) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && par -w -intstyle ise -ol high -mt 2 $(MAP) $(NCD) $(PCF)
+ cd $(TMP) && trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml $(TWX) $(NCD) -o $(TWR) $(PCF)
+
+$(BIT): $(UT) $(NCD) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && bitgen -intstyle ise -f $(UT) $(NCD)
+
+all: $(BIT) $(BOOT) $(UCF) $(RTLS)
+
+install: $(BIT) $(BOOT) $(UCF) $(RTLS)
+ cd $(TMP) && impact -batch $(IMP)
+
+clean:
+ -rm -v $(TMP)/*
Index: darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.prj
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.prj (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.prj (revision 2)
@@ -0,0 +1,3 @@
+verilog work "../rtl/darkriscv.v"
+verilog work "../rtl/darksocv.v"
+verilog work "../rtl/darkuart.v"
Index: darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.ucf
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.ucf (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.ucf (revision 2)
@@ -0,0 +1,48 @@
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+NET XCLK LOC = P16 | IOSTANDARD = LVCMOS33 | PERIOD = 90MHz HIGH 50%;
+NET XCLK CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET XCLKP LOC = M21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | PERIOD = 156.25MHz HIGH 50%;
+#NET XCLKN LOC = M22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | PERIOD = 156.25MHz HIGH 50%;
+
+NET XRES LOC = U4 | IOSTANDARD = SSTL15 | PULLDOWN;
+
+NET UART_RXD LOC = T19 | IOSTANDARD = LVCMOS18;
+NET UART_TXD LOC = U19 | IOSTANDARD = LVCMOS18;
+
+NET LED[3] LOC = R26 | IOSTANDARD = LVCMOS33;
+NET LED[2] LOC = T25 | IOSTANDARD = LVCMOS33;
+NET LED[1] LOC = T24 | IOSTANDARD = LVCMOS33;
+NET LED[0] LOC = M26 | IOSTANDARD = LVCMOS33;
+
+NET DEBUG[3] LOC = T23 | IOSTANDARD = LVCMOS33; # J48-1
+NET DEBUG[2] LOC = R22 | IOSTANDARD = LVCMOS33; # J48-2
+NET DEBUG[1] LOC = T22 | IOSTANDARD = LVCMOS33; # J48-3
+NET DEBUG[0] LOC = P26 | IOSTANDARD = LVCMOS33; # J48-4
Index: darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.ut
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.ut (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.ut (revision 2)
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+#-g Reset_on_err:No
+#-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+#-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+#-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+#-g en_sw_gsr:No
+#-g drive_awake:No
+#-g sw_clk:Startupclk
+#-g sw_gwe_cycle:5
+#-g sw_gts_cycle:4
Index: darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.xise
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.xise (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.xise (revision 2)
@@ -0,0 +1,379 @@
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Index: darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.xst
===================================================================
--- darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.xst (nonexistent)
+++ darkriscv/trunk/boards/xilinx_ac701_a200/darksocv.xst (revision 2)
@@ -0,0 +1,53 @@
+set -tmpdir "../tmp"
+set -xsthdpdir "../tmp/"
+run
+-ifn ../boards/xilinx_ac701_a200/darksocv.prj
+-ofn darksocv
+-ofmt NGC
+-p xc7a200t-2-fbg676
+-top darksocv
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+-define XILINX_AC701_A200=1
Index: darkriscv/trunk/boards/Makefile
===================================================================
--- darkriscv/trunk/boards/Makefile (nonexistent)
+++ darkriscv/trunk/boards/Makefile (revision 2)
@@ -0,0 +1,43 @@
+#
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+ifndef BOARD
+ BOARD = avnet_microboard_lx9
+ #BOARD = xilinx_ac701_a200
+ #BOARD = qmtech_sdram_lx16
+ #BOARD = lattice_brevia2_xp2
+endif
+
+include $(BOARD)/darksocv.mk
+
+default: all
+
+all: ../tmp/darksocv.bit
+ echo build ok.
Index: darkriscv/trunk/boards/README.md
===================================================================
--- darkriscv/trunk/boards/README.md (nonexistent)
+++ darkriscv/trunk/boards/README.md (revision 2)
@@ -0,0 +1,38 @@
+## Add your board here! o/
+
+Use the AVNET Microboard LX9 as template, since is the best tested board at this
+moment, as long I can plug it in the computer and test it in less than five
+minutes:
+
+ cp -rp avnet_micrboard_lx9 vendor_board_fpga
+
+In the case of Vivado, the easy way is use the QMTech Spartan-7 board as
+template. In the case of Vivado, there is no automation as found in the
+other FPGAs.
+
+Current supported board/FPGAs:
+
+ avnet_microboard_lx9
+ qmtech_sdram_lx16
+ qmtech spartan7 s15
+ xilinx_ac701_a200
+ lattice brevia2 lxp2
+ piswords rs485 lx9
+
+I am working in a way to make the directory structure better, but it is not
+so easy make everything work at the same time! :)
+
+Proposed structure:
+
+ boards/vendor_boardname_fpga/ top level directory
+ boards/vendor_boardname_fpga/darksocv.mk top level makefile
+ boards/vendor_boardname_fpga/darksocv.* other files (board/fpga specific)
+
+In the current directory is possible set:
+
+ make BOARD=avnet_microboard_lx9 all # build fpga for $BOARD
+ make install # program fpga
+
+Of course, the FPGA programming via JTAG depends of some configurations
+which are different in different environments. Please check the README file
+regarding the board!
Index: darkriscv/trunk/rtl/README.md
===================================================================
--- darkriscv/trunk/rtl/README.md (nonexistent)
+++ darkriscv/trunk/rtl/README.md (revision 2)
@@ -0,0 +1,15 @@
+## Verilog Sources
+
+Description of current Verilog files:
+
+- darkriscv.v: the DarkRISCV core
+- darksocv.v: a primitive system on-chip w/ the DarkRISCV core wired to ROM and RAM memories and IO
+- darkuart.v: a small full-duplex UART w/ programmable baud-rate
+- config.vh: configuration file!
+
+TODO:
+
+- add a cache controller
+- add a SDRAM controller
+- add a SPI controller
+- add a GbE controller
Index: darkriscv/trunk/rtl/config.vh
===================================================================
--- darkriscv/trunk/rtl/config.vh (nonexistent)
+++ darkriscv/trunk/rtl/config.vh (revision 2)
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+`timescale 1ns / 1ps
+
+// memory architecture
+//
+// TODO: fix the different memory architecture concepts:
+// status:
+// ICACHE: works without interrupt
+// DCACHE: does not work!
+// WAITSTATE: works
+//
+//`define __ICACHE__ // instruction cache
+//`define __DCACHE__ // data cache (bug: simulation only)
+//`define __WAITSTATES__ // wait-state tests, no cache
+
+// peripheral configuration
+//
+// UART speed is set in bits per second, typically 115200 bps:
+
+`define __UARTSPEED__ 115200
+
+// darkriscv/darksocv configuration
+//
+// pipeline stages:
+//
+// 2-stage version: core and memory in different clock edges result in less
+// clock performance, but less losses when the program counter changes
+// (pipeline flush = 1 clock). Works like a 4-stage pipeline and remember
+// the 68040 clock scheme, with instruction per clock = 1. alternatively,
+// it is possible work w/ 1 wait-state and 1 clock edge, but with a penalty
+// in performance (instruction per clock = 0.5).
+//
+// 3-stage version: core and memory in the same clock edge require one extra
+// stage in the pipeline, but keep a good performance most of time
+// (instruction per clock = 1). of course, read operations require 1
+// wait-state, which means sometimes the read performance is reduced.
+
+`define __3STAGE__
+
+// muti-threading support:
+//
+// Decreases clock performance by 10% (90MHz), but enables two contexts
+// (threads) in the core. They start in the same code, but the "interrupt"
+// handling is locked in a separate loop and the conext switch is always
+// delayed until the next pipeline flush, in order to decrease the
+// performance impact. Note: threading is currently supported only in the
+// 3-stage pipeline version.
+
+//`define __THREADING__
+
+// performance measurement:
+//
+// The performance measurement can be done in the simulation level by
+// eabling the __PERFMETER__ define, in order to check how the clock cycles
+// are used in the core. The value defines how many clocks are computed
+// before print the result.
+
+//`define __PERFMETER__ 70000
+
+// mac instruction:
+//
+// The mac instruction is similar to other register to register
+// instructions, but with a different opcode 7'h1111111. the format is mac
+// rd,r1,r2, but is not currently possible encode in asm, by this way it is
+// available in licb as int mac(int rd, short r1, short r2). Although it
+// can be used to accelerate the mul/div operations, the mac operation is
+// designed for DSP applications. with some effort (low level machine
+// code), it is possible peak 100MMAC/s @100MHz.
+
+//`define __MAC16X16__
+
+// RV32I vs RV32E:
+//
+// The difference between the RV32I and RV32E regarding the logic space is
+// minimal in typical applications with modern 5 or 6 input LUT based FPGAs,
+// but the RV32E is better with old 4 input LUT based FPGAs.
+
+`define __RV32E__
+
+// initial PC and SP
+//
+// it is possible program the initial PC and SP. Typically, the PC is set
+// to address 0, representing the start of ROM memory and the SP is set to
+// the final of RAM memory. In the linker, the start of ROM memory matches
+// with the .text area, which is defined in the boot.c code and the start of
+// RAM memory matches with the .data and other volatile data, in a way that
+// the stack can be positioned in the top of RAM and does not match with the
+// .data.
+
+`define __HARVARD__
+
+// full harvard architecture:
+//
+// When defined, enforses that the instruction and data buses are connected
+// to fully separate memory banks. Although the darkriscv always use
+// harvard architecture in the core, with separate instruction and data
+// buses, the logic levels outside the core can use different architectures
+// and concepts, including von neumann, wich a single bus shared by
+// instruction and data access, as well a mix between harvard and von
+// neumann, which is possible in the case of dual-port blockrams, where is
+// possible connect two separate buses in a single memory bank. the main
+// advantage of a single memory bank is that the .text and .data areas can
+// be better allocated, but in this case is not possible protect the .text
+// area as in the case of separate memory banks.
+
+`define __FLEXBUZZ__
+
+// flexbuzz interface (experimental):
+//
+// A new data bus interface similar to a well known c*ldfire bus interface, in
+// a way that part of the bus routing is moved to the core, in a way that
+// is possible support different bus widths (8, 16 or 32 bit) and endians more
+// easily (the new interface is natively big-endian, but the endian can be adjusted
+// in the bus interface dinamically). Similarly to the standard 32-bit interface,
+// the external logic must detect the RD/WR operation quick enough and assert HLT
+// in order to insert wait-states and perform the required multiplexing to fit
+// the DLEN operand size in the data bus width available.
+
+`define __RESETPC__ 32'd0
+`define __RESETSP__ 32'd8192
+
+// board definition:
+//
+// The board is automatically defined in the xst/xise files via Makefile or
+// ISE. Case it is not the case, please define you board name here:
+
+//`define AVNET_MICROBOARD_LX9
+//`define XILINX_AC701_A200
+//`define QMTECH_SDRAM_LX16
+
+// the following defines are automatically defined:
+
+`ifdef __ICARUS__
+ `define SIMULATION 1
+`endif
+
+`ifdef XILINX_ISIM
+ `define SIMULATION 2
+`endif
+
+`ifdef MODEL_TECH
+ `define SIMULATION 3
+`endif
+
+`ifdef XILINX_SIMULATOR
+ `define SIMULATION 4
+`endif
+
+`ifdef AVNET_MICROBOARD_LX9
+ `define BOARD_ID 1
+ //`define BOARD_CK 100000000
+ //`define BOARD_CK 66666666
+ //`define BOARD_CK 40000000
+ // example of DCM logic:
+ `define BOARD_CK_REF 100000000
+ `define BOARD_CK_MUL 2
+ `ifdef __3STAGE__
+ `define BOARD_CK_DIV 2 // 100MHz
+ `else
+ `define BOARD_CK_DIV 4 // 50MHz
+ `endif
+`endif
+
+`ifdef XILINX_AC701_A200
+ `define BOARD_ID 2
+ //`define BOARD_CK 90000000
+ `define BOARD_CK_REF 90000000
+ `define BOARD_CK_MUL 4
+ `define BOARD_CK_DIV 2
+`endif
+
+`ifdef QMTECH_SDRAM_LX16
+ `define BOARD_ID 3
+ `define BOARD_CK_REF 50000000
+ `define BOARD_CK_MUL 4
+ `define BOARD_CK_DIV 2
+ `define INVRES 1
+`endif
+
+`ifdef QMTECH_SPARTAN7_S15
+ `define BOARD_ID 4
+ `define BOARD_CK_REF 50000000
+ `define BOARD_CK_MUL 20
+ `define BOARD_CK_DIV 10
+ `define XILINX7CLK 1
+ `define VIVADO 1
+ `define INVRES 1
+`endif
+
+`ifdef LATTICE_BREVIA2_XP2
+ `define BOARD_ID 5
+ `define BOARD_CK 50000000
+ `define INVRES 1
+`endif
+
+`ifdef PISWORDS_RS485_LX9
+ `define BOARD_ID 6
+ `define BOARD_CK_REF 50000000
+ `define BOARD_CK_MUL 4
+ `define BOARD_CK_DIV 2
+ `define INVRES 1
+`endif
+
+`ifdef DIGILENT_SPARTAN3_S200
+ `define BOARD_ID 7
+ `define BOARD_CK 50000000
+`endif
+
+`ifdef ALIEXPRESS_HPC40GBE_K420
+ `define BOARD_ID 8
+ //`define BOARD_CK 200000000
+ `define BOARD_CK_REF 100000000
+ `define BOARD_CK_MUL 11
+ `define BOARD_CK_DIV 5
+ `define XILINX7CLK 1
+ `define INVRES 1
+`endif
+
+`ifdef QMTECH_ARTIX7_A35
+ `define BOARD_ID 9
+ `define BOARD_CK_REF 50000000
+ `define BOARD_CK_MUL 20
+ `define BOARD_CK_DIV 10
+ `define XILINX7CLK 1
+ `define VIVADO 1
+ `define INVRES 1
+`endif
+
+`ifndef BOARD_ID
+ `define BOARD_ID 0
+ `define BOARD_CK 100000000
+`endif
+
+`ifdef BOARD_CK_REF
+ `define BOARD_CK (`BOARD_CK_REF * `BOARD_CK_MUL / `BOARD_CK_DIV)
+`endif
+
+// darkuart baudrate automtically calculated according to board clock:
+
+`ifndef __UARTSPEED__
+ `define __UARTSPEED__ 115200
+`endif
+
+`define __BAUD__ ((`BOARD_CK/`__UARTSPEED__))
Index: darkriscv/trunk/rtl/darkriscv.v
===================================================================
--- darkriscv/trunk/rtl/darkriscv.v (nonexistent)
+++ darkriscv/trunk/rtl/darkriscv.v (revision 2)
@@ -0,0 +1,495 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+`timescale 1ns / 1ps
+
+// implemented opcodes:
+
+`define LUI 7'b01101_11 // lui rd,imm[31:12]
+`define AUIPC 7'b00101_11 // auipc rd,imm[31:12]
+`define JAL 7'b11011_11 // jal rd,imm[xxxxx]
+`define JALR 7'b11001_11 // jalr rd,rs1,imm[11:0]
+`define BCC 7'b11000_11 // bcc rs1,rs2,imm[12:1]
+`define LCC 7'b00000_11 // lxx rd,rs1,imm[11:0]
+`define SCC 7'b01000_11 // sxx rs1,rs2,imm[11:0]
+`define MCC 7'b00100_11 // xxxi rd,rs1,imm[11:0]
+`define RCC 7'b01100_11 // xxx rd,rs1,rs2
+`define MAC 7'b11111_11 // mac rd,rs1,rs2
+
+// not implemented opcodes:
+
+`define FCC 7'b00011_11 // fencex
+`define CCC 7'b11100_11 // exx, csrxx
+
+// configuration file
+
+`include "../rtl/config.vh"
+
+module darkriscv
+//#(
+// parameter [31:0] RESET_PC = 0,
+// parameter [31:0] RESET_SP = 4096
+//)
+(
+ input CLK, // clock
+ input RES, // reset
+ input HLT, // halt
+
+`ifdef __THREADING__
+ input IREQ, // irq req
+`endif
+
+ input [31:0] IDATA, // instruction data bus
+ output [31:0] IADDR, // instruction addr bus
+
+ input [31:0] DATAI, // data bus (input)
+ output [31:0] DATAO, // data bus (output)
+ output [31:0] DADDR, // addr bus
+
+`ifdef __FLEXBUZZ__
+ output [ 2:0] DLEN, // data length
+ output RW, // data read/write
+`else
+ output [ 3:0] BE, // byte enable
+ output WR, // write enable
+ output RD, // read enable
+`endif
+
+ output [3:0] DEBUG // old-school osciloscope based debug! :)
+);
+
+ // dummy 32-bit words w/ all-0s and all-1s:
+
+ wire [31:0] ALL0 = 0;
+ wire [31:0] ALL1 = -1;
+
+`ifdef __THREADING__
+ reg XMODE = 0; // 0 = user, 1 = exception
+`endif
+
+ // pre-decode: IDATA is break apart as described in the RV32I specification
+
+ reg [31:0] XIDATA;
+
+ reg XLUI, XAUIPC, XJAL, XJALR, XBCC, XLCC, XSCC, XMCC, XRCC, XMAC, XRES=1; //, XFCC, XCCC;
+
+ reg [31:0] XSIMM;
+ reg [31:0] XUIMM;
+
+ always@(posedge CLK)
+ begin
+ XIDATA <= XRES ? 0 : HLT ? XIDATA : IDATA;
+
+ XLUI <= XRES ? 0 : HLT ? XLUI : IDATA[6:0]==`LUI;
+ XAUIPC <= XRES ? 0 : HLT ? XAUIPC : IDATA[6:0]==`AUIPC;
+ XJAL <= XRES ? 0 : HLT ? XJAL : IDATA[6:0]==`JAL;
+ XJALR <= XRES ? 0 : HLT ? XJALR : IDATA[6:0]==`JALR;
+
+ XBCC <= XRES ? 0 : HLT ? XBCC : IDATA[6:0]==`BCC;
+ XLCC <= XRES ? 0 : HLT ? XLCC : IDATA[6:0]==`LCC;
+ XSCC <= XRES ? 0 : HLT ? XSCC : IDATA[6:0]==`SCC;
+ XMCC <= XRES ? 0 : HLT ? XMCC : IDATA[6:0]==`MCC;
+
+ XRCC <= XRES ? 0 : HLT ? XRCC : IDATA[6:0]==`RCC;
+ XMAC <= XRES ? 0 : HLT ? XRCC : IDATA[6:0]==`MAC;
+ //XFCC <= XRES ? 0 : HLT ? XFCC : IDATA[6:0]==`FCC;
+ //XCCC <= XRES ? 0 : HLT ? XCCC : IDATA[6:0]==`CCC;
+
+ // signal extended immediate, according to the instruction type:
+
+ XSIMM <= XRES ? 0 : HLT ? XSIMM :
+ IDATA[6:0]==`SCC ? { IDATA[31] ? ALL1[31:12]:ALL0[31:12], IDATA[31:25],IDATA[11:7] } : // s-type
+ IDATA[6:0]==`BCC ? { IDATA[31] ? ALL1[31:13]:ALL0[31:13], IDATA[31],IDATA[7],IDATA[30:25],IDATA[11:8],ALL0[0] } : // b-type
+ IDATA[6:0]==`JAL ? { IDATA[31] ? ALL1[31:21]:ALL0[31:21], IDATA[31], IDATA[19:12], IDATA[20], IDATA[30:21], ALL0[0] } : // j-type
+ IDATA[6:0]==`LUI||
+ IDATA[6:0]==`AUIPC ? { IDATA[31:12], ALL0[11:0] } : // u-type
+ { IDATA[31] ? ALL1[31:12]:ALL0[31:12], IDATA[31:20] }; // i-type
+ // non-signal extended immediate, according to the instruction type:
+
+ XUIMM <= XRES ? 0: HLT ? XUIMM :
+ IDATA[6:0]==`SCC ? { ALL0[31:12], IDATA[31:25],IDATA[11:7] } : // s-type
+ IDATA[6:0]==`BCC ? { ALL0[31:13], IDATA[31],IDATA[7],IDATA[30:25],IDATA[11:8],ALL0[0] } : // b-type
+ IDATA[6:0]==`JAL ? { ALL0[31:21], IDATA[31], IDATA[19:12], IDATA[20], IDATA[30:21], ALL0[0] } : // j-type
+ IDATA[6:0]==`LUI||
+ IDATA[6:0]==`AUIPC ? { IDATA[31:12], ALL0[11:0] } : // u-type
+ { ALL0[31:12], IDATA[31:20] }; // i-type
+ end
+
+ // decode: after XIDATA
+`ifdef __3STAGE__
+ reg [1:0] FLUSH = -1; // flush instruction pipeline
+`else
+ reg FLUSH = -1; // flush instruction pipeline
+`endif
+
+`ifdef __THREADING__
+
+ `ifdef __RV32E__
+
+ reg [4:0] RESMODE = -1;
+
+ wire [4:0] DPTR = XRES ? RESMODE : { XMODE, XIDATA[10: 7] }; // set SP_RESET when RES==1
+ wire [4:0] S1PTR = { XMODE, XIDATA[18:15] };
+ wire [4:0] S2PTR = { XMODE, XIDATA[23:20] };
+ `else
+ reg [5:0] RESMODE = -1;
+
+ wire [5:0] DPTR = XRES ? RESMODE : { XMODE, XIDATA[11: 7] }; // set SP_RESET when RES==1
+ wire [5:0] S1PTR = { XMODE, XIDATA[19:15] };
+ wire [5:0] S2PTR = { XMODE, XIDATA[24:20] };
+ `endif
+
+ wire [6:0] OPCODE = FLUSH ? 0 : XIDATA[6:0];
+ wire [2:0] FCT3 = XIDATA[14:12];
+ wire [6:0] FCT7 = XIDATA[31:25];
+
+`else
+
+ `ifdef __RV32E__
+
+ reg [3:0] RESMODE = -1;
+
+ wire [3:0] DPTR = XRES ? RESMODE : XIDATA[10: 7]; // set SP_RESET when RES==1
+ wire [3:0] S1PTR = XIDATA[18:15];
+ wire [3:0] S2PTR = XIDATA[23:20];
+ `else
+ reg [4:0] RESMODE = -1;
+
+ wire [4:0] DPTR = XRES ? RESMODE : XIDATA[11: 7]; // set SP_RESET when RES==1
+ wire [4:0] S1PTR = XIDATA[19:15];
+ wire [4:0] S2PTR = XIDATA[24:20];
+ `endif
+
+ wire [6:0] OPCODE = FLUSH ? 0 : XIDATA[6:0];
+ wire [2:0] FCT3 = XIDATA[14:12];
+ wire [6:0] FCT7 = XIDATA[31:25];
+
+`endif
+
+ wire [31:0] SIMM = XSIMM;
+ wire [31:0] UIMM = XUIMM;
+
+ // main opcode decoder:
+
+ wire LUI = FLUSH ? 0 : XLUI; // OPCODE==7'b0110111;
+ wire AUIPC = FLUSH ? 0 : XAUIPC; // OPCODE==7'b0010111;
+ wire JAL = FLUSH ? 0 : XJAL; // OPCODE==7'b1101111;
+ wire JALR = FLUSH ? 0 : XJALR; // OPCODE==7'b1100111;
+
+ wire BCC = FLUSH ? 0 : XBCC; // OPCODE==7'b1100011; //FCT3
+ wire LCC = FLUSH ? 0 : XLCC; // OPCODE==7'b0000011; //FCT3
+ wire SCC = FLUSH ? 0 : XSCC; // OPCODE==7'b0100011; //FCT3
+ wire MCC = FLUSH ? 0 : XMCC; // OPCODE==7'b0010011; //FCT3
+
+ wire RCC = FLUSH ? 0 : XRCC; // OPCODE==7'b0110011; //FCT3
+ wire MAC = FLUSH ? 0 : XMAC; // OPCODE==7'b0110011; //FCT3
+ //wire FCC = FLUSH ? 0 : XFCC; // OPCODE==7'b0001111; //FCT3
+ //wire CCC = FLUSH ? 0 : XCCC; // OPCODE==7'b1110011; //FCT3
+
+`ifdef __THREADING__
+`ifdef __3STAGE__
+ reg [31:0] NXPC2 [0:1]; // 32-bit program counter t+2
+`endif
+ reg [31:0] NXPC; // 32-bit program counter t+1
+ reg [31:0] PC; // 32-bit program counter t+0
+
+ `ifdef __RV32E__
+ reg [31:0] REG1 [0:31]; // general-purpose 16x32-bit registers (s1)
+ reg [31:0] REG2 [0:31]; // general-purpose 16x32-bit registers (s2)
+ `else
+ reg [31:0] REG1 [0:63]; // general-purpose 32x32-bit registers (s1)
+ reg [31:0] REG2 [0:63]; // general-purpose 32x32-bit registers (s2)
+ `endif
+`else
+`ifdef __3STAGE__
+ reg [31:0] NXPC2; // 32-bit program counter t+2
+`endif
+ reg [31:0] NXPC; // 32-bit program counter t+1
+ reg [31:0] PC; // 32-bit program counter t+0
+
+ `ifdef __RV32E__
+ reg [31:0] REG1 [0:15]; // general-purpose 16x32-bit registers (s1)
+ reg [31:0] REG2 [0:15]; // general-purpose 16x32-bit registers (s2)
+ `else
+ reg [31:0] REG1 [0:31]; // general-purpose 32x32-bit registers (s1)
+ reg [31:0] REG2 [0:31]; // general-purpose 32x32-bit registers (s2)
+ `endif
+`endif
+
+ // source-1 and source-1 register selection
+
+ wire signed [31:0] S1REG = REG1[S1PTR];
+ wire signed [31:0] S2REG = REG2[S2PTR];
+
+ wire [31:0] U1REG = REG1[S1PTR];
+ wire [31:0] U2REG = REG2[S2PTR];
+
+ // L-group of instructions (OPCODE==7'b0000011)
+
+`ifdef __FLEXBUZZ__
+
+ wire [31:0] LDATA = FCT3[1:0]==0 ? { FCT3[2]==0&&DATAI[ 7] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[ 7: 0] } :
+ FCT3[1:0]==1 ? { FCT3[2]==0&&DATAI[15] ? ALL1[31:16]:ALL0[31:16] , DATAI[15: 0] } :
+ DATAI;
+`else
+ wire [31:0] LDATA = FCT3==0||FCT3==4 ? ( DADDR[1:0]==3 ? { FCT3==0&&DATAI[31] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[31:24] } :
+ DADDR[1:0]==2 ? { FCT3==0&&DATAI[23] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[23:16] } :
+ DADDR[1:0]==1 ? { FCT3==0&&DATAI[15] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[15: 8] } :
+ { FCT3==0&&DATAI[ 7] ? ALL1[31: 8]:ALL0[31: 8] , DATAI[ 7: 0] } ):
+ FCT3==1||FCT3==5 ? ( DADDR[1]==1 ? { FCT3==1&&DATAI[31] ? ALL1[31:16]:ALL0[31:16] , DATAI[31:16] } :
+ { FCT3==1&&DATAI[15] ? ALL1[31:16]:ALL0[31:16] , DATAI[15: 0] } ) :
+ DATAI;
+`endif
+
+ // S-group of instructions (OPCODE==7'b0100011)
+
+`ifdef __FLEXBUZZ__
+
+ wire [31:0] SDATA = U2REG; /* FCT3==0 ? { ALL0 [31: 8], U2REG[ 7:0] } :
+ FCT3==1 ? { ALL0 [31:16], U2REG[15:0] } :
+ U2REG;*/
+`else
+ wire [31:0] SDATA = FCT3==0 ? ( DADDR[1:0]==3 ? { U2REG[ 7: 0], ALL0 [23:0] } :
+ DADDR[1:0]==2 ? { ALL0 [31:24], U2REG[ 7:0], ALL0[15:0] } :
+ DADDR[1:0]==1 ? { ALL0 [31:16], U2REG[ 7:0], ALL0[7:0] } :
+ { ALL0 [31: 8], U2REG[ 7:0] } ) :
+ FCT3==1 ? ( DADDR[1]==1 ? { U2REG[15: 0], ALL0 [15:0] } :
+ { ALL0 [31:16], U2REG[15:0] } ) :
+ U2REG;
+`endif
+
+ // C-group not implemented yet!
+
+ wire [31:0] CDATA = 0; // status register istructions not implemented yet
+
+ // RM-group of instructions (OPCODEs==7'b0010011/7'b0110011), merged! src=immediate(M)/register(R)
+
+ wire signed [31:0] S2REGX = XMCC ? SIMM : S2REG;
+ wire [31:0] U2REGX = XMCC ? UIMM : U2REG;
+
+ wire [31:0] RMDATA = FCT3==7 ? U1REG&S2REGX :
+ FCT3==6 ? U1REG|S2REGX :
+ FCT3==4 ? U1REG^S2REGX :
+ FCT3==3 ? U1REG>U2REGX[4:0]; // workaround for modelsim
+//`else
+ FCT7[5] ? $signed(S1REG>>>U2REGX[4:0]) : // (FCT7[5] ? U1REG>>>U2REG[4:0] :
+//`endif
+ U1REG>>U2REGX[4:0];
+`ifdef __MAC16X16__
+
+ // MAC instruction rd += s1*s2 (OPCODE==7'b1111111)
+ //
+ // 0000000 01100 01011 100 01100 0110011 xor a2,a1,a2
+ // 0000000 01010 01100 000 01010 0110011 add a0,a2,a0
+ // 0000000 01100 01011 000 01010 1111111 mac a0,a1,a2
+ //
+ // 0000 0000 1100 0101 1000 0101 0111 1111 = 00c5857F
+
+ wire signed [15:0] K1TMP = S1REG[15:0];
+ wire signed [15:0] K2TMP = S2REG[15:0];
+ wire signed [31:0] KDATA = K1TMP*K2TMP;
+
+`endif
+
+ // J/B-group of instructions (OPCODE==7'b1100011)
+
+ wire BMUX = BCC==1 && (
+ FCT3==4 ? S1REG< S2REGX : // blt
+ FCT3==5 ? S1REG>=S2REG : // bge
+ FCT3==6 ? U1REG< U2REGX : // bltu
+ FCT3==7 ? U1REG>=U2REG : // bgeu
+ FCT3==0 ? !(U1REG^S2REGX) : //U1REG==U2REG : // beq
+ /*FCT3==1 ? */ U1REG^S2REGX); //U1REG!=U2REG); // bne
+ //0);
+
+ wire JREQ = (JAL||JALR||BMUX);
+ wire [31:0] JVAL = JALR ? DADDR : PC+SIMM; // SIMM + (JALR ? U1REG : PC);
+
+`ifdef __PERFMETER__
+ integer clocks=0, user=0, super=0, halt=0, flush=0;
+
+ always@(posedge CLK)
+ begin
+ if(!XRES)
+ begin
+ clocks = clocks+1;
+
+ `ifdef __THREADING__
+
+ if(XMODE==0 && !HLT && !FLUSH) user = user +1;
+ if(XMODE==1 && !HLT && !FLUSH) super = super+1;
+ `else
+ if(!HLT && !FLUSH) user = user +1;
+ `endif
+
+ if(HLT) halt=halt+1;
+ if(FLUSH) flush=flush+1;
+
+ if(clocks && clocks%`__PERFMETER__==0)
+ begin
+ $display("%d clocks: %0d%% user, %0d%% super, %0d%% ws, %0d%% flush",
+ clocks,
+ 100*user/clocks,
+ 100*super/clocks,
+ 100*halt/clocks,
+ 100*flush/clocks);
+ end
+ end
+ end
+`endif
+
+ always@(posedge CLK)
+ begin
+ RESMODE <= RES ? -1 : RESMODE ? RESMODE-1 : 0;
+
+ XRES <= |RESMODE;
+
+`ifdef __3STAGE__
+ FLUSH <= XRES ? 2 : HLT ? FLUSH : // reset and halt
+ FLUSH ? FLUSH-1 :
+ (JAL||JALR||BMUX) ? 2 : 0; // flush the pipeline!
+`else
+ FLUSH <= XRES ? 1 : HLT ? FLUSH : // reset and halt
+ (JAL||JALR||BMUX); // flush the pipeline!
+`endif
+
+`ifdef __RV32E__
+ REG1[DPTR] <= XRES ? (RESMODE[3:0]==2 ? `__RESETSP__ : 0) : // reset sp
+`else
+ REG1[DPTR] <= XRES ? (RESMODE[4:0]==2 ? `__RESETSP__ : 0) : // reset sp
+`endif
+ HLT ? REG1[DPTR] : // halt
+ !DPTR ? 0 : // x0 = 0, always!
+ AUIPC ? PC+SIMM :
+ JAL||
+ JALR ? NXPC :
+ LUI ? SIMM :
+ LCC ? LDATA :
+ MCC||RCC ? RMDATA:
+`ifdef __MAC16X16__
+ MAC ? REG2[DPTR]+KDATA :
+`endif
+ //CCC ? CDATA :
+ REG1[DPTR];
+`ifdef __RV32E__
+ REG2[DPTR] <= XRES ? (RESMODE[3:0]==2 ? `__RESETSP__ : 0) : // reset sp
+`else
+ REG2[DPTR] <= XRES ? (RESMODE[4:0]==2 ? `__RESETSP__ : 0) : // reset sp
+`endif
+ HLT ? REG2[DPTR] : // halt
+ !DPTR ? 0 : // x0 = 0, always!
+ AUIPC ? PC+SIMM :
+ JAL||
+ JALR ? NXPC :
+ LUI ? SIMM :
+ LCC ? LDATA :
+ MCC||RCC ? RMDATA:
+`ifdef __MAC16X16__
+ MAC ? REG2[DPTR]+KDATA :
+`endif
+ //CCC ? CDATA :
+ REG2[DPTR];
+
+`ifdef __3STAGE__
+
+`ifdef __THREADING__
+
+ NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2[XMODE];
+
+ NXPC2[RES ? RESMODE[0] : XMODE] <= XRES ? `__RESETPC__ : HLT ? NXPC2[XMODE] : // reset and halt
+ JREQ ? JVAL : // jmp/bra
+ NXPC2[XMODE]+4; // normal flow
+
+ XMODE <= XRES ? 0 : HLT ? XMODE : // reset and halt
+ XMODE==0&& IREQ&&(JAL||JALR||BMUX) ? 1 : // wait pipeflush to switch to irq
+ XMODE==1&&!IREQ&&(JAL||JALR||BMUX) ? 0 : XMODE; // wait pipeflush to return from irq
+
+`else
+ NXPC <= /*XRES ? `__RESETPC__ :*/ HLT ? NXPC : NXPC2;
+
+ NXPC2 <= XRES ? `__RESETPC__ : HLT ? NXPC2 : // reset and halt
+ JREQ ? JVAL : // jmp/bra
+ NXPC2+4; // normal flow
+
+`endif
+
+`else
+ NXPC <= XRES ? `__RESETPC__ : HLT ? NXPC : // reset and halt
+ JREQ ? JVAL : // jmp/bra
+ NXPC+4; // normal flow
+`endif
+ PC <= /*XRES ? `__RESETPC__ :*/ HLT ? PC : NXPC; // current program counter
+ end
+
+ // IO and memory interface
+
+ assign DATAO = SDATA; // SCC ? SDATA : 0;
+ assign DADDR = U1REG + SIMM; // (SCC||LCC) ? U1REG + SIMM : 0;
+
+ // based in the Scc and Lcc
+
+`ifdef __FLEXBUZZ__
+ assign RW = !SCC;
+ assign DLEN[0] = (SCC||LCC)&&FCT3[1:0]==0;
+ assign DLEN[1] = (SCC||LCC)&&FCT3[1:0]==1;
+ assign DLEN[2] = (SCC||LCC)&&FCT3[1:0]==2;
+`else
+ assign RD = LCC;
+ assign WR = SCC;
+ assign BE = FCT3==0||FCT3==4 ? ( DADDR[1:0]==3 ? 4'b1000 : // sb/lb
+ DADDR[1:0]==2 ? 4'b0100 :
+ DADDR[1:0]==1 ? 4'b0010 :
+ 4'b0001 ) :
+ FCT3==1||FCT3==5 ? ( DADDR[1]==1 ? 4'b1100 : // sh/lh
+ 4'b0011 ) :
+ 4'b1111; // sw/lw
+`endif
+
+`ifdef __3STAGE__
+`ifdef __THREADING__
+ assign IADDR = NXPC2[XMODE];
+`else
+ assign IADDR = NXPC2;
+`endif
+`else
+ assign IADDR = NXPC;
+`endif
+
+ assign DEBUG = { XRES, |FLUSH, SCC, LCC };
+
+endmodule
Index: darkriscv/trunk/rtl/darksocv.v
===================================================================
--- darkriscv/trunk/rtl/darksocv.v (nonexistent)
+++ darkriscv/trunk/rtl/darksocv.v (revision 2)
@@ -0,0 +1,746 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+`timescale 1ns / 1ps
+`include "../rtl/config.vh"
+
+module darksocv
+(
+ input XCLK, // external clock
+ input XRES, // external reset
+
+ input UART_RXD, // UART receive line
+ output UART_TXD, // UART transmit line
+
+ output [3:0] LED, // on-board leds
+ output [3:0] DEBUG // osciloscope
+);
+
+ // internal/external reset logic
+
+ reg [7:0] IRES = -1;
+
+`ifdef INVRES
+ always@(posedge XCLK) IRES <= XRES==0 ? -1 : IRES[7] ? IRES-1 : 0; // reset low
+`else
+ always@(posedge XCLK) IRES <= XRES==1 ? -1 : IRES[7] ? IRES-1 : 0; // reset high
+`endif
+
+ // clock generator logic
+
+`ifdef BOARD_CK_REF
+
+ //`define BOARD_CK (`BOARD_CK_REF * `BOARD_CK_MUL / `BOARD_CK_DIV)
+
+ wire LOCKED, CLKFB, CLK;
+
+ // useful script to calculate MUL/DIV values:
+ //
+ // awk 'BEGIN { for(m=2;m<=32;m++) for(d=1;d<=32;d++) print 66.666*m/d,m,d }' | sort -n
+ //
+ // example: reference w/ 66MHz, m=19, d=13 and fx=97.4MHz. not so useful after I discovered
+ // that my evaluation board already has external clock generator :D
+
+ `ifdef XILINX7CLK
+
+ MMCME2_BASE #(
+ .BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
+ .CLKFBOUT_MULT_F(`BOARD_CK_MUL), // Multiply value for all CLKOUT (2.000-64.000).
+ .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
+ .CLKIN1_PERIOD((1e9/`BOARD_CK_REF)), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
+ // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
+ .CLKOUT0_DIVIDE_F(`BOARD_CK_DIV), // Divide amount for CLKOUT0 (1.000-128.000).
+ .CLKOUT1_DIVIDE(`BOARD_CK_DIV),
+ .CLKOUT2_DIVIDE(`BOARD_CK_DIV),
+ .CLKOUT3_DIVIDE(`BOARD_CK_DIV),
+ .CLKOUT4_DIVIDE(`BOARD_CK_DIV),
+ .CLKOUT5_DIVIDE(`BOARD_CK_DIV),
+ .CLKOUT6_DIVIDE(`BOARD_CK_DIV),
+ // CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
+ .CLKOUT0_DUTY_CYCLE(0.5),
+ .CLKOUT1_DUTY_CYCLE(0.5),
+ .CLKOUT2_DUTY_CYCLE(0.5),
+ .CLKOUT3_DUTY_CYCLE(0.5),
+ .CLKOUT4_DUTY_CYCLE(0.5),
+ .CLKOUT5_DUTY_CYCLE(0.5),
+ .CLKOUT6_DUTY_CYCLE(0.5),
+ // CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
+ .CLKOUT0_PHASE(0.0),
+ .CLKOUT1_PHASE(0.0),
+ .CLKOUT2_PHASE(0.0),
+ .CLKOUT3_PHASE(0.0),
+ .CLKOUT4_PHASE(0.0),
+ .CLKOUT5_PHASE(0.0),
+ .CLKOUT6_PHASE(0.0),
+ .CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
+ .DIVCLK_DIVIDE(1), // Master division value (1-106)
+ .REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
+ .STARTUP_WAIT("TRUE") // Delays DONE until MMCM is locked (FALSE, TRUE)
+ )
+ MMCME2_BASE_inst (
+ // Clock Outputs: 1-bit (each) output: User configurable clock outputs
+ .CLKOUT0(CLK), // 1-bit output: CLKOUT0
+ //.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
+ //.CLKOUT1(CLKPWM), // 1-bit output: CLKOUT1
+ //.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
+ //.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
+ //.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
+ //.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
+ //.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
+ //.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
+ //.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
+ //.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
+ // Feedback Clocks: 1-bit (each) output: Clock feedback ports
+ .CLKFBOUT(CLKFB), // 1-bit output: Feedback clock
+ //.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
+ // Status Ports: 1-bit (each) output: MMCM status ports
+ .LOCKED(LOCKED), // 1-bit output: LOCK
+ // Clock Inputs: 1-bit (each) input: Clock input
+ .CLKIN1(XCLK), // 1-bit input: Clock
+ // Control Ports: 1-bit (each) input: MMCM control ports
+ .PWRDWN(1'b0), // 1-bit input: Power-down
+ .RST(IRES[7]), // 1-bit input: Reset
+ // Feedback Clocks: 1-bit (each) input: Clock feedback ports
+ .CLKFBIN(CLKFB) // 1-bit input: Feedback clock
+ );
+
+ `else
+
+ DCM_SP #(
+ .CLKDV_DIVIDE(2.0), // CLKDV divide value
+ // (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
+ .CLKFX_DIVIDE(`BOARD_CK_DIV), // Divide value on CLKFX outputs - D - (1-32)
+ .CLKFX_MULTIPLY(`BOARD_CK_MUL), // Multiply value on CLKFX outputs - M - (2-32)
+ .CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE)
+ .CLKIN_PERIOD((1e9/`BOARD_CK_REF)), // Input clock period specified in nS
+ .CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE)
+ .CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X)
+ .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
+ .DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
+ .DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
+ .DSS_MODE("NONE"), // Unsupported - Do not change value
+ .DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value
+ .FACTORY_JF(16'hc080), // Unsupported - Do not change value
+ .PHASE_SHIFT(0), // Amount of fixed phase shift (-255 to 255)
+ .STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
+ )
+ DCM_SP_inst (
+ //.CLK0(CLK0), // 1-bit output: 0 degree clock output
+ //.CLK180(CLK180), // 1-bit output: 180 degree clock output
+ //.CLK270(CLK270), // 1-bit output: 270 degree clock output
+ //.CLK2X(CLK2X), // 1-bit output: 2X clock frequency clock output
+ //.CLK2X180(CLK2X180), // 1-bit output: 2X clock frequency, 180 degree clock output
+ //.CLK90(CLK90), // 1-bit output: 90 degree clock output
+ //.CLKDV(CLKDV), // 1-bit output: Divided clock output
+ .CLKFX(CLK), // 1-bit output: Digital Frequency Synthesizer output (DFS)
+ //.CLKFX180(CLKFX180), // 1-bit output: 180 degree CLKFX output
+ .LOCKED(LOCKED), // 1-bit output: DCM_SP Lock Output
+ //.PSDONE(PSDONE), // 1-bit output: Phase shift done output
+ //.STATUS(STATUS), // 8-bit output: DCM_SP status output
+ //.CLKFB(CLKFB), // 1-bit input: Clock feedback input
+ .CLKIN(XCLK), // 1-bit input: Clock input
+ //.DSSEN(DSSEN), // 1-bit input: Unsupported, specify to GND.
+ //.PSCLK(PSCLK), // 1-bit input: Phase shift clock input
+ .PSEN(1'b0), // 1-bit input: Phase shift enable
+ //.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement input
+ .RST(IRES[7]) // 1-bit input: Active high reset input
+ );
+
+ `endif
+
+ reg [7:0] DRES = -1;
+
+ always@(posedge CLK)
+ begin
+ DRES <= LOCKED==0 ? -1 : DRES ? DRES-1 : 0;
+ end
+
+ wire RES = DRES[7];
+
+`else
+
+ // when there is no need for a clock generator:
+
+ wire CLK = XCLK;
+ wire RES = IRES[7];
+`endif
+ // ro/rw memories
+
+`ifdef __HARVARD__
+
+ reg [31:0] ROM [0:1023]; // ro memory
+ reg [31:0] RAM [0:1023]; // rw memory
+
+ // memory initialization
+
+ integer i;
+ initial
+ begin
+ for(i=0;i!=1024;i=i+1)
+ begin
+ ROM[i] = 32'd0;
+ RAM[i] = 32'd0;
+ end
+
+ // workaround for vivado: no path in simulation and .mem extension
+
+`ifdef XILINX_SIMULATOR
+ $readmemh("darksocv.rom.mem",ROM);
+ $readmemh("darksocv.ram.mem",RAM);
+`else
+ $readmemh("../src/darksocv.rom.mem",ROM);
+ $readmemh("../src/darksocv.ram.mem",RAM);
+`endif
+ end
+
+`else
+
+ reg [31:0] MEM [0:2047]; // ro memory
+
+ // memory initialization
+
+ integer i;
+ initial
+ begin
+ for(i=0;i!=2048;i=i+1)
+ begin
+ MEM[i] = 32'd0;
+ end
+
+ // workaround for vivado: no path in simulation and .mem extension
+
+`ifdef XILINX_SIMULATOR
+ $readmemh("darksocv.mem",MEM);
+`else
+ $readmemh("../src/darksocv.mem",MEM);
+`endif
+ end
+
+`endif
+
+ // darkriscv bus interface
+
+ wire [31:0] IADDR;
+ wire [31:0] DADDR;
+ wire [31:0] IDATA;
+ wire [31:0] DATAO;
+ wire [31:0] DATAI;
+ wire WR,RD;
+ wire [3:0] BE;
+
+`ifdef __FLEXBUZZ__
+ wire [31:0] XATAO;
+ wire [31:0] XATAI;
+ wire [ 2:0] DLEN;
+ wire RW;
+`endif
+
+ wire [31:0] IOMUX [0:3];
+
+ reg [15:0] GPIOFF = 0;
+ reg [15:0] LEDFF = 0;
+
+ wire HLT;
+
+`ifdef __ICACHE__
+
+ // instruction cache
+
+ reg [55:0] ICACHE [0:63]; // instruction cache
+ reg [63:0] ITAG = 0; // instruction cache tag
+
+ wire [5:0] IPTR = IADDR[7:2];
+ wire [55:0] ICACHEO = ICACHE[IPTR];
+ wire [31:0] ICACHED = ICACHEO[31: 0]; // data
+ wire [31:8] ICACHEA = ICACHEO[55:32]; // address
+
+ wire IHIT = ITAG[IPTR] && ICACHEA==IADDR[31:8];
+
+ reg IFFX = 0;
+ reg IFFX2 = 0;
+
+ reg [31:0] ROMFF;
+
+ always@(posedge CLK)
+ begin
+ ROMFF <= ROM[IADDR[11:2]];
+
+ if(IFFX2)
+ begin
+ IFFX2 <= 0;
+ IFFX <= 0;
+ end
+ else
+ if(!IHIT)
+ begin
+ ICACHE[IPTR] <= { IADDR[31:8], ROMFF };
+ ITAG[IPTR] <= IFFX; // cached!
+ IFFX <= 1;
+ IFFX2 <= IFFX;
+ end
+ end
+
+ assign IDATA = ICACHED;
+
+`else
+
+ reg [31:0] ROMFF;
+
+`ifdef __WAITSTATES__
+
+ reg [1:0] IHITACK = 0;
+
+ wire IHIT = !(IHITACK!=1);
+
+ always@(posedge CLK) // stage #1.0
+ begin
+ IHITACK <= RES ? 1 : IHITACK ? IHITACK-1 : 1; // wait-states
+ end
+`else
+
+ wire IHIT = 1;
+
+`endif
+
+
+`ifdef __3STAGE__
+
+ reg [31:0] ROMFF2 = 0;
+ reg HLT2 = 0;
+
+ always@(posedge CLK) // stage #0.5
+ begin
+ if(HLT)
+ begin
+ ROMFF2 <= ROMFF;
+ end
+
+ HLT2 <= HLT;
+ end
+
+ assign IDATA = HLT2 ? ROMFF2 : ROMFF;
+`else
+ assign IDATA = ROMFF;
+`endif
+
+ always@(posedge CLK) // stage #0.5
+ begin
+`ifdef __HARVARD__
+ ROMFF <= ROM[IADDR[11:2]];
+`else
+ ROMFF <= MEM[IADDR[12:2]];
+`endif
+ end
+
+ //assign IDATA = ROM[IADDR[11:2]];
+
+// always@(posedge CLK)
+// begin
+// // weird bug appears to be related to the "sw ra,12(sp)" instruction.
+// if(WR&&DADDR[31]==0&&DADDR[12]==0)
+// begin
+// ROMBUG <= IADDR;
+// end
+// end
+
+// assign IDATA = ROMFF;
+
+`endif
+
+`ifdef __DCACHE__
+
+ // data cache
+
+ reg [55:0] DCACHE [0:63]; // data cache
+ reg [63:0] DTAG = 0; // data cache tag
+
+ wire [5:0] DPTR = DADDR[7:2];
+ wire [55:0] DCACHEO = DCACHE[DPTR];
+ wire [31:0] DCACHED = DCACHEO[31: 0]; // data
+ wire [31:8] DCACHEA = DCACHEO[55:32]; // address
+
+ wire DHIT = RD&&!DADDR[31]/*&&DADDR[12]*/ ? DTAG[DPTR] && DCACHEA==DADDR[31:8] : 1;
+
+ reg FFX = 0;
+ reg FFX2 = 0;
+
+ reg [31:0] RAMFF;
+
+ reg WTAG = 0;
+ reg [31:0] WCACHEA = 0;
+
+ wire WHIT = WR&&!DADDR[31]/*&&DADDR[12]*/ ? WTAG&&WCACHEA==DADDR : 1;
+
+ always@(posedge CLK)
+ begin
+ RAMFF <= RAM[DADDR[11:2]];
+
+ if(FFX2)
+ begin
+ FFX2 <= 0;
+ FFX <= 0;
+ WCACHEA <= 0;
+ WTAG <= 0;
+ end
+ else
+ if(!WHIT)
+ begin
+ //individual byte/word/long selection, thanks to HYF!
+ if(BE[0]) RAM[DADDR[11:2]][0 * 8 + 7: 0 * 8] <= DATAO[0 * 8 + 7: 0 * 8];
+ if(BE[1]) RAM[DADDR[11:2]][1 * 8 + 7: 1 * 8] <= DATAO[1 * 8 + 7: 1 * 8];
+ if(BE[2]) RAM[DADDR[11:2]][2 * 8 + 7: 2 * 8] <= DATAO[2 * 8 + 7: 2 * 8];
+ if(BE[3]) RAM[DADDR[11:2]][3 * 8 + 7: 3 * 8] <= DATAO[3 * 8 + 7: 3 * 8];
+
+ DCACHE[DPTR][0 * 8 + 7: 0 * 8] <= BE[0] ? DATAO[0 * 8 + 7: 0 * 8] : RAMFF[0 * 8 + 7: 0 * 8];
+ DCACHE[DPTR][1 * 8 + 7: 1 * 8] <= BE[1] ? DATAO[1 * 8 + 7: 1 * 8] : RAMFF[1 * 8 + 7: 1 * 8];
+ DCACHE[DPTR][2 * 8 + 7: 2 * 8] <= BE[2] ? DATAO[2 * 8 + 7: 2 * 8] : RAMFF[2 * 8 + 7: 2 * 8];
+ DCACHE[DPTR][3 * 8 + 7: 3 * 8] <= BE[3] ? DATAO[3 * 8 + 7: 3 * 8] : RAMFF[3 * 8 + 7: 3 * 8];
+
+ DCACHE[DPTR][55:32] <= DADDR[31:8];
+
+ //DCACHE[DPTR] <= { DADDR[31:8],
+ // BE[3] ? DATAO[3 * 8 + 7: 3 * 8] : RAMFF[3 * 8 + 7: 3 * 8],
+ // BE[2] ? DATAO[2 * 8 + 7: 2 * 8] : RAMFF[2 * 8 + 7: 2 * 8],
+ // BE[1] ? DATAO[1 * 8 + 7: 1 * 8] : RAMFF[1 * 8 + 7: 1 * 8],
+ // BE[0] ? DATAO[0 * 8 + 7: 0 * 8] : RAMFF[0 * 8 + 7: 0 * 8]
+ // };
+
+ DTAG[DPTR] <= FFX; // cached!
+ WTAG <= FFX;
+
+ WCACHEA <= DADDR;
+
+ FFX <= 1;
+ FFX2 <= FFX;
+ end
+ else
+ if(!DHIT)
+ begin
+ DCACHE[DPTR] <= { DADDR[31:8], RAMFF };
+ DTAG[DPTR] <= FFX; // cached!
+ FFX <= 1;
+ FFX2 <= FFX;
+ end
+ end
+
+ assign DATAI = DADDR[31] ? IOMUX[DADDR[3:2]] : DCACHED;
+
+`else
+
+ // no cache!
+
+ `ifdef __FLEXBUZZ__
+
+ // must work just exactly as the default interface, since we have no
+ // flexbuzz devices available yet (i.e., all devices are 32-bit now)
+
+ assign XATAI = DLEN[0] ? ( DADDR[1:0]==3 ? DATAI[31:24] :
+ DADDR[1:0]==2 ? DATAI[23:16] :
+ DADDR[1:0]==1 ? DATAI[15: 8] :
+ DATAI[ 7: 0] ):
+ DLEN[1] ? ( DADDR[1]==1 ? DATAI[31:16] :
+ DATAI[15: 0] ):
+ DATAI;
+
+ assign DATAO = DLEN[0] ? ( DADDR[1:0]==3 ? { XATAO[ 7: 0], 24'hx } :
+ DADDR[1:0]==2 ? { 8'hx, XATAO[ 7: 0], 16'hx } :
+ DADDR[1:0]==1 ? { 16'hx, XATAO[ 7: 0], 8'hx } :
+ { 24'hx, XATAO[ 7: 0] } ):
+ DLEN[1] ? ( DADDR[1]==1 ? { XATAO[15: 0], 16'hx } :
+ { 16'hx, XATAO[15: 0] } ):
+ XATAO;
+
+ assign RD = DLEN&&RW==1;
+ assign WR = DLEN&&RW==0;
+
+ assign BE = DLEN[0] ? ( DADDR[1:0]==3 ? 4'b1000 : // 8-bit
+ DADDR[1:0]==2 ? 4'b0100 :
+ DADDR[1:0]==1 ? 4'b0010 :
+ 4'b0001 ) :
+ DLEN[1] ? ( DADDR[1]==1 ? 4'b1100 : // 16-bit
+ 4'b0011 ) :
+ 4'b1111; // 32-bit
+
+ `endif
+
+ reg [31:0] RAMFF;
+`ifdef __WAITSTATES__
+
+ reg [1:0] DACK = 0;
+
+ wire WHIT = 1;
+ wire DHIT = !((WR||RD) && DACK!=1);
+
+ always@(posedge CLK) // stage #1.0
+ begin
+ DACK <= RES ? 0 : DACK ? DACK-1 : (RD||WR) ? 1 : 0; // wait-states
+ end
+
+`elsif __3STAGE__
+
+ // for single phase clock: 1 wait state in read op always required!
+
+ reg [1:0] DACK = 0;
+
+ wire WHIT = 1;
+ wire DHIT = !((RD||WR) && DACK!=1); // the WR operatio does not need ws. in this config.
+
+ always@(posedge CLK) // stage #1.0
+ begin
+ DACK <= RES ? 0 : DACK ? DACK-1 : (RD||WR) ? 1 : 0; // wait-states
+ end
+
+`else
+
+ // for dual phase clock: 0 wait state
+
+ wire WHIT = 1;
+ wire DHIT = 1;
+
+`endif
+
+ always@(posedge CLK) // stage #1.5
+ begin
+`ifdef __HARVARD__
+ RAMFF <= RAM[DADDR[11:2]];
+`else
+ RAMFF <= MEM[DADDR[12:2]];
+`endif
+ end
+
+ //assign DATAI = DADDR[31] ? IOMUX : RAM[DADDR[11:2]];
+
+ reg [31:0] IOMUXFF;
+
+ //individual byte/word/long selection, thanks to HYF!
+
+ always@(posedge CLK)
+ begin
+
+`ifdef __3STAGE__
+
+ // read-modify-write operation w/ 1 wait-state:
+
+ if(!HLT&&WR&&DADDR[31]==0/*&&DADDR[12]==1*/)
+ begin
+ `ifdef __HARVARD__
+ RAM[DADDR[11:2]] <=
+ `else
+ MEM[DADDR[12:2]] <=
+ `endif
+ {
+ BE[3] ? DATAO[3 * 8 + 7: 3 * 8] : RAMFF[3 * 8 + 7: 3 * 8],
+ BE[2] ? DATAO[2 * 8 + 7: 2 * 8] : RAMFF[2 * 8 + 7: 2 * 8],
+ BE[1] ? DATAO[1 * 8 + 7: 1 * 8] : RAMFF[1 * 8 + 7: 1 * 8],
+ BE[0] ? DATAO[0 * 8 + 7: 0 * 8] : RAMFF[0 * 8 + 7: 0 * 8]
+ };
+ end
+
+`else
+ // write-only operation w/ 0 wait-states:
+ `ifdef __HARVARD__
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[3]) RAM[DADDR[11:2]][3 * 8 + 7: 3 * 8] <= DATAO[3 * 8 + 7: 3 * 8];
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[2]) RAM[DADDR[11:2]][2 * 8 + 7: 2 * 8] <= DATAO[2 * 8 + 7: 2 * 8];
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[1]) RAM[DADDR[11:2]][1 * 8 + 7: 1 * 8] <= DATAO[1 * 8 + 7: 1 * 8];
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[0]) RAM[DADDR[11:2]][0 * 8 + 7: 0 * 8] <= DATAO[0 * 8 + 7: 0 * 8];
+ `else
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[3]) MEM[DADDR[12:2]][3 * 8 + 7: 3 * 8] <= DATAO[3 * 8 + 7: 3 * 8];
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[2]) MEM[DADDR[12:2]][2 * 8 + 7: 2 * 8] <= DATAO[2 * 8 + 7: 2 * 8];
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[1]) MEM[DADDR[12:2]][1 * 8 + 7: 1 * 8] <= DATAO[1 * 8 + 7: 1 * 8];
+ if(WR&&DADDR[31]==0&&/*DADDR[12]==1&&*/BE[0]) MEM[DADDR[12:2]][0 * 8 + 7: 0 * 8] <= DATAO[0 * 8 + 7: 0 * 8];
+ `endif
+`endif
+
+ IOMUXFF <= IOMUX[DADDR[3:2]]; // read w/ 2 wait-states
+ end
+
+ //assign DATAI = DADDR[31] ? IOMUX[DADDR[3:2]] : RAMFF;
+ assign DATAI = DADDR[31] ? /*IOMUX[DADDR[3:2]]*/ IOMUXFF : RAMFF;
+
+`endif
+
+ // io for debug
+
+ reg [7:0] IREQ = 0;
+ reg [7:0] IACK = 0;
+
+ reg [31:0] TIMERFF;
+
+ wire [7:0] BOARD_IRQ;
+
+ wire [7:0] BOARD_ID = `BOARD_ID; // board id
+ wire [7:0] BOARD_CM = (`BOARD_CK/1000000); // board clock (MHz)
+ wire [7:0] BOARD_CK = (`BOARD_CK/10000)%100; // board clock (kHz)
+
+ assign IOMUX[0] = { BOARD_IRQ, BOARD_CK, BOARD_CM, BOARD_ID };
+ //assign IOMUX[1] = from UART!
+ assign IOMUX[2] = { GPIOFF, LEDFF };
+ assign IOMUX[3] = TIMERFF;
+
+ reg [31:0] TIMER = 0;
+
+ reg XTIMER = 0;
+
+ always@(posedge CLK)
+ begin
+ if(WR&&DADDR[31]&&DADDR[3:0]==4'b1000)
+ begin
+ LEDFF <= DATAO[15:0];
+ end
+
+ if(WR&&DADDR[31]&&DADDR[3:0]==4'b1010)
+ begin
+ GPIOFF <= DATAO[31:16];
+ end
+
+ if(RES)
+ TIMERFF <= (`BOARD_CK/1000000)-1; // timer set to 1MHz by default
+ else
+ if(WR&&DADDR[31]&&DADDR[3:0]==4'b1100)
+ begin
+ TIMERFF <= DATAO[31:0];
+ end
+
+ if(RES)
+ IACK <= 0;
+ else
+ if(WR&&DADDR[31]&&DADDR[3:0]==4'b0011)
+ begin
+ //$display("clear io.irq = %x (ireq=%x, iack=%x)",DATAO[32:24],IREQ,IACK);
+
+ IACK[7] <= DATAO[7+24] ? IREQ[7] : IACK[7];
+ IACK[6] <= DATAO[6+24] ? IREQ[6] : IACK[6];
+ IACK[5] <= DATAO[5+24] ? IREQ[5] : IACK[5];
+ IACK[4] <= DATAO[4+24] ? IREQ[4] : IACK[4];
+ IACK[3] <= DATAO[3+24] ? IREQ[3] : IACK[3];
+ IACK[2] <= DATAO[2+24] ? IREQ[2] : IACK[2];
+ IACK[1] <= DATAO[1+24] ? IREQ[1] : IACK[1];
+ IACK[0] <= DATAO[0+24] ? IREQ[0] : IACK[0];
+ end
+
+ if(RES)
+ IREQ <= 0;
+ else
+ if(TIMERFF)
+ begin
+ TIMER <= TIMER ? TIMER-1 : TIMERFF;
+
+ if(TIMER==0 && IREQ==IACK)
+ begin
+ IREQ[7] <= !IACK[7];
+
+ //$display("timr0 set");
+ end
+
+ XTIMER <= XTIMER+(TIMER==0);
+ end
+ end
+
+ assign BOARD_IRQ = IREQ^IACK;
+
+ assign HLT = !IHIT||!DHIT||!WHIT;
+
+ // darkuart
+
+ wire [3:0] UDEBUG;
+
+ darkuart
+// #(
+// .BAUD((`BOARD_CK/115200))
+// )
+ uart0
+ (
+ .CLK(CLK),
+ .RES(RES),
+ .RD(!HLT&&RD&&DADDR[31]&&DADDR[3:2]==1),
+ .WR(!HLT&&WR&&DADDR[31]&&DADDR[3:2]==1),
+ .BE(BE),
+ .DATAI(DATAO),
+ .DATAO(IOMUX[1]),
+ //.IRQ(BOARD_IRQ[1]),
+ .RXD(UART_RXD),
+ .TXD(UART_TXD),
+ .DEBUG(UDEBUG)
+ );
+
+ // darkriscv
+
+ wire [3:0] KDEBUG;
+
+ darkriscv
+// #(
+// .RESET_PC(32'h00000000),
+// .RESET_SP(32'h00002000)
+// )
+ core0
+ (
+`ifdef __3STAGE__
+ .CLK(CLK),
+`else
+ .CLK(!CLK),
+`endif
+ .RES(RES),
+ .HLT(HLT),
+`ifdef __THREADING__
+ .IREQ(|(IREQ^IACK)),
+`endif
+ .IDATA(IDATA),
+ .IADDR(IADDR),
+ .DADDR(DADDR),
+
+`ifdef __FLEXBUZZ__
+ .DATAI(XATAI),
+ .DATAO(XATAO),
+ .DLEN(DLEN),
+ .RW(RW),
+`else
+ .DATAI(DATAI),
+ .DATAO(DATAO),
+ .BE(BE),
+ .WR(WR),
+ .RD(RD),
+`endif
+
+ .DEBUG(KDEBUG)
+ );
+
+`ifdef __ICARUS__
+ initial
+ begin
+ $dumpfile("darksocv.vcd");
+ $dumpvars();
+ end
+`endif
+
+ assign LED = LEDFF[3:0];
+
+ assign DEBUG = { GPIOFF[0], XTIMER, WR, RD }; // UDEBUG;
+
+endmodule
\ No newline at end of file
Index: darkriscv/trunk/rtl/darkuart.v
===================================================================
--- darkriscv/trunk/rtl/darkuart.v (nonexistent)
+++ darkriscv/trunk/rtl/darkuart.v (revision 2)
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+`timescale 1ns / 1ps
+`include "../rtl/config.vh"
+
+// the following defines are automatically defined:
+/*
+`ifdef __ICARUS__
+ `define SIMULATION 1
+`endif
+
+`ifdef XILINX_ISIM
+ `define SIMULATION 2
+`endif
+
+`ifdef MODEL_TECH
+ `define SIMULATION 3
+`endif
+
+`ifdef XILINX_SIMULATOR
+ `define SIMULATION 4
+`endif
+*/
+// uart states
+
+`define UART_STATE_IDLE 6
+`define UART_STATE_START 7
+`define UART_STATE_DATA0 8
+`define UART_STATE_DATA1 9
+`define UART_STATE_DATA2 10
+`define UART_STATE_DATA3 11
+`define UART_STATE_DATA4 12
+`define UART_STATE_DATA5 13
+`define UART_STATE_DATA6 14
+`define UART_STATE_DATA7 15
+`define UART_STATE_STOP 0
+`define UART_STATE_ACK 1
+
+// UART registers
+//
+// 0: status register ro, 1 = xmit busy, 2 = recv busy
+// 1: buffer register rw, w = xmit fifo, r = recv fifo
+// 2: baud rate msb rw (not used)
+// 3: baud rate lsb rw (not used)
+
+module darkuart
+//#(
+// parameter [15:0] BAUD = 0
+//)
+(
+ input CLK, // clock
+ input RES, // reset
+
+ input RD, // bus read
+ input WR, // bus write
+ input [ 3:0] BE, // byte enable
+ input [31:0] DATAI, // data input
+ output [31:0] DATAO, // data output
+ output IRQ, // interrupt req
+
+ input RXD, // UART recv line
+ output TXD, // UART xmit line
+
+ output [3:0] DEBUG // osc debug
+);
+
+ reg [15:0] UART_TIMER = `__BAUD__; // baud rate from config.vh
+ reg UART_IREQ = 0; // UART interrupt req
+ reg UART_IACK = 0; // UART interrupt ack
+
+ reg [ 7:0] UART_XFIFO = 0; // UART TX FIFO
+ reg UART_XREQ = 0; // xmit request (core side)
+ reg UART_XACK = 0; // xmit ack (uart side)
+ reg [15:0] UART_XBAUD = 0; // baud rate counter
+ reg [ 3:0] UART_XSTATE= 0; // idle state
+
+ reg [ 7:0] UART_RFIFO = 0; // UART RX FIFO
+ reg UART_RREQ = 0; // request (uart side)
+ reg UART_RACK = 0; // ack (core side)
+ reg [15:0] UART_RBAUD = 0; // baud rate counter
+ reg [ 3:0] UART_RSTATE= 0; // idle state
+
+ reg [2:0] UART_RXDFF = -1;
+
+ wire [7:0] UART_STATE = { 6'd0, UART_RREQ^UART_RACK, UART_XREQ^UART_XACK };
+
+ reg [7:0] UART_STATEFF = 0;
+
+ // bus interface
+
+ reg [31:0] DATAOFF = 0;
+
+ always@(posedge CLK)
+ begin
+ if(WR)
+ begin
+ if(BE[1])
+ begin
+ UART_XFIFO <= DATAI[15:8];
+`ifdef SIMULATION
+ // print the UART output to console! :)
+ if(DATAI[15:8]!=13) // remove the '\r'
+ begin
+ $write("%c",DATAI[15:8]);
+ end
+
+ if(DATAI[15:8]=="#") // break point
+ begin
+ $display("[checkpoint #]");
+ $stop();
+ end
+
+ if(DATAI[15:8]==">") // prompt '>'
+ begin
+ $display(" no UART input, finishing simulation...");
+ $finish();
+ end
+`else
+ UART_XREQ <= !UART_XACK; // activate UART!
+`endif
+ end
+ //if(BE[2]) UART_TIMER[ 7:0] <= DATAI[23:16];
+ //if(BE[3]) UART_TIMER[15:8] <= DATAI[31:24];
+ end
+
+ if(RES)
+ begin
+ UART_RACK <= UART_RREQ;
+ UART_STATEFF <= UART_STATE;
+ end
+ else
+ if(RD)
+ begin
+ if(BE[1]) UART_RACK <= UART_RREQ; // fifo ready
+ if(BE[0]) UART_STATEFF <= UART_STATE; // state update, clear irq
+ end
+ end
+
+ assign IRQ = |(UART_STATE^UART_STATEFF);
+
+ assign DATAO = { UART_TIMER, UART_RFIFO, UART_STATE };
+
+ // xmit path: 6(IDLE), 7(START), 8, 9, 10, 11, 12, 13, 14, 15, 0(STOP), 1(ACK)
+
+ always@(posedge CLK)
+ begin
+ UART_XBAUD <= UART_XSTATE==`UART_STATE_IDLE ? UART_TIMER : // xbaud=timer
+ UART_XBAUD ? UART_XBAUD-1 : UART_TIMER; // while() { while(xbaud--); xbaud=timer }
+
+ UART_XSTATE <= RES||UART_XSTATE==`UART_STATE_ACK ? `UART_STATE_IDLE :
+ UART_XSTATE==`UART_STATE_IDLE ? UART_XSTATE+(UART_XREQ^UART_XACK) :
+ UART_XSTATE+(UART_XBAUD==0);
+
+ UART_XACK <= RES||UART_XSTATE==`UART_STATE_ACK ? UART_XREQ : UART_XACK;
+ end
+
+ assign TXD = UART_XSTATE[3] ? UART_XFIFO[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
+
+ // recv path: 6(IDLE), 7(START), 8, 9, 10, 11, 12, 13, 14, 15, 0(STOP), 1(ACK)
+
+ always@(posedge CLK)
+ begin
+ UART_RXDFF <= (UART_RXDFF<<1)|RXD;
+
+ UART_RBAUD <= UART_RSTATE==`UART_STATE_IDLE ? { 1'b0, UART_TIMER[15:1] } : // rbaud=timer/2
+ UART_RBAUD ? UART_RBAUD-1 : UART_TIMER; // while() { while(rbaud--); rbaud=timer }
+
+
+ UART_RSTATE <= RES||UART_RSTATE==`UART_STATE_ACK ? `UART_STATE_IDLE :
+ UART_RSTATE==`UART_STATE_IDLE ? UART_RSTATE+(UART_RXDFF[2:1]==2'b10) : // start bit detection
+ UART_RSTATE+(UART_RBAUD==0);
+
+ UART_RREQ <= UART_RSTATE==`UART_STATE_ACK ? !UART_RACK : UART_RREQ;
+
+ if(UART_RSTATE[3])
+ begin
+ UART_RFIFO[UART_RSTATE[2:0]] <= UART_RXDFF[2];
+ end
+ end
+
+ //debug
+
+ assign DEBUG = { RXD, TXD, UART_XSTATE!=`UART_STATE_IDLE, UART_RSTATE!=`UART_STATE_IDLE };
+
+endmodule
Index: darkriscv/trunk/sim/Makefile
===================================================================
--- darkriscv/trunk/sim/Makefile (nonexistent)
+++ darkriscv/trunk/sim/Makefile (revision 2)
@@ -0,0 +1,57 @@
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+## Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+## Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+## Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ifndef ICARUS
+ ICARUS = iverilog
+endif
+
+RTLS = darksimv.v ../rtl/darksocv.v ../rtl/darkuart.v ../rtl/darkriscv.v
+INCS = ../rtl/config.vh
+XSIM = darksocv
+VCDS = darksocv.vcd
+
+ifdef HARVARD
+ SRCS = ../src/darksocv.rom.mem ../src/darksocv.ram.mem
+else
+ SRCS = ../src/darksocv.mem
+endif
+
+DEPS = $(SRCS) $(RTLS) $(INCS)
+
+all: $(VCDS)
+ echo simulation ok.
+
+clean:
+ -rm $(VCDS) $(XSIM)
+
+$(VCDS): $(XSIM)
+ ./$(XSIM)
+
+
+$(XSIM): $(DEPS)
+ $(ICARUS) -I ../rtl -o $(XSIM) $(RTLS)
Index: darkriscv/trunk/sim/README.md
===================================================================
--- darkriscv/trunk/sim/README.md (nonexistent)
+++ darkriscv/trunk/sim/README.md (revision 2)
@@ -0,0 +1,9 @@
+## Simulation
+
+This directory provides support for simulation tools.
+
+The main simulation tool is the opensource tools Icarus Verilog and the
+gtkWave. Alternatively, it is possible use proprietary simulation tools, as
+the Xilinx ISIM and ModelSIM.
+
+TODO: simulation models for external peripherals, such as the DarkUART.
Index: darkriscv/trunk/sim/darksimv.v
===================================================================
--- darkriscv/trunk/sim/darksimv.v (nonexistent)
+++ darkriscv/trunk/sim/darksimv.v (revision 2)
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+`timescale 1ns / 1ps
+`include "../rtl/config.vh"
+
+// clock and reset logic
+
+module darksimv;
+
+ reg CLK = 0;
+
+ reg RES = 1;
+
+ initial while(1) #(500e6/`BOARD_CK) CLK = !CLK; // clock generator w/ freq defined by config.vh
+
+ initial
+ begin
+ $display("reset (startup)");
+ #1e3 RES = 0; // wait 1us in reset state
+ //#1000e3 RES = 1; // run 1ms
+ //$display("reset (restart)");
+ //#1e3 RES = 0; // wait 1us in reset state
+ //#1000e3 $finish(); // run 1ms
+ end
+
+ wire TX;
+ wire RX = 1;
+
+ darksocv darksocv
+ (
+ .XCLK(CLK),
+ .XRES(|RES),
+ .UART_RXD(RX),
+ .UART_TXD(TX)
+ );
+
+endmodule
Index: darkriscv/trunk/src/include/io.h
===================================================================
--- darkriscv/trunk/src/include/io.h (nonexistent)
+++ darkriscv/trunk/src/include/io.h (revision 2)
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IO__
+#define __IO__
+
+extern volatile int threads; // number of threads in the core
+extern volatile int utimers; // microsecond timer
+
+struct DARKIO {
+
+ unsigned char board_id; // 00
+ unsigned char board_cm; // 01
+ unsigned char board_ck; // 02
+ unsigned char irq; // 03
+
+ struct DARKUART {
+
+ unsigned char stat; // 04
+ unsigned char fifo; // 05
+ unsigned short baud; // 06/07
+
+ } uart;
+
+ unsigned short led; // 08/09
+ unsigned short gpio; // 0a/0b
+
+ unsigned int timer; // 0c
+};
+
+extern volatile struct DARKIO io;
+
+extern char *board_name(int);
+
+#ifdef __RISCV__
+#define kmem 0
+#else
+extern unsigned char kmem[8192];
+#endif
+
+#define IRQ_TIMR 0x80
+#define IRQ_UART 0x02
+
+#endif
Index: darkriscv/trunk/src/include/stdio.h
===================================================================
--- darkriscv/trunk/src/include/stdio.h (nonexistent)
+++ darkriscv/trunk/src/include/stdio.h (revision 2)
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __STDIO__
+#define __STDIO__
+
+#define EOF -1
+#define NUL 0
+#define NULL (void *)0
+
+int getchar(void);
+int putchar(int c);
+char *gets(char *p,int s);
+void putstr(char *p);
+int puts(char *p);
+int printf(char *fmt,...);
+int strcmp(char *s1, char *s2);
+int strncmp(char *s1, char *s2, int len);
+int strlen(char *s1);
+void putx(unsigned);
+void putd(int);
+char *memcpy(char *dptr,char *sptr,int len);
+char *memset(char *dptr, int c, int len);
+char *strtok(char *str,char *dptr);
+int atoi(char *);
+int xtoi(char *);
+int mac(int,short,short);
+void usleep(int);
+
+#endif
Index: darkriscv/trunk/src/Makefile
===================================================================
--- darkriscv/trunk/src/Makefile (nonexistent)
+++ darkriscv/trunk/src/Makefile (revision 2)
@@ -0,0 +1,140 @@
+# Copyright (c) 2018, Marcelo Samsoniuk
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ifndef HOST_CC
+ HOST_CC = gcc
+ HOST_CFLAGS = -Wall -Wno-incompatible-library-redeclaration -I./include -Os
+endif
+
+ifndef CROSS
+
+ ARCH = rv32e
+ #ARCH = rv32i
+
+ #TODO: better way to switch little/big-endian:
+ #ENDIAN = _le # gcc for little-endian
+ #ENDIAN = _be # gcc for big-endian
+
+ CROSS = riscv32-embedded$(ENDIAN)-elf
+ #CROSS = riscv-elf
+ #CROSS = riscv32-unknown-elf
+ #CROSS = riscv32-embedded-elf
+
+ CCPATH = /usr/local/share/gcc-$(CROSS)/bin/
+ #CCPATH = /usr/local/share/toolchain-$(CROSS)/bin
+ HARVARD = 1
+endif
+
+ifndef BUILD
+ BUILD = $(shell date -R)
+endif
+
+ CC = $(CCPATH)/$(CROSS)-gcc
+ AS = $(CCPATH)/$(CROSS)-as
+ LD = $(CCPATH)/$(CROSS)-ld
+ OC = $(CCPATH)/$(CROSS)-objcopy
+ OD = $(CCPATH)/$(CROSS)-objdump
+ CPP = $(CCPATH)/$(CROSS)-cpp
+
+CCFLAGS = -Wall -I./include -Os -march=$(ARCH) -mabi=ilp32e -D__RISCV__ -DBUILD="\"$(BUILD)\"" -DARCH="\"$(ARCH)\""
+ASFLAGS = -march=$(ARCH)
+LDFLAGS = -T$(PROJ).ld -Map=$(PROJ).map -m elf32lriscv # -Ttext=0
+CPFLAGS = -P
+
+#CCFLAGS += -mcmodel=medany -mexplicit-relocs # relocable clode
+
+ifdef HARVARD
+ CPFLAGS += -DHARVARD=1
+endif
+
+OCFLAGS = -O binary # --reverse-bytes=4 # workaround for darkriscv big-endian blockrams
+ODFLAGS = -d
+
+PROJ = darksocv
+OBJS = boot.o stdio.o main.o io.o banner.o
+ASMS = boot.s stdio.s main.s io.s banner.s
+SRCS = boot.c stdio.c main.c io.c banner.c
+
+#include app/Makefile.in
+
+DEPS = $(SRCS) $(ASMS) $(OBJS) $(PROJ).ld $(PROJ).ld.src
+
+ifdef HARVARD
+ TARGETS = $(PROJ).rom.mem $(PROJ).ram.mem
+else
+ TARGETS = $(PROJ).mem
+endif
+
+.PHONY: all
+
+all: $(TARGETS) $(DEPS)
+ echo sources ok.
+
+clean:
+ -rm *.s *.o $(PROJ).{bin,lst,map,ram,rom,x86,text,data,bin,ld}
+
+%.o: %.s
+ $(AS) $(ASFLAGS) -c $< -o $@
+
+%.s: %.c
+ $(CC) $(CCFLAGS) -S $< -o $@
+
+$(PROJ).ld: $(PROJ).ld.src
+ $(CPP) $(CPFLAGS) $(PROJ).ld.src $(PROJ).ld
+
+$(PROJ).o: $(OBJS) $(PROJ).ld
+ $(LD) $(LDFLAGS) $(OBJS) -o $@
+ $(OD) $(ODFLAGS) $@ > $(PROJ).lst
+
+$(PROJ).rom.mem: $(PROJ).o
+ $(OC) $(OCFLAGS) $< $(PROJ).text --only-section .text*
+ hexdump -ve '1/4 "%08x\n"' $(PROJ).text > $@
+ #xxd -p -c 4 -g 4 $< > $@
+ rm $(PROJ).text
+ wc -l $@
+ echo rom ok.
+
+$(PROJ).ram.mem: $(PROJ).o
+ $(OC) $(OCFLAGS) $< $(PROJ).data --only-section .*data*
+ hexdump -ve '1/4 "%08x\n"' $(PROJ).data > $@
+ #xxd -p -c 4 -g 4 $< > $@
+ rm $(PROJ).data
+ wc -l $@
+ echo ram ok.
+
+$(PROJ).mem: $(PROJ).o
+ $(OC) $(OCFLAGS) $< $(PROJ).bin
+ hexdump -ve '1/4 "%08x\n"' $(PROJ).bin > $@
+ #xxd -p -c 4 -g 4 $< > $@
+ rm $(PROJ).bin
+ wc -l $@
+ echo mem ok.
+
+$(PROJ).x86: $(SRCS)
+ $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\""
+ echo x86 ok.
Index: darkriscv/trunk/src/README.md
===================================================================
--- darkriscv/trunk/src/README.md (nonexistent)
+++ darkriscv/trunk/src/README.md (revision 2)
@@ -0,0 +1,15 @@
+## Software
+
+This directory provides support for DarkRISCV software.
+
+The software is 100% written in C language, is compiled by the GCC and lots
+of support files (elf, assembler, maps, etc) are produced in order to help
+debug and/or study the RISCV architecture.
+
+TODO:
+
+- add a gdb-stub in order to support UART debug
+- add a SREC decoder in order to support application upload via UART
+- split the "stdio" in other files
+- add more libc features and optimize the existing features
+
Index: darkriscv/trunk/src/banner.c
===================================================================
--- darkriscv/trunk/src/banner.c (nonexistent)
+++ darkriscv/trunk/src/banner.c (revision 2)
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define RLE 1
+
+#include
+
+void banner(void)
+{
+#ifndef RLE
+
+ // https://github.com/riscv/riscv-pk/blob/master/bbl/riscv_logo.txt
+ // https://github.com/riscv/riscv-pk/blob/master/LICENSE.riscv_logo.txt
+ // Copyright (C) 2015 Andrew Waterman
+
+ char *logo =
+
+ " vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv\n"
+ " vvvvvvvvvvvvvvvvvvvvvvvvvvvv\n"
+ "rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvvvv\n"
+ "rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv\n"
+ "rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv\n"
+ "rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv\n"
+ "rrrrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvvvv\n"
+ "rrrrrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv \n"
+ "rrrrrrrrrrrrr vvvvvvvvvvvvvvvvvvvvvv \n"
+ "rr vvvvvvvvvvvvvvvvvvvvvv \n"
+ "rr vvvvvvvvvvvvvvvvvvvvvvvv rr\n"
+ "rrrr vvvvvvvvvvvvvvvvvvvvvvvvvv rrrr\n"
+ "rrrrrr vvvvvvvvvvvvvvvvvvvvvv rrrrrr\n"
+ "rrrrrrrr vvvvvvvvvvvvvvvvvv rrrrrrrr\n"
+ "rrrrrrrrrr vvvvvvvvvvvvvv rrrrrrrrrr\n"
+ "rrrrrrrrrrrr vvvvvvvvvv rrrrrrrrrrrr\n"
+ "rrrrrrrrrrrrrr vvvvvv rrrrrrrrrrrrrr\n"
+ "rrrrrrrrrrrrrrrr vv rrrrrrrrrrrrrrrr\n"
+ "rrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrr\n"
+ "rrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrr\n"
+ "rrrrrrrrrrrrrrrrrrrrrr rrrrrrrrrrrrrrrrrrrrrr\n"
+ "\n"
+ " INSTRUCTION SETS WANT TO BE FREE\n\n";
+
+ // rle compressor: 1030 to 269 bytes! +_+
+
+ register int xc=0,xs=0,xp;
+
+ printf(" char rle_logo[] = {\n");
+
+ for(xp=0;;xp++)
+ {
+ if(xc!=logo[xp])
+ {
+ if(xc)
+ {
+ printf("0x%x, 0x%x, ",xc,xs);
+ }
+ xs=1;
+ if(!(xc=logo[xp])) break;
+ }
+ else xs++;
+ }
+
+ printf("0x00 };\n");
+
+#else
+
+ char rle_logo[] = {
+ 0x20, 0x0e, 0x76, 0x20, 0x0a, 0x01, 0x20, 0x12, 0x76, 0x1c, 0x0a,
+ 0x01, 0x72, 0x0d, 0x20, 0x07, 0x76, 0x1a, 0x0a, 0x01, 0x72, 0x10,
+ 0x20, 0x06, 0x76, 0x18, 0x0a, 0x01, 0x72, 0x12, 0x20, 0x04, 0x76,
+ 0x18, 0x0a, 0x01, 0x72, 0x12, 0x20, 0x04, 0x76, 0x18, 0x0a, 0x01,
+ 0x72, 0x12, 0x20, 0x04, 0x76, 0x18, 0x0a, 0x01, 0x72, 0x10, 0x20,
+ 0x06, 0x76, 0x16, 0x20, 0x02, 0x0a, 0x01, 0x72, 0x0d, 0x20, 0x07,
+ 0x76, 0x16, 0x20, 0x04, 0x0a, 0x01, 0x72, 0x02, 0x20, 0x10, 0x76,
+ 0x16, 0x20, 0x06, 0x0a, 0x01, 0x72, 0x02, 0x20, 0x0c, 0x76, 0x18,
+ 0x20, 0x06, 0x72, 0x02, 0x0a, 0x01, 0x72, 0x04, 0x20, 0x06, 0x76,
+ 0x1a, 0x20, 0x06, 0x72, 0x04, 0x0a, 0x01, 0x72, 0x06, 0x20, 0x06,
+ 0x76, 0x16, 0x20, 0x06, 0x72, 0x06, 0x0a, 0x01, 0x72, 0x08, 0x20,
+ 0x06, 0x76, 0x12, 0x20, 0x06, 0x72, 0x08, 0x0a, 0x01, 0x72, 0x0a,
+ 0x20, 0x06, 0x76, 0x0e, 0x20, 0x06, 0x72, 0x0a, 0x0a, 0x01, 0x72,
+ 0x0c, 0x20, 0x06, 0x76, 0x0a, 0x20, 0x06, 0x72, 0x0c, 0x0a, 0x01,
+ 0x72, 0x0e, 0x20, 0x06, 0x76, 0x06, 0x20, 0x06, 0x72, 0x0e, 0x0a,
+ 0x01, 0x72, 0x10, 0x20, 0x06, 0x76, 0x02, 0x20, 0x06, 0x72, 0x10,
+ 0x0a, 0x01, 0x72, 0x12, 0x20, 0x0a, 0x72, 0x12, 0x0a, 0x01, 0x72,
+ 0x14, 0x20, 0x06, 0x72, 0x14, 0x0a, 0x01, 0x72, 0x16, 0x20, 0x02,
+ 0x72, 0x16, 0x0a, 0x02, 0x20, 0x07, 0x49, 0x01, 0x4e, 0x01, 0x53,
+ 0x01, 0x54, 0x01, 0x52, 0x01, 0x55, 0x01, 0x43, 0x01, 0x54, 0x01,
+ 0x49, 0x01, 0x4f, 0x01, 0x4e, 0x01, 0x20, 0x01, 0x53, 0x01, 0x45,
+ 0x01, 0x54, 0x01, 0x53, 0x01, 0x20, 0x01, 0x57, 0x01, 0x41, 0x01,
+ 0x4e, 0x01, 0x54, 0x01, 0x20, 0x01, 0x54, 0x01, 0x4f, 0x01, 0x20,
+ 0x01, 0x42, 0x01, 0x45, 0x01, 0x20, 0x01, 0x46, 0x01, 0x52, 0x01,
+ 0x45, 0x02, 0x0a, 0x02, 0x00 };
+
+ //printf("\33[H\33[2J");
+ putchar('\n');
+
+ register int c,s;
+ register char *p = rle_logo;
+
+ while(*p)
+ {
+ c = *p++;
+ s = *p++;
+
+ while(s--) putchar(c);
+ }
+
+#endif
+}
Index: darkriscv/trunk/src/banner.s
===================================================================
--- darkriscv/trunk/src/banner.s (nonexistent)
+++ darkriscv/trunk/src/banner.s (revision 2)
@@ -0,0 +1,46 @@
+ .file "banner.c"
+ .option nopic
+ .text
+ .align 2
+ .globl banner
+ .type banner, @function
+banner:
+ addi sp,sp,-288
+ lui a1,%hi(.LC0)
+ li a2,269
+ addi a1,a1,%lo(.LC0)
+ addi a0,sp,4
+ sw ra,284(sp)
+ sw s0,280(sp)
+ sw s1,276(sp)
+ call memcpy
+ li a0,10
+ call putchar
+ addi s0,sp,4
+.L2:
+ lbu a5,0(s0)
+ bnez a5,.L5
+ lw ra,284(sp)
+ lw s0,280(sp)
+ lw s1,276(sp)
+ addi sp,sp,288
+ jr ra
+.L5:
+ addi s0,s0,2
+ lbu s1,-1(s0)
+.L3:
+ addi s1,s1,-1
+ li a4,-1
+ beq s1,a4,.L2
+ mv a0,a5
+ sw a5,0(sp)
+ call putchar
+ lw a5,0(sp)
+ j .L3
+ .size banner, .-banner
+ .section .rodata.str1.4,"aMS",@progbits,1
+ .align 2
+.LC0:
+ .ascii " \016v \n\001 \022v\034\n\001"
+ .string "r\r \007v\032\n\001r\020 \006v\030\n\001r\022 \004v\030\n\001r\022 \004v\030\n\001r\022 \004v\030\n\001r\020 \006v\026 \002\n\001r\r \007v\026 \004\n\001r\002 \020v\026 \006\n\001r\002 \fv\030 \006r\002\n\001r\004 \006v\032 \006r\004\n\001r\006 \006v\026 \006r\006\n\001r\b \006v\022 \006r\b\n\001r\n \006v\016 \006r\n\n\001r\f \006v\n \006r\f\n\001r\016 \006v\006 \006r\016\n\001r\020 \006v\002 \006r\020\n\001r\022 \nr\022\n\001r\024 \006r\024\n\001r\026 \002r\026\n\002 \007I\001N\001S\001T\001R\001U\001C\001T\001I\001O\001N\001 \001S\001E\001T\001S\001 \001W\001A\001N\001T\001 \001T\001O\001 \001B\001E\001 \001F\001R\001E\002\n\002"
+ .ident "GCC: (GNU) 9.0.0 20180818 (experimental)"
Index: darkriscv/trunk/src/boot.c
===================================================================
--- darkriscv/trunk/src/boot.c (nonexistent)
+++ darkriscv/trunk/src/boot.c (revision 2)
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+
+extern int banner(void);
+extern int main (void);
+
+void boot(void)
+{
+ int tmp = 1&threads++;
+
+ io.irq = IRQ_TIMR; // clear interrupt
+
+ // thread #0
+
+ if(tmp==0)
+ {
+ while(1)
+ {
+ banner();
+
+ printf("boot0: text@%d data@%d stack@%d\n",
+ (unsigned int)boot,
+ (unsigned int)&utimers,
+ (unsigned int)&tmp+16);
+
+ main();
+ }
+ }
+
+ // thread #1
+
+ while(1)
+ {
+ if(!utimers--)
+ {
+ io.led++;
+ utimers=999999;
+ }
+
+ io.irq = IRQ_TIMR; // clear interrupts and switch context
+ }
+}
Index: darkriscv/trunk/src/boot.s
===================================================================
--- darkriscv/trunk/src/boot.s (nonexistent)
+++ darkriscv/trunk/src/boot.s (revision 2)
@@ -0,0 +1,58 @@
+ .file "boot.c"
+ .option nopic
+ .text
+ .align 2
+ .globl boot
+ .type boot, @function
+boot:
+ lui a5,%hi(threads)
+ lw a4,%lo(threads)(a5)
+ addi sp,sp,-16
+ sw s0,8(sp)
+ addi a3,a4,1
+ sw a3,%lo(threads)(a5)
+ lui a5,%hi(io)
+ sw ra,12(sp)
+ sw s1,4(sp)
+ andi a4,a4,1
+ addi a3,a5,%lo(io)
+ li a2,-128
+ sw a4,0(sp)
+ sb a2,3(a3)
+ lui s0,%hi(utimers)
+ beqz a4,.L6
+ li a3,999424
+ addi a5,a5,%lo(io)
+ addi a3,a3,575
+.L2:
+ lw a4,%lo(utimers)(s0)
+ addi a1,a4,-1
+ sw a1,%lo(utimers)(s0)
+ bnez a4,.L4
+ lhu a4,8(a5)
+ addi a4,a4,1
+ slli a4,a4,16
+ srli a4,a4,16
+ sh a4,8(a5)
+ sw a3,%lo(utimers)(s0)
+.L4:
+ sb a2,3(a5)
+ j .L2
+.L6:
+ lui s1,%hi(boot)
+.L3:
+ call banner
+ lui a0,%hi(.LC0)
+ addi a3,sp,16
+ addi a2,s0,%lo(utimers)
+ addi a1,s1,%lo(boot)
+ addi a0,a0,%lo(.LC0)
+ call printf
+ call main
+ j .L3
+ .size boot, .-boot
+ .section .rodata.str1.4,"aMS",@progbits,1
+ .align 2
+.LC0:
+ .string "boot0: text@%d data@%d stack@%d\n"
+ .ident "GCC: (GNU) 9.0.0 20180818 (experimental)"
Index: darkriscv/trunk/src/darksocv.ld
===================================================================
--- darkriscv/trunk/src/darksocv.ld (nonexistent)
+++ darkriscv/trunk/src/darksocv.ld (revision 2)
@@ -0,0 +1,27 @@
+MEMORY
+{
+ IO (rw!x) : ORIGIN = 0x80000000, LENGTH = 0x10
+ ROM (x!rw) : ORIGIN = 0x00000000, LENGTH = 0x1000
+ RAM (rw!x) : ORIGIN = 0x00001000, LENGTH = 0x1000
+}
+SECTIONS
+{
+ .io :
+ {
+ io.o(COMMON)
+ } > IO
+ .text :
+ {
+ boot.o(.text)
+ *(.text)
+ } > ROM
+ .data :
+ {
+ *(.sbss)
+ *(.rodata*)
+ *(.data)
+ *(.bss)
+ *(.rela*)
+ *(COMMON)
+ } > RAM
+}
Index: darkriscv/trunk/src/darksocv.ld.src
===================================================================
--- darkriscv/trunk/src/darksocv.ld.src (nonexistent)
+++ darkriscv/trunk/src/darksocv.ld.src (revision 2)
@@ -0,0 +1,89 @@
+/* Copyright (c) 2018, Marcelo Samsoniuk
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ Memory Architectures:
+
+ - Harvard: separate instruction (ROM) and data (RAM), has the
+ advantage that is possible make the ROM memory readonly, in a way
+ that bugs in the code cannot destruct the code. Also, the use of
+ separate ROM and RAM makes possible share the dual-port ROM and/or
+ RAM between two cores.
+
+ - Von Neumann: unified instruction and data in a single memory
+ (MEM), has the advantage that the .text and .data are contigous
+ and without gaps, which means that the memory is better utilized.
+ However, as long there is no physical separation, a bug in the
+ code can destroy both data and code. Also, as long both ports of
+ the dual-port MEM is already in use, there is no way to share to
+ more than one core.
+*/
+
+MEMORY
+{
+ IO (rw!x) : ORIGIN = 0x80000000, LENGTH = 0x10
+#if HARVARD
+ ROM (x!rw) : ORIGIN = 0x00000000, LENGTH = 0x1000
+ RAM (rw!x) : ORIGIN = 0x00001000, LENGTH = 0x1000
+#else
+ MEM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x2000
+#endif
+}
+
+SECTIONS
+{
+ .io :
+ {
+ io.o(COMMON)
+
+ } > IO
+
+ .text :
+ {
+ boot.o(.text)
+ *(.text)
+#if HARVARD
+ } > ROM
+#else
+ } > MEM
+#endif
+ .data :
+ {
+ *(.sbss)
+ *(.rodata*)
+ *(.data)
+ *(.bss)
+ *(.rela*)
+ *(COMMON)
+#if HARVARD
+ } > RAM
+#else
+ } > MEM
+#endif
+}
Index: darkriscv/trunk/src/darksocv.lst
===================================================================
--- darkriscv/trunk/src/darksocv.lst (nonexistent)
+++ darkriscv/trunk/src/darksocv.lst (revision 2)
@@ -0,0 +1,978 @@
+
+darksocv.o: file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+00000000 :
+ 0: 000017b7 lui a5,0x1
+ 4: 0047a703 lw a4,4(a5) # 1004
+ 8: ff010113 addi sp,sp,-16
+ c: 00812423 sw s0,8(sp)
+ 10: 00170693 addi a3,a4,1
+ 14: 00d7a223 sw a3,4(a5)
+ 18: 800007b7 lui a5,0x80000
+ 1c: 00112623 sw ra,12(sp)
+ 20: 00912223 sw s1,4(sp)
+ 24: 00177713 andi a4,a4,1
+ 28: 00078693 mv a3,a5
+ 2c: f8000613 li a2,-128
+ 30: 00e12023 sw a4,0(sp)
+ 34: 00c681a3 sb a2,3(a3)
+ 38: 00001437 lui s0,0x1
+ 3c: 04070063 beqz a4,7c
+ 40: 000f46b7 lui a3,0xf4
+ 44: 00078793 mv a5,a5
+ 48: 23f68693 addi a3,a3,575 # f423f
+ 4c: 00042703 lw a4,0(s0) # 1000
+ 50: fff70593 addi a1,a4,-1
+ 54: 00b42023 sw a1,0(s0)
+ 58: 00071e63 bnez a4,74
+ 5c: 0087d703 lhu a4,8(a5) # 80000008
+ 60: 00170713 addi a4,a4,1
+ 64: 01071713 slli a4,a4,0x10
+ 68: 01075713 srli a4,a4,0x10
+ 6c: 00e79423 sh a4,8(a5)
+ 70: 00d42023 sw a3,0(s0)
+ 74: 00c781a3 sb a2,3(a5)
+ 78: fd5ff06f j 4c
+ 7c: 000004b7 lui s1,0x0
+ 80: 001000ef jal ra,880
+ 84: 00001537 lui a0,0x1
+ 88: 01010693 addi a3,sp,16
+ 8c: 00040613 mv a2,s0
+ 90: 00048593 mv a1,s1
+ 94: 0ec50513 addi a0,a0,236 # 10ec
+ 98: 354000ef jal ra,3ec
+ 9c: 059000ef jal ra,8f4
+ a0: fe1ff06f j 80
+
+000000a4 :
+ a4: 04050c63 beqz a0,fc
+ a8: 00100793 li a5,1
+ ac: 04f50e63 beq a0,a5,108
+ b0: 00200793 li a5,2
+ b4: 06f50063 beq a0,a5,114
+ b8: 00300793 li a5,3
+ bc: 06f50263 beq a0,a5,120
+ c0: 00400793 li a5,4
+ c4: 06f50463 beq a0,a5,12c
+ c8: 00500793 li a5,5
+ cc: 06f50663 beq a0,a5,138
+ d0: 00600793 li a5,6
+ d4: 06f50863 beq a0,a5,144
+ d8: 00700793 li a5,7
+ dc: 06f50a63 beq a0,a5,150
+ e0: 00800793 li a5,8
+ e4: 06f50c63 beq a0,a5,15c
+ e8: 00900793 li a5,9
+ ec: 06f50e63 beq a0,a5,168
+ f0: 00001537 lui a0,0x1
+ f4: 0e450513 addi a0,a0,228 # 10e4
+ f8: 00008067 ret
+ fc: 00001537 lui a0,0x1
+ 100: 03850513 addi a0,a0,56 # 1038
+ 104: 00008067 ret
+ 108: 00001537 lui a0,0x1
+ 10c: 04850513 addi a0,a0,72 # 1048
+ 110: 00008067 ret
+ 114: 00001537 lui a0,0x1
+ 118: 06050513 addi a0,a0,96 # 1060
+ 11c: 00008067 ret
+ 120: 00001537 lui a0,0x1
+ 124: 07450513 addi a0,a0,116 # 1074
+ 128: 00008067 ret
+ 12c: 00001537 lui a0,0x1
+ 130: 08850513 addi a0,a0,136 # 1088
+ 134: 00008067 ret
+ 138: 00001537 lui a0,0x1
+ 13c: 09c50513 addi a0,a0,156 # 109c
+ 140: 00008067 ret
+ 144: 00001537 lui a0,0x1
+ 148: 0b450513 addi a0,a0,180 # 10b4
+ 14c: 00008067 ret
+ 150: 00001537 lui a0,0x1
+ 154: 02050513 addi a0,a0,32 # 1020
+ 158: 00008067 ret
+ 15c: 00001537 lui a0,0x1
+ 160: 0c850513 addi a0,a0,200 # 10c8
+ 164: 00008067 ret
+ 168: 00001537 lui a0,0x1
+ 16c: 00c50513 addi a0,a0,12 # 100c
+ 170: 00008067 ret
+
+00000174 :
+ 174: 800007b7 lui a5,0x80000
+ 178: 00078793 mv a5,a5
+ 17c: 0047c703 lbu a4,4(a5) # 80000004
+ 180: 00277713 andi a4,a4,2
+ 184: fe070ce3 beqz a4,17c
+ 188: 0057c503 lbu a0,5(a5)
+ 18c: 00008067 ret
+
+00000190 :
+ 190: 800007b7 lui a5,0x80000
+ 194: 00a00713 li a4,10
+ 198: 00078793 mv a5,a5
+ 19c: 00e51c63 bne a0,a4,1b4
+ 1a0: 0047c703 lbu a4,4(a5) # 80000004
+ 1a4: 00177713 andi a4,a4,1
+ 1a8: fe071ce3 bnez a4,1a0
+ 1ac: 00d00713 li a4,13
+ 1b0: 00e782a3 sb a4,5(a5)
+ 1b4: 0047c703 lbu a4,4(a5)
+ 1b8: 00177713 andi a4,a4,1
+ 1bc: fe071ce3 bnez a4,1b4
+ 1c0: 0ff57713 andi a4,a0,255
+ 1c4: 00e782a3 sb a4,5(a5)
+ 1c8: 00070513 mv a0,a4
+ 1cc: 00008067 ret
+
+000001d0 :
+ 1d0: fe810113 addi sp,sp,-24
+ 1d4: 00812823 sw s0,16(sp)
+ 1d8: 00912623 sw s1,12(sp)
+ 1dc: 00112a23 sw ra,20(sp)
+ 1e0: 00050493 mv s1,a0
+ 1e4: 00050413 mv s0,a0
+ 1e8: fff58713 addi a4,a1,-1
+ 1ec: 02070063 beqz a4,20c
+ 1f0: 00b12223 sw a1,4(sp)
+ 1f4: 00e12023 sw a4,0(sp)
+ 1f8: f7dff0ef jal ra,174
+ 1fc: 00a00693 li a3,10
+ 200: 00012703 lw a4,0(sp)
+ 204: 00412583 lw a1,4(sp)
+ 208: 02d51863 bne a0,a3,238
+ 20c: 00a00513 li a0,10
+ 210: f81ff0ef jal ra,190
+ 214: 00040023 sb zero,0(s0)
+ 218: 00941463 bne s0,s1,220
+ 21c: 00000493 li s1,0
+ 220: 01412083 lw ra,20(sp)
+ 224: 01012403 lw s0,16(sp)
+ 228: 00048513 mv a0,s1
+ 22c: 00c12483 lw s1,12(sp)
+ 230: 01810113 addi sp,sp,24
+ 234: 00008067 ret
+ 238: 00b12423 sw a1,8(sp)
+ 23c: 00e12223 sw a4,4(sp)
+ 240: 00d00693 li a3,13
+ 244: 00a12023 sw a0,0(sp)
+ 248: fcd502e3 beq a0,a3,20c
+ 24c: f45ff0ef jal ra,190
+ 250: 00012783 lw a5,0(sp)
+ 254: 00800693 li a3,8
+ 258: 00412703 lw a4,4(sp)
+ 25c: 00812583 lw a1,8(sp)
+ 260: 00d79e63 bne a5,a3,27c
+ 264: 00940863 beq s0,s1,274
+ 268: fe040fa3 sb zero,-1(s0)
+ 26c: 00058713 mv a4,a1
+ 270: fff40413 addi s0,s0,-1
+ 274: 00070593 mv a1,a4
+ 278: f71ff06f j 1e8
+ 27c: 00f40023 sb a5,0(s0)
+ 280: 00140413 addi s0,s0,1
+ 284: ff1ff06f j 274
+
+00000288 :
+ 288: ff410113 addi sp,sp,-12
+ 28c: 00812223 sw s0,4(sp)
+ 290: 00112423 sw ra,8(sp)
+ 294: 00050413 mv s0,a0
+ 298: 00051663 bnez a0,2a4
+ 29c: 00001437 lui s0,0x1
+ 2a0: 15040413 addi s0,s0,336 # 1150
+ 2a4: 00044503 lbu a0,0(s0)
+ 2a8: 00051a63 bnez a0,2bc
+ 2ac: 00812083 lw ra,8(sp)
+ 2b0: 00412403 lw s0,4(sp)
+ 2b4: 00c10113 addi sp,sp,12
+ 2b8: 00008067 ret
+ 2bc: 00140413 addi s0,s0,1
+ 2c0: ed1ff0ef jal ra,190
+ 2c4: fe1ff06f j 2a4
+
+000002c8 :
+ 2c8: ff410113 addi sp,sp,-12
+ 2cc: 00112423 sw ra,8(sp)
+ 2d0: fb9ff0ef jal ra,288
+ 2d4: 00812083 lw ra,8(sp)
+ 2d8: 00a00513 li a0,10
+ 2dc: 00c10113 addi sp,sp,12
+ 2e0: eb1ff06f j 190
+
+000002e4 :
+ 2e4: fac10113 addi sp,sp,-84
+ 2e8: 00b12023 sw a1,0(sp)
+ 2ec: 000015b7 lui a1,0x1
+ 2f0: 04812623 sw s0,76(sp)
+ 2f4: 04912423 sw s1,72(sp)
+ 2f8: 02c00613 li a2,44
+ 2fc: 11058493 addi s1,a1,272 # 1110
+ 300: 00050413 mv s0,a0
+ 304: 11058593 addi a1,a1,272
+ 308: 01c10513 addi a0,sp,28
+ 30c: 04112823 sw ra,80(sp)
+ 310: 210000ef jal ra,520
+ 314: 01400613 li a2,20
+ 318: 02c48593 addi a1,s1,44 # 2c
+ 31c: 00810513 addi a0,sp,8
+ 320: 200000ef jal ra,520
+ 324: 00012703 lw a4,0(sp)
+ 328: 00810793 addi a5,sp,8
+ 32c: 00070463 beqz a4,334
+ 330: 01c10793 addi a5,sp,28
+ 334: 01800493 li s1,24
+ 338: 0007a583 lw a1,0(a5)
+ 33c: 00059c63 bnez a1,354
+ 340: 05012083 lw ra,80(sp)
+ 344: 04c12403 lw s0,76(sp)
+ 348: 04812483 lw s1,72(sp)
+ 34c: 05410113 addi sp,sp,84
+ 350: 00008067 ret
+ 354: 00100713 li a4,1
+ 358: 00e58463 beq a1,a4,360
+ 35c: 04b46063 bltu s0,a1,39c
+ 360: 00012683 lw a3,0(sp)
+ 364: 00001737 lui a4,0x1
+ 368: 00f12223 sw a5,4(sp)
+ 36c: 15870713 addi a4,a4,344 # 1158
+ 370: 02068c63 beqz a3,3a8
+ 374: 00040513 mv a0,s0
+ 378: 400000ef jal ra,778 <__udivsi3>
+ 37c: 00a00593 li a1,10
+ 380: 400000ef jal ra,780 <__umodsi3>
+ 384: 000017b7 lui a5,0x1
+ 388: 15878713 addi a4,a5,344 # 1158
+ 38c: 00a70533 add a0,a4,a0
+ 390: 00054503 lbu a0,0(a0)
+ 394: dfdff0ef jal ra,190
+ 398: 00412783 lw a5,4(sp)
+ 39c: ff848493 addi s1,s1,-8
+ 3a0: 00478793 addi a5,a5,4
+ 3a4: f95ff06f j 338
+ 3a8: 00448693 addi a3,s1,4
+ 3ac: 00d456b3 srl a3,s0,a3
+ 3b0: 00f6f693 andi a3,a3,15
+ 3b4: 00d706b3 add a3,a4,a3
+ 3b8: 0006c503 lbu a0,0(a3)
+ 3bc: dd5ff0ef jal ra,190
+ 3c0: 00945533 srl a0,s0,s1
+ 3c4: 000017b7 lui a5,0x1
+ 3c8: 00f57513 andi a0,a0,15
+ 3cc: 15878713 addi a4,a5,344 # 1158
+ 3d0: 00a70733 add a4,a4,a0
+ 3d4: 00074503 lbu a0,0(a4)
+ 3d8: fbdff06f j 394
+
+000003dc :
+ 3dc: 00000593 li a1,0
+ 3e0: f05ff06f j 2e4
+
+000003e4 :
+ 3e4: 00100593 li a1,1
+ 3e8: efdff06f j 2e4
+
+000003ec :
+ 3ec: fdc10113 addi sp,sp,-36
+ 3f0: 02f12023 sw a5,32(sp)
+ 3f4: 01010793 addi a5,sp,16
+ 3f8: 00812423 sw s0,8(sp)
+ 3fc: 00112623 sw ra,12(sp)
+ 400: 00912223 sw s1,4(sp)
+ 404: 00050413 mv s0,a0
+ 408: 00b12823 sw a1,16(sp)
+ 40c: 00c12a23 sw a2,20(sp)
+ 410: 00d12c23 sw a3,24(sp)
+ 414: 00e12e23 sw a4,28(sp)
+ 418: 00f12023 sw a5,0(sp)
+ 41c: 00044503 lbu a0,0(s0)
+ 420: 00051c63 bnez a0,438
+ 424: 00c12083 lw ra,12(sp)
+ 428: 00812403 lw s0,8(sp)
+ 42c: 00412483 lw s1,4(sp)
+ 430: 02410113 addi sp,sp,36
+ 434: 00008067 ret
+ 438: 02500793 li a5,37
+ 43c: 00140493 addi s1,s0,1
+ 440: 06f51a63 bne a0,a5,4b4
+ 444: 00144503 lbu a0,1(s0)
+ 448: 07300793 li a5,115
+ 44c: 02f51063 bne a0,a5,46c
+ 450: 00012783 lw a5,0(sp)
+ 454: 0007a503 lw a0,0(a5)
+ 458: 00478713 addi a4,a5,4
+ 45c: 00e12023 sw a4,0(sp)
+ 460: e29ff0ef jal ra,288
+ 464: 00148413 addi s0,s1,1
+ 468: fb5ff06f j 41c
+ 46c: 07800793 li a5,120
+ 470: 00f51e63 bne a0,a5,48c
+ 474: 00012783 lw a5,0(sp)
+ 478: 0007a503 lw a0,0(a5)
+ 47c: 00478713 addi a4,a5,4
+ 480: 00e12023 sw a4,0(sp)
+ 484: f59ff0ef jal ra,3dc
+ 488: fddff06f j 464
+ 48c: 06400793 li a5,100
+ 490: 00f51e63 bne a0,a5,4ac
+ 494: 00012783 lw a5,0(sp)
+ 498: 0007a503 lw a0,0(a5)
+ 49c: 00478713 addi a4,a5,4
+ 4a0: 00e12023 sw a4,0(sp)
+ 4a4: f41ff0ef jal ra,3e4
+ 4a8: fbdff06f j 464
+ 4ac: ce5ff0ef jal ra,190
+ 4b0: fb5ff06f j 464
+ 4b4: cddff0ef jal ra,190
+ 4b8: 00040493 mv s1,s0
+ 4bc: fa9ff06f j 464
+
+000004c0 :
+ 4c0: fff60613 addi a2,a2,-1
+ 4c4: 00000793 li a5,0
+ 4c8: 00f50733 add a4,a0,a5
+ 4cc: 00074683 lbu a3,0(a4)
+ 4d0: 00f58733 add a4,a1,a5
+ 4d4: 00074703 lbu a4,0(a4)
+ 4d8: 00c78a63 beq a5,a2,4ec
+ 4dc: 00068863 beqz a3,4ec
+ 4e0: 00070663 beqz a4,4ec
+ 4e4: 00178793 addi a5,a5,1
+ 4e8: fee680e3 beq a3,a4,4c8
+ 4ec: 40e68533 sub a0,a3,a4
+ 4f0: 00008067 ret
+
+000004f4 :
+ 4f4: fff00613 li a2,-1
+ 4f8: fc9ff06f j 4c0
+
+000004fc :
+ 4fc: 00000793 li a5,0
+ 500: 00f50733 add a4,a0,a5
+ 504: 00074703 lbu a4,0(a4)
+ 508: 00070863 beqz a4,518
+ 50c: 00178793 addi a5,a5,1
+ 510: 00f50733 add a4,a0,a5
+ 514: fe0716e3 bnez a4,500
+ 518: 00078513 mv a0,a5
+ 51c: 00008067 ret
+
+00000520 :
+ 520: 00000793 li a5,0
+ 524: 00c79463 bne a5,a2,52c
+ 528: 00008067 ret
+ 52c: 00f58733 add a4,a1,a5
+ 530: 00074683 lbu a3,0(a4)
+ 534: 00f50733 add a4,a0,a5
+ 538: 00178793 addi a5,a5,1
+ 53c: 00d70023 sb a3,0(a4)
+ 540: fe5ff06f j 524
+
+00000544 :
+ 544: 00c50633 add a2,a0,a2
+ 548: 00050793 mv a5,a0
+ 54c: 00c79463 bne a5,a2,554
+ 550: 00008067 ret
+ 554: 00178793 addi a5,a5,1
+ 558: feb78fa3 sb a1,-1(a5)
+ 55c: ff1ff06f j 54c
+
+00000560 :
+ 560: fec10113 addi sp,sp,-20
+ 564: 00812623 sw s0,12(sp)
+ 568: 00050413 mv s0,a0
+ 56c: 00058513 mv a0,a1
+ 570: 00912423 sw s1,8(sp)
+ 574: 00112823 sw ra,16(sp)
+ 578: 00058493 mv s1,a1
+ 57c: f81ff0ef jal ra,4fc
+ 580: 00050693 mv a3,a0
+ 584: 00041863 bnez s0,594
+ 588: 000017b7 lui a5,0x1
+ 58c: 0087a403 lw s0,8(a5) # 1008
+ 590: 04040863 beqz s0,5e0
+ 594: 00040793 mv a5,s0
+ 598: 0007c703 lbu a4,0(a5)
+ 59c: 00071863 bnez a4,5ac
+ 5a0: 000017b7 lui a5,0x1
+ 5a4: 0007a423 sw zero,8(a5) # 1008
+ 5a8: 0380006f j 5e0
+ 5ac: 00068613 mv a2,a3
+ 5b0: 00078513 mv a0,a5
+ 5b4: 00048593 mv a1,s1
+ 5b8: 00d12223 sw a3,4(sp)
+ 5bc: 00f12023 sw a5,0(sp)
+ 5c0: f01ff0ef jal ra,4c0
+ 5c4: 00012783 lw a5,0(sp)
+ 5c8: 00412683 lw a3,4(sp)
+ 5cc: 00178713 addi a4,a5,1
+ 5d0: 02051463 bnez a0,5f8
+ 5d4: 00078023 sb zero,0(a5)
+ 5d8: 000017b7 lui a5,0x1
+ 5dc: 00e7a423 sw a4,8(a5) # 1008
+ 5e0: 00040513 mv a0,s0
+ 5e4: 01012083 lw ra,16(sp)
+ 5e8: 00c12403 lw s0,12(sp)
+ 5ec: 00812483 lw s1,8(sp)
+ 5f0: 01410113 addi sp,sp,20
+ 5f4: 00008067 ret
+ 5f8: 00070793 mv a5,a4
+ 5fc: f9dff06f j 598
+
+00000600 :
+ 600: 00000693 li a3,0
+ 604: 00000793 li a5,0
+ 608: 02d00613 li a2,45
+ 60c: 00051c63 bnez a0,624
+ 610: 02069e63 bnez a3,64c
+ 614: 00078513 mv a0,a5
+ 618: 00008067 ret
+ 61c: 00100693 li a3,1
+ 620: 0240006f j 644
+ 624: 00054703 lbu a4,0(a0)
+ 628: fe0704e3 beqz a4,610
+ 62c: fec708e3 beq a4,a2,61c
+ 630: 00379593 slli a1,a5,0x3
+ 634: fd070713 addi a4,a4,-48
+ 638: 00b70733 add a4,a4,a1
+ 63c: 00179793 slli a5,a5,0x1
+ 640: 00f707b3 add a5,a4,a5
+ 644: 00150513 addi a0,a0,1
+ 648: fc5ff06f j 60c
+ 64c: 40f007b3 neg a5,a5
+ 650: fc5ff06f j 614
+
+00000654 :
+ 654: 00050693 mv a3,a0
+ 658: 03900613 li a2,57
+ 65c: 00000513 li a0,0
+ 660: 00068663 beqz a3,66c
+ 664: 0006c783 lbu a5,0(a3)
+ 668: 00079463 bnez a5,670
+ 66c: 00008067 ret
+ 670: 00451713 slli a4,a0,0x4
+ 674: 00f66a63 bltu a2,a5,688
+ 678: fd078793 addi a5,a5,-48
+ 67c: 00e78533 add a0,a5,a4
+ 680: 00168693 addi a3,a3,1
+ 684: fddff06f j 660
+ 688: 05f7f793 andi a5,a5,95
+ 68c: fc978793 addi a5,a5,-55
+ 690: fedff06f j 67c
+
+00000694 :
+ 694: 857f 0x857f
+ 696: 00c5 addi ra,ra,17
+ 698: 00008067 ret
+
+0000069c <__umulsi3>:
+ 69c: 00050793 mv a5,a0
+ 6a0: 00b57663 bleu a1,a0,6ac <__umulsi3+0x10>
+ 6a4: 00058793 mv a5,a1
+ 6a8: 00050593 mv a1,a0
+ 6ac: 00000513 li a0,0
+ 6b0: 00059463 bnez a1,6b8 <__umulsi3+0x1c>
+ 6b4: 00008067 ret
+ 6b8: 0015f713 andi a4,a1,1
+ 6bc: 00070463 beqz a4,6c4 <__umulsi3+0x28>
+ 6c0: 00f50533 add a0,a0,a5
+ 6c4: 00179793 slli a5,a5,0x1
+ 6c8: 0015d593 srli a1,a1,0x1
+ 6cc: fe5ff06f j 6b0 <__umulsi3+0x14>
+
+000006d0 <__mulsi3>:
+ 6d0: ff410113 addi sp,sp,-12
+ 6d4: 00912023 sw s1,0(sp)
+ 6d8: 00112423 sw ra,8(sp)
+ 6dc: 00812223 sw s0,4(sp)
+ 6e0: 00000493 li s1,0
+ 6e4: 00055663 bgez a0,6f0 <__mulsi3+0x20>
+ 6e8: 40a00533 neg a0,a0
+ 6ec: 00100493 li s1,1
+ 6f0: 00000413 li s0,0
+ 6f4: 0005d663 bgez a1,700 <__mulsi3+0x30>
+ 6f8: 40b005b3 neg a1,a1
+ 6fc: 00100413 li s0,1
+ 700: f9dff0ef jal ra,69c <__umulsi3>
+ 704: 00050793 mv a5,a0
+ 708: 00848463 beq s1,s0,710 <__mulsi3+0x40>
+ 70c: 40a007b3 neg a5,a0
+ 710: 00812083 lw ra,8(sp)
+ 714: 00412403 lw s0,4(sp)
+ 718: 00012483 lw s1,0(sp)
+ 71c: 00078513 mv a0,a5
+ 720: 00c10113 addi sp,sp,12
+ 724: 00008067 ret
+
+00000728 <__udiv_umod_si3>:
+ 728: 00100793 li a5,1
+ 72c: 00059a63 bnez a1,740 <__udiv_umod_si3+0x18>
+ 730: 00058513 mv a0,a1
+ 734: 00008067 ret
+ 738: 00179793 slli a5,a5,0x1
+ 73c: 00159593 slli a1,a1,0x1
+ 740: fea5ece3 bltu a1,a0,738 <__udiv_umod_si3+0x10>
+ 744: 00058713 mv a4,a1
+ 748: 00000593 li a1,0
+ 74c: 00050463 beqz a0,754 <__udiv_umod_si3+0x2c>
+ 750: 00079863 bnez a5,760 <__udiv_umod_si3+0x38>
+ 754: fc061ee3 bnez a2,730 <__udiv_umod_si3+0x8>
+ 758: 00050593 mv a1,a0
+ 75c: fd5ff06f j 730 <__udiv_umod_si3+0x8>
+ 760: 00e56663 bltu a0,a4,76c <__udiv_umod_si3+0x44>
+ 764: 40e50533 sub a0,a0,a4
+ 768: 00f585b3 add a1,a1,a5
+ 76c: 0017d793 srli a5,a5,0x1
+ 770: 00175713 srli a4,a4,0x1
+ 774: fd9ff06f j 74c <__udiv_umod_si3+0x24>
+
+00000778 <__udivsi3>:
+ 778: 00100613 li a2,1
+ 77c: fadff06f j 728 <__udiv_umod_si3>
+
+00000780 <__umodsi3>:
+ 780: 00000613 li a2,0
+ 784: fa5ff06f j 728 <__udiv_umod_si3>
+
+00000788 <__div_mod_si3>:
+ 788: 06058e63 beqz a1,804 <__div_mod_si3+0x7c>
+ 78c: ff010113 addi sp,sp,-16
+ 790: 00812423 sw s0,8(sp)
+ 794: 00112623 sw ra,12(sp)
+ 798: 00912223 sw s1,4(sp)
+ 79c: 00060793 mv a5,a2
+ 7a0: 00000413 li s0,0
+ 7a4: 00055663 bgez a0,7b0 <__div_mod_si3+0x28>
+ 7a8: 40a00533 neg a0,a0
+ 7ac: 00100413 li s0,1
+ 7b0: 00000493 li s1,0
+ 7b4: 0005d663 bgez a1,7c0 <__div_mod_si3+0x38>
+ 7b8: 40b005b3 neg a1,a1
+ 7bc: 00100493 li s1,1
+ 7c0: 00078613 mv a2,a5
+ 7c4: 00f12023 sw a5,0(sp)
+ 7c8: f61ff0ef jal ra,728 <__udiv_umod_si3>
+ 7cc: 00012783 lw a5,0(sp)
+ 7d0: 00050593 mv a1,a0
+ 7d4: 02078263 beqz a5,7f8 <__div_mod_si3+0x70>
+ 7d8: 00940463 beq s0,s1,7e0 <__div_mod_si3+0x58>
+ 7dc: 40a005b3 neg a1,a0
+ 7e0: 00c12083 lw ra,12(sp)
+ 7e4: 00812403 lw s0,8(sp)
+ 7e8: 00412483 lw s1,4(sp)
+ 7ec: 00058513 mv a0,a1
+ 7f0: 01010113 addi sp,sp,16
+ 7f4: 00008067 ret
+ 7f8: fe0404e3 beqz s0,7e0 <__div_mod_si3+0x58>
+ 7fc: 40a005b3 neg a1,a0
+ 800: fe1ff06f j 7e0 <__div_mod_si3+0x58>
+ 804: 00058513 mv a0,a1
+ 808: 00008067 ret
+
+0000080c <__divsi3>:
+ 80c: 00100613 li a2,1
+ 810: f79ff06f j 788 <__div_mod_si3>
+
+00000814 <__modsi3>:
+ 814: 00000613 li a2,0
+ 818: f71ff06f j 788 <__div_mod_si3>
+
+0000081c :
+ 81c: 000017b7 lui a5,0x1
+ 820: 0047a703 lw a4,4(a5) # 1004
+ 824: 00100793 li a5,1
+ 828: 00e7dc63 ble a4,a5,840
+ 82c: fff00713 li a4,-1
+ 830: 000017b7 lui a5,0x1
+ 834: fff50513 addi a0,a0,-1
+ 838: 02e51263 bne a0,a4,85c
+ 83c: 00008067 ret
+ 840: 800007b7 lui a5,0x80000
+ 844: fff00693 li a3,-1
+ 848: 00078793 mv a5,a5
+ 84c: f8000613 li a2,-128
+ 850: fff50513 addi a0,a0,-1
+ 854: 00d51c63 bne a0,a3,86c
+ 858: 00008067 ret
+ 85c: 0007a683 lw a3,0(a5) # 80000000
+ 860: 0007a603 lw a2,0(a5)
+ 864: fed60ee3 beq a2,a3,860
+ 868: fcdff06f j 834
+ 86c: 00c781a3 sb a2,3(a5)
+ 870: 0037c703 lbu a4,3(a5)
+ 874: 0ff77713 andi a4,a4,255
+ 878: fe070ce3 beqz a4,870
+ 87c: fd5ff06f j 850
+
+00000880 :
+ 880: ee010113 addi sp,sp,-288
+ 884: 000015b7 lui a1,0x1
+ 888: 10d00613 li a2,269
+ 88c: 44058593 addi a1,a1,1088 # 1440
+ 890: 00410513 addi a0,sp,4
+ 894: 10112e23 sw ra,284(sp)
+ 898: 10812c23 sw s0,280(sp)
+ 89c: 10912a23 sw s1,276(sp)
+ 8a0: c81ff0ef jal ra,520
+ 8a4: 00a00513 li a0,10
+ 8a8: 8e9ff0ef jal ra,190
+ 8ac: 00410413 addi s0,sp,4
+ 8b0: 00044783 lbu a5,0(s0)
+ 8b4: 00079c63 bnez a5,8cc
+ 8b8: 11c12083 lw ra,284(sp)
+ 8bc: 11812403 lw s0,280(sp)
+ 8c0: 11412483 lw s1,276(sp)
+ 8c4: 12010113 addi sp,sp,288
+ 8c8: 00008067 ret
+ 8cc: 00240413 addi s0,s0,2
+ 8d0: fff44483 lbu s1,-1(s0)
+ 8d4: fff48493 addi s1,s1,-1
+ 8d8: fff00713 li a4,-1
+ 8dc: fce48ae3 beq s1,a4,8b0
+ 8e0: 00078513 mv a0,a5
+ 8e4: 00f12023 sw a5,0(sp)
+ 8e8: 8a9ff0ef jal ra,190
+ 8ec: 00012783 lw a5,0(sp)
+ 8f0: fe5ff06f j 8d4
+
+Disassembly of section .text.startup:
+
+000008f4 :
+ 8f4: f8810113 addi sp,sp,-120
+ 8f8: 06812823 sw s0,112(sp)
+ 8fc: 80000437 lui s0,0x80000
+ 900: 00044503 lbu a0,0(s0) # 80000000
+ 904: 06112a23 sw ra,116(sp)
+ 908: 06912623 sw s1,108(sp)
+ 90c: f98ff0ef jal ra,a4
+ 910: 00044603 lbu a2,0(s0)
+ 914: 00050593 mv a1,a0
+ 918: 00001537 lui a0,0x1
+ 91c: 17850513 addi a0,a0,376 # 1178
+ 920: acdff0ef jal ra,3ec
+ 924: 000015b7 lui a1,0x1
+ 928: 00001537 lui a0,0x1
+ 92c: 18c58593 addi a1,a1,396 # 118c
+ 930: 1ac50513 addi a0,a0,428 # 11ac
+ 934: ab9ff0ef jal ra,3ec
+ 938: 00040793 mv a5,s0
+ 93c: 000014b7 lui s1,0x1
+ 940: 0017c303 lbu t1,1(a5)
+ 944: 0027c283 lbu t0,2(a5)
+ 948: 0044a703 lw a4,4(s1) # 1004
+ 94c: 00100793 li a5,1
+ 950: 0ff37313 andi t1,t1,255
+ 954: 0ff2f293 andi t0,t0,255
+ 958: 00040413 mv s0,s0
+ 95c: 18e7c263 blt a5,a4,ae0
+ 960: 00001737 lui a4,0x1
+ 964: 54c70713 addi a4,a4,1356 # 154c
+ 968: 01000613 li a2,16
+ 96c: 01000593 li a1,16
+ 970: 3e800513 li a0,1000
+ 974: 00e12423 sw a4,8(sp)
+ 978: 00512223 sw t0,4(sp)
+ 97c: 00612023 sw t1,0(sp)
+ 980: d15ff0ef jal ra,694
+ 984: 4e800793 li a5,1256
+ 988: 00012303 lw t1,0(sp)
+ 98c: 00412283 lw t0,4(sp)
+ 990: 00812703 lw a4,8(sp)
+ 994: 14f50c63 beq a0,a5,aec
+ 998: 000017b7 lui a5,0x1
+ 99c: 54c78793 addi a5,a5,1356 # 154c
+ 9a0: 000016b7 lui a3,0x1
+ 9a4: 00001537 lui a0,0x1
+ 9a8: 00028613 mv a2,t0
+ 9ac: 00030593 mv a1,t1
+ 9b0: 1cc68693 addi a3,a3,460 # 11cc
+ 9b4: 1d450513 addi a0,a0,468 # 11d4
+ 9b8: a35ff0ef jal ra,3ec
+ 9bc: 0004a223 sw zero,4(s1)
+ 9c0: 00645583 lhu a1,6(s0)
+ 9c4: 00001537 lui a0,0x1
+ 9c8: 1fc50513 addi a0,a0,508 # 11fc
+ 9cc: a21ff0ef jal ra,3ec
+ 9d0: 00144503 lbu a0,1(s0)
+ 9d4: 00244483 lbu s1,2(s0)
+ 9d8: 00c42703 lw a4,12(s0)
+ 9dc: 00c42603 lw a2,12(s0)
+ 9e0: 000f45b7 lui a1,0xf4
+ 9e4: 24058593 addi a1,a1,576 # f4240
+ 9e8: 00c12223 sw a2,4(sp)
+ 9ec: 00e12423 sw a4,8(sp)
+ 9f0: ce1ff0ef jal ra,6d0 <__mulsi3>
+ 9f4: 0ff4f493 andi s1,s1,255
+ 9f8: 000025b7 lui a1,0x2
+ 9fc: 00a12023 sw a0,0(sp)
+ a00: 71058593 addi a1,a1,1808 # 2710
+ a04: 00048513 mv a0,s1
+ a08: cc9ff0ef jal ra,6d0 <__mulsi3>
+ a0c: 00812703 lw a4,8(sp)
+ a10: 00012783 lw a5,0(sp)
+ a14: 00170593 addi a1,a4,1
+ a18: 00a78533 add a0,a5,a0
+ a1c: d5dff0ef jal ra,778 <__udivsi3>
+ a20: 00412603 lw a2,4(sp)
+ a24: 00050593 mv a1,a0
+ a28: 00001537 lui a0,0x1
+ a2c: 21850513 addi a0,a0,536 # 1218
+ a30: 9bdff0ef jal ra,3ec
+ a34: 00a00513 li a0,10
+ a38: f58ff0ef jal ra,190
+ a3c: 00001537 lui a0,0x1
+ a40: 24450513 addi a0,a0,580 # 1244
+ a44: 885ff0ef jal ra,2c8
+ a48: 00a00513 li a0,10
+ a4c: dd1ff0ef jal ra,81c
+ a50: 000017b7 lui a5,0x1
+ a54: 25c78513 addi a0,a5,604 # 125c
+ a58: 995ff0ef jal ra,3ec
+ a5c: 04000613 li a2,64
+ a60: 00000593 li a1,0
+ a64: 02c10513 addi a0,sp,44
+ a68: addff0ef jal ra,544
+ a6c: 04000593 li a1,64
+ a70: 02c10513 addi a0,sp,44
+ a74: f5cff0ef jal ra,1d0
+ a78: 00000493 li s1,0
+ a7c: 02c10513 addi a0,sp,44
+ a80: 00001737 lui a4,0x1
+ a84: 26070593 addi a1,a4,608 # 1260
+ a88: ad9ff0ef jal ra,560
+ a8c: 06c10713 addi a4,sp,108
+ a90: 00249793 slli a5,s1,0x2
+ a94: 00f707b3 add a5,a4,a5
+ a98: faa7a023 sw a0,-96(a5)
+ a9c: 00001737 lui a4,0x1
+ aa0: 00050a63 beqz a0,ab4
+ aa4: 00148493 addi s1,s1,1
+ aa8: 00800793 li a5,8
+ aac: 00000513 li a0,0
+ ab0: fcf49ae3 bne s1,a5,a84
+ ab4: 00c12483 lw s1,12(sp)
+ ab8: f8048ce3 beqz s1,a50
+ abc: 000015b7 lui a1,0x1
+ ac0: 26458593 addi a1,a1,612 # 1264
+ ac4: 00048513 mv a0,s1
+ ac8: a2dff0ef jal ra,4f4
+ acc: 02051663 bnez a0,af8
+ ad0: 00001537 lui a0,0x1
+ ad4: 26c50513 addi a0,a0,620 # 126c
+ ad8: 915ff0ef jal ra,3ec
+ adc: f75ff06f j a50
+ ae0: 00001737 lui a4,0x1
+ ae4: 16c70713 addi a4,a4,364 # 116c
+ ae8: e81ff06f j 968
+ aec: 000017b7 lui a5,0x1
+ af0: 17078793 addi a5,a5,368 # 1170
+ af4: eadff06f j 9a0
+ af8: 000015b7 lui a1,0x1
+ afc: 27458593 addi a1,a1,628 # 1274
+ b00: 00048513 mv a0,s1
+ b04: 9f1ff0ef jal ra,4f4
+ b08: 2c050263 beqz a0,dcc
+ b0c: 000015b7 lui a1,0x1
+ b10: 2a058593 addi a1,a1,672 # 12a0
+ b14: 00048513 mv a0,s1
+ b18: 9ddff0ef jal ra,4f4
+ b1c: 0a051863 bnez a0,bcc
+ b20: 01012483 lw s1,16(sp)
+ b24: 00048863 beqz s1,b34
+ b28: 00048513 mv a0,s1
+ b2c: b29ff0ef jal ra,654
+ b30: 00050493 mv s1,a0
+ b34: 10048793 addi a5,s1,256
+ b38: 00f12023 sw a5,0(sp)
+ b3c: 000017b7 lui a5,0x1
+ b40: 00048593 mv a1,s1
+ b44: 2a878513 addi a0,a5,680 # 12a8
+ b48: 8a5ff0ef jal ra,3ec
+ b4c: 00000713 li a4,0
+ b50: 00001637 lui a2,0x1
+ b54: 00e486b3 add a3,s1,a4
+ b58: 0006c583 lbu a1,0(a3)
+ b5c: 2b060513 addi a0,a2,688 # 12b0
+ b60: 00e12223 sw a4,4(sp)
+ b64: 889ff0ef jal ra,3ec
+ b68: 00412703 lw a4,4(sp)
+ b6c: 01000693 li a3,16
+ b70: 00001637 lui a2,0x1
+ b74: 00170713 addi a4,a4,1
+ b78: fcd71ee3 bne a4,a3,b54
+ b7c: 00000713 li a4,0
+ b80: 00e486b3 add a3,s1,a4
+ b84: 0006c503 lbu a0,0(a3)
+ b88: 05e00613 li a2,94
+ b8c: fe050693 addi a3,a0,-32
+ b90: 0ff6f693 andi a3,a3,255
+ b94: 00d67463 bleu a3,a2,b9c
+ b98: 02e00513 li a0,46
+ b9c: 00e12223 sw a4,4(sp)
+ ba0: df0ff0ef jal ra,190
+ ba4: 00412703 lw a4,4(sp)
+ ba8: 01000693 li a3,16
+ bac: 00170713 addi a4,a4,1
+ bb0: fcd718e3 bne a4,a3,b80
+ bb4: 00a00513 li a0,10
+ bb8: dd8ff0ef jal ra,190
+ bbc: 00012783 lw a5,0(sp)
+ bc0: 01048493 addi s1,s1,16
+ bc4: f6f49ce3 bne s1,a5,b3c
+ bc8: e89ff06f j a50
+ bcc: 000015b7 lui a1,0x1
+ bd0: 2b458593 addi a1,a1,692 # 12b4
+ bd4: 00048513 mv a0,s1
+ bd8: 91dff0ef jal ra,4f4
+ bdc: 02051863 bnez a0,c0c
+ be0: 01012503 lw a0,16(sp)
+ be4: 00050a63 beqz a0,bf8
+ be8: a6dff0ef jal ra,654
+ bec: 01051513 slli a0,a0,0x10
+ bf0: 01055513 srli a0,a0,0x10
+ bf4: 00a41423 sh a0,8(s0)
+ bf8: 00845583 lhu a1,8(s0)
+ bfc: 00001537 lui a0,0x1
+ c00: 2b850513 addi a0,a0,696 # 12b8
+ c04: fe8ff0ef jal ra,3ec
+ c08: e49ff06f j a50
+ c0c: 000015b7 lui a1,0x1
+ c10: 2c458593 addi a1,a1,708 # 12c4
+ c14: 00048513 mv a0,s1
+ c18: 8ddff0ef jal ra,4f4
+ c1c: 02051263 bnez a0,c40
+ c20: 01012503 lw a0,16(sp)
+ c24: 00050663 beqz a0,c30
+ c28: 9d9ff0ef jal ra,600
+ c2c: 00a42623 sw a0,12(s0)
+ c30: 00001537 lui a0,0x1
+ c34: 00c42583 lw a1,12(s0)
+ c38: 2cc50513 addi a0,a0,716 # 12cc
+ c3c: fc9ff06f j c04
+ c40: 000015b7 lui a1,0x1
+ c44: 2d858593 addi a1,a1,728 # 12d8
+ c48: 00048513 mv a0,s1
+ c4c: 8a9ff0ef jal ra,4f4
+ c50: 02051663 bnez a0,c7c