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/trunk/bench/verilog/dbg_tb_defines.v
0,0 → 1,167
//////////////////////////////////////////////////////////////////////
//// ////
//// dbgTB_defines.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/06/01 22:23:40 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:05 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:12 mohor
// Initial release
//
//
 
// Following defines are used in the testbench only
 
// MODER register
`define CONTIN 32'h00000001
`define ENABLE 32'h00000002
// TSEL register
`define WPTRIG_0 32'h00000001
`define WPTRIG_1 32'h00000002
`define WPTRIG_2 32'h00000004
`define WPTRIG_3 32'h00000008
`define WPTRIG_4 32'h00000010
`define WPTRIG_5 32'h00000020
`define WPTRIG_6 32'h00000040
`define WPTRIG_7 32'h00000080
`define WPTRIG_8 32'h00000100
`define WPTRIG_9 32'h00000200
`define WPTRIG_10 32'h00000400
`define WPTRIGVALID 32'h00000800
`define BPTRIG 32'h00001000
`define BPTRIGVALID 32'h00002000
`define LSSTRIG_0 32'h00010000
`define LSSTRIG_1 32'h00020000
`define LSSTRIG_2 32'h00040000
`define LSSTRIG_3 32'h00080000
`define LSSTRIGVALID 32'h00100000
`define ISTRIGVALID 32'h00800000
`define TRIGOP_AND 32'hc0000000
`define TRIGOP_OR 32'h80000000
// QSEL register
`define WPQUALIF_0 32'h00000001
`define WPQUALIF_1 32'h00000002
`define WPQUALIF_2 32'h00000004
`define WPQUALIF_3 32'h00000008
`define WPQUALIF_4 32'h00000010
`define WPQUALIF_5 32'h00000020
`define WPQUALIF_6 32'h00000040
`define WPQUALIF_7 32'h00000080
`define WPQUALIF_8 32'h00000100
`define WPQUALIF_9 32'h00000200
`define WPQUALIF_10 32'h00000400
`define WPQUALIFVALID 32'h00000800
`define BPQUALIF 32'h00001000
`define BPQUALIFVALID 32'h00002000
`define LSSQUALIF_0 32'h00010000
`define LSSQUALIF_1 32'h00020000
`define LSSQUALIF_2 32'h00040000
`define LSSQUALIF_3 32'h00080000
`define LSSQUALIFVALID 32'h00100000
`define ISQUALIFVALID 32'h00800000
`define QUALIFOP_AND 32'hc0000000
`define QUALIFOP_OR 32'h80000000
 
 
// SSEL register
`define WPSTOP_0 32'h00000001
`define WPSTOP_1 32'h00000002
`define WPSTOP_2 32'h00000004
`define WPSTOP_3 32'h00000008
`define WPSTOP_4 32'h00000010
`define WPSTOP_5 32'h00000020
`define WPSTOP_6 32'h00000040
`define WPSTOP_7 32'h00000080
`define WPSTOP_8 32'h00000100
`define WPSTOP_9 32'h00000200
`define WPSTOP_10 32'h00000400
`define WPSTOPVALID 32'h00000800
`define BPSTOP 32'h00001000
`define BPSTOPVALID 32'h00002000
`define LSSSTOP_0 32'h00010000
`define LSSSTOP_1 32'h00020000
`define LSSSTOP_2 32'h00040000
`define LSSSTOP_3 32'h00080000
`define LSSSTOPVALID 32'h00100000
`define ISSTOPVALID 32'h00800000
`define STOPOP_AND 32'hc0000000
`define STOPOP_OR 32'h80000000
 
`define IS_NO_FETCH 32'h00000000
`define IS_FETCH 32'h00200000
`define IS_BRANCH 32'h00400000
`define IS_FETCH_DELAY 32'h00600000
 
`define LSS_NO_LOADSTORE 32'h00000000
`define LSS_LOADBYTE_ZEROEXT 32'h00020000
`define LSS_LOADBYTE_SIGNEXT 32'h00030000
`define LSS_LOADHALF_ZEROEXT 32'h00040000
`define LSS_LOADHALF_SIGNEXT 32'h00050000
`define LSS_LOADWORD_ZEROEXT 32'h00060000
`define LSS_LOADWORD_SIGNEXT 32'h00070000
`define LSS_STORE_BYTE 32'h000A0000
`define LSS_STORE_HALF 32'h000C0000
 
// End: Following defines are used in the testbench only
 
 
/trunk/bench/verilog/dbg_tb.v
0,0 → 1,788
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_tb.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/06/01 22:23:40 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:05 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:15 mohor
// Initial release
//
//
 
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
`include "dbg_tb_defines.v"
 
// Test bench
module dbg_tb;
 
parameter Tp = 1;
parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
 
 
reg P_TMS, P_TCK;
reg P_TRST, P_TDI;
reg P_PowerONReset;
reg Mclk;
 
reg [10:0] Wp;
reg Bp;
reg [3:0] LsStatus;
reg [1:0] IStatus;
 
wire P_TDO;
wire [31:0] ADDR_RISC;
wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
wire RISC_CS;
wire RISC_RW;
 
wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
 
wire [`OPSELECTWIDTH-1:0] OpSelect;
 
// Connecting TAP module
dbg_top dbgTAP1(.P_TMS(P_TMS), .P_TCK(P_TCK), .P_TRST(P_TRST), .P_TDI(P_TDI),
.P_TDO(P_TDO), .P_PowerONReset(P_PowerONReset), .Mclk(Mclk),
.RISC_ADDR(ADDR_RISC), .RISC_DATA_IN(DATAOUT_RISC), .RISC_DATA_OUT(DATAIN_RISC),
.RISC_CS(RISC_CS), .RISC_RW(RISC_RW), .Wp(Wp), .Bp(Bp),
.OpSelect(OpSelect), .LsStatus(LsStatus), .IStatus(IStatus)
);
 
 
reg TestEnabled;
//integer i;
 
 
 
initial
begin
TestEnabled<=#Tp 0;
P_TMS<=#Tp 0;
P_TCK<=#Tp 0;
P_TDI<=#Tp 0;
P_TRST<=#Tp 1;
 
Wp<=#Tp 0;
Bp<=#Tp 0;
LsStatus<=#Tp 0;
IStatus<=#Tp 0;
 
P_PowerONReset<=#Tp 1;
#100 P_PowerONReset<=#Tp 0; // PowerONReset is active low
#100 P_PowerONReset<=#Tp 1;
#Tp TestEnabled<=#Tp 1;
end
 
 
// Generating master clock (RISC clock) 200 MHz
initial
begin
Mclk<=#Tp 0;
#1 forever #`RISC_CLOCK Mclk<=~Mclk;
end
 
 
// Generating random number for use in DATAOUT_RISC[31:0]
reg [31:0] RandNumb;
always @ (posedge Mclk or negedge P_PowerONReset) // PowerONReset is active low
begin
if(~P_PowerONReset)
RandNumb[31:0]<=#Tp 0;
else
RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
end
 
 
assign DATAOUT_RISC[31:0] = RandNumb[31:0];
 
 
 
always @ (posedge TestEnabled)
begin
ResetTAP;
GotoRunTestIdle;
 
// Testing read and write to RISC registers
SetInstruction(`CHAIN_SELECT);
ChainSelect(`RISC_DEBUG_CHAIN, 8'h38); // {chain, crc}
SetInstruction(`DEBUG);
ReadRISCRegister(32'h12345ead, 8'hbf); // {addr, crc}
WriteRISCRegister(32'h11223344, 32'h12345678, 8'haf); // {data, addr, crc}
//
 
 
 
// Testing read and write to internal registers
SetInstruction(`IDCODE);
ReadIDCode;
 
SetInstruction(`CHAIN_SELECT);
ChainSelect(`REGISTER_SCAN_CHAIN, 8'h0e); // {chain, crc}
SetInstruction(`DEBUG);
 
//
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
ReadRegister(`RECWP0_ADR, 8'hc4); // {addr, crc}
ReadRegister(`RECWP1_ADR, 8'ha0); // {addr, crc}
ReadRegister(`RECWP2_ADR, 8'hf6); // {addr, crc}
ReadRegister(`RECWP3_ADR, 8'h92); // {addr, crc}
ReadRegister(`RECWP4_ADR, 8'hdd); // {addr, crc}
ReadRegister(`RECWP5_ADR, 8'hb9); // {addr, crc}
ReadRegister(`RECWP6_ADR, 8'hef); // {addr, crc}
ReadRegister(`RECWP7_ADR, 8'h8b); // {addr, crc}
ReadRegister(`RECWP8_ADR, 8'h4b); // {addr, crc}
ReadRegister(`RECWP9_ADR, 8'h2f); // {addr, crc}
ReadRegister(`RECWP10_ADR, 8'h79); // {addr, crc}
ReadRegister(`RECBP0_ADR, 8'h1d); // {addr, crc}
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
 
WriteRegister(32'h00000001, `MODER_ADR, 8'h53); // {data, addr, crc}
WriteRegister(32'h00000020, `TSEL_ADR, 8'h5e); // {data, addr, crc}
WriteRegister(32'h00000300, `QSEL_ADR, 8'hdd); // {data, addr, crc}
WriteRegister(32'h00004000, `SSEL_ADR, 8'he2); // {data, addr, crc}
WriteRegister(32'h00050000, `RECWP0_ADR, 8'hbe); // {data, addr, crc}
WriteRegister(32'h00600000, `RECWP1_ADR, 8'hbc); // {data, addr, crc}
WriteRegister(32'h07000000, `RECWP2_ADR, 8'h3a); // {data, addr, crc}
WriteRegister(32'h80000000, `RECWP3_ADR, 8'hf7); // {data, addr, crc}
WriteRegister(32'h09000000, `RECWP4_ADR, 8'h46); // {data, addr, crc}
WriteRegister(32'h00a00000, `RECWP5_ADR, 8'h9a); // {data, addr, crc}
WriteRegister(32'h000b0000, `RECWP6_ADR, 8'h37); // {data, addr, crc}
WriteRegister(32'h0000c000, `RECWP7_ADR, 8'h54); // {data, addr, crc}
WriteRegister(32'h00000d00, `RECWP8_ADR, 8'hc3); // {data, addr, crc}
WriteRegister(32'h000000e0, `RECWP9_ADR, 8'h2f); // {data, addr, crc}
WriteRegister(32'h0000000f, `RECWP10_ADR, 8'h18); // {data, addr, crc}
WriteRegister(32'hdeadbeef, `RECBP0_ADR, 8'h80); // {data, addr, crc}
 
ReadRegister(`MODER_ADR, 8'h00); // {addr, crc}
ReadRegister(`TSEL_ADR, 8'h64); // {addr, crc}
ReadRegister(`QSEL_ADR, 8'h32); // {addr, crc}
ReadRegister(`SSEL_ADR, 8'h56); // {addr, crc}
ReadRegister(`RECWP0_ADR, 8'hc4); // {addr, crc}
ReadRegister(`RECWP1_ADR, 8'ha0); // {addr, crc}
ReadRegister(`RECWP2_ADR, 8'hf6); // {addr, crc}
ReadRegister(`RECWP3_ADR, 8'h92); // {addr, crc}
ReadRegister(`RECWP4_ADR, 8'hdd); // {addr, crc}
ReadRegister(`RECWP5_ADR, 8'hb9); // {addr, crc}
ReadRegister(`RECWP6_ADR, 8'hef); // {addr, crc}
ReadRegister(`RECWP7_ADR, 8'h8b); // {addr, crc}
ReadRegister(`RECWP8_ADR, 8'h4b); // {addr, crc}
ReadRegister(`RECWP9_ADR, 8'h2f); // {addr, crc}
ReadRegister(`RECWP10_ADR, 8'h79); // {addr, crc}
ReadRegister(`RECBP0_ADR, 8'h1d); // {addr, crc}
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
ReadRegister(5'h1f, 8'h04); // {addr, crc} // Register address don't exist. Read should return high-Z.
//
 
 
// testing trigger and qualifier
`ifdef TRACE_ENABLED
/* Watchpoint Wp[0] starts trigger, anything starts qualifier
#1000 WriteRegister(`WPTRIG_0 | `WPTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'h9c); // Wp[0] starts trigger, anything starts qualifier
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hf9); // {data, addr, crc}
#2000 Wp=11'h001;
*/
 
/* Watchpoint Wp[10] & (IStatus[1:0] == IS_FETCH) start trigger, anything starts qualifier
#1000 WriteRegister(`WPTRIG_10 | `IS_FETCH | `WPTRIGVALID | `ISTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'haf); // Wp[10] & IStatus = IS_FETCH start trigger, anything starts qualifier
#1000 WriteRegister(`ENABLE | `CONTIN, `MODER_ADR, 8'hc8); // {data, addr, crc}
#2000 Wp=11'h001; // Wp[0] is active
#2000 IStatus=2'b01; // IStatus = IS_FETCH
#1999 Wp=11'h400; // Wp[10] is active
*/
 
/* Watchpoint Wp[10] & IStatus[1:0] = IS_BRANCH start trigger, anything starts qualifier
#1000 WriteRegister(`WPTRIG_10 | `IS_BRANCH | `WPTRIGVALID | `ISTRIGVALID | `TRIGOP_AND, `TSEL_ADR, 8'hd1); // Wp[10] & IStatus = IS_BRANCH start trigger, anything starts qualifier
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hf9); // {data, addr, crc}
#2000 Wp=11'h001; // Wp[0] is active
#2000 IStatus=2'b10; // IStatus = IS_BRANCH
#1999 Wp=11'h400; // Wp[10] is active
*/
 
/* Watchpoint Wp[5] starts qualifier, anything starts trigger
#1000 WriteRegister(`WPQUALIF_5 | `WPQUALIFVALID | `QUALIFOP_AND, `QSEL_ADR, 8'ha3); // Wp[5] starts Qualifier, anything starts trigger
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hf9); // {data, addr, crc}
#2000 Wp=11'h020; // Wp[5] is active
*/
 
// igor !!! od tu naprej je test TRACE-A, ki sem ga zakomentiral, ker moram najprej urediti read/write registrov
// Breakpoint Bp & LsStatus[1] start qualifier, anything starts trigger
#1000 WriteRegister(32'h12345673, `RECBP0_ADR, 8'hfe); // Ta je brez veze in mora iti ven. tu je le zato, da bi se videlo ali se registri berejo ok
#1000 WriteRegister(32'h00000003, `RECBP0_ADR, 8'hd5); // Breakpoint Bp selects two samples for recording
#100 WriteRegister(32'h80000801, `SSEL_ADR, 8'ha0); // Watchpoint Wp0 stops recording
// #1000 WriteRegister(`BPQUALIF | `LSS_LOADBYTE_ZEROEXT | `BPQUALIFVALID | `LSSQUALIFVALID | `QUALIFOP_AND, `QSEL_ADR, 8'h50); // Breakpoint Bp & LsStatus[1] start qualifier, anything starts trigger
#1000 WriteRegister(`ENABLE, `MODER_ADR, 8'hf9); // {data, addr, crc}
#2000 Bp=1; // Bp is active
// #2000 LsStatus[3:0]=4'h2; // LsStatus = LSS_LOADBYTE_ZEROEXT
#2000 LsStatus[3:0]=4'h2; // LsStatus = LSS_LOADBYTE_ZEROEXT
#45 LsStatus[3:0]=4'h1; // LsStatus != LSS_LOADBYTE_ZEROEXT ()
#90 LsStatus[3:0]=4'h2; // LsStatus = LSS_LOADBYTE_ZEROEXT
WriteRegister(32'h0000000c, `RECWP5_ADR, 8'h72); // Watchpoint Wp5 selects two samples for recording
#45 LsStatus[3:0]=4'h1; // LsStatus != LSS_LOADBYTE_ZEROEXT ()
#45 LsStatus[3:0]=4'h2; // LsStatus = LSS_LOADBYTE_ZEROEXT
Bp=0; // Bp is active
Wp=11'h020; // Wp[5] is active
#250 Wp=11'h021; // Wp[0] and Wp[5] are active. Wp[0] will stop recording
 
 
#45 LsStatus[3:0]=4'h1; // LsStatus != LSS_LOADBYTE_ZEROEXT ()
#45 LsStatus[3:0]=4'h2; // LsStatus = LSS_LOADBYTE_ZEROEXT
#1000 LsStatus[3:0]=4'h1; // LsStatus != LSS_LOADBYTE_ZEROEXT ()
 
 
 
 
//
 
#1000 WriteRegister(0, `MODER_ADR, 8'h62); // {data, addr, crc} Disable Trace
SetInstruction(`CHAIN_SELECT);
ChainSelect(`TRACE_TEST_CHAIN, 8'h24); // {chain, crc}
SetInstruction(`DEBUG);
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
ReadTraceBuffer;
 
// for(i=0;i<1500;i=i+1)
// ReadTraceBuffer;
 
// // igor !!! konec zakomentiranega trace-a
`endif // TRACE_ENABLED
 
 
 
#5000 GenClk(1); // One extra TCLK for debugging purposes
#100 $stop;
 
end
 
 
 
// Generation of the TCLK signal
task GenClk;
input [7:0] Number;
integer i;
begin
for(i=0; i<Number; i=i+1)
begin
#Tclk P_TCK<=1;
#Tclk P_TCK<=0;
end
end
endtask
 
 
// TAP reset
task ResetTAP;
begin
P_TMS<=#Tp 1;
GenClk(7);
end
endtask
 
 
// Goes to RunTestIdle state
task GotoRunTestIdle;
begin
P_TMS<=#Tp 0;
GenClk(1);
end
endtask
 
 
// sets the instruction to the IR register and goes to the RunTestIdle state
task SetInstruction;
input [3:0] Instr;
integer i;
begin
P_TMS<=#Tp 1;
GenClk(2);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftIR
 
for(i=0; i<`IR_LENGTH-1; i=i+1)
begin
P_TDI<=#Tp Instr[i];
GenClk(1);
end
P_TDI<=#Tp Instr[i]; // last shift
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // tri-state
GenClk(1);
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
end
endtask
 
 
// sets the selected scan chain and goes to the RunTestIdle state
task ChainSelect;
input [3:0] Data;
input [7:0] Crc;
integer i;
begin
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftDR
 
for(i=0; i<`CHAIN_ID_LENGTH; i=i+1)
begin
P_TDI<=#Tp Data[i];
GenClk(1);
end
 
for(i=0; i<`CRC_LENGTH-1; i=i+1)
begin
P_TDI<=#Tp Crc[i];
GenClk(1);
end
 
P_TDI<=#Tp Crc[i]; // last shift
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // tri-state
GenClk(1);
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
end
endtask
 
 
// Reads the ID code
task ReadIDCode;
begin
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftDR
 
P_TDI<=#Tp 0;
GenClk(31);
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // tri-state
GenClk(1);
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
end
endtask
 
 
// Reads sample from the Trace Buffer
task ReadTraceBuffer;
begin
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftDR
 
P_TDI<=#Tp 0;
GenClk(47);
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // tri-state
GenClk(1);
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
end
endtask
 
 
// Reads the RISC register and latches the data so it is ready for reading
task ReadRISCRegister;
input [31:0] Address;
input [7:0] Crc;
integer i;
begin
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftDR
 
for(i=0; i<32; i=i+1)
begin
P_TDI<=#Tp Address[i]; // Shifting address
GenClk(1);
end
 
P_TDI<=#Tp 0; // shifting RW bit = read
GenClk(1);
 
for(i=0; i<32; i=i+1)
begin
P_TDI<=#Tp 0; // Shifting data. Data is not important in read cycle.
GenClk(1);
end
 
for(i=0; i<`CRC_LENGTH-1; i=i+1)
begin
P_TDI<=#Tp Crc[i]; // Shifting CRC.
GenClk(1);
end
 
P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC.
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // Tristate TDI.
GenClk(1);
 
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
end
endtask
 
 
// Write the RISC register
task WriteRISCRegister;
input [31:0] Data;
input [31:0] Address;
input [`CRC_LENGTH-1:0] Crc;
integer i;
begin
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftDR
 
for(i=0; i<32; i=i+1)
begin
P_TDI<=#Tp Address[i]; // Shifting address
GenClk(1);
end
 
P_TDI<=#Tp 1; // shifting RW bit = write
GenClk(1);
 
for(i=0; i<32; i=i+1)
begin
P_TDI<=#Tp Data[i]; // Shifting data
GenClk(1);
end
 
for(i=0; i<`CRC_LENGTH-1; i=i+1)
begin
P_TDI<=#Tp Crc[i]; // Shifting CRC
GenClk(1);
end
 
P_TDI<=#Tp Crc[i]; // shifting last bit of CRC
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // tristate TDI
GenClk(1);
 
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
 
GenClk(10); // Generating few clock cycles needed for the write operation to accomplish
end
endtask
 
 
// Reads the register and latches the data so it is ready for reading
task ReadRegister;
input [4:0] Address;
input [7:0] Crc;
integer i;
begin
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftDR
 
for(i=0; i<5; i=i+1)
begin
P_TDI<=#Tp Address[i]; // Shifting address
GenClk(1);
end
 
P_TDI<=#Tp 0; // shifting RW bit = read
GenClk(1);
 
for(i=0; i<32; i=i+1)
begin
P_TDI<=#Tp 0; // Shifting data. Data is not important in read cycle.
GenClk(1);
end
 
for(i=0; i<`CRC_LENGTH-1; i=i+1)
begin
P_TDI<=#Tp Crc[i]; // Shifting CRC. CRC is not important in read cycle.
GenClk(1);
end
 
P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC.
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // Tri state TDI
GenClk(1);
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
 
GenClk(10); // Generating few clock cycles needed for the read operation to accomplish
end
endtask
 
// Write the register
task WriteRegister;
input [31:0] Data;
input [4:0] Address;
input [`CRC_LENGTH-1:0] Crc;
integer i;
begin
P_TMS<=#Tp 1;
GenClk(1);
P_TMS<=#Tp 0;
GenClk(2); // we are in shiftDR
 
for(i=0; i<5; i=i+1)
begin
P_TDI<=#Tp Address[i]; // Shifting address
GenClk(1);
end
 
P_TDI<=#Tp 1; // shifting RW bit = write
GenClk(1);
 
for(i=0; i<32; i=i+1)
begin
P_TDI<=#Tp Data[i]; // Shifting data
GenClk(1);
end
for(i=0; i<`CRC_LENGTH-1; i=i+1)
begin
P_TDI<=#Tp Crc[i]; // Shifting CRC
GenClk(1);
end
 
P_TDI<=#Tp Crc[i]; // Shifting last bit of CRC
P_TMS<=#Tp 1; // going out of shiftIR
GenClk(1);
P_TDI<=#Tp 'hz; // Tri state TDI
GenClk(1);
 
P_TMS<=#Tp 0;
GenClk(1); // we are in RunTestIdle
end
endtask
 
 
 
/**********************************************************************************
* *
* Printing the information to the screen *
* *
**********************************************************************************/
 
// Print samples that are recorded to the trace buffer
`ifdef TRACE_ENABLED
always @ (posedge Mclk)
begin
if(dbg_tb.dbgTAP1.dbgTrace1.WriteSample)
$write("\n\tWritten to Trace buffer: WritePointer=0x%x, Data=0x%x", dbg_tb.dbgTAP1.dbgTrace1.WritePointer, {dbg_tb.dbgTAP1.dbgTrace1.RISC_DATA_IN, 1'b0, dbg_tb.dbgTAP1.dbgTrace1.OpSelect[`OPSELECTWIDTH-1:0]});
end
`endif
 
 
// Print selected instruction
reg UpdateIR_q;
always @ (posedge P_TCK)
begin
UpdateIR_q<=#Tp dbg_tb.dbgTAP1.UpdateIR;
end
 
always @ (posedge P_TCK)
begin
if(UpdateIR_q)
case(dbg_tb.dbgTAP1.JTAG_IR[`IR_LENGTH-1:0])
`EXTEST : $write("\n\tInstruction EXTEST");
`SAMPLE_PRELOAD : $write("\n\tInstruction SAMPLE_PRELOAD");
`IDCODE : $write("\n\tInstruction IDCODE");
`CHAIN_SELECT : $write("\n\tInstruction CHAIN_SELECT");
`INTEST : $write("\n\tInstruction INTEST");
`CLAMP : $write("\n\tInstruction CLAMP");
`CLAMPZ : $write("\n\tInstruction CLAMPZ");
`HIGHZ : $write("\n\tInstruction HIGHZ");
`DEBUG : $write("\n\tInstruction DEBUG");
`BYPASS : $write("\n\tInstruction BYPASS");
default : $write("\n\tInstruction not valid. Instruction BYPASS activated !!!");
endcase
end
 
 
 
// Print selected chain
always @ (posedge P_TCK)
begin
if(dbg_tb.dbgTAP1.CHAIN_SELECTSelected & dbg_tb.dbgTAP1.UpdateDR_q)
case(dbg_tb.dbgTAP1.Chain[`CHAIN_ID_LENGTH-1:0])
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
`RISC_DEBUG_CHAIN : $write("\nChain RISC_DEBUG_CHAIN");
`RISC_TEST_CHAIN : $write("\nChain RISC_TEST_CHAIN");
`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
endcase
end
 
 
// print RISC registers read/write
always @ (posedge Mclk)
begin
if(dbg_tb.dbgTAP1.RISC_CS)
if(dbg_tb.dbgTAP1.RISC_RW)
begin
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
end
else
begin
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.RISC_DATA_IN[31:0]);
end
end
 
 
// print registers read/write
always @ (posedge Mclk)
begin
if(dbg_tb.dbgTAP1.RegAccess_q & ~dbg_tb.dbgTAP1.RegAccess_q2)
begin
if(dbg_tb.dbgTAP1.RW)
$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.DataOut[31:0]);
else
$write("\n\t\tRead from Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[4:0], dbg_tb.dbgTAP1.RegDataIn[31:0]);
end
end
 
 
// print CRC error
`ifdef TRACE_ENABLED
wire CRCErrorReport = ~(dbg_tb.dbgTAP1.CrcMatch & (dbg_tb.dbgTAP1.CHAIN_SELECTSelected | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RegisterScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RiscDebugScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.TraceTestScanChain));
`else // TRACE_ENABLED not enabled
wire CRCErrorReport = ~(dbg_tb.dbgTAP1.CrcMatch & (dbg_tb.dbgTAP1.CHAIN_SELECTSelected | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RegisterScanChain | dbg_tb.dbgTAP1.DEBUGSelected & dbg_tb.dbgTAP1.RiscDebugScanChain));
`endif
 
always @ (posedge P_TCK)
begin
if(dbg_tb.dbgTAP1.UpdateDR & ~dbg_tb.dbgTAP1.IDCODESelected)
begin
if(dbg_tb.dbgTAP1.CHAIN_SELECTSelected)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.dbgTAP1.JTAG_DR_IN[11:4], dbg_tb.dbgTAP1.CalculatedCrcOut[`CRC_LENGTH-1:0]);
else
if(dbg_tb.dbgTAP1.RegisterScanChain & ~dbg_tb.dbgTAP1.CHAIN_SELECTSelected)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.dbgTAP1.JTAG_DR_IN[45:38], dbg_tb.dbgTAP1.CalculatedCrcOut[`CRC_LENGTH-1:0]);
else
if(dbg_tb.dbgTAP1.RiscDebugScanChain & ~dbg_tb.dbgTAP1.CHAIN_SELECTSelected)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.dbgTAP1.JTAG_DR_IN[72:65], dbg_tb.dbgTAP1.CalculatedCrcOut[`CRC_LENGTH-1:0]);
 
if(CRCErrorReport)
begin
$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! Crc should be: 0x%h\n", dbg_tb.dbgTAP1.CalculatedCrcIn);
#1000 $stop;
end
end
end
 
 
// Print shifted IDCode
reg [31:0] TempData;
always @ (posedge P_TCK)
begin
if(dbg_tb.dbgTAP1.IDCODESelected)
begin
if(dbg_tb.dbgTAP1.ShiftDR)
TempData[31:0]<=#Tp {dbg_tb.dbgTAP1.TDOData, TempData[31:1]};
else
if(dbg_tb.dbgTAP1.UpdateDR)
$write("\n\t\tIDCode = 0x%h", TempData[31:0]);
end
end
 
 
// Print data from the trace buffer
reg [47:0] TraceData;
always @ (posedge P_TCK)
begin
if(dbg_tb.dbgTAP1.DEBUGSelected & (dbg_tb.dbgTAP1.Chain==`TRACE_TEST_CHAIN))
begin
if(dbg_tb.dbgTAP1.ShiftDR)
TraceData[47:0]<=#Tp {dbg_tb.dbgTAP1.TDOData, TraceData[47:1]};
else
if(dbg_tb.dbgTAP1.UpdateDR)
$write("\n\t\TraceData = 0x%h + Crc = 0x%h", TraceData[39:0], TraceData[47:40]);
end
end
 
 
endmodule // TB
 
 
/trunk/bench/verilog/file_communication.v
0,0 → 1,170
//////////////////////////////////////////////////////////////////////
//// ////
//// File_communication.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
//
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
`include "dbg_tb_defines.v"
 
module File_communication();
 
parameter Tp = 1;
 
integer handle1, handle2;
reg [3:0] memory[0:0];
reg Mclk;
reg P_PowerONReset;
 
reg StartTesting;
wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;
 
 
initial
begin
StartTesting = 0;
P_PowerONReset = 1;
#500;
P_PowerONReset = 0;
#500;
P_PowerONReset = 1;
// handle2 = $fopen("file1.out");
#1000;
// $fdisplay(handle2 | 1, "\n\nDa vidimo, ce ta shit dela OK.");
#1000;
// $fclose(handle2);
// $display("Memory = 0x%0x", memory[0]);
// handle1 = $fopen("file1.in");
// $fdisplay(handle2 | 1, "\n\nDa vidimo, ce dela shit od pisanja nazaj v prvi file OK.");
// $fclose(handle1);
// $fclose(handle2);
StartTesting = 1;
$display("StartTesting = 1");
 
 
end
 
initial
begin
wait(StartTesting);
while(1)
begin
#1000;
$readmemh("E:\\tmp\\out.txt", memory);
// handle2 = $fopen("E:\\tmp\\in.txt");
// $fdisplay(handle2 | 1, "%b", P_TDO); // Vpisem TDO v file
// $fclose(handle2);
#1000;
// handle1 = $fopen("E:\\tmp\\out.txt");
// handle2 = $fopen("E:\\tmp\\in.txt");
// handle1 = $fopen("E:\\tmp\\out.txt");
// $display("TDO = 0x%0x", P_TDO);
// $fdisplay(handle1 | 1, " "); // zbrisem Markov podatek
// $fclose(handle1);
end
end
 
 
always @ (posedge P_TCK)
begin
handle2 = $fopen("E:\\tmp\\in.txt");
// $fdisplay(handle2 | 1, "%b, %t", P_TDO, $time); // Vpisem TDO v file
$fdisplay(handle2 | 1, "%b", P_TDO); // Vpisem TDO v file
// $fdisplay(handle2 | 1, "%t", $time); // Vpisem TDO v file
$fclose(handle2);
end
 
 
 
 
wire [3:0]Temp = memory[0];
 
assign P_TCK = Temp[0];
assign P_TRST = Temp[1];
assign P_TDI = Temp[2];
assign P_TMS = Temp[3];
 
 
 
// Generating master clock (RISC clock) 10 MHz
initial
begin
Mclk<=#Tp 0;
#1 forever #`RISC_CLOCK Mclk<=~Mclk;
end
 
// Generating random number for use in DATAOUT_RISC[31:0]
reg [31:0] RandNumb;
always @ (posedge Mclk or negedge P_PowerONReset) // PowerONReset is active low
begin
if(~P_PowerONReset)
RandNumb[31:0]<=#Tp 0;
else
RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
end
 
wire [31:0] DataIn = RandNumb;
 
// Connecting dbgTAP module
dbg_top dbg1 (.P_TMS(P_TMS), .P_TCK(P_TCK), .P_TRST(P_TRST), .P_TDI(P_TDI), .P_TDO(P_TDO),
.P_PowerONReset(P_PowerONReset), .Mclk(Mclk), .RISC_ADDR(), .RISC_DATA_IN(DataIn),
.RISC_DATA_OUT(), .RISC_CS(), .RISC_RW(), .Wp(11'h0), .Bp(1'b0),
.OpSelect(), .LsStatus(4'h0), .IStatus(2'h0)
);
 
 
 
 
endmodule // TAP
/trunk/rtl/verilog/dbg_sync_clk1_clk2.v
0,0 → 1,142
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_sync_clk1_clk2.v ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
//
 
`include "dbg_timescale.v"
 
// FF in clock domain 1 is being set by a signal from the clock domain 2
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
 
parameter Tp = 1;
 
input clk1;
input clk2;
input reset1;
input reset2;
input set2;
 
output sync_out;
 
reg set2_q;
reg set2_q2;
reg set1_q;
reg set1_q2;
reg clear2_q;
reg clear2_q2;
reg sync_out;
 
wire z;
 
assign z = set2 | set2_q & ~clear2_q2;
 
 
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q <=#Tp 1'b0;
else
set2_q <=#Tp z;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q2 <=#Tp 1'b0;
else
set2_q2 <=#Tp set2_q;
end
 
 
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q <=#Tp 1'b0;
else
set1_q <=#Tp set2_q2;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q2 <=#Tp 1'b0;
else
set1_q2 <=#Tp set1_q;
end
 
 
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q <=#Tp 1'b0;
else
clear2_q <=#Tp set1_q2;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q2 <=#Tp 1'b0;
else
clear2_q2 <=#Tp clear2_q;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
sync_out <=#Tp 1'b0;
else
sync_out <=#Tp set1_q2;
end
 
endmodule
/trunk/rtl/verilog/dbg_top.v
0,0 → 1,1222
// Potrebno narediti STALL procesorja pri read-u in write-u
 
// Potrebno racunati crc kadar je izbran trace. Ko delamo read iz bufferja
// Dodati registre RISCOP
 
 
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_top.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
// Initial release
//
//
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
// Top module
module dbg_top(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO, P_PowerONReset, Mclk, RISC_ADDR, RISC_DATA_IN,
RISC_DATA_OUT, RISC_CS, RISC_RW, Wp, Bp, OpSelect, LsStatus, IStatus
);
 
parameter Tp = 1;
 
input P_TMS, P_TCK;
input P_TRST, P_TDI;
input P_PowerONReset;
input Mclk; // High speed clock (RISC clock)
input [31:0] RISC_DATA_IN;
input [10:0] Wp;
input Bp;
input [3:0] LsStatus;
input [1:0] IStatus;
 
output P_TDO;
output [31:0] RISC_ADDR;
output [31:0] RISC_DATA_OUT;
output [`OPSELECTWIDTH-1:0] OpSelect;
output RISC_CS; // CS for accessing RISC registers
output RISC_RW; // RW for accessing RISC registers
 
reg [31:0] RISC_ADDR;
reg [31:0] ADDR;
reg [31:0] RISC_DATA_OUT;
reg [31:0] DataOut;
 
wire TCK = P_TCK;
wire TMS = P_TMS;
wire TDI = P_TDI;
wire TRST= ~P_TRST; // P_TRST is active low
wire PowerONReset = ~P_PowerONReset; // PowerOnReset is active low
 
reg TestLogicReset;
reg RunTestIdle;
reg SelectDRScan;
reg CaptureDR;
reg ShiftDR;
reg Exit1DR;
reg PauseDR;
reg Exit2DR;
reg UpdateDR;
 
reg SelectIRScan;
reg CaptureIR;
reg ShiftIR;
reg Exit1IR;
reg PauseIR;
reg Exit2IR;
reg UpdateIR;
 
reg EXTESTSelected;
reg SAMPLE_PRELOADSelected;
reg IDCODESelected;
reg CHAIN_SELECTSelected;
reg INTESTSelected;
reg CLAMPSelected;
reg CLAMPZSelected;
reg HIGHZSelected;
reg DEBUGSelected;
reg BYPASSSelected;
 
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
reg [31:0] RISC_DATAINLatch; // Data from DataIn is latched one Mclk clock cycle after RISC register is
// accessed for reading
reg [31:0] RegisterReadLatch; // Data when reading register is latched one TCK clock after the register is read.
 
wire[31:0] RegDataIn; // Data from registers (read data)
reg RegAccessTck; // Indicates access to the registers (read or write)
reg RISCAccessTck; // Indicates access to the RISC (read or write)
 
wire[`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
 
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
reg RW; // Read/Write bit
 
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
 
 
 
 
`ifdef TRACE_ENABLED
wire [39:0] TraceChain; // Chain that comes from trace module
reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with TCK)
reg ReadBuffer_Mclk; // Command for incrementing the trace read pointer (synchr with MClk)
reg DisableReadBuffer_Mclk; // Incrementing trace read buffer can be active for one MClk clock. Then it is disabled.
 
// Outputs from registers
wire ContinMode;
wire TraceEnable;
wire RecSelDepend;
wire [10:0] WpTrigger;
wire BpTrigger;
wire [3:0] LSSTrigger;
wire [1:0] ITrigger;
wire [1:0] TriggerOper;
wire WpTriggerValid;
wire BpTriggerValid;
wire LSSTriggerValid;
wire ITriggerValid;
wire [10:0] WpQualif;
wire BpQualif;
wire [3:0] LSSQualif;
wire [1:0] IQualif;
wire [1:0] QualifOper;
wire WpQualifValid;
wire BpQualifValid;
wire LSSQualifValid;
wire IQualifValid;
wire [10:0] WpStop;
wire BpStop;
wire [3:0] LSSStop;
wire [1:0] IStop;
wire [1:0] StopOper;
wire WpStopValid;
wire BpStopValid;
wire LSSStopValid;
wire IStopValid;
wire [10:0] RecordPC_Wp;
wire [10:0] RecordLSEA_Wp;
wire [10:0] RecordLDATA_Wp;
wire [10:0] RecordSDATA_Wp;
wire [10:0] RecordReadSPR_Wp;
wire [10:0] RecordWriteSPR_Wp;
wire [10:0] RecordINSTR_Wp;
wire RecordPC_Bp;
wire RecordLSEA_Bp;
wire RecordLDATA_Bp;
wire RecordSDATA_Bp;
wire RecordReadSPR_Bp;
wire RecordWriteSPR_Bp;
wire RecordINSTR_Bp;
// End: Outputs from registers
 
wire TraceTestScanChain; // Trace Test Scan chain selected
 
wire [47:0] Trace_Data;
 
`endif
 
 
 
wire RegisterScanChain; // Register Scan chain selected
wire RiscDebugScanChain; // Risc Debug Scan chain selected
 
 
/**********************************************************************************
* *
* TAP State Machine: Fully JTAG compliant *
* *
**********************************************************************************/
wire RESET = TRST | PowerONReset;
 
// TestLogicReset state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
TestLogicReset<=#Tp 1;
else
begin
if(TMS & (TestLogicReset | SelectIRScan))
TestLogicReset<=#Tp 1;
else
TestLogicReset<=#Tp 0;
end
end
 
// RunTestIdle state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
RunTestIdle<=#Tp 0;
else
begin
if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
RunTestIdle<=#Tp 1;
else
RunTestIdle<=#Tp 0;
end
end
 
// SelectDRScan state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
SelectDRScan<=#Tp 0;
else
begin
if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
SelectDRScan<=#Tp 1;
else
SelectDRScan<=#Tp 0;
end
end
 
// CaptureDR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
CaptureDR<=#Tp 0;
else
begin
if(~TMS & SelectDRScan)
CaptureDR<=#Tp 1;
else
CaptureDR<=#Tp 0;
end
end
 
// ShiftDR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
ShiftDR<=#Tp 0;
else
begin
if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
ShiftDR<=#Tp 1;
else
ShiftDR<=#Tp 0;
end
end
 
// Exit1DR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
Exit1DR<=#Tp 0;
else
begin
if(TMS & (CaptureDR | ShiftDR))
Exit1DR<=#Tp 1;
else
Exit1DR<=#Tp 0;
end
end
 
// PauseDR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
PauseDR<=#Tp 0;
else
begin
if(~TMS & (Exit1DR | PauseDR))
PauseDR<=#Tp 1;
else
PauseDR<=#Tp 0;
end
end
 
// Exit2DR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
Exit2DR<=#Tp 0;
else
begin
if(TMS & PauseDR)
Exit2DR<=#Tp 1;
else
Exit2DR<=#Tp 0;
end
end
 
// UpdateDR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
UpdateDR<=#Tp 0;
else
begin
if(TMS & (Exit1DR | Exit2DR))
UpdateDR<=#Tp 1;
else
UpdateDR<=#Tp 0;
end
end
 
reg UpdateDR_q;
always @ (posedge TCK)
begin
UpdateDR_q<=#Tp UpdateDR;
end
 
 
// SelectIRScan state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
SelectIRScan<=#Tp 0;
else
begin
if(TMS & SelectDRScan)
SelectIRScan<=#Tp 1;
else
SelectIRScan<=#Tp 0;
end
end
 
// CaptureIR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
CaptureIR<=#Tp 0;
else
begin
if(~TMS & SelectIRScan)
CaptureIR<=#Tp 1;
else
CaptureIR<=#Tp 0;
end
end
 
// ShiftIR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
ShiftIR<=#Tp 0;
else
begin
if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
ShiftIR<=#Tp 1;
else
ShiftIR<=#Tp 0;
end
end
 
// Exit1IR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
Exit1IR<=#Tp 0;
else
begin
if(TMS & (CaptureIR | ShiftIR))
Exit1IR<=#Tp 1;
else
Exit1IR<=#Tp 0;
end
end
 
// PauseIR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
PauseIR<=#Tp 0;
else
begin
if(~TMS & (Exit1IR | PauseIR))
PauseIR<=#Tp 1;
else
PauseIR<=#Tp 0;
end
end
 
// Exit2IR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
Exit2IR<=#Tp 0;
else
begin
if(TMS & PauseIR)
Exit2IR<=#Tp 1;
else
Exit2IR<=#Tp 0;
end
end
 
// UpdateIR state
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
UpdateIR<=#Tp 0;
else
begin
if(TMS & (Exit1IR | Exit2IR))
UpdateIR<=#Tp 1;
else
UpdateIR<=#Tp 0;
end
end
 
/**********************************************************************************
* *
* End: TAP State Machine *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* JTAG_IR: JTAG Instruction Register *
* *
**********************************************************************************/
wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
reg TDOInstruction;
 
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
else
begin
if(CaptureIR)
begin
JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection
JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
end
else
begin
if(ShiftIR)
begin
JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};
end
end
end
end
 
 
//TDO is changing on the falling edge of TCK
always @ (negedge TCK)
begin
if(ShiftIR)
TDOInstruction <= #Tp JTAG_IR[0];
end
/**********************************************************************************
* *
* End: JTAG_IR *
* *
**********************************************************************************/
 
 
/**********************************************************************************
* *
* JTAG_DR: JTAG Data Register *
* *
**********************************************************************************/
wire [31:0] IDCodeValue = `IDCODE_VALUE; // IDCODE value is 32-bit long.
 
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
reg TDOData;
 
 
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
else
if(ShiftDR)
JTAG_DR_IN[BitCounter]<=#Tp TDI;
end
 
wire [72:0] RISC_Data;
wire [45:0] Register_Data;
 
assign RISC_Data = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
assign Register_Data = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
 
`ifdef TRACE_ENABLED
assign Trace_Data = {CalculatedCrcOut, TraceChain};
`endif
 
//TDO is changing on the falling edge of TCK
always @ (negedge TCK or posedge RESET)
begin
if(RESET)
begin
TDOData <= #Tp 0;
`ifdef TRACE_ENABLED
ReadBuffer_Tck<=#Tp 0;
`endif
end
else
if(UpdateDR)
begin
TDOData <= #Tp CrcMatch;
`ifdef TRACE_ENABLED
if(DEBUGSelected & TraceTestScanChain & TraceChain[0]) // Sample is valid
ReadBuffer_Tck<=#Tp 1; // Increment read pointer
`endif
end
else
begin
if(ShiftDR)
begin
if(IDCODESelected)
TDOData <= #Tp IDCodeValue[BitCounter];
else
if(CHAIN_SELECTSelected)
TDOData <= #Tp 0;
else
if(DEBUGSelected)
begin
if(RiscDebugScanChain)
TDOData <= #Tp RISC_Data[BitCounter];
else
if(RegisterScanChain)
TDOData <= #Tp Register_Data[BitCounter];
`ifdef TRACE_ENABLED
else
if(TraceTestScanChain)
TDOData <= #Tp Trace_Data[BitCounter];
`endif
end
end
else
begin
TDOData <= #Tp 0;
`ifdef TRACE_ENABLED
ReadBuffer_Tck<=#Tp 0;
`endif
end
end
end
 
/**********************************************************************************
* *
* End: JTAG_DR *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* CHAIN_SELECT logic *
* *
**********************************************************************************/
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;
else
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];
end
 
 
 
/**********************************************************************************
* *
* Register read/write logic *
* RISC registers read/write logic *
* *
**********************************************************************************/
 
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
begin
ADDR[31:0] <=#Tp 32'h0;
DataOut[31:0] <=#Tp 32'h0;
RW <=#Tp 1'b0;
RegAccessTck <=#Tp 1'b0;
RISCAccessTck <=#Tp 1'b0;
end
else
if(UpdateDR & DEBUGSelected & CrcMatch)
begin
if(RegisterScanChain)
begin
ADDR[4:0] <=#Tp JTAG_DR_IN[4:0]; // Latching address for register access
RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
RegAccessTck <=#Tp 1'b1;
end
else
if(RiscDebugScanChain)
begin
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
RISCAccessTck <=#Tp 1'b1;
end
end
else
begin
RegAccessTck <=#Tp 1'b0; // This signals are valid for one TCK clock period only
RISCAccessTck <=#Tp 1'b0;
end
end
 
integer ii, jj, kk;
// Relocating bits because RISC works in big endian mode
always @(ADDR)
begin
for(ii=0; ii<32; ii=ii+1)
RISC_ADDR[ii] = ADDR[31-ii];
end
 
 
// Relocating bits because RISC works in big endian mode
always @(DataOut)
begin
for(jj=0; jj<32; jj=jj+1)
RISC_DATA_OUT[jj] = DataOut[31-jj];
end
 
// Synchronizing the RegAccess signal to Mclk clock
dbg_sync_clk1_clk2 syn1 (.clk1(Mclk), .clk2(TCK), .reset1(RESET), .reset2(RESET),
.set2(RegAccessTck), .sync_out(RegAccess)
);
 
// Synchronizing the RISCAccess signal to Mclk clock
dbg_sync_clk1_clk2 syn2 (.clk1(Mclk), .clk2(TCK), .reset1(RESET), .reset2(RESET),
.set2(RISCAccessTck), .sync_out(RISCAccess)
);
 
reg RegAccess_q;
reg RegAccess_q2;
reg RISCAccess_q;
reg RISCAccess_q2;
 
always @ (posedge Mclk or posedge RESET)
begin
if(RESET)
begin
RegAccess_q <=#Tp 1'b0;
RegAccess_q2 <=#Tp 1'b0;
RISCAccess_q <=#Tp 1'b0;
RISCAccess_q2 <=#Tp 1'b0;
end
else
begin
RegAccess_q <=#Tp RegAccess;
RegAccess_q2 <=#Tp RegAccess_q;
RISCAccess_q <=#Tp RISCAccess;
RISCAccess_q2 <=#Tp RISCAccess_q;
end
end
 
// Latching data read from registers
always @ (posedge Mclk or posedge RESET)
begin
if(RESET)
RegisterReadLatch[31:0]<=#Tp 0;
else
if(RegAccess_q & ~RegAccess_q2)
RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
end
 
 
assign RISC_CS = RISCAccess & ~RISCAccess_q;
assign RISC_RW = RW;
 
 
reg [31:0] RISC_DATA_IN_TEMP;
// Latching data read from RISC
always @ (posedge Mclk or posedge RESET)
begin
if(RESET)
RISC_DATAINLatch[31:0]<=#Tp 0;
else
if(RISCAccess_q & ~RISCAccess_q2)
RISC_DATAINLatch[31:0]<=#Tp RISC_DATA_IN_TEMP[31:0];
end
 
 
// Relocating bits because RISC works in big endian mode
always @(RISC_DATA_IN)
begin
for(kk=0; kk<32; kk=kk+1)
RISC_DATA_IN_TEMP[kk] = RISC_DATA_IN[31-kk];
end
 
 
 
/**********************************************************************************
* *
* Read Trace buffer logic *
* *
**********************************************************************************/
`ifdef TRACE_ENABLED
wire Reset_ReadBuffer_Mclk = ReadBuffer_Mclk | DisableReadBuffer_Mclk | RESET;
always @(posedge Mclk)
begin
if(Reset_ReadBuffer_Mclk)
ReadBuffer_Mclk<=#Tp 0;
else
if(ReadBuffer_Tck)
ReadBuffer_Mclk<=#Tp 1;
end
always @(posedge Mclk)
begin
if(ReadBuffer_Mclk)
DisableReadBuffer_Mclk<=#Tp 1;
else
if(~ReadBuffer_Tck)
DisableReadBuffer_Mclk<=#Tp 0;
end
`endif
 
/**********************************************************************************
* *
* End: Read Trace buffer logic *
* *
**********************************************************************************/
 
 
/**********************************************************************************
* *
* Bypass logic *
* *
**********************************************************************************/
reg BypassRegister;
reg TDOBypassed;
 
always @ (posedge TCK)
begin
if(ShiftDR)
BypassRegister<=#Tp TDI;
end
 
always @ (negedge TCK)
begin
TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
* *
* End: Bypass logic *
* *
**********************************************************************************/
 
 
/**********************************************************************************
* *
* Multiplexing TDO and Tristate control *
* *
**********************************************************************************/
wire TDOShifted;
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
 
reg TDOMuxed;
 
 
// Tristate control for P_TDO pin
assign P_TDO = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
 
 
/**********************************************************************************
* *
* End: Multiplexing TDO and Tristate control *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* Activating Instructions *
* *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 1; // After reset IDCODE is selected
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
else
begin
if(UpdateIR)
begin
case(JTAG_IR)
`EXTEST: // External test
begin
EXTESTSelected<=#Tp 1;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`SAMPLE_PRELOAD: // Sample preload
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 1;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`IDCODE: // ID Code
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 1;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`CHAIN_SELECT: // Chain select
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 1;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`INTEST: // Internal test
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 1;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`CLAMP: // Clamp
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 1;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`CLAMPZ: // ClampZ
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 1;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`HIGHZ: // High Z
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 1;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 0;
end
`DEBUG: // Debug
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 1;
BYPASSSelected<=#Tp 0;
end
`BYPASS: // BYPASS
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 1;
end
default: // BYPASS
begin
EXTESTSelected<=#Tp 0;
SAMPLE_PRELOADSelected<=#Tp 0;
IDCODESelected<=#Tp 0;
CHAIN_SELECTSelected<=#Tp 0;
INTESTSelected<=#Tp 0;
CLAMPSelected<=#Tp 0;
CLAMPZSelected<=#Tp 0;
HIGHZSelected<=#Tp 0;
DEBUGSelected<=#Tp 0;
BYPASSSelected<=#Tp 1;
end
endcase
end
end
end
 
 
// This multiplexing can be expanded with number of user registers
always @ (JTAG_IR or TDOShifted or TDOBypassed)
begin
case(JTAG_IR)
`IDCODE: // Reading ID code
begin
TDOMuxed<=#Tp TDOShifted;
end
`CHAIN_SELECT: // Selecting the chain
begin
TDOMuxed<=#Tp TDOShifted;
end
`DEBUG: // Debug
begin
TDOMuxed<=#Tp TDOShifted;
end
// SAMPLE_PRELOAD: // Sampling/Preloading
// begin
// TDOMuxed<=#Tp ExitFromBSCell[`BSLength-1];
// end
// EXTEST: // External test
// begin
// TDOMuxed<=#Tp ExitFromBSCell[`BSLength-1];
// end
default: // BYPASS instruction
begin
TDOMuxed<=#Tp TDOBypassed;
end
endcase
end
 
 
/**********************************************************************************
* *
* End: Activating Instructions *
* *
**********************************************************************************/
 
/**********************************************************************************
* *
* Bit counter *
* *
**********************************************************************************/
 
 
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
BitCounter[7:0]<=#Tp 0;
else
if(ShiftDR)
BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
else
if(UpdateDR)
BitCounter[7:0]<=#Tp 0;
end
 
 
 
/**********************************************************************************
* *
* End: Bit counter *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* Connecting Registers *
* *
**********************************************************************************/
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
.Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(Mclk),
.Reset(PowerONReset)
`ifdef TRACE_ENABLED
,
.ContinMode(ContinMode), .TraceEnable(TraceEnable), .RecSelDepend(RecSelDepend),
.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
.QualifOper(QualifOper), .RecordPC_Wp(RecordPC_Wp),
.RecordLSEA_Wp(RecordLSEA_Wp), .RecordLDATA_Wp(RecordLDATA_Wp),
.RecordSDATA_Wp(RecordSDATA_Wp), .RecordReadSPR_Wp(RecordReadSPR_Wp),
.RecordWriteSPR_Wp(RecordWriteSPR_Wp), .RecordINSTR_Wp(RecordINSTR_Wp),
.RecordPC_Bp(RecordPC_Bp), .RecordLSEA_Bp(RecordLSEA_Bp),
.RecordLDATA_Bp(RecordLDATA_Bp), .RecordSDATA_Bp(RecordSDATA_Bp),
.RecordReadSPR_Bp(RecordReadSPR_Bp), .RecordWriteSPR_Bp(RecordWriteSPR_Bp),
.RecordINSTR_Bp(RecordINSTR_Bp), .WpTriggerValid(WpTriggerValid),
.BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
.ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
.BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
.IQualifValid(IQualifValid),
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
.S topOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
`endif
);
 
/**********************************************************************************
* *
* End: Connecting Registers *
* *
**********************************************************************************/
 
 
/**********************************************************************************
* *
* Connecting CRC module *
* *
**********************************************************************************/
wire ResetCrc = RESET | UpdateDR_q; // igor !!! Ta asinhroni reset popraviti
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
 
wire EnableCrcIn = ShiftDR &
( (CHAIN_SELECTSelected & (BitCounter<4)) |
((DEBUGSelected & RegisterScanChain) & (BitCounter<38)) |
((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65))
);
 
wire EnableCrcOut= ShiftDR &
// ( (CHAIN_SELECTSelected & (BitCounter<4)) | Crc is not generated because crc of data that is equal to 0 is 0.
(
((DEBUGSelected & RegisterScanChain) & (BitCounter<38)) |
((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65))
`ifdef TRACE_ENABLED
|
((DEBUGSelected & TraceTestScanChain) & (BitCounter<40))
`endif
);
 
// Calculating crc for input data
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .ResetCrc(ResetCrc),
.CrcOut(CalculatedCrcIn), .Clk(TCK));
 
// Calculating crc for output data
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .ResetCrc(ResetCrc),
.CrcOut(CalculatedCrcOut), .Clk(TCK));
 
 
// Generating CrcMatch signal
always @ (posedge TCK or posedge RESET)
begin
if(RESET)
CrcMatch <=#Tp 1'b0;
else
if(Exit1DR)
begin
if(CHAIN_SELECTSelected)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
else
if(RegisterScanChain & ~CHAIN_SELECTSelected)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
else
if(RiscDebugScanChain & ~CHAIN_SELECTSelected)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
end
end
 
 
// Active chain
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
assign RiscDebugScanChain = Chain == `RISC_DEBUG_CHAIN;
 
`ifdef TRACE_ENABLED
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
`endif
 
/**********************************************************************************
* *
* End: Connecting CRC module *
* *
**********************************************************************************/
 
/**********************************************************************************
* *
* Connecting trace module *
* *
**********************************************************************************/
`ifdef TRACE_ENABLED
dbg_trace dbgTrace1(.Wp(Wp), .Bp(Bp), .DataIn(DataIn), .OpSelect(OpSelect),
.LsStatus(LsStatus), .IStatus(IStatus), .CpuStall(CpuStall),
.Mclk(Mclk), .Reset(RESET), .TraceChain(TraceChain),
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
.RecSelDepend(RecSelDepend), .WpTrigger(WpTrigger),
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
.RecordPC_Wp(RecordPC_Wp), .RecordLSEA_Wp(RecordLSEA_Wp),
.RecordLDATA_Wp(RecordLDATA_Wp), .RecordSDATA_Wp(RecordSDATA_Wp),
.RecordReadSPR_Wp(RecordReadSPR_Wp), .RecordWriteSPR_Wp(RecordWriteSPR_Wp),
.RecordINSTR_Wp(RecordINSTR_Wp), .RecordPC_Bp(RecordPC_Bp),
.RecordLSEA_Bp(RecordLSEA_Bp), .RecordLDATA_Bp(RecordLDATA_Bp),
.RecordSDATA_Bp(RecordSDATA_Bp), .RecordReadSPR_Bp(RecordReadSPR_Bp),
.RecordWriteSPR_Bp(RecordWriteSPR_Bp), .RecordINSTR_Bp(RecordINSTR_Bp),
.WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
.LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
.WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
.LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
.ReadBuffer(ReadBuffer_Mclk),
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
);
`endif
/**********************************************************************************
* *
* End: Connecting trace module *
* *
**********************************************************************************/
 
 
 
endmodule // TAP
/trunk/rtl/verilog/dbg_crc8_d1.v
0,0 → 1,140
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_crc8_d1 crc1.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/06/01 22:22:36 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:03 mohor
// Initial release
//
//
///////////////////////////////////////////////////////////////////////
// File: CRC8_D1.v
// Date: Fri Apr 27 20:56:55 2001
//
// Copyright (C) 1999 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 8)
// * data width: 1
//
// Info: jand@easics.be (Jan Decaluwe)
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
 
module dbg_crc8_d1 (Data, EnableCrc, ResetCrc, CrcOut, Clk);
 
parameter Tp = 1;
 
 
input Data;
input EnableCrc;
input ResetCrc;
input Clk;
 
 
output [7:0] CrcOut;
reg [7:0] CrcOut;
 
 
always @ (posedge Clk or posedge ResetCrc)
begin
if(ResetCrc)
CrcOut[7:0] <= #Tp 0;
else
if(EnableCrc)
CrcOut[7:0] <= #Tp nextCRC8_D1(Data, CrcOut);
end
 
 
// polynomial: (0 1 2 8)
// data width: 1
function [7:0] nextCRC8_D1;
 
input Data;
input [7:0] Crc;
reg [0:0] D;
reg [7:0] C;
reg [7:0] NewCRC;
begin
D[0] = Data;
C = Crc;
NewCRC[0] = D[0] ^ C[7];
NewCRC[1] = D[0] ^ C[0] ^ C[7];
NewCRC[2] = D[0] ^ C[1] ^ C[7];
NewCRC[3] = C[2];
NewCRC[4] = C[3];
NewCRC[5] = C[4];
NewCRC[6] = C[5];
NewCRC[7] = C[6];
nextCRC8_D1 = NewCRC;
end
endfunction
 
endmodule
 
 
 
/trunk/rtl/verilog/dbg_register.v
0,0 → 1,83
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_register.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
//
 
`include "dbg_timescale.v"
 
module dbg_register(DataIn, DataOut, Write, Clk, Reset, Default);
 
parameter WIDTH = 8; // default parameter of the register width
 
input [WIDTH-1:0] DataIn;
 
input Write;
input Clk;
input Reset;
input [WIDTH-1:0] Default;
 
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
 
//always @ (posedge Clk or posedge Reset)
always @ (posedge Clk)
begin
if(Reset)
DataOut[WIDTH-1:0]<=#1 Default;
else
begin
if(Write) // write
DataOut[WIDTH-1:0]<=#1 DataIn[WIDTH-1:0];
end
end
 
 
endmodule // Register
 
/trunk/rtl/verilog/dbg_timescale.v
0,0 → 1,54
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_timescale.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
//
 
 
`timescale 1ns / 1ns
/trunk/rtl/verilog/dbg_registers.v
0,0 → 1,427
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_registers.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:10 mohor
// Initial release
//
//
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Reset
`ifdef TRACE_ENABLED
,
ContinMode,
TraceEnable, RecSelDepend, WpTrigger, BpTrigger, LSSTrigger,
ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
QualifOper, RecordPC_Wp, RecordLSEA_Wp, RecordLDATA_Wp,
RecordSDATA_Wp, RecordReadSPR_Wp, RecordReadSPR_Bp,
RecordWriteSPR_Wp, RecordWriteSPR_Bp, RecordINSTR_Wp, RecordPC_Bp,
RecordLSEA_Bp, RecordLDATA_Bp, RecordSDATA_Bp, RecordINSTR_Bp,
WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
LSSStopValid, IStopValid
`endif
);
 
parameter Tp = 1;
 
input [31:0] DataIn;
input [4:0] Address;
 
input RW;
input Access;
input Clk;
input Reset;
 
output [31:0] DataOut;
reg [31:0] DataOut;
 
`ifdef TRACE_ENABLED
output RecSelDepend;
output ContinMode;
output TraceEnable;
output [10:0] WpTrigger;
output BpTrigger;
output [3:0] LSSTrigger;
output [1:0] ITrigger;
output [1:0] TriggerOper;
output WpTriggerValid;
output BpTriggerValid;
output LSSTriggerValid;
output ITriggerValid;
output [10:0] WpQualif;
output BpQualif;
output [3:0] LSSQualif;
output [1:0] IQualif;
output [1:0] QualifOper;
output WpQualifValid;
output BpQualifValid;
output LSSQualifValid;
output IQualifValid;
output [10:0] WpStop;
output BpStop;
output [3:0] LSSStop;
output [1:0] IStop;
output [1:0] StopOper;
output WpStopValid;
output BpStopValid;
output LSSStopValid;
output IStopValid;
output [10:0] RecordPC_Wp;
output [10:0] RecordLSEA_Wp;
output [10:0] RecordLDATA_Wp;
output [10:0] RecordSDATA_Wp;
output [10:0] RecordReadSPR_Wp;
output [10:0] RecordWriteSPR_Wp;
output [10:0] RecordINSTR_Wp;
output RecordPC_Bp;
output RecordLSEA_Bp;
output RecordLDATA_Bp;
output RecordSDATA_Bp;
output RecordReadSPR_Bp;
output RecordWriteSPR_Bp;
output RecordINSTR_Bp;
`endif
 
`ifdef TRACE_ENABLED
wire MODER_Acc = (Address == `MODER_ADR) & Access;
wire TSEL_Acc = (Address == `TSEL_ADR) & Access;
wire QSEL_Acc = (Address == `QSEL_ADR) & Access;
wire SSEL_Acc = (Address == `SSEL_ADR) & Access;
wire RECWP0_Acc = (Address == `RECWP0_ADR) & Access;
wire RECWP1_Acc = (Address == `RECWP1_ADR) & Access;
wire RECWP2_Acc = (Address == `RECWP2_ADR) & Access;
wire RECWP3_Acc = (Address == `RECWP3_ADR) & Access;
wire RECWP4_Acc = (Address == `RECWP4_ADR) & Access;
wire RECWP5_Acc = (Address == `RECWP5_ADR) & Access;
wire RECWP6_Acc = (Address == `RECWP6_ADR) & Access;
wire RECWP7_Acc = (Address == `RECWP7_ADR) & Access;
wire RECWP8_Acc = (Address == `RECWP8_ADR) & Access;
wire RECWP9_Acc = (Address == `RECWP9_ADR) & Access;
wire RECWP10_Acc = (Address == `RECWP10_ADR) & Access;
wire RECBP0_Acc = (Address == `RECBP0_ADR) & Access;
wire MODER_Wr = MODER_Acc & RW;
wire TSEL_Wr = TSEL_Acc & RW;
wire QSEL_Wr = QSEL_Acc & RW;
wire SSEL_Wr = SSEL_Acc & RW;
wire RECWP0_Wr = RECWP0_Acc & RW;
wire RECWP1_Wr = RECWP1_Acc & RW;
wire RECWP2_Wr = RECWP2_Acc & RW;
wire RECWP3_Wr = RECWP3_Acc & RW;
wire RECWP4_Wr = RECWP4_Acc & RW;
wire RECWP5_Wr = RECWP5_Acc & RW;
wire RECWP6_Wr = RECWP6_Acc & RW;
wire RECWP7_Wr = RECWP7_Acc & RW;
wire RECWP8_Wr = RECWP8_Acc & RW;
wire RECWP9_Wr = RECWP9_Acc & RW;
wire RECWP10_Wr = RECWP10_Acc & RW;
wire RECBP0_Wr = RECBP0_Acc & RW;
wire MODER_Rd = MODER_Acc & ~RW;
wire TSEL_Rd = TSEL_Acc & ~RW;
wire QSEL_Rd = QSEL_Acc & ~RW;
wire SSEL_Rd = SSEL_Acc & ~RW;
wire RECWP0_Rd = RECWP0_Acc & ~RW;
wire RECWP1_Rd = RECWP1_Acc & ~RW;
wire RECWP2_Rd = RECWP2_Acc & ~RW;
wire RECWP3_Rd = RECWP3_Acc & ~RW;
wire RECWP4_Rd = RECWP4_Acc & ~RW;
wire RECWP5_Rd = RECWP5_Acc & ~RW;
wire RECWP6_Rd = RECWP6_Acc & ~RW;
wire RECWP7_Rd = RECWP7_Acc & ~RW;
wire RECWP8_Rd = RECWP8_Acc & ~RW;
wire RECWP9_Rd = RECWP9_Acc & ~RW;
wire RECWP10_Rd = RECWP10_Acc & ~RW;
wire RECBP0_Rd = RECBP0_Acc & ~RW;
`endif
 
 
`ifdef TRACE_ENABLED
wire [31:0] MODEROut;
wire [31:0] TSELOut;
wire [31:0] QSELOut;
wire [31:0] SSELOut;
wire [31:0] RECWP0Out;
wire [31:0] RECWP1Out;
wire [31:0] RECWP2Out;
wire [31:0] RECWP3Out;
wire [31:0] RECWP4Out;
wire [31:0] RECWP5Out;
wire [31:0] RECWP6Out;
wire [31:0] RECWP7Out;
wire [31:0] RECWP8Out;
wire [31:0] RECWP9Out;
wire [31:0] RECWP10Out;
wire [31:0] RECBP0Out;
`endif
 
 
`ifdef TRACE_ENABLED
dbg_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`MODER_DEF));
dbg_register #(32) TSEL (.DataIn(DataIn), .DataOut(TSELOut), .Write(TSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`TSEL_DEF));
dbg_register #(32) QSEL (.DataIn(DataIn), .DataOut(QSELOut), .Write(QSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`QSEL_DEF));
dbg_register #(32) SSEL (.DataIn(DataIn), .DataOut(SSELOut), .Write(SSEL_Wr), .Clk(Clk), .Reset(Reset), .Default(`SSEL_DEF));
dbg_register #(32) RECWP0 (.DataIn(DataIn), .DataOut(RECWP0Out), .Write(RECWP0_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP0_DEF));
dbg_register #(32) RECWP1 (.DataIn(DataIn), .DataOut(RECWP1Out), .Write(RECWP1_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP1_DEF));
dbg_register #(32) RECWP2 (.DataIn(DataIn), .DataOut(RECWP2Out), .Write(RECWP2_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP2_DEF));
dbg_register #(32) RECWP3 (.DataIn(DataIn), .DataOut(RECWP3Out), .Write(RECWP3_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP3_DEF));
dbg_register #(32) RECWP4 (.DataIn(DataIn), .DataOut(RECWP4Out), .Write(RECWP4_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP4_DEF));
dbg_register #(32) RECWP5 (.DataIn(DataIn), .DataOut(RECWP5Out), .Write(RECWP5_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP5_DEF));
dbg_register #(32) RECWP6 (.DataIn(DataIn), .DataOut(RECWP6Out), .Write(RECWP6_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP6_DEF));
dbg_register #(32) RECWP7 (.DataIn(DataIn), .DataOut(RECWP7Out), .Write(RECWP7_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP7_DEF));
dbg_register #(32) RECWP8 (.DataIn(DataIn), .DataOut(RECWP8Out), .Write(RECWP8_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP8_DEF));
dbg_register #(32) RECWP9 (.DataIn(DataIn), .DataOut(RECWP9Out), .Write(RECWP9_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP9_DEF));
dbg_register #(32) RECWP10(.DataIn(DataIn), .DataOut(RECWP10Out), .Write(RECWP10_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECWP10_DEF));
dbg_register #(32) RECBP0 (.DataIn(DataIn), .DataOut(RECBP0Out), .Write(RECBP0_Wr), .Clk(Clk), .Reset(Reset), .Default(`RECBP0_DEF));
`endif
 
 
`ifdef TRACE_ENABLED
always @ (posedge Clk)
begin
if(MODER_Rd) DataOut<= #Tp MODEROut;
else
if(TSEL_Rd) DataOut<= #Tp TSELOut;
else
if(QSEL_Rd) DataOut<= #Tp QSELOut;
else
if(SSEL_Rd) DataOut<= #Tp SSELOut;
else
if(RECWP0_Rd) DataOut<= #Tp RECWP0Out;
else
if(RECWP1_Rd) DataOut<= #Tp RECWP1Out;
else
if(RECWP2_Rd) DataOut<= #Tp RECWP2Out;
else
if(RECWP3_Rd) DataOut<= #Tp RECWP3Out;
else
if(RECWP4_Rd) DataOut<= #Tp RECWP4Out;
else
if(RECWP5_Rd) DataOut<= #Tp RECWP5Out;
else
if(RECWP6_Rd) DataOut<= #Tp RECWP6Out;
else
if(RECWP7_Rd) DataOut<= #Tp RECWP7Out;
else
if(RECWP8_Rd) DataOut<= #Tp RECWP8Out;
else
if(RECWP9_Rd) DataOut<= #Tp RECWP9Out;
else
if(RECWP10_Rd) DataOut<= #Tp RECWP10Out;
else
if(RECBP0_Rd) DataOut<= #Tp RECBP0Out;
else DataOut<= #Tp 'h0;
end
`endif
 
`ifdef TRACE_ENABLED
assign ContinMode = MODEROut[0];
assign TraceEnable = MODEROut[1];
assign RecSelDepend = MODEROut[2];
assign WpTrigger[10:0] = TSELOut[10:0];
assign WpTriggerValid = TSELOut[11];
assign BpTrigger = TSELOut[12];
assign BpTriggerValid = TSELOut[13];
assign LSSTrigger[3:0] = TSELOut[19:16];
assign LSSTriggerValid = TSELOut[20];
assign ITrigger[1:0] = TSELOut[22:21];
assign ITriggerValid = TSELOut[23];
assign TriggerOper[1:0] = TSELOut[31:30];
assign WpQualif[10:0] = QSELOut[10:0];
assign WpQualifValid = QSELOut[11];
assign BpQualif = QSELOut[12];
assign BpQualifValid = QSELOut[13];
assign LSSQualif[3:0] = QSELOut[19:16];
assign LSSQualifValid = QSELOut[20];
assign IQualif[1:0] = QSELOut[22:21];
assign IQualifValid = QSELOut[23];
assign QualifOper[1:0] = QSELOut[31:30];
assign WpStop[10:0] = SSELOut[10:0];
assign WpStopValid = SSELOut[11];
assign BpStop = SSELOut[12];
assign BpStopValid = SSELOut[13];
assign LSSStop[3:0] = SSELOut[19:16];
assign LSSStopValid = SSELOut[20];
assign IStop[1:0] = SSELOut[22:21];
assign IStopValid = SSELOut[23];
assign StopOper[1:0] = SSELOut[31:30];
assign RecordPC_Wp[0] = RECWP0Out[0];
assign RecordLSEA_Wp[0] = RECWP0Out[1];
assign RecordLDATA_Wp[0] = RECWP0Out[2];
assign RecordSDATA_Wp[0] = RECWP0Out[3];
assign RecordReadSPR_Wp[0] = RECWP0Out[4];
assign RecordWriteSPR_Wp[0] = RECWP0Out[5];
assign RecordINSTR_Wp[0] = RECWP0Out[6];
assign RecordPC_Wp[1] = RECWP1Out[0];
assign RecordLSEA_Wp[1] = RECWP1Out[1];
assign RecordLDATA_Wp[1] = RECWP1Out[2];
assign RecordSDATA_Wp[1] = RECWP1Out[3];
assign RecordReadSPR_Wp[1] = RECWP1Out[4];
assign RecordWriteSPR_Wp[1] = RECWP1Out[5];
assign RecordINSTR_Wp[1] = RECWP1Out[6];
assign RecordPC_Wp[2] = RECWP2Out[0];
assign RecordLSEA_Wp[2] = RECWP2Out[1];
assign RecordLDATA_Wp[2] = RECWP2Out[2];
assign RecordSDATA_Wp[2] = RECWP2Out[3];
assign RecordReadSPR_Wp[2] = RECWP2Out[4];
assign RecordWriteSPR_Wp[2] = RECWP2Out[5];
assign RecordINSTR_Wp[2] = RECWP2Out[6];
assign RecordPC_Wp[3] = RECWP3Out[0];
assign RecordLSEA_Wp[3] = RECWP3Out[1];
assign RecordLDATA_Wp[3] = RECWP3Out[2];
assign RecordSDATA_Wp[3] = RECWP3Out[3];
assign RecordReadSPR_Wp[3] = RECWP3Out[4];
assign RecordWriteSPR_Wp[3] = RECWP3Out[5];
assign RecordINSTR_Wp[3] = RECWP3Out[6];
assign RecordPC_Wp[4] = RECWP4Out[0];
assign RecordLSEA_Wp[4] = RECWP4Out[1];
assign RecordLDATA_Wp[4] = RECWP4Out[2];
assign RecordSDATA_Wp[4] = RECWP4Out[3];
assign RecordReadSPR_Wp[4] = RECWP4Out[4];
assign RecordWriteSPR_Wp[4] = RECWP4Out[5];
assign RecordINSTR_Wp[4] = RECWP4Out[6];
assign RecordPC_Wp[5] = RECWP5Out[0];
assign RecordLSEA_Wp[5] = RECWP5Out[1];
assign RecordLDATA_Wp[5] = RECWP5Out[2];
assign RecordSDATA_Wp[5] = RECWP5Out[3];
assign RecordReadSPR_Wp[5] = RECWP5Out[4];
assign RecordWriteSPR_Wp[5] = RECWP5Out[5];
assign RecordINSTR_Wp[5] = RECWP5Out[6];
assign RecordPC_Wp[6] = RECWP6Out[0];
assign RecordLSEA_Wp[6] = RECWP6Out[1];
assign RecordLDATA_Wp[6] = RECWP6Out[2];
assign RecordSDATA_Wp[6] = RECWP6Out[3];
assign RecordReadSPR_Wp[6] = RECWP6Out[4];
assign RecordWriteSPR_Wp[6] = RECWP6Out[5];
assign RecordINSTR_Wp[6] = RECWP6Out[6];
assign RecordPC_Wp[7] = RECWP7Out[0];
assign RecordLSEA_Wp[7] = RECWP7Out[1];
assign RecordLDATA_Wp[7] = RECWP7Out[2];
assign RecordSDATA_Wp[7] = RECWP7Out[3];
assign RecordReadSPR_Wp[7] = RECWP7Out[4];
assign RecordWriteSPR_Wp[7] = RECWP7Out[5];
assign RecordINSTR_Wp[7] = RECWP7Out[6];
assign RecordPC_Wp[8] = RECWP8Out[0];
assign RecordLSEA_Wp[8] = RECWP8Out[1];
assign RecordLDATA_Wp[8] = RECWP8Out[2];
assign RecordSDATA_Wp[8] = RECWP8Out[3];
assign RecordReadSPR_Wp[8] = RECWP8Out[4];
assign RecordWriteSPR_Wp[8] = RECWP8Out[5];
assign RecordINSTR_Wp[8] = RECWP8Out[6];
assign RecordPC_Wp[9] = RECWP9Out[0];
assign RecordLSEA_Wp[9] = RECWP9Out[1];
assign RecordLDATA_Wp[9] = RECWP9Out[2];
assign RecordSDATA_Wp[9] = RECWP9Out[3];
assign RecordReadSPR_Wp[9] = RECWP9Out[4];
assign RecordWriteSPR_Wp[9] = RECWP9Out[5];
assign RecordINSTR_Wp[9] = RECWP9Out[6];
assign RecordPC_Wp[10] = RECWP10Out[0];
assign RecordLSEA_Wp[10] = RECWP10Out[1];
assign RecordLDATA_Wp[10] = RECWP10Out[2];
assign RecordSDATA_Wp[10] = RECWP10Out[3];
assign RecordReadSPR_Wp[10] = RECWP10Out[4];
assign RecordWriteSPR_Wp[10] = RECWP10Out[5];
assign RecordINSTR_Wp[10] = RECWP10Out[6];
assign RecordPC_Bp = RECBP0Out[0];
assign RecordLSEA_Bp = RECBP0Out[1];
assign RecordLDATA_Bp = RECBP0Out[2];
assign RecordSDATA_Bp = RECBP0Out[3];
assign RecordReadSPR_Bp = RECBP0Out[4];
assign RecordWriteSPR_Bp = RECBP0Out[5];
assign RecordINSTR_Bp = RECBP0Out[6];
`endif
 
 
endmodule
/trunk/rtl/verilog/dbg_defines.v
0,0 → 1,157
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_defines.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
// Initial release
//
//
 
 
 
// Enable TRACE
//`define TRACE_ENABLED // Uncomment this define to activate the trace
 
 
// Define IDCODE Value
`define IDCODE_VALUE 32'hdeadbeef
 
// Define master clock (RISC clock)
`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
 
// Length of the Instruction register
`define IR_LENGTH 4
 
// Length of the Data register (must be equal to the longest scan chain)
`define DR_LENGTH 73
 
// Length of the CHAIN ID register
`define CHAIN_ID_LENGTH 4
 
// Length of the CRC
`define CRC_LENGTH 8
 
// Trace buffer size and counter and write/read pointer width
`define TRACECOUNTERWIDTH 10
`define TRACEBUFFERLENGTH 1024 //2^10
`define TRACESAMPLEWIDTH 36
 
// OpSelect width
`define OPSELECTWIDTH 3
`define OPSELECTIONCOUNTER 8 //2^3
 
// Supported Instructions
`define EXTEST 4'b0000
`define SAMPLE_PRELOAD 4'b0001
`define IDCODE 4'b0010
`define CHAIN_SELECT 4'b0011
`define INTEST 4'b0100
`define CLAMP 4'b0101
`define CLAMPZ 4'b0110
`define HIGHZ 4'b0111
`define DEBUG 4'b1000
`define BYPASS 4'b1111
 
// Chains
`define GLOBAL_BS_CHAIN 4'b0000
`define RISC_DEBUG_CHAIN 4'b0001
`define RISC_TEST_CHAIN 4'b0010
`define TRACE_TEST_CHAIN 4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100
 
 
// Registers addresses
`define MODER_ADR 5'h00
`define TSEL_ADR 5'h01
`define QSEL_ADR 5'h02
`define SSEL_ADR 5'h03
 
`define RECWP0_ADR 5'h10
`define RECWP1_ADR 5'h11
`define RECWP2_ADR 5'h12
`define RECWP3_ADR 5'h13
`define RECWP4_ADR 5'h14
`define RECWP5_ADR 5'h15
`define RECWP6_ADR 5'h16
`define RECWP7_ADR 5'h17
`define RECWP8_ADR 5'h18
`define RECWP9_ADR 5'h19
`define RECWP10_ADR 5'h1A
`define RECBP0_ADR 5'h1B
 
 
// Registers default values (after reset)
`define MODER_DEF 32'h00000000
`define TSEL_DEF 32'h00000000
`define QSEL_DEF 32'h00000000
`define SSEL_DEF 32'h00000000
 
`define RECWP0_DEF 32'h00000000
`define RECWP1_DEF 32'h00000000
`define RECWP2_DEF 32'h00000000
`define RECWP3_DEF 32'h00000000
`define RECWP4_DEF 32'h00000000
`define RECWP5_DEF 32'h00000000
`define RECWP6_DEF 32'h00000000
`define RECWP7_DEF 32'h00000000
`define RECWP8_DEF 32'h00000000
`define RECWP9_DEF 32'h00000000
`define RECWP10_DEF 32'h00000000
`define RECBP0_DEF 32'h00000000
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/dbg_trace.v
0,0 → 1,445
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_trace.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:06 mohor
// Initial release
//
//
 
 
`include "dbg_timescale.v"
`include "dbg_defines.v"
 
// module Trace
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, CpuStall,
Mclk, Reset, TraceChain, ContinMode, TraceEnable, RecSelDepend,
WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
BpQualif, LSSQualif, IQualif, QualifOper, RecordPC_Wp, RecordLSEA_Wp,
RecordLDATA_Wp, RecordSDATA_Wp, RecordReadSPR_Wp, RecordWriteSPR_Wp,
RecordINSTR_Wp, RecordPC_Bp, RecordLSEA_Bp, RecordLDATA_Bp,
RecordSDATA_Bp, RecordReadSPR_Bp, RecordWriteSPR_Bp, RecordINSTR_Bp,
WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
LSSStopValid, IStopValid
);
 
parameter Tp = 1;
 
 
input [10:0] Wp; // Watchpoints
input Bp; // Breakpoint
input [31:0] DataIn; // Data from the RISC
input [3:0] LsStatus; // Load/Store status
input [1:0] IStatus; // Instruction status
 
input Mclk; // Master clock (RISC clock)
input Reset; // Reset
input ReadBuffer;// Instruction for reading a sample from the Buffer
 
// from registers
input ContinMode;
input TraceEnable;
input RecSelDepend;
 
input [10:0] WpTrigger;
input BpTrigger;
input [3:0] LSSTrigger;
input [1:0] ITrigger;
input [1:0] TriggerOper;
 
input [10:0] WpQualif;
input BpQualif;
input [3:0] LSSQualif;
input [1:0] IQualif;
input [1:0] QualifOper;
 
input [10:0] WpStop;
input BpStop;
input [3:0] LSSStop;
input [1:0] IStop;
input [1:0] StopOper;
 
input [10:0] RecordPC_Wp;
input [10:0] RecordLSEA_Wp;
input [10:0] RecordLDATA_Wp;
input [10:0] RecordSDATA_Wp;
input [10:0] RecordReadSPR_Wp;
input [10:0] RecordWriteSPR_Wp;
input [10:0] RecordINSTR_Wp;
 
input RecordPC_Bp;
input RecordLSEA_Bp;
input RecordLDATA_Bp;
input RecordSDATA_Bp;
input RecordReadSPR_Bp;
input RecordWriteSPR_Bp;
input RecordINSTR_Bp;
 
input WpTriggerValid;
input BpTriggerValid;
input LSSTriggerValid;
input ITriggerValid;
 
input WpQualifValid;
input BpQualifValid;
input LSSQualifValid;
input IQualifValid;
 
input WpStopValid;
input BpStopValid;
input LSSStopValid;
input IStopValid;
// end: from registers
 
 
output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
output CpuStall; // CPU stall (stalls the RISC)
output [39:0] TraceChain; // Scan shain from the trace module
 
 
reg [`TRACECOUNTERWIDTH:0] Counter;
reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
reg CpuStall;
reg CpuStall_q;
reg [`OPSELECTWIDTH-1:0] StallCounter;
 
reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
 
reg TriggerLatch;
 
 
/**********************************************************************************
* *
* Generation of the trigger *
* *
**********************************************************************************/
wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
wire TempBpTrigger = Bp & BpTrigger;
wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
 
wire TempTriggerAND = ( (TempWpTrigger | ~WpTriggerValid)
& (TempBpTrigger | ~BpTriggerValid)
& (TempLSSTrigger | ~LSSTriggerValid)
& (TempITrigger | ~ITriggerValid)
)
& (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
 
wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)
| (TempBpTrigger & BpTriggerValid)
| (TempLSSTrigger & LSSTriggerValid)
| (TempITrigger & ITriggerValid)
);
 
wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any
TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR
);
 
/**********************************************************************************
* *
* Generation of the qualifier *
* *
**********************************************************************************/
wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
wire TempBpQualifier = Bp & BpQualif;
wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
 
wire TempQualifierAND = ( (TempWpQualifier | ~WpQualifValid)
& (TempBpQualifier | ~BpQualifValid)
& (TempLSSQualifier | ~LSSQualifValid)
& (TempIQualifier | ~IQualifValid)
)
& (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
 
wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)
| (TempBpQualifier & BpQualifValid)
| (TempLSSQualifier & LSSQualifValid)
| (TempIQualifier & IQualifValid)
);
 
 
wire Stop;
wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any
QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR
);
 
/**********************************************************************************
* *
* Generation of the stop signal *
* *
**********************************************************************************/
wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
wire TempBpStop = Bp & BpStop;
wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
wire TempIStop = IStatus[1:0] == IStop[1:0];
 
wire TempStopAND = ( (TempWpStop | ~WpStopValid)
& (TempBpStop | ~BpStopValid)
& (TempLSSStop | ~LSSStopValid)
& (TempIStop | ~IStopValid)
)
& (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
 
wire TempStopOR = ( (TempWpStop & WpStopValid)
| (TempBpStop & BpStopValid)
| (TempLSSStop & LSSStopValid)
| (TempIStop & IStopValid)
);
 
 
assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing
StopOper[0]? TempStopAND : TempStopOR // AND : OR
);
 
 
 
/**********************************************************************************
* *
* Generation of the TriggerLatch *
* *
**********************************************************************************/
wire Reset_TriggerLatch = Reset | TriggerLatch & ~TraceEnable;
always @(posedge Mclk or posedge Reset_TriggerLatch)
begin
if(Reset_TriggerLatch)
TriggerLatch<=#Tp 0;
else
if(Trigger)
TriggerLatch<=#Tp 1;
end
 
 
/**********************************************************************************
* *
* CpuStall, counter and pointers generation *
* *
**********************************************************************************/
reg BufferFullDetected;
reg [`OPSELECTIONCOUNTER-1:0] RecEnable;
 
wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
wire IncrementCounter = CpuStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = CpuStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
 
wire WriteSample = IncrementPointer;
 
wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
wire CounterEn = IncrementCounter ^ Decrement;
 
wire ResetCpuStall;
wire ResetStallCounter;
reg BufferFull_q;
reg BufferFull_2q;
 
reg Qualifier_mclk;
 
always @(posedge Mclk)
begin
Qualifier_mclk<=#Tp Qualifier;
BufferFull_q<=#Tp BufferFull;
BufferFull_2q<=#Tp BufferFull_q;
CpuStall_q <=#Tp CpuStall;
end
 
 
wire AsyncSetCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch | Qualifier_mclk & Trigger & ~TriggerLatch |
Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch;
 
 
wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
(
(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) |
( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
);
 
assign ResetCpuStall = (
(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
) | Reset;
 
 
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
Counter<=#Tp 0;
else
if(CounterEn)
if(IncrementCounter)
Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
else
Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
begin
WritePointer<=#Tp 0;
ReadPointer<=#Tp 0;
end
else
begin
if(IncrementPointer)
WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
// else igor !!! Probably else is missing here. Check it.
if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
else
if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
end
end
 
always @(posedge Mclk)
begin
if(~TraceEnable)
BufferFullDetected<=#Tp 0;
else
if(ContinMode & BufferFull)
BufferFullDetected<=#Tp 1;
end
 
 
always @(posedge Mclk or posedge AsyncSetCpuStall)
begin
if(AsyncSetCpuStall)
CpuStall<=#Tp 1;
else
if(SyncSetCpuStall)
CpuStall<=#Tp 1;
else
if(ResetCpuStall)
CpuStall<=#Tp 0;
end
 
 
always @(posedge Mclk)
begin
if(ResetStallCounter)
StallCounter<=#Tp 0;
else
if(CpuStall_q & (~BufferFull | ContinMode))
StallCounter<=#Tp StallCounter+1;
end
 
assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
 
 
/**********************************************************************************
* *
* Valid status *
* *
**********************************************************************************/
wire Valid = ~BufferEmpty;
 
 
/**********************************************************************************
* *
* Writing and reading the sample to/from the buffer *
* *
**********************************************************************************/
always @ (posedge Mclk)
begin
if(WriteSample)
Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
end
 
assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
 
 
/**********************************************************************************
* *
* Operation select (to select which kind of data appears on the DATAIN lines) *
* *
**********************************************************************************/
assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
 
 
 
/**********************************************************************************
* *
* Selecting which parts are going to be recorded as part of the sample *
* *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
RecEnable<=#Tp 0;
else
if(CpuStall)
begin
RecEnable<=#Tp {1'b0, RecordINSTR_Wp[0], RecordWriteSPR_Wp[0], RecordReadSPR_Wp[0], RecordSDATA_Wp[0], RecordLDATA_Wp[0], RecordLSEA_Wp[0], RecordPC_Wp[0]} & {`OPSELECTIONCOUNTER{Wp[0]}} |
{1'b0, RecordINSTR_Wp[1], RecordWriteSPR_Wp[1], RecordReadSPR_Wp[1], RecordSDATA_Wp[1], RecordLDATA_Wp[1], RecordLSEA_Wp[1], RecordPC_Wp[1]} & {`OPSELECTIONCOUNTER{Wp[1]}} |
{1'b0, RecordINSTR_Wp[2], RecordWriteSPR_Wp[2], RecordReadSPR_Wp[2], RecordSDATA_Wp[2], RecordLDATA_Wp[2], RecordLSEA_Wp[2], RecordPC_Wp[2]} & {`OPSELECTIONCOUNTER{Wp[2]}} |
{1'b0, RecordINSTR_Wp[3], RecordWriteSPR_Wp[3], RecordReadSPR_Wp[3], RecordSDATA_Wp[3], RecordLDATA_Wp[3], RecordLSEA_Wp[3], RecordPC_Wp[3]} & {`OPSELECTIONCOUNTER{Wp[3]}} |
{1'b0, RecordINSTR_Wp[4], RecordWriteSPR_Wp[4], RecordReadSPR_Wp[4], RecordSDATA_Wp[4], RecordLDATA_Wp[4], RecordLSEA_Wp[4], RecordPC_Wp[4]} & {`OPSELECTIONCOUNTER{Wp[4]}} |
{1'b0, RecordINSTR_Wp[5], RecordWriteSPR_Wp[5], RecordReadSPR_Wp[5], RecordSDATA_Wp[5], RecordLDATA_Wp[5], RecordLSEA_Wp[5], RecordPC_Wp[5]} & {`OPSELECTIONCOUNTER{Wp[5]}} |
{1'b0, RecordINSTR_Wp[6], RecordWriteSPR_Wp[6], RecordReadSPR_Wp[6], RecordSDATA_Wp[6], RecordLDATA_Wp[6], RecordLSEA_Wp[6], RecordPC_Wp[6]} & {`OPSELECTIONCOUNTER{Wp[6]}} |
{1'b0, RecordINSTR_Wp[7], RecordWriteSPR_Wp[7], RecordReadSPR_Wp[7], RecordSDATA_Wp[7], RecordLDATA_Wp[7], RecordLSEA_Wp[7], RecordPC_Wp[7]} & {`OPSELECTIONCOUNTER{Wp[7]}} |
{1'b0, RecordINSTR_Wp[8], RecordWriteSPR_Wp[8], RecordReadSPR_Wp[8], RecordSDATA_Wp[8], RecordLDATA_Wp[8], RecordLSEA_Wp[8], RecordPC_Wp[8]} & {`OPSELECTIONCOUNTER{Wp[8]}} |
{1'b0, RecordINSTR_Wp[9], RecordWriteSPR_Wp[9], RecordReadSPR_Wp[9], RecordSDATA_Wp[9], RecordLDATA_Wp[9], RecordLSEA_Wp[9], RecordPC_Wp[9]} & {`OPSELECTIONCOUNTER{Wp[9]}} |
{1'b0, RecordINSTR_Wp[10], RecordWriteSPR_Wp[10], RecordReadSPR_Wp[10], RecordSDATA_Wp[10], RecordLDATA_Wp[10], RecordLSEA_Wp[10], RecordPC_Wp[10]}& {`OPSELECTIONCOUNTER{Wp[10]}} |
{1'b0, RecordINSTR_Bp, RecordWriteSPR_Bp, RecordReadSPR_Bp, RecordSDATA_Bp, RecordLDATA_Bp, RecordLSEA_Bp, RecordPC_Bp} & {`OPSELECTIONCOUNTER{Bp}};
end
end
 
 
endmodule // Trace
/trunk/rtl/README.txt
0,0 → 1,107
//////////////////////////////////////////////////////////////////////
//// ////
//// README.txt ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in this README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.1 2001/05/18 13:12:09 mohor
// Header changed. All additional information is now avaliable in this README.txt file.
//
//
 
 
 
PROJECT:
SoC/OpenRISC Development (debug) Interface
 
 
PROJECT AND DOCUMENTATION ON THE WEB:
 
The project that this files are part of is avaliable on the opencores
web page:
 
http://www.opencores.org/cores/DebugInterface/
 
Documentation can also be found there. For direct download of the
documentation go to:
 
http://www.opencores.org/cgi-bin/cvsget.cgi/DebugInterface/Doc/DbgSupp.pdf
 
 
 
 
OVERVIEW (main Features):
Development Interface is used for development purposes
(Boundary Scan testing and debugging). It is an interface
between the RISC, peripheral cores and any commercial
debugger/emulator or BS testing device. The external
debugger or BS tester connects to the core via JTAG port.
The Development Port also contains a trace and support for
tracing the program flow, execution coverage and profiling
the code.
 
 
 
COMPATIBILITY:
 
- WISHBONE rev B.1
- IEEE 1149.1 (JTAG)
 
 
 
KNOWN PROBLEMS (limits):
- RISC changes Watchpoints and breakpoints on rising edge of the
Mclk clock signal. Simulation should do the same.
 
 
 
TO DO:
- Add reset and cpu stall signals that are related to the RISCOP register
- Add a WISHBONE master support
- Add support for boundary scan (This is already done, but not yet incorporated in the design)
- Signal RecSelDepend is not connected anywhere, yet. Read the pdf for details on that.
/trunk/sim/rtl_sim/run/file.do
0,0 → 1,26
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_crc8_d1.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_defines.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_register.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_registers.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_timescale.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v}
 
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/file_communication.v}
 
vsim work.File_communication
 
add wave -r -hexadecimal /*
.wave.tree zoomfull
 
 
 
 
 
 
#vsim work.File_communication
 
 
 
run -all
/trunk/sim/rtl_sim/run/do.do
0,0 → 1,18
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_crc8_d1.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_defines.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_register.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_registers.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_timescale.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v}
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v}
 
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb.v}
 
 
vsim work.dbg_tb
 
add wave -r -hexadecimal /*
.wave.tree zoomfull
 
run -all

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