OpenCores

0,0 → 1,193

trunk/README.developers Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/AUTHORS =================================================================== --- trunk/AUTHORS (nonexistent) +++ trunk/AUTHORS (revision 2) @@ -0,0 +1,5 @@ +ORIGINAL AUTHOR +~~~~~~~~~~~~~~~~ + +Peter J. Bleackley, BBC Research and Development +dirac@rd.bbc.co.uk \ No newline at end of file

trunk/AUTHORS Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/TODO =================================================================== --- trunk/TODO (nonexistent) +++ trunk/TODO (revision 2) @@ -0,0 +1,9 @@ +TO DO +~~~~~ + +Last updated 29 Nov 2004 + +The most current list can be found at +http://dirac.sourceforge.net/todo.html + +The list covers both software and algorithmic issues.

trunk/TODO Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/OUTPUT_UNIT.vhd =================================================================== --- trunk/src/encoder/OUTPUT_UNIT.vhd (nonexistent) +++ trunk/src/encoder/OUTPUT_UNIT.vhd (revision 2) @@ -0,0 +1,54 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity OUTPUT_UNIT is + Port ( ENABLE : in std_logic; + DATA : in std_logic; + FOLLOW : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic; + FOLLOW_COUNTER_TEST : out std_logic; + SHIFT : out std_logic); +end OUTPUT_UNIT; + +architecture RTL of OUTPUT_UNIT is + component D_TYPE + port(D,CLOCK: in std_logic; + Q: out std_logic); + end component D_TYPE; + signal OUTVALUE: std_logic; + signal DELAYED: std_logic; + signal NOFOLLOW: std_logic; + signal ACTIVE: std_logic; + signal FEEDBACK : std_logic; +begin + +-- combinatorial logic + + ACTIVE <= ENABLE and not (FEEDBACK or RESET); + OUTVALUE <= DATA xor FOLLOW; + NOFOLLOW <= not FOLLOW; + DATA_OUT <= ACTIVE and OUTVALUE; + FOLLOW_COUNTER_TEST <= DELAYED; + FEEDBACK <= DELAYED and NOFOLLOW; + SHIFT <= FEEDBACK; + SENDING <= ACTIVE; + +-- sequential logic + +FLIP_FLOP: D_TYPE + port map(D => ACTIVE, + CLOCK => CLOCK, + Q => DELAYED); + + +end RTL;

trunk/src/encoder/OUTPUT_UNIT.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/arithmeticcoder.prj =================================================================== --- trunk/src/encoder/arithmeticcoder.prj (nonexistent) +++ trunk/src/encoder/arithmeticcoder.prj (revision 2) @@ -0,0 +1,12 @@ +vhdl work ../common/D_TYPE.vhd +vhdl work ../common/COUNT_UNIT.vhd +vhdl work ../common/ENABLEABLE_D_TYPE.vhd +vhdl work ../common/FIFO.vhd +vhdl work ../common/INPUT_CONTROL.vhd +vhdl work ../common/STORE_BLOCK.vhd +vhdl work LIMIT_REGISTER.vhd +vhdl work ../common/ARITHMETIC_UNIT.vhd +vhdl work ../common/CONVERGENCE_CHECK.vhd +vhdl work FOLLOW_COUNTER.vhd +vhdl work OUTPUT_UNIT.vhd +vhdl work ARITHMETICCODER.vhd

trunk/src/encoder/arithmeticcoder.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/FOLLOW_COUNTER.vhd =================================================================== --- trunk/src/encoder/FOLLOW_COUNTER.vhd (nonexistent) +++ trunk/src/encoder/FOLLOW_COUNTER.vhd (revision 2) @@ -0,0 +1,170 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: FOLLOW_COUNTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FOLLOW_COUNTER is + Port ( INCREMENT : in std_logic; + TEST : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic); +end FOLLOW_COUNTER; + +architecture RTL of FOLLOW_COUNTER is + component COUNT_UNIT + port(INCREMENT: in std_logic; + DECREMENT: in std_logic; + RESET : in std_logic; + CLOCK: in std_logic; + OUTPUT: out std_logic; + INCREMENT_CARRY: out std_logic; + DECREMENT_CARRY: out std_logic); + end component COUNT_UNIT; + signal A,B,C,D,E,F,G,H: std_logic; + signal AB,CD,EF,GH: std_logic; + signal AD,EH: std_logic; + signal NONZERO: std_logic; + signal INC0,INC1,INC2,INC3,INC4,INC5,INC6,INC7: std_logic; + signal DEC0,DEC1,DEC2,DEC3,DEC4,DEC5,DEC6,DEC7: std_logic; + signal DECREMENT: std_logic; +begin + +-- detect non-zero result + + AB <= A or B; + CD <= C or D; + EF <= E or F; + GH <= G or H; + + AD <= AB or CD; + EH <= EF or GH; + + NONZERO <= AD or EH; + +-- Output + + OUTPUT <= DECREMENT; + +-- Feedback + + DECREMENT <= TEST and NONZERO; + +-- Sequential arithmetic + +COUNT0: COUNT_UNIT + port map(INCREMENT => INCREMENT, + DECREMENT => DECREMENT, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => A, + INCREMENT_CARRY => INC0, + DECREMENT_CARRY => DEC0); + +COUNT1: COUNT_UNIT + port map(INCREMENT => INC0, + DECREMENT => DEC0, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => B, + INCREMENT_CARRY => INC1, + DECREMENT_CARRY => DEC1); + +COUNT2: COUNT_UNIT + port map(INCREMENT => INC1, + DECREMENT => DEC1, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => C, + INCREMENT_CARRY => INC2, + DECREMENT_CARRY => DEC2); + +COUNT3: COUNT_UNIT + port map(INCREMENT => INC2, + DECREMENT => DEC2, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => D, + INCREMENT_CARRY => INC3, + DECREMENT_CARRY => DEC3); + +COUNT4: COUNT_UNIT + port map(INCREMENT => INC3, + DECREMENT => DEC3, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => E, + INCREMENT_CARRY => INC4, + DECREMENT_CARRY => DEC4); + +COUNT5: COUNT_UNIT + port map(INCREMENT => INC4, + DECREMENT => DEC4, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => F, + INCREMENT_CARRY => INC5, + DECREMENT_CARRY => DEC5); + +COUNT6: COUNT_UNIT + port map(INCREMENT => INC5, + DECREMENT => DEC5, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => G, + INCREMENT_CARRY => INC6, + DECREMENT_CARRY => DEC6); + +COUNT7: COUNT_UNIT + port map(INCREMENT => INC6, + DECREMENT => DEC6, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => H, + INCREMENT_CARRY => INC7, + DECREMENT_CARRY => DEC7); + + +end RTL;

trunk/src/encoder/FOLLOW_COUNTER.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/LIMIT_REGISTER.vhd =================================================================== --- trunk/src/encoder/LIMIT_REGISTER.vhd (nonexistent) +++ trunk/src/encoder/LIMIT_REGISTER.vhd (revision 2) @@ -0,0 +1,272 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: LIMIT_REGISTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity LIMIT_REGISTER is + generic(CONST : std_logic := '1'); + Port ( LOAD : in std_logic_vector(15 downto 0); + SET_VALUE : in std_logic; + SHIFT_ALL : in std_logic; + SHIFT_MOST : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic_vector(15 downto 0)); +end entity LIMIT_REGISTER; + +architecture RTL of LIMIT_REGISTER is + component STORE_BLOCK + port(LOAD_IN, SHIFT_IN, SHIFT, ENABLE, CLK: in std_logic; + OUTPUT: out std_logic); + end component STORE_BLOCK; + signal SHIFT_LSBS: std_logic; + signal SET_RESET: std_logic; + signal ENABLE_MSB: std_logic; + signal ENABLE_LSBS: std_logic; + signal D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15: std_logic; + signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15: std_logic; +begin + +-- control logic + SET_RESET <= SET_VALUE or RESET; + ENABLE_MSB <= SET_RESET or SHIFT_ALL; + SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST; + ENABLE_LSBS <= SET_RESET or SHIFT_LSBS; + +-- outputs + + OUTPUT(0) <= Q0; + OUTPUT(1) <= Q1; + OUTPUT(2) <= Q2; + OUTPUT(3) <= Q3; + OUTPUT(4) <= Q4; + OUTPUT(5) <= Q5; + OUTPUT(6) <= Q6; + OUTPUT(7) <= Q7; + OUTPUT(8) <= Q8; + OUTPUT(9) <= Q9; + OUTPUT(10) <= Q10; + OUTPUT(11) <= Q11; + OUTPUT(12) <= Q12; + OUTPUT(13) <= Q13; + OUTPUT(14) <= Q14; + OUTPUT(15) <= Q15; + +-- initialisation + +INIT: process(RESET,LOAD) +begin + if RESET = '1' then + D0 <= CONST; + D1 <= CONST; + D2 <= CONST; + D3 <= CONST; + D4 <= CONST; + D5 <= CONST; + D6 <= CONST; + D7 <= CONST; + D8 <= CONST; + D9 <= CONST; + D10 <= CONST; + D11 <= CONST; + D12 <= CONST; + D13 <= CONST; + D14 <= CONST; + D15 <= CONST; + else + D0 <= LOAD(0); + D1 <= LOAD(1); + D2 <= LOAD(2); + D3 <= LOAD(3); + D4 <= LOAD(4); + D5 <= LOAD(5); + D6 <= LOAD(6); + D7 <= LOAD(7); + D8 <= LOAD(8); + D9 <= LOAD(9); + D10 <= LOAD(10); + D11 <= LOAD(11); + D12 <= LOAD(12); + D13 <= LOAD(13); + D14 <= LOAD(14); + D15 <= LOAD(15); + end if; +end process INIT; + +-- storage + + STORE0: STORE_BLOCK + port map(LOAD_IN => D0, + SHIFT_IN => CONST, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q0); + + STORE1: STORE_BLOCK + port map(LOAD_IN => D1, + SHIFT_IN => Q0, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q1); + + STORE2: STORE_BLOCK + port map(LOAD_IN => D2, + SHIFT_IN => Q1, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q2); + + STORE3: STORE_BLOCK + port map(LOAD_IN => D3, + SHIFT_IN => Q2, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q3); + + STORE4: STORE_BLOCK + port map(LOAD_IN => D4, + SHIFT_IN => Q3, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q4); + + STORE5: STORE_BLOCK + port map(LOAD_IN => D5, + SHIFT_IN => Q4, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q5); + + STORE6: STORE_BLOCK + port map(LOAD_IN => D6, + SHIFT_IN => Q5, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q6); + + STORE7: STORE_BLOCK + port map(LOAD_IN => D7, + SHIFT_IN => Q6, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q7); + + STORE8: STORE_BLOCK + port map(LOAD_IN => D8, + SHIFT_IN => Q7, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q8); + + STORE9: STORE_BLOCK + port map(LOAD_IN => D9, + SHIFT_IN => Q8, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q9); + + STORE10: STORE_BLOCK + port map(LOAD_IN => D10, + SHIFT_IN => Q9, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q10); + + STORE11: STORE_BLOCK + port map(LOAD_IN => D11, + SHIFT_IN => Q10, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q11); + + STORE12: STORE_BLOCK + port map(LOAD_IN => D12, + SHIFT_IN => Q11, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q12); + + STORE13: STORE_BLOCK + port map(LOAD_IN => D13, + SHIFT_IN => Q12, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q13); + + STORE14: STORE_BLOCK + port map(LOAD_IN => D14, + SHIFT_IN => Q13, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q14); + + STORE15: STORE_BLOCK + port map(LOAD_IN => D15, + SHIFT_IN => Q14, + SHIFT => SHIFT_ALL, + ENABLE => ENABLE_MSB, + CLK => CLOCK, + OUTPUT => Q15); + + + +end architecture RTL; +

trunk/src/encoder/LIMIT_REGISTER.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/ARITHMETICCODER.vhd =================================================================== --- trunk/src/encoder/ARITHMETICCODER.vhd (nonexistent) +++ trunk/src/encoder/ARITHMETICCODER.vhd (revision 2) @@ -0,0 +1,286 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: ARITHMETICCODER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ARITHMETICCODER is + generic (PROB : std_logic_vector (9 downto 0) := "1010101010"); + Port ( ENABLE : in std_logic; + DATA_IN : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic); +end ARITHMETICCODER; + +architecture RTL of ARITHMETICCODER is + component D_TYPE + port(D: in std_logic; + CLOCK: in std_logic; + Q: out std_logic); + end component D_TYPE; + component INPUT_CONTROL + port( ENABLE : in std_logic; + DATA_IN : in std_logic; + BUFFER_CONTROL : in std_logic; + DEMAND : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic); + end component INPUT_CONTROL; + component LIMIT_REGISTER + generic(CONST: std_logic); + port( LOAD : in std_logic_vector(15 downto 0); + SET_VALUE : in std_logic; + SHIFT_ALL : in std_logic; + SHIFT_MOST : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic_vector(15 downto 0)); + end component LIMIT_REGISTER; + component FOLLOW_COUNTER + port ( INCREMENT : in std_logic; + TEST : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic); + end component FOLLOW_COUNTER; + component CONVERGENCE_CHECK + port ( HIGH_MSB : in std_logic; + LOW_MSB : in std_logic; + HIGH_SECONDBIT : in std_logic; + LOW_SECONDBIT : in std_logic; + CHECK : in std_logic; + TRIGGER_OUTPUT : out std_logic; + TRIGGER_FOLLOW : out std_logic); + end component CONVERGENCE_CHECK; + component ARITHMETIC_UNIT + port ( DIFFERENCE : in std_logic_vector(15 downto 0); + PROB : in std_logic_vector(9 downto 0); + LOW : in std_logic_vector(15 downto 0); + ENABLE : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0); + DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0); + RESULT_OUT0 : out std_logic_vector(15 downto 0); + RESULT_OUT1 : out std_logic_vector(15 downto 0); + DATA_LOAD : out std_logic); + end component ARITHMETIC_UNIT; + component OUTPUT_UNIT + port ( ENABLE : in std_logic; + DATA : in std_logic; + FOLLOW : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic; + FOLLOW_COUNTER_TEST : out std_logic; + SHIFT : out std_logic); + end component OUTPUT_UNIT; + signal HIGH_SET : std_logic; + signal LOW_SET : std_logic; + signal SHIFT_ALL : std_logic; + signal DIFFERENCE_SHIFT_ALL : std_logic; + signal SHIFT_MOST : std_logic; + signal ZERO_INPUT : std_logic; + signal ARITHMETIC_UNIT_ENABLE : std_logic; + signal ARITHMETIC_UNIT_DATA_LOAD : std_logic; + signal CONVERGENCE_TEST : std_logic; + signal TRIGGER_OUTPUT : std_logic; + signal FOLLOW_COUNTER_TEST : std_logic; + signal FOLLOW: std_logic; + signal DATA_LOAD: std_logic; + signal OUTPUT_ACTIVE : std_logic; + signal CHECK : std_logic; + signal DELAYED_CHECK : std_logic; + signal DATA_AVAILABLE : std_logic; + signal BUFFERED_DATA : std_logic; + signal BUFFER_INPUT : std_logic; + signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector (15 downto 0); + signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0); + signal DIFFERENCE_IN : std_logic_vector (15 downto 0); + signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0); + signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0); + signal DIFFERENCE_OUT : std_logic_vector (15 downto 0); + signal HIGH_OUT : std_logic_vector (15 downto 0); + signal LOW_OUT : std_logic_vector (15 downto 0); + +begin +-- input buffering +INBUFFER: INPUT_CONTROL + port map(ENABLE => ENABLE, + DATA_IN => DATA_IN, + BUFFER_CONTROL => BUFFER_INPUT, + DEMAND => ARITHMETIC_UNIT_DATA_LOAD, + RESET => RESET, + CLOCK => CLOCK, + SENDING => DATA_AVAILABLE, + DATA_OUT => BUFFERED_DATA); + +-- Specify the registers +HIGH: LIMIT_REGISTER + generic map(CONST => '1') + port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0, + SET_VALUE => HIGH_SET, + SHIFT_ALL => SHIFT_ALL, + SHIFT_MOST => SHIFT_MOST, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => HIGH_OUT); + +DIFFERENCE: LIMIT_REGISTER + generic map(CONST => '1') + port map( LOAD => DIFFERENCE_IN, + SET_VALUE => DATA_LOAD, + SHIFT_ALL => DIFFERENCE_SHIFT_ALL, + SHIFT_MOST => '0', + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => DIFFERENCE_OUT); + +LOW: LIMIT_REGISTER + generic map(CONST => '0') + port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1, + SET_VALUE => LOW_SET, + SHIFT_ALL => SHIFT_ALL, + SHIFT_MOST => SHIFT_MOST, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => LOW_OUT); + +-- The arithmetic + +ARITH: ARITHMETIC_UNIT + port map(DIFFERENCE => DIFFERENCE_OUT, + PROB => PROB, + LOW => LOW_OUT, + ENABLE => ARITHMETIC_UNIT_ENABLE, + RESET => RESET, + CLOCK => CLOCK, + DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0, + DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1, + RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0, + RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1, + DATA_LOAD => ARITHMETIC_UNIT_DATA_LOAD); + +--The convergence checks + +CONVERGE: CONVERGENCE_CHECK + port map(HIGH_MSB => HIGH_OUT(15), + LOW_MSB => LOW_OUT(15), + HIGH_SECONDBIT => HIGH_OUT(14), + LOW_SECONDBIT => LOW_OUT(14), + CHECK => CONVERGENCE_TEST, + TRIGGER_OUTPUT => TRIGGER_OUTPUT, + TRIGGER_FOLLOW => SHIFT_MOST); + +--The Follow Counter + +FC: FOLLOW_COUNTER + port map( INCREMENT => SHIFT_MOST, + TEST => FOLLOW_COUNTER_TEST, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => FOLLOW); + +--The output unit + +OUTPUT: OUTPUT_UNIT + port map(ENABLE => TRIGGER_OUTPUT, + DATA => HIGH_OUT(15), + FOLLOW => FOLLOW, + RESET => RESET, + CLOCK => CLOCK, + SENDING => OUTPUT_ACTIVE, + DATA_OUT => DATA_OUT, + FOLLOW_COUNTER_TEST => FOLLOW_COUNTER_TEST, + SHIFT => SHIFT_ALL); + + SENDING <= OUTPUT_ACTIVE; + +-- Input logic + + DATA_LOAD <= DATA_AVAILABLE and ARITHMETIC_UNIT_DATA_LOAD; + HIGH_SET <= ZERO_INPUT and DATA_LOAD; + ZERO_INPUT <= not BUFFERED_DATA; + LOW_SET <= BUFFERED_DATA and DATA_LOAD; + +-- Control logic for DIFFERENCE register + + DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST; + +-- Control logic for convergence check + + CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD; + +CONVERGENCE_TEST_DELAY: D_TYPE + port map( D => CHECK, + CLOCK => CLOCK, + Q => DELAYED_CHECK); + + CONVERGENCE_TEST <= DELAYED_CHECK or FOLLOW_COUNTER_TEST; + +-- Control logic for arithmetic unit + + ARITHMETIC_UNIT_ENABLE <= not(OUTPUT_ACTIVE or DIFFERENCE_SHIFT_ALL or DATA_LOAD); + +-- Control Logic for input control + + BUFFER_INPUT <= OUTPUT_ACTIVE or not ARITHMETIC_UNIT_DATA_LOAD; + +-- Select the new difference value + +NEWDIFF : process(BUFFERED_DATA,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1) + begin + if(BUFFERED_DATA = '1') then + DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1; + else + DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0; + end if; + end process NEWDIFF; + +end RTL;

trunk/src/encoder/ARITHMETICCODER.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/output_unit.prj =================================================================== --- trunk/src/encoder/output_unit.prj (nonexistent) +++ trunk/src/encoder/output_unit.prj (revision 2) @@ -0,0 +1,2 @@ +vhdl work ../common/D_TYPE.vhd +vhdl work OUTPUT_UNIT.vhd

trunk/src/encoder/output_unit.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/follow_counter.prj =================================================================== --- trunk/src/encoder/follow_counter.prj (nonexistent) +++ trunk/src/encoder/follow_counter.prj (revision 2) @@ -0,0 +1,3 @@ +vhdl work ../common/D_TYPE.vhd +vhdl work ../common/COUNT_UNIT.vhd +vhdl work ../common/FOLLOW_COUNTER.vhd

trunk/src/encoder/follow_counter.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/encoder/limit_register.prj =================================================================== --- trunk/src/encoder/limit_register.prj (nonexistent) +++ trunk/src/encoder/limit_register.prj (revision 2) @@ -0,0 +1,4 @@ +vhdl work ../common/D_TYPE.vhd +vhdl work ../common/ENABLEABLE_D_TYPE.vhd +vhdl work ../common/STORE_BLOCK.vhd +vhdl work REGISTER.vhd

trunk/src/encoder/limit_register.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/testbench/ArithmeticCoderTestbench.prj =================================================================== --- trunk/src/testbench/ArithmeticCoderTestbench.prj (nonexistent) +++ trunk/src/testbench/ArithmeticCoderTestbench.prj (revision 2) @@ -0,0 +1,16 @@ +vhdl work ../common/D_TYPE.vhd +vhdl work ../common/COUNT_UNIT.vhd +vhdl work ../common/ENABLEABLE_D_TYPE.vhd +vhdl work ../common/FIFO.vhd +vhdl work ../common/INPUT_CONTROL.vhd +vhdl work ../common/STORE_BLOCK.vhd +vhdl work ../encoder/LIMIT_REGISTER.vhd +vhdl work ../common/ARITHMETIC_UNIT.vhd +vhdl work ../common/CONVERGENCE_CHECK.vhd +vhdl work ../encoder/FOLLOW_COUNTER.vhd +vhdl work ../encoder/OUTPUT_UNIT.vhd +vhdl work ../encoder.ARITHMETICCODER.vhd +vhdl work ../decoder/STORAGE_REGISTER.vhd +vhdl work ../decoder/SYMBOL_DETECTOR.vhd +vhdl work ../decoder/ARITHMETICDECODER.vhd +vhdl work ArithmeticCoderTestbench.vhd \ No newline at end of file

trunk/src/testbench/ArithmeticCoderTestbench.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/testbench/raw_data =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/src/testbench/raw_data =================================================================== --- trunk/src/testbench/raw_data (nonexistent) +++ trunk/src/testbench/raw_data (revision 2)

trunk/src/testbench/raw_data Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/src/testbench/ArithmeticCoderTestbench.vhd =================================================================== --- trunk/src/testbench/ArithmeticCoderTestbench.vhd (nonexistent) +++ trunk/src/testbench/ArithmeticCoderTestbench.vhd (revision 2) @@ -0,0 +1,151 @@ + +-- VHDL Test Bench Created from source file arithmeticcoder.vhd -- 13:44:22 01/05/2005 +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +use IEEE.std_logic_textio.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use STD.textio.all; + +ENTITY arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS +END arithmeticcoder_ArithmeticCoderTestbench_vhd_tb; + +ARCHITECTURE behavior OF arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS + + COMPONENT arithmeticcoder + generic( + PROB : std_logic_vector (9 downto 0)); + PORT( + ENABLE : IN std_logic; + DATA_IN : IN std_logic; + CONTEXT_ENABLE : in std_logic; + CONTEXT_IN : in std_logic_vector (5 downto 0); + RESET : IN std_logic; + CLOCK : IN std_logic; + SENDING : OUT std_logic; + DATA_OUT : OUT std_logic + ); + END COMPONENT; + component ARITHMETICDECODER + generic( + PROB : std_logic_vector (9 downto 0)); + port (ENABLE : in std_logic; + DATA_IN : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic); + end component ARITHMETICDECODER; + + SIGNAL ENABLE : std_logic; + SIGNAL DATA_IN : std_logic := '0'; + SIGNAL RESET : std_logic; + SIGNAL CLOCK : std_logic := '0'; + SIGNAL SENDING : std_logic; + SIGNAL DATA_OUT : std_logic; + signal TRANSMIT : std_logic; + signal DATA_TRANSFER : std_logic; + constant PERIOD : time := 10 ns; + signal CONTEXT_ENABLE : std_logic; + signal CONTEXT : std_logic_vector (5 downto 0) := "000000"; + file TESTDATA : text is in ""; + file RESULTS : text is out "results"; + +BEGIN + + uut: arithmeticcoder + generic map( + PROB => "1110010000") + PORT MAP( + ENABLE => ENABLE, + DATA_IN => DATA_IN, + CONTEXT_ENABLE => CONTEXT_ENABLE, + CONTEXT_IN => CONTEXT, + RESET => RESET, + CLOCK => CLOCK, + SENDING => TRANSMIT, + DATA_OUT => DATA_TRANSFER + ); + + CLOCK <= not CLOCK after PERIOD/2; + + DECODER: ARITHMETICDECODER + generic map( + PROB => "1110010000") + port map( ENABLE => TRANSMIT, + DATA_IN => DATA_TRANSFER, + RESET => RESET, + CLOCK => CLOCK, + SENDING => SENDING, + DATA_OUT => DATA_OUT); + --*** Test Bench - User Defined Section *** + tb : PROCESS + variable GETLINE : line; + variable INDATA : std_logic; + BEGIN + for COUNT in 0 to 4194307 loop + wait until CLOCK'event and CLOCK = '1'; + if COUNT = 0 then + RESET <= '1'; + ENABLE <= '0'; + DATA_IN <= '0'; + elsif COUNT = 1 then + RESET <= '0'; + + elsif (COUNT - 2) mod 4 = 0 then + if (COUNT < 4194307) then + if (COUNT - 2) mod 128 = 0 then + readline(TESTDATA,GETLINE); + end if; + read(GETLINE,INDATA); + DATA_IN <= INDATA; + ENABLE <= '1'; + else + DATA_IN <= '1'; + ENABLE <= '1'; + end if; + + elsif COUNT < 4194307 then + ENABLE <= '0'; + else + wait; -- will wait forever + end if; + end loop; + END PROCESS; + + OUTPUT : process + variable OUTLINE : line; + begin + for WRITTEN in 0 to 1048576 loop + wait until CLOCK'event and CLOCK = '1' and SENDING = '1'; + if WRITTEN = 1048576 then + report "Process Complete" severity failure; + wait; + else + write(OUTLINE,DATA_OUT); + if (WRITTEN mod 32) = 31 then + writeline(RESULTS,OUTLINE); + end if; + end loop; + end process; + + +-- *** End Test Bench - User Defined Section *** + +COUNT_BITS: process (CLOCK, TRANSMIT) + variable BITS_SENT : integer range 0 to 1048576 := 0; + begin + if (CLOCK'event and CLOCK='1' and TRANSMIT='1') then + BITS_SENT := BITS_SENT+1; + end if; + end process; +END;

trunk/src/testbench/ArithmeticCoderTestbench.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/decoder/ARITHMETICDECODER.vhd =================================================================== --- trunk/src/decoder/ARITHMETICDECODER.vhd (nonexistent) +++ trunk/src/decoder/ARITHMETICDECODER.vhd (revision 2) @@ -0,0 +1,265 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: ARITHMETICDECODER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ARITHMETICDECODER is + generic (PROB : std_logic_vector (9 downto 0) := "1010101010"); + Port ( ENABLE : in std_logic; + DATA_IN : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic); +end ARITHMETICDECODER; + +architecture RTL of ARITHMETICDECODER is + component INPUT_CONTROL + port( ENABLE : in std_logic; + DATA_IN : in std_logic; + BUFFER_CONTROL : in std_logic; + DEMAND : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic); + end component INPUT_CONTROL; + component STORAGE_REGISTER + Port ( LOAD : in std_logic_vector(15 downto 0); + SHIFT_IN : in std_logic; + SET_VALUE : in std_logic; + SHIFT_ALL : in std_logic; + SHIFT_MOST : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic_vector(15 downto 0)); + end component STORAGE_REGISTER; + component CONVERGENCE_CHECK + port ( HIGH_MSB : in std_logic; + LOW_MSB : in std_logic; + HIGH_SECONDBIT : in std_logic; + LOW_SECONDBIT : in std_logic; + CHECK : in std_logic; + TRIGGER_OUTPUT : out std_logic; + TRIGGER_FOLLOW : out std_logic); + end component CONVERGENCE_CHECK; + component ARITHMETIC_UNIT + port ( DIFFERENCE : in std_logic_vector(15 downto 0); + PROB : in std_logic_vector(9 downto 0); + LOW : in std_logic_vector(15 downto 0); + ENABLE : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0); + DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0); + RESULT_OUT0 : out std_logic_vector(15 downto 0); + RESULT_OUT1 : out std_logic_vector(15 downto 0); + DATA_LOAD : out std_logic); + end component ARITHMETIC_UNIT; + component SYMBOL_DETECTOR + port ( ENABLE : in std_logic; + DATA_IN : in std_logic_vector (15 downto 0); + THRESHOLD : in std_logic_vector (15 downto 0); + DATA_OUT : out std_logic); + end component SYMBOL_DETECTOR; + signal HIGH_SET : std_logic; + signal LOW_SET : std_logic; + signal SHIFT_ALL : std_logic; + signal DIFFERENCE_SHIFT_ALL : std_logic; + signal SHIFT_MOST : std_logic; + signal ZERO_OUTPUT : std_logic; + signal ARITHMETIC_UNIT_ENABLE : std_logic; + signal CONVERGENCE_TEST : std_logic; + signal TRIGGER_INPUT : std_logic; + signal TRIGGER_FOLLOW: std_logic; + signal DATA_LOAD: std_logic; + signal GET_DATA : std_logic; + signal DATA_AVAILABLE : std_logic; + signal BUFFERED_DATA : std_logic; + signal SYMBOL : std_logic; + signal HOLD : std_logic; + signal DIFFERENCE_IN : std_logic_vector (15 downto 0); + signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0); + signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0); + signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector(15 downto 0); + signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0); + signal DIFFERENCE_VALUE : std_logic_vector (15 downto 0); + signal HIGH_VALUE : std_logic_vector (15 downto 0); + signal LOW_VALUE : std_logic_vector (15 downto 0); + signal CURRENT_VALUE : std_logic_vector (15 downto 0); + +begin +-- input buffering +INBUFFER: INPUT_CONTROL + port map(ENABLE => ENABLE, + DATA_IN => DATA_IN, + BUFFER_CONTROL => HOLD, + DEMAND => GET_DATA, + RESET => RESET, + CLOCK => CLOCK, + SENDING => DATA_AVAILABLE, + DATA_OUT => BUFFERED_DATA); + +-- Specify the registers + HIGH: STORAGE_REGISTER + port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0, + SHIFT_IN => '1', + SET_VALUE => HIGH_SET, + SHIFT_ALL => SHIFT_ALL, + SHIFT_MOST => SHIFT_MOST, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => HIGH_VALUE); + +LOW: STORAGE_REGISTER + port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1, + SHIFT_IN => '0', + SET_VALUE => LOW_SET, + SHIFT_ALL => SHIFT_ALL, + SHIFT_MOST => SHIFT_MOST, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => LOW_VALUE); + +DIFFERENCE: STORAGE_REGISTER + port map( LOAD => DIFFERENCE_IN, + SHIFT_IN => '1', + SET_VALUE => DATA_LOAD, + SHIFT_ALL => DIFFERENCE_SHIFT_ALL, + SHIFT_MOST => '0', + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => DIFFERENCE_VALUE); + +CURRENT: STORAGE_REGISTER + port map( LOAD => "0000000000000000", + SHIFT_IN => BUFFERED_DATA, + SET_VALUE => '0', + SHIFT_ALL => SHIFT_ALL, + SHIFT_MOST => SHIFT_MOST, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => CURRENT_VALUE); +-- The arithmetic + +ARITH: ARITHMETIC_UNIT + port map(DIFFERENCE => DIFFERENCE_VALUE, + PROB => PROB, + LOW => LOW_VALUE, + ENABLE => ARITHMETIC_UNIT_ENABLE, + RESET => RESET, + CLOCK => CLOCK, + DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0, + DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1, + RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0, + RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1, + DATA_LOAD => DATA_LOAD); + +--The convergence checks + +CONVERGE: CONVERGENCE_CHECK + port map(HIGH_MSB => HIGH_VALUE(15), + LOW_MSB => LOW_VALUE(15), + HIGH_SECONDBIT => HIGH_VALUE(14), + LOW_SECONDBIT => LOW_VALUE(14), + CHECK => CONVERGENCE_TEST, + TRIGGER_OUTPUT => TRIGGER_INPUT, + TRIGGER_FOLLOW => TRIGGER_FOLLOW); + +--The output unit + +OUTPUT: SYMBOL_DETECTOR + port map(ENABLE => DATA_LOAD, + DATA_IN => CURRENT_VALUE, + THRESHOLD => ARITHMETIC_UNIT_RESULT_OUT1, + DATA_OUT => SYMBOL); + + SENDING <= DATA_LOAD; + DATA_OUT <= SYMBOL; +-- Input logic + + HIGH_SET <= ZERO_OUTPUT and DATA_LOAD; + ZERO_OUTPUT <= not SYMBOL; + LOW_SET <= SYMBOL and DATA_LOAD; + GET_DATA <= TRIGGER_INPUT or TRIGGER_FOLLOW; + HOLD <= DATA_LOAD or not GET_DATA; + +-- Control logic for DIFFERENCE register + + DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST; + +-- Control logic for convergence check + +-- CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD or RESET; + +-- CONVERGENCE_TEST_DELAY: D_TYPE +-- port map( D => CHECK, +-- CLOCK => CLOCK, +-- Q => CONVERGENCE_TEST); + + CONVERGENCE_TEST <= not DATA_LOAD; + +-- Control logic for arithmetic unit + + ARITHMETIC_UNIT_ENABLE <= GET_DATA nor DATA_LOAD; + +-- Control Logic for input control + SHIFT_ALL <= TRIGGER_INPUT and DATA_AVAILABLE; + SHIFT_MOST <= TRIGGER_FOLLOW and DATA_AVAILABLE; + +--Select new difference value +NEWDIFF : process(SYMBOL,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1) + begin + if(SYMBOL = '1') then + DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1; + else + DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0; + end if; + end process NEWDIFF; + + + +end RTL;

trunk/src/decoder/ARITHMETICDECODER.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/decoder/storage_register.prj =================================================================== --- trunk/src/decoder/storage_register.prj (nonexistent) +++ trunk/src/decoder/storage_register.prj (revision 2) @@ -0,0 +1,2 @@ +vhdl work ../common/D_TYPE.vhd +vhdl work STORAGE_REGISTER.vhd

trunk/src/decoder/storage_register.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/decoder/STORAGE_REGISTER.vhd =================================================================== --- trunk/src/decoder/STORAGE_REGISTER.vhd (nonexistent) +++ trunk/src/decoder/STORAGE_REGISTER.vhd (revision 2) @@ -0,0 +1,272 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: STORAGE_REGISTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity STORAGE_REGISTER is + Port ( LOAD : in std_logic_vector(15 downto 0); + SHIFT_IN : in std_logic; + SET_VALUE : in std_logic; + SHIFT_ALL : in std_logic; + SHIFT_MOST : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic_vector(15 downto 0)); +end entity STORAGE_REGISTER; + +architecture RTL of STORAGE_REGISTER is + component STORE_BLOCK + port(LOAD_IN, SHIFT_IN, SHIFT, ENABLE, CLK: in std_logic; + OUTPUT: out std_logic); + end component STORE_BLOCK; + signal SHIFT_LSBS: std_logic; + signal SET_RESET: std_logic; + signal ENABLE_MSB: std_logic; + signal ENABLE_LSBS: std_logic; + signal D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15: std_logic; + signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15: std_logic; +begin + +-- control logic + SET_RESET <= SET_VALUE or RESET; + ENABLE_MSB <= SET_RESET or SHIFT_ALL; + SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST; + ENABLE_LSBS <= SET_RESET or SHIFT_LSBS; + +-- outputs + + OUTPUT(0) <= Q0; + OUTPUT(1) <= Q1; + OUTPUT(2) <= Q2; + OUTPUT(3) <= Q3; + OUTPUT(4) <= Q4; + OUTPUT(5) <= Q5; + OUTPUT(6) <= Q6; + OUTPUT(7) <= Q7; + OUTPUT(8) <= Q8; + OUTPUT(9) <= Q9; + OUTPUT(10) <= Q10; + OUTPUT(11) <= Q11; + OUTPUT(12) <= Q12; + OUTPUT(13) <= Q13; + OUTPUT(14) <= Q14; + OUTPUT(15) <= Q15; + +-- initialisation + +INIT: process(RESET,LOAD) +begin + if RESET = '1' then + D0 <= '0'; + D1 <= '0'; + D2 <= '0'; + D3 <= '0'; + D4 <= '0'; + D5 <= '0'; + D6 <= '0'; + D7 <= '0'; + D8 <= '0'; + D9 <= '0'; + D10 <= '0'; + D11 <= '0'; + D12 <= '0'; + D13 <= '0'; + D14 <= '0'; + D15 <= '0'; + else + D0 <= LOAD(0); + D1 <= LOAD(1); + D2 <= LOAD(2); + D3 <= LOAD(3); + D4 <= LOAD(4); + D5 <= LOAD(5); + D6 <= LOAD(6); + D7 <= LOAD(7); + D8 <= LOAD(8); + D9 <= LOAD(9); + D10 <= LOAD(10); + D11 <= LOAD(11); + D12 <= LOAD(12); + D13 <= LOAD(13); + D14 <= LOAD(14); + D15 <= LOAD(15); + end if; +end process INIT; + +-- storage + + STORE0: STORE_BLOCK + port map(LOAD_IN => D0, + SHIFT_IN => SHIFT_IN, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q0); + + STORE1: STORE_BLOCK + port map(LOAD_IN => D1, + SHIFT_IN => Q0, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q1); + + STORE2: STORE_BLOCK + port map(LOAD_IN => D2, + SHIFT_IN => Q1, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q2); + + STORE3: STORE_BLOCK + port map(LOAD_IN => D3, + SHIFT_IN => Q2, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q3); + + STORE4: STORE_BLOCK + port map(LOAD_IN => D4, + SHIFT_IN => Q3, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q4); + + STORE5: STORE_BLOCK + port map(LOAD_IN => D5, + SHIFT_IN => Q4, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q5); + + STORE6: STORE_BLOCK + port map(LOAD_IN => D6, + SHIFT_IN => Q5, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q6); + + STORE7: STORE_BLOCK + port map(LOAD_IN => D7, + SHIFT_IN => Q6, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q7); + + STORE8: STORE_BLOCK + port map(LOAD_IN => D8, + SHIFT_IN => Q7, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q8); + + STORE9: STORE_BLOCK + port map(LOAD_IN => D9, + SHIFT_IN => Q8, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q9); + + STORE10: STORE_BLOCK + port map(LOAD_IN => D10, + SHIFT_IN => Q9, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q10); + + STORE11: STORE_BLOCK + port map(LOAD_IN => D11, + SHIFT_IN => Q10, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q11); + + STORE12: STORE_BLOCK + port map(LOAD_IN => D12, + SHIFT_IN => Q11, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q12); + + STORE13: STORE_BLOCK + port map(LOAD_IN => D13, + SHIFT_IN => Q12, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q13); + + STORE14: STORE_BLOCK + port map(LOAD_IN => D14, + SHIFT_IN => Q13, + SHIFT => SHIFT_LSBS, + ENABLE => ENABLE_LSBS, + CLK => CLOCK, + OUTPUT => Q14); + + STORE15: STORE_BLOCK + port map(LOAD_IN => D15, + SHIFT_IN => Q14, + SHIFT => SHIFT_ALL, + ENABLE => ENABLE_MSB, + CLK => CLOCK, + OUTPUT => Q15); + + + +end architecture RTL; +

trunk/src/decoder/STORAGE_REGISTER.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/decoder/symbol_detector.prj =================================================================== --- trunk/src/decoder/symbol_detector.prj (nonexistent) +++ trunk/src/decoder/symbol_detector.prj (revision 2) @@ -0,0 +1 @@ +vhdl work SYMBOL_DETECTOR.vhd

trunk/src/decoder/symbol_detector.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/decoder/arithmeticdecoder.prj =================================================================== --- trunk/src/decoder/arithmeticdecoder.prj (nonexistent) +++ trunk/src/decoder/arithmeticdecoder.prj (revision 2) @@ -0,0 +1,11 @@ +vhdl work ../common/D_TYPE.vhd +vhdl work ../common/COUNT_UNIT.vhd +vhdl work ../common/ENABLEABLE_D_TYPE.vhd +vhdl work ../common/FIFO.vhd +vhdl work ../common/INPUT_CONTROL.vhd +vhdl work ../common/STORE_BLOCK.vhd +vhdl work STORAGE_REGISTER.vhd +vhdl work ../common/ARITHMETIC_UNIT.vhd +vhdl work ../common/CONVERGENCE_CHECK.vhd +vhdl work SYMBOL_DETECTOR.vhd +vhdl work ARITHMETICDECODER.vhd

trunk/src/decoder/arithmeticdecoder.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/decoder/SYMBOL_DETECTOR.vhd =================================================================== --- trunk/src/decoder/SYMBOL_DETECTOR.vhd (nonexistent) +++ trunk/src/decoder/SYMBOL_DETECTOR.vhd (revision 2) @@ -0,0 +1,71 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: SYMBOL_DETECTOR.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SYMBOL_DETECTOR is + Port ( ENABLE : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + THRESHOLD : in std_logic_vector(15 downto 0); + DATA_OUT : out std_logic); +end SYMBOL_DETECTOR; + +architecture RTL of SYMBOL_DETECTOR is + +begin +DECODE: process(ENABLE,DATA_IN,THRESHOLD) + begin + if ((ENABLE = '1') and (DATA_IN >= THRESHOLD)) then + DATA_OUT <= '1'; + else + DATA_OUT <= '0'; + end if; +end process DECODE; + + + + +end RTL;

trunk/src/decoder/SYMBOL_DETECTOR.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/INPUT_CONTROL.vhd =================================================================== --- trunk/src/common/INPUT_CONTROL.vhd (nonexistent) +++ trunk/src/common/INPUT_CONTROL.vhd (revision 2) @@ -0,0 +1,107 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: INPUT_CONTROL.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity INPUT_CONTROL is + Port ( ENABLE : in std_logic; + DATA_IN : in std_logic; + BUFFER_CONTROL : in std_logic; + DEMAND : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + SENDING : out std_logic; + DATA_OUT : out std_logic); +end INPUT_CONTROL; + +architecture RTL of INPUT_CONTROL is + component FIFO + port( WRITE_ENABLE : in std_logic; + DATA_IN : in std_logic; + READ_ENABLE : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + DATA_OUT : out std_logic; + EMPTY : out std_logic); + end component FIFO; + signal FIFO_WRITE_ENABLE : std_logic; + signal FIFO_READ_ENABLE : std_logic; + signal FIFO_DATA_IN : std_logic; + signal FIFO_DATA_OUT : std_logic; + signal FIFO_EMPTY : std_logic; + signal USE_BUFFER : std_logic; + signal PUT_IN_BUFFER : std_logic; +begin + +STORAGE : FIFO + port map(WRITE_ENABLE => FIFO_WRITE_ENABLE, + DATA_IN => FIFO_DATA_IN, + READ_ENABLE => FIFO_READ_ENABLE, + RESET => RESET, + CLOCK => CLOCK, + DATA_OUT => FIFO_DATA_OUT, + EMPTY => FIFO_EMPTY); + + FIFO_WRITE_ENABLE <= ENABLE and USE_BUFFER; + FIFO_DATA_IN <= DATA_IN and USE_BUFFER; + FIFO_READ_ENABLE <= DEMAND and USE_BUFFER; + + PUT_IN_BUFFER <= ENABLE and BUFFER_CONTROL; + USE_BUFFER <= PUT_IN_BUFFER or not FIFO_EMPTY; + +OUTPUT_SELECT: process(USE_BUFFER,DEMAND,FIFO_DATA_OUT,ENABLE,DATA_IN) +begin + if USE_BUFFER = '1' then + SENDING <= DEMAND; + DATA_OUT <= FIFO_DATA_OUT; + else + SENDING <= ENABLE; + DATA_OUT <= DATA_IN; + end if; +end process OUTPUT_SELECT; + + +end RTL;

trunk/src/common/INPUT_CONTROL.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/count_unit.prj =================================================================== --- trunk/src/common/count_unit.prj (nonexistent) +++ trunk/src/common/count_unit.prj (revision 2) @@ -0,0 +1,2 @@ +vhdl work D_TYPE.vhd +vhdl work COUNT_UNIT.vhd

trunk/src/common/count_unit.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/arithmetic_unit.prj =================================================================== --- trunk/src/common/arithmetic_unit.prj (nonexistent) +++ trunk/src/common/arithmetic_unit.prj (revision 2) @@ -0,0 +1,2 @@ +vhdl work D_TYPE.vhd +vhdl work ARITHMETIC_UNIT.vhd

trunk/src/common/arithmetic_unit.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/convergence_check.prj =================================================================== --- trunk/src/common/convergence_check.prj (nonexistent) +++ trunk/src/common/convergence_check.prj (revision 2) @@ -0,0 +1 @@ +vhdl work CONVERGENCE_CHECK.vhd

trunk/src/common/convergence_check.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/STORE_BLOCK.vhd =================================================================== --- trunk/src/common/STORE_BLOCK.vhd (nonexistent) +++ trunk/src/common/STORE_BLOCK.vhd (revision 2) @@ -0,0 +1,86 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: STORE_BLOCK.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity STORE_BLOCK is + Port ( LOAD_IN : in std_logic; + SHIFT_IN : in std_logic; + SHIFT : in std_logic; + ENABLE : in std_logic; + CLK : in std_logic; + OUTPUT : out std_logic); +end STORE_BLOCK; + +architecture RTL of STORE_BLOCK is + component ENABLEABLE_D_TYPE + port (DATA_IN, ENABLE, CLK: in std_logic; + DATA_OUT: out std_logic); + end component; + + signal LOAD_VALUE : std_logic; +begin + + + STORAGE: ENABLEABLE_D_TYPE + port map(DATA_IN => LOAD_VALUE, + ENABLE => ENABLE, + CLK => CLK, + DATA_OUT => OUTPUT); + + SELECT_VALUE: process(SHIFT,SHIFT_IN,LOAD_IN) + begin + if SHIFT = '1' then + LOAD_VALUE <= SHIFT_IN; + else + LOAD_VALUE <= LOAD_IN; + end if; + end process SELECT_VALUE; + + + + +end RTL;

trunk/src/common/STORE_BLOCK.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/input_control.prj =================================================================== --- trunk/src/common/input_control.prj (nonexistent) +++ trunk/src/common/input_control.prj (revision 2) @@ -0,0 +1,5 @@ +vhdl work D_TYPE.vhd +vhdl work COUNT_UNIT.vhd +vhdl work ENABLEABLE_D_TYPE.vhd +vhdl work FIFO.vhd +vhdl work INPUT_CONTROL.vhd

trunk/src/common/input_control.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/ENABLEABLE_D_TYPE.vhd =================================================================== --- trunk/src/common/ENABLEABLE_D_TYPE.vhd (nonexistent) +++ trunk/src/common/ENABLEABLE_D_TYPE.vhd (revision 2) @@ -0,0 +1,82 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: ENABLEABLE_D_TYPE.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ENABLEABLE_D_TYPE is + Port ( DATA_IN : in std_logic; + ENABLE : in std_logic; + CLK : in std_logic; + DATA_OUT : out std_logic); +end ENABLEABLE_D_TYPE; + +architecture RTL of ENABLEABLE_D_TYPE is + signal RETAIN : std_logic; + signal D_IN : std_logic; + component D_TYPE + port(D,CLOCK: in std_logic; + Q: out std_logic); + end component; +begin + + FLIP_FLOP: D_TYPE + port map( + D => D_IN, + CLOCK => CLK, + Q => RETAIN); + + DATA_OUT <= RETAIN; + + LOAD: process(ENABLE,DATA_IN,RETAIN) + begin + if ENABLE = '1' then + D_IN <= DATA_IN; + else + D_IN <= RETAIN; + end if; + end process LOAD; + +end architecture RTL;

trunk/src/common/ENABLEABLE_D_TYPE.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/store_block.prj =================================================================== --- trunk/src/common/store_block.prj (nonexistent) +++ trunk/src/common/store_block.prj (revision 2) @@ -0,0 +1,3 @@ +vhdl work D_TYPE.vhd +vhdl work ENABLEABLE_D_TYPE.vhd +vhdl work STORE_BLOCK.vhd

trunk/src/common/store_block.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/FIFO.vhd =================================================================== --- trunk/src/common/FIFO.vhd (nonexistent) +++ trunk/src/common/FIFO.vhd (revision 2) @@ -0,0 +1,212 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: FIFO.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FIFO is + generic (RANK : integer range 0 to 16 :=8); + Port ( WRITE_ENABLE : in std_logic; + DATA_IN : in std_logic; + READ_ENABLE : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + DATA_OUT : out std_logic; + EMPTY : out std_logic); +end FIFO; + +architecture RTL of FIFO is + component ENABLEABLE_D_TYPE + port (DATA_IN : in std_logic; + ENABLE : in std_logic; + CLK : in std_logic; + DATA_OUT: out std_logic); + end component ENABLEABLE_D_TYPE; + component D_TYPE + port( D : in std_logic; + CLOCK : in std_logic; + Q : out std_logic); +end component D_TYPE; + component COUNT_UNIT + port( INCREMENT : in std_logic; + DECREMENT : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic; + INCREMENT_CARRY : out std_logic; + DECREMENT_CARRY : out std_logic); +end component COUNT_UNIT; + function TWO_TO_N(N: integer) return integer is + variable A: integer; + begin + A := 1; + for Z in 0 to N - 1 loop + A := 2*A; + end loop; + return A; + end function TWO_TO_N; + function ZERO_VALUE(ADDRESS: std_logic_vector) return std_logic is + begin + for J in 0 to RANK - 1 loop + if ADDRESS(J) = '1' then + return '0'; + end if; + end loop; + return '1'; + end function ZERO_VALUE; + + signal READ_ADDRESS : std_logic_vector (RANK - 1 downto 0); + signal INC : std_logic_vector (RANK - 1 downto 0); + signal DEC : std_logic_vector (RANK - 1 downto 0); + type MATRIX is + array (RANK downto 0) of std_logic_vector (TWO_TO_N(RANK) -1 downto 0); + signal GET_OUTPUT: MATRIX; + signal NEWVAL : std_logic_vector(TWO_TO_N(RANK) - 1 downto 0); + signal INCREMENT : std_logic; + signal DECREMENT : std_logic; + signal TOGGLE : std_logic; + signal IS_EMPTY : std_logic; + signal ZERO : std_logic; + signal NEW_EMPTY : std_logic; + signal EMPTY_OUT : std_logic; + signal NOWRITE : std_logic; + signal CHANGED_VALUE : std_logic; + signal EMPTY_IF_READ : std_logic; + signal LOAD_ENABLE : std_logic; +begin +-- Storage registers + + +BUILD: for I in 0 to RANK -1 generate + +LSB: if I = 0 generate +COUNTER : COUNT_UNIT + port map( INCREMENT => INCREMENT, + DECREMENT => DECREMENT, + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => READ_ADDRESS(I), + INCREMENT_CARRY => INC(I), + DECREMENT_CARRY => DEC(I)); + + end generate; + +OTHER_BITS: if I > 0 generate +COUNTER : COUNT_UNIT + port map( INCREMENT => INC(I-1), + DECREMENT => DEC(I-1), + RESET => RESET, + CLOCK => CLOCK, + OUTPUT => READ_ADDRESS(I), + INCREMENT_CARRY => INC(I), + DECREMENT_CARRY => DEC(I)); + end generate; + +MULTIPLEX: for Z in 0 to TWO_TO_N(I) - 1 generate +OUTPUT_SELECT: process(READ_ADDRESS(RANK - I - 1),GET_OUTPUT(RANK - I -1)) +begin + if READ_ADDRESS(RANK - I - 1) = '1' then + GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z + 1); + else + GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z); + end if; +end process OUTPUT_SELECT; +end generate; + +STORAGE: if I = RANK - 1 generate +BITS: for X in 0 to TWO_TO_N(RANK) - 1 generate +STORE: ENABLEABLE_D_TYPE + port map (DATA_IN => NEWVAL(X), + ENABLE => LOAD_ENABLE, + CLK => CLOCK, + DATA_OUT => GET_OUTPUT(0)(X)); +MOST_RECENT: if X = 0 generate + NEWVAL(X) <= DATA_IN and not RESET; +end generate; + +OLDER_DATA: if X > 0 generate + NEWVAL(X) <= GET_OUTPUT(0)(X-1) and not RESET; +end generate; +end generate; +end generate; + + +end generate; + +LOAD_ENABLE <= WRITE_ENABLE or RESET; +INCREMENT <= WRITE_ENABLE and not (READ_ENABLE or EMPTY_OUT); +DECREMENT <= READ_ENABLE and not (WRITE_ENABLE or ZERO); + +EMPTY_VALUE: D_TYPE + port map(D => IS_EMPTY, + CLOCK => CLOCK, + Q => EMPTY_OUT); + +IS_EMPTY <= NEW_EMPTY or RESET; + +SWITCH_EMPTY: process(TOGGLE,EMPTY_OUT,CHANGED_VALUE) +begin + if(TOGGLE = '1') then + NEW_EMPTY <= CHANGED_VALUE; + else + NEW_EMPTY <= EMPTY_OUT; + end if; +end process SWITCH_EMPTY; + +TOGGLE <= WRITE_ENABLE xor READ_ENABLE; +CHANGED_VALUE <= EMPTY_IF_READ and NOWRITE; +NOWRITE <= not WRITE_ENABLE; +EMPTY_IF_READ <= ZERO or EMPTY_OUT; + + +ZERO <= ZERO_VALUE(READ_ADDRESS); + +EMPTY <= EMPTY_OUT; + +DATA_OUT <= GET_OUTPUT(RANK)(0); + + + +end RTL;

trunk/src/common/FIFO.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/D_TYPE.vhd =================================================================== --- trunk/src/common/D_TYPE.vhd (nonexistent) +++ trunk/src/common/D_TYPE.vhd (revision 2) @@ -0,0 +1,69 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: D_TYPE.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity D_TYPE is + Port ( + D : in std_logic; + CLOCK : in std_logic; + Q : out std_logic); +end D_TYPE; + +architecture RTL of D_TYPE is +begin +FLIP_FLOP: process(CLOCK) +begin + if CLOCK'event and CLOCK = '1' then + Q <= D; + end if; +end process FLIP_FLOP; + +end RTL; + +configuration STANDARD of D_TYPE is +for RTL end for; +end configuration STANDARD; \ No newline at end of file

trunk/src/common/D_TYPE.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/COUNT_UNIT.vhd =================================================================== --- trunk/src/common/COUNT_UNIT.vhd (nonexistent) +++ trunk/src/common/COUNT_UNIT.vhd (revision 2) @@ -0,0 +1,92 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: COUNT_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity COUNT_UNIT is + Port ( INCREMENT : in std_logic; + DECREMENT : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + OUTPUT : out std_logic; + INCREMENT_CARRY : out std_logic; + DECREMENT_CARRY : out std_logic); +end COUNT_UNIT; + +architecture RTL of COUNT_UNIT is + component D_TYPE + port(D,CLOCK: in std_logic; + Q: out std_logic); + end component D_TYPE; + signal UPDATE: std_logic :='0'; + signal TOGGLE: std_logic; + signal Q_VAL: std_logic; + signal INVERSE: std_logic; + signal NEWVAL : std_logic; +begin + +-- combinatorial logic + + TOGGLE <= INCREMENT xor DECREMENT; + INVERSE <= not Q_VAL; + OUTPUT <= Q_VAL; + INCREMENT_CARRY <= INCREMENT and not DECREMENT and Q_VAL; + DECREMENT_CARRY <= DECREMENT and not INCREMENT and INVERSE; + NEWVAL <= Q_VAL xor TOGGLE; + UPDATE <= NEWVAL and not RESET; + + + + + +-- The D_TYPE + +FLIP_FLOP: D_TYPE + port map(D => UPDATE, + CLOCK => CLOCK, + Q => Q_VAL); + +end RTL;

trunk/src/common/COUNT_UNIT.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/ARITHMETIC_UNIT.vhd =================================================================== --- trunk/src/common/ARITHMETIC_UNIT.vhd (nonexistent) +++ trunk/src/common/ARITHMETIC_UNIT.vhd (revision 2) @@ -0,0 +1,143 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: ARITHMETIC_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ARITHMETIC_UNIT is + Port ( DIFFERENCE : in std_logic_vector(15 downto 0); + PROB : in std_logic_vector(9 downto 0); + LOW : in std_logic_vector(15 downto 0); + ENABLE : in std_logic; + RESET : in std_logic; + CLOCK : in std_logic; + DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0); + DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0); + RESULT_OUT0 : out std_logic_vector(15 downto 0); + RESULT_OUT1 : out std_logic_vector(15 downto 0); + DATA_LOAD : out std_logic :='1'); +end ARITHMETIC_UNIT; + +architecture RTL of ARITHMETIC_UNIT is + component D_TYPE + port(D,CLOCK: in std_logic; + Q: out std_logic); + end component D_TYPE; + signal LOW2 : std_logic_vector(16 downto 0); + signal PRODUCT : std_logic_vector (26 downto 0); + signal PRODUCT2 : std_logic_vector (16 downto 0); + signal RESULT : std_logic_vector (16 downto 0); + signal RESULT0 : std_logic_vector (15 downto 0); + signal DIFFERENCE1 : std_logic_vector (16 downto 0); + signal DIFFERENCE2 : std_logic_vector(16 downto 0); + signal DIFFERENCE3 : std_logic_vector(16 downto 0); + signal DIFFERENCE4 : std_logic_vector(16 downto 0); + signal DELAY1 : std_logic; + signal DELAY2 : std_logic; + signal CALCULATE : std_logic; +begin + +-- The arithmetic + DIFFERENCE2 <= ('0' & DIFFERENCE) + "00000000000000001"; +MULTIPLY : process (CLOCK, DIFFERENCE2, PROB) + begin + if CLOCK'event and CLOCK = '1' then + PRODUCT <= DIFFERENCE2 * PROB; + end if; + end process MULTIPLY; + PRODUCT2 <= PRODUCT(26 downto 10); + RESULT <= LOW2 + PRODUCT2; + RESULT_OUT1 <= RESULT(15 downto 0); + RESULT0 <= (RESULT - "00000000000000001"); + RESULT_OUT0 <= RESULT0(15 downto 0); + DIFFERENCE3 <= (PRODUCT2 - "00000000000000001"); + DIFFERENCE4 <= (DIFFERENCE1 - PRODUCT2); + DIFFERENCE_OUT1 <= DIFFERENCE4(15 downto 0); + + + + +-- Control logic + CALCULATE <= ENABLE and not RESET; + DATA_LOAD <= DELAY1 and DELAY2; + +-- Sequential control logic + +READ_DELAY: D_TYPE + port map(D => CALCULATE, + CLOCK => CLOCK, + Q => DELAY1); + +CHECK_DELAY: D_TYPE + port map(D => DELAY1, + CLOCK => CLOCK, + Q => DELAY2); + +DELAYS: for I in 0 to 15 generate + +DIFF_DELAY: D_TYPE + port map(D => DIFFERENCE(I), + CLOCK => CLOCK, + Q => DIFFERENCE1(I)); + +LOW_DELAY: D_TYPE + port map(D => LOW(I), + CLOCK => CLOCK, + Q => LOW2(I)); + +OUT_DELAY0: D_TYPE + port map(D => DIFFERENCE3(I), + CLOCK => CLOCK, + Q => DIFFERENCE_OUT0(I)); + + +end generate; + +LOW2(16) <= '0'; +DIFFERENCE1(16) <= '0'; + + +end RTL;

trunk/src/common/ARITHMETIC_UNIT.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/enableable_d_type.prj =================================================================== --- trunk/src/common/enableable_d_type.prj (nonexistent) +++ trunk/src/common/enableable_d_type.prj (revision 2) @@ -0,0 +1,2 @@ +vhdl work D_TYPE.vhd +vhdl work ENABLEABLE_D_TYPE.vhd

trunk/src/common/enableable_d_type.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/CONVERGENCE_CHECK.vhd =================================================================== --- trunk/src/common/CONVERGENCE_CHECK.vhd (nonexistent) +++ trunk/src/common/CONVERGENCE_CHECK.vhd (revision 2) @@ -0,0 +1,82 @@ +-- ***** BEGIN LICENSE BLOCK ***** +-- +-- $Id: CONVERGENCE_CHECK.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ +-- * +-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 +-- * +-- * The contents of this file are subject to the Mozilla Public License +-- * Version 1.1 (the "License"); you may not use this file except in compliance +-- * with the License. You may obtain a copy of the License at +-- * http://www.mozilla.org/MPL/ +-- * +-- * Software distributed under the License is distributed on an "AS IS" basis, +-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for +-- * the specific language governing rights and limitations under the License. +-- * +-- * The Original Code is BBC Research and Development code. +-- * +-- * The Initial Developer of the Original Code is the British Broadcasting +-- * Corporation. +-- * Portions created by the Initial Developer are Copyright (C) 2004. +-- * All Rights Reserved. +-- * +-- * Contributor(s): Peter Bleackley (Original author) +-- * +-- * Alternatively, the contents of this file may be used under the terms of +-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser +-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of +-- * the GPL or the LGPL are applicable instead of those above. If you wish to +-- * allow use of your version of this file only under the terms of the either +-- * the GPL or LGPL and not to allow others to use your version of this file +-- * under the MPL, indicate your decision by deleting the provisions above +-- * and replace them with the notice and other provisions required by the GPL +-- * or LGPL. If you do not delete the provisions above, a recipient may use +-- * your version of this file under the terms of any one of the MPL, the GPL +-- * or the LGPL. +-- * ***** END LICENSE BLOCK ***** */ + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CONVERGENCE_CHECK is + Port ( HIGH_MSB : in std_logic; + LOW_MSB : in std_logic; + HIGH_SECONDBIT : in std_logic; + LOW_SECONDBIT : in std_logic; + CHECK : in std_logic; + TRIGGER_OUTPUT : out std_logic; + TRIGGER_FOLLOW : out std_logic); +end CONVERGENCE_CHECK; + +architecture RTL of CONVERGENCE_CHECK is + signal MSB_AND : std_logic; + signal MSB_NOR : std_logic; + signal MSB_EQ : std_logic; + signal MSB_XOR : std_logic; + signal INV : std_logic; + signal SECOND_BIT_01: std_logic; + signal STRADDLE: std_logic; +begin + + MSB_AND <= HIGH_MSB and LOW_MSB; + MSB_NOR <= HIGH_MSB nor LOW_MSB; + MSB_EQ <= MSB_AND or MSB_NOR; + MSB_XOR <= not MSB_EQ; + + INV <= not HIGH_SECONDBIT; + SECOND_BIT_01 <= INV and LOW_SECONDBIT; + STRADDLE <= MSB_XOR and SECOND_BIT_01; + + TRIGGER_OUTPUT <= CHECK and MSB_EQ; + TRIGGER_FOLLOW <= CHECK and STRADDLE; + + +end RTL;

trunk/src/common/CONVERGENCE_CHECK.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/fifo.prj =================================================================== --- trunk/src/common/fifo.prj (nonexistent) +++ trunk/src/common/fifo.prj (revision 2) @@ -0,0 +1,4 @@ +vhdl work D_TYPE.vhd +vhdl work COUNT_UNIT.vhd +vhdl work ENABLEABLE_D_TYPE.vhd +vhdl work FIFO.vhd

trunk/src/common/fifo.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/common/d_type.prj =================================================================== --- trunk/src/common/d_type.prj (nonexistent) +++ trunk/src/common/d_type.prj (revision 2) @@ -0,0 +1 @@ +vhdl work D_TYPE.vhd

trunk/src/common/d_type.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/COPYING =================================================================== --- trunk/COPYING (nonexistent) +++ trunk/COPYING (revision 2) @@ -0,0 +1,1332 @@ +The Dirac VHDL source is licensed under the Mozilla Public License +Version 1.1, which is included below. The provisions of this license allow +for relicensing under other licenses, which are specified in the license +preamble at the beginning of each source-code file. For the purposes of this +distribution, the licenses under which relicensing is possible are uniformly +specified to be the GNU Public License Version 2.0 and the GNU Lesser Public +License Version 2.1. These may be downloaded from www.gnu.org/licenses; however +copies are also provided in Annex A and Annex B to this document. + + + MOZILLA PUBLIC LICENSE + Version 1.1 + + --------------- + +1. Definitions. + + 1.0.1. "Commercial Use" means distribution or otherwise making the + Covered Code available to a third party. + + 1.1. "Contributor" means each entity that creates or contributes to + the creation of Modifications. + + 1.2. "Contributor Version" means the combination of the Original + Code, prior Modifications used by a Contributor, and the Modifications + made by that particular Contributor. + + 1.3. "Covered Code" means the Original Code or Modifications or the + combination of the Original Code and Modifications, in each case + including portions thereof. + + 1.4. "Electronic Distribution Mechanism" means a mechanism generally + accepted in the software development community for the electronic + transfer of data. + + 1.5. "Executable" means Covered Code in any form other than Source + Code. + + 1.6. "Initial Developer" means the individual or entity identified + as the Initial Developer in the Source Code notice required by Exhibit + A. + + 1.7. "Larger Work" means a work which combines Covered Code or + portions thereof with code not governed by the terms of this License. + + 1.8. "License" means this document. + + 1.8.1. "Licensable" means having the right to grant, to the maximum + extent possible, whether at the time of the initial grant or + subsequently acquired, any and all of the rights conveyed herein. + + 1.9. "Modifications" means any addition to or deletion from the + substance or structure of either the Original Code or any previous + Modifications. When Covered Code is released as a series of files, a + Modification is: + A. Any addition to or deletion from the contents of a file + containing Original Code or previous Modifications. + + B. Any new file that contains any part of the Original Code or + previous Modifications. + + 1.10. "Original Code" means Source Code of computer software code + which is described in the Source Code notice required by Exhibit A as + Original Code, and which, at the time of its release under this + License is not already Covered Code governed by this License. + + 1.10.1. "Patent Claims" means any patent claim(s), now owned or + hereafter acquired, including without limitation, method, process, + and apparatus claims, in any patent Licensable by grantor. + + 1.11. "Source Code" means the preferred form of the Covered Code for + making modifications to it, including all modules it contains, plus + any associated interface definition files, scripts used to control + compilation and installation of an Executable, or source code + differential comparisons against either the Original Code or another + well known, available Covered Code of the Contributor's choice. The + Source Code can be in a compressed or archival form, provided the + appropriate decompression or de-archiving software is widely available + for no charge. + + 1.12. "You" (or "Your") means an individual or a legal entity + exercising rights under, and complying with all of the terms of, this + License or a future version of this License issued under Section 6.1. + For legal entities, "You" includes any entity which controls, is + controlled by, or is under common control with You. For purposes of + this definition, "control" means (a) the power, direct or indirect, + to cause the direction or management of such entity, whether by + contract or otherwise, or (b) ownership of more than fifty percent + (50%) of the outstanding shares or beneficial ownership of such + entity. + +2. Source Code License. + + 2.1. The Initial Developer Grant. + The Initial Developer hereby grants You a world-wide, royalty-free, + non-exclusive license, subject to third party intellectual property + claims: + (a) under intellectual property rights (other than patent or + trademark) Licensable by Initial Developer to use, reproduce, + modify, display, perform, sublicense and distribute the Original + Code (or portions thereof) with or without Modifications, and/or + as part of a Larger Work; and + + (b) under Patents Claims infringed by the making, using or + selling of Original Code, to make, have made, use, practice, + sell, and offer for sale, and/or otherwise dispose of the + Original Code (or portions thereof). + + (c) the licenses granted in this Section 2.1(a) and (b) are + effective on the date Initial Developer first distributes + Original Code under the terms of this License. + + (d) Notwithstanding Section 2.1(b) above, no patent license is + granted: 1) for code that You delete from the Original Code; 2) + separate from the Original Code; or 3) for infringements caused + by: i) the modification of the Original Code or ii) the + combination of the Original Code with other software or devices. + + 2.2. Contributor Grant. + Subject to third party intellectual property claims, each Contributor + hereby grants You a world-wide, royalty-free, non-exclusive license + + (a) under intellectual property rights (other than patent or + trademark) Licensable by Contributor, to use, reproduce, modify, + display, perform, sublicense and distribute the Modifications + created by such Contributor (or portions thereof) either on an + unmodified basis, with other Modifications, as Covered Code + and/or as part of a Larger Work; and + + (b) under Patent Claims infringed by the making, using, or + selling of Modifications made by that Contributor either alone + and/or in combination with its Contributor Version (or portions + of such combination), to make, use, sell, offer for sale, have + made, and/or otherwise dispose of: 1) Modifications made by that + Contributor (or portions thereof); and 2) the combination of + Modifications made by that Contributor with its Contributor + Version (or portions of such combination). + + (c) the licenses granted in Sections 2.2(a) and 2.2(b) are + effective on the date Contributor first makes Commercial Use of + the Covered Code. + + (d) Notwithstanding Section 2.2(b) above, no patent license is + granted: 1) for any code that Contributor has deleted from the + Contributor Version; 2) separate from the Contributor Version; + 3) for infringements caused by: i) third party modifications of + Contributor Version or ii) the combination of Modifications made + by that Contributor with other software (except as part of the + Contributor Version) or other devices; or 4) under Patent Claims + infringed by Covered Code in the absence of Modifications made by + that Contributor. + +3. Distribution Obligations. + + 3.1. Application of License. + The Modifications which You create or to which You contribute are + governed by the terms of this License, including without limitation + Section 2.2. The Source Code version of Covered Code may be + distributed only under the terms of this License or a future version + of this License released under Section 6.1, and You must include a + copy of this License with every copy of the Source Code You + distribute. You may not offer or impose any terms on any Source Code + version that alters or restricts the applicable version of this + License or the recipients' rights hereunder. However, You may include + an additional document offering the additional rights described in + Section 3.5. + + 3.2. Availability of Source Code. + Any Modification which You create or to which You contribute must be + made available in Source Code form under the terms of this License + either on the same media as an Executable version or via an accepted + Electronic Distribution Mechanism to anyone to whom you made an + Executable version available; and if made available via Electronic + Distribution Mechanism, must remain available for at least twelve (12) + months after the date it initially became available, or at least six + (6) months after a subsequent version of that particular Modification + has been made available to such recipients. You are responsible for + ensuring that the Source Code version remains available even if the + Electronic Distribution Mechanism is maintained by a third party. + + 3.3. Description of Modifications. + You must cause all Covered Code to which You contribute to contain a + file documenting the changes You made to create that Covered Code and + the date of any change. You must include a prominent statement that + the Modification is derived, directly or indirectly, from Original + Code provided by the Initial Developer and including the name of the + Initial Developer in (a) the Source Code, and (b) in any notice in an + Executable version or related documentation in which You describe the + origin or ownership of the Covered Code. + + 3.4. Intellectual Property Matters + (a) Third Party Claims. + If Contributor has knowledge that a license under a third party's + intellectual property rights is required to exercise the rights + granted by such Contributor under Sections 2.1 or 2.2, + Contributor must include a text file with the Source Code + distribution titled "LEGAL" which describes the claim and the + party making the claim in sufficient detail that a recipient will + know whom to contact. If Contributor obtains such knowledge after + the Modification is made available as described in Section 3.2, + Contributor shall promptly modify the LEGAL file in all copies + Contributor makes available thereafter and shall take other steps + (such as notifying appropriate mailing lists or newsgroups) + reasonably calculated to inform those who received the Covered + Code that new knowledge has been obtained. + + (b) Contributor APIs. + If Contributor's Modifications include an application programming + interface and Contributor has knowledge of patent licenses which + are reasonably necessary to implement that API, Contributor must + also include this information in the LEGAL file. + + (c) Representations. + Contributor represents that, except as disclosed pursuant to + Section 3.4(a) above, Contributor believes that Contributor's + Modifications are Contributor's original creation(s) and/or + Contributor has sufficient rights to grant the rights conveyed by + this License. + + 3.5. Required Notices. + You must duplicate the notice in Exhibit A in each file of the Source + Code. If it is not possible to put such notice in a particular Source + Code file due to its structure, then You must include such notice in a + location (such as a relevant directory) where a user would be likely + to look for such a notice. If You created one or more Modification(s) + You may add your name as a Contributor to the notice described in + Exhibit A. You must also duplicate this License in any documentation + for the Source Code where You describe recipients' rights or ownership + rights relating to Covered Code. You may choose to offer, and to + charge a fee for, warranty, support, indemnity or liability + obligations to one or more recipients of Covered Code. However, You + may do so only on Your own behalf, and not on behalf of the Initial + Developer or any Contributor. You must make it absolutely clear than + any such warranty, support, indemnity or liability obligation is + offered by You alone, and You hereby agree to indemnify the Initial + Developer and every Contributor for any liability incurred by the + Initial Developer or such Contributor as a result of warranty, + support, indemnity or liability terms You offer. + + 3.6. Distribution of Executable Versions. + You may distribute Covered Code in Executable form only if the + requirements of Section 3.1-3.5 have been met for that Covered Code, + and if You include a notice stating that the Source Code version of + the Covered Code is available under the terms of this License, + including a description of how and where You have fulfilled the + obligations of Section 3.2. The notice must be conspicuously included + in any notice in an Executable version, related documentation or + collateral in which You describe recipients' rights relating to the + Covered Code. You may distribute the Executable version of Covered + Code or ownership rights under a license of Your choice, which may + contain terms different from this License, provided that You are in + compliance with the terms of this License and that the license for the + Executable version does not attempt to limit or alter the recipient's + rights in the Source Code version from the rights set forth in this + License. If You distribute the Executable version under a different + license You must make it absolutely clear that any terms which differ + from this License are offered by You alone, not by the Initial + Developer or any Contributor. You hereby agree to indemnify the + Initial Developer and every Contributor for any liability incurred by + the Initial Developer or such Contributor as a result of any such + terms You offer. + + 3.7. Larger Works. + You may create a Larger Work by combining Covered Code with other code + not governed by the terms of this License and distribute the Larger + Work as a single product. In such a case, You must make sure the + requirements of this License are fulfilled for the Covered Code. + +4. Inability to Comply Due to Statute or Regulation. + + If it is impossible for You to comply with any of the terms of this + License with respect to some or all of the Covered Code due to + statute, judicial order, or regulation then You must: (a) comply with + the terms of this License to the maximum extent possible; and (b) + describe the limitations and the code they affect. Such description + must be included in the LEGAL file described in Section 3.4 and must + be included with all distributions of the Source Code. Except to the + extent prohibited by statute or regulation, such description must be + sufficiently detailed for a recipient of ordinary skill to be able to + understand it. + +5. Application of this License. + + This License applies to code to which the Initial Developer has + attached the notice in Exhibit A and to related Covered Code. + +6. Versions of the License. + + 6.1. New Versions. + Netscape Communications Corporation ("Netscape") may publish revised + and/or new versions of the License from time to time. Each version + will be given a distinguishing version number. + + 6.2. Effect of New Versions. + Once Covered Code has been published under a particular version of the + License, You may always continue to use it under the terms of that + version. You may also choose to use such Covered Code under the terms + of any subsequent version of the License published by Netscape. No one + other than Netscape has the right to modify the terms applicable to + Covered Code created under this License. + + 6.3. Derivative Works. + If You create or use a modified version of this License (which you may + only do in order to apply it to code which is not already Covered Code + governed by this License), You must (a) rename Your license so that + the phrases "Mozilla", "MOZILLAPL", "MOZPL", "Netscape", + "MPL", "NPL" or any confusingly similar phrase do not appear in your + license (except to note that your license differs from this License) + and (b) otherwise make it clear that Your version of the license + contains terms which differ from the Mozilla Public License and + Netscape Public License. (Filling in the name of the Initial + Developer, Original Code or Contributor in the notice described in + Exhibit A shall not of themselves be deemed to be modifications of + this License.) + +7. DISCLAIMER OF WARRANTY. + + COVERED CODE IS PROVIDED UNDER THIS LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, + WITHOUT LIMITATION, WARRANTIES THAT THE COVERED CODE IS FREE OF + DEFECTS, MERCHANTABLE, FIT FOR A PARTICULAR PURPOSE OR NON-INFRINGING. + THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE COVERED CODE + IS WITH YOU. SHOULD ANY COVERED CODE PROVE DEFECTIVE IN ANY RESPECT, + YOU (NOT THE INITIAL DEVELOPER OR ANY OTHER CONTRIBUTOR) ASSUME THE + COST OF ANY NECESSARY SERVICING, REPAIR OR CORRECTION. THIS DISCLAIMER + OF WARRANTY CONSTITUTES AN ESSENTIAL PART OF THIS LICENSE. NO USE OF + ANY COVERED CODE IS AUTHORIZED HEREUNDER EXCEPT UNDER THIS DISCLAIMER. + +8. TERMINATION. + + 8.1. This License and the rights granted hereunder will terminate + automatically if You fail to comply with terms herein and fail to cure + such breach within 30 days of becoming aware of the breach. All + sublicenses to the Covered Code which are properly granted shall + survive any termination of this License. Provisions which, by their + nature, must remain in effect beyond the termination of this License + shall survive. + + 8.2. If You initiate litigation by asserting a patent infringement + claim (excluding declatory judgment actions) against Initial Developer + or a Contributor (the Initial Developer or Contributor against whom + You file such action is referred to as "Participant") alleging that: + + (a) such Participant's Contributor Version directly or indirectly + infringes any patent, then any and all rights granted by such + Participant to You under Sections 2.1 and/or 2.2 of this License + shall, upon 60 days notice from Participant terminate prospectively, + unless if within 60 days after receipt of notice You either: (i) + agree in writing to pay Participant a mutually agreeable reasonable + royalty for Your past and future use of Modifications made by such + Participant, or (ii) withdraw Your litigation claim with respect to + the Contributor Version against such Participant. If within 60 days + of notice, a reasonable royalty and payment arrangement are not + mutually agreed upon in writing by the parties or the litigation claim + is not withdrawn, the rights granted by Participant to You under + Sections 2.1 and/or 2.2 automatically terminate at the expiration of + the 60 day notice period specified above. + + (b) any software, hardware, or device, other than such Participant's + Contributor Version, directly or indirectly infringes any patent, then + any rights granted to You by such Participant under Sections 2.1(b) + and 2.2(b) are revoked effective as of the date You first made, used, + sold, distributed, or had made, Modifications made by that + Participant. + + 8.3. If You assert a patent infringement claim against Participant + alleging that such Participant's Contributor Version directly or + indirectly infringes any patent where such claim is resolved (such as + by license or settlement) prior to the initiation of patent + infringement litigation, then the reasonable value of the licenses + granted by such Participant under Sections 2.1 or 2.2 shall be taken + into account in determining the amount or value of any payment or + license. + + 8.4. In the event of termination under Sections 8.1 or 8.2 above, + all end user license agreements (excluding distributors and resellers) + which have been validly granted by You or any distributor hereunder + prior to termination shall survive termination. + +9. LIMITATION OF LIABILITY. + + UNDER NO CIRCUMSTANCES AND UNDER NO LEGAL THEORY, WHETHER TORT + (INCLUDING NEGLIGENCE), CONTRACT, OR OTHERWISE, SHALL YOU, THE INITIAL + DEVELOPER, ANY OTHER CONTRIBUTOR, OR ANY DISTRIBUTOR OF COVERED CODE, + OR ANY SUPPLIER OF ANY OF SUCH PARTIES, BE LIABLE TO ANY PERSON FOR + ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES OF ANY + CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF GOODWILL, + WORK STOPPAGE, COMPUTER FAILURE OR MALFUNCTION, OR ANY AND ALL OTHER + COMMERCIAL DAMAGES OR LOSSES, EVEN IF SUCH PARTY SHALL HAVE BEEN + INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. THIS LIMITATION OF + LIABILITY SHALL NOT APPLY TO LIABILITY FOR DEATH OR PERSONAL INJURY + RESULTING FROM SUCH PARTY'S NEGLIGENCE TO THE EXTENT APPLICABLE LAW + PROHIBITS SUCH LIMITATION. SOME JURISDICTIONS DO NOT ALLOW THE + EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO + THIS EXCLUSION AND LIMITATION MAY NOT APPLY TO YOU. + +10. U.S. GOVERNMENT END USERS. + + The Covered Code is a "commercial item," as that term is defined in + 48 C.F.R. 2.101 (Oct. 1995), consisting of "commercial computer + software" and "commercial computer software documentation," as such + terms are used in 48 C.F.R. 12.212 (Sept. 1995). Consistent with 48 + C.F.R. 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (June 1995), + all U.S. Government End Users acquire Covered Code with only those + rights set forth herein. + +11. MISCELLANEOUS. + + This License represents the complete agreement concerning subject + matter hereof. If any provision of this License is held to be + unenforceable, such provision shall be reformed only to the extent + necessary to make it enforceable. This License shall be governed by + California law provisions (except to the extent applicable law, if + any, provides otherwise), excluding its conflict-of-law provisions. + With respect to disputes in which at least one party is a citizen of, + or an entity chartered or registered to do business in the United + States of America, any litigation relating to this License shall be + subject to the jurisdiction of the Federal Courts of the Northern + District of California, with venue lying in Santa Clara County, + California, with the losing party responsible for costs, including + without limitation, court costs and reasonable attorneys' fees and + expenses. The application of the United Nations Convention on + Contracts for the International Sale of Goods is expressly excluded. + Any law or regulation which provides that the language of a contract + shall be construed against the drafter shall not apply to this + License. + +12. RESPONSIBILITY FOR CLAIMS. + + As between Initial Developer and the Contributors, each party is + responsible for claims and damages arising, directly or indirectly, + out of its utilization of rights under this License and You agree to + work with Initial Developer and Contributors to distribute such + responsibility on an equitable basis. Nothing herein is intended or + shall be deemed to constitute any admission of liability. + +13. MULTIPLE-LICENSED CODE. + + Initial Developer may designate portions of the Covered Code as + "Multiple-Licensed". "Multiple-Licensed" means that the Initial + Developer permits you to utilize portions of the Covered Code under + Your choice of the NPL or the alternative licenses, if any, specified + by the Initial Developer in the file described in Exhibit A. + +EXHIBIT A -Mozilla Public License. + + ``The contents of this file are subject to the Mozilla Public License + Version 1.1 (the "License"); you may not use this file except in + compliance with the License. You may obtain a copy of the License at + http://www.mozilla.org/MPL/ + + Software distributed under the License is distributed on an "AS IS" + basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the + License for the specific language governing rights and limitations + under the License. + + The Original Code is ______________________________________. + + The Initial Developer of the Original Code is ________________________. + Portions created by ______________________ are Copyright (C) ______ + _______________________. All Rights Reserved. + + Contributor(s): ______________________________________. + + Alternatively, the contents of this file may be used under the terms + of the _____ license (the "[___] License"), in which case the + provisions of [______] License are applicable instead of those + above. If you wish to allow use of your version of this file only + under the terms of the [____] License and not to allow others to use + your version of this file under the MPL, indicate your decision by + deleting the provisions above and replace them with the notice and + other provisions required by the [___] License. If you do not delete + the provisions above, a recipient may use your version of this file + under either the MPL or the [___] License." + + [NOTE: The text of this Exhibit A may differ slightly from the text of + the notices in the Source Code files of the Original Code. You should + use the text of this Exhibit A rather than the text found in the + Original Code Source Code for Your Modifications.] + +ANNEX A: The GNU GENERAL PUBLIC LICENSE +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. However, as a +special exception, the source code distributed need not include +anything that is normally distributed (in either source or binary +form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component +itself accompanies the executable. + +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. + + 4. You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. 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See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! + + +

trunk/COPYING Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/DCO.developers =================================================================== --- trunk/DCO.developers (nonexistent) +++ trunk/DCO.developers (revision 2) @@ -0,0 +1,58 @@ + Developer's Certificate of Origin 1.0 + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +By making a contribution to this project*, I certify that: + +(a) The contribution was created in whole or in part by me and +I have the right to submit it under the open source license +indicated in the file; or + +(b) The contribution is based upon previous work that, to the + best of my knowledge, is covered under an appropriate open + source license and I have the right under that license to + submit that work with modifications, whether created in whole + or in part by me, under the same open source license (unless + I am permitted to submit under a different license), as + indicated in the file; or + +(c) The contribution was provided directly to me by some other + person who certified (a), (b) or (c) and I have not modified it. + +Definitions: + +*this project refers to the Dirac video codec: + + Development website : http://www.sourceforge.net/projects/dirac + Hardware website : http://www.opencores.org/projects.cgi/web/dirac/overview + Project home page : http://www.bbc.co.uk/rd/projects/dirac/ + + +Developer details +~~~~~~~~~~~~~~~~~ + +Name (please print): + +Address: + + + + + + + + + +email: + + +Signed: + + + + + + + + + +

trunk/DCO.developers Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/README =================================================================== --- trunk/README (nonexistent) +++ trunk/README (revision 2) @@ -0,0 +1,62 @@ +README for the Dirac video codec hardware implementation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +by Thomas Davies and Peter Bleackley, BBC R&D (dirac@rd.bbc.co.uk) + + +1. Executive Summary +~~~~~~~~~~~~~~~~~~~~ + +Dirac is an open source video codec. It uses a traditional hybrid video codec +architecture, but with the wavelet transform instead of the usual block +transforms. Motion compensation uses overlapped blocks to reduce block +artefacts that would upset the transform coding stage. + +Dirac can code just about any size of video, from streaming up to HD and +beyond, although certain presets are defined for different applications and +standards. These cover the parameters that need to be set for the encoder to +work, such as block sizes and temporal prediction structures, which must +otherwise be set by hand. + +Dirac is intended to develop into real coding and decoding software and hardware, capable of plugging +into video processing applications and media players that need compression. It is intended to develop +into a simple set of reliable but effective coding tools that work over a wide variety of content and +formats, using well-understood compression techniques, in a clear and accessible software or hardware +structure. It is not intended as a demonstration or reference coder. + +This release of the hardware implementation comprises VHDL modules for a prototype arithmetic coder +and decoder. These implement a fixed probability model. + + +2. Documentation +~~~~~~~~~~~~~~~~ + +A user guide and a guide to the software is in progress. More details on +running the codec can be found at http://dirac.sourceforge.net/ +Documentation specific to the hardware will be posted the directory /docs. + + +3. Synthesis +~~~~~~~~~~ + + All modules are built in RTL style, and are synthesizable. Modules common to +the encoder and the decoder are in /src/common. Modules specific to the encoder are in /src/encoder +and those specific to the decoder are in /src/decoder. + +Alongside each vhdl module (.vhd) is a .prj file. This specifies the compilation sequence for the +module. + +The initial development of the vhdl was done with Xilinx ISE Webpack. + +4. Simulation +~~~~~~~~~~~ +The encoder may run at clock rates of up to 100MHz, and process an input symbol every 4 clock cycles, +thus giving a possible troughput of 25 Msymbol/second. The decoder can run at the same clock rate as +the encoder, and decode the encoded stream at the same rate that it is produced by the encoder. + +A testbench is provided in /src/testbench, together with a test input file /src/rawdata. This +testbench provides an end-to end simulation of the encoding and decoding process, for a data stream +with a fixed source entropy of 0.498 bits/symbol. The testbench also provides a process that counts +the number of bits produced by the encoder. + +Simulations have been perfomed with Modelsym XE.

trunk/README Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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