URL
https://opencores.org/ocsvn/ecpu_alu/ecpu_alu/trunk
Subversion Repositories ecpu_alu
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/ecpu_alu/trunk/alu/veriwell.key
--- ecpu_alu/trunk/alu/veriwell.key (nonexistent)
+++ ecpu_alu/trunk/alu/veriwell.key (revision 2)
ecpu_alu/trunk/alu/veriwell.key
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/conv_fsm.pl
===================================================================
--- ecpu_alu/trunk/alu/conv_fsm.pl (nonexistent)
+++ ecpu_alu/trunk/alu/conv_fsm.pl (revision 2)
@@ -0,0 +1,28 @@
+#!/usr/bin/perl -w
+
+use strict;
+my $fsm = pop @ARGV;
+
+if (defined $fsm)
+{
+ my $contents = `cat $fsm`;
+
+ my ($others) = $contents =~ /(\w+.+?\=\>)/;
+
+ while ($others !~ /others.+\=\>/ and defined $others)
+ {
+ $contents =~ s/\=\>(.*\n(?:.*?\n)*?)(.+=\>)/\:\n\t\t\t\t\t\tbegin\n$1\n\t\t\t end\n$2/;
+ ($others) = $contents =~ /(\w+.+?\=\>)/;
+ }
+
+ $contents =~ s/others.+\=\>\n((?:.+\n)*.+)end.*?case/default :\n\t\t\t\t\t\tbegin\n$1\tend\n\t\t\t\t\t\tendcase/;
+
+ $contents =~ s/\'(\d)\'/1\'b$1/g;
+ print $contents;
+}
+else
+{
+ print "Please supply a VHDL fsm to parse\n";
+}
+
+
ecpu_alu/trunk/alu/conv_fsm.pl
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu_adder.v
===================================================================
--- ecpu_alu/trunk/alu/alu_adder.v (nonexistent)
+++ ecpu_alu/trunk/alu/alu_adder.v (revision 2)
@@ -0,0 +1,64 @@
+
+// ported from university project for an ALU in VHDL
+module alu_adder (
+ x ,
+ y ,
+ carry_in ,
+ ORsel ,
+ XORsel ,
+
+ carry_out ,
+ xor_result ,
+ or_result ,
+ and_result ,
+ z
+ );
+
+ parameter ADDER_WIDTH = 8;
+
+ input [ADDER_WIDTH - 1 :0] x ;
+ input [ADDER_WIDTH - 1 :0] y ;
+ input carry_in ;
+ input ORsel ;
+ input XORsel ;
+
+ output [ADDER_WIDTH - 1 :0] xor_result ;
+ output [ADDER_WIDTH - 1 :0] or_result ;
+ output [ADDER_WIDTH - 1 :0] and_result ;
+ output reg [ADDER_WIDTH :0] carry_out ;
+ output reg [ADDER_WIDTH - 1 :0] z ;
+
+ wire [ADDER_WIDTH - 1 :0] XxorY ;
+ wire [ADDER_WIDTH - 1 :0] XandY ;
+ wire [ADDER_WIDTH - 1 :0] XorY ;
+
+ // loop variable register
+ reg [31:0] i;
+
+ ////////////////////////////////////////////////////
+ // adder
+ ////////////////////////////////////////////////////
+ assign xor_result = XxorY ;
+ assign or_result = XorY ;
+ assign and_result = XandY ;
+
+ assign XxorY = x ^ y ;
+ assign XandY = x & y ;
+ assign XorY = x | y ;
+
+
+ // adder
+ always @(x or y or carry_out or XxorY or XandY or XorY or XORsel or ORsel)
+ begin
+ carry_out[0] <= carry_in;
+ for (i = 0; i < ADDER_WIDTH ; i = i+1)
+ begin
+ z[i] <= XxorY[i] ^ ( carry_out[i] & XORsel);
+ carry_out[i+1] <= XandY[i] | ((carry_out[i] | ORsel) & XorY[i]);
+ end
+ end
+
+
+endmodule
+
+
ecpu_alu/trunk/alu/alu_adder.v
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/fsm
===================================================================
--- ecpu_alu/trunk/alu/fsm (nonexistent)
+++ ecpu_alu/trunk/alu/fsm (revision 2)
@@ -0,0 +1,53 @@
+ always @(this_opcode)
+ begin
+
+ // reset opcode_sel signals
+ opcode_sel <= 'h0;
+ load_inputs <= 'h0;
+
+ case (this_opcode)
+ cCLR =>
+ opcode_sel(clrALL) <= '1' ;
+ cADD_AB =>
+ opcode_sel(addAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cINC_A =>
+ opcode_sel(incA) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cSUB_AB =>
+ opcode_sel(subAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cCMP_AB =>
+ opcode_sel(cmpAB) <= '1';
+ load_inputs <= '1';
+ cAND_AB =>
+ opcode_sel(andAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cOR_AB =>
+ opcode_sel(orAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cXOR_AB =>
+ opcode_sel(xorAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cCPL_B =>
+ opcode_sel(cplB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cASL_AbyB =>
+ opcode_sel(slAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cASR_AbyB =>
+ opcode_sel(srAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ others =>
+ next_opcode <= this_opcode;
+ endcase
+ end // always begin for FSM
ecpu_alu/trunk/alu/fsm
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/f
===================================================================
--- ecpu_alu/trunk/alu/f (nonexistent)
+++ ecpu_alu/trunk/alu/f (revision 2)
@@ -0,0 +1,45 @@
+ case (this_opcode)
+ cCLR =>
+ opcode_sel(clrALL) <= '1' ;
+ cADD_AB =>
+ opcode_sel(addAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cINC_A =>
+ opcode_sel(incA) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cSUB_AB =>
+ opcode_sel(subAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cCMP_AB =>
+ opcode_sel(cmpAB) <= '1';
+ load_inputs <= '1';
+ cAND_AB =>
+ opcode_sel(andAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cOR_AB =>
+ opcode_sel(orAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cXOR_AB =>
+ opcode_sel(xorAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cCPL_B =>
+ opcode_sel(cplB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cASL_AbyB =>
+ opcode_sel(slAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ cASR_AbyB =>
+ opcode_sel(srAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ others =>
+ next_opcode <= this_opcode;
+ endcase
ecpu_alu/trunk/alu/f
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu.v
===================================================================
--- ecpu_alu/trunk/alu/alu.v (nonexistent)
+++ ecpu_alu/trunk/alu/alu.v (revision 2)
@@ -0,0 +1,116 @@
+// port from university ALU VHDL project
+//
+module alu (A, B, S, Y, CLR, CLK, C, V, Z);
+
+ parameter DWIDTH = 16;
+ parameter OPWIDTH = 4;
+
+ input [(DWIDTH -1):0] A ;
+ input [(DWIDTH -1):0] B ;
+ input [(OPWIDTH-1):0] S ;
+ output [(DWIDTH -1):0] Y ;
+ input CLR ;
+ input CLK ;
+ output C ;
+ output V ;
+ output Z ;
+
+ wire add_AB ;
+ wire inc_A ;
+ wire inc_B ;
+ wire sub_AB ;
+ wire cmp_AB ;
+ wire sl_AB ;
+ wire sr_AB ;
+ wire clr_ALL ;
+ wire dec_A ;
+ wire dec_B ;
+ wire mul_AB ;
+ wire cpl_A ;
+ wire and_AB ;
+ wire or_AB ;
+ wire xor_AB ;
+ wire cpl_B ;
+
+ wire clr_Z ;
+ wire clr_V ;
+ wire clr_C ;
+
+ wire reset ;
+ wire load_inputs ;
+ wire load_outputs ;
+
+ // clear is the same as reset
+ assign reset = CLR;
+
+ // controller instance
+ alu_controller #(OPWIDTH) controller (
+ add_AB ,
+ inc_A ,
+ inc_B ,
+ sub_AB ,
+ cmp_AB ,
+ sl_AB ,
+ sr_AB ,
+ clr_ALL ,
+ dec_A ,
+ dec_B ,
+ mul_AB ,
+ cpl_A ,
+ and_AB ,
+ or_AB ,
+ xor_AB ,
+ cpl_B ,
+
+ clr_Z ,
+ clr_V ,
+ clr_C ,
+
+ load_inputs ,
+ load_outputs,
+
+ S ,
+
+ reset ,
+ CLK
+ );
+
+ // datapath instance
+ alu_datapath #(DWIDTH) datapath (
+ A ,
+ B ,
+ Y ,
+
+ add_AB ,
+ inc_A ,
+ inc_B ,
+ sub_AB ,
+ cmp_AB ,
+ sl_AB ,
+ sr_AB ,
+ clr_ALL ,
+ dec_A ,
+ dec_B ,
+ mul_AB ,
+ cpl_A ,
+ and_AB ,
+ or_AB ,
+ xor_AB ,
+ cpl_B ,
+
+ clr_Z ,
+ clr_V ,
+ clr_C ,
+
+ C ,
+ V ,
+ Z ,
+
+ load_inputs ,
+ load_outputs ,
+
+ reset ,
+
+ CLK
+ );
+endmodule
ecpu_alu/trunk/alu/alu.v
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/fa
===================================================================
--- ecpu_alu/trunk/alu/fa (nonexistent)
+++ ecpu_alu/trunk/alu/fa (revision 2)
@@ -0,0 +1,91 @@
+ case (this_opcode)
+ cCLR :
+ begin
+
+ opcode_sel(clrALL) <= 1'b1 ;
+
+ end
+ cADD_AB :
+ begin
+
+ opcode_sel(addAB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cINC_A :
+ begin
+
+ opcode_sel(incA) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cSUB_AB :
+ begin
+
+ opcode_sel(subAB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cCMP_AB :
+ begin
+
+ opcode_sel(cmpAB) <= 1'b1;
+ load_inputs <= 1'b1;
+
+ end
+ cAND_AB :
+ begin
+
+ opcode_sel(andAB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cOR_AB :
+ begin
+
+ opcode_sel(orAB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cXOR_AB :
+ begin
+
+ opcode_sel(xorAB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cCPL_B :
+ begin
+
+ opcode_sel(cplB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cASL_AbyB :
+ begin
+
+ opcode_sel(slAB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ cASR_AbyB :
+ begin
+
+ opcode_sel(srAB) <= 1'b1;
+ load_inputs <= 1'b1;
+ load_outputs <= 1'b1;
+
+ end
+ default :
+ begin
+ next_opcode <= this_opcode;
+ end
+ endcase
ecpu_alu/trunk/alu/fa
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu_controller.v
===================================================================
--- ecpu_alu/trunk/alu/alu_controller.v (nonexistent)
+++ ecpu_alu/trunk/alu/alu_controller.v (revision 2)
@@ -0,0 +1,243 @@
+// port from university project for ALU in VHDL
+//
+`include "alu_controller.vh"
+module alu_controller (
+ add_AB ,
+ inc_A ,
+ inc_B ,
+ sub_AB ,
+ cmp_AB ,
+ sl_AB ,
+ sr_AB ,
+ clr ,
+ dec_A ,
+ dec_B ,
+ mul_AB ,
+ cpl_A ,
+ and_AB ,
+ or_AB ,
+ xor_AB ,
+ cpl_B ,
+
+ clr_Z ,
+ clr_V ,
+ clr_C ,
+
+ load_inputs ,
+ load_outputs ,
+
+ opcode ,
+ reset ,
+ clk
+ );
+
+ // default opcode bit width
+ parameter OPWIDTH = 4;
+ parameter OPBITS = 1<
ecpu_alu/trunk/alu/alu_controller.v
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu_datapath.v
===================================================================
--- ecpu_alu/trunk/alu/alu_datapath.v (nonexistent)
+++ ecpu_alu/trunk/alu/alu_datapath.v (revision 2)
@@ -0,0 +1,237 @@
+// ported from university project for alu in VHDL
+module alu_datapath (
+ A ,
+ B ,
+ Y ,
+
+ add_AB ,
+ inc_A ,
+ inc_B ,
+ sub_AB ,
+ cmp_AB ,
+ sl_AB ,
+ sr_AB ,
+ clr ,
+ dec_A ,
+ dec_B ,
+ mul_AB ,
+ cpl_A ,
+ and_AB ,
+ or_AB ,
+ xor_AB ,
+ cpl_B ,
+
+ clr_Z ,
+ clr_V ,
+ clr_C ,
+
+ C ,
+ V ,
+ Z ,
+
+ load_inputs ,
+ load_outputs ,
+
+ reset ,
+ clk
+ );
+
+ // data input/output width for the ALU
+ parameter ALU_WIDTH = 8;
+
+ input [ALU_WIDTH - 1:0] A ;
+ input [ALU_WIDTH - 1:0] B ;
+ output [ALU_WIDTH - 1:0] Y ;
+
+ input add_AB ; // ALU control commands
+ input inc_A ;
+ input inc_B ;
+ input sub_AB ;
+ input cmp_AB ;
+ input sl_AB ;
+ input sr_AB ;
+ input clr ;
+ input dec_A ;
+ input dec_B ;
+ input mul_AB ; // Not yet implemented
+ input cpl_A ;
+ input and_AB ;
+ input or_AB ;
+ input xor_AB ; // soft reset! via opcode
+ input cpl_B ;
+
+ input clr_Z ;
+ input clr_V ;
+ input clr_C ;
+
+ output C ; // carry flag
+ output V ; // overflow flag
+ output Z ; // ALU result = 0
+
+ input load_inputs ;
+ input load_outputs;
+
+ input reset ; // hard reset!
+
+ input clk ; // clk wire
+
+
+ wire [ALU_WIDTH - 1:0] adder_in_a ;
+ wire [ALU_WIDTH - 1:0] adder_in_b ;
+ wire [ALU_WIDTH - 1:0] adder_out ;
+
+ wire [ALU_WIDTH - 1:0] shifter_inA ;
+ wire [ALU_WIDTH - 1:0] shifter_inB ;
+ wire [ALU_WIDTH - 1:0] shifter_out ;
+
+ wire shifter_carry ;
+ wire shifter_direction ;
+
+ wire carry_in ;
+ wire carry ;
+ wire adderORsel ;
+ wire adderXORsel ;
+
+ wire [ALU_WIDTH :0] carry_out ;
+
+ wire [ALU_WIDTH - 1:0] AandB ;
+ wire [ALU_WIDTH - 1:0] AxorB ;
+ wire [ALU_WIDTH - 1:0] AorB ;
+
+ wire [ALU_WIDTH - 1:0] logic0 ;
+ wire [ALU_WIDTH - 1:0] logic1 ;
+
+
+ reg [ALU_WIDTH - 1:0] Areg ;
+ reg [ALU_WIDTH - 1:0] Breg ;
+ reg [ALU_WIDTH - 1:0] Yreg ;
+ reg Zreg ;
+ reg Creg ;
+ reg Vreg ;
+
+ wire [ALU_WIDTH - 1:0] alu_out ;
+
+
+ assign logic1 = 'd1 ;
+ assign logic0 = 'd0 ;
+
+ // assign registers to outputs
+ assign Y = Yreg;
+ assign Z = Zreg;
+ assign C = Creg;
+ assign V = Vreg;
+
+ // inputs to adder
+ assign adder_in_a = (cpl_B) ? 'd0 : ((cpl_A) ? ~Areg : ((inc_B) ? 1'b0 :((dec_B) ? {ALU_WIDTH{1'b1}} :Areg)) );
+
+ assign adder_in_b = (!sub_AB && !inc_A && !cpl_A && !cpl_B) ? ((dec_A) ? {ALU_WIDTH{1'b1}} : Breg) :
+ (((sub_AB && !inc_A) || cpl_B) ? ~Breg :
+ ((!sub_AB && inc_A && !cpl_B) ?'d0 :
+ ((cpl_A) ? 'd0 : adder_in_b)));
+
+ // carry_in to adder is set to 1 during subtract and increment
+ // operations
+ assign carry_in = (sub_AB || inc_A || inc_B) ? 1'b1 : 1'b0;
+
+ // select appropriate alu_output to go to Z depending
+ // on control wires
+
+ assign alu_out = ((and_AB || or_AB) && (!sl_AB && !sr_AB)) ? carry_out[ALU_WIDTH:1]
+ : ((sl_AB || sr_AB) ? shifter_out
+ : adder_out);
+
+ // selects use of the Adder as an OR gate
+ assign adderORsel = (or_AB) ? 'b1 : 'b0;
+
+ // selects use of the Adder as an XOR gate
+ // or as a compare [which uses the XOR function]
+ assign adderXORsel = (xor_AB || cmp_AB) ? 'b0 : 'b1;
+
+ // set/unset carry flag depending on relevant conditions
+ assign carry = (add_AB && !and_AB && !or_AB && !xor_AB && !cpl_B && !clr) ?
+ carry_out[ALU_WIDTH] :
+ ((and_AB || or_AB || xor_AB || cpl_B || clr) ?
+ 'b0 : ((sl_AB || sr_AB) ? shifter_carry :carry));
+
+
+ // barrel shifter wires
+ assign shifter_direction = (sr_AB) ? 'b1 : 'b0;
+
+ assign shifter_inA = Areg;
+ assign shifter_inB = Breg;
+
+ alu_adder #(ALU_WIDTH) adder (
+ .x (adder_in_a ) ,
+ .y (adder_in_b ) ,
+ .carry_in (carry_in ) ,
+ .ORsel (adderORsel ) ,
+ .XORsel (adderXORsel) ,
+ .carry_out (carry_out ) ,
+ .z (adder_out )
+ );
+
+ alu_barrel_shifter #(ALU_WIDTH) shifter (
+ .x (shifter_inA ) ,
+ .y (shifter_inB ) ,
+ .z (shifter_out ) ,
+ .c (shifter_carry ) ,
+ .direction (shifter_direction)
+ );
+
+ //registered_ios
+ always @(posedge clk or reset)
+ begin
+ if (reset)
+ begin
+ Areg <= 'd0;
+ Breg <= 'd0;
+ Yreg <= 'd0;
+
+ Zreg <= 'b1;
+ Creg <= 'b0;
+ Vreg <= 'b0;
+ end
+ else
+ begin
+ if (load_inputs)
+ begin
+ Areg <= A;
+ Breg <= B;
+ end
+ if (load_outputs)
+ Yreg <= alu_out;
+
+ //// clear command clears all registers
+ //// and the carry bit
+ if (clr)
+ begin
+ Areg <= 'd0;
+ Breg <= 'd0;
+ Yreg <= 'd0;
+
+ Creg <= 'b0;
+ end
+
+
+ if (clr_Z)
+ Zreg <= 'b0;
+ if (clr_C)
+ Creg <= 'b0;
+ if (clr_V)
+ Vreg <= 'b0;
+
+ // set the Z register
+ if (alu_out == 'd0)
+ Zreg <= 'b1;
+ else
+ Zreg <= 'b0;
+
+
+ Creg <= carry;
+ end
+ end // end always registered IOs;
+
+
+endmodule
+
+
ecpu_alu/trunk/alu/alu_datapath.v
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/compile_alu.simili.files
===================================================================
--- ecpu_alu/trunk/alu/vhdl/compile_alu.simili.files (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/compile_alu.simili.files (revision 2)
@@ -0,0 +1,16 @@
+# Design files
+# ALU
+ ../labs/lab6/alu_adder.vhd
+ ../labs/lab6/alu_barrel_shifter.vhd
+ ../labs/lab6/alu_datapath.vhd
+ ../labs/lab6/alu_controller.vhd
+ ../labs/lab6/alu.vhd
+
+# Design with scan cells inserted
+ ./source/boundary_scan/All/bscan_tester_pkg.vhd
+ ../scripts/alu_bscan.vhd
+#### Testbench files
+ ../labs/lab6/alu_tb.vhd
+ ./source/boundary_scan/All/bscan_tester_all_tests_final.vhd
+ ./source/boundary_scan/All/lfsr_recursive.vhd
+ ../scripts/alu_bscan_tester.vhd
ecpu_alu/trunk/alu/vhdl/compile_alu.simili.files
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_tb.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_tb.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_tb.vhd (revision 2)
@@ -0,0 +1,354 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design [03ELD005]
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU testbench
+-- Entity : alu_tb
+-- Architecture : behavioural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all; -- for unsigned()
+
+use std.textio.all; -- for file i/o
+use work.txt_util.all; -- for string<->other types conversions
+
+entity alu_tb is
+end alu_tb;
+
+architecture behavioural of alu_tb is
+component alu
+ port (
+ A : in std_logic_vector(7 downto 0);
+ B : in std_logic_vector(7 downto 0);
+ S : in std_logic_vector(3 downto 0);
+ Y : out std_logic_vector(7 downto 0);
+ CLR : in std_logic ;
+ CLK : in std_logic ;
+ C : out std_logic ;
+ V : out std_logic ;
+ Z : out std_logic
+ );
+end component;
+
+-- ALU test vector record
+type test_vector is record
+ A : string(8 downto 1) ; -- ALU input operand 1
+ B : string(8 downto 1) ; -- ALU input operand 2
+ S : string(3 downto 1) ; -- ALU input opcode
+end record test_vector;
+
+-- records to store stimulus for verification
+signal this_record, next_record : test_vector;
+-- ALU access signals
+signal A : std_logic_vector(7 downto 0) ;
+signal B : std_logic_vector(7 downto 0) ;
+signal S : std_logic_vector(3 downto 0) ;
+signal Y : std_logic_vector(7 downto 0) ;
+signal CLR : std_logic ;
+signal CLK : std_logic ;
+signal C : std_logic ;
+signal V : std_logic ;
+signal Z : std_logic ;
+
+-- finished = '1' indicates end of test run
+signal finished : std_logic;
+
+-- used to synchronise verification with stimulus
+signal started : boolean := false;
+
+-- testbench clock half period
+constant CLK_HALF_PERIOD : time := 10 ns ;
+constant zero : std_logic_vector(7 downto 0)
+ := (others => '0');
+
+-- procedure to write a string to the screen
+procedure writestr (s : string) is
+ variable lout : line;
+ begin
+ write(lout, s);
+ writeline(output, lout);
+ end writestr;
+
+-- procedure to write a character to the screen
+procedure writechr (s : character) is
+ variable lout : line;
+ begin
+ write(lout, s);
+ writeline(output, lout);
+ end writechr;
+
+begin
+
+ -- instantiate ALU
+ alu_inst0 : alu
+ port map (
+ A ,
+ B ,
+ S ,
+ Y ,
+ CLR ,
+ CLK ,
+ C ,
+ V ,
+ Z
+ );
+
+ -- apply clock stimulus
+ clock_stim : process
+ begin
+ CLK <= '1', '0' after CLK_HALF_PERIOD;
+
+ if (finished /= '1') then
+ wait for 2 * CLK_HALF_PERIOD;
+ else
+ wait; -- end test
+ end if;
+ end process clock_stim;
+
+ apply_test_vectors
+ : process
+ -- uncomment this line for VHDL '87 file i/o
+ --file infile : text is in "alu_test.txt";
+ file infile : text open read_mode is "alu_test.txt";
+ variable buff : line;
+ variable in_vec : test_vector;
+ variable aa, bb, yy
+ : string(A'low + 1 to A'high + 1);
+ variable ss, last_ss
+ : string(1 to 3);
+ variable cc, vv, zz, clrc, space
+ : character;
+ variable count : integer;
+
+ -- function to return the opcode as a std_logic_vector
+ -- from the given string
+ function string2opcode(s: string) return std_logic_vector is
+ variable opcode : std_logic_vector(3 downto 0);
+ begin
+ if (s = "add") then
+ opcode := "0000";
+ elsif (s = "inc") then
+ opcode := "0001";
+ elsif (s = "sub") then
+ opcode := "0010";
+ elsif (s = "cmp") then
+ opcode := "0011";
+ elsif (s = "and") then
+ opcode := "1100";
+ elsif (s = "or ") then
+ opcode := "1101";
+ elsif (s = "xor") then
+ opcode := "1110";
+ elsif (s = "cpl") then
+ opcode := "1111";
+ elsif (s = "asl") then
+ opcode := "0100";
+ elsif (s = "asr") then
+ opcode := "0101";
+ elsif (s = "clr") then
+ opcode := "0110";
+ end if;
+ return opcode;
+ end string2opcode;
+ begin
+ finished <= '0';
+ count := 0;
+ CLR <= '1';
+ started <= false;
+ while ( not endfile(infile) ) loop
+ count := count + 1;
+ -- verify outputs are as expected
+ readline (infile, buff);
+ if (count = 1) then
+ readline (infile, buff); -- first read was the header
+ writestr("**** Start of Test ****");
+ end if;
+ read (buff, aa);
+ read (buff, space);
+
+ read (buff, bb);
+ read (buff, space);
+
+ read (buff, ss);
+ read (buff, space);
+
+ read (buff, clrc);
+
+ -- wait for falling edge of clk
+ wait until (CLK'event and CLK = '0');
+ -- wait for half of half a period
+ wait for (CLK_HALF_PERIOD / 2);
+
+ -- apply stimulus to inputs
+ A <= to_std_logic_vector(aa);
+ B <= to_std_logic_vector(bb);
+ S <= string2opcode(ss);
+ CLR <= to_std_logic(clrc);
+
+ -- store stimulus for use when verifying outputs
+ if (last_ss = "clr") then
+ next_record.A <= str(zero);
+ next_record.B <= str(zero);
+ else
+ next_record.A <= aa;
+ next_record.B <= bb;
+ end if;
+ next_record.S <= ss;
+ last_ss := ss;
+ -- wait for rising edge of clock when data
+ -- should be loaded from registers into ALU
+ wait until clk'event and clk = '1';
+
+ -- set local 'started' flag so verification can
+ -- start
+ -- grace period of 2 clock cycles for ALU to read
+ -- first set of data
+ if (clr = '0' and started = false) then
+ wait until clk'event and clk = '1';
+ wait until clk'event and clk = '1';
+ started <= true;
+ end if;
+ end loop;
+
+ -- end test
+ finished <= '1';
+ wait;
+ end process apply_test_vectors;
+
+ verify_test : process
+ variable result : std_logic_vector(7 downto 0);
+ variable op1, op2: std_logic_vector(7 downto 0);
+ begin
+ -- await positive clock edge
+ wait until clk'event and clk = '1';
+ -- wait a little more after results appear
+ wait for (CLK_HALF_PERIOD/2);
+
+ -- get expected record
+ this_record <= next_record;
+
+ if (started = true and clr = '0') then
+ -- convert string operands from this_record
+ -- into std_logic_vectors
+ op1 := to_std_logic_vector(this_record.A);
+ op2 := to_std_logic_vector(this_record.B);
+
+ -- depending on opcode command string...perform
+ -- high level equivalent of ALU operation and store
+ -- in 'result'
+ if (this_record.S = "add") then
+ result := op1 + op2;
+ elsif (this_record.S = "inc") then
+ result := op1 + 1;
+ elsif (this_record.S = "sub") then
+ result := op1 - op2;
+ elsif (this_record.S = "cmp") then
+ result := y;
+ elsif (this_record.S = "and") then
+ result := op1 and op2;
+ elsif (this_record.S = "or ") then
+ result := op1 or op2;
+ elsif (this_record.S = "xor") then
+ result := op1 xor op2;
+ elsif (this_record.S = "cpl") then
+ result := not op2;
+
+ -- VHDL functions sla and sra require left operand = bit_vector
+ -- and right operand = integer
+ -- bv2slv [see above] converts bit_vector to std_logic_vector
+ elsif (this_record.S = "asl") then
+ result := bv2slv(to_bitvector(op1) sla conv_integer(unsigned(op2 and x"07")));
+ -- Also, these functions fill shifted bit positions with 1s not 0s
+ -- so this has to be taken care of
+ if (conv_integer(unsigned(op2 and x"07")) > 0) then
+ result(conv_integer(unsigned(op2 and x"07")) - 1 downto 0) := (others => '0');
+ end if;
+ elsif (this_record.S = "asr") then
+ result := bv2slv(to_bitvector(op1) sra conv_integer(unsigned(op2 and x"07")));
+ if (conv_integer(unsigned(op2 and x"07")) > 1) then
+ result(result'high - 1 downto result'high - conv_integer(unsigned(op2 and x"07")) + 1 ) := (others => '0');
+ end if;
+ elsif (this_record.S = "clr") then
+ result := y;
+ end if;
+
+ writestr(hstr(to_std_logic_vector(this_record.A)) & " " & this_record.S & " " & hstr(to_std_logic_vector(this_record.B)) & " = " & hstr(Y) & " expected " & hstr(result));
+ assert Y = result
+ report "Output Y is wrong"
+ severity warning;
+ --assert C = to_std_logic(cc)
+ -- report "Output C is wrong"
+ -- severity warning;
+ --assert V = to_std_logic(vv)
+ -- report "Output V is wrong"
+ -- severity warning;
+ --assert Z = to_std_logic(zz)
+ -- report "Output Z is wrong"
+ -- severity warning;
+ end if;
+ end process verify_test;
+
+ vector_stim_out : process ( A ,
+ B ,
+ S ,
+ Y ,
+ CLR ,
+ CLK ,
+ C ,
+ V ,
+ Z
+ )
+-- type out_vector is record
+-- A : string(8 downto 0) ;
+-- B : string(8 downto 0) ;
+-- S : string(4 downto 0) ;
+-- Y : string(8 downto 0) ;
+-- CLR : string(1 downto 1) ;
+-- CLK : string(1 downto 1) ;
+-- C : string(1 downto 1) ;
+-- V : string(1 downto 1) ;
+-- Z : string(1 downto 1) ;
+-- end record;
+ file infile : text open write_mode is "alu_test.out";
+ variable buff : line ;
+ constant space : string := " ";
+ begin
+ if (CLK'event) then
+ write (buff, str(A));
+ write (buff, space);
+ write (buff, str(B));
+ write (buff, space);
+ write (buff, str(S));
+ write (buff, space);
+ write (buff, str(Y));
+ write (buff, space);
+ write (buff, str(CLR));
+ write (buff, space);
+ write (buff, str(CLK));
+ write (buff, space);
+ write (buff, str(C));
+ write (buff, space);
+ write (buff, str(V));
+ write (buff, space);
+ write (buff, str(Z));
+ writeline (infile, buff);
+ end if;
+
+ end process vector_stim_out;
+end behavioural;
+
ecpu_alu/trunk/alu/vhdl/alu_tb.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_from_net.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_from_net.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_from_net.vhd (revision 2)
@@ -0,0 +1,325 @@
+----------------------------------------------------------------------------
+---- ----
+---- WISHBONE RISCMCU IP Core ----
+---- ----
+---- This file is part of the RISCMCU project ----
+---- http://www.opencores.org/projects/riscmcu/ ----
+---- ----
+---- Description ----
+---- Implementation of a RISC Microcontroller based on Atmel AVR ----
+---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
+---- ----
+---- Author(s): ----
+---- - Yap Zi He, yapzihe@hotmail.com ----
+---- ----
+----------------------------------------------------------------------------
+---- ----
+---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
+---- ----
+---- This source file may be used and distributed without ----
+---- restriction provided that this copyright statement is not ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer. ----
+---- ----
+---- This source file is free software; you can redistribute it ----
+---- and/or modify it under the terms of the GNU Lesser General ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any ----
+---- later version. ----
+---- ----
+---- This source is distributed in the hope that it will be ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
+---- PURPOSE. See the GNU Lesser General Public License for more ----
+---- details. ----
+---- ----
+---- You should have received a copy of the GNU Lesser General ----
+---- Public License along with this source; if not, download it ----
+---- from http://www.opencores.org/lgpl.shtml ----
+---- ----
+----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library lpm;
+use lpm.lpm_components.all;
+
+entity v_alu is
+ port( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
+ c2a, c2b : in std_logic;
+ asel : in integer range 0 to 1;
+ bsel : in integer range 0 to 3;
+
+ bitsel : in integer range 0 to 7;
+ set : in std_logic;
+ c_flag, t_flag : in std_logic;
+
+ add, subcp, logic, right, dir, bld, cbisbi, pass_a : in std_logic;
+ cpse, skiptest : in std_logic;
+
+ wcarry : in std_logic;
+ logicsel : in integer range 0 to 3;
+ rightsel : in integer range 0 to 2;
+ dirsel : in integer range 0 to 1;
+
+ clk, clrn : in std_logic;
+
+ c : buffer std_logic_vector(7 downto 0);
+ tosr : buffer std_logic_vector (6 downto 0);
+ skip : out std_logic
+ );
+
+end v_alu;
+
+architecture alu of v_alu is
+
+signal a, b : std_logic_vector(7 downto 0);
+
+signal sr : std_logic_vector(6 downto 0);
+
+signal cin, overflow, cout : std_logic;
+
+signal sum, logic_out, right_out, dir_out, bldcbi_out : std_logic_vector(7 downto 0);
+
+begin
+
+-- Operand Fetch Unit --
+
+process(clrn, clk)
+begin
+ if clrn = '0' then
+ a <= "00000000";
+ b <= "00000000";
+ elsif clk'event and clk = '1' then
+ case asel is
+ when 0 =>
+ if c2a = '1' then
+ a <= c;
+ else
+ a <= reg_rd;
+ end if;
+ when 1 =>
+ a <= "00000000";
+ end case;
+
+ case bsel is
+ when 0 =>
+ if c2b = '1' then
+ b <= c;
+ else
+ b <= reg_rr;
+ end if;
+ when 1 =>
+ b <= reg_rd;
+ when 2 =>
+ b <= imm_value;
+ when 3 =>
+ b <= "00000001";
+ end case;
+ end if;
+end process;
+
+
+-- Execution Unit --
+
+cin <= c_flag when add = '1' and wcarry = '1' else
+ '0' when add = '1' and wcarry = '0' else
+ not c_flag when wcarry = '1' else
+ '1';
+
+
+-- Adder-Subtracter
+adder1 : lpm_add_sub
+ generic map(lpm_width => 8)
+ port map (dataa => a, datab => b, cin => cin, add_sub => add, result => sum, cout => cout, overflow => overflow);
+
+-- Logic Unit
+with logicsel select
+ logic_out <= a and --------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Christmas 2003 coursework...
+-- better than watching "Saved by the Bell- the college years"
+-- Details: Scheduling and allocation in FSMs
+-- 4 bit multiplier design example
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : radix-4 multiplier top level linkink
+-- datapath and controller
+-- Entity : radix4_multi_structure
+-- Architecture : structural
+-- Created on : 01/01/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+b when 0, -- and, andi
+ a or b when 1, -- or, ori
+ a xor b when 2, -- eor
+ not a when 3; -- com
+
+-- Shifter
+right_out(6 downto 0) <= a(7 downto 1);
+with rightsel select
+ right_out(7) <= '0' when 0, -- lsr
+ c_flag when 1, -- ror
+ a(7) when 2; -- asr
+
+-- Direct Unit
+with dirsel select
+ dir_out <= b when 0, -- ldi, mov
+ (a(3 downto 0) & a(7 downto 4)) when 1; -- swap
+
+-- Bit Loader
+process(bld, bitsel, a, t_flag, set)
+begin
+ for i in 0 to 7 loop
+ if i /= bitsel then
+ bldcbi_out(i) <= a(i);
+ elsif bld = '1' then
+ bldcbi_out(i) <= t_flag;
+ else
+ bldcbi_out(i) <= set;
+ end if;
+ end loop;
+end process;
+
+-- Results to Data Bus
+process(add, subcp, logic, right, dir, bld, cbisbi, pass_a, sum, logic_out, right_out, dir_out, bldcbi_out, a)
+begin
+
+ c <= "ZZZZZZZZ";
+
+ -- add, adc, inc, sub, sbc, subi, sbci, cp, cpc, cpi, dec, neg
+ if add = '1' or subcp = '1' then
+ c <= sum;
+ end if;
+
+ -- and, andi, or, ori, eor, com
+ if logic = '1' then
+ c <= logic_out;
+ end if;
+
+ -- lsr, lsr, asr
+ if right = '1' then
+ c <= right_out;
+ end if;
+
+ -- ldi, mov, swap
+ if dir = '1' then
+ c <= dir_out;
+ end if;
+
+ -- bld, cbisbi
+ if bld = '1' or cbisbi = '1' then
+ c <= bldcbi_out;
+ end if;
+
+ -- out, st z, st z+, st -z
+ if pass_a = '1' then
+ c <= a;
+ end if;
+
+end process;
+
+
+-- Skip Evaluation Unit --
+process(cpse, skiptest, a, b, set, bitsel, c)
+begin
+
+ skip <= '0';
+
+ -- cpse
+ if cpse = '1' then
+ if a = b then
+ skip <= '1';
+ end if;
+
+ -- sbrc, sbrs
+ elsif skiptest = '1' then
+ if (set = '1' and a(bitsel) = '1') or (set = '0' and a(bitsel) = '0') then
+ skip <= '1';
+ end if;
+
+ end if;
+end process;
+
+-- Flags Evaluation Unit --
+process(add, subcp, cout, right, a, logic, a, b, sum, logic_out, right_out, c, overflow, sr, bitsel)
+begin
+
+-- C sr(0)
+ if add = '1' then
+ sr(0) <= cout;
+ elsif right = '1' then
+ sr(0) <= a(0);
+ elsif logic = '1' then -- com
+ sr(0) <= '1';
+ else -- subcp
+ sr(0) <= not cout;
+ --sr(0) <= (not a(7) and b(7)) or (b(7) and c(7)) or (c(7) and not a(7));
+ end if;
+
+-- Z sr(1)
+ if (add = '1' or subcp = '1') and sum = "00000000" then
+ sr(1) <= '1';
+ elsif logic = '1' and logic_out = "00000000" then
+ sr(1) <= '1';
+ elsif right = '1' and right_out = "00000000" then
+ sr(1) <= '1';
+ else
+ sr(1) <= '0';
+ end if;
+
+-- N sr(2)
+ if (add = '1' or subcp = '1') and sum(7) = '1' then
+ sr(2) <= '1';
+ elsif logic = '1' and logic_out(7) = '1' then
+ sr(2) <= '1';
+ elsif right = '1' and right_out(7) = '1' then
+ sr(2) <= '1';
+ else
+ sr(2) <= '0';
+ end if;
+
+-- V sr(3)
+ if right = '1' then
+ sr(3) <= right_out(7) xor a(0);
+ elsif logic = '1' then
+ sr(3) <= '0';
+ else
+ sr(3) <= overflow;
+ end if;
+
+-- S sr(4)
+ sr(4) <= sr(2) xor sr(3);
+
+-- H sr(5)
+ if add = '1' then
+ sr(5) <= (a(3) and b(3)) or (b(3) and not sum(3)) or (not sum(3) and a(3));
+ else -- subcp
+ sr(5) <= (not a(3) and b(3)) or (b(3) and sum(3)) or (sum(3) and not a(3));
+ end if;
+
+-- T sr(6)
+ sr(6) <= a(bitsel);
+
+end process;
+
+tosr <= sr;
+
+end alu;
+
+
+
ecpu_alu/trunk/alu/vhdl/alu_from_net.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_test.txt
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_test.txt (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_test.txt (revision 2)
@@ -0,0 +1,34 @@
+dsdfsdssSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
+01010101 00000001 add 1
+01010101 00000000 add 1
+01010101 00000010 add 1
+01010101 00000000 add 1
+01010101 00000100 add 0
+01010101 00000000 add 0
+01010101 00001000 add 0
+01010101 00000000 add 0
+01010101 00010000 add 0
+01010101 00000000 add 0
+01010101 00100000 add 0
+01010101 00000000 add 0
+01010101 01000000 add 0
+01010101 00000000 add 0
+01010101 10000000 add 0
+01010101 00000001 sub 0
+01010101 00000000 sub 0
+01010101 00000010 sub 0
+01010101 00000000 sub 0
+01010101 00000100 sub 0
+01010101 00010000 sub 0
+01010101 01000000 sub 0
+01010101 00000000 sub 0
+01010101 10000000 sub 0
+01010101 00000001 asl 0
+01010101 00000000 asl 0
+01010101 00000010 asr 0
+01010101 00000000 asr 0
+01010101 00000100 asl 0
+01010101 00010000 asr 0
+01010101 01000000 sub 0
+01010101 00000000 sub 0
+01010101 10000000 sub 0
ecpu_alu/trunk/alu/vhdl/alu_test.txt
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/do_all_simili
===================================================================
--- ecpu_alu/trunk/alu/vhdl/do_all_simili (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/do_all_simili (revision 2)
@@ -0,0 +1,6 @@
+#!/bin/bash
+export SYMPHONYEDA="/usr/local/Simili31"
+. /usr/local/Simili31/bin/init.sh
+../scripts/bscan_compile_simili compile.simili.files -log compile.simili.results -lib main_lib
+../scripts/bscan_compile_simili compile_alu.simili.files -log compile_alu.simili.results -lib main_lib
+../scripts/bscan_sim_simili alu_bscan_tester
ecpu_alu/trunk/alu/vhdl/do_all_simili
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_adder.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_adder.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_adder.vhd (revision 2)
@@ -0,0 +1,78 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU datapath
+-- Entity : alu_datapath
+-- Architecture : structural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity alu_adder is
+ generic (
+ adder_width : integer := 8
+ );
+ port (
+ x : in std_logic_vector(adder_width - 1 downto 0) ;
+ y : in std_logic_vector(adder_width - 1 downto 0) ;
+ carry_in : in std_logic ;
+ ORsel : in std_logic ;
+ XORsel : in std_logic ;
+ carry_out : out std_logic_vector(adder_width downto 0) ;
+ xor_result : out std_logic_vector(adder_width - 1 downto 0) ;
+ or_result : out std_logic_vector(adder_width - 1 downto 0) ;
+ and_result : out std_logic_vector(adder_width - 1 downto 0) ;
+ z : out std_logic_vector(adder_width - 1 downto 0)
+ );
+end alu_adder;
+
+
+architecture structural of alu_adder is
+signal c : std_logic_vector(adder_width downto 0);
+signal XxorY,
+ XandY,
+ XorY : std_logic_vector(adder_width - 1 downto 0);
+
+begin
+
+ ----------------------------------------------------
+ -- adder
+ ----------------------------------------------------
+ xor_result <= XxorY;
+ or_result <= XorY ;
+ and_result <= XandY;
+
+ XxorY <= x xor y;
+ XandY <= x and y;
+ XorY <= x or y;
+
+ carry_out <= c;
+
+ adder : process (x, y, c, XxorY, XandY, XorY)
+ begin
+ c(0) <= carry_in;
+ for i in z'range loop
+ z(i) <= XxorY(i) xor (c(i) and XORsel);
+ c(i+1) <= XandY(i) or
+ ((c(i) or ORsel) and XorY(i));
+ end loop;
+ end process adder;
+
+end structural;
+
+
ecpu_alu/trunk/alu/vhdl/alu_adder.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/runit
===================================================================
--- ecpu_alu/trunk/alu/vhdl/runit (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/runit (revision 2)
@@ -0,0 +1,5 @@
+#!/bin/bash
+export SYMPHONYEDA="/usr/local/Simili31"
+. /usr/local/Simili31/bin/init.sh
+sonata
+
ecpu_alu/trunk/alu/vhdl/runit
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter_tb.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter_tb.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter_tb.vhd (revision 2)
@@ -0,0 +1,88 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : test ALU barrel shifter
+-- Entity : alu_barrel_shifter_tb
+-- Architecture : structural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity alu_barrel_shifter_tb is
+end alu_barrel_shifter_tb;
+
+
+architecture structural of alu_barrel_shifter_tb is
+component alu_barrel_shifter
+ port (
+ x : in std_logic_vector(7 downto 0) ;
+ y : in std_logic_vector(7 downto 0) ;
+ z : out std_logic_vector(7 downto 0) ;
+ direction : in std_logic
+ );
+end component;
+
+signal x,
+ y,
+ z : std_logic_vector(7 downto 0) := (others => '0');
+signal direction : std_logic;
+signal finished, clk : std_logic;
+begin
+
+ ----------------------------------------------------
+ -- adder
+ ----------------------------------------------------
+ clk_stim : process
+ begin
+
+ clk <= '1', '0' after 10 ns;
+ if ( finished = '1') then
+ wait;
+ else
+ wait for 20 ns;
+ end if;
+ end process clk_stim;
+
+ shifter : alu_barrel_shifter
+ port map (
+ x,
+ y,
+ z,
+ direction
+ );
+
+
+ stimulus : process (clk)
+ begin
+ finished <= '0';
+ direction<= '1';
+ if (clk'event and clk = '1') then
+ x <= x + 2;
+ end if;
+
+ if (conv_integer(x) mod 3 = 0) then
+ y <= y + 1;
+ end if;
+ if (x > 10) then
+ finished <= '1';
+ end if;
+ end process stimulus;
+end structural;
+
+
+
ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter_tb.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu.vhd (revision 2)
@@ -0,0 +1,206 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design [03ELD005]
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU controller
+-- Entity : alu_controller
+-- Architecture : behavioural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity alu is
+ port (
+ A : in std_logic_vector(7 downto 0);
+ B : in std_logic_vector(7 downto 0);
+ S : in std_logic_vector(3 downto 0);
+ Y : out std_logic_vector(7 downto 0);
+ CLR : in std_logic ;
+ CLK : in std_logic ;
+ C : out std_logic ;
+ V : out std_logic ;
+ Z : out std_logic
+ );
+end alu;
+
+architecture structural of alu is
+component alu_controller
+ port (
+ add_AB : out std_logic;
+ sub_AB : out std_logic;
+ inc_A : out std_logic;
+ inc_B : out std_logic;
+ dec_A : out std_logic;
+ dec_B : out std_logic;
+ cmp_AB : out std_logic;
+ and_AB : out std_logic;
+ or_AB : out std_logic;
+ xor_AB : out std_logic;
+ cpl_B : out std_logic;
+ cpl_A : out std_logic;
+ sl_AB : out std_logic;
+ sr_AB : out std_logic;
+ clr : out std_logic;
+
+ clr_Z : out std_logic;
+ clr_V : out std_logic;
+ clr_C : out std_logic;
+
+ load_inputs : out std_logic;
+ load_outputs: out std_logic;
+
+
+ opcode : in std_logic_vector(3 downto 0);
+ reset : in std_logic;
+ clk : in std_logic
+ );
+end component;
+component alu_datapath
+ port (
+ A : in std_logic_vector(7 downto 0);
+ B : in std_logic_vector(7 downto 0);
+ Y : out std_logic_vector(7 downto 0);
+
+ add_AB : in std_logic;
+ sub_AB : in std_logic;
+ inc_A : in std_logic;
+ inc_B : in std_logic;
+ dec_A : in std_logic;
+ dec_B : in std_logic;
+ cmp_AB : in std_logic;
+ and_AB : in std_logic;
+ or_AB : in std_logic;
+ xor_AB : in std_logic;
+ cpl_B : in std_logic;
+ cpl_A : in std_logic;
+ sl_AB : in std_logic;
+ sr_AB : in std_logic;
+ clr : in std_logic;
+
+ clr_Z : in std_logic;
+ clr_V : in std_logic;
+ clr_C : in std_logic;
+
+ C : out std_logic;
+ V : out std_logic;
+ Z : out std_logic;
+
+ load_inputs : in std_logic;
+ load_outputs: in std_logic;
+
+ reset : in std_logic;
+
+ clk : in std_logic
+ );
+end component;
+
+signal add_AB : std_logic ;
+signal sub_AB : std_logic ;
+signal inc_A : std_logic ;
+signal inc_B : std_logic ;
+signal dec_A : std_logic ;
+signal dec_B : std_logic ;
+signal cmp_AB : std_logic ;
+signal and_AB : std_logic ;
+signal or_AB : std_logic ;
+signal xor_AB : std_logic ;
+signal cpl_B : std_logic ;
+signal cpl_A : std_logic ;
+signal sl_AB : std_logic ;
+signal sr_AB : std_logic ;
+signal clr_ALL : std_logic ;
+
+signal clr_Z : std_logic ;
+signal clr_V : std_logic ;
+signal clr_C : std_logic ;
+
+signal reset : std_logic ;
+signal load_inputs : std_logic ;
+signal load_outputs: std_logic ;
+
+begin
+ -- clear is the same as reset
+ reset <= CLR;
+
+ controller : alu_controller
+ port map (
+ add_AB ,
+ sub_AB ,
+ inc_A ,
+ inc_B ,
+ dec_A ,
+ dec_B ,
+ cmp_AB ,
+ and_AB ,
+ or_AB ,
+ xor_AB ,
+ cpl_B ,
+ cpl_A ,
+ sl_AB ,
+ sr_AB ,
+ clr_ALL ,
+
+ clr_Z ,
+ clr_V ,
+ clr_C ,
+
+ load_inputs ,
+ load_outputs,
+
+ S ,
+
+ reset ,
+ clk
+ );
+ datapath : alu_datapath
+ port map (
+ A ,
+ B ,
+ Y ,
+
+ add_AB ,
+ sub_AB ,
+ inc_A ,
+ inc_B ,
+ dec_A ,
+ dec_B ,
+ cmp_AB ,
+ and_AB ,
+ or_AB ,
+ xor_AB ,
+ cpl_B ,
+ cpl_A ,
+ sl_AB ,
+ sr_AB ,
+ clr_ALL ,
+
+ clr_Z ,
+ clr_V ,
+ clr_C ,
+
+ C ,
+ V ,
+ Z ,
+
+ load_inputs ,
+ load_outputs,
+
+ reset,
+
+ clk
+ );
+end structural;
ecpu_alu/trunk/alu/vhdl/alu.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_controller.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_controller.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_controller.vhd (revision 2)
@@ -0,0 +1,190 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design [03ELD005]
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU opcode_seller
+-- Entity : alu_opcode_seller
+-- Architecture : behavioural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity alu_controller is
+ generic (
+ ALU_WIDTH : integer := 8
+ );
+ port (
+ add_AB : out std_logic;
+ sub_AB : out std_logic;
+ inc_A : out std_logic;
+ inc_B : out std_logic;
+ dec_A : out std_logic;
+ dec_B : out std_logic;
+ cmp_AB : out std_logic;
+ and_AB : out std_logic;
+ or_AB : out std_logic;
+ xor_AB : out std_logic;
+ cpl_B : out std_logic;
+ cpl_A : out std_logic;
+ sl_AB : out std_logic;
+ sr_AB : out std_logic;
+ clr : out std_logic;
+
+ clr_Z : out std_logic;
+ clr_V : out std_logic;
+ clr_C : out std_logic;
+
+ load_inputs : out std_logic;
+ load_outputs: out std_logic;
+
+ opcode : in std_logic_vector(3 downto 0);
+ reset : in std_logic;
+ clk : in std_logic
+ );
+
+end alu_controller;
+
+
+architecture behavioural of alu_controller is
+
+subtype opcode_selLER_opcode is std_logic_vector(3 downto 0);
+type OPERATION is (add_op, inc_op, sub_op, cmp_op, and_op, or_op, xor_op, cpl_op, asl_op,asr_op, clr_op);
+signal this_opcode, next_opcode
+ : opcode_selLER_opcode;
+signal opcode_sel : std_logic_vector(16 downto 0);
+signal control : std_logic_vector(2 downto 0);
+
+constant addAB : integer := 00;
+constant subAB : integer := 01;
+constant incA : integer := 02;
+constant incB : integer := 03;
+
+constant decA : integer := 04;
+constant decB : integer := 05;
+constant cmpAB : integer := 06;
+constant andAB : integer := 07;
+
+constant orAB : integer := 08;
+constant xorAB : integer := 09;
+constant cplB : integer := 10;
+constant cplA : integer := 11;
+
+constant slAB : integer := 12;
+constant srAB : integer := 13;
+constant clrALL : integer := 14;
+constant clrZ : integer := 0;
+
+constant clrV : integer := 1;
+constant clrC : integer := 2;
+
+constant cADD_AB : opcode_selLER_opcode := "0000";
+constant cINC_A : opcode_selLER_opcode := "0001";
+constant cSUB_AB : opcode_selLER_opcode := "0010";
+constant cCMP_AB : opcode_selLER_opcode := "0011";
+constant cAND_AB : opcode_selLER_opcode := "1100";
+constant cOR_AB : opcode_selLER_opcode := "1101";
+constant cXOR_AB : opcode_selLER_opcode := "1110";
+constant cCPL_B : opcode_selLER_opcode := "1111";
+constant cASL_AbyB : opcode_selLER_opcode := "0100";
+constant cASR_AbyB : opcode_selLER_opcode := "0101";
+constant cCLR : opcode_selLER_opcode := "0110";
+
+
+begin
+
+
+ add_AB <= opcode_sel(addAB);
+ sub_AB <= opcode_sel(subAB);
+ inc_A <= opcode_sel(incA);
+ inc_B <= opcode_sel(incB);
+ dec_A <= opcode_sel(decA);
+ dec_B <= opcode_sel(decB);
+ cmp_AB <= opcode_sel(cmpAB);
+ and_AB <= opcode_sel(andAB);
+ or_AB <= opcode_sel(orAB);
+ xor_AB <= opcode_sel(xorAB);
+ cpl_B <= opcode_sel(cplB);
+ cpl_A <= opcode_sel(cplA);
+ sl_AB <= opcode_sel(slAB);
+ sr_AB <= opcode_sel(srAB);
+ clr <= opcode_sel(clrALL);
+
+ clr_Z <= control(clrZ);
+ clr_V <= control(clrV);
+ clr_C <= control(clrC);
+
+ state : process (clk)
+ begin
+ if (reset = '1') then
+ this_opcode <= cCLR;
+ elsif (clk'event and clk = '1') then
+ this_opcode <= opcode;
+ end if;
+ end process state;
+
+ comb : process (this_opcode)
+ begin
+ -- reset opcode_sel signals
+ opcode_sel <= (others => '0');
+ load_inputs <= '0';
+ case (this_opcode) is
+ when cCLR =>
+ opcode_sel(clrALL) <= '1' ;
+ when cADD_AB =>
+ opcode_sel(addAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cINC_A =>
+ opcode_sel(incA) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cSUB_AB =>
+ opcode_sel(subAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cCMP_AB =>
+ opcode_sel(cmpAB) <= '1';
+ load_inputs <= '1';
+ when cAND_AB =>
+ opcode_sel(andAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cOR_AB =>
+ opcode_sel(orAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cXOR_AB =>
+ opcode_sel(xorAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cCPL_B =>
+ opcode_sel(cplB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cASL_AbyB =>
+ opcode_sel(slAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when cASR_AbyB =>
+ opcode_sel(srAB) <= '1';
+ load_inputs <= '1';
+ load_outputs <= '1';
+ when others =>
+ next_opcode <= this_opcode;
+ end case;
+ end process comb;
+end behavioural;
ecpu_alu/trunk/alu/vhdl/alu_controller.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_stimulus.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_stimulus.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_stimulus.vhd (revision 2)
@@ -0,0 +1,75 @@
+ vector_stim_in : process ( clock_tb )
+ variable i : integer := 0;
+type out_vector is record
+ A : std_logic_vector(8 downto 1) ;
+ B : std_logic_vector(8 downto 1) ;
+ S : std_logic_vector(4 downto 1) ;
+ Y : std_logic_vector(8 downto 1) ;
+ CLR : std_logic ;
+ CLK : std_logic ;
+ C : std_logic ;
+ V : std_logic ;
+ Z : std_logic ;
+ end record;
+type out_vectors is array (natural range <>) of out_vector;
+constant vectors : out_vectors := (
+("UUUUUUUU", "UUUUUUUU", "UUUU", "UUUUUUUU", '1', '1', 'U', 'U', 'U'),
+("01010101", "00000001", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000010", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01011001", '0', '1', '0', '0', '0'),
+("01010101", "00001000", "0000", "01011001", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0000", "01011101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00100000", "0000", "01100101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0000", "01110101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0000", "10010101", '0', '1', '0', '0', '0'),
+("01010101", "00000001", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "11010101", '0', '1', '0', '0', '0'),
+("01010101", "00000010", "0010", "01010100", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0010", "01010011", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0010", "01010001", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "01000101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "00000001", "0100", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0100", "11010101", '0', '1', '0', '0', '0'),
+("01010101", "00000010", "0101", "10101010", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0101", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0100", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0101", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0010", "01010000", '0', '1', '1', '0', '0'),
+("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "01010101", '0', '1', '0', '0', '0'));
+ begin
+ if (clock_tb'event and clock_tb = '1') then
+ if ( i <= vectors'high) then
+ A <= vectors(i).A;
+ B <= vectors(i).B;
+ S <= vectors(i).S;
+ --Y <= vectors(i).Y;
+ CLR <= vectors(i).CLR;
+ CLK <= vectors(i).CLK;
+ --C <= vectors(i).C;
+ --V <= vectors(i).V;
+ --Z <= vectors(i).Z;
+
+ i := i + 1;
+ else
+ finished <= '1';
+ end if;
+ else
+ CLK <= clock_tb;
+ end if;
+
+ end process vector_stim_in;
+
ecpu_alu/trunk/alu/vhdl/alu_stimulus.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_datapath.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_datapath.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_datapath.vhd (revision 2)
@@ -0,0 +1,282 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design [03ELD005]
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU datapath description
+-- Entity : alu_datapath
+-- Architecture : behavioural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity alu_datapath is
+ generic (
+ ALU_WIDTH : integer := 8
+ );
+ port (
+ A : in std_logic_vector(ALU_WIDTH - 1 downto 0);
+ B : in std_logic_vector(ALU_WIDTH - 1 downto 0);
+ Y : out std_logic_vector(ALU_WIDTH - 1 downto 0);
+
+ add_AB : in std_logic; -- ALU control commands
+ sub_AB : in std_logic;
+ inc_A : in std_logic;
+ inc_B : in std_logic;
+ dec_A : in std_logic;
+ dec_B : in std_logic;
+ cmp_AB : in std_logic;
+ and_AB : in std_logic;
+ or_AB : in std_logic;
+ xor_AB : in std_logic;
+ cpl_B : in std_logic;
+ cpl_A : in std_logic;
+ sl_AB : in std_logic;
+ sr_AB : in std_logic;
+ clr : in std_logic; -- soft reset! via opcode
+
+ clr_Z : in std_logic;
+ clr_V : in std_logic;
+ clr_C : in std_logic;
+
+ C : out std_logic; -- carry flag
+ V : out std_logic; -- overflow flag
+ Z : out std_logic; -- ALU result = 0
+
+ load_inputs : in std_logic;
+ load_outputs: in std_logic;
+
+ reset : in std_logic; -- hard reset!
+
+ clk : in std_logic -- clk signal
+ );
+end alu_datapath;
+
+architecture behavioural of alu_datapath is
+component alu_adder
+ generic (
+ adder_width : integer := ALU_WIDTH
+ );
+ port (
+ x : in std_logic_vector(ALU_WIDTH - 1 downto 0);
+ y : in std_logic_vector(ALU_WIDTH - 1 downto 0);
+ carry_in : in std_logic ;
+ ORsel : in std_logic ;
+ XORsel : in std_logic ;
+ carry_out : out std_logic_vector(ALU_WIDTH downto 0);
+ xor_result : out std_logic_vector(ALU_WIDTH - 1 downto 0);
+ or_result : out std_logic_vector(ALU_WIDTH - 1 downto 0);
+ and_result : out std_logic_vector(ALU_WIDTH - 1 downto 0);
+ z : out std_logic_vector(ALU_WIDTH - 1 downto 0)
+ );
+end component;
+component mux8to1_1bit is
+ PORT (
+ sel : in std_logic_vector(2 downto 0);
+ din0 : in std_logic ;
+ din1 : in std_logic ;
+ din2 : in std_logic ;
+ din3 : in std_logic ;
+ din4 : in std_logic ;
+ din5 : in std_logic ;
+ din6 : in std_logic ;
+ din7 : in std_logic ;
+ dout : out std_logic
+ );
+end component;
+component alu_barrel_shifter
+ port (
+ x : in std_logic_vector(7 downto 0);
+ y : in std_logic_vector(7 downto 0);
+ z : out std_logic_vector(7 downto 0);
+ c : out std_logic ;
+ direction : in std_logic
+ );
+end component;
+component mux2to1_1bit is
+ port (
+ sel : in std_logic ;
+ din0 : in std_logic ;
+ din1 : in std_logic ;
+ dout : out std_logic
+ );
+end component;
+
+signal adder_in_a ,
+ adder_in_b ,
+ adder_out : std_logic_vector(ALU_WIDTH - 1 downto 0) ;
+signal shifter_inA ,
+ shifter_inB ,
+ shifter_out : std_logic_vector(ALU_WIDTH - 1 downto 0) ;
+signal shifter_carry,
+ shifter_direction
+ : std_logic ;
+signal carry_in ,
+ carry ,
+ adderORsel ,
+ adderXORsel : std_logic ;
+signal carry_out : std_logic_vector(ALU_WIDTH downto 0) ;
+signal Areg ,
+ Breg ,
+ Yreg ,
+ B_path ,
+ alu_out : std_logic_vector(ALU_WIDTH - 1 downto 0) ;
+signal Zreg,
+ Creg,
+ Vreg : std_logic ;
+
+signal AandB,
+ AxorB,
+ AorB : std_logic_vector(ALU_WIDTH - 1 downto 0) ;
+signal logic1,
+ logic0 : std_logic_vector(ALU_WIDTH - 1 downto 0) ;
+begin
+
+ logic1 <= (others => '1') ;
+ logic0 <= (others => '0') ;
+
+ -- assign registers to outputs
+ Y <= Yreg;
+ Z <= Zreg;
+ C <= Creg;
+ V <= Vreg;
+
+ -- inputs to adder
+ adder_in_a <= (others => '0') when (cpl_B = '1') else
+ Areg ;
+ adder_in_b <= Breg when
+ (sub_AB = '0' and inc_A = '0' and cpl_B = '0') else
+ not Breg when
+ ((sub_AB = '1' and inc_A = '0') or cpl_B = '1') else
+ (others => '0') when
+ (sub_AB = '0' and inc_A = '1' and cpl_B = '0');
+
+ -- carry_in to adder is set to 1 during subtract and increment
+ -- operations
+ carry_in <= '1' when
+ (sub_AB = '1' or inc_A = '1' ) else
+ '0';
+
+ -- select appropriate alu_output to go to Z depending
+ -- on control signals
+ alu_out <= carry_out(ALU_WIDTH downto 1) when
+ ((and_AB = '1' or or_AB = '1') and (sl_AB = '0' and sr_AB = '0')) else
+ shifter_out when
+ (sl_AB = '1' or sr_AB = '1') else
+ adder_out;
+
+ -- selects use of the Adder as an OR gate
+ adderORsel <= '1' when
+ (or_AB = '1') else
+ '0';
+ -- selects use of the Adder as an XOR gate
+ -- or as a compare [which uses the XOR function]
+ adderXORsel <= '0' when
+ (xor_AB = '1' or cmp_AB = '1') else
+ '1';
+
+ -- set/unset carry flag depending on relevant conditions
+ carry <= carry_out(carry_out'high) when
+ (add_AB = '1' and and_AB = '0' and or_AB = '0' and xor_AB = '0' and cpl_B = '0' and clr = '0') else
+ '0' when
+ (and_AB = '1' or or_AB = '1' or xor_AB = '1' or cpl_B = '1' or clr = '1') else
+ shifter_carry when
+ (sl_AB = '1' or sr_AB = '1');
+
+ -- barrel shifter signals
+ shifter_direction <= '1' when
+ (sr_AB = '1') else
+ '0';
+
+ shifter_inA <= Areg;
+ shifter_inB <= Breg;
+
+ adder : alu_adder
+ port map (
+ x => adder_in_a ,
+ y => adder_in_b ,
+ carry_in => carry_in ,
+ ORsel => adderORsel ,
+ XORsel => adderXORsel ,
+ carry_out => carry_out ,
+ z => adder_out
+ );
+
+ shifter : alu_barrel_shifter
+ port map (
+ x => shifter_inA ,
+ y => shifter_inB ,
+ z => shifter_out ,
+ c => shifter_carry ,
+ direction => shifter_direction
+ );
+
+ registered_ios : process (reset, clr, clk, A, B, adder_out, Creg, Zreg, Vreg, load_inputs, load_outputs)
+ begin
+ if (reset = '1') then
+ Areg <= (others => '0');
+ Breg <= (others => '0');
+ Yreg <= (others => '0');
+
+ Zreg <= '1';
+ Creg <= '0';
+ Vreg <= '0';
+ elsif (clk'event and clk = '1') then
+ if (load_inputs = '1') then
+ Areg <= A;
+ Breg <= B;
+ end if;
+ if (load_outputs = '1') then
+ Yreg <= alu_out;
+ end if;
+
+ -- clear command clears all registers
+ -- and the carry bit
+ if (clr = '1') then
+ Areg <= (others => '0');
+ Breg <= (others => '0');
+ Yreg <= (others => '0');
+
+ Creg <= '0';
+ end if;
+
+
+ if (clr_Z = '1') then
+ Zreg <= '0';
+ end if;
+ if (clr_C = '1') then
+ Creg <= '0';
+ end if;
+ if (clr_V = '1') then
+ Vreg <= '0';
+ end if;
+
+ -- set the Z register
+ if (alu_out = 0) then
+ Zreg <= '1';
+ else
+ Zreg <= '0';
+ end if;
+
+
+ Creg <= carry;
+ end if;
+ end process registered_ios;
+
+
+end behavioural;
+
+
ecpu_alu/trunk/alu/vhdl/alu_datapath.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_analog_tb.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_analog_tb.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_analog_tb.vhd (revision 2)
@@ -0,0 +1,193 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design [03ELD005]
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU testbench
+-- Entity : alu_tb
+-- Architecture : behavioural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_unsigned.all;
+--use ieee.std_logic_arith.all; -- for unsigned()
+
+-- use std.textio.all; -- for file i/o
+-- use work.txt_util.all; -- for string<->other types conversions
+
+entity alu_analog_tb is
+-- port (
+-- clock_tb : in std_logic
+-- );
+end alu_analog_tb;
+
+architecture behavioural of alu_analog_tb is
+component alu
+ port (
+ A : in std_logic_vector(7 downto 0);
+ B : in std_logic_vector(7 downto 0);
+ S : in std_logic_vector(3 downto 0);
+ Y : out std_logic_vector(7 downto 0);
+ CLR : in std_logic ;
+ CLK : in std_logic ;
+ C : out std_logic ;
+ V : out std_logic ;
+ Z : out std_logic
+ );
+end component;
+component mtest IS
+ PORT(
+ clock_tb: IN STD_LOGIC;
+ A : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ CLR : OUT STD_LOGIC;
+ ground_in : IN STD_LOGIC;
+ CLK : OUT STD_LOGIC
+ );
+END component;
+
+-- ALU test vector record
+-- records to store stimulus for verification
+-- ALU access signals
+signal A : std_logic_vector(7 downto 0) ;
+signal B : std_logic_vector(7 downto 0) ;
+signal S : std_logic_vector(3 downto 0) ;
+signal Y : std_logic_vector(7 downto 0) ;
+signal CLR : std_logic ;
+signal CLK : std_logic ;
+signal C : std_logic ;
+signal V : std_logic ;
+signal Z : std_logic ;
+signal clock_tb : std_logic ;
+signal ground_in : std_logic ;
+
+-- finished = '1' indicates end of test run
+
+-- testbench clock half period
+constant clock_tb_HALF_PERIOD : time := 10 ns ;
+constant zero : std_logic_vector(7 downto 0)
+ := (others => '0');
+signal finished :std_logic;
+
+-- procedure to write a string to the screen
+-- procedure writestr (s : string) is
+-- variable lout : line;
+-- begin
+-- write(lout, s);
+-- writeline(output, lout);
+-- end writestr;
+--
+-- -- procedure to write a character to the screen
+-- procedure writechr (s : character) is
+-- variable lout : line;
+-- begin
+-- write(lout, s);
+-- writeline(output, lout);
+-- end writechr;
+--
+type out_vector is record
+ A : std_logic_vector(8 downto 1) ;
+ B : std_logic_vector(8 downto 1) ;
+ S : std_logic_vector(4 downto 1) ;
+ Y : std_logic_vector(8 downto 1) ;
+ CLR : std_logic ;
+ CLK : std_logic ;
+ C : std_logic ;
+ V : std_logic ;
+ Z : std_logic ;
+ end record;
+type out_vectors is array (natural range <>) of out_vector;
+constant vectors : out_vectors := (
+("UUUUUUUU", "UUUUUUUU", "UUUU", "UUUUUUUU", '1', '1', 'U', 'U', 'U'),
+("01010101", "00000001", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000010", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01011001", '0', '1', '0', '0', '0'),
+("01010101", "00001000", "0000", "01011001", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0000", "01011101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00100000", "0000", "01100101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0000", "01110101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0000", "10010101", '0', '1', '0', '0', '0'),
+("01010101", "00000001", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "11010101", '0', '1', '0', '0', '0'),
+("01010101", "00000010", "0010", "01010100", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0010", "01010011", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0010", "01010001", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "01000101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "00000001", "0100", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0100", "11010101", '0', '1', '0', '0', '0'),
+("01010101", "00000010", "0101", "10101010", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0101", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0100", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0101", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0010", "01010000", '0', '1', '1', '0', '0'),
+("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "01010101", '0', '1', '0', '0', '0'));
+
+
+begin
+
+ -- instantiate ALU
+ alu_inst0 : alu
+ port map (
+ A ,
+ B ,
+ S ,
+ Y ,
+ CLR ,
+ CLK ,
+ C ,
+ V ,
+ Z
+ );
+mtester: mtest
+ PORT MAP (
+ clock_tb,
+ A ,
+ B ,
+ S ,
+ CLR,
+ ground_in,
+ CLK
+ );
+
+ ground_in <= '1', '0' after 100 ns;
+ -- apply clock stimulus
+ clock_stim : process
+ begin
+ clock_tb <= '1', '0' after clock_tb_HALF_PERIOD;
+
+ if (finished /= '1') then
+ wait for 2 * clock_tb_HALF_PERIOD;
+ else
+ wait; -- end test
+ end if;
+ end process clock_stim;
+
+end behavioural;
+
ecpu_alu/trunk/alu/vhdl/alu_analog_tb.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_analog_cadence_tb.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_analog_cadence_tb.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_analog_cadence_tb.vhd (revision 2)
@@ -0,0 +1,194 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design [03ELD005]
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU testbench
+-- Entity : alu_tb
+-- Architecture : behavioural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_unsigned.all;
+--use ieee.std_logic_arith.all; -- for unsigned()
+
+-- use std.textio.all; -- for file i/o
+-- use work.txt_util.all; -- for string<->other types conversions
+
+entity alu_analog_cadence_tb is
+ port (
+ clock_tb : in std_logic
+ );
+end alu_analog_cadence_tb;
+
+architecture behavioural of alu_analog_cadence_tb is
+component alu
+ port (
+ A : in std_logic_vector(7 downto 0);
+ B : in std_logic_vector(7 downto 0);
+ S : in std_logic_vector(3 downto 0);
+ Y : out std_logic_vector(7 downto 0);
+ reset : in std_logic ;
+ CLK : in std_logic ;
+ C : out std_logic ;
+ V : out std_logic ;
+ Z : out std_logic
+ );
+end component;
+
+-- ALU test vector record
+-- records to store stimulus for verification
+-- ALU access signals
+signal A : std_logic_vector(7 downto 0) ;
+signal B : std_logic_vector(7 downto 0) ;
+signal S : std_logic_vector(3 downto 0) ;
+signal Y : std_logic_vector(7 downto 0) ;
+signal CLR : std_logic ;
+signal CLK : std_logic ;
+signal C : std_logic ;
+signal V : std_logic ;
+signal Z : std_logic ;
+-- signal clock_tb : std_logic ;
+--
+-- -- finished = '1' indicates end of test run
+--
+-- -- testbench clock half period
+-- constant clock_tb_HALF_PERIOD : time := 10 ns ;
+constant zero : std_logic_vector(7 downto 0)
+ := (others => '0');
+signal finished :std_logic;
+
+-- procedure to write a string to the screen
+-- procedure writestr (s : string) is
+-- variable lout : line;
+-- begin
+-- write(lout, s);
+-- writeline(output, lout);
+-- end writestr;
+--
+-- -- procedure to write a character to the screen
+-- procedure writechr (s : character) is
+-- variable lout : line;
+-- begin
+-- write(lout, s);
+-- writeline(output, lout);
+-- end writechr;
+--
+type out_vector is record
+ A : std_logic_vector(8 downto 1) ;
+ B : std_logic_vector(8 downto 1) ;
+ S : std_logic_vector(4 downto 1) ;
+ Y : std_logic_vector(8 downto 1) ;
+ CLR : std_logic ;
+ CLK : std_logic ;
+ C : std_logic ;
+ V : std_logic ;
+ Z : std_logic ;
+ end record;
+type out_vectors is array (natural range <>) of out_vector;
+constant vectors : out_vectors := (
+("UUUUUUUU", "UUUUUUUU", "UUUU", "UUUUUUUU", '1', '1', 'U', 'U', 'U'),
+("01010101", "00000001", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000010", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "00000000", '1', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0000", "00000000", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01011001", '0', '1', '0', '0', '0'),
+("01010101", "00001000", "0000", "01011001", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0000", "01011101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00100000", "0000", "01100101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0000", "01110101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0000", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0000", "10010101", '0', '1', '0', '0', '0'),
+("01010101", "00000001", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "11010101", '0', '1', '0', '0', '0'),
+("01010101", "00000010", "0010", "01010100", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0010", "01010011", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0010", "01010001", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0010", "01000101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "00000001", "0100", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0100", "11010101", '0', '1', '0', '0', '0'),
+("01010101", "00000010", "0101", "10101010", '0', '1', '0', '0', '0'),
+("01010101", "00000000", "0101", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "00000100", "0100", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "00010000", "0101", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "01000000", "0010", "01010000", '0', '1', '1', '0', '0'),
+("01010101", "00000000", "0010", "01010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "00010101", '0', '1', '0', '0', '0'),
+("01010101", "10000000", "0010", "01010101", '0', '1', '0', '0', '0'));
+
+
+begin
+
+ -- instantiate ALU
+ alu_inst0 : alu
+ port map (
+ A ,
+ B ,
+ S ,
+ Y ,
+ CLR ,
+ CLK ,
+ C ,
+ V ,
+ Z
+ );
+
+ -- apply clock stimulus
+-- clock_stim : process
+-- begin
+-- clock_tb <= '1', '0' after clock_tb_HALF_PERIOD;
+--
+-- if (finished /= '1') then
+-- wait for 2 * clock_tb_HALF_PERIOD;
+-- else
+-- wait; -- end test
+-- end if;
+-- end process clock_stim;
+
+ vector_stim_in : process ( clock_tb )
+ variable i : integer := 0;
+ begin
+ if (clock_tb'event and clock_tb = '1') then
+ if ( i <= vectors'high) then
+ A <= vectors(i).A;
+ B <= vectors(i).B;
+ S <= vectors(i).S;
+ --Y <= vectors(i).Y;
+ CLR <= vectors(i).CLR;
+ CLK <= vectors(i).CLK;
+ --C <= vectors(i).C;
+ --V <= vectors(i).V;
+ --Z <= vectors(i).Z;
+
+ i := i + 1;
+ else
+ finished <= '1';
+ end if;
+ else
+ CLK <= clock_tb;
+ end if;
+
+ end process vector_stim_in;
+end behavioural;
+
ecpu_alu/trunk/alu/vhdl/alu_analog_cadence_tb.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter.vhd
===================================================================
--- ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter.vhd (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter.vhd (revision 2)
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Module - Introduction to VLSI Design [03ELD005]
+-- Lecturer - Dr V. M. Dwyer
+-- Course - MEng Electronic and Electrical Engineering
+-- Year - Part D
+-- Student - Sahrfili Leonous Matturi A028459 [elslm]
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Final coursework 2004
+--
+-- Details: Design and Layout of an ALU
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+-- Description : ALU barrel shifter
+-- Entity : alu_barrel_shifter
+-- Architecture : structural
+-- Created on : 07/03/2004
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+entity alu_barrel_shifter is
+ generic (
+ adder_width : integer := 8
+ );
+ port (
+ x : in std_logic_vector(adder_width - 1 downto 0) ;
+ y : in std_logic_vector(adder_width - 1 downto 0) ;
+ z : out std_logic_vector(adder_width - 1 downto 0) ;
+ c : out std_logic ;
+ direction : in std_logic
+ );
+end alu_barrel_shifter;
+
+
+architecture structural of alu_barrel_shifter is
+
+signal Yor, Yreg, Xreg, Zreg, Zout
+ : std_logic_vector(adder_width downto 0);
+signal Xrev, Zrev : std_logic_vector(adder_width downto 0);
+
+signal Xmsb : std_logic;
+
+
+function reverse(a : in std_logic_vector(Zreg'range)) return std_logic_vector is
+-- reverse_range doesn't appear to work in NC-VHDL!!! but works in VHDL Simili
+--variable a_reversed : std_logic_vector(Zreg'REVERSE_RANGE);
+variable a_reversed : std_logic_vector(0 to adder_width);
+begin
+
+-- for i in a'reverse_range loop
+ for i in 0 to adder_width loop
+ a_reversed(i) := a(i);
+ end loop;
+
+ return a_reversed;
+end reverse;
+begin
+
+
+ ----------------------------------------------------
+ -- shifter
+ ----------------------------------------------------
+ Yreg <= '0' & (y and x"07");
+ Zrev <= reverse(Zreg);
+ Xrev <= reverse('0' & x) when (direction = '0') else
+ reverse(x & '0');
+ Xmsb <= x(x'high);
+ z <= Zout(Zout'high-1 downto 0) when (direction = '0') else
+ Xmsb & Zout(Zout'high-1 downto 1);
+ c <= Zout(Zout'high) when (direction = '0') else
+ Zout(Zout'low);
+ Zout <= Zreg when (direction = '0') else
+ Zrev;
+ Xreg <= '0' & x when (direction = '0') else
+ Xrev;
+
+
+ Yor(0) <= '1' when (Yreg = conv_std_logic_vector(0,adder_width + 1)) else
+ '0';
+ Yor(1) <= '1' when (Yreg = conv_std_logic_vector(1,adder_width + 1)) else
+ '0';
+ Yor(2) <= '1' when (Yreg = conv_std_logic_vector(2,adder_width + 1)) else
+ '0';
+ Yor(3) <= '1' when (Yreg = conv_std_logic_vector(3,adder_width + 1)) else
+ '0';
+ Yor(4) <= '1' when (Yreg = conv_std_logic_vector(4,adder_width + 1)) else
+ '0';
+ Yor(5) <= '1' when (Yreg = conv_std_logic_vector(5,adder_width + 1)) else
+ '0';
+ Yor(6) <= '1' when (Yreg = conv_std_logic_vector(6,adder_width + 1)) else
+ '0';
+ Yor(7) <= '1' when (Yreg = conv_std_logic_vector(7,adder_width + 1)) else
+ '0';
+ Yor(8) <= '0';
+
+
+ shifter : process (Xreg, Yreg, Yor)
+ variable Ztmp : std_logic;
+ begin
+ Zreg <= (others => '0');
+ for i in Zreg'range loop
+ Ztmp := '0';
+ if (i = 0) then
+ Zreg(i) <= Xreg(i) and Yor(0);
+ else
+ Ztmp := Xreg(i) and Yor(0);
+ for j in 1 to i loop
+ Ztmp := (Xreg(i-j) and Yor(j)) or Ztmp;
+ end loop;
+ Zreg(i) <= Ztmp;
+ end if;
+ end loop;
+ end process shifter;
+end structural;
+
+
+
ecpu_alu/trunk/alu/vhdl/alu_barrel_shifter.vhd
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/vhdl/compile.simili.files
===================================================================
--- ecpu_alu/trunk/alu/vhdl/compile.simili.files (nonexistent)
+++ ecpu_alu/trunk/alu/vhdl/compile.simili.files (revision 2)
@@ -0,0 +1,39 @@
+ ./source/boundary_scan/All/txt_util.vhd
+ ./source/boundary_scan/All/bscan_pkg.vhd
+
+ ./source/boundary_scan/All/var_register.vhd
+ ./source/boundary_scan/All/var_register2.vhd
+ ./source/boundary_scan/All/var_register2_negedge.vhd
+ ./source/boundary_scan/All/var_register_sr.vhd
+ ./source/boundary_scan/All/register_1bit_sr.vhd
+ ./source/boundary_scan/All/register_1bit_sr_negedge_triggered.vhd
+ ./source/boundary_scan/All/register_1bit.vhd
+ ./source/boundary_scan/All/register_1bit2.vhd
+ ./source/boundary_scan/All/register_1bit2_negedge.vhd
+ ./source/boundary_scan/All/register_1bit_negedge_triggered.vhd
+ ./source/boundary_scan/All/register_1bit_negedge_triggered2.vhd
+
+ ./source/boundary_scan/All/mux2to1_var.vhd
+ ./source/boundary_scan/All/mux2to1_1bit.vhd
+ ./source/boundary_scan/All/mux4to1_var.vhd
+ ./source/boundary_scan/All/mux4to1_1bit.vhd
+ ./source/boundary_scan/All/mux8to1_var.vhd
+ ./source/boundary_scan/All/mux8to1_1bit.vhd
+
+
+ ../ncvhdl/source/boundary_scan/All/bscan_cell.vhd
+ ../ncvhdl/source/boundary_scan/All/ir_cell.vhd
+
+ ../ncvhdl/source/boundary_scan/All/ir_reg_var.vhd
+ ../ncvhdl/source/boundary_scan/All/ir_reg_4bit.vhd
+ ../ncvhdl/source/boundary_scan/All/ir_reg_8bit.vhd
+
+ ../ncvhdl/source/boundary_scan/All/bscan_controller_fsm.vhd
+ ../ncvhdl/source/boundary_scan/All/bscan_datapath.vhd
+ ../ncvhdl/source/boundary_scan/All/bscan_structure.vhd
+
+# New Files
+# tristate buffer
+ ../ncvhdl/source/boundary_scan/All/tristate_buffer.vhd
+# flipper for bscs
+ ../ncvhdl/source/boundary_scan/All/bidi_component.vhd
ecpu_alu/trunk/alu/vhdl/compile.simili.files
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/ReadLine.pm
===================================================================
--- ecpu_alu/trunk/alu/ReadLine.pm (nonexistent)
+++ ecpu_alu/trunk/alu/ReadLine.pm (revision 2)
@@ -0,0 +1,413 @@
+=head1 NAME
+
+Term::ReadLine - Perl interface to various C packages.
+If no real package is found, substitutes stubs instead of basic functions.
+
+=head1 SYNOPSIS
+
+ use Term::ReadLine;
+ my $term = new Term::ReadLine 'Simple Perl calc';
+ my $prompt = "Enter your arithmetic expression: ";
+ my $OUT = $term->OUT || \*STDOUT;
+ while ( defined ($_ = $term->readline($prompt)) ) {
+ my $res = eval($_);
+ warn $@ if $@;
+ print $OUT $res, "\n" unless $@;
+ $term->addhistory($_) if /\S/;
+ }
+
+=head1 DESCRIPTION
+
+This package is just a front end to some other packages. It's a stub to
+set up a common interface to the various ReadLine implementations found on
+CPAN (under the C namespace).
+
+=head1 Minimal set of supported functions
+
+All the supported functions should be called as methods, i.e., either as
+
+ $term = new Term::ReadLine 'name';
+
+or as
+
+ $term->addhistory('row');
+
+where $term is a return value of Term::ReadLine-Enew().
+
+=over 12
+
+=item C
+
+returns the actual package that executes the commands. Among possible
+values are C, C,
+C.
+
+=item C
+
+returns the handle for subsequent calls to following
+functions. Argument is the name of the application. Optionally can be
+followed by two arguments for C and C filehandles. These
+arguments should be globs.
+
+=item C
+
+gets an input line, I with actual C
+support. Trailing newline is removed. Returns C on C.
+
+=item C
+
+adds the line to the history of input, from where it can be used if
+the actual C is present.
+
+=item C, C
+
+return the filehandles for input and output or C if C
+input and output cannot be used for Perl.
+
+=item C
+
+If argument is specified, it is an advice on minimal size of line to
+be included into history. C means do not include anything into
+history. Returns the old value.
+
+=item C
+
+returns an array with two strings that give most appropriate names for
+files for input and output using conventions C<"E$in">, C<"Eout">.
+
+=item Attribs
+
+returns a reference to a hash which describes internal configuration
+of the package. Names of keys in this hash conform to standard
+conventions with the leading C stripped.
+
+=item C
+
+Returns a reference to a hash with keys being features present in
+current implementation. Several optional features are used in the
+minimal interface: C should be present if the first argument
+to C is recognized, and C should be present if
+C method is not dummy. C should be present if
+lines are put into history automatically (maybe subject to
+C), and C if C method is not dummy.
+
+If C method reports a feature C as present, the
+method C is not dummy.
+
+=back
+
+=head1 Additional supported functions
+
+Actually C can use some other package, that will
+support a richer set of commands.
+
+All these commands are callable via method interface and have names
+which conform to standard conventions with the leading C stripped.
+
+The stub package included with the perl distribution allows some
+additional methods:
+
+=over 12
+
+=item C
+
+makes Tk event loop run when waiting for user input (i.e., during
+C method).
+
+=item C
+
+makes the command line stand out by using termcap data. The argument
+to C should be 0, 1, or a string of a form
+C<"aa,bb,cc,dd">. Four components of this string should be names of
+I, first two will be issued to make the prompt
+standout, last two to make the input line standout.
+
+=item C
+
+takes two arguments which are input filehandle and output filehandle.
+Switches to use these filehandles.
+
+=back
+
+One can check whether the currently loaded ReadLine package supports
+these methods by checking for corresponding C.
+
+=head1 EXPORTS
+
+None
+
+=head1 ENVIRONMENT
+
+The environment variable C governs which ReadLine clone is
+loaded. If the value is false, a dummy interface is used. If the value
+is true, it should be tail of the name of the package to use, such as
+C or C.
+
+As a special case, if the value of this variable is space-separated,
+the tail might be used to disable the ornaments by setting the tail to
+be C or C. The head should be as described above, say
+
+If the variable is not set, or if the head of space-separated list is
+empty, the best available package is loaded.
+
+ export "PERL_RL=Perl o=0" # Use Perl ReadLine without ornaments
+ export "PERL_RL= o=0" # Use best available ReadLine without ornaments
+
+(Note that processing of C for ornaments is in the discretion of the
+particular used C package).
+
+=head1 CAVEATS
+
+It seems that using Term::ReadLine from Emacs minibuffer doesn't work
+quite right and one will get an error message like
+
+ Cannot open /dev/tty for read at ...
+
+One possible workaround for this is to explicitly open /dev/tty like this
+
+ open (FH, "/dev/tty" )
+ or eval 'sub Term::ReadLine::findConsole { ("&STDIN", "&STDERR") }';
+ die $@ if $@;
+ close (FH);
+
+or you can try using the 4-argument form of Term::ReadLine->new().
+
+=cut
+
+use strict;
+
+package Term::ReadLine::Stub;
+our @ISA = qw'Term::ReadLine::Tk Term::ReadLine::TermCap';
+
+$DB::emacs = $DB::emacs; # To peacify -w
+our @rl_term_set;
+*rl_term_set = \@Term::ReadLine::TermCap::rl_term_set;
+
+sub PERL_UNICODE_STDIN () { 0x0001 }
+
+sub ReadLine {'Term::ReadLine::Stub'}
+sub readline {
+ my $self = shift;
+ my ($in,$out,$str) = @$self;
+ my $prompt = shift;
+ print $out $rl_term_set[0], $prompt, $rl_term_set[1], $rl_term_set[2];
+ $self->register_Tk
+ if not $Term::ReadLine::registered and $Term::ReadLine::toloop
+ and defined &Tk::DoOneEvent;
+ #$str = scalar <$in>;
+ $str = $self->get_line;
+ $str =~ s/^\s*\Q$prompt\E// if ($^O eq 'MacOS');
+ utf8::upgrade($str)
+ if (${^UNICODE} & PERL_UNICODE_STDIN || defined ${^ENCODING}) &&
+ utf8::valid($str);
+ print $out $rl_term_set[3];
+ # bug in 5.000: chomping empty string creats length -1:
+ chomp $str if defined $str;
+ $str;
+}
+sub addhistory {}
+
+sub findConsole {
+ my $console;
+ my $consoleOUT;
+
+ if ($^O eq 'MacOS') {
+ $console = "Dev:Console";
+ } elsif (-e "/dev/tty") {
+ $console = "/dev/tty";
+ } elsif (-e "con" or $^O eq 'MSWin32') {
+ $console = 'CONIN$';
+ $consoleOUT = 'CONOUT$';
+ } else {
+ $console = "sys\$command";
+ }
+
+ if (($^O eq 'amigaos') || ($^O eq 'beos') || ($^O eq 'epoc')) {
+ $console = undef;
+ }
+ elsif ($^O eq 'os2') {
+ if ($DB::emacs) {
+ $console = undef;
+ } else {
+ $console = "/dev/con";
+ }
+ }
+
+ $consoleOUT = $console unless defined $consoleOUT;
+ $console = "&STDIN" unless defined $console;
+ if (!defined $consoleOUT) {
+ $consoleOUT = defined fileno(STDERR) && $^O ne 'MSWin32' ? "&STDERR" : "&STDOUT";
+ }
+ ($console,$consoleOUT);
+}
+
+sub new {
+ die "method new called with wrong number of arguments"
+ unless @_==2 or @_==4;
+ #local (*FIN, *FOUT);
+ my ($FIN, $FOUT, $ret);
+ if (@_==2) {
+ my($console, $consoleOUT) = $_[0]->findConsole;
+
+
+ # the Windows CONIN$ needs GENERIC_WRITE mode to allow
+ # a SetConsoleMode() if we end up using Term::ReadKey
+ open FIN, ( $^O eq 'MSWin32' && $console eq 'CONIN$' ) ? "+<$console" :
+ "<$console";
+ open FOUT,">$consoleOUT";
+
+ #OUT->autoflush(1); # Conflicts with debugger?
+ my $sel = select(FOUT);
+ $| = 1; # for DB::OUT
+ select($sel);
+ $ret = bless [\*FIN, \*FOUT];
+ } else { # Filehandles supplied
+ $FIN = $_[2]; $FOUT = $_[3];
+ #OUT->autoflush(1); # Conflicts with debugger?
+ my $sel = select($FOUT);
+ $| = 1; # for DB::OUT
+ select($sel);
+ $ret = bless [$FIN, $FOUT];
+ }
+ if ($ret->Features->{ornaments}
+ and not ($ENV{PERL_RL} and $ENV{PERL_RL} =~ /\bo\w*=0/)) {
+ local $Term::ReadLine::termcap_nowarn = 1;
+ $ret->ornaments(1);
+ }
+ return $ret;
+}
+
+sub newTTY {
+ my ($self, $in, $out) = @_;
+ $self->[0] = $in;
+ $self->[1] = $out;
+ my $sel = select($out);
+ $| = 1; # for DB::OUT
+ select($sel);
+}
+
+sub IN { shift->[0] }
+sub OUT { shift->[1] }
+sub MinLine { undef }
+sub Attribs { {} }
+
+my %features = (tkRunning => 1, ornaments => 1, 'newTTY' => 1);
+sub Features { \%features }
+
+sub get_line {
+ my $self = shift;
+ my $in = $self->IN;
+ local ($/) = "\n";
+ return scalar <$in>;
+}
+
+package Term::ReadLine; # So late to allow the above code be defined?
+
+our $VERSION = '1.03';
+
+my ($which) = exists $ENV{PERL_RL} ? split /\s+/, $ENV{PERL_RL} : undef;
+if ($which) {
+ if ($which =~ /\bgnu\b/i){
+ eval "use Term::ReadLine::Gnu;";
+ } elsif ($which =~ /\bperl\b/i) {
+ eval "use Term::ReadLine::Perl;";
+ } else {
+ eval "use Term::ReadLine::$which;";
+ }
+} elsif (defined $which and $which ne '') { # Defined but false
+ # Do nothing fancy
+} else {
+ eval "use Term::ReadLine::Gnu; 1" or eval "use Term::ReadLine::Perl; 1";
+}
+
+#require FileHandle;
+
+# To make possible switch off RL in debugger: (Not needed, work done
+# in debugger).
+our @ISA;
+if (defined &Term::ReadLine::Gnu::readline) {
+ @ISA = qw(Term::ReadLine::Gnu Term::ReadLine::Stub);
+} elsif (defined &Term::ReadLine::Perl::readline) {
+ @ISA = qw(Term::ReadLine::Perl Term::ReadLine::Stub);
+} elsif (defined $which && defined &{"Term::ReadLine::$which\::readline"}) {
+ @ISA = "Term::ReadLine::$which";
+} else {
+ @ISA = qw(Term::ReadLine::Stub);
+}
+
+package Term::ReadLine::TermCap;
+
+# Prompt-start, prompt-end, command-line-start, command-line-end
+# -- zero-width beautifies to emit around prompt and the command line.
+our @rl_term_set = ("","","","");
+# string encoded:
+our $rl_term_set = ',,,';
+
+our $terminal;
+sub LoadTermCap {
+ return if defined $terminal;
+
+ require Term::Cap;
+ $terminal = Tgetent Term::Cap ({OSPEED => 9600}); # Avoid warning.
+}
+
+sub ornaments {
+ shift;
+ return $rl_term_set unless @_;
+ $rl_term_set = shift;
+ $rl_term_set ||= ',,,';
+ $rl_term_set = 'us,ue,md,me' if $rl_term_set eq '1';
+ my @ts = split /,/, $rl_term_set, 4;
+ eval { LoadTermCap };
+ unless (defined $terminal) {
+ warn("Cannot find termcap: $@\n") unless $Term::ReadLine::termcap_nowarn;
+ $rl_term_set = ',,,';
+ return;
+ }
+ @rl_term_set = map {$_ ? $terminal->Tputs($_,1) || '' : ''} @ts;
+ return $rl_term_set;
+}
+
+
+package Term::ReadLine::Tk;
+
+our($count_handle, $count_DoOne, $count_loop);
+$count_handle = $count_DoOne = $count_loop = 0;
+
+our($giveup);
+sub handle {$giveup = 1; $count_handle++}
+
+sub Tk_loop {
+ # Tk->tkwait('variable',\$giveup); # needs Widget
+ $count_DoOne++, Tk::DoOneEvent(0) until $giveup;
+ $count_loop++;
+ $giveup = 0;
+}
+
+sub register_Tk {
+ my $self = shift;
+ $Term::ReadLine::registered++
+ or Tk->fileevent($self->IN,'readable',\&handle);
+}
+
+sub tkRunning {
+ $Term::ReadLine::toloop = $_[1] if @_ > 1;
+ $Term::ReadLine::toloop;
+}
+
+sub get_c {
+ my $self = shift;
+ $self->Tk_loop if $Term::ReadLine::toloop && defined &Tk::DoOneEvent;
+ return getc $self->IN;
+}
+
+sub get_line {
+ my $self = shift;
+ $self->Tk_loop if $Term::ReadLine::toloop && defined &Tk::DoOneEvent;
+ my $in = $self->IN;
+ local ($/) = "\n";
+ return scalar <$in>;
+}
+
+1;
+
ecpu_alu/trunk/alu/ReadLine.pm
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu_test.txt
===================================================================
--- ecpu_alu/trunk/alu/alu_test.txt (nonexistent)
+++ ecpu_alu/trunk/alu/alu_test.txt (revision 2)
@@ -0,0 +1,34 @@
+dsdfsdssSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
+00010000 00000001 asl 1
+00000000 00000000 asl 1
+00000000 00000010 asl 1
+00000000 00000000 asl 1
+00000001 00000100 asl 0
+00000000 00000000 asl 0
+00000010 00001000 asl 0
+00000000 00000000 asl 0
+00100100 00010000 asl 0
+00000000 00000000 asl 0
+01001000 00100000 asl 0
+00000000 00000000 asl 0
+10000000 01000000 asl 0
+00000000 00000000 asl 0
+00000000 10000000 asl 0
+00010000 00000001 asl 0
+00000000 00000000 asl 0
+00000000 00000010 asl 0
+00000000 00000000 asl 0
+00000001 00000100 asl 0
+00100100 00010000 asl 0
+10000000 01000000 asl 0
+00000000 00000000 asl 0
+00000000 10000000 decb 0
+00010000 00000001 clr 0
+00000000 00000000 add 0
+10000000 10000000 inca 0
+10110100 11101101 inca 0
+10100110 11100000 cmp 0
+10011010 10010011 add 0
+01111111 01111111 asl 0
+11111111 11111111 asl 0
+00000000 10000000 asl 0
ecpu_alu/trunk/alu/alu_test.txt
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu_controller.vh
===================================================================
--- ecpu_alu/trunk/alu/alu_controller.vh (nonexistent)
+++ ecpu_alu/trunk/alu/alu_controller.vh (revision 2)
@@ -0,0 +1,39 @@
+// alu controller defines
+// `define addAB 00
+// `define subAB 01
+// `define incA 02
+// `define incB 03
+// `define decA 04
+// `define decB 05
+// `define cmpAB 06
+// `define andAB 07
+// `define orAB 08
+// `define xorAB 09
+// `define cplB 10
+// `define cplA 11
+// `define slAB 12
+// `define srAB 13
+// `define clrALL 14
+
+
+`define clrZ 0
+
+`define clrV 1
+`define clrC 2
+
+`define cADD_AB 0
+`define cINC_A 1
+`define cINC_B 9
+`define cSUB_AB 2
+`define cCMP_AB 3
+`define cASL_AbyB 4
+`define cASR_AbyB 5
+`define cCLR 6
+`define cDEC_A 7
+`define cDEC_B 8
+`define cMUL_AB 10
+`define cCPL_A 11
+`define cAND_AB 12
+`define cOR_AB 13
+`define cXOR_AB 14
+`define cCPL_B 15
ecpu_alu/trunk/alu/alu_controller.vh
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu_barrel_shifter.v
===================================================================
--- ecpu_alu/trunk/alu/alu_barrel_shifter.v (nonexistent)
+++ ecpu_alu/trunk/alu/alu_barrel_shifter.v (revision 2)
@@ -0,0 +1,161 @@
+// port from univeristy project for an ALU in VHDL
+//
+module alu_barrel_shifter (
+ x ,
+ y ,
+ z ,
+ c ,
+ direction
+ );
+
+ parameter SHIFTER_WIDTH = 8;
+
+ input [SHIFTER_WIDTH - 1 : 0] x ;
+ input [SHIFTER_WIDTH - 1 : 0] y ;
+ output [SHIFTER_WIDTH - 1 : 0] z ;
+ output c ;
+ input direction ;
+
+
+ wire [SHIFTER_WIDTH : 0] Yor ;
+ wire [SHIFTER_WIDTH : 0] Yreg ;
+ wire [SHIFTER_WIDTH : 0] Xreg ;
+ reg [SHIFTER_WIDTH : 0] Zreg ;
+ wire [SHIFTER_WIDTH : 0] Zout ;
+
+ wire [SHIFTER_WIDTH : 0] Xrev ;
+ wire [SHIFTER_WIDTH : 0] Zrev ;
+
+ reg [SHIFTER_WIDTH-1 : 0] Zrev_copy ; // for missing bits
+
+ wire Xmsb ;
+
+ reg Ztmp, update_extra_bits;
+ integer j, k, m;
+
+ //initial update_extra_bits = 1'b0;
+
+ function [SHIFTER_WIDTH : 0] reverse;
+ input [SHIFTER_WIDTH : 0] a ;
+ reg [0 : SHIFTER_WIDTH] a_reversed;
+ reg [31:0] i ;
+ begin
+ for (i=0;i<= SHIFTER_WIDTH;i = i + 1)
+ a_reversed[i] = a[i];
+ reverse = a_reversed;
+ end
+ endfunction
+
+
+ wire [SHIFTER_WIDTH : 0] value_7 ;
+
+ assign value_7 = 'h7;
+ ////////////////////////////////////////////////////
+ // shifter
+ ////////////////////////////////////////////////////
+
+ /// theoretical solution for missing bits START ///
+ //assign Zrev_copy = {Xreg[SHIFTER_WIDTH-1:SHIFTER_WIDTH-m] ;
+ /// theoretical solution for missing bits END ///
+
+ assign Yreg = {1'b0, y & value_7} ;
+ assign Zrev = reverse(Zreg) ;
+ assign Xrev = (!direction) ? reverse({1'b0, x}) : reverse({x, 1'b0});
+// assign Xmsb = x[SHIFTER_WIDTH-1] ;
+ assign Xmsb = (y[2:0]==0) ? x[SHIFTER_WIDTH-1] : 1'b0 ;
+ //assign z = (!direction) ? Zout[SHIFTER_WIDTH-1:0] : {Xmsb, Zout[SHIFTER_WIDTH-1:1]} ;
+
+ assign z = (!direction) ? Zout[SHIFTER_WIDTH-1:0] : {Xmsb, Zout[SHIFTER_WIDTH-1:1]} | ((y[2:0]==0) ? 'd0 : Zrev_copy);
+
+ assign c = (!direction) ? Zout[SHIFTER_WIDTH] : Zout[0] ;
+
+ assign Zout = (!direction) ? Zreg : Zrev ;
+
+ assign Xreg = (!direction) ? {1'b0, x} : Xrev ;
+
+
+ assign Yor[0]= (Yreg == 'd0) ? 1'b1 : 1'b0;
+ assign Yor[1]= (Yreg == 'd1) ? 1'b1 : 1'b0;
+ assign Yor[2]= (Yreg == 'd2) ? 1'b1 : 1'b0;
+ assign Yor[3]= (Yreg == 'd3) ? 1'b1 : 1'b0;
+ assign Yor[4]= (Yreg == 'd4) ? 1'b1 : 1'b0;
+ assign Yor[5]= (Yreg == 'd5) ? 1'b1 : 1'b0;
+ assign Yor[6]= (Yreg == 'd6) ? 1'b1 : 1'b0;
+ assign Yor[7]= (Yreg == 'd7) ? 1'b1 : 1'b0;
+ assign Yor[8]= 1'b0;
+
+
+ // shifter : process (Xreg, Yreg, Yor)
+ // temporary variables but declare as regs
+ // for synthesis reasons.
+ // They extra unneeded bits should be optimized away
+ //
+ initial j = 'd0;
+ initial k = 'd0;
+
+ initial update_extra_bits = 1'b0;
+
+ always @(x or y or direction)
+ begin
+ update_extra_bits = 1'b0;
+ end
+
+ always @(Xreg or Yreg or Yor)
+ begin
+ //#1;
+ Zreg = 'h0;
+ `ifdef DEBUG_BARREL_SHIFTER
+ $display("**** BARREL SHIFTER always block stage 1 ****");
+ `endif
+ for (j=SHIFTER_WIDTH; j>=0 ; j=j-1)
+ begin
+ Ztmp = 1'b0;
+ if (j == 0)
+ begin
+ Zreg[j] = Xreg[j] & Yor[0];
+ `ifdef DEBUG_BARREL_SHIFTER
+ $display("**** BARREL SHIFTER always block stage 2 ****");
+ $display("%d %d", j, k);
+ `endif
+ end
+ else
+ begin
+ `ifdef DEBUG_BARREL_SHIFTER
+ $display("**** BARREL SHIFTER always block stage 3 ****");
+ $display("%d %d", j, k);
+ `endif
+ Ztmp = Xreg[j] & Yor[0];
+ for (k=1 ; k<=j ; k=k+1)
+ begin
+ Ztmp = (Xreg[j-k] & Yor[k]) | Ztmp;
+
+ if (Yor[k] && direction)
+ begin
+ Zrev_copy = 'd0 ;
+ for(m=0; m
ecpu_alu/trunk/alu/alu_barrel_shifter.v
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/runit
===================================================================
--- ecpu_alu/trunk/alu/runit (nonexistent)
+++ ecpu_alu/trunk/alu/runit (revision 2)
@@ -0,0 +1,18 @@
+#!/bin/sh -f
+
+if [ ! -n "$1" ]; then
+ EXTRA_OPTS=""
+else
+ EXTRA_OPTS="$*"
+fi
+
+if [ ! -n "$BARREL_SHIFTER" ]; then
+ BARREL_SHIFTER="../barrel_shifter/simple/barrel_shifter_simple.v"
+fi
+
+
+echo Using iverilog options $EXTRA_OPTS
+cmd="iverilog ${EXTRA_OPTS} alu_adder.v $BARREL_SHIFTER alu_datapath.v alu_controller.v alu.v alu_tb.v -o run_alu"
+echo $cmd
+$cmd
+./run_alu
ecpu_alu/trunk/alu/runit
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/run_alu
===================================================================
--- ecpu_alu/trunk/alu/run_alu (nonexistent)
+++ ecpu_alu/trunk/alu/run_alu (revision 2)
@@ -0,0 +1,1612 @@
+#! /usr/bin/vvp
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x1c4b0c0 .scope module, "alu_tb" "alu_tb" 2 37;
+ .timescale -9 -12;
+P_0x1ca6bc8 .param/l "DWIDTH" 2 40, +C4<01000>;
+P_0x1ca6bf0 .param/l "OPWIDTH" 2 41, +C4<0100>;
+v0x1cd2510_0 .var "A", 7 0;
+v0x1cd25b0_0 .var "A_u", 7 0;
+v0x1cd2650_0 .var "B", 7 0;
+v0x1cd26d0_0 .var "B_u", 7 0;
+v0x1cd2750_0 .net "C", 0 0, v0x1c982f0_0; 1 drivers
+v0x1cd27d0_0 .var "CLK", 0 0;
+v0x1cd2850_0 .var "CLR", 0 0;
+v0x1cd28d0_0 .var "S", 3 0;
+v0x1cd2950_0 .net "V", 0 0, v0x1c97fd0_0; 1 drivers
+v0x1cd29d0_0 .net/s "Y", 7 0, v0x1cba400_0; 1 drivers
+v0x1cd2a50_0 .var "Y_u", 7 0;
+v0x1cd2ad0_0 .net "Z", 0 0, v0x1c910c0_0; 1 drivers
+v0x1cd2b50_0 .var "aa", 7 0;
+v0x1cd2bf0_0 .var "bb", 7 0;
+v0x1cd2cf0_0 .var "check_here", 0 0;
+v0x1cd2d90_0 .var "clrc", 0 0;
+v0x1cd2c70_0 .var/i "count", 31 0;
+v0x1cd2ea0_0 .var/i "errors_found", 31 0;
+v0x1cd2e10_0 .var "finished", 0 0;
+v0x1cd2fc0_0 .var/i "infile", 31 0;
+v0x1cd2f20_0 .var "last_CLR", 0 0;
+v0x1cd30f0_0 .var "last_ss", 31 0;
+v0x1cd3040_0 .var "op1", 7 0;
+v0x1cd3230_0 .var "op2", 7 0;
+v0x1cd3170 .array "opcode_list", 15 0, 32 1;
+v0x1cd35f0_0 .var/i "outfile", 31 0;
+v0x1cd32b0_0 .var/i "random_count", 31 0;
+v0x1cd3750_0 .var "random_mode", 0 0;
+v0x1cd3670_0 .var/i "random_number", 31 0;
+v0x1cd38c0_0 .var/s "result", 7 0;
+v0x1cd37d0_0 .var "result_u", 7 0;
+v0x1cd3a40_0 .var "ss", 31 0;
+v0x1cd3940_0 .var "started", 0 0;
+v0x1cd39c0_0 .var/i "success", 31 0;
+E_0x1c9be10 .event posedge, v0x1c498d0_0;
+E_0x1cbfcd0 .event negedge, v0x1c498d0_0;
+E_0x1cc0e10/0 .event edge, v0x1cd2e10_0;
+E_0x1cc0e10/1 .event posedge, v0x1c498d0_0;
+E_0x1cc0e10 .event/or E_0x1cc0e10/0, E_0x1cc0e10/1;
+E_0x1c8ebf0 .event edge, v0x1c498d0_0;
+S_0x1cd2070 .scope function, "bas" "bas" 2 451, 2 451, S_0x1c4b0c0;
+ .timescale -9 -12;
+v0x1cd2150_0 .var "a1", 7 0;
+v0x1cd2210_0 .var "bas", 7 0;
+v0x1cd22b0_0 .var "direction", 0 0;
+v0x1cd2350_0 .var "shift_size", 7 0;
+v0x1cd23d0_0 .var "tmp", 7 0;
+v0x1cd2470_0 .var/i "tmp2", 31 0;
+TD_alu_tb.bas ;
+ %load/v 8, v0x1cd2150_0, 8;
+ %set/v v0x1cd23d0_0, 8, 8;
+ %load/v 8, v0x1cd2350_0, 3; Only need 3 of 8 bits
+; Save base=8 wid=3 in lookaside.
+ %mov 11, 8, 3;
+ %mov 14, 0, 29;
+ %set/v v0x1cd2470_0, 11, 32;
+T_0.0 ;
+ %load/v 8, v0x1cd2470_0, 32;
+ %cmp/s 0, 8, 32;
+ %jmp/0xz T_0.1, 5;
+ %load/v 8, v0x1cd22b0_0, 1;
+ %jmp/0xz T_0.2, 8;
+ %ix/load 1, 1;
+ %mov 4, 0, 1;
+ %load/x1p 16, v0x1cd23d0_0, 7;
+; Save base=16 wid=7 in lookaside.
+ %mov 8, 16, 7;
+ %load/v 16, v0x1cd23d0_0, 1; Only need 1 of 8 bits
+; Save base=16 wid=1 in lookaside.
+ %mov 15, 16, 1;
+ %set/v v0x1cd23d0_0, 8, 8;
+ %jmp T_0.3;
+T_0.2 ;
+ %ix/load 1, 7;
+ %mov 4, 0, 1;
+ %load/x1p 16, v0x1cd23d0_0, 1;
+; Save base=16 wid=1 in lookaside.
+ %mov 8, 16, 1;
+ %load/v 16, v0x1cd23d0_0, 7; Only need 7 of 8 bits
+; Save base=16 wid=7 in lookaside.
+ %mov 9, 16, 7;
+ %set/v v0x1cd23d0_0, 8, 8;
+T_0.3 ;
+ %load/v 8, v0x1cd2470_0, 32;
+ %mov 40, 8, 32;
+ %mov 72, 39, 1;
+ %subi 40, 1, 33;
+ %set/v v0x1cd2470_0, 40, 32;
+ %jmp T_0.0;
+T_0.1 ;
+ %load/v 8, v0x1cd23d0_0, 8;
+ %set/v v0x1cd2210_0, 8, 8;
+ %end;
+S_0x1cd1df0 .scope function, "get_random_opcode" "get_random_opcode" 2 442, 2 442, S_0x1c4b0c0;
+ .timescale -9 -12;
+v0x1cd1ed0_0 .var "get_random_opcode", 32 1;
+v0x1cd1f50_0 .var/s "myseed", 31 0;
+v0x1cd1fd0_0 .var/i "tmp", 31 0;
+TD_alu_tb.get_random_opcode ;
+ %vpi_func 2 446 "$random", 8, 32, v0x1cd1f50_0;
+ %set/v v0x1cd1fd0_0, 8, 32;
+ %load/v 40, v0x1cd1fd0_0, 32;
+ %movi 72, 11, 32;
+ %mod 40, 72, 32;
+ %ix/get 3, 40, 32;
+ %load/av 8, v0x1cd3170, 32;
+ %set/v v0x1cd1ed0_0, 8, 32;
+ %end;
+S_0x1cd1b90 .scope function, "string2opcode" "string2opcode" 2 413, 2 413, S_0x1c4b0c0;
+ .timescale -9 -12;
+v0x1cd1c70_0 .var "opcode", 3 0;
+v0x1cd1cf0_0 .var "s", 31 0;
+v0x1cd1d70_0 .var "string2opcode", 3 0;
+TD_alu_tb.string2opcode ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 0;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.4, 8;
+ %set/v v0x1cd1c70_0, 0, 4;
+ %jmp T_2.5;
+T_2.4 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 1;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.6, 8;
+ %movi 8, 1, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.7;
+T_2.6 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 9;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.8, 8;
+ %movi 8, 9, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.9;
+T_2.8 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 2;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.10, 8;
+ %movi 8, 2, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.11;
+T_2.10 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 3;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.12, 8;
+ %movi 8, 3, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.13;
+T_2.12 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 4;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.14, 8;
+ %movi 8, 4, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.15;
+T_2.14 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 5;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.16, 8;
+ %movi 8, 5, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.17;
+T_2.16 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 6;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.18, 8;
+ %movi 8, 6, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.19;
+T_2.18 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 7;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.20, 8;
+ %movi 8, 7, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.21;
+T_2.20 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 8;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.22, 8;
+ %movi 8, 8, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.23;
+T_2.22 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 10;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.24, 8;
+ %movi 8, 10, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.25;
+T_2.24 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 11;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.26, 8;
+ %movi 8, 11, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.27;
+T_2.26 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 12;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.28, 8;
+ %movi 8, 12, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.29;
+T_2.28 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 13;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.30, 8;
+ %movi 8, 13, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.31;
+T_2.30 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 14;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.32, 8;
+ %movi 8, 14, 4;
+ %set/v v0x1cd1c70_0, 8, 4;
+ %jmp T_2.33;
+T_2.32 ;
+ %load/v 8, v0x1cd1cf0_0, 32;
+ %ix/load 3, 15;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_2.34, 8;
+ %set/v v0x1cd1c70_0, 1, 4;
+T_2.34 ;
+T_2.33 ;
+T_2.31 ;
+T_2.29 ;
+T_2.27 ;
+T_2.25 ;
+T_2.23 ;
+T_2.21 ;
+T_2.19 ;
+T_2.17 ;
+T_2.15 ;
+T_2.13 ;
+T_2.11 ;
+T_2.9 ;
+T_2.7 ;
+T_2.5 ;
+ %load/v 8, v0x1cd1c70_0, 4;
+ %set/v v0x1cd1d70_0, 8, 4;
+ %end;
+S_0x1cd18b0 .scope module, "this_record" "test_vector" 2 120, 2 26, S_0x1c4b0c0;
+ .timescale -9 -12;
+P_0x1c66968 .param/l "DWIDTH" 2 27, +C4<01000>;
+P_0x1c66990 .param/l "OPWIDTH" 2 28, +C4<0100>;
+v0x1cd1990_0 .var/s "A", 7 0;
+v0x1cd1a10_0 .var/s "B", 7 0;
+v0x1cd1a90_0 .var "S", 31 0;
+v0x1cd1b10_0 .var "Y", 7 0;
+S_0x1cd15d0 .scope module, "next_record" "test_vector" 2 121, 2 26, S_0x1c4b0c0;
+ .timescale -9 -12;
+P_0x1cc59e8 .param/l "DWIDTH" 2 27, +C4<01000>;
+P_0x1cc5a10 .param/l "OPWIDTH" 2 28, +C4<0100>;
+v0x1cd16b0_0 .var/s "A", 7 0;
+v0x1cd1730_0 .var/s "B", 7 0;
+v0x1cd17b0_0 .var "S", 31 0;
+v0x1cd1830_0 .var "Y", 7 0;
+S_0x1cb23e0 .scope module, "alu_inst0" "alu" 2 124, 3 3, S_0x1c4b0c0;
+ .timescale -9 -12;
+P_0x1cc6488 .param/l "DWIDTH" 3 5, +C4<01000>;
+P_0x1cc64b0 .param/l "OPWIDTH" 3 6, +C4<0100>;
+L_0x1c46f90 .functor BUFZ 1, v0x1cd2850_0, C4<0>, C4<0>, C4<0>;
+v0x1cd0240_0 .net "A", 7 0, v0x1cd2510_0; 1 drivers
+v0x1cd02f0_0 .net "B", 7 0, v0x1cd2650_0; 1 drivers
+v0x1cd03a0_0 .alias "C", 0 0, v0x1cd2750_0;
+v0x1cd0450_0 .net "CLK", 0 0, v0x1cd27d0_0; 1 drivers
+v0x1cd0500_0 .net "CLR", 0 0, v0x1cd2850_0; 1 drivers
+v0x1cd0580_0 .net "S", 3 0, v0x1cd28d0_0; 1 drivers
+v0x1cd0600_0 .alias "V", 0 0, v0x1cd2950_0;
+v0x1cd06b0_0 .alias "Y", 7 0, v0x1cd29d0_0;
+v0x1cd0760_0 .alias "Z", 0 0, v0x1cd2ad0_0;
+v0x1cd0810_0 .net "add_AB", 0 0, L_0x1cd3be0; 1 drivers
+v0x1cd0890_0 .net "and_AB", 0 0, L_0x1cd4570; 1 drivers
+v0x1cd0910_0 .net "clr_ALL", 0 0, L_0x1cd4150; 1 drivers
+v0x1cd0990_0 .net "clr_C", 0 0, C4; 0 drivers
+v0x1cd0a10_0 .net "clr_V", 0 0, C4; 0 drivers
+v0x1cd0b10_0 .net "clr_Z", 0 0, C4; 0 drivers
+v0x1cd0b90_0 .net "cmp_AB", 0 0, L_0x1cd3e60; 1 drivers
+v0x1cd0a90_0 .net "cpl_A", 0 0, L_0x1cd4330; 1 drivers
+v0x1cd0ca0_0 .net "cpl_B", 0 0, L_0x1cd4610; 1 drivers
+v0x1cd0c10_0 .net "dec_A", 0 0, L_0x1cd4290; 1 drivers
+v0x1cd0dc0_0 .net "dec_B", 0 0, L_0x1cd41f0; 1 drivers
+v0x1cd0d20_0 .net "inc_A", 0 0, L_0x1cd3c80; 1 drivers
+v0x1cd0ef0_0 .net "inc_B", 0 0, L_0x1cd3d20; 1 drivers
+v0x1cd0e40_0 .net "load_inputs", 0 0, v0x1ccfa40_0; 1 drivers
+v0x1cd1030_0 .net "load_outputs", 0 0, v0x1ccfaf0_0; 1 drivers
+v0x1cd0f70_0 .net "mul_AB", 0 0, L_0x1cd43f0; 1 drivers
+v0x1cd1180_0 .net "or_AB", 0 0, L_0x1cd4490; 1 drivers
+v0x1cd10b0_0 .net "reset", 0 0, L_0x1c46f90; 1 drivers
+v0x1cd12e0_0 .net "sl_AB", 0 0, L_0x1cd3f00; 1 drivers
+v0x1cd1200_0 .net "sr_AB", 0 0, L_0x1cd4020; 1 drivers
+v0x1cd1450_0 .net "sub_AB", 0 0, L_0x1cd3dc0; 1 drivers
+v0x1cd1360_0 .net "xor_AB", 0 0, L_0x1cd4710; 1 drivers
+S_0x1ccebf0 .scope module, "controller" "alu_controller" 3 47, 4 4, S_0x1cb23e0;
+ .timescale -9 -12;
+P_0x1c98278 .param/l "OPBITS" 4 36, C4<00000000000000000000000000010000>;
+P_0x1c982a0 .param/l "OPWIDTH" 4 35, +C4<0100>;
+v0x1ccecd0_0 .alias "add_AB", 0 0, v0x1cd0810_0;
+v0x1cced50_0 .alias "and_AB", 0 0, v0x1cd0890_0;
+v0x1ccee00_0 .alias "clk", 0 0, v0x1cd0450_0;
+v0x1ccf350_0 .alias "clr", 0 0, v0x1cd0910_0;
+v0x1ccf430_0 .alias "clr_C", 0 0, v0x1cd0990_0;
+v0x1ccf4e0_0 .alias "clr_V", 0 0, v0x1cd0a10_0;
+v0x1ccf560_0 .alias "clr_Z", 0 0, v0x1cd0b10_0;
+v0x1ccf610_0 .alias "cmp_AB", 0 0, v0x1cd0b90_0;
+v0x1ccf690_0 .alias "cpl_A", 0 0, v0x1cd0a90_0;
+v0x1ccf710_0 .alias "cpl_B", 0 0, v0x1cd0ca0_0;
+v0x1ccf790_0 .alias "dec_A", 0 0, v0x1cd0c10_0;
+v0x1ccf810_0 .alias "dec_B", 0 0, v0x1cd0dc0_0;
+v0x1ccf890_0 .alias "inc_A", 0 0, v0x1cd0d20_0;
+v0x1ccf940_0 .alias "inc_B", 0 0, v0x1cd0ef0_0;
+v0x1ccfa40_0 .var "load_inputs", 0 0;
+v0x1ccfaf0_0 .var "load_outputs", 0 0;
+v0x1ccf9c0_0 .alias "mul_AB", 0 0, v0x1cd0f70_0;
+v0x1ccfc00_0 .var "next_opcode", 3 0;
+v0x1ccfb70_0 .alias "opcode", 3 0, v0x1cd0580_0;
+v0x1ccfd20_0 .var "opcode_sel", 65537 0;
+v0x1ccfc80_0 .alias "or_AB", 0 0, v0x1cd1180_0;
+v0x1ccfe50_0 .alias "reset", 0 0, v0x1cd10b0_0;
+v0x1ccfda0_0 .alias "sl_AB", 0 0, v0x1cd12e0_0;
+v0x1ccff90_0 .alias "sr_AB", 0 0, v0x1cd1200_0;
+v0x1ccfed0_0 .alias "sub_AB", 0 0, v0x1cd1450_0;
+v0x1cd00e0_0 .var "this_opcode", 3 0;
+v0x1cd0010_0 .alias "xor_AB", 0 0, v0x1cd1360_0;
+E_0x1cbabb0 .event edge, v0x1cd00e0_0;
+L_0x1cd3be0 .part v0x1ccfd20_0, 0, 1;
+L_0x1cd3c80 .part v0x1ccfd20_0, 1, 1;
+L_0x1cd3d20 .part v0x1ccfd20_0, 9, 1;
+L_0x1cd3dc0 .part v0x1ccfd20_0, 2, 1;
+L_0x1cd3e60 .part v0x1ccfd20_0, 3, 1;
+L_0x1cd3f00 .part v0x1ccfd20_0, 4, 1;
+L_0x1cd4020 .part v0x1ccfd20_0, 5, 1;
+L_0x1cd4150 .part v0x1ccfd20_0, 6, 1;
+L_0x1cd4290 .part v0x1ccfd20_0, 7, 1;
+L_0x1cd41f0 .part v0x1ccfd20_0, 8, 1;
+L_0x1cd43f0 .part v0x1ccfd20_0, 10, 1;
+L_0x1cd4330 .part v0x1ccfd20_0, 11, 1;
+L_0x1cd4570 .part v0x1ccfd20_0, 12, 1;
+L_0x1cd4490 .part v0x1ccfd20_0, 13, 1;
+L_0x1cd4710 .part v0x1ccfd20_0, 14, 1;
+L_0x1cd4610 .part v0x1ccfd20_0, 15, 1;
+S_0x1cb1680 .scope module, "datapath" "alu_datapath" 3 79, 5 2, S_0x1cb23e0;
+ .timescale -9 -12;
+P_0x1ca6908 .param/l "ALU_WIDTH" 5 40, +C4<01000>;
+L_0x1c461b0 .functor NOT 8, v0x1cab770_0, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0x1cd4e70 .functor AND 1, L_0x1cd4c70, L_0x1cd4d70, C4<1>, C4<1>;
+L_0x1cd4b70 .functor AND 1, L_0x1cd4e70, L_0x1cd4ed0, C4<1>, C4<1>;
+L_0x1c66860 .functor AND 1, L_0x1cd4b70, L_0x1cd4f70, C4<1>, C4<1>;
+L_0x1cd13e0 .functor AND 1, L_0x1cd3dc0, L_0x1cd5110, C4<1>, C4<1>;
+L_0x1cd4d10 .functor OR 1, L_0x1cd13e0, L_0x1cd4610, C4<0>, C4<0>;
+L_0x1c6c8f0 .functor NOT 8, v0x1cac0c0_0, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0x1cce580 .functor AND 1, L_0x1cd51b0, L_0x1cd3c80, C4<1>, C4<1>;
+L_0x1cd4e10 .functor AND 1, L_0x1cce580, L_0x1cd5350, C4<1>, C4<1>;
+L_0x1c59620 .functor OR 1, L_0x1cd3dc0, L_0x1cd3c80, C4<0>, C4<0>;
+L_0x1c4a7b0 .functor OR 1, L_0x1c59620, L_0x1cd3d20, C4<0>, C4<0>;
+L_0x1c40a60 .functor OR 1, L_0x1cd4570, L_0x1cd4490, C4<0>, C4<0>;
+L_0x1cd5c60 .functor AND 1, L_0x1cd59c0, L_0x1cd5b60, C4<1>, C4<1>;
+L_0x1cd5cc0 .functor AND 1, L_0x1c40a60, L_0x1cd5c60, C4<1>, C4<1>;
+L_0x1cd55c0 .functor OR 1, L_0x1cd3f00, L_0x1cd4020, C4<0>, C4<0>;
+L_0x1cd5c00 .functor OR 1, L_0x1cd4710, L_0x1cd3e60, C4<0>, C4<0>;
+L_0x1cd6290 .functor AND 1, L_0x1cd3be0, L_0x1cd6050, C4<1>, C4<1>;
+L_0x1cd3850 .functor AND 1, L_0x1cd6290, L_0x1cd6350, C4<1>, C4<1>;
+L_0x1cd4a70 .functor AND 1, L_0x1cd3850, L_0x1cd61d0, C4<1>, C4<1>;
+L_0x1cd53f0 .functor AND 1, L_0x1cd4a70, L_0x1cd65c0, C4<1>, C4<1>;
+L_0x1cd6850 .functor AND 1, L_0x1cd53f0, L_0x1cd60f0, C4<1>, C4<1>;
+L_0x1cd6700 .functor OR 1, L_0x1cd4570, L_0x1cd4490, C4<0>, C4<0>;
+L_0x1c6c810 .functor OR 1, L_0x1cd6700, L_0x1cd4710, C4<0>, C4<0>;
+L_0x1cd6550 .functor OR 1, L_0x1c6c810, L_0x1cd4610, C4<0>, C4<0>;
+L_0x1cd6660 .functor OR 1, L_0x1cd6550, L_0x1cd4150, C4<0>, C4<0>;
+L_0x1cd67f0 .functor OR 1, L_0x1cd3f00, L_0x1cd4020, C4<0>, C4<0>;
+L_0x1cd69f0 .functor BUFZ 8, v0x1cab770_0, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0x1cd64e0 .functor BUFZ 8, v0x1cac0c0_0, C4<00000000>, C4<00000000>, C4<00000000>;
+v0x1cabab0_0 .alias "A", 7 0, v0x1cd0240_0;
+v0x1cab770_0 .var "Areg", 7 0;
+v0x1cab7f0_0 .alias "B", 7 0, v0x1cd02f0_0;
+v0x1cac0c0_0 .var "Breg", 7 0;
+v0x1cac140_0 .alias "C", 0 0, v0x1cd2750_0;
+v0x1c982f0_0 .var "Creg", 0 0;
+v0x1c98370_0 .alias "V", 0 0, v0x1cd2950_0;
+v0x1c97fd0_0 .var "Vreg", 0 0;
+v0x1c98050_0 .alias "Y", 7 0, v0x1cd29d0_0;
+v0x1cba400_0 .var "Yreg", 7 0;
+v0x1cba480_0 .alias "Z", 0 0, v0x1cd2ad0_0;
+v0x1c910c0_0 .var "Zreg", 0 0;
+v0x1c91140_0 .net *"_s102", 0 0, C4<1>; 1 drivers
+v0x1c8f210_0 .net *"_s104", 0 0, C4<0>; 1 drivers
+v0x1ca6ca0_0 .net *"_s108", 0 0, L_0x1cd5c00; 1 drivers
+v0x1ca6d20_0 .net *"_s110", 0 0, C4<0>; 1 drivers
+v0x1c9fda0_0 .net *"_s112", 0 0, C4<1>; 1 drivers
+v0x1c9fe20_0 .net *"_s116", 0 0, L_0x1cd6050; 1 drivers
+v0x1c8f290_0 .net *"_s118", 0 0, L_0x1cd6290; 1 drivers
+v0x1c91880_0 .net *"_s12", 7 0, C4<00000000>; 1 drivers
+v0x1ca4430_0 .net *"_s120", 0 0, L_0x1cd6350; 1 drivers
+v0x1c917e0_0 .net *"_s122", 0 0, L_0x1cd3850; 1 drivers
+v0x1ca4120_0 .net *"_s124", 0 0, L_0x1cd61d0; 1 drivers
+v0x1ca4380_0 .net *"_s126", 0 0, L_0x1cd4a70; 1 drivers
+v0x1ca4060_0 .net *"_s128", 0 0, L_0x1cd65c0; 1 drivers
+v0x1ca3a20_0 .net *"_s130", 0 0, L_0x1cd53f0; 1 drivers
+v0x1ca3aa0_0 .net *"_s132", 0 0, L_0x1cd60f0; 1 drivers
+v0x1ca64a0_0 .net *"_s134", 0 0, L_0x1cd6850; 1 drivers
+v0x1ca6520_0 .net *"_s137", 0 0, L_0x1cd68b0; 1 drivers
+v0x1ca6140_0 .net *"_s138", 0 0, L_0x1cd6700; 1 drivers
+v0x1ca61c0_0 .net *"_s14", 7 0, L_0x1c461b0; 1 drivers
+v0x1ca3d40_0 .net *"_s140", 0 0, L_0x1c6c810; 1 drivers
+v0x1ca5a80_0 .net *"_s142", 0 0, L_0x1cd6550; 1 drivers
+v0x1ca5b00_0 .net *"_s144", 0 0, L_0x1cd6660; 1 drivers
+v0x1ca5de0_0 .net *"_s146", 0 0, C4<0>; 1 drivers
+v0x1ca5e60_0 .net *"_s148", 0 0, L_0x1cd67f0; 1 drivers
+v0x1ca53c0_0 .net *"_s150", 0 0, L_0x1cd6b90; 1 drivers
+v0x1ca5440_0 .net *"_s152", 0 0, L_0x1cd6e00; 1 drivers
+v0x1ca5060_0 .net *"_s156", 0 0, C4<1>; 1 drivers
+v0x1ca50e0_0 .net *"_s158", 0 0, C4<0>; 1 drivers
+v0x1ca4d00_0 .net *"_s16", 7 0, C4<00000000>; 1 drivers
+v0x1ca4da0_0 .net *"_s18", 7 0, C4<11111111>; 1 drivers
+v0x1ca49c0_0 .net *"_s20", 7 0, L_0x1cd48d0; 1 drivers
+v0x1ca4a60_0 .net *"_s22", 7 0, L_0x1cd49d0; 1 drivers
+v0x1ca46a0_0 .net *"_s24", 7 0, L_0x1cd4ad0; 1 drivers
+v0x1ca4740_0 .net *"_s28", 0 0, L_0x1cd4c70; 1 drivers
+v0x1c668c0_0 .net *"_s30", 0 0, L_0x1cd4d70; 1 drivers
+v0x1ca3700_0 .net *"_s32", 0 0, L_0x1cd4e70; 1 drivers
+v0x1ca3780_0 .net *"_s34", 0 0, L_0x1cd4ed0; 1 drivers
+v0x1c409e0_0 .net *"_s36", 0 0, L_0x1cd4b70; 1 drivers
+v0x1c45d10_0 .net *"_s38", 0 0, L_0x1cd4f70; 1 drivers
+v0x1cb9a80_0 .net *"_s40", 0 0, L_0x1c66860; 1 drivers
+v0x1cb9b00_0 .net *"_s42", 7 0, C4<11111111>; 1 drivers
+v0x1c587a0_0 .net *"_s44", 7 0, L_0x1cd5010; 1 drivers
+v0x1c49990_0 .net *"_s46", 0 0, L_0x1cd5110; 1 drivers
+v0x1cba740_0 .net *"_s48", 0 0, L_0x1cd13e0; 1 drivers
+v0x1c6c730_0 .net *"_s50", 0 0, L_0x1cd4d10; 1 drivers
+v0x1cba7c0_0 .net *"_s52", 7 0, L_0x1c6c8f0; 1 drivers
+v0x1c6b8b0_0 .net *"_s54", 0 0, L_0x1cd51b0; 1 drivers
+v0x1cba200_0 .net *"_s56", 0 0, L_0x1cce580; 1 drivers
+v0x1ccbc60_0 .net *"_s58", 0 0, L_0x1cd5350; 1 drivers
+v0x1cba280_0 .net *"_s60", 0 0, L_0x1cd4e10; 1 drivers
+v0x1cb9fa0_0 .net *"_s62", 7 0, C4<00000000>; 1 drivers
+v0x1cba040_0 .net *"_s64", 7 0, C4<00000000>; 1 drivers
+v0x1ca3dc0_0 .net *"_s66", 7 0, L_0x1cd5480; 1 drivers
+v0x1cb9d40_0 .net *"_s68", 7 0, L_0x1cd5520; 1 drivers
+v0x1cb9dc0_0 .net *"_s70", 7 0, L_0x1cd5640; 1 drivers
+v0x1ca5720_0 .net *"_s74", 0 0, L_0x1c59620; 1 drivers
+v0x1ca57a0_0 .net *"_s76", 0 0, L_0x1c4a7b0; 1 drivers
+v0x1c91640_0 .net *"_s78", 0 0, C4<1>; 1 drivers
+v0x1c916c0_0 .net *"_s80", 0 0, C4<0>; 1 drivers
+v0x1cb97f0_0 .net *"_s84", 0 0, L_0x1c40a60; 1 drivers
+v0x1cb9870_0 .net *"_s86", 0 0, L_0x1cd59c0; 1 drivers
+v0x1c97e40_0 .net *"_s88", 0 0, L_0x1cd5b60; 1 drivers
+v0x1c97ec0_0 .net *"_s90", 0 0, L_0x1cd5c60; 1 drivers
+v0x1c91940_0 .net *"_s92", 0 0, L_0x1cd5cc0; 1 drivers
+v0x1c919c0_0 .net *"_s95", 7 0, L_0x1cd5dc0; 1 drivers
+v0x1c66740_0 .net *"_s96", 0 0, L_0x1cd55c0; 1 drivers
+v0x1c667c0_0 .net *"_s98", 7 0, L_0x1cd5f10; 1 drivers
+v0x1c40850_0 .alias "add_AB", 0 0, v0x1cd0810_0;
+v0x1c408d0_0 .net "adderORsel", 0 0, L_0x1cd5e60; 1 drivers
+v0x1c40950_0 .net "adderXORsel", 0 0, L_0x1cd5d20; 1 drivers
+v0x1c45b70_0 .net "adder_in_a", 7 0, L_0x1cd4bd0; 1 drivers
+v0x1c45bf0_0 .net "adder_in_b", 7 0, L_0x1cd56e0; 1 drivers
+v0x1c45c70_0 .net "adder_out", 7 0, v0x1cabce0_0; 1 drivers
+v0x1c585f0_0 .net "alu_out", 7 0, L_0x1cd5fb0; 1 drivers
+v0x1c58670_0 .alias "and_AB", 0 0, v0x1cd0890_0;
+v0x1c586f0_0 .net "carry", 0 0, L_0x1cd6950; 1 drivers
+v0x1c497d0_0 .net "carry_in", 0 0, L_0x1cd5250; 1 drivers
+v0x1c49850_0 .net "carry_out", 8 0, v0x1cb3f30_0; 1 drivers
+v0x1c498d0_0 .alias "clk", 0 0, v0x1cd0450_0;
+v0x1c6c560_0 .alias "clr", 0 0, v0x1cd0910_0;
+v0x1c6c5e0_0 .alias "clr_C", 0 0, v0x1cd0990_0;
+v0x1c6c660_0 .alias "clr_V", 0 0, v0x1cd0a10_0;
+v0x1c6b6d0_0 .alias "clr_Z", 0 0, v0x1cd0b10_0;
+v0x1c6b750_0 .alias "cmp_AB", 0 0, v0x1cd0b90_0;
+v0x1c6b7d0_0 .alias "cpl_A", 0 0, v0x1cd0a90_0;
+v0x1ccba70_0 .alias "cpl_B", 0 0, v0x1cd0ca0_0;
+v0x1ccbaf0_0 .alias "dec_A", 0 0, v0x1cd0c10_0;
+v0x1ccbb90_0 .alias "dec_B", 0 0, v0x1cd0dc0_0;
+v0x1cce5f0_0 .alias "inc_A", 0 0, v0x1cd0d20_0;
+v0x1cce690_0 .alias "inc_B", 0 0, v0x1cd0ef0_0;
+v0x1cce2c0_0 .alias "load_inputs", 0 0, v0x1cd0e40_0;
+v0x1cce360_0 .alias "load_outputs", 0 0, v0x1cd1030_0;
+v0x1cce3e0_0 .net "logic0", 7 0, C4<00000000>; 1 drivers
+v0x1cce480_0 .net "logic1", 7 0, C4<00000001>; 1 drivers
+v0x1cce500_0 .alias "mul_AB", 0 0, v0x1cd0f70_0;
+v0x1ccea70_0 .alias "or_AB", 0 0, v0x1cd1180_0;
+v0x1cce710_0 .alias "reset", 0 0, v0x1cd10b0_0;
+v0x1cce7b0_0 .net "shifter_carry", 0 0, v0x1cc6520_0; 1 drivers
+v0x1cce830_0 .net "shifter_direction", 0 0, L_0x1cd6fb0; 1 drivers
+v0x1cce8b0_0 .net "shifter_inA", 7 0, L_0x1cd69f0; 1 drivers
+v0x1cce930_0 .net "shifter_inB", 7 0, L_0x1cd64e0; 1 drivers
+v0x1cce9b0_0 .net "shifter_out", 7 0, v0x1c59b70_0; 1 drivers
+v0x1ccee90_0 .alias "sl_AB", 0 0, v0x1cd12e0_0;
+v0x1ccef10_0 .alias "sr_AB", 0 0, v0x1cd1200_0;
+v0x1cceaf0_0 .alias "sub_AB", 0 0, v0x1cd1450_0;
+v0x1cceb70_0 .alias "xor_AB", 0 0, v0x1cd1360_0;
+E_0x1c8ed20/0 .event edge, v0x1cce710_0;
+E_0x1c8ed20/1 .event posedge, v0x1c498d0_0;
+E_0x1c8ed20 .event/or E_0x1c8ed20/0, E_0x1c8ed20/1;
+L_0x1cd48d0 .functor MUXZ 8, v0x1cab770_0, C4<11111111>, L_0x1cd41f0, C4<>;
+L_0x1cd49d0 .functor MUXZ 8, L_0x1cd48d0, C4<00000000>, L_0x1cd3d20, C4<>;
+L_0x1cd4ad0 .functor MUXZ 8, L_0x1cd49d0, L_0x1c461b0, L_0x1cd4330, C4<>;
+L_0x1cd4bd0 .functor MUXZ 8, L_0x1cd4ad0, C4<00000000>, L_0x1cd4610, C4<>;
+L_0x1cd4c70 .reduce/nor L_0x1cd3dc0;
+L_0x1cd4d70 .reduce/nor L_0x1cd3c80;
+L_0x1cd4ed0 .reduce/nor L_0x1cd4330;
+L_0x1cd4f70 .reduce/nor L_0x1cd4610;
+L_0x1cd5010 .functor MUXZ 8, v0x1cac0c0_0, C4<11111111>, L_0x1cd4290, C4<>;
+L_0x1cd5110 .reduce/nor L_0x1cd3c80;
+L_0x1cd51b0 .reduce/nor L_0x1cd3dc0;
+L_0x1cd5350 .reduce/nor L_0x1cd4610;
+L_0x1cd5480 .functor MUXZ 8, L_0x1cd56e0, C4<00000000>, L_0x1cd4330, C4<>;
+L_0x1cd5520 .functor MUXZ 8, L_0x1cd5480, C4<00000000>, L_0x1cd4e10, C4<>;
+L_0x1cd5640 .functor MUXZ 8, L_0x1cd5520, L_0x1c6c8f0, L_0x1cd4d10, C4<>;
+L_0x1cd56e0 .functor MUXZ 8, L_0x1cd5640, L_0x1cd5010, L_0x1c66860, C4<>;
+L_0x1cd5250 .functor MUXZ 1, C4<0>, C4<1>, L_0x1c4a7b0, C4<>;
+L_0x1cd59c0 .reduce/nor L_0x1cd3f00;
+L_0x1cd5b60 .reduce/nor L_0x1cd4020;
+L_0x1cd5dc0 .part v0x1cb3f30_0, 1, 8;
+L_0x1cd5f10 .functor MUXZ 8, v0x1cabce0_0, v0x1c59b70_0, L_0x1cd55c0, C4<>;
+L_0x1cd5fb0 .functor MUXZ 8, L_0x1cd5f10, L_0x1cd5dc0, L_0x1cd5cc0, C4<>;
+L_0x1cd5e60 .functor MUXZ 1, C4<0>, C4<1>, L_0x1cd4490, C4<>;
+L_0x1cd5d20 .functor MUXZ 1, C4<1>, C4<0>, L_0x1cd5c00, C4<>;
+L_0x1cd6050 .reduce/nor L_0x1cd4570;
+L_0x1cd6350 .reduce/nor L_0x1cd4490;
+L_0x1cd61d0 .reduce/nor L_0x1cd4710;
+L_0x1cd65c0 .reduce/nor L_0x1cd4610;
+L_0x1cd60f0 .reduce/nor L_0x1cd4150;
+L_0x1cd68b0 .part v0x1cb3f30_0, 8, 1;
+L_0x1cd6b90 .functor MUXZ 1, L_0x1cd6950, v0x1cc6520_0, L_0x1cd67f0, C4<>;
+L_0x1cd6e00 .functor MUXZ 1, L_0x1cd6b90, C4<0>, L_0x1cd6660, C4<>;
+L_0x1cd6950 .functor MUXZ 1, L_0x1cd6e00, L_0x1cd68b0, L_0x1cd6850, C4<>;
+L_0x1cd6fb0 .functor MUXZ 1, C4<0>, C4<1>, L_0x1cd4020, C4<>;
+S_0x1cb8c00 .scope module, "adder" "alu_adder" 5 163, 6 3, S_0x1cb1680;
+ .timescale 0 0;
+P_0x1cb8d38 .param/l "ADDER_WIDTH" 6 17, +C4<01000>;
+L_0x1cd5a60 .functor BUFZ 8, L_0x1cd7170, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0x1cd6d00 .functor BUFZ 8, L_0x1cd71d0, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0x1cd6d60 .functor BUFZ 8, L_0x1cd7230, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0x1cd7170 .functor XOR 8, L_0x1cd4bd0, L_0x1cd56e0, C4<00000000>, C4<00000000>;
+L_0x1cd7230 .functor AND 8, L_0x1cd4bd0, L_0x1cd56e0, C4<11111111>, C4<11111111>;
+L_0x1cd71d0 .functor OR 8, L_0x1cd4bd0, L_0x1cd56e0, C4<00000000>, C4<00000000>;
+v0x1cbaab0_0 .alias "ORsel", 0 0, v0x1c408d0_0;
+v0x1cb46b0_0 .alias "XORsel", 0 0, v0x1c40950_0;
+v0x1cb5220_0 .net "XandY", 7 0, L_0x1cd7230; 1 drivers
+v0x1cb9440_0 .net "XorY", 7 0, L_0x1cd71d0; 1 drivers
+v0x1ca6800_0 .net "XxorY", 7 0, L_0x1cd7170; 1 drivers
+v0x1ca3310_0 .net "and_result", 7 0, L_0x1cd6d60; 1 drivers
+v0x1cb3eb0_0 .alias "carry_in", 0 0, v0x1c497d0_0;
+v0x1cb3f30_0 .var "carry_out", 8 0;
+v0x1ca3410_0 .var "i", 31 0;
+v0x1ca3490_0 .net "or_result", 7 0, L_0x1cd6d00; 1 drivers
+v0x1cabe90_0 .alias "x", 7 0, v0x1c45b70_0;
+v0x1cabf10_0 .net "xor_result", 7 0, L_0x1cd5a60; 1 drivers
+v0x1cabc60_0 .alias "y", 7 0, v0x1c45bf0_0;
+v0x1cabce0_0 .var "z", 7 0;
+E_0x1cc3090/0 .event edge, v0x1cbaab0_0, v0x1cb46b0_0, v0x1cb9440_0, v0x1cb5220_0;
+E_0x1cc3090/1 .event edge, v0x1ca6800_0, v0x1cb3f30_0, v0x1cabc60_0, v0x1cabe90_0;
+E_0x1cc3090 .event/or E_0x1cc3090/0, E_0x1cc3090/1;
+S_0x1cad4e0 .scope module, "shifter" "alu_barrel_shifter" 5 173, 7 2, S_0x1cb1680;
+ .timescale -9 -12;
+P_0x1cb17b8 .param/l "DWIDTH" 7 9, +C4<01000>;
+v0x1cc6520_0 .var "c", 0 0;
+v0x1cc6360_0 .alias "direction", 0 0, v0x1cce830_0;
+v0x1cc60c0_0 .alias "x", 7 0, v0x1cce8b0_0;
+v0x1c67060_0 .alias "y", 7 0, v0x1cce930_0;
+v0x1c41350_0 .var "y_tmp", 7 0;
+v0x1c59b70_0 .var "z", 7 0;
+E_0x1cc6cf0 .event edge, v0x1cc6360_0, v0x1c67060_0, v0x1cc60c0_0;
+ .scope S_0x1ccebf0;
+T_3 ;
+ %wait E_0x1c8ed20;
+ %load/v 8, v0x1ccfe50_0, 1;
+ %jmp/0xz T_3.0, 8;
+ %movi 8, 6, 4;
+ %ix/load 0, 4;
+ %assign/v0 v0x1cd00e0_0, 0, 8;
+ %jmp T_3.1;
+T_3.0 ;
+ %load/v 8, v0x1ccfb70_0, 4;
+ %ix/load 0, 4;
+ %assign/v0 v0x1cd00e0_0, 0, 8;
+T_3.1 ;
+ %jmp T_3;
+ .thread T_3;
+ .scope S_0x1ccebf0;
+T_4 ;
+ %wait E_0x1cbabb0;
+ %ix/load 0, 65538;
+ %assign/v0 v0x1ccfd20_0, 0, 0;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 0;
+ %load/v 8, v0x1cd00e0_0, 4;
+ %cmpi/u 8, 6, 4;
+ %jmp/1 T_4.0, 6;
+ %cmpi/u 8, 0, 4;
+ %jmp/1 T_4.1, 6;
+ %cmpi/u 8, 1, 4;
+ %jmp/1 T_4.2, 6;
+ %cmpi/u 8, 9, 4;
+ %jmp/1 T_4.3, 6;
+ %cmpi/u 8, 7, 4;
+ %jmp/1 T_4.4, 6;
+ %cmpi/u 8, 8, 4;
+ %jmp/1 T_4.5, 6;
+ %cmpi/u 8, 2, 4;
+ %jmp/1 T_4.6, 6;
+ %cmpi/u 8, 3, 4;
+ %jmp/1 T_4.7, 6;
+ %cmpi/u 8, 12, 4;
+ %jmp/1 T_4.8, 6;
+ %cmpi/u 8, 13, 4;
+ %jmp/1 T_4.9, 6;
+ %cmpi/u 8, 14, 4;
+ %jmp/1 T_4.10, 6;
+ %cmpi/u 8, 10, 4;
+ %jmp/1 T_4.11, 6;
+ %cmpi/u 8, 11, 4;
+ %jmp/1 T_4.12, 6;
+ %cmpi/u 8, 15, 4;
+ %jmp/1 T_4.13, 6;
+ %cmpi/u 8, 4, 4;
+ %jmp/1 T_4.14, 6;
+ %cmpi/u 8, 5, 4;
+ %jmp/1 T_4.15, 6;
+ %load/v 8, v0x1cd00e0_0, 4;
+ %ix/load 0, 4;
+ %assign/v0 v0x1ccfc00_0, 0, 8;
+ %jmp T_4.17;
+T_4.0 ;
+ %ix/load 0, 1;
+ %ix/load 1, 6;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %jmp T_4.17;
+T_4.1 ;
+ %ix/load 0, 1;
+ %ix/load 1, 0;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.2 ;
+ %ix/load 0, 1;
+ %ix/load 1, 1;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.3 ;
+ %ix/load 0, 1;
+ %ix/load 1, 9;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.4 ;
+ %ix/load 0, 1;
+ %ix/load 1, 7;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.5 ;
+ %ix/load 0, 1;
+ %ix/load 1, 8;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.6 ;
+ %ix/load 0, 1;
+ %ix/load 1, 2;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.7 ;
+ %ix/load 0, 1;
+ %ix/load 1, 3;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %jmp T_4.17;
+T_4.8 ;
+ %ix/load 0, 1;
+ %ix/load 1, 12;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.9 ;
+ %ix/load 0, 1;
+ %ix/load 1, 13;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.10 ;
+ %ix/load 0, 1;
+ %ix/load 1, 14;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.11 ;
+ %ix/load 0, 1;
+ %ix/load 1, 10;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.12 ;
+ %ix/load 0, 1;
+ %ix/load 1, 11;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.13 ;
+ %ix/load 0, 1;
+ %ix/load 1, 15;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.14 ;
+ %ix/load 0, 1;
+ %ix/load 1, 4;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.15 ;
+ %ix/load 0, 1;
+ %ix/load 1, 5;
+ %assign/v0/x1 v0x1ccfd20_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfa40_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1ccfaf0_0, 0, 1;
+ %jmp T_4.17;
+T_4.17 ;
+ %jmp T_4;
+ .thread T_4, $push;
+ .scope S_0x1cb8c00;
+T_5 ;
+ %wait E_0x1cc3090;
+ %load/v 8, v0x1cb3eb0_0, 1;
+ %ix/load 0, 1;
+ %ix/load 1, 0;
+ %assign/v0/x1 v0x1cb3f30_0, 0, 8;
+ %set/v v0x1ca3410_0, 0, 32;
+T_5.0 ;
+ %load/v 8, v0x1ca3410_0, 32;
+ %cmpi/u 8, 8, 32;
+ %jmp/0xz T_5.1, 5;
+ %ix/getv 1, v0x1ca3410_0;
+ %load/x1p 8, v0x1ca6800_0, 1;
+; Save base=8 wid=1 in lookaside.
+ %ix/getv 1, v0x1ca3410_0;
+ %load/x1p 9, v0x1cb3f30_0, 1;
+; Save base=9 wid=1 in lookaside.
+ %load/v 10, v0x1cb46b0_0, 1;
+ %and 9, 10, 1;
+ %xor 8, 9, 1;
+ %ix/getv 1, v0x1ca3410_0;
+ %jmp/1 t_0, 4;
+ %ix/load 0, 1;
+ %assign/v0/x1 v0x1cabce0_0, 0, 8;
+t_0 ;
+ %ix/getv 1, v0x1ca3410_0;
+ %load/x1p 8, v0x1cb5220_0, 1;
+; Save base=8 wid=1 in lookaside.
+ %ix/getv 1, v0x1ca3410_0;
+ %load/x1p 9, v0x1cb3f30_0, 1;
+; Save base=9 wid=1 in lookaside.
+ %load/v 10, v0x1cbaab0_0, 1;
+ %or 9, 10, 1;
+ %ix/getv 1, v0x1ca3410_0;
+ %load/x1p 10, v0x1cb9440_0, 1;
+; Save base=10 wid=1 in lookaside.
+ %and 9, 10, 1;
+ %or 8, 9, 1;
+ %ix/load 0, 1;
+ %load/vp0 9, v0x1ca3410_0, 32;
+ %ix/get 1, 9, 32;
+ %jmp/1 t_1, 4;
+ %ix/load 0, 1;
+ %assign/v0/x1 v0x1cb3f30_0, 0, 8;
+t_1 ;
+ %ix/load 0, 1;
+ %load/vp0 8, v0x1ca3410_0, 32;
+ %set/v v0x1ca3410_0, 8, 32;
+ %jmp T_5.0;
+T_5.1 ;
+ %jmp T_5;
+ .thread T_5, $push;
+ .scope S_0x1cad4e0;
+T_6 ;
+ %set/v v0x1cc6520_0, 0, 1;
+ %set/v v0x1c41350_0, 0, 8;
+ %end;
+ .thread T_6;
+ .scope S_0x1cad4e0;
+T_7 ;
+ %wait E_0x1cc6cf0;
+ %load/v 8, v0x1cc60c0_0, 8;
+ %set/v v0x1c59b70_0, 8, 8;
+ %set/v v0x1cc6520_0, 0, 1;
+ %load/v 16, v0x1c67060_0, 3; Only need 3 of 8 bits
+; Save base=16 wid=3 in lookaside.
+ %mov 8, 16, 3;
+ %mov 11, 0, 5;
+ %set/v v0x1c41350_0, 8, 8;
+T_7.0 ;
+ %load/v 8, v0x1c41350_0, 8;
+ %cmp/u 0, 8, 8;
+ %jmp/0xz T_7.1, 5;
+ %load/v 8, v0x1cc6360_0, 1;
+ %jmp/0xz T_7.2, 8;
+ %ix/load 1, 1;
+ %mov 4, 0, 1;
+ %load/x1p 16, v0x1c59b70_0, 7;
+; Save base=16 wid=7 in lookaside.
+ %mov 8, 16, 7;
+ %load/v 16, v0x1c59b70_0, 1; Only need 1 of 8 bits
+; Save base=16 wid=1 in lookaside.
+ %mov 15, 16, 1;
+ %set/v v0x1c59b70_0, 8, 8;
+ %load/v 8, v0x1c59b70_0, 1; Only need 1 of 8 bits
+; Save base=8 wid=1 in lookaside.
+ %set/v v0x1cc6520_0, 8, 1;
+ %jmp T_7.3;
+T_7.2 ;
+ %ix/load 1, 7;
+ %mov 4, 0, 1;
+ %load/x1p 16, v0x1c59b70_0, 1;
+; Save base=16 wid=1 in lookaside.
+ %mov 8, 16, 1;
+ %load/v 16, v0x1c59b70_0, 7; Only need 7 of 8 bits
+; Save base=16 wid=7 in lookaside.
+ %mov 9, 16, 7;
+ %set/v v0x1c59b70_0, 8, 8;
+ %ix/load 1, 6;
+ %mov 4, 0, 1;
+ %load/x1p 8, v0x1c59b70_0, 1;
+; Save base=8 wid=1 in lookaside.
+ %set/v v0x1cc6520_0, 8, 1;
+T_7.3 ;
+ %load/v 8, v0x1c41350_0, 8;
+ %mov 16, 8, 8;
+ %mov 24, 0, 24;
+ %subi 16, 1, 32;
+ %set/v v0x1c41350_0, 16, 8;
+ %jmp T_7.0;
+T_7.1 ;
+ %jmp T_7;
+ .thread T_7, $push;
+ .scope S_0x1cb1680;
+T_8 ;
+ %wait E_0x1c8ed20;
+ %load/v 8, v0x1cce710_0, 1;
+ %jmp/0xz T_8.0, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cab770_0, 0, 0;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cac0c0_0, 0, 0;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cba400_0, 0, 0;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c910c0_0, 0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c982f0_0, 0, 0;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c97fd0_0, 0, 0;
+ %jmp T_8.1;
+T_8.0 ;
+ %load/v 8, v0x1cce2c0_0, 1;
+ %jmp/0xz T_8.2, 8;
+ %load/v 8, v0x1cabab0_0, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cab770_0, 0, 8;
+ %load/v 8, v0x1cab7f0_0, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cac0c0_0, 0, 8;
+T_8.2 ;
+ %load/v 8, v0x1cce360_0, 1;
+ %jmp/0xz T_8.4, 8;
+ %load/v 8, v0x1c585f0_0, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cba400_0, 0, 8;
+T_8.4 ;
+ %load/v 8, v0x1c6c560_0, 1;
+ %jmp/0xz T_8.6, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cab770_0, 0, 0;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cac0c0_0, 0, 0;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cba400_0, 0, 0;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c982f0_0, 0, 0;
+T_8.6 ;
+ %load/v 8, v0x1c6b6d0_0, 1;
+ %jmp/0xz T_8.8, 8;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c910c0_0, 0, 0;
+T_8.8 ;
+ %load/v 8, v0x1c6c5e0_0, 1;
+ %jmp/0xz T_8.10, 8;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c982f0_0, 0, 0;
+T_8.10 ;
+ %load/v 8, v0x1c6c660_0, 1;
+ %jmp/0xz T_8.12, 8;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c97fd0_0, 0, 0;
+T_8.12 ;
+ %load/v 8, v0x1c585f0_0, 8;
+ %cmpi/u 8, 0, 8;
+ %jmp/0xz T_8.14, 4;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c910c0_0, 0, 1;
+ %jmp T_8.15;
+T_8.14 ;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c910c0_0, 0, 0;
+T_8.15 ;
+ %load/v 8, v0x1c586f0_0, 1;
+ %ix/load 0, 1;
+ %assign/v0 v0x1c982f0_0, 0, 8;
+T_8.1 ;
+ %jmp T_8;
+ .thread T_8;
+ .scope S_0x1c4b0c0;
+T_9 ;
+ %movi 8, 6382692, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 0;
+ %set/av v0x1cd3170, 8, 32;
+ %movi 8, 1768842081, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 1;
+ %set/av v0x1cd3170, 8, 32;
+ %movi 40, 1768842082, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 9;
+ %set/av v0x1cd3170, 40, 32;
+ %movi 72, 7566690, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 2;
+ %set/av v0x1cd3170, 72, 32;
+ %movi 72, 6516080, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 3;
+ %set/av v0x1cd3170, 72, 32;
+ %movi 72, 6386540, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 4;
+ %set/av v0x1cd3170, 72, 32;
+ %movi 72, 6386546, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 5;
+ %set/av v0x1cd3170, 72, 32;
+ %movi 72, 6515826, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 6;
+ %set/av v0x1cd3170, 72, 32;
+ %movi 72, 1684366177, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 7;
+ %set/av v0x1cd3170, 72, 32;
+ %movi 104, 1684366178, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 8;
+ %set/av v0x1cd3170, 104, 32;
+ %movi 136, 7173484, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 10;
+ %set/av v0x1cd3170, 136, 32;
+ %movi 136, 1668312161, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 11;
+ %set/av v0x1cd3170, 136, 32;
+ %movi 168, 6385252, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 12;
+ %set/av v0x1cd3170, 168, 32;
+ %movi 168, 28530, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 13;
+ %set/av v0x1cd3170, 168, 32;
+ %movi 168, 7892850, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 14;
+ %set/av v0x1cd3170, 168, 32;
+ %movi 168, 1668312162, 32;
+ %ix/load 1, 0;
+ %ix/load 3, 15;
+ %set/av v0x1cd3170, 168, 32;
+ %end;
+ .thread T_9;
+ .scope S_0x1c4b0c0;
+T_10 ;
+ %movi 8, 1000000, 32;
+ %set/v v0x1cd32b0_0, 8, 32;
+ %set/v v0x1cd3750_0, 1, 1;
+ %vpi_call 2 112 "$display", "Generating %0d random inputs", v0x1cd32b0_0;
+ %end;
+ .thread T_10;
+ .scope S_0x1c4b0c0;
+T_11 ;
+ %set/v v0x1cd27d0_0, 0, 1;
+T_11.0 ;
+ %delay 10000000, 0;
+ %load/v 8, v0x1cd27d0_0, 1;
+ %inv 8, 1;
+ %set/v v0x1cd27d0_0, 8, 1;
+ %jmp T_11.0;
+ %end;
+ .thread T_11;
+ .scope S_0x1c4b0c0;
+T_12 ;
+ %wait E_0x1c8ebf0;
+ %jmp T_12;
+ .thread T_12, $push;
+ .scope S_0x1c4b0c0;
+T_13 ;
+ %set/v v0x1cd2ea0_0, 0, 32;
+ %end;
+ .thread T_13;
+ .scope S_0x1c4b0c0;
+T_14 ;
+ %wait E_0x1cc0e10;
+ %load/v 8, v0x1cd2e10_0, 1;
+ %jmp/0xz T_14.0, 8;
+ %load/v 8, v0x1cd2ea0_0, 32;
+ %cmp/s 0, 8, 32;
+ %jmp/0xz T_14.2, 5;
+ %vpi_call 2 159 "$display", "Test FAILED with %d ERRORs [%0t] ", v0x1cd2ea0_0, $time;
+ %jmp T_14.3;
+T_14.2 ;
+ %vpi_call 2 161 "$display", "Test PASSED ";
+T_14.3 ;
+ %vpi_call 2 164 "$fclose", v0x1cd2fc0_0;
+ %vpi_call 2 165 "$fclose", v0x1cd35f0_0;
+ %vpi_call 2 166 "$finish";
+T_14.0 ;
+ %jmp T_14;
+ .thread T_14;
+ .scope S_0x1c4b0c0;
+T_15 ;
+ %delay 1000, 0;
+ %vpi_func 2 177 "$fopen", 8, 32, "alu_test.txt", "r";
+ %set/v v0x1cd2fc0_0, 8, 32;
+ %set/v v0x1cd2e10_0, 0, 1;
+ %set/v v0x1cd2c70_0, 0, 32;
+ %set/v v0x1cd2850_0, 1, 1;
+ %set/v v0x1cd3940_0, 0, 1;
+T_15.0 ;
+ %vpi_func 2 188 "$feof", 8, 32, v0x1cd2fc0_0;
+ %nor/r 8, 8, 32;
+ %load/v 9, v0x1cd3750_0, 1;
+ %inv 9, 1;
+ %and 8, 9, 1;
+ %load/v 9, v0x1cd3750_0, 1;
+ %load/v 10, v0x1cd32b0_0, 32;
+ %cmp/s 0, 10, 32;
+ %mov 10, 5, 1;
+ %and 9, 10, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_15.1, 8;
+ %load/v 8, v0x1cd2c70_0, 32;
+ %mov 40, 8, 32;
+ %mov 72, 39, 1;
+ %addi 40, 1, 33;
+ %set/v v0x1cd2c70_0, 40, 32;
+ %load/v 8, v0x1cd3750_0, 1;
+ %jmp/0xz T_15.2, 8;
+ %vpi_func 2 201 "$random", 8, 32;
+ %set/v v0x1cd3670_0, 8, 32;
+ %load/v 8, v0x1cd3670_0, 32;
+ %set/v v0x1cd2b50_0, 8, 8;
+ %vpi_func 2 208 "$random", 8, 32;
+ %set/v v0x1cd3670_0, 8, 32;
+ %load/v 8, v0x1cd3670_0, 32;
+ %set/v v0x1cd2bf0_0, 8, 8;
+ %vpi_func 2 215 "$random", 8, 32;
+ %set/v v0x1cd3670_0, 8, 32;
+ %movi 8, 1684366178, 32;
+ %set/v v0x1cd3a40_0, 8, 32;
+ %vpi_func 2 222 "$random", 40, 32;
+ %set/v v0x1cd3670_0, 40, 32;
+ %set/v v0x1cd2d90_0, 0, 1;
+ %load/v 40, v0x1cd32b0_0, 32;
+ %mov 72, 40, 32;
+ %mov 104, 71, 1;
+ %subi 72, 1, 33;
+ %set/v v0x1cd32b0_0, 72, 32;
+ %jmp T_15.3;
+T_15.2 ;
+ %vpi_func 2 233 "$fscanf", 8, 32, v0x1cd2fc0_0, "%b %b %s %b", v0x1cd2b50_0, v0x1cd2bf0_0, v0x1cd3a40_0, v0x1cd2d90_0;
+ %set/v v0x1cd39c0_0, 8, 32;
+T_15.4 ;
+ %load/v 8, v0x1cd39c0_0, 32;
+ %cmpi/u 8, 0, 32;
+ %mov 8, 4, 1;
+ %vpi_func 2 234 "$feof", 9, 32, v0x1cd2fc0_0;
+ %nor/r 9, 9, 32;
+ %and 8, 9, 1;
+ %jmp/0xz T_15.5, 8;
+ %vpi_func 2 236 "$fgetc", 8, 32, v0x1cd2fc0_0;
+ %set/v v0x1cd39c0_0, 8, 32;
+ %vpi_func 2 237 "$fscanf", 8, 32, v0x1cd2fc0_0, "%b %b %s %b", v0x1cd2b50_0, v0x1cd2bf0_0, v0x1cd3a40_0, v0x1cd2d90_0;
+ %set/v v0x1cd39c0_0, 8, 32;
+ %jmp T_15.4;
+T_15.5 ;
+T_15.3 ;
+ %load/v 8, v0x1cd2c70_0, 32;
+ %cmpi/u 8, 1, 32;
+ %jmp/0xz T_15.6, 4;
+ %vpi_call 2 242 "$display", "**** Start of Test ****";
+T_15.6 ;
+ %wait E_0x1cbfcd0;
+ %delay 5000000, 0;
+ %load/v 8, v0x1cd2b50_0, 8;
+ %set/v v0x1cd2510_0, 8, 8;
+ %load/v 8, v0x1cd2bf0_0, 8;
+ %set/v v0x1cd2650_0, 8, 8;
+ %load/v 8, v0x1cd3a40_0, 32;
+ %set/v v0x1cd1cf0_0, 8, 32;
+ %fork TD_alu_tb.string2opcode, S_0x1cd1b90;
+ %join;
+ %load/v 8, v0x1cd1d70_0, 4;
+ %set/v v0x1cd28d0_0, 8, 4;
+ %load/v 8, v0x1cd2d90_0, 1;
+ %set/v v0x1cd2850_0, 8, 1;
+ %load/v 8, v0x1cd2b50_0, 8;
+ %set/v v0x1cd16b0_0, 8, 8;
+ %load/v 8, v0x1cd2bf0_0, 8;
+ %set/v v0x1cd1730_0, 8, 8;
+ %load/v 8, v0x1cd3a40_0, 32;
+ %set/v v0x1cd17b0_0, 8, 32;
+ %wait E_0x1c9be10;
+ %load/v 8, v0x1cd2850_0, 1;
+ %inv 8, 1;
+ %load/v 9, v0x1cd3940_0, 1;
+ %inv 9, 1;
+ %and 8, 9, 1;
+ %jmp/0xz T_15.8, 8;
+ %wait E_0x1c9be10;
+ %wait E_0x1c9be10;
+ %set/v v0x1cd3940_0, 1, 1;
+T_15.8 ;
+ %jmp T_15.0;
+T_15.1 ;
+ %set/v v0x1cd2e10_0, 1, 1;
+ %end;
+ .thread T_15;
+ .scope S_0x1c4b0c0;
+T_16 ;
+ %set/v v0x1cd2cf0_0, 0, 1;
+ %end;
+ .thread T_16;
+ .scope S_0x1c4b0c0;
+T_17 ;
+ %wait E_0x1c9be10;
+ %delay 5000000, 0;
+ %load/v 8, v0x1cd16b0_0, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cd1990_0, 0, 8;
+ %load/v 8, v0x1cd1730_0, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cd1a10_0, 0, 8;
+ %load/v 8, v0x1cd17b0_0, 32;
+ %ix/load 0, 32;
+ %assign/v0 v0x1cd1a90_0, 0, 8;
+ %load/v 8, v0x1cd1830_0, 8;
+ %ix/load 0, 8;
+ %assign/v0 v0x1cd1b10_0, 0, 8;
+ %load/v 8, v0x1cd3940_0, 1;
+ %load/v 9, v0x1cd2850_0, 1;
+ %inv 9, 1;
+ %and 8, 9, 1;
+ %jmp/0xz T_17.0, 8;
+ %load/v 8, v0x1cd1990_0, 8;
+ %set/v v0x1cd3040_0, 8, 8;
+ %load/v 8, v0x1cd1a10_0, 8;
+ %set/v v0x1cd3230_0, 8, 8;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 0;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.2, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %load/v 16, v0x1cd3230_0, 8;
+ %add 8, 16, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.3;
+T_17.2 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 1;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.4, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %mov 16, 8, 8;
+ %mov 24, 0, 24;
+ %addi 16, 1, 32;
+ %set/v v0x1cd38c0_0, 16, 8;
+ %jmp T_17.5;
+T_17.4 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 9;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.6, 8;
+ %load/v 8, v0x1cd3230_0, 8;
+ %mov 16, 8, 8;
+ %mov 24, 0, 24;
+ %addi 16, 1, 32;
+ %set/v v0x1cd38c0_0, 16, 8;
+ %jmp T_17.7;
+T_17.6 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 2;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.8, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %load/v 16, v0x1cd3230_0, 8;
+ %sub 8, 16, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.9;
+T_17.8 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 3;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.10, 8;
+ %load/v 8, v0x1cd29d0_0, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.11;
+T_17.10 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 4;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.12, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %set/v v0x1cd2150_0, 8, 8;
+ %load/v 8, v0x1cd3230_0, 8;
+ %set/v v0x1cd2350_0, 8, 8;
+ %set/v v0x1cd22b0_0, 0, 1;
+ %fork TD_alu_tb.bas, S_0x1cd2070;
+ %join;
+ %load/v 8, v0x1cd2210_0, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.13;
+T_17.12 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 5;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.14, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %set/v v0x1cd2150_0, 8, 8;
+ %load/v 8, v0x1cd3230_0, 8;
+ %set/v v0x1cd2350_0, 8, 8;
+ %set/v v0x1cd22b0_0, 1, 1;
+ %fork TD_alu_tb.bas, S_0x1cd2070;
+ %join;
+ %load/v 8, v0x1cd2210_0, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.15;
+T_17.14 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 6;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.16, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %load/v 16, v0x1cd3230_0, 8;
+ %cmp/u 8, 16, 8;
+ %mov 8, 4, 1;
+ %jmp/0 T_17.18, 8;
+ %mov 9, 0, 8;
+ %jmp/1 T_17.20, 8;
+T_17.18 ; End of true expr.
+ %load/v 17, v0x1cd29d0_0, 8;
+ %jmp/0 T_17.19, 8;
+ ; End of false expr.
+ %blend 9, 17, 8; Condition unknown.
+ %jmp T_17.20;
+T_17.19 ;
+ %mov 9, 17, 8; Return false value
+T_17.20 ;
+ %set/v v0x1cd38c0_0, 9, 8;
+ %jmp T_17.17;
+T_17.16 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 7;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.21, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %mov 16, 8, 8;
+ %mov 24, 0, 24;
+ %subi 16, 1, 32;
+ %set/v v0x1cd38c0_0, 16, 8;
+ %jmp T_17.22;
+T_17.21 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 8;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.23, 8;
+ %load/v 8, v0x1cd3230_0, 8;
+ %mov 16, 8, 8;
+ %mov 24, 0, 24;
+ %subi 16, 1, 32;
+ %set/v v0x1cd38c0_0, 16, 8;
+ %jmp T_17.24;
+T_17.23 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 10;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.25, 8;
+ %load/v 8, v0x1cd29d0_0, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.26;
+T_17.25 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 11;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.27, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %inv 8, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.28;
+T_17.27 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 12;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.29, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %load/v 16, v0x1cd3230_0, 8;
+ %and 8, 16, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.30;
+T_17.29 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 13;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.31, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %load/v 16, v0x1cd3230_0, 8;
+ %or 8, 16, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.32;
+T_17.31 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 14;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.33, 8;
+ %load/v 8, v0x1cd3040_0, 8;
+ %load/v 16, v0x1cd3230_0, 8;
+ %xor 8, 16, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+ %jmp T_17.34;
+T_17.33 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %ix/load 3, 15;
+ %mov 4, 0, 1;
+ %load/av 40, v0x1cd3170, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %jmp/0xz T_17.35, 8;
+ %load/v 8, v0x1cd3230_0, 8;
+ %inv 8, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+T_17.35 ;
+T_17.34 ;
+T_17.32 ;
+T_17.30 ;
+T_17.28 ;
+T_17.26 ;
+T_17.24 ;
+T_17.22 ;
+T_17.17 ;
+T_17.15 ;
+T_17.13 ;
+T_17.11 ;
+T_17.9 ;
+T_17.7 ;
+T_17.5 ;
+T_17.3 ;
+ %load/v 8, v0x1cd30f0_0, 32;
+ %movi 40, 6515826, 32;
+ %cmp/u 8, 40, 32;
+ %mov 8, 4, 1;
+ %load/v 9, v0x1cd2f20_0, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_17.37, 8;
+ %load/v 8, v0x1cd29d0_0, 8;
+ %set/v v0x1cd38c0_0, 8, 8;
+T_17.37 ;
+ %load/v 8, v0x1cd1a90_0, 32;
+ %set/v v0x1cd30f0_0, 8, 32;
+ %load/v 8, v0x1cd1990_0, 8;
+ %set/v v0x1cd25b0_0, 8, 8;
+ %load/v 8, v0x1cd1a10_0, 8;
+ %set/v v0x1cd26d0_0, 8, 8;
+ %load/v 8, v0x1cd29d0_0, 8;
+ %set/v v0x1cd2a50_0, 8, 8;
+ %load/v 8, v0x1cd38c0_0, 8;
+ %set/v v0x1cd37d0_0, 8, 8;
+ %load/v 8, v0x1cd2cf0_0, 1;
+ %inv 8, 1;
+ %set/v v0x1cd2cf0_0, 8, 1;
+ %load/v 8, v0x1cd29d0_0, 8;
+ %load/v 16, v0x1cd38c0_0, 8;
+ %cmp/u 8, 16, 8;
+ %inv 4, 1;
+ %mov 8, 4, 1;
+ %load/v 9, v0x1cd38c0_0, 8;
+ %and/r 9, 9, 8;
+ %cmp/u 9, 2, 1;
+ %mov 9, 6, 1;
+ %or 8, 9, 1;
+ %load/v 9, v0x1cd38c0_0, 8;
+ %or/r 9, 9, 8;
+ %cmp/u 9, 3, 1;
+ %mov 9, 6, 1;
+ %or 8, 9, 1;
+ %load/v 9, v0x1cd29d0_0, 8;
+ %and/r 9, 9, 8;
+ %cmp/u 9, 2, 1;
+ %mov 9, 6, 1;
+ %or 8, 9, 1;
+ %load/v 9, v0x1cd29d0_0, 8;
+ %or/r 9, 9, 8;
+ %cmp/u 9, 3, 1;
+ %mov 9, 6, 1;
+ %or 8, 9, 1;
+ %jmp/0xz T_17.39, 8;
+ %vpi_call 2 379 "$display", "[%0t ps] A:%h[u%h] S:%s[%b] B:%h[u%h] = Y:%h [u%h] expected %h [u%h] -- ERROR Output Y is wrong", $time, v0x1cd1990_0, v0x1cd25b0_0, v0x1cd1a90_0, v0x1cd28d0_0, v0x1cd1a10_0, v0x1cd26d0_0, v0x1cd29d0_0, v0x1cd2a50_0, v0x1cd38c0_0, v0x1cd37d0_0;
+ %load/v 8, v0x1cd2ea0_0, 32;
+ %mov 40, 8, 32;
+ %mov 72, 39, 1;
+ %addi 40, 1, 33;
+ %set/v v0x1cd2ea0_0, 40, 32;
+ %jmp T_17.40;
+T_17.39 ;
+ %vpi_call 2 383 "$display", "[%0t ps] A:%h[u%h] S:%s[%b] B:%h[u%h] = Y:%h [u%h] expected %h [u%h]", $time, v0x1cd1990_0, v0x1cd25b0_0, v0x1cd1a90_0, v0x1cd28d0_0, v0x1cd1a10_0, v0x1cd26d0_0, v0x1cd29d0_0, v0x1cd2a50_0, v0x1cd38c0_0, v0x1cd37d0_0;
+T_17.40 ;
+ %movi 8, 1, 32;
+ %load/v 40, v0x1cd2ea0_0, 32;
+ %cmp/s 8, 40, 32;
+ %jmp/0xz T_17.41, 5;
+ %vpi_call 2 388 "$display", "Maximum error count of %d reached...Terminating simulation", v0x1cd2ea0_0;
+ %vpi_call 2 389 "$finish";
+T_17.41 ;
+T_17.0 ;
+ %load/v 8, v0x1cd2850_0, 1;
+ %set/v v0x1cd2f20_0, 8, 1;
+ %jmp T_17;
+ .thread T_17;
+ .scope S_0x1c4b0c0;
+T_18 ;
+ %vpi_call 2 475 "$dumpfile", "alu_tb.vcd";
+ %vpi_call 2 476 "$dumpvars";
+ %end;
+ .thread T_18;
+# The file index is used to find the file name in the following table.
+:file_names 8;
+ "N/A";
+ "";
+ "alu_tb.v";
+ "alu.v";
+ "alu_controller.v";
+ "alu_datapath.v";
+ "alu_adder.v";
+ "../barrel_shifter/simple/barrel_shifter_simple.v";
ecpu_alu/trunk/alu/run_alu
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/arun
===================================================================
--- ecpu_alu/trunk/alu/arun (nonexistent)
+++ ecpu_alu/trunk/alu/arun (revision 2)
@@ -0,0 +1 @@
+./runit -DRANDOM=10000000 -DDECIMAL_DISPLAY -DFORCE_CLR=0 -DNO_WAVES
ecpu_alu/trunk/alu/arun
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/veriwell.log
===================================================================
--- ecpu_alu/trunk/alu/veriwell.log (nonexistent)
+++ ecpu_alu/trunk/alu/veriwell.log (revision 2)
@@ -0,0 +1,29 @@
+
+
+Veriwell version 2.8.7,
+Copyright (C) 1993-2008 Elliot Mednick and Mark Hummel
+
+Veriwell comes with ABSOLUTELY NO WARRANTY; This is free
+software, and you are welcome to redistribute it under the
+terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License,
+or (at your option) any later version.
+
+lxt support compiled in
+lxt2 support compiled in
+
+Entering Phase I...
+Compiling source file : ../barrel_shifter/simple/barrel_shifter_simple.v
+../barrel_shifter/simple/barrel_shifter_simple.v: L23: warning: INITIAL not supported by Synopsys HDL Compiler(tm)
+
+Entering Phase II...
+Entering Phase III...
+1 warning in compilation
+No errors in compilation
+Top-level modules:
+ alu_barrel_shifter
+
+0 Errors, 1 Warning, Compile time = 0.0, Load time = 0.0, Simulation time = 0.0
+
+Normal exit
+Thank you for using Veriwell
ecpu_alu/trunk/alu/veriwell.log
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/alu/alu_tb.v
===================================================================
--- ecpu_alu/trunk/alu/alu_tb.v (nonexistent)
+++ ecpu_alu/trunk/alu/alu_tb.v (revision 2)
@@ -0,0 +1,480 @@
+//
+`timescale 1ns/1ps
+
+// testbench clock half period
+`define CLK_HALF_PERIOD 10000
+`define ZERO 0
+
+// Use the same defines from the controller
+`include "alu_controller.vh"
+`ifdef DECIMAL_DISPLAY
+ `define DISPLAY_FORMAT_SELECTED "[%0t ps] A:%d[u%d] S:%s[%b] B:%d[u%d] = Y:%d [u%d] expected %d [u%d]"
+`endif
+`ifdef HEX_DISPLAY
+ `define DISPLAY_FORMAT_SELECTED "[%0t ps] A:%h[u%h] S:%s[%b] B:%h[u%h] = Y:%h [u%h] expected %h [u%h]"
+`endif
+`ifdef BINARY_DISPLAY
+ `define DISPLAY_FORMAT_SELECTED "[%0t ps] A:%b[u%b] S:%s[%b] B:%b[u%b] = Y:%b [u%b] expected %b [u%b]"
+`endif
+
+`ifndef DISPLAY_FORMAT_SELECTED
+ `define DISPLAY_FORMAT_SELECTED "[%0t ps] A:%h[u%h] S:%s[%b] B:%h[u%h] = Y:%h [u%h] expected %h [u%h]"
+`endif
+
+`define DISPLAY_FORMAT `DISPLAY_FORMAT_SELECTED
+`define DISPLAY_FORMAT_ERROR {`DISPLAY_FORMAT_SELECTED, " -- ERROR Output Y is wrong"}
+module test_vector;
+ parameter DWIDTH = 8;
+ parameter OPWIDTH = 4;
+
+ reg signed [DWIDTH-1:0] A ; // ALU input operand 1
+ reg signed [DWIDTH-1:0] B ; // ALU input operand 2
+ reg [8*OPWIDTH-1:0] S ; // ALU input opcode
+ reg [DWIDTH-1:0] Y ; // ALU output
+
+endmodule
+
+module alu_tb;
+
+ // ALU test vector record
+ parameter DWIDTH = 8;
+ parameter OPWIDTH = 4;
+
+
+ // ALU access regs
+ reg [DWIDTH-1:0 ] A ;
+ reg [DWIDTH-1:0 ] B ;
+ reg [OPWIDTH-1:0] S ;
+ wire signed [DWIDTH-1:0 ] Y ;
+ reg CLR ;
+
+ reg CLK ;
+ wire C ;
+ wire V ;
+ wire Z ;
+
+ // keep a copy of the previous CLR
+ reg last_CLR ;
+
+ // unsigned local copies for the "recorded" copies for stimulus
+ //
+ reg [DWIDTH-1:0 ] A_u ;
+ reg [DWIDTH-1:0 ] B_u ;
+ reg [DWIDTH-1:0 ] Y_u ;
+
+ // finished = '1' indicates end of test run
+ reg finished ;
+
+ // used to synchronise verification with stimulus
+ reg started ;
+
+ integer infile , success ;
+ integer outfile ;
+ integer count ;
+
+ reg cc, vv, zz, clrc, space ;
+ reg [DWIDTH-1:0] aa, bb, yy ;
+
+ reg [8*OPWIDTH-1:0] ss, last_ss ;
+
+ reg random_mode ;
+ integer random_count ;
+ integer random_number ;
+
+ integer errors_found ;
+
+ reg [8*OPWIDTH:1] opcode_list [0:15] ;
+ initial
+ begin
+ opcode_list[`cADD_AB ] = "add";
+ opcode_list[`cINC_A ] = "inca";
+ opcode_list[`cINC_B ] = "incb";
+ opcode_list[`cSUB_AB ] = "sub";
+ opcode_list[`cCMP_AB ] = "cmp";
+ opcode_list[`cASL_AbyB] = "asl";
+ opcode_list[`cASR_AbyB] = "asr";
+ opcode_list[`cCLR ] = "clr";
+ opcode_list[`cDEC_A ] = "deca";
+ opcode_list[`cDEC_B ] = "decb";
+ opcode_list[`cMUL_AB ] = "mul";
+ opcode_list[`cCPL_A ] = "cpla";
+ opcode_list[`cAND_AB ] = "and";
+ opcode_list[`cOR_AB ] = "or";
+ opcode_list[`cXOR_AB ] = "xor";
+ opcode_list[`cCPL_B ] = "cplb";
+
+ end
+ initial
+ begin
+ `ifdef RANDOM
+ random_count = `RANDOM;
+ random_mode = 1'b1;
+ $display ("Generating %0d random inputs", random_count);
+ `else
+ random_mode = 1'b0;
+ random_count = 0;
+ `endif
+ end
+
+ // records to store stimulus for verification
+ test_vector #(DWIDTH, OPWIDTH) this_record ();
+ test_vector #(DWIDTH, OPWIDTH) next_record ();
+
+ // instantiate ALU
+ alu #(DWIDTH, OPWIDTH) alu_inst0 (
+ A ,
+ B ,
+ S ,
+ Y ,
+ CLR ,
+ CLK ,
+ C ,
+ V ,
+ Z
+ );
+
+ // apply clock stimulus
+ //clock_stim : process
+ initial
+ begin
+ CLK = 1'b0;
+ forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
+ end
+
+ always @(CLK)
+ begin
+ `ifdef DEBUG_ALU_TB
+ $display("Time has reached [%0t] ",$time);
+ `endif
+ end
+
+ initial errors_found = 0;
+
+ // end test
+ always @(posedge CLK or finished)
+ begin
+ if (finished)
+ begin
+ if (errors_found > 0)
+ $display("Test FAILED with %d ERRORs [%0t] ", errors_found, $time);
+ else
+ $display("Test PASSED ");
+
+ // close files and finish
+ $fclose(infile);
+ $fclose(outfile);
+ $finish;
+ end
+ end
+
+
+
+ // apply_test_vectors
+ initial
+ begin
+ #1;
+ //file infile : text is in "alu_test.txt";
+ infile = $fopen("alu_test.txt", "r");
+
+
+ finished = 1'b0;
+ count = 0;
+
+ CLR = 1'b1;
+
+ started = 1'b0;
+
+
+ while ((!$feof(infile) && !random_mode) || (random_mode && random_count > 0))
+ begin
+
+ count = count + 1;
+
+ // verify outputs are as expected
+
+ `ifdef DEBUG_ALU_TB
+ $display ("%t %0d random inputs", $time, random_count);
+ `endif
+
+ if (random_mode)
+ begin
+ random_number = $random ;
+ `ifdef FORCE_A
+ aa = `FORCE_A ;
+ `else
+ aa = random_number ;
+ `endif
+
+ random_number = $random ;
+ `ifdef FORCE_B
+ bb = `FORCE_B ;
+ `else
+ bb = random_number ;
+ `endif
+
+ random_number = $random ;
+ `ifdef FORCE_OPCODE
+ ss = `FORCE_OPCODE ;
+ `else
+ ss = get_random_opcode(random_number);
+ `endif
+
+ random_number = $random ;
+ `ifdef FORCE_CLR
+ clrc = `FORCE_CLR ;
+ `else
+ clrc = random_number ;
+ `endif
+
+ random_count = random_count - 1;
+ end
+ else
+ begin
+ success = $fscanf(infile, "%b %b %s %b", aa, bb, ss, clrc);
+ while (success == 0 && !$feof(infile))
+ begin
+ success = $fgetc(infile);
+ success = $fscanf(infile, "%b %b %s %b", aa, bb, ss, clrc);
+ end
+ end
+
+ if (count == 1)
+ $display("**** Start of Test ****");
+
+ //$display("%b %b %s %b", aa, bb, ss, clrc);
+ `ifdef DEBUG_ALU_TB
+
+ $stop;
+ `endif
+
+ // wait for falling edge of CLK
+ @(negedge CLK);
+
+ `ifdef DEBUG_ALU_TB
+ $display("**** stage2 of Test ****");
+ $stop;
+ `endif
+ // wait for half of half a period
+ #(`CLK_HALF_PERIOD / 2);
+
+
+ // apply stimulus to inputs
+ `ifdef DEBUG_ALU_TB
+ $display("**** stage3 of Test ****");
+ $stop;
+ `endif
+ A = aa ;
+ B = bb ;
+ S = string2opcode(ss) ;
+ CLR = clrc ;
+
+ `ifdef DEBUG_ALU_TB
+ $display("**** stage4 of Test ****");
+ $stop;
+ `endif
+ // store stimulus for use when verifying outputs
+ //if (last_ss == "clr")
+ //begin
+ // next_record.A = `ZERO;
+ // next_record.B = `ZERO;
+ //end
+ //else
+ //begin
+ next_record.A = aa;
+ next_record.B = bb;
+ //end
+
+ next_record.S = ss;
+
+ // wait for rising edge of clock when data
+ // should be loaded from registers into ALU
+ @(posedge CLK);
+
+ // set local 'started' flag so verification can
+ // start
+ // grace period of 2 clock cycles for ALU to read
+ // first set of data
+
+ `ifdef DEBUG_ALU_TB
+ $stop;
+ `endif
+
+ if (!CLR && !started)
+ begin
+ @(posedge CLK);
+ @(posedge CLK);
+ started = 1'b1;
+ end
+ end // while $feof
+
+ // end test
+ finished = 1'b1;
+
+ end // process apply_test_vectors
+
+ reg signed [DWIDTH-1:0] result ;
+ reg [DWIDTH-1:0] result_u ;
+ reg [DWIDTH-1:0] op1 ;
+ reg [DWIDTH-1:0] op2 ;
+
+
+ reg check_here;
+ initial check_here = 1'b0;
+ // verify_test
+ always @(posedge CLK)
+ begin
+ // wait a little more after results appear
+ #(`CLK_HALF_PERIOD/2);
+
+ // get expected record
+ this_record.A <= next_record.A;
+ this_record.B <= next_record.B;
+ this_record.S <= next_record.S;
+ this_record.Y <= next_record.Y;
+
+ if (started && !CLR)
+ begin
+ // convert string operands from this_record
+ // into std_logic_vectors
+ op1 = this_record.A;
+ op2 = this_record.B;
+
+ // depending on opcode command string...perform
+ // high level equivalent of ALU operation and store
+ // in 'result'
+ if (this_record.S == opcode_list[`cADD_AB ] ) result = op1 + op2 ;
+ else if (this_record.S == opcode_list[`cINC_A ] ) result = op1 + 1 ;
+ else if (this_record.S == opcode_list[`cINC_B ] ) result = op2 + 1 ;
+ else if (this_record.S == opcode_list[`cSUB_AB ] ) result = op1 - op2 ;
+ else if (this_record.S == opcode_list[`cCMP_AB ] ) result = Y ;
+ else if (this_record.S == opcode_list[`cASL_AbyB] ) result = bas(op1, op2, 1'b0);
+ else if (this_record.S == opcode_list[`cASR_AbyB] ) result = bas(op1, op2, 1'b1);
+ else if (this_record.S == opcode_list[`cCLR ] ) result = (op1==op2) ? 'd0: Y;
+ else if (this_record.S == opcode_list[`cDEC_A ] ) result = op1 - 1 ;
+ else if (this_record.S == opcode_list[`cDEC_B ] ) result = op2 - 1 ;
+ else if (this_record.S == opcode_list[`cMUL_AB ] ) result = Y ;
+ else if (this_record.S == opcode_list[`cCPL_A ] ) result = ~op1 ;
+ else if (this_record.S == opcode_list[`cAND_AB ] ) result = op1 & op2 ;
+ else if (this_record.S == opcode_list[`cOR_AB ] ) result = op1 | op2 ;
+ else if (this_record.S == opcode_list[`cXOR_AB ] ) result = op1 ^ op2 ;
+ else if (this_record.S == opcode_list[`cCPL_B ] ) result = ~op2 ;
+
+
+ // WORKAROUND for bug wher clr lasts for two cycles
+ if (last_ss == "clr" || last_CLR)
+ result = Y;
+ last_ss = this_record.S;
+
+ // create signed and unsigned copies of
+ // ALU output Y, stimulus values and the expected result
+ A_u = this_record.A ;
+ B_u = this_record.B ;
+ Y_u = Y ;
+ result_u = result ;
+
+ check_here = ~ check_here; // for debug
+ if( Y != result || (&result === 1'bx) || (|result === 1'bz)
+ || (&Y === 1'bx) || (|Y === 1'bz))
+ begin
+ $display(`DISPLAY_FORMAT_ERROR, $time, this_record.A, A_u, this_record.S, S, this_record.B, B_u, Y, Y_u, result, result_u);
+ errors_found = errors_found + 1;
+ end
+ else
+ $display(`DISPLAY_FORMAT, $time, this_record.A, A_u, this_record.S, S, this_record.B, B_u, Y, Y_u, result, result_u);
+
+ `ifdef STOP_ON_ERROR
+ if (errors_found > `STOP_ON_ERROR)
+ begin
+ $display("Maximum error count of %d reached...Terminating simulation", errors_found);
+ $finish;
+ end
+ `endif
+
+ end // end if (started and !CLR)
+
+ last_CLR = CLR;
+
+ end // process verify_test
+
+ `ifdef CREATE_SIGNAL_LOG
+ // open output file for writing
+ initial outfile = $fopen("alu_test.out","w");
+
+ // vector_stim_out
+ always @(posedge CLK )
+ begin
+ $fwrite (outfile, "A=%h B=%h S=%b Y=%h CLR=%b CLK=%b C=%b V=%b Z=%b\n", A,B,S,Y,CLR,CLK,C,V,Z);
+ end
+ `endif
+
+
+ // function to return the opcode as a std_logic_vector
+ // from the given string
+ function [OPWIDTH-1:0] string2opcode;
+ input [8*OPWIDTH-1:0] s;
+ reg [8*OPWIDTH:1] t;
+ reg [OPWIDTH-1:0] opcode;
+ begin
+
+
+ if (s == opcode_list[`cADD_AB ]) opcode = `cADD_AB ;
+ else if (s == opcode_list[`cINC_A ]) opcode = `cINC_A ;
+ else if (s == opcode_list[`cINC_B ]) opcode = `cINC_B ;
+ else if (s == opcode_list[`cSUB_AB ]) opcode = `cSUB_AB ;
+ else if (s == opcode_list[`cCMP_AB ]) opcode = `cCMP_AB ;
+ else if (s == opcode_list[`cASL_AbyB ]) opcode = `cASL_AbyB ;
+ else if (s == opcode_list[`cASR_AbyB ]) opcode = `cASR_AbyB ;
+ else if (s == opcode_list[`cCLR ]) opcode = `cCLR ;
+ else if (s == opcode_list[`cDEC_A ]) opcode = `cDEC_A ;
+ else if (s == opcode_list[`cDEC_B ]) opcode = `cDEC_B ;
+ else if (s == opcode_list[`cMUL_AB ]) opcode = `cMUL_AB ;
+ else if (s == opcode_list[`cCPL_A ]) opcode = `cCPL_A ;
+ else if (s == opcode_list[`cAND_AB ]) opcode = `cAND_AB ;
+ else if (s == opcode_list[`cOR_AB ]) opcode = `cOR_AB ;
+ else if (s == opcode_list[`cXOR_AB ]) opcode = `cXOR_AB ;
+ else if (s == opcode_list[`cCPL_B ]) opcode = `cCPL_B ;
+
+ string2opcode = opcode;
+ end
+ endfunction
+
+
+ function [8*OPWIDTH:1] get_random_opcode;
+ input integer myseed;
+ integer tmp;
+ begin
+ tmp = $random(myseed);
+ get_random_opcode = opcode_list[({tmp} % 11)];
+ end
+ endfunction
+
+ function [DWIDTH-1:0] bas ;
+ input [DWIDTH-1:0] a1 ;
+ input [DWIDTH-1:0] shift_size ;
+ input direction ;
+ reg [DWIDTH-1:0] tmp ;
+ integer tmp2 ;
+ begin
+ tmp = a1;
+ tmp2 = shift_size[2:0];
+ while (tmp2 > 0)
+ begin
+ if (direction)
+ tmp = {tmp[0], tmp[DWIDTH-1:1]};
+ else
+ tmp = {tmp[DWIDTH-2:0], tmp[DWIDTH-1]};
+ tmp2 = tmp2 - 1;
+ end
+ bas = tmp;
+ end
+ endfunction
+
+ `ifndef NO_WAVES
+ initial
+ begin
+ $dumpfile("alu_tb.vcd");
+ $dumpvars;
+ end
+ `endif
+endmodule
+
ecpu_alu/trunk/alu/alu_tb.v
Property changes :
Added: svn:executable
Index: ecpu_alu/trunk/barrel_shifter/simple/barrel_shifter_simple.v
===================================================================
--- ecpu_alu/trunk/barrel_shifter/simple/barrel_shifter_simple.v (nonexistent)
+++ ecpu_alu/trunk/barrel_shifter/simple/barrel_shifter_simple.v (revision 2)
@@ -0,0 +1,54 @@
+`timescale 1ns/1ps
+module alu_barrel_shifter (
+ x ,
+ y ,
+ z ,
+ c ,
+ direction
+ );
+ parameter DWIDTH = 8;
+
+ input [DWIDTH-1:0] x ;
+ input [DWIDTH-1:0] y ;
+ output [DWIDTH-1:0] z ;
+ output c ;
+ input direction ;
+
+ reg [DWIDTH-1:0] z ;
+ reg c ;
+
+ reg [DWIDTH-1:0] y_tmp ;
+
+
+ initial
+ begin
+ c = 1'b0;
+ y_tmp = 'd0; // initialise for simulation purposes
+ end
+
+ always @(x or y or direction)
+ begin
+
+ z = x;
+ c = 0;
+ for (y_tmp={{DWIDTH-3{1'b0}},y[2:0]}; y_tmp > 0; y_tmp = y_tmp - 1)
+ begin
+
+ `ifdef DEBUG_BARREL_SHIFTER
+ $display ("[%0t] D%0d z=%0b", $time, y_tmp, z);
+ `endif
+ if (direction)
+ begin
+ z = {z[0], z[DWIDTH-1:1]};
+ c = z[0] ;
+ end
+ else
+ begin
+ z = {z[DWIDTH-2:0], z[DWIDTH-1]} ;
+ c = z[DWIDTH-2] ;
+ end
+ end
+
+ end
+
+endmodule
ecpu_alu/trunk/barrel_shifter/simple/barrel_shifter_simple.v
Property changes :
Added: svn:executable
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.