URL
https://opencores.org/ocsvn/fluid_core_2/fluid_core_2/trunk
Subversion Repositories fluid_core_2
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/fluid_core_2/trunk/rtl/Inst_Mem.v
0,0 → 1,61
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
`include "Programming.v" |
|
module Inst_Mem( |
input [0:`pc_w] inst_addr, |
input Clk, |
output [0:`inst_w] inst |
); |
|
reg [0:`inst_w] instruction [0:15]; |
reg [0:`inst_w] instb; |
|
initial begin |
instruction[0] = {`iLoad_RI,`dR3,6'd2}; |
instruction[1] = {`iAdduOP_RRI,5'd0,`R3,3'd0}; |
instruction[2] = {`iLoad_RI,`dR2,6'd1}; |
instruction[3] = {`iAddVector_RI,`dR1,6'd11}; |
instruction[4] = {`iAddVector_RI,`dR0,6'b11111100}; |
instruction[5] = {`iLoad_RI,`dR1,6'd0}; |
instruction[6] = {5'd0,`dR0,`R1,`R2}; |
instruction[7] = {`iStore_sRI,`dR0,6'd3}; |
instruction[8] = {`iBranch_RI,`ulnk,`bALL,6'd4}; |
instruction[9] = {16'hFFFF}; |
instruction[10] = {6'd8,`dR0,`R1,`R2}; |
instruction[11] = {`iADD_RRR,`dR3,`R2,`R1}; |
instruction[12] = {`iBranch_RI,`bRET,6'd0}; |
instruction[13] = {`iAND_RRI,`dR2,`R2,3'd1}; |
instruction[14] = {`iOR_RRI,`dR2,`R2,3'd1}; |
instruction[15] = {`iXOR_RRI,`dR2,`R2,3'd1}; |
end |
|
assign inst = instruction[inst_addr]; |
|
endmodule |
/fluid_core_2/trunk/rtl/ioPort.v
0,0 → 1,46
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
module ioPort( |
input en, rd, wr, |
input Clk, |
inout [0:3] fc_data, |
inout [0:3] io_data |
); |
|
reg [0:3] io_data_buff; |
|
always @(posedge Clk) begin |
if (en & wr) io_data_buff <= fc_data; |
end |
|
|
assign fc_data = (rd) ? io_data:'bz; |
assign io_data = (~rd) ? io_data_buff:'bz; |
|
endmodule |
/fluid_core_2/trunk/rtl/FluidCore.v
0,0 → 1,258
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module FluidCore( |
input [0:`inst_w] exInstruction, |
input Clk, |
input RST, |
input [0:`intr_msb] Interrupt, |
output [0:`pc_w] exInstAddr, |
output [0:`memory_bus_w] exMemoryAddr, |
inout [0:`dpw] exMemoryData, |
output exMemoryClk, |
output exMemoryWrite |
); |
|
wire Return, linked; |
wire wb_write, write_intr, write_uop, intr, branch; |
wire [0:`pc_w] intr_vector; |
wire [0:`uop_vector_msb] uop_vector; |
wire [0:`uop_msb] uop; |
wire [0:4] bubble_lines; |
wire stall_IF_ID_EX, load_hazard; |
Staller Staller_inst(.Clk(Clk),.RST(RST),.bubble(branch|Return),.bubble_lines(bubble_lines),.load_hazard(load_hazard),.stall(stall_IF_ID_EX)); |
|
wire [0:`IF_ID_reg_w] IF_ID_reg_in, IF_ID_reg_out; |
P_Reg #(`IF_ID_reg_w) IF_ID_reg(.Clk(Clk),.RST(RST),.stall(stall_IF_ID_EX),.bubble(bubble_lines[0]),.prev_stage(IF_ID_reg_in),.next_stage(IF_ID_reg_out)); |
|
wire [0:`ID_EX_reg_w] ID_EX_reg_in, ID_EX_reg_out; |
P_Reg #(`ID_EX_reg_w) ID_EX_reg(.Clk(Clk),.RST(RST),.stall(stall_IF_ID_EX),.bubble(bubble_lines[1]),.prev_stage(ID_EX_reg_in),.next_stage(ID_EX_reg_out)); |
|
wire [0:`EX_MEM_reg_w] EX_MEM_reg_in, EX_MEM_reg_out; |
P_Reg #(`EX_MEM_reg_w) EX_MEM_reg(.Clk(Clk),.RST(RST),.stall(stall_IF_ID_EX),.bubble(bubble_lines[2]),.prev_stage(EX_MEM_reg_in),.next_stage(EX_MEM_reg_out)); |
|
wire [0:`MEM_WB_reg_w] MEM_WB_reg_in, MEM_WB_reg_out; |
P_Reg #(`MEM_WB_reg_w) MEM_WB_reg(.Clk(Clk),.RST(RST),.stall(0),.bubble(bubble_lines[3]),.prev_stage(MEM_WB_reg_in),.next_stage(MEM_WB_reg_out)); |
|
|
wire [0:`dpw] op_reg_a, op_reg_b, wb_data; |
wire [0:`reg_sel_w] reg_a, reg_b; |
wire [0:`bc_msb] wb_dst; |
wire [0:`pc_w] branch_target; |
wire [0:3] stkFlag; |
|
//------Forwarding Logic-----------// |
wire s_EX_MEM_reg, s_ID_EX_reg, rrr_adm, rri_adm, not_ID_EX_branch, not_EX_MEM_branch, ID_EX_load, not_branch; |
wire [0:`reg_sel_w] d_EX_MEM_reg, d_ID_EX_reg; |
wire [0:`dpw] b_EX_MEM_reg, b_MEM_WB_reg; |
wire [0:1] reg_src_A, reg_src_B, st_src; |
wire [0:2] load_hazard_abs; |
wire [0:3] adm; |
wire [0:`type_msb] t_ID_EX_reg, t_EX_MEM_reg, t_IF_ID_reg; |
/* |
d prefixed wires carry previous stage destination registers, these are compared with current inst's dest reg |
if they match, current inst is associated with some bits to specify fwding from that stage |
*/ |
assign s_EX_MEM_reg = bubble_lines[3]; //actual reg is populated a cycle after so sample it after a cycle hence 3 instead of 2 |
assign s_ID_EX_reg = bubble_lines[2]; //same as above |
assign t_ID_EX_reg = ID_EX_reg_out[0:`type_msb]; |
assign t_EX_MEM_reg = EX_MEM_reg_out[0:`type_msb]; |
assign d_ID_EX_reg = ID_EX_reg_out[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb]; |
assign d_EX_MEM_reg = EX_MEM_reg_out[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+1+`bc_msb]; |
assign b_EX_MEM_reg = EX_MEM_reg_out[`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+1:`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+1+`dpw]; |
assign b_MEM_WB_reg = MEM_WB_reg_out[`type_msb+1+`wb_dst_msb+1+`reg_sel_w+1:`type_msb+1+`wb_dst_msb+1+`reg_sel_w+1+`dpw]; |
assign not_ID_EX_branch = ~(t_ID_EX_reg == `type_branch);//(|(t_ID_EX_reg ^ `type_branch)); |
assign not_EX_MEM_branch = ~(t_EX_MEM_reg == `type_branch);// (|(t_EX_MEM_reg ^ `type_branch)); |
assign ID_EX_load = (t_ID_EX_reg == `type_load);//~(|(t_ID_EX_reg ^ `type_load)); |
assign fw_c_1 = s_ID_EX_reg & not_branch & not_ID_EX_branch; |
assign fw_c_2 = s_EX_MEM_reg & not_branch & not_EX_MEM_branch; |
//--------Clock and Reset Behaviour--------// |
|
//always@(posedge Clk or posedge RST) begin |
// if (RST) begin |
// |
// ID_EX_reg <= 0; |
// EX_MEM_reg <= 0; |
// MEM_WB_reg <= 0; |
// end |
// else begin |
// |
// ID_EX_reg <= ID_EX_reg_wire; |
// EX_MEM_reg <= EX_MEM_reg_wire; |
// MEM_WB_reg <= MEM_WB_reg_wire; |
// end |
//end |
|
//--------Sub Modules-------------------// |
|
//Instruction Fetch Stage |
IF_Stage IF_Stage_inst ( |
.Clk(Clk), |
.RST(RST), |
.intr(intr), |
.stkFlag(stkFlag), |
.return_back(Return), |
.linked(linked), |
.intr_vector(intr_vector), |
.exInstruction(exInstruction), |
.exInstAddr(exInstAddr), |
.IF_ID_reg(IF_ID_reg_in), |
.branch_target(branch_target), |
.branch(branch), |
.stall(stall_IF_ID_EX) |
); |
|
//Register File |
Reg_File Reg_File_inst ( |
.Clk(Clk), |
.RST(RST), |
.reg_a(reg_a), |
.reg_b(reg_b), |
.wb_reg(wb_dst), |
.op_a(op_reg_a), |
.op_b(op_reg_b), |
.word(wb_data), |
.write(wb_write) |
); |
|
//----Operand Forwarding----// |
Reg_Hist Reg_Hist_inst ( |
//.Clk(Clk), |
//.RST(RST), |
//.s_ID_EX_reg(s_ID_EX_reg), |
//.s_EX_MEM_reg(s_EX_MEM_reg), |
.ID_EX_reg(d_ID_EX_reg), |
.EX_MEM_reg(d_EX_MEM_reg), |
//.ID_EX_type(t_ID_EX_reg), |
.nxt_reg_A(IF_ID_reg_out[`uop_vector_msb+1+`bc_msb+1+`reg_sel_w+1:`uop_vector_msb+1+`bc_msb+1+`reg_sel_w+1+`reg_sel_w]), |
.nxt_reg_B(IF_ID_reg_out[`uop_vector_msb+1+`bc_msb+1:`uop_vector_msb+1+`bc_msb+1+`reg_sel_w]), |
.st_reg(IF_ID_reg_out[`uop_vector_msb+1+`bc_msb-`reg_sel_w:`uop_vector_msb+1+`bc_msb]), |
//.type(t_IF_ID_reg), |
.reg_src_A(reg_src_A), |
.reg_src_B(reg_src_B), |
.load_hazard(load_hazard), |
.load_hazard_abs(load_hazard_abs), |
.st_src(st_src), |
.rrr_adm(rrr_adm), |
.rri_adm(rri_adm), |
//.not_ID_EX_branch(not_ID_EX_branch), |
//.not_EX_MEM_branch(not_EX_MEM_branch), |
.ID_EX_load(ID_EX_load), |
//.not_branch(not_branch), |
.fw_c_1(fw_c_1), |
.fw_c_2(fw_c_2) |
//.stall(stall_IF_ID_EX) |
); |
//Instruction Decode Stage |
ID_Stage ID_Stage_inst ( |
.Clk(Clk), |
.RST(RST), |
.IF_ID_reg(IF_ID_reg_out), |
.RF_a(reg_a), |
.RF_b(reg_b), |
.RF_op_a(op_reg_a), |
.RF_op_b(op_reg_b), |
.ID_EX_reg(ID_EX_reg_in), |
.reg_src_A(reg_src_A), |
.reg_src_B(reg_src_B), |
//.curr_type(t_IF_ID_reg), |
.load_hazard_abs(load_hazard_abs), |
.st_src(st_src), |
.rrr_adm(rrr_adm), |
.rri_adm(rri_adm), |
.not_branch(not_branch), |
.uop_vector(uop_vector), |
.uop(uop) |
); |
|
//uOP Store |
uOP_Store uOP_Store_inst( |
.Clk(Clk), |
.uop_vector(uop_vector), |
.uop(uop), |
.write(write_uop), |
.write_vector(wb_dst), |
.write_uop(wb_data) |
); |
|
//Execute Stage |
EX_Stage EX_Stage_inst ( |
.Clk(Clk), |
.RST(RST), |
.ret(Return), |
.stkFlag(stkFlag), |
.ID_EX_reg(ID_EX_reg_out), |
.EX_MEM_reg(EX_MEM_reg_in), |
.b_EX_MEM_reg(b_EX_MEM_reg), |
.b_MEM_WB_reg(b_MEM_WB_reg) |
); |
|
//Memory Stage |
MEM_Stage MEM_Stage_inst ( |
.Clk(Clk), |
.RST(RST), |
.linked(linked), |
.EX_MEM_reg(EX_MEM_reg_out), |
.MEM_WB_reg(MEM_WB_reg_in), |
.ex_mem_addr(exMemoryAddr), |
.ex_mem_data(exMemoryData), |
.mem_Clk(exMemoryClk), |
.mem_wr(exMemoryWrite), |
.branch_target(branch_target), |
.branch(branch), |
.return_back(Return) |
); |
|
//Write Back Stage |
WB_Stage WB_Stage_inst ( |
.Clk(Clk), |
.RST(RST), |
.MEM_WB_reg(MEM_WB_reg_out), |
.wb_dst(wb_dst), |
.wb_data(wb_data), |
.write_rf(wb_write), |
.write_intr(write_intr), |
.write_uop(write_uop), |
.branch(branch), |
.bubble_free(bubble_lines[4]) |
); |
|
//Interrupt Unit |
interrupt_unit interrupt_unit_inst( |
.Clk(Clk), |
.return_back(Return), |
.intr_req(Interrupt), |
.intr_inx(wb_dst), |
.intr(intr), |
.vector(intr_vector), |
.new_vector(wb_data), |
.write(write_intr) |
); |
|
endmodule |
/fluid_core_2/trunk/rtl/Reg_File.v
0,0 → 1,70
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
module Reg_File( |
input Clk, |
input RST, |
input [0:`reg_sel_w] reg_a, |
input [0:`reg_sel_w] reg_b, |
input [0:`reg_sel_w] wb_reg, |
input [0: `dpw] word, |
output [0:`dpw] op_a, |
output [0:`dpw] op_b, |
input write |
); |
|
//------------Register Array---------------// |
reg [0:`dpw] registers[0:`reg_n]; |
|
//Init for Testing |
initial begin |
registers[0] <= 0; |
registers[1] <= 0; |
registers[2] <= 0; |
registers[3] <= 0; |
registers[4] <= 0; |
registers[5] <= 0; |
registers[6] <= 0; |
registers[7] <= 0; |
end |
|
|
//Write Back Stage |
|
|
always@(posedge Clk) begin //---The reg_a and word lines are ready before the edge, the rising edge of next cycle completes the write back---// |
if (write) begin//write |
registers[wb_reg] <= word; |
end |
end |
|
//ID stage - Read |
assign op_a = registers[reg_a]; |
assign op_b = registers[reg_b]; |
|
endmodule |
/fluid_core_2/trunk/rtl/ID_Stage.v
0,0 → 1,110
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
|
module ID_Stage( |
input [0:`IF_ID_reg_w] IF_ID_reg, |
input Clk, |
input RST, |
output [0:`reg_sel_w] RF_a, |
output [0:`reg_sel_w] RF_b, |
input [0:`dpw] RF_op_a, |
input [0:`dpw] RF_op_b, |
output [0:`ID_EX_reg_w] ID_EX_reg, |
//---op forwarding pins---// |
//output [0:`type_msb] curr_type, |
input [0:1] reg_src_A, reg_src_B, st_src, |
input [0:2] load_hazard_abs, |
output rrr_adm, rri_adm, not_branch, |
output [0:`uop_vector_msb] uop_vector, |
input [0:`uop_msb] uop |
); |
//-----------------------MicroOperation--------------------------// |
// wire [0:`uop_vector_msb] uop_vector; |
// wire [0:`uop_msb] uop; |
assign uop_vector = IF_ID_reg[0:`uop_vector_msb]; |
|
|
|
wire [0:3] adm; |
wire [0:`type_msb] Type; |
wire [0:`wb_dst_msb] WB_Dest; |
wire [0:`mod_sel_msb] Mod_Sel; |
wire [0:`operation_msb] Operation; |
wire bS0, bS1, bS2, bImm; |
|
|
assign Type = uop[0:`type_msb]; |
assign WB_Dest = uop[`type_msb+1:`type_msb+1+`wb_dst_msb]; |
assign adm = uop[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+4]; |
assign bS0 = uop[`type_msb+1+`wb_dst_msb+1]; |
assign bS1 = uop[`type_msb+1+`wb_dst_msb+2]; |
assign bS2 = uop[`type_msb+1+`wb_dst_msb+3]; |
assign bImm = uop[`type_msb+1+`wb_dst_msb+4]; |
assign Mod_Sel = uop[`type_msb+1+`wb_dst_msb+5:`type_msb+1+`wb_dst_msb+5+`mod_sel_msb]; |
assign Operation = uop[`type_msb+1+`wb_dst_msb+5+`mod_sel_msb+1:`type_msb+1+`wb_dst_msb+5+`mod_sel_msb+1+`operation_msb]; |
|
//------------fetch operands------------------// |
wire [0:`inst_w-`uop_vector_msb-1] raw_operands; |
assign raw_operands = IF_ID_reg[`uop_vector_msb+1:`inst_w]; |
|
wire [0:`dpw] S0, S1, S2, Imm; |
reg [0:`dpw] buff_op_a, buff_op_b; |
wire [0:`bc_msb] Rd_BC; |
|
assign Rd_BC = raw_operands[0:`bc_msb]; |
|
|
//update RF_a in negative half of cycle -- no need for that wrong comment! |
assign RF_a = bS0 ? Rd_BC[1:`bc_msb] : bS2 ? raw_operands[`bc_msb+1+`reg_sel_w+1:`bc_msb+1+`reg_sel_w+1+`reg_sel_w]:0 ; |
assign S0 = bS0 ? buff_op_a : 0; |
|
assign RF_b = bS1 ? raw_operands[`bc_msb+1:`bc_msb+1+`reg_sel_w]:0; |
assign S1 = bS1 ? buff_op_b : 0; |
|
|
assign Imm = bImm ? raw_operands[`bc_msb+1:`inst_w-`uop_vector_msb-1]:raw_operands[`bc_msb+1+`reg_sel_w+1:`inst_w-`uop_vector_msb-1]; |
assign S2 = bS2 ? buff_op_a : Imm; |
|
//latch on to reg file in the negative half |
always@(*) begin |
if (~Clk) begin |
buff_op_a <= RF_op_a; |
buff_op_b <= RF_op_b; |
end |
end |
|
//----Operand Forwarding----// |
assign not_branch = (|(Type ^ `type_branch)); |
assign rrr_adm = (adm == `RRR);//(~(|(adm ^ `RRR))); |
assign rri_adm = (adm == `RRI); |
|
//-----next stage----// |
assign ID_EX_reg = {Type,WB_Dest,Mod_Sel,Operation,Rd_BC,S0,S1,S2,reg_src_A,reg_src_B,st_src,load_hazard_abs};// |
endmodule |
/fluid_core_2/trunk/rtl/uOP_Store.v
0,0 → 1,86
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
/* |
-----General Format--------- |
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, |
|Type|S0|S1|S2|Imm|Mod_Sel|Operation| |
````````````````````````````````````` |
|
*/ |
|
|
module uOP_Store( |
input Clk, |
input write, |
input [0:`uop_vector_msb] write_vector, |
input [0:`uop_msb] write_uop, |
input [0:`uop_vector_msb] uop_vector, |
output [0:`uop_msb] uop |
); |
|
reg [0:`uop_msb] uOP_rom [0:`uop_n]; |
|
assign uop = uOP_rom[uop_vector]; |
|
//---initialize-----// |
initial begin |
uOP_rom[0] <= {`type_other,`wb_none,`RRR,`none,`op_none};// iNone_RRR |
uOP_rom[1] <= {`type_other,`wb_rf,`RRR,`int_ALU,`ADD};// iADD_RRR |
uOP_rom[2] <= {`type_other,`wb_rf,`RRI,`int_ALU,`ADD};// iADD_RRI |
uOP_rom[3] <= {`type_other,`wb_rf,`RRR,`int_ALU,`SUB};// iSUB_RRR |
uOP_rom[4] <= {`type_other,`wb_rf,`RRI,`int_ALU,`SUB};// iSUB_RRI |
uOP_rom[5] <= {`type_other,`wb_rf,`RRR,`int_ALU,`ADC};// iADC_RRR |
uOP_rom[6] <= {`type_other,`wb_rf,`RRI,`int_ALU,`ADC};// iADC_RRI |
uOP_rom[7] <= {`type_other,`wb_rf,`RRR,`int_ALU,`SBC};// iSBC_RRR |
uOP_rom[8] <= {`type_other,`wb_rf,`RRI,`int_ALU,`SBC};// iSBC_RRI |
uOP_rom[9] <= {`type_other,`wb_rf,`RRR,`int_ALU,`AND};// iAND_RRR |
uOP_rom[10] <= {`type_other,`wb_rf,`RRI,`int_ALU,`AND};// iAND_RRI |
uOP_rom[11] <= {`type_other,`wb_rf,`RRR,`int_ALU,`OR};// iOR_RRR |
uOP_rom[12] <= {`type_other,`wb_rf,`RRI,`int_ALU,`OR};// iOR_RRI |
uOP_rom[13] <= {`type_other,`wb_rf,`RRR,`int_ALU,`XOR};// iXOR_RRR |
uOP_rom[14] <= {`type_other,`wb_rf,`RRI,`int_ALU,`XOR};// iXOR_RRI |
uOP_rom[15] <= {`type_branch,`wb_rf,`RRR,`int_ALU,`ADD};// iBranch_RRR |
uOP_rom[16] <= {`type_branch,`wb_rf,`RRI,`int_ALU,`ADD};// iBranch_RRI |
uOP_rom[17] <= {`type_branch,`wb_rf,`RI,`int_ALU,`ADD};// iBranch_RI |
uOP_rom[18] <= {`type_load,`wb_rf,`RRR,`int_ALU,`ADD};// iLoad_RRR |
uOP_rom[19] <= {`type_load,`wb_rf,`RRI,`int_ALU,`ADD};// iLoad_RRI |
uOP_rom[20] <= {`type_load,`wb_rf,`RI,`int_ALU,`ADD};// iLoad_RI |
uOP_rom[21] <= {`type_store,`wb_rf,`sRR,`int_ALU,`ADD};// iStore_sRR |
uOP_rom[22] <= {`type_store,`wb_rf,`sRI,`int_ALU,`ADD};// iStore_sRI |
uOP_rom[23] <= {`type_other,`wb_int,`RI,`int_ALU,`ADD};// iAddVector_RI |
uOP_rom[24] <= {`type_other,`wb_uop,`RI,`int_ALU,`ADD};// iAdduOP_RI |
uOP_rom[25] <= {`type_other,`wb_uop,`RRI,`int_ALU,`ADD};// iAdduOP_RRI |
end |
|
always@(posedge Clk) begin |
if (write) begin//write |
uOP_rom[write_vector] <= write_uop; |
end |
end |
endmodule |
/fluid_core_2/trunk/rtl/IF_Stage.v
0,0 → 1,96
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module IF_Stage( |
input Clk, |
input RST, |
input stall, |
input intr, |
input return_back, |
input [0:`pc_w] intr_vector, |
input [0:`inst_w] exInstruction, |
input [0:`pc_w] branch_target, |
input branch, linked, |
inout [0:3] stkFlag, |
output [0:`pc_w] exInstAddr, |
output exInstClk, |
output [0:`IF_ID_reg_w] IF_ID_reg |
); |
|
|
reg [0:`pc_w] PC; |
reg [0:`inst_w] IR; |
reg [0:`pc_w+4] PCStack [0:3]; |
reg [0:1] PCStackPtr; |
reg HLT; |
|
initial begin |
PC <= 0; |
IR <=0; |
PCStackPtr <= 0; |
end |
|
always@ (posedge Clk) begin |
if (RST) begin |
PC <=0; |
IR <= 0; |
PCStackPtr <= 0; |
HLT <= 0; |
end else if (~HLT) begin |
|
if (intr) begin |
PCStack[PCStackPtr] <= {PC,stkFlag}; |
PCStackPtr <= PCStackPtr + 1; |
PC <= intr_vector; |
end else if (branch) begin |
if (linked) begin |
PCStack[PCStackPtr] <= {PC+1,stkFlag}; |
PCStackPtr <= PCStackPtr + 1; |
end |
PC <= branch_target; |
end else if (return_back) begin |
PCStackPtr <= PCStackPtr - 1; |
PC <= PCStack[PCStackPtr-1][0:`pc_w]; |
end else if (~stall) begin |
PC <= PC + 1; |
IR <= exInstruction; |
HLT <= &exInstruction[0:`uop_vector_msb]; |
end |
|
end |
end |
|
assign stkFlag = return_back ? PCStack[PCStackPtr][`pc_w+1:`pc_w+4]:'bz; |
|
assign exInstAddr = PC; |
assign exInstClk = Clk; |
|
assign IF_ID_reg = IR; |
|
endmodule |
/fluid_core_2/trunk/rtl/Programming.v
0,0 → 1,72
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
`define dR0 5'b0000 |
`define dR1 5'b0001 |
`define dR2 5'b0010 |
`define dR3 5'b0011 |
`define dR4 5'b0100 |
`define dR5 5'b0101 |
`define dR6 5'b0110 |
`define dR7 5'b0111 |
|
`define R0 3'b000 |
`define R1 3'b001 |
`define R2 3'b010 |
`define R3 3'b011 |
`define R4 3'b100 |
`define R5 3'b101 |
`define R6 3'b110 |
`define R7 3'b111 |
|
`define iNone_RRR 'd0 |
`define iADD_RRR 'd1 |
`define iADD_RRI 'd2 |
`define iSUB_RRR 'd3 |
`define iSUB_RRI 'd4 |
`define iADC_RRR 'd5 |
`define iADC_RRI 'd6 |
`define iSBC_RRR 'd7 |
`define iSBC_RRI 'd8 |
`define iAND_RRR 'd9 |
`define iAND_RRI 'd10 |
`define iOR_RRR 'd11 |
`define iOR_RRI 'd12 |
`define iXOR_RRR 'd13 |
`define iXOR_RRI 'd14 |
`define iBranch_RRR 'd15 |
`define iBranch_RRI 'd16 |
`define iBranch_RI 'd17 |
`define iLoad_RRR 'd18 |
`define iLoad_RRI 'd19 |
`define iLoad_RI 'd20 |
`define iStore_sRR 'd21 |
`define iStore_sRI 'd22 |
`define iAddVector_RI 'd23 |
`define iAdduOP_RI 'd24 |
`define iAdduOP_RRI 'd25 |
/fluid_core_2/trunk/rtl/Test_Bed.v
0,0 → 1,79
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module Test_Bed( |
input Clk, |
input RST, |
input [0:`intr_msb] Interrupt, |
output [0:`dpw] data, |
output reg [0:`dpw] io_port |
); |
|
wire [0:`inst_w] exInstruction; |
wire [0:`pc_w] exInstAddr; |
wire MemoryClk, MemoryWrite; |
wire [0:`memory_bus_w] MemoryAddr; |
wire [0:`dpw] MemoryData; |
|
assign data = MemoryData; |
|
FluidCore FC_inst( |
.Clk (Clk), |
.RST (RST), |
.Interrupt(Interrupt), |
.exInstruction(exInstruction), |
.exInstAddr(exInstAddr), |
.exMemoryData(MemoryData), |
.exMemoryClk(MemoryClk), |
.exMemoryAddr(MemoryAddr), |
.exMemoryWrite(MemoryWrite) |
); |
|
Inst_Mem Inst_Mem_inst ( |
.Clk (Clk), |
.inst(exInstruction), |
.inst_addr(exInstAddr) |
); |
|
data_mem data_mem_inst( |
.Clk(MemoryClk), |
.mem_addr(MemoryAddr), |
.data(MemoryData), |
.write_en(MemoryWrite), |
.en(~MemoryAddr[0]) |
); |
|
ioPort ioPort_inst( |
.Clk(MemoryClk), |
.en(MemoryAddr[0]), |
.wr(MemoryAddr[3]), |
.rd(~MemoryAddr[3]), |
.fc_data(MemoryData) |
); |
endmodule |
/fluid_core_2/trunk/rtl/WB_Stage.v
0,0 → 1,57
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module WB_Stage( |
input Clk, |
input RST, |
input branch, |
input bubble_free, |
input [0:`MEM_WB_reg_w] MEM_WB_reg, |
output [0:`bc_msb] wb_dst, |
output [0:`dpw] wb_data, |
output write_rf, write_intr, write_uop |
); |
|
wire [0:`type_msb] Type; |
wire [0:`wb_dst_msb] WB_Dest; |
wire [0:`reg_sel_w] Rd; |
wire write; |
|
assign Type = MEM_WB_reg[0:`type_msb]; |
assign WB_Dest = MEM_WB_reg[`type_msb+1:`type_msb+1+`wb_dst_msb]; |
assign Rd = MEM_WB_reg[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+1+`reg_sel_w]; |
|
assign wb_dst = ((Clk) && ((Type==`type_other) || (Type==`type_load))) ? Rd : 'bZ; |
assign wb_data = ((Clk) && ((Type==`type_other) || (Type==`type_load))) ? MEM_WB_reg[`type_msb+1+`wb_dst_msb+1+`reg_sel_w+1:`type_msb+1+`wb_dst_msb+1+`reg_sel_w+1+`dpw]:'bZ; |
assign write = ((Type==`type_other) || (Type==`type_load)) && (branch || bubble_free); |
assign write_rf = (WB_Dest==`wb_rf) && write; |
assign write_intr = (WB_Dest==`wb_int) && write; |
assign write_uop = (WB_Dest==`wb_uop) && write; |
|
endmodule |
/fluid_core_2/trunk/rtl/int_ALU.v
0,0 → 1,76
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module int_ALU( |
input [0:`mod_sel_msb] Module, |
input [0:`operation_msb] Operation, |
input [0:`dpw] OP1, |
input [0:`dpw] OP2, |
output [0:`dpw] Result, |
output [0:3] Flag, |
input [0:3] prev_Flag |
); |
|
wire en; |
assign en = (Module==`int_ALU); |
|
wire [0:`dpw] OP1_; |
assign OP1_ = (~OP1 + `dpw'b01); |
|
reg [0:`dpw] result_buff; |
reg C,Z,S,O; |
//----[C|Z|S|O]------// |
|
initial begin |
{C,Z,S,O} = {0,0,0,0}; |
result_buff = 0; |
end |
always@(*) begin |
|
if (en) begin |
case (Operation) |
`ADD: {C,result_buff} <= OP1 + OP2; |
`SUB: {C,result_buff} <= OP2 + OP1_; |
`ADC: {C,result_buff} <= OP1 + OP2 + prev_Flag[0]; |
`SBC: {C,result_buff} <= OP2 + OP1_ + prev_Flag[0]; |
`AND: result_buff <= OP1 & OP2; |
`OR: result_buff <= OP1 | OP2; |
`XOR: result_buff <= OP1 ^ OP2; |
endcase |
|
S <= result_buff[0]; |
O <= OP1_[0]^OP2[0]^result_buff[0]^C; |
Z <= result_buff == 0; |
|
end |
end |
|
assign Result = en ? result_buff : 'bz; |
assign Flag = {C,Z,S,O}; |
endmodule |
/fluid_core_2/trunk/rtl/interrupt_unit.v
0,0 → 1,80
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module interrupt_unit( |
input Clk, |
input [0:`intr_msb] intr_req, |
input [0:log2(`intr_msb)] intr_inx, |
input [0:`pc_w] new_vector, |
input write, return_back, |
output intr, |
output [0:`pc_w] vector |
); |
|
reg [0:`pc_w] isr_vectors [0:`intr_msb+1]; |
reg [0:`intr_msb] masks; |
reg temp_unblock; |
reg [0:log2(`intr_msb)-1] vctr_inx; |
|
integer i; |
always@(*) begin |
for ( i = `intr_msb; (i >= 0); i = i - 1) begin |
if (intr_req[i] == 1) begin |
vctr_inx <= i; |
end |
end |
end |
initial begin |
temp_unblock <= 1; |
end |
assign intr = |(masks & intr_req ) & temp_unblock; //(~(vctr_inx == 0)&&(masks[vctr_inx])); |
assign vector = intr ? isr_vectors[vctr_inx]:'bz; |
|
always@(posedge Clk) begin |
if (write) begin//write |
if (intr_inx == 0) masks <= new_vector; //(aligned by MSB) |
else begin |
isr_vectors[intr_inx] <= new_vector; |
end |
end |
if (intr) temp_unblock <= 0; |
else if (return_back) temp_unblock <= 1; |
end |
|
|
//--- Constant Function ----// |
function integer log2; |
input integer value; |
begin |
value = value-1; |
for (log2=0; value>0; log2=log2+1) |
value = value>>1; |
end |
endfunction |
endmodule |
/fluid_core_2/trunk/rtl/P_Reg.v
0,0 → 1,61
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module P_Reg( |
Clk, |
RST, |
bubble, |
stall, |
prev_stage, |
next_stage |
); |
|
parameter p_reg_w = 7; |
|
input Clk, RST, bubble, stall; |
input [0:p_reg_w] prev_stage; |
output [0:p_reg_w] next_stage; |
|
wire zero, Clk_RST; |
assign Clk_RST = Clk || RST; |
assign zero = RST || ~bubble; |
|
reg [0:p_reg_w] pipeline_register; |
|
|
always@(posedge Clk_RST) begin |
if (zero) begin |
pipeline_register <=0; |
end else begin |
if (~stall) pipeline_register <= prev_stage; |
end |
end |
|
assign next_stage = pipeline_register; |
endmodule |
/fluid_core_2/trunk/rtl/EX_Stage.v
0,0 → 1,100
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module EX_Stage( |
input Clk, |
input RST, |
inout [0:3] stkFlag, |
input ret, |
input [0:`ID_EX_reg_w] ID_EX_reg, |
output [0:`EX_MEM_reg_w] EX_MEM_reg, |
input [0:`dpw] b_EX_MEM_reg, b_MEM_WB_reg |
); |
|
reg [0:`dpw] bb_MEM_WB_reg; |
wire [0:`type_msb] Type; |
wire [0:`wb_dst_msb] WB_Dest; |
wire [0:`bc_msb] Rd_BC; |
wire [0:`operation_msb] Operation; |
wire [0:`mod_sel_msb] Module; |
wire [0:`dpw] OP1, OP2, OP3, E0, E1; |
wire [0:3] Flag, aluFlag; |
reg [0:3] prev_Flag; |
wire [0:1] reg_src_A, reg_src_B, st_src; |
wire [0:2] load_hazard_abs; |
|
assign Type = ID_EX_reg[0:`type_msb]; |
assign WB_Dest = ID_EX_reg[`type_msb+1:`type_msb+1+`wb_dst_msb]; |
|
assign Module = ID_EX_reg[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb]; |
assign Operation = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb]; |
|
assign Rd_BC = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb]; |
|
assign OP1 = (reg_src_A[0] & load_hazard_abs[0]) | (reg_src_A[1] & ~load_hazard_abs[0]) ? b_MEM_WB_reg : (reg_src_A[0] & ~load_hazard_abs[0]) ? b_EX_MEM_reg : (reg_src_A[1] & load_hazard_abs[0]) ? bb_MEM_WB_reg : ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3+`dpw]; |
assign OP2 = (reg_src_B[0] & load_hazard_abs[1]) | (reg_src_B[1] & ~load_hazard_abs[1]) ? b_MEM_WB_reg : (reg_src_B[0] & ~load_hazard_abs[1]) ? b_EX_MEM_reg : (reg_src_B[1] & load_hazard_abs[1]) ? bb_MEM_WB_reg : ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2+`dpw]; |
|
// assign OP1 = reg_src_A[0] ? b_EX_MEM_reg : reg_src_A[1] ? load_hazard_abs[0] ? bb_MEM_WB_reg : b_MEM_WB_reg : ID_EX_reg[`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3:`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+`dpw+3+`dpw]; |
// assign OP2 = reg_src_B[0] ? b_EX_MEM_reg : reg_src_B[1] ? load_hazard_abs[1] ? bb_MEM_WB_reg : b_MEM_WB_reg : ID_EX_reg[`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2:`type_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+`dpw+2+`dpw]; |
|
assign reg_src_A = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+3:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+4]; |
assign reg_src_B = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+5:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+6]; |
assign st_src = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+7:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+8]; |
assign load_hazard_abs = ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+9:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+11]; |
|
//----Sub Modules----// |
int_ALU int_ALU_inst( |
.Module(Module), |
.Operation(Operation), |
.OP1(OP1), |
.OP2(OP2), |
.Result(E1), |
.Flag(aluFlag), |
.prev_Flag(prev_Flag) |
); |
|
Shifter barrel_shifter_inst( |
.Module(Module), |
.Operation(Operation), |
.OP1(OP1), |
.OP2(OP2), |
.Result(E1) |
); |
assign Flag = ret ? stkFlag : aluFlag; |
assign stkFlag = ~ret ? Flag : 'bz; |
|
always@(posedge Clk) begin |
prev_Flag <= Flag; |
bb_MEM_WB_reg <= b_MEM_WB_reg; //store previous MEM_WB_reg coz we can't read it back from RF |
end |
|
assign E0 = (Type==`type_store) ? st_src[0] ? b_EX_MEM_reg : st_src[1] ? load_hazard_abs[2] ? bb_MEM_WB_reg : b_MEM_WB_reg : ID_EX_reg[`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1:`type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw] : (Type==`type_other) ? Flag : (Type==`type_branch) ? prev_Flag : 'bZ ; |
|
assign EX_MEM_reg = {Type,WB_Dest,Rd_BC,E0,E1}; |
endmodule |
/fluid_core_2/trunk/rtl/MEM_Stage.v
0,0 → 1,103
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
|
module MEM_Stage( |
input Clk, |
input RST, |
input [0:`EX_MEM_reg_w] EX_MEM_reg, |
output [0:`MEM_WB_reg_w] MEM_WB_reg, |
output [0:`memory_bus_w] ex_mem_addr, |
inout [0:`dpw] ex_mem_data, |
output mem_Clk, |
output mem_wr, |
output branch, linked, |
output return_back, |
output [0:`pc_w] branch_target |
); |
|
wire [0:`type_msb] Type; |
wire [0:`wb_dst_msb] WB_Dest; |
wire [0:`bc_msb] Rd_BC; |
wire [0:`dpw] E1, E0, M0; |
wire C,Z,S,O; |
|
assign Type = EX_MEM_reg[0:`type_msb]; |
assign WB_Dest = EX_MEM_reg[`type_msb+1:`type_msb+1+`wb_dst_msb]; |
assign Rd_BC = EX_MEM_reg[`type_msb+1+`wb_dst_msb+1:`type_msb+1+`wb_dst_msb+1+`bc_msb]; |
assign E0 = EX_MEM_reg[`type_msb+1+`wb_dst_msb+1+`bc_msb+1:`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw]; |
assign E1 = EX_MEM_reg[`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+1:`type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+1+`dpw]; |
assign {C,Z,S,O} = E0[`dpw+1-4:`dpw]; |
|
assign ex_mem_addr = E1; |
|
assign mem_wr = (Type==`type_store) ? 1: 0; |
assign ex_mem_data = (Type==`type_store) ? E0 : 'bZ; |
assign M0 = (Type==`type_load) ? ex_mem_data : E1; |
|
assign mem_Clk = ((Type==`type_load) || (Type==`type_store)) ? ~Clk : 'bZ; |
|
|
//--branch logic--// |
reg bc, ret; |
always@(*) begin |
if (Type==`type_branch) begin |
case (Rd_BC[1:`bc_msb]) |
`bLT: bc <= S^O; |
`bLE: bc <= Z + (S^O); |
`bNEG: bc <= S; |
`bPOS: bc <= ~S; |
`bEQ: bc <= Z; |
`bNEQ: bc <= ~Z; |
`bGE: bc <= ~(S^O); |
`bGT: bc <= ~(Z+(S^O)); |
`bLTU: bc <= C; |
`bLEU: bc <= C + Z; |
`bGTU: bc <= ~(C+Z); |
`bGEU: bc <= ~C; |
`bOVF: bc <= O; |
`bNOVF: bc <= ~O; |
`bALL: bc <= 1; |
`bRET: begin |
bc <= 1; |
ret <= 1; |
end |
endcase |
end else begin |
bc <= 0; |
ret <= 0; |
end |
end |
assign branch = (Type==`type_branch) & bc & ~ret; |
assign linked = Rd_BC[0]; |
assign return_back = ret; |
assign branch_target = (Type==`type_branch) ? E1:'bZ; |
|
assign MEM_WB_reg = {Type,WB_Dest, Rd_BC[2:`bc_msb], M0}; |
|
endmodule |
/fluid_core_2/trunk/rtl/Reg_Hist.v
0,0 → 1,108
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
module Reg_Hist( |
// input Clk, RST, |
input [0:`reg_sel_w] ID_EX_reg, EX_MEM_reg, |
input [0:`reg_sel_w] nxt_reg_A, nxt_reg_B, st_reg, |
output [0:1] reg_src_A, reg_src_B, st_src, |
output [0:2] load_hazard_abs, |
output load_hazard, |
input rrr_adm, rri_adm, ID_EX_load, fw_c_1, fw_c_2 |
); |
|
|
// //pure combinational |
wire reg_src_a_1, reg_src_a_2, reg_src_b_1, reg_src_b_2; |
//store hazards |
wire st_src_1, st_src_2; |
|
//assign rrr_adm = (~(|(adm ^ `RRR))); |
// assign not_branch = (|(type ^ `type_branch)); |
// assign not_ID_EX_branch = (|(ID_EX_type ^ `type_branch)); |
// assign not_EX_MEM_branch = (|(EX_MEM_type ^ `type_branch)); |
assign load_hazard = (reg_src_a_1 | reg_src_b_1 | st_src_1) & ID_EX_load;//~(|(ID_EX_type ^ `type_load)); |
//WORK HERE WORK HERE --- below --- below |
assign reg_src_a_1 = (rrr_adm & fw_c_1 & (~(|(nxt_reg_A ^ ID_EX_reg))));// |
assign reg_src_a_2 = (rrr_adm & fw_c_2 & (~(|(nxt_reg_A ^ EX_MEM_reg))));// |
assign reg_src_b_1 = ((rrr_adm | rri_adm) & fw_c_1 & (~(|(nxt_reg_B ^ ID_EX_reg)))); |
assign reg_src_b_2 = ((rrr_adm | rri_adm) & fw_c_2 & (~(|(nxt_reg_B ^ EX_MEM_reg)))); |
assign st_src_1 = (fw_c_1 & (~(|(st_reg ^ ID_EX_reg)))); |
assign st_src_2 = (fw_c_2 & (~(|(st_reg ^ EX_MEM_reg)))); |
|
assign reg_src_A = {reg_src_a_1,reg_src_a_2};//load_hazard_abs[0] ? 2'b01 : |
assign reg_src_B = {reg_src_b_1,reg_src_b_2};//load_hazard_abs[1] ? 2'b01 : |
assign st_src = load_hazard_abs[2] ? 2'b01 : {st_src_1,st_src_2}; |
assign load_hazard_abs = {load_hazard & reg_src_a_1,load_hazard & reg_src_b_1,load_hazard & st_src_1}; |
|
// always@(Clk) begin |
// if (|(type ^ `type_branch)) begin |
// if ((|(ID_EX_type ^ `type_branch))&(~(|(nxt_reg_A ^ ID_EX_reg)))) reg_src_A <= 2'b01; |
// else if ((|(ID_EX_type ^ `type_branch))&(~(|(nxt_reg_A ^ EX_MEM_reg)))) reg_src_A <= 2'b10; |
// else reg_src_A <= 2'b00; |
// |
// if ((|(EX_MEM_type ^ `type_branch))&(~(|(nxt_reg_B ^ ID_EX_reg)))) reg_src_B <= 2'b01; |
// else if ((|(EX_MEM_type ^ `type_branch))&(~(|(nxt_reg_B ^ EX_MEM_reg)))) reg_src_B <= 2'b10; |
// else reg_src_B <= 2'b00; |
// end else begin |
// reg_src_A <= 2'b00; |
// reg_src_B <= 2'b00; |
// end |
// end |
|
|
// wire Clk_RST; |
// assign Clk_RST = Clk || RST; |
// reg stall_reg; |
// |
// initial begin |
// stall_reg <= 0; |
// end |
// always@(posedge Clk_RST) begin |
// if (RST) begin |
// bubble_reg <= 9'b111100000; |
// end else begin |
// if (bubble) begin |
// bubble_reg <= 9'b111100000; |
// end else begin |
// bubble_reg <= {1,bubble_reg[0:7]}; |
// end |
// |
// if (~stall_reg) begin |
// if (load_hazard) begin |
// stall_reg <= 1; |
// end else begin |
// stall_reg <= 0; |
// end |
// end else begin |
// stall_reg <= 0; |
// end |
// end |
// |
// assign stall = stall_reg; |
endmodule |
/fluid_core_2/trunk/rtl/Shifter.v
0,0 → 1,53
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
`define sh_left 3'b001 |
`define sh_right 3'b010 |
|
module Shifter( |
input [0:`mod_sel_msb] Module, |
input [0:`operation_msb] Operation, |
input [0:`dpw] OP1, OP2, |
output [0:`dpw] Result |
); |
|
reg [0:`dpw] Result_buff; |
wire en; |
assign en = (Module==`barrel_Shifter); |
|
always@(*) begin |
case(Operation) |
`sh_left: Result_buff <= OP1<<OP2; |
`sh_right: Result_buff <= OP1>>OP2; |
endcase |
end |
|
assign Result = en ? Result_buff : 'bz; |
|
|
endmodule |
/fluid_core_2/trunk/rtl/Staller.v
0,0 → 1,74
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
module Staller( |
input Clk, |
input RST, |
input bubble, |
input load_hazard, |
output stall, |
output [0:4] bubble_lines |
); |
|
reg [0:8] bubble_reg; |
reg stall_reg; |
|
initial begin |
stall_reg <= 0; |
end |
|
wire Clk_RST; |
assign Clk_RST = Clk || RST; |
|
always@(posedge Clk_RST) begin |
if (RST) begin |
bubble_reg <= 9'b111100000; |
end else begin |
if (bubble) begin |
bubble_reg <= 9'b111100000; |
end else begin |
bubble_reg <= {1,bubble_reg[0:7]}; |
end |
|
if (~stall_reg) begin |
if (load_hazard) begin |
stall_reg <= 1; |
end else begin |
stall_reg <= 0; |
end |
end else begin |
stall_reg <= 0; |
end |
end |
end |
|
|
|
assign bubble_lines = bubble_reg[4:8]; |
assign stall = stall_reg; |
endmodule |
/fluid_core_2/trunk/rtl/Configuration.v
0,0 → 1,140
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
/*----------NOTES---------------/ |
1. All numerical values are counted from 0 |
|
*/ |
|
`ifndef dpw |
//----Processor Interface------// |
`define dpw 31 // -- Datapath Width -- // |
`define inst_w 15 // -- Instruction Width -- // |
`define pc_w 5 // -- Program Counter Width i.e. Instruction Memory Space -- // |
`define memory_bus_w 3 // -- Memory Bus Width i.e. Data Memory Space -- // |
`define intr_msb 3 // -- Interrupt Bus i.e. No. of Ext Interrupts to support -- // |
|
|
`define reg_n 7 // -- Number of Registers -- // |
`define reg_sel_w 2 // -- Register Address Width -- // |
|
//------ISA Specifics----------// |
`define uop_vector_msb 4 |
`define uop_msb 12 // -- Type|WB_Destination|ADM|Module_Sel|Operation -- [2|2|4|2|3] -- // |
`define uop_n 25 |
`define type_msb 1 |
`define wb_dst_msb 1 |
`define mod_sel_msb 1 |
`define operation_msb 2 |
`define bc_msb 4 |
|
|
|
|
//-----Pipeline Registers-----// |
`define IF_ID_reg_w `inst_w |
`define ID_EX_reg_w `type_msb+1+`wb_dst_msb+1+`mod_sel_msb+1+`operation_msb+1+`bc_msb+1+`dpw+`dpw+`dpw+2+6+3 //55 //Type + Mod_Sel + Operation + reg_sel_w + (dpw x 3) + (2 bit reg_src x 3) + (3 bit load_hazard_a/b/s) |
`define EX_MEM_reg_w `type_msb+1+`wb_dst_msb+1+`bc_msb+1+`dpw+`dpw+1 |
`define MEM_WB_reg_w `type_msb+1+`wb_dst_msb+1+`reg_sel_w+1+`dpw |
|
/******************************************************************************** |
//---------------------------------MicroOp Store-------------------------------// |
********************************************************************************/ |
|
//------Module Identifiers-------// |
`define int_ALU 2'b01 |
`define barrel_Shifter 2'b10 |
|
//------Empty Instructions----// |
`define none 2'b00 |
`define op_none 3'b000 |
|
//---ALU Operations---// |
`define ADD 3'b001 |
`define SUB 3'b010 |
`define ADC 3'b011 |
`define SBC 3'b100 |
`define AND 3'b101 |
`define OR 3'b110 |
`define XOR 3'b111 |
|
//---Branch Conditions---// |
`define bLT 4'd1 |
`define bLE 4'd2 |
|
`define bEQ 4'd3 |
`define bZ 4'd3 |
`define bNEQ 4'd4 |
`define bNZ 4'd4 |
|
`define bGE 4'd5 |
`define bGT 4'd6 |
|
`define bLTU 4'd7 |
`define bCRY 4'd7 |
|
`define bLEU 4'd8 |
|
`define bGEU 4'd9 |
`define bNCRY 4'd9 |
|
`define bGTU 4'd10 |
`define bNEG 4'd11 |
`define bPOS 4'd12 |
|
`define bOVF 4'd13 |
`define bNOVF 4'd14 |
|
`define bALL 4'd0 |
|
`define bRET 5'd15 |
|
`define lnk 1'b1 |
`define ulnk 1'b0 |
|
//----Declarations for easing readability of Micro_Ops------// |
`define type_other 2'b00 |
`define type_load 2'b01 |
`define type_store 2'b10 |
`define type_branch 2'b11 //never make this 00, conflict in reg_history |
|
//----S0,S1,S2,Imm---// |
`define RRR 4'b0111 |
`define RRI 4'b0100 |
`define RI 4'b0001 |
`define sRR 4'b1100 |
`define sRI 4'b1001 |
|
//---- Write Back Destination ----// |
`define wb_rf 2'b00 |
`define wb_uop 2'b01 |
`define wb_int 2'b10 |
`define wb_none 2'b11 |
|
// ---- Constant Functions ---- // |
|
`endif |
/fluid_core_2/trunk/rtl/data_mem.v
0,0 → 1,63
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2014-2015 Azmath Moosa //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 3 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
`include "Configuration.v" |
module data_mem( |
input [0:`memory_bus_w] mem_addr, |
input Clk, |
input write_en, en, |
inout [0:`dpw] data |
); |
|
reg [0:`dpw] data_bank [0:9]; |
reg [0:`dpw] data_buff; |
|
initial begin |
data_bank[0] <= `dpw'd1; |
data_bank[1] <= `dpw'd5; |
data_bank[2] <= {19'd0,`type_other,`wb_rf,`RRR,`barrel_Shifter,3'b001}; |
data_bank[3] <= `dpw'd15; |
data_bank[4] <= `dpw'd25; |
data_bank[5] <= `dpw'd35; |
data_bank[6] <= `dpw'd45; |
data_bank[7] <= `dpw'd55; |
data_bank[8] <= `dpw'd85; |
data_bank[9] <= `dpw'd95; |
end |
|
always@(posedge Clk) begin |
if (en) begin |
if (write_en) begin |
data_bank[mem_addr] <= data; |
end else begin |
data_buff <= data_bank[mem_addr]; |
end |
end |
end |
|
assign data = en ? write_en ? 'bZ: data_buff:'bZ; |
endmodule |