URL
https://opencores.org/ocsvn/gigabit_udp_mac/gigabit_udp_mac/trunk
Subversion Repositories gigabit_udp_mac
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/gigabit_udp_mac/trunk/LAN/UDP_KED/ARP.vhd
0,0 → 1,892
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
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library work; |
use work.signal_Package.all; |
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entity ARP is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900"; --20S |
g_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector(31 downto 0):= x"07735940"; --1S |
g_RE_SEND_ARP_REQUEST : std_logic_vector(3 downto 0):= x"A" --10 |
); |
port( |
-- system signals |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
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--for ARP Data |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
i_our_mac_addr : in std_logic_vector (47 downto 0); |
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-- to/from IP Layer |
i_fpga_req : in std_logic; |
i_lookup_ip : in std_logic_vector (31 downto 0); |
o_lookup_mac_addr : out std_logic_vector (47 downto 0); |
o_lookup_mac_got : out std_logic; |
o_lookup_mac_err : out std_logic; |
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--ARP_RX Input |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
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--ARP_TX Input/Output |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0); |
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-- Error Out |
o_arp_rx_err_out : out std_logic_vector (3 downto 0) |
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); |
end ARP; |
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architecture Behavioral of ARP is |
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--=========================== ARP_RX ==================================================== |
component ARP_RX is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900" --20S |
); |
port ( |
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-- system signals |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
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-- MAC layer RX inputs |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
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-- Outputs to ARP |
o_ip_addr0 : out std_logic_vector(31 downto 0); |
o_mac_addr0 : out std_logic_vector(47 downto 0); |
o_addr_valid0 : out std_logic; |
o_pc_reply : out std_logic; |
o_pc_req : out std_logic; |
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-- Error Out |
o_arp_rx_err_out : out std_logic_vector (3 downto 0) |
); |
end component; |
--======================================================================================== |
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--================================= ARP_TX ================================================ |
component ARP_TX is |
port ( |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
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--for ARP Data |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
i_our_mac_addr : in std_logic_vector (47 downto 0); |
i_dst_ip_addr_pc : in std_logic_vector (31 downto 0); |
i_dst_mac_addr_pc : in std_logic_vector (47 downto 0); |
i_dst_ip_addr_lookup : in std_logic_vector (31 downto 0); |
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--ARP Request's |
i_fpga_req : in std_logic; |
i_pc_req : in std_logic; |
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-- for transfer data to mac layer |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0) |
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); |
end component; |
--======================================================================================== |
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--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--============================= Top Signals ============================================================ |
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--signal s_udp_tx_data_len : std_logic_vector (15 downto 0):= c_PACKET_LENGTH; --1472 (Maximum Application Layer Packet Length) |
--signal s_udp_tx_start : std_logic:='0'; |
--signal s_udp_tx_ready : std_logic; |
--signal s_udp_tx_din : std_logic_vector (7 downto 0); |
-- |
--signal s_udp_rx_dout : std_logic_vector(7 downto 0); |
--signal s_udp_rx_dout_rdy : std_logic; |
--signal s_udp_rx_dout_last : std_logic; |
-- |
--signal s_udp_rx_src_ip : std_logic_vector(31 downto 0); |
--signal s_udp_rx_src_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_dst_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_data_len : std_logic_vector(15 downto 0); |
--signal s_udp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_udp_tx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_arp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_ip_rx_dst_ip_top : std_logic_vector(31 downto 0); |
--signal s_ip_rx_err_out_top : std_logic_vector (3 downto 0); |
--signal s_ip_tx_err_out_top : std_logic_vector (3 downto 0); |
-- |
-- |
--signal s_rx_clk_out : std_logic; |
--signal s_buff_rx_clk_out : std_logic; |
--signal s_tx_clk_out : std_logic; |
--signal s_buff_tx_clk_out : std_logic; |
--signal s_clk_125 : std_logic; |
--signal s_clk_100 : std_logic; |
--signal s_clk_m : std_logic; |
-- |
----chip scope |
--signal s_control : std_logic_vector (35 downto 0); |
--signal s_data_log : std_logic_vector (15 downto 0); |
-- |
-- |
----for transmit data |
--signal s_data_test_val : std_logic:='0'; |
--signal s_data_test_last : std_logic:='0'; |
--signal s_data_test : std_logic_vector (7 downto 0):=(others=>'0'); |
--signal s_cnt2 : std_logic_vector (15 downto 0):=(others=>'0'); |
--signal s_global_reset : std_logic:='1'; |
-- |
-- |
-- |
--signal s_gmii_txd : std_logic_vector(7 downto 0); |
--signal s_gmii_tx_en : std_logic; |
--signal s_gmii_tx_er : std_logic; |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
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--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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begin |
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--=============== Wait for ARP Requests and so Reply them ===================================== |
p_arp_control:process(i_tx_clk) |
begin |
if rising_edge(i_tx_clk) then |
s_pc_req_tx <= '0'; |
s_fpga_req_tx <= '0'; |
o_lookup_mac_got <= '0'; |
o_lookup_mac_err <= '0'; |
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if (i_reset= '1') then |
s_fpga_req_tx <= '0'; |
s_pc_req_tx <= '0'; |
s_dst_ip_addr_pc <= (others=>'0'); |
s_dst_mac_addr_pc <= (others=>'0'); |
s_dst_ip_addr_lookup <= (others=>'0'); |
s_timeout_wait_reply_cnt <= (others=>'0'); |
s_error_cnt <= (others=>'0'); |
st_ARP_STATE <= IDLE; |
else |
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CASE st_ARP_STATE IS |
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WHEN IDLE => |
s_timeout_wait_reply_cnt <= (others=>'0'); |
s_error_cnt <= (others=>'0'); |
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if (s_pc_req_rx='1') then |
s_pc_req_tx <= '1'; |
s_dst_ip_addr_pc <= s_ip_addr0; |
s_dst_mac_addr_pc <= s_mac_addr0; |
end if; |
if(i_fpga_req='1') then |
s_pc_req_tx <='0'; |
st_ARP_STATE <= LOOK_UP; |
end if; |
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WHEN LOOK_UP => |
s_fpga_req_tx <= '1'; |
s_dst_ip_addr_lookup <= i_lookup_ip; |
st_ARP_STATE <= WAIT_PC_REPLY; |
s_error_cnt <= s_error_cnt+1; |
if ((s_addr_valid0='1') and (s_ip_addr0=i_lookup_ip)) then |
o_lookup_mac_addr <= s_mac_addr0; |
o_lookup_mac_got <= '1'; |
s_fpga_req_tx <= '0'; |
s_error_cnt <= (others=>'0'); |
st_ARP_STATE <= IDLE; |
end if; |
if (s_error_cnt = g_RE_SEND_ARP_REQUEST) then |
s_fpga_req_tx <= '0'; |
s_error_cnt <= (others=>'0'); |
o_lookup_mac_err <= '1'; |
st_ARP_STATE <= IDLE; |
end if; |
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WHEN WAIT_PC_REPLY => |
s_timeout_wait_reply_cnt <= s_timeout_wait_reply_cnt+1; |
if (s_pc_reply_rx='1') then |
s_timeout_wait_reply_cnt <= (others=>'0'); |
st_ARP_STATE <= LOOK_UP; |
end if; |
if (s_timeout_wait_reply_cnt=g_TIME_OUT_WAIT_FOR_ARP_REPLY) then -- 1 second time_out |
s_timeout_wait_reply_cnt <= (others=>'0'); |
st_ARP_STATE <= LOOK_UP; |
end if; |
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END CASE; |
end if; |
end if; |
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end process p_arp_control; |
--================================================================================================ |
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--============================= ARP_RX =========================================================== |
inst_ARP_RX: ARP_RX |
generic map ( |
g_TIME_OUT_LOOKUP_TABLE_ARP => g_TIME_OUT_LOOKUP_TABLE_ARP |
) |
port map ( |
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-- system signals |
i_rx_clk => i_rx_clk, |
i_tx_clk => i_tx_clk, |
i_reset => i_reset, |
i_our_ip_addr => i_our_ip_addr, |
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-- MAC layer RX inputs |
i_mac_data_in => i_mac_data_in, |
i_mac_data_in_valid => i_mac_data_in_valid, |
i_mac_data_in_last => i_mac_data_in_last, |
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-- Outputs to ARP |
o_ip_addr0 => s_ip_addr0, |
o_mac_addr0 => s_mac_addr0, |
o_addr_valid0 => s_addr_valid0, |
o_pc_reply => s_pc_reply_rx, |
o_pc_req => s_pc_req_rx, |
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-- Error Out |
o_arp_rx_err_out => o_arp_rx_err_out |
); |
--================================================================================================ |
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--================================== ARP_TX ====================================================== |
inst_ARP_TX: ARP_TX |
port map ( |
i_tx_clk => i_tx_clk, |
i_reset => i_reset, |
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--for ARP Data |
i_our_ip_addr => i_our_ip_addr, |
i_our_mac_addr => i_our_mac_addr, |
i_dst_ip_addr_pc => s_dst_ip_addr_pc, |
i_dst_mac_addr_pc => s_dst_mac_addr_pc, |
i_dst_ip_addr_lookup => s_dst_ip_addr_lookup, |
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--ARP Request's |
i_fpga_req => s_fpga_req_tx, |
i_pc_req => s_pc_req_tx, |
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-- for transfer data to mac layer |
o_mac_tx_req => o_mac_tx_req, |
i_mac_tx_granted => i_mac_tx_granted, |
i_mac_tready => i_mac_tready, |
o_mac_tvalid => o_mac_tvalid, |
o_mac_tlast => o_mac_tlast, |
o_mac_tdata => o_mac_tdata |
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); |
--================================================================================================ |
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end Behavioral; |
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/gigabit_udp_mac/trunk/LAN/UDP_KED/ARP_Lookup_table.vhd
0,0 → 1,703
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
|
library work; |
use work.signal_Package.all; |
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entity ARP_Lookup_table is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900" --20S |
); |
port ( |
-- system signals |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
|
-- Data in |
i_mac_addr_in : in std_logic_vector(47 downto 0); |
i_ip_addr_in : in std_logic_vector(31 downto 0); |
i_addr_valid_in : in std_logic; |
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i_request_in : in std_logic; |
i_reqly_in : in std_logic; |
i_trans_data_in : in std_logic; |
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-- Data out |
o_mac_addr_out : out std_logic_vector(47 downto 0); |
o_ip_addr_out : out std_logic_vector(31 downto 0); |
o_addr_valid_out : out std_logic; |
o_request_out : out std_logic; |
o_reply_out : out std_logic |
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); |
end ARP_Lookup_table; |
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architecture Behavioral of ARP_Lookup_table is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--============================= Top Signals ============================================================ |
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--signal s_udp_tx_data_len : std_logic_vector (15 downto 0):= c_PACKET_LENGTH; --1472 (Maximum Application Layer Packet Length) |
--signal s_udp_tx_start : std_logic:='0'; |
--signal s_udp_tx_ready : std_logic; |
--signal s_udp_tx_din : std_logic_vector (7 downto 0); |
-- |
--signal s_udp_rx_dout : std_logic_vector(7 downto 0); |
--signal s_udp_rx_dout_rdy : std_logic; |
--signal s_udp_rx_dout_last : std_logic; |
-- |
--signal s_udp_rx_src_ip : std_logic_vector(31 downto 0); |
--signal s_udp_rx_src_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_dst_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_data_len : std_logic_vector(15 downto 0); |
--signal s_udp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_udp_tx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_arp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_ip_rx_dst_ip_top : std_logic_vector(31 downto 0); |
--signal s_ip_rx_err_out_top : std_logic_vector (3 downto 0); |
--signal s_ip_tx_err_out_top : std_logic_vector (3 downto 0); |
-- |
-- |
--signal s_rx_clk_out : std_logic; |
--signal s_buff_rx_clk_out : std_logic; |
--signal s_tx_clk_out : std_logic; |
--signal s_buff_tx_clk_out : std_logic; |
--signal s_clk_125 : std_logic; |
--signal s_clk_100 : std_logic; |
--signal s_clk_m : std_logic; |
-- |
----chip scope |
--signal s_control : std_logic_vector (35 downto 0); |
--signal s_data_log : std_logic_vector (15 downto 0); |
-- |
-- |
----for transmit data |
--signal s_data_test_val : std_logic:='0'; |
--signal s_data_test_last : std_logic:='0'; |
--signal s_data_test : std_logic_vector (7 downto 0):=(others=>'0'); |
--signal s_cnt2 : std_logic_vector (15 downto 0):=(others=>'0'); |
--signal s_global_reset : std_logic:='1'; |
-- |
-- |
-- |
--signal s_gmii_txd : std_logic_vector(7 downto 0); |
--signal s_gmii_tx_en : std_logic; |
--signal s_gmii_tx_er : std_logic; |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
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--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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--=========Sync Fifo for Convert RX_CLK Domain Signals to TX_CLK Domain Signals=============== |
component arp_sync_fifo |
port |
( |
rst : IN STD_LOGIC; |
wr_clk : IN STD_LOGIC; |
wr_en : IN STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(82 DOWNTO 0); |
rd_clk : IN STD_LOGIC; |
rd_en : IN STD_LOGIC; |
dout : OUT STD_LOGIC_VECTOR(82 DOWNTO 0); |
valid : OUT STD_LOGIC; |
full : OUT STD_LOGIC; |
empty : OUT STD_LOGIC |
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); |
end component; |
--============================================================================================ |
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begin |
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s_notempty <= not(s_empty); |
s_din <= (i_reqly_in & i_request_in & i_addr_valid_in & i_ip_addr_in & i_mac_addr_in); |
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s_mac_addr_out <= s_dout(47 downto 0); |
s_ip_addr_out <= s_dout(79 downto 48); |
s_addr_valid_out <= s_dout(80); |
s_request_out <= s_dout(81); |
s_reply_out <= s_dout(82); |
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--================== Process for Update and Timeout Arp Lookup Table ============================ |
p_update_arp_lookup:process(i_tx_clk) |
begin |
if rising_edge(i_tx_clk) then |
if (i_reset = '1' ) then |
s_timeout_lookup_table_cnt <= (others=>'0'); |
o_addr_valid_out <= '0'; |
else |
s_timeout_lookup_table_cnt <= s_timeout_lookup_table_cnt+1; |
if (s_valid = '1') then |
s_timeout_lookup_table_cnt <= (others=>'0'); |
o_addr_valid_out <= s_addr_valid_out; |
o_mac_addr_out <= s_mac_addr_out; |
o_ip_addr_out <= s_ip_addr_out; |
elsif (s_timeout_lookup_table_cnt = g_TIME_OUT_LOOKUP_TABLE_ARP) then --20s time out |
s_timeout_lookup_table_cnt <= (others=>'0'); |
o_addr_valid_out <= '0'; |
end if; |
end if; |
end if; |
end process p_update_arp_lookup; |
--=============================================================================================== |
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--==================== Process for deliver ARP Requests to ARP_RX Module ======================== |
p_Synchronous:process(i_tx_clk) |
begin |
if rising_edge(i_tx_clk) then |
if (i_reset = '1' ) then |
o_request_out <= '0'; |
o_reply_out <= '0'; |
else |
o_request_out <= '0'; |
o_reply_out <= '0'; |
if (s_valid = '1') then |
o_request_out <=s_request_out; |
o_reply_out <=s_reply_out; |
end if; |
end if; |
end if; |
end process p_Synchronous; |
--=============================================================================================== |
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--=========Sync Fifo for Convert RX_CLK Domain Signals to TX_CLK Domain Signals ================= |
inst_arp_sync_fifo1:arp_sync_fifo |
port map |
( |
rst => i_reset, |
wr_clk => i_rx_clk, |
wr_en => i_trans_data_in, |
din => s_din, |
rd_clk => i_tx_clk, |
rd_en => s_notempty, |
dout => s_dout, |
valid => s_valid, |
full => open, |
empty => s_empty |
); |
--=============================================================================================== |
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end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/ARP_RX.vhd
0,0 → 1,906
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
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library work; |
use work.signal_Package.all; |
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entity ARP_RX is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900" --20S |
); |
port ( |
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-- system signals |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
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-- MAC layer RX inputs |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
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-- Outputs to ARP |
o_ip_addr0 : out std_logic_vector(31 downto 0); |
o_mac_addr0 : out std_logic_vector(47 downto 0); |
o_addr_valid0 : out std_logic; |
o_pc_reply : out std_logic; |
o_pc_req : out std_logic; |
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-- Error Out |
o_arp_rx_err_out : out std_logic_vector (3 downto 0) |
); |
end ARP_RX; |
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architecture Behavioral of ARP_RX is |
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--=========================== ARP Lookup Table ========================================= |
component ARP_Lookup_table is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900" --20S |
); |
port ( |
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-- system signals |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
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-- Data in |
i_mac_addr_in : in std_logic_vector(47 downto 0); |
i_ip_addr_in : in std_logic_vector(31 downto 0); |
i_addr_valid_in : in std_logic; |
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i_request_in : in std_logic; |
i_reqly_in : in std_logic; |
i_trans_data_in : in std_logic; |
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-- Data out |
o_mac_addr_out : out std_logic_vector(47 downto 0); |
o_ip_addr_out : out std_logic_vector(31 downto 0); |
o_addr_valid_out : out std_logic; |
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o_request_out : out std_logic; |
o_reply_out : out std_logic |
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); |
end component; |
--====================================================================================== |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--============================= Top Signals ============================================================ |
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--signal s_udp_tx_data_len : std_logic_vector (15 downto 0):= c_PACKET_LENGTH; --1472 (Maximum Application Layer Packet Length) |
--signal s_udp_tx_start : std_logic:='0'; |
--signal s_udp_tx_ready : std_logic; |
--signal s_udp_tx_din : std_logic_vector (7 downto 0); |
-- |
--signal s_udp_rx_dout : std_logic_vector(7 downto 0); |
--signal s_udp_rx_dout_rdy : std_logic; |
--signal s_udp_rx_dout_last : std_logic; |
-- |
--signal s_udp_rx_src_ip : std_logic_vector(31 downto 0); |
--signal s_udp_rx_src_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_dst_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_data_len : std_logic_vector(15 downto 0); |
--signal s_udp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_udp_tx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_arp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_ip_rx_dst_ip_top : std_logic_vector(31 downto 0); |
--signal s_ip_rx_err_out_top : std_logic_vector (3 downto 0); |
--signal s_ip_tx_err_out_top : std_logic_vector (3 downto 0); |
-- |
-- |
--signal s_rx_clk_out : std_logic; |
--signal s_buff_rx_clk_out : std_logic; |
--signal s_tx_clk_out : std_logic; |
--signal s_buff_tx_clk_out : std_logic; |
--signal s_clk_125 : std_logic; |
--signal s_clk_100 : std_logic; |
--signal s_clk_m : std_logic; |
-- |
----chip scope |
--signal s_control : std_logic_vector (35 downto 0); |
--signal s_data_log : std_logic_vector (15 downto 0); |
-- |
-- |
----for transmit data |
--signal s_data_test_val : std_logic:='0'; |
--signal s_data_test_last : std_logic:='0'; |
--signal s_data_test : std_logic_vector (7 downto 0):=(others=>'0'); |
--signal s_cnt2 : std_logic_vector (15 downto 0):=(others=>'0'); |
--signal s_global_reset : std_logic:='1'; |
-- |
-- |
-- |
--signal s_gmii_txd : std_logic_vector(7 downto 0); |
--signal s_gmii_tx_en : std_logic; |
--signal s_gmii_tx_er : std_logic; |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
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--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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begin |
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--================================= Recieve ARP Data from Mac Layer =================== |
p_recieve_arp_data:process(i_rx_clk) |
begin |
if(rising_edge(i_rx_clk)) then |
if (i_reset='1') then |
st_RX_ARP_STATE <= IDLE; |
s_cnt_arp_rx <= x"0001"; |
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-- to Lookup |
s_src_mac_arp_rx <= (others => '0'); |
s_src_ip_arp_rx <= (others => '0'); |
s_addr_valid_pulse <= '0'; |
s_pc_req_pulse <= '0'; |
s_pc_reply_pulse <= '0'; |
s_trans_data_pulse <= '0'; |
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-- Internal Signals |
s_addr_valid <= '0'; |
s_pc_req <= '0'; |
s_pc_reply <= '0'; |
s_dst_ip <= (others => '0'); |
s_operation <= (others => '0'); |
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--error status |
o_arp_rx_err_out <= (others => '0'); |
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else |
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s_addr_valid_pulse <= '0'; |
s_pc_req_pulse <= '0'; |
s_pc_reply_pulse <= '0'; |
s_trans_data_pulse <= '0'; |
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CASE st_RX_ARP_STATE IS |
--************************************************************************************************************************************ |
WHEN IDLE => |
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s_cnt_arp_rx <= x"0001"; |
--error status |
o_arp_rx_err_out <= (others => '0'); |
if ( i_mac_data_in_valid = '1') then |
s_cnt_arp_rx <= s_cnt_arp_rx+1; |
st_RX_ARP_STATE <= ETH_H; |
end if; |
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--************************************************************************************************************************************ |
WHEN ETH_H => |
if ( i_mac_data_in_valid = '1') then |
s_cnt_arp_rx <= s_cnt_arp_rx+1; |
---------- Checking Frame Type ------------------------------ |
if(s_cnt_arp_rx= 13) then |
if i_mac_data_in /= x"08" then |
o_arp_rx_err_out <= x"1"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
if(s_cnt_arp_rx= 14) then |
st_RX_ARP_STATE <= ARP_DATA; |
if i_mac_data_in /= x"06" then |
o_arp_rx_err_out <= x"1"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
------------------------------------------------------ |
if ( i_mac_data_in_last = '1') then |
s_cnt_arp_rx <= x"0001"; |
--error status |
o_arp_rx_err_out <= x"2"; |
st_RX_ARP_STATE <= IDLE; |
end if; |
------------------------------------------------------ |
end if; |
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--************************************************************************************************************************************ |
WHEN ARP_DATA => |
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if (i_mac_data_in_valid = '1') then |
s_cnt_arp_rx <= s_cnt_arp_rx+1; |
------------- Checking Hardware Type ----------------------------------------------------------------- |
if(s_cnt_arp_rx= 15) then |
if i_mac_data_in /= x"00" then |
o_arp_rx_err_out <= x"3"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
if(s_cnt_arp_rx= 16) then |
if i_mac_data_in /= x"01" then |
o_arp_rx_err_out <= x"3"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
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------------- Checking Protocol Type ----------------------------------------------------------------- |
if(s_cnt_arp_rx= 17) then |
if i_mac_data_in /= x"08" then |
o_arp_rx_err_out <= x"4"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
if(s_cnt_arp_rx= 18) then |
if i_mac_data_in /= x"00" then |
o_arp_rx_err_out <= x"4"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
------------- Checking Address Length ----------------------------------------------------------------- |
if(s_cnt_arp_rx= 19) then |
if i_mac_data_in /= x"06" then |
o_arp_rx_err_out <= x"5"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
if(s_cnt_arp_rx= 20) then |
if i_mac_data_in /= x"04" then |
o_arp_rx_err_out <= x"5"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
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------------- Checking & Loading Operation ---------------------------------------------------------- |
if(s_cnt_arp_rx=21) then |
s_operation (15 downto 8) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=22) then |
s_operation (7 downto 0) <= i_mac_data_in; |
s_pc_req <= '0'; |
s_pc_reply <= '0'; |
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if ((s_operation (15 downto 8) & i_mac_data_in) = x"0001") then |
s_pc_req <= '1'; |
elsif ((s_operation (15 downto 8) & i_mac_data_in) = x"0002") then |
s_pc_reply <= '1'; |
else |
o_arp_rx_err_out <= x"6"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
------------- Loading Source MAC Address ---------------------------------------------------------------------- |
if(s_cnt_arp_rx=23) then |
s_src_mac_arp_rx(47 downto 40) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=24) then |
s_src_mac_arp_rx(39 downto 32) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=25) then |
s_src_mac_arp_rx(31 downto 24) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=26) then |
s_src_mac_arp_rx(23 downto 16) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=27) then |
s_src_mac_arp_rx(15 downto 8) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=28) then |
s_src_mac_arp_rx(7 downto 0) <= i_mac_data_in; |
end if; |
------------- Loading Source IP Address ---------------------------------------------------------------------- |
if(s_cnt_arp_rx=29) then |
s_src_ip_arp_rx(31 downto 24) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=30) then |
s_src_ip_arp_rx(23 downto 16) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=31) then |
s_src_ip_arp_rx(15 downto 8) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=32) then |
s_src_ip_arp_rx(7 downto 0) <= i_mac_data_in; |
s_addr_valid <= '1'; |
if ((s_src_ip_arp_rx(31 downto 8) & i_mac_data_in) = c_IP_BC_ADDR) then |
s_addr_valid <= '0'; |
o_arp_rx_err_out <= x"7"; |
st_RX_ARP_STATE <= WAIT_END; |
end if; |
end if; |
------------- Loading Dst IP Address ---------------------------------------------------------------------- |
if(s_cnt_arp_rx=39) then |
s_dst_ip(31 downto 24) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=40) then |
s_dst_ip(23 downto 16) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=41) then |
s_dst_ip(15 downto 8) <= i_mac_data_in; |
end if; |
if(s_cnt_arp_rx=42) then -- End of ARP Packet |
s_dst_ip(7 downto 0) <= i_mac_data_in; |
st_RX_ARP_STATE <= WAIT_END; |
-- transmit to Lookup |
s_trans_data_pulse <= '1'; |
s_addr_valid_pulse <= s_addr_valid; |
if ((s_dst_ip(31 downto 8) & i_mac_data_in) = i_our_ip_addr) then |
s_pc_req_pulse <= s_pc_req; |
s_pc_reply_pulse <= s_pc_reply; |
end if; |
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end if; |
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------------------------------------------------ |
if (i_mac_data_in_last = '1') then |
s_cnt_arp_rx <= x"0001"; |
st_RX_ARP_STATE <= IDLE; |
if (s_cnt_arp_rx < 42) then |
o_arp_rx_err_out <= x"2"; |
end if; |
end if; |
------------------------------------------------ |
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end if; |
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--============================================= |
WHEN WAIT_END => |
if ( i_mac_data_in_valid = '1') then |
if ( i_mac_data_in_last = '1') then |
s_cnt_arp_rx <= x"0001"; |
--error status |
o_arp_rx_err_out <= x"0"; |
st_RX_ARP_STATE <= IDLE; |
end if; |
end if; |
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END CASE; |
--============================================= |
end if; |
end if; |
end process p_recieve_arp_data; |
--================================================================================================ |
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--===================== ARP_Lookup_table ========================================================== |
inst_arp_lookup_table : ARP_Lookup_table |
generic map( |
g_TIME_OUT_LOOKUP_TABLE_ARP => g_TIME_OUT_LOOKUP_TABLE_ARP |
) |
port map ( |
-- system signals |
i_rx_clk => i_rx_clk, |
i_tx_clk => i_tx_clk, |
i_reset => i_reset, |
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-- Data in |
i_mac_addr_in => s_src_mac_arp_rx, |
i_ip_addr_in => s_src_ip_arp_rx, |
i_addr_valid_in => s_addr_valid_pulse, |
i_request_in => s_pc_req_pulse, |
i_reqly_in => s_pc_reply_pulse, |
i_trans_data_in => s_trans_data_pulse, |
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-- Data out |
o_mac_addr_out => o_mac_addr0, |
o_ip_addr_out => o_ip_addr0, |
o_addr_valid_out => o_addr_valid0, |
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o_request_out => o_pc_req, |
o_reply_out => o_pc_reply |
); |
--================================================================================================ |
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end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/ARP_TX.vhd
0,0 → 1,773
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
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library work; |
use work.signal_Package.all; |
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entity ARP_TX is |
port ( |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
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--for ARP Data |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
i_our_mac_addr : in std_logic_vector (47 downto 0); |
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i_dst_ip_addr_pc : in std_logic_vector (31 downto 0); |
i_dst_mac_addr_pc : in std_logic_vector (47 downto 0); |
i_dst_ip_addr_lookup : in std_logic_vector (31 downto 0); |
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--ARP Request's |
i_fpga_req : in std_logic; |
i_pc_req : in std_logic; |
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-- for transfer data to mac layer |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0) |
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); |
end ARP_TX; |
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architecture Behavioral of ARP_TX is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--============================= Top Signals ============================================================ |
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--signal s_udp_tx_data_len : std_logic_vector (15 downto 0):= c_PACKET_LENGTH; --1472 (Maximum Application Layer Packet Length) |
--signal s_udp_tx_start : std_logic:='0'; |
--signal s_udp_tx_ready : std_logic; |
--signal s_udp_tx_din : std_logic_vector (7 downto 0); |
-- |
--signal s_udp_rx_dout : std_logic_vector(7 downto 0); |
--signal s_udp_rx_dout_rdy : std_logic; |
--signal s_udp_rx_dout_last : std_logic; |
-- |
--signal s_udp_rx_src_ip : std_logic_vector(31 downto 0); |
--signal s_udp_rx_src_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_dst_port : std_logic_vector(15 downto 0); |
--signal s_udp_rx_data_len : std_logic_vector(15 downto 0); |
--signal s_udp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_udp_tx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_arp_rx_err_out_top : std_logic_vector(3 downto 0); |
--signal s_ip_rx_dst_ip_top : std_logic_vector(31 downto 0); |
--signal s_ip_rx_err_out_top : std_logic_vector (3 downto 0); |
--signal s_ip_tx_err_out_top : std_logic_vector (3 downto 0); |
-- |
-- |
--signal s_rx_clk_out : std_logic; |
--signal s_buff_rx_clk_out : std_logic; |
--signal s_tx_clk_out : std_logic; |
--signal s_buff_tx_clk_out : std_logic; |
--signal s_clk_125 : std_logic; |
--signal s_clk_100 : std_logic; |
--signal s_clk_m : std_logic; |
-- |
----chip scope |
--signal s_control : std_logic_vector (35 downto 0); |
--signal s_data_log : std_logic_vector (15 downto 0); |
-- |
-- |
----for transmit data |
--signal s_data_test_val : std_logic:='0'; |
--signal s_data_test_last : std_logic:='0'; |
--signal s_data_test : std_logic_vector (7 downto 0):=(others=>'0'); |
--signal s_cnt2 : std_logic_vector (15 downto 0):=(others=>'0'); |
--signal s_global_reset : std_logic:='1'; |
-- |
-- |
-- |
--signal s_gmii_txd : std_logic_vector(7 downto 0); |
--signal s_gmii_tx_en : std_logic; |
--signal s_gmii_tx_er : std_logic; |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
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--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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begin |
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--============================== Transmit ARP Data to Mac Layer ================================ |
p_transmission_arp_data:process(i_tx_clk) |
begin |
if(rising_edge(i_tx_clk)) then |
if (i_reset='1') then |
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st_tx_arp_state <=IDLE; |
s_cnt_arp_tx <=(others=>'0'); |
s_arp_type <=(others=>'0'); |
s_dst_ip_addr <=(others=>'0'); |
s_dst_mac_addr1 <=(others=>'0'); |
s_dst_mac_addr2 <=(others=>'0'); |
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--for mac |
o_mac_tx_req <= '0'; |
o_mac_tvalid <= '0'; |
o_mac_tlast <= '0'; |
o_mac_tdata <=(others=>'0'); |
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else |
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case st_tx_arp_state is |
when IDLE => |
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s_cnt_arp_tx <=(others=>'0'); |
s_arp_type <=(others=>'0'); |
s_dst_ip_addr <=(others=>'0'); |
s_dst_mac_addr1 <=(others=>'0'); |
s_dst_mac_addr2 <=(others=>'0'); |
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--for mac |
o_mac_tx_req <= '0'; |
o_mac_tvalid <= '0'; |
o_mac_tlast <= '0'; |
o_mac_tdata <=(others=>'0'); |
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if (i_fpga_req = '1') then |
o_mac_tx_req <= '1'; |
s_arp_type <= x"0001"; |
s_dst_ip_addr <= i_dst_ip_addr_lookup; |
s_dst_mac_addr1 <= x"ffffffffffff"; |
s_dst_mac_addr2 <= x"000000000000"; |
st_tx_arp_state <= WAIT_CHN; |
elsif(i_pc_req = '1') then |
o_mac_tx_req <= '1'; |
s_arp_type <= x"0002"; |
s_dst_ip_addr <= i_dst_ip_addr_pc; |
s_dst_mac_addr1 <= i_dst_mac_addr_pc; |
s_dst_mac_addr2 <= i_dst_mac_addr_pc; |
st_tx_arp_state <= WAIT_CHN; |
end if; |
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when WAIT_CHN => |
if i_mac_tx_granted = '1' then |
st_tx_arp_state <= SEND_DATA; |
end if; |
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when SEND_DATA => |
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if (s_cnt_arp_tx=x"00") then |
o_mac_tdata <= s_dst_mac_addr1(47 downto 40); |
s_cnt_arp_tx <= s_cnt_arp_tx+1; |
o_mac_tvalid <= '1'; |
end if; |
|
if (i_mac_tready='1') then |
--************************************************************************************** |
s_cnt_arp_tx <= s_cnt_arp_tx+1; |
case s_cnt_arp_tx is |
--dst MAC Addr |
when X"01" => o_mac_tdata <= s_dst_mac_addr1(39 downto 32); |
when X"02" => o_mac_tdata <= s_dst_mac_addr1(31 downto 24); |
when X"03" => o_mac_tdata <= s_dst_mac_addr1(23 downto 16); |
when X"04" => o_mac_tdata <= s_dst_mac_addr1(15 downto 8); |
when X"05" => o_mac_tdata <= s_dst_mac_addr1(7 downto 0); |
|
-- src MAC Addr |
when X"06" => o_mac_tdata <= i_our_mac_addr(47 downto 40); |
when X"07" => o_mac_tdata <= i_our_mac_addr(39 downto 32); |
when X"08" => o_mac_tdata <= i_our_mac_addr(31 downto 24); |
when X"09" => o_mac_tdata <= i_our_mac_addr(23 downto 16); |
when X"0A" => o_mac_tdata <= i_our_mac_addr(15 downto 8); |
when X"0B" => o_mac_tdata <= i_our_mac_addr(7 downto 0); |
|
--Frame Type |
when X"0C" => o_mac_tdata <= x"08"; |
when X"0D" => o_mac_tdata <= x"06"; |
|
--Hardware type |
when X"0E" => o_mac_tdata <= x"00"; |
when X"0F" => o_mac_tdata <= x"01"; |
|
--Protocol Type |
when X"10" => o_mac_tdata <= x"08"; |
when X"11" => o_mac_tdata <= x"00"; |
|
-- Addr Length |
when X"12" => o_mac_tdata <= x"06"; |
when X"13" => o_mac_tdata <= x"04"; |
|
--ARP Type |
when X"14" => o_mac_tdata <= s_arp_type(15 downto 8); |
when X"15" => o_mac_tdata <= s_arp_type(7 downto 0); |
|
--src MAC Addr |
when X"16" => o_mac_tdata <= i_our_mac_addr(47 downto 40); |
when X"17" => o_mac_tdata <= i_our_mac_addr(39 downto 32); |
when X"18" => o_mac_tdata <= i_our_mac_addr(31 downto 24); |
when X"19" => o_mac_tdata <= i_our_mac_addr(23 downto 16); |
when X"1A" => o_mac_tdata <= i_our_mac_addr(15 downto 8); |
when X"1B" => o_mac_tdata <= i_our_mac_addr(7 downto 0); |
|
--src IP Addr |
when X"1C" => o_mac_tdata <= i_our_ip_addr(31 downto 24); |
when X"1D" => o_mac_tdata <= i_our_ip_addr(23 downto 16); |
when X"1E" => o_mac_tdata <= i_our_ip_addr(15 downto 8); |
when X"1F" => o_mac_tdata <= i_our_ip_addr(7 downto 0); |
|
--Broadcast MAC Addr |
when X"20" => o_mac_tdata <= s_dst_mac_addr2(47 downto 40); |
when X"21" => o_mac_tdata <= s_dst_mac_addr2(39 downto 32); |
when X"22" => o_mac_tdata <= s_dst_mac_addr2(31 downto 24); |
when X"23" => o_mac_tdata <= s_dst_mac_addr2(23 downto 16); |
when X"24" => o_mac_tdata <= s_dst_mac_addr2(15 downto 8); |
when X"25" => o_mac_tdata <= s_dst_mac_addr2(7 downto 0); |
|
-- dst IP Addr |
when X"26" => o_mac_tdata <= s_dst_ip_addr(31 downto 24); |
when X"27" => o_mac_tdata <= s_dst_ip_addr(23 downto 16); |
when X"28" => o_mac_tdata <= s_dst_ip_addr(15 downto 8); |
when X"29" => o_mac_tdata <= s_dst_ip_addr(7 downto 0); |
when others => null; |
|
end case; |
|
if (s_cnt_arp_tx=X"29") then |
o_mac_tlast <= '1'; |
end if; |
--********************************************************************************************* |
end if; |
|
if (s_cnt_arp_tx=X"2A") then |
s_cnt_arp_tx <= (others=>'0'); |
o_mac_tx_req <= '0'; |
o_mac_tvalid <= '0'; |
o_mac_tlast <= '0'; |
o_mac_tdata <= (others=>'0'); |
st_tx_arp_state <= IDLE; |
end if; |
|
END CASE; |
|
end if; |
end if; |
end process p_transmission_arp_data; |
--===================================================================================================== |
|
end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/IP_ARP_PING.vhd
0,0 → 1,930
--**************************************************************************************** |
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.NUMERIC_STD.all; |
|
library work; |
use work.signal_Package.all; |
|
entity IP_ARP_PING is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0) := x"9502F900"; --20S |
g_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector(31 downto 0) := x"07735940"; --1S |
g_RE_SEND_ARP_REQUEST : std_logic_vector(3 downto 0) := x"A"; --10 |
g_GENERATE_PING_MODULE : boolean := true; |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0):= x"AABBCCDDEEFF" |
); |
port |
( |
-- system signals |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
--******************************* TX *************************************** |
-- Tx header construction |
i_ip_tx_src_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_dst_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_data_len : in std_logic_vector (15 downto 0); |
i_ip_tcp_tx_id : in std_logic_vector (15 downto 0):=(others => '0'); |
i_ip_tx_protocol : in std_logic_vector (7 downto 0); |
i_ip_tx_src_mac : in std_logic_vector (47 downto 0); |
i_ip_tx_fragmantation : in std_logic_vector(15 downto 0); |
|
-- TX Inputs |
i_ip_tx_start : in std_logic; |
o_ip_tx_rdy : out std_logic; |
i_ip_tx_din : in std_logic_vector (7 downto 0); |
|
-- TX Outputs |
i_mac_tx_tready : in std_logic; |
o_mac_tx_tdata : out std_logic_vector(7 downto 0); |
o_mac_tx_tvalid : out std_logic; |
o_mac_tx_tlast : out std_logic; |
|
-- Error Status |
o_ip_tx_err_out : out std_logic_vector (3 downto 0); |
o_lookup_mac_err : out std_logic; |
--******************************* RX *************************************** |
-- RX Inputs |
i_mac_rx_tdata : in std_logic_vector(7 downto 0); |
i_mac_rx_tvalid : in std_logic; |
i_mac_rx_tlast : in std_logic; |
|
-- RX Outputs |
o_ip_rx_dout : out std_logic_vector(7 downto 0); |
o_ip_rx_dout_rdy : out std_logic; |
o_ip_rx_dout_last : out std_logic; |
|
-- RX Status Outputs |
o_ip_rx_src_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_dst_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_data_len : out std_logic_vector(15 downto 0); |
o_ip_rx_protocol : out std_logic_vector(7 downto 0); |
o_ip_rx_broadcast : out std_logic; |
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
|
-- Error Status |
o_ip_rx_err_out : out std_logic_vector (3 downto 0); |
o_arp_rx_err_out : out std_logic_vector (3 downto 0) |
--**************************************************************************** |
); |
end IP_ARP_PING; |
|
architecture structural of IP_ARP_PING is |
|
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
|
|
--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
|
|
--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
|
--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
|
--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
|
--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
|
|
--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
|
signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
|
|
|
--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
|
signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
|
|
--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
|
-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
|
-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
|
-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
|
|
|
--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
|
signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
|
signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
|
signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
|
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
|
|
signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
|
signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
|
--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
|
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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--====================================== IP4 ==================================== |
component IPv4 |
generic ( |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF" |
); |
port |
( |
-- system signals |
i_rx_clk : in STD_LOGIC; |
i_tx_clk : in STD_LOGIC; |
i_reset : in STD_LOGIC; |
--************************************ TX ********************************** |
-- Tx header construction |
i_ip_tx_src_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_dst_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_data_len : in std_logic_vector (15 downto 0); |
i_ip_tx_fragmantation : in std_logic_vector(15 downto 0); |
i_ip_tx_protocol : in std_logic_vector (7 downto 0); |
i_ip_tx_src_mac : in std_logic_vector (47 downto 0); |
-- TX Inputs |
i_ip_tx_start : in std_logic; |
o_ip_tx_rdy : out std_logic; |
i_ip_tx_din : in std_logic_vector (7 downto 0); |
-- TX Outputs |
i_mac_tx_tready : in std_logic; |
o_mac_tx_tvalid : out std_logic; |
o_mac_tx_tlast : out std_logic; |
o_mac_tx_tdata : out std_logic_vector (7 downto 0); |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
-- TX & ARP inouts |
o_lookup_req : out std_logic; |
o_lookup_ip : out std_logic_vector (31 downto 0); |
i_lookup_mac_addr : in std_logic_vector (47 downto 0); |
i_lookup_mac_got : in std_logic; |
i_lookup_mac_err : in std_logic; |
-- Error Status |
o_ip_tx_err_out : out std_logic_vector (3 downto 0); |
--******************************* RX *************************************** |
-- RX Inputs |
i_mac_rx_tdata : in std_logic_vector(7 downto 0); |
i_mac_rx_tvalid : in std_logic; |
i_mac_rx_tlast : in std_logic; |
-- RX Outputs |
o_ip_rx_dout : out std_logic_vector(7 downto 0); |
o_ip_rx_dout_rdy : out std_logic; |
o_ip_rx_dout_last : out std_logic; |
-- RX Status Outputs |
o_ip_rx_src_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_dst_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_data_len : out std_logic_vector(15 downto 0); |
o_ip_rx_protocol : out std_logic_vector(7 downto 0); |
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
o_ip_rx_broadcast : out std_logic; |
-- Error Status |
o_no_ping_packet : out std_logic; |
o_ip_rx_err_out : out std_logic_vector (3 downto 0) |
); |
end component; |
--========================================================================================= |
--========================= ARP =========================================================== |
component ARP is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0) := x"9502F900"; --20S |
g_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector(31 downto 0) := x"07735940"; --1S |
g_RE_SEND_ARP_REQUEST : std_logic_vector(3 downto 0) := x"A" --10 |
); |
port |
( |
-- system signals |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
|
-- for ARP Data |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
i_our_mac_addr : in std_logic_vector (47 downto 0); |
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-- to/from IP Layer |
i_fpga_req : in std_logic; |
i_lookup_ip : in std_logic_vector (31 downto 0); |
o_lookup_mac_addr : out std_logic_vector (47 downto 0); |
o_lookup_mac_got : out std_logic; |
o_lookup_mac_err : out std_logic; |
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-- ARP_RX Input |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
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-- ARP_TX Input/Output |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0); |
|
-- Error Out |
o_arp_rx_err_out : out std_logic_vector (3 downto 0) |
); |
end component; |
--========================================================================================= |
--================================ Ping =================================================== |
component ping is |
port |
( |
-- system signals |
i_tx_clk : in std_logic; |
i_rx_clk : in std_logic; |
i_reset : in std_logic; |
|
-- MAC layer RX inputs |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
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--IP_RX output and status |
i_ip_rx_err_in : in std_logic_vector(3 downto 0); |
i_no_ping_packet : in std_logic; |
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-- for transfer data to mac layer |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0) |
); |
end component; |
--========================================================================================= |
--======================== TX Channel Priority ============================================ |
component tx_arbitrator is |
port |
( |
-- system signals |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
|
-- IP Inputs Path |
i_req_1 : in std_logic; |
o_grant_1 : out std_logic; |
i_data_1 : in std_logic_vector(7 downto 0); |
i_valid_1 : in std_logic; |
i_last_1 : in std_logic; |
|
-- ARP Inputs Path |
i_req_2 : in std_logic; |
o_grant_2 : out std_logic; |
i_data_2 : in std_logic_vector(7 downto 0); |
i_valid_2 : in std_logic; |
i_last_2 : in std_logic; |
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-- PING Inputs Path |
i_req_3 : in std_logic; |
o_grant_3 : out std_logic; |
i_data_3 : in std_logic_vector(7 downto 0); |
i_valid_3 : in std_logic; |
i_last_3 : in std_logic; |
|
-- Outputs Path |
o_data : out std_logic_vector(7 downto 0); |
o_valid : out std_logic; |
o_last : out std_logic |
); |
end component; |
--========================================================================================= |
begin |
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o_ip_rx_err_out <= s_ip_rx_err_out; |
o_lookup_mac_err <= s_lookup_mac_err; |
--============================ IP layer ============================================ |
inst_IPv4 : IPv4 |
generic map |
( |
g_GENERATE_ARP_MODULE => g_GENERATE_ARP_MODULE, |
g_DEFAULT_DST_MAC_ADDR => g_DEFAULT_DST_MAC_ADDR |
) |
port map |
( |
-- system signals |
i_rx_clk => i_rx_clk, |
i_tx_clk => i_tx_clk, |
i_reset => i_reset, |
|
--************************************ TX ********************************** |
-- Tx header construction |
i_ip_tx_src_ip => i_ip_tx_src_ip, |
i_ip_tx_dst_ip => i_ip_tx_dst_ip, |
i_ip_tx_data_len => i_ip_tx_data_len, |
i_ip_tx_protocol => i_ip_tx_protocol, |
i_ip_tx_fragmantation => i_ip_tx_fragmantation, |
i_ip_tx_src_mac => i_ip_tx_src_mac, |
|
-- TX Inputs |
i_ip_tx_start => i_ip_tx_start, |
o_ip_tx_rdy => o_ip_tx_rdy, |
i_ip_tx_din => i_ip_tx_din, |
-- TX Outputs |
i_mac_tx_tready => i_mac_tx_tready, |
o_mac_tx_tvalid => s_ip_mac_tx_tvalid, |
o_mac_tx_tlast => s_ip_mac_tx_tlast, |
o_mac_tx_tdata => s_ip_mac_tx_tdata, |
o_mac_tx_req => s_ip_mac_tx_req, |
i_mac_tx_granted => s_ip_mac_tx_granted, |
|
-- TX & ARP inouts |
-- o_lookup_req => open, |
-- o_lookup_ip => open, |
-- i_lookup_mac_addr => x"F46D04962225", |
-- i_lookup_mac_got => '1', |
-- i_lookup_mac_err => '0', |
|
o_lookup_req => s_lookup_req, |
o_lookup_ip => s_lookup_ip, |
i_lookup_mac_addr => s_lookup_mac_addr, |
i_lookup_mac_got => s_lookup_mac_got, |
i_lookup_mac_err => s_lookup_mac_err, |
|
-- Error Status |
o_ip_tx_err_out => o_ip_tx_err_out, |
|
--******************************* RX *************************************** |
-- RX Inputs |
i_mac_rx_tdata => i_mac_rx_tdata, |
i_mac_rx_tvalid => i_mac_rx_tvalid, |
i_mac_rx_tlast => i_mac_rx_tlast, |
|
-- RX Outputs |
o_ip_rx_dout => o_ip_rx_dout, |
o_ip_rx_dout_rdy => o_ip_rx_dout_rdy, |
o_ip_rx_dout_last => o_ip_rx_dout_last, |
|
-- RX Status Outputs |
o_ip_rx_src_ip => o_ip_rx_src_ip, |
o_ip_rx_dst_ip => o_ip_rx_dst_ip, |
o_ip_rx_data_len => o_ip_rx_data_len, |
o_ip_rx_protocol => o_ip_rx_protocol, |
o_ip_rx_fragmantation => o_ip_rx_fragmantation, |
o_ip_rx_broadcast => o_ip_rx_broadcast, |
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o_no_ping_packet => s_no_ping_packet, |
o_ip_rx_err_out => s_ip_rx_err_out |
); |
--===================================================================================== |
--=============================== ARP ================================================= |
Arp_gen:if (g_GENERATE_ARP_MODULE) generate |
begin |
inst_arp: ARP |
generic map |
( |
g_TIME_OUT_LOOKUP_TABLE_ARP => g_TIME_OUT_LOOKUP_TABLE_ARP, |
g_TIME_OUT_WAIT_FOR_ARP_REPLY => g_TIME_OUT_WAIT_FOR_ARP_REPLY, |
g_RE_SEND_ARP_REQUEST => g_RE_SEND_ARP_REQUEST |
) |
port map |
( |
-- system signals |
i_rx_clk => i_rx_clk, |
i_tx_clk => i_tx_clk, |
i_reset => i_reset, |
|
-- for ARP Data |
i_our_ip_addr => i_ip_tx_src_ip, |
i_our_mac_addr => i_ip_tx_src_mac, |
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-- to/from IP Layer |
i_fpga_req => s_lookup_req, |
i_lookup_ip => s_lookup_ip, |
o_lookup_mac_addr => s_lookup_mac_addr, |
o_lookup_mac_got => s_lookup_mac_got, |
o_lookup_mac_err => s_lookup_mac_err, |
|
-- ARP_RX Input |
i_mac_data_in => i_mac_rx_tdata, |
i_mac_data_in_valid => i_mac_rx_tvalid, |
i_mac_data_in_last => i_mac_rx_tlast, |
|
-- ARP_TX Input/Output |
o_mac_tx_req => s_arp_mac_tx_req, |
i_mac_tx_granted => s_arp_mac_tx_granted, |
i_mac_tready => i_mac_tx_tready, |
o_mac_tvalid => s_arp_mac_tx_tvalid, |
o_mac_tlast => s_arp_mac_tx_tlast, |
o_mac_tdata => s_arp_mac_tx_tdata, |
|
-- Error Out |
o_arp_rx_err_out => o_arp_rx_err_out |
); |
end generate; |
--===================================================================================== |
--==================================== Ping =========================================== |
ping_gen:if (g_GENERATE_PING_MODULE) generate |
begin |
inst_ping:ping |
port map |
( |
-- system signals |
i_tx_clk => i_tx_clk, |
i_rx_clk => i_rx_clk, |
i_reset => i_reset, |
|
-- MAC layer RX inputs |
i_mac_data_in => i_mac_rx_tdata, |
i_mac_data_in_valid => i_mac_rx_tvalid, |
i_mac_data_in_last => i_mac_rx_tlast, |
|
-- IP_RX output and status |
i_ip_rx_err_in => s_ip_rx_err_out, |
i_no_ping_packet => s_no_ping_packet, |
|
-- for transfer data to mac layer |
o_mac_tx_req => s_ping_mac_tx_req, |
i_mac_tx_granted => s_ping_mac_tx_granted, |
i_mac_tready => i_mac_tx_tready, |
o_mac_tvalid => s_ping_mac_tx_tvalid, |
o_mac_tlast => s_ping_mac_tx_tlast, |
o_mac_tdata => s_ping_mac_tx_tdata |
); |
end generate; |
--===================================================================================== |
--================================ TX Channel Priority ================================ |
inst_tx_arbitrator : tx_arbitrator |
port map |
( |
-- system signals |
i_tx_clk => i_tx_clk, |
i_reset => i_reset, |
|
-- IP Inputs Path |
i_req_1 => s_ip_mac_tx_req, |
o_grant_1 => s_ip_mac_tx_granted, |
i_data_1 => s_ip_mac_tx_tdata, |
i_valid_1 => s_ip_mac_tx_tvalid, |
i_last_1 => s_ip_mac_tx_tlast, |
|
-- ARP Inputs Path |
i_req_2 => s_arp_mac_tx_req, |
o_grant_2 => s_arp_mac_tx_granted, |
i_data_2 => s_arp_mac_tx_tdata, |
i_valid_2 => s_arp_mac_tx_tvalid, |
i_last_2 => s_arp_mac_tx_tlast, |
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-- PING Inputs Path |
i_req_3 => s_ping_mac_tx_req, |
o_grant_3 => s_ping_mac_tx_granted, |
i_data_3 => s_ping_mac_tx_tdata, |
i_valid_3 => s_ping_mac_tx_tvalid, |
i_last_3 => s_ping_mac_tx_tlast, |
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-- Outputs Path |
o_data => o_mac_tx_tdata, |
o_valid => o_mac_tx_tvalid, |
o_last => o_mac_tx_tlast |
); |
--===================================================================================== |
end structural; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/IP_RX.vhd
0,0 → 1,830
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
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library work; |
use work.signal_Package.all; |
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entity IPv4_RX is |
port ( |
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-- system signals |
i_rx_clk : in std_logic; |
i_reset : in std_logic; |
i_our_ip_address : in std_logic_vector (31 downto 0); |
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-- MAC layer RX inputs |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
|
-- Outputs to ip layer |
o_ip_dout : buffer std_logic_vector(7 downto 0); |
o_ip_dout_rdy : buffer std_logic; |
o_ip_data_last : buffer std_logic; |
|
--Status Outputs |
o_src_ip : out std_logic_vector(31 downto 0); |
o_dst_ip : out std_logic_vector(31 downto 0); |
o_data_len : out std_logic_vector(15 downto 0); --data len is ip_data_length that is udp data (ip_data-20) |
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
o_protocol : out std_logic_vector(7 downto 0); --udp protocol |
o_broadcast : out std_logic; |
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--Error Status |
o_no_ping_packet : out std_logic; |
o_ip_rx_err_out : buffer std_logic_vector(3 downto 0) |
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); |
end IPv4_RX; |
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architecture Behavioral of ipv4_rx is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
|
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
|
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
|
|
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
|
signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
|
|
--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
|
-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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begin |
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o_src_ip <= s_src_ip_ip_rx ; |
o_dst_ip <= s_dst_ip_ip_rx ; |
o_data_len <= s_data_len_ip_rx ; |
o_protocol <= s_protocol_ip_rx ; |
o_broadcast <= s_broadcast_ip_rx; |
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--============================== Recieve IP Data =================================================================================== |
p_recieve_data:process(i_rx_clk) |
begin |
if(rising_edge(i_rx_clk)) then |
o_no_ping_packet <= '0'; |
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if (i_reset='1') then |
st_RX_IP_STATE <= IDLE; |
s_cnt_ip_rx <= x"0001"; |
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--status |
s_src_ip_ip_rx <= (others => '0'); |
s_dst_ip_ip_rx <= (others => '0'); |
s_data_len_ip_rx <= (others => '0'); |
s_protocol_ip_rx <= (others => '0'); |
s_broadcast_ip_rx <= '0'; |
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--data to ip layer |
o_ip_dout <= (others => '0'); |
o_ip_dout_rdy <= '0' ; |
o_ip_data_last <= '0' ; |
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--error status |
o_ip_rx_err_out <= (others => '0'); |
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else |
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o_ip_dout <= (others => '0'); |
o_ip_dout_rdy <= '0' ; |
o_ip_data_last <= '0' ; |
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CASE st_RX_IP_STATE IS |
--************************************************************************************************************************************ |
WHEN IDLE => |
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s_cnt_ip_rx <= x"0001"; |
--status |
-- s_src_ip_ip_rx <= (others => '0'); |
-- s_dst_ip_ip_rx <= (others => '0'); |
-- s_data_len_ip_rx <= (others => '0'); |
-- s_protocol_ip_rx <= (others => '0'); |
-- s_broadcast_ip_rx <= '0'; |
--error status |
o_ip_rx_err_out <= (others => '0'); |
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if ( i_mac_data_in_valid = '1') then |
s_cnt_ip_rx <= s_cnt_ip_rx+1; |
st_RX_IP_STATE <= ETH_H; |
end if; |
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--************************************************************************************************************************************ |
WHEN ETH_H => |
if ( i_mac_data_in_valid = '1') then |
s_cnt_ip_rx <= s_cnt_ip_rx+1; |
---------- Cheking Type ------------------------------ |
if(s_cnt_ip_rx= 13) then |
if i_mac_data_in /= x"08" then |
o_ip_rx_err_out <= x"1"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
end if; |
---------- Cheking Type ------------------------------ |
if(s_cnt_ip_rx= 14) then |
st_RX_IP_STATE <= IP_H; |
if i_mac_data_in /= x"00" then |
o_ip_rx_err_out <= x"1"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
end if; |
------------------------------------------------------ |
if ( i_mac_data_in_last = '1') then |
s_cnt_ip_rx <= x"0001"; |
--status |
-- s_src_ip_ip_rx <= (others => '0'); |
-- s_dst_ip_ip_rx <= (others => '0'); |
-- s_data_len_ip_rx <= (others => '0'); |
-- s_protocol_ip_rx <= (others => '0'); |
s_broadcast_ip_rx <= '0'; |
--error status |
o_ip_rx_err_out <= x"2"; |
st_RX_IP_STATE <= IDLE; |
end if; |
------------------------------------------------------ |
end if; |
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--************************************************************************************************************************************ |
WHEN IP_H => |
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if (i_mac_data_in_valid = '1') then |
s_cnt_ip_rx <= s_cnt_ip_rx+1; |
------------- Checking Version & IHL ----------------------------------------------------------------- |
if(s_cnt_ip_rx= 15) then |
if i_mac_data_in /= x"45" then |
o_ip_rx_err_out <= x"3"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
end if; |
------------- Checking & Loading Data Length ---------------------------------------------------------- |
if(s_cnt_ip_rx=17) then |
s_data_len_ip_rx (15 downto 8) <= i_mac_data_in; |
s_data_len_ip_rx (7 downto 0) <= x"00"; |
end if; |
if(s_cnt_ip_rx=18) then |
s_data_len_ip_rx <= std_logic_vector((s_data_len_ip_rx(15 downto 8) & i_mac_data_in) - 20); |
if ((s_data_len_ip_rx(15 downto 8) & i_mac_data_in) < 20) then |
o_ip_rx_err_out <= x"4"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
end if; |
------------- Cheching Frag & Offset ----------------------------------------------------------------- |
if(s_cnt_ip_rx=21) then |
o_ip_rx_fragmantation(15 downto 8) <= i_mac_data_in; |
-- if (i_mac_data_in(7) = '1') or (i_mac_data_in (4 downto 0) /= "00000") then |
-- o_ip_rx_err_out <= x"5"; |
-- st_RX_IP_STATE <= WAIT_END; |
-- end if; |
end if; |
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if(s_cnt_ip_rx=22) then |
o_ip_rx_fragmantation(7 downto 0) <= i_mac_data_in; |
-- if (i_mac_data_in /= x"00") then |
-- o_ip_rx_err_out <= x"5"; |
-- st_RX_IP_STATE <= WAIT_END; |
-- end if; |
end if; |
------------- Loading Protocol ------------------------------------------------------------ |
if(s_cnt_ip_rx=24) then |
s_protocol_ip_rx <= i_mac_data_in; |
if (i_mac_data_in/=x"01") then |
o_no_ping_packet <= '1'; |
end if; |
end if; |
------------- Loading Source IP ---------------------------------------------------------------------- |
if(s_cnt_ip_rx=27) then |
s_src_ip_ip_rx(31 downto 24) <= i_mac_data_in; |
end if; |
if(s_cnt_ip_rx=28) then |
s_src_ip_ip_rx(23 downto 16) <= i_mac_data_in; |
end if; |
if(s_cnt_ip_rx=29) then |
s_src_ip_ip_rx(15 downto 8) <= i_mac_data_in; |
end if; |
if(s_cnt_ip_rx=30) then |
s_src_ip_ip_rx(7 downto 0) <= i_mac_data_in; |
end if; |
------------- Checking & Loaoding Dest IP------------------------------------------------------------- |
if(s_cnt_ip_rx=31) then |
s_dst_ip_ip_rx(31 downto 24) <= i_mac_data_in; |
if ((i_mac_data_in /= i_our_ip_address(31 downto 24)))then |
o_ip_rx_err_out <= x"7"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
end if; |
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if(s_cnt_ip_rx=32) then |
s_dst_ip_ip_rx(23 downto 16) <= i_mac_data_in; |
if ((i_mac_data_in /= i_our_ip_address(23 downto 16)))then |
o_ip_rx_err_out <= x"7"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
end if; |
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if(s_cnt_ip_rx=33) then |
s_dst_ip_ip_rx(15 downto 8) <= i_mac_data_in; |
if ((i_mac_data_in /= i_our_ip_address(15 downto 8)))then |
o_ip_rx_err_out <= x"7"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
end if; |
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if(s_cnt_ip_rx=34) then |
s_dst_ip_ip_rx(7 downto 0) <= i_mac_data_in; |
st_RX_IP_STATE <= USER_DATA; |
if ((i_mac_data_in /= i_our_ip_address(7 downto 0)))then |
o_ip_rx_err_out <= x"7"; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
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if (s_data_len_ip_rx=x"0000") then |
st_RX_IP_STATE <= WAIT_END; |
end if; |
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s_broadcast_ip_rx <= '0'; |
if ((s_dst_ip_ip_rx(31 downto 8) & i_mac_data_in) = c_IP_BC_ADDR) then |
s_broadcast_ip_rx <= '1'; |
end if; |
end if; |
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------------------------------------------------------------------------------------------------------- |
if (i_mac_data_in_last = '1') then |
s_cnt_ip_rx <= x"0001"; |
--status |
-- s_src_ip_ip_rx <= (others => '0'); |
-- s_dst_ip_ip_rx <= (others => '0'); |
-- s_data_len_ip_rx <= (others => '0'); |
-- s_protocol_ip_rx <= (others => '0'); |
s_broadcast_ip_rx <= '0'; |
--error status |
o_ip_rx_err_out <= x"2"; |
st_RX_IP_STATE <= IDLE; |
end if; |
-------------------------------------------------------------------------------------------------------- |
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end if; |
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--************************************************************************************************************************************ |
WHEN USER_DATA => |
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o_ip_dout <= i_mac_data_in ; |
o_ip_dout_rdy <= i_mac_data_in_valid ; |
o_ip_data_last <= i_mac_data_in_last; |
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if (i_mac_data_in_valid = '1') then |
----------------------------------------------- |
s_cnt_ip_rx <= s_cnt_ip_rx+1; |
if (s_cnt_ip_rx = (s_data_len_ip_rx+34)) then |
o_ip_data_last <= '1'; |
st_RX_IP_STATE <= WAIT_END; |
end if; |
----------------------------------------------- |
if (i_mac_data_in_last = '1') then |
s_cnt_ip_rx <= x"0001"; |
st_RX_IP_STATE <= IDLE; |
--status |
-- s_src_ip_ip_rx <= (others => '0'); |
-- s_dst_ip_ip_rx <= (others => '0'); |
-- s_data_len_ip_rx <= (others => '0'); |
-- s_protocol_ip_rx <= (others => '0'); |
s_broadcast_ip_rx <= '0'; |
--error status |
if (s_cnt_ip_rx < (s_data_len_ip_rx+34)) then |
o_ip_rx_err_out <= x"2"; |
end if; |
end if; |
------------------------------------------------ |
end if; |
|
--******************************************************************************************************************************************* |
WHEN WAIT_END => |
if ( i_mac_data_in_valid = '1') then |
if ( i_mac_data_in_last = '1') then |
s_cnt_ip_rx <= x"0001"; |
--status |
-- s_src_ip_ip_rx <= (others => '0'); |
-- s_dst_ip_ip_rx <= (others => '0'); |
-- s_data_len_ip_rx <= (others => '0'); |
-- s_protocol_ip_rx <= (others => '0'); |
s_broadcast_ip_rx <= '0'; |
--error status |
o_ip_rx_err_out <= x"0"; |
st_RX_IP_STATE <= IDLE; |
end if; |
end if; |
|
END CASE; |
--******************************************************************************************************************************************* |
end if; |
end if; |
end process p_recieve_data; |
|
--================================================================================================================================================ |
-- my_ila_Phy : entity work.ila_0 |
-- PORT MAP ( |
-- clk => i_rx_clk, |
|
-- probe0(27 downto 0) => (others => '0'), |
-- probe0(31 downto 28) => o_ip_rx_err_out, |
|
-- probe0(39 downto 32) => (others => '0'), --i_ip_protocol, |
-- probe0(40) => i_mac_data_in_last , |
-- probe0(41) => i_mac_data_in_valid , |
-- probe0(49 downto 42) => i_mac_data_in, |
|
-- probe0(57 downto 50) => o_ip_dout, |
-- probe0(58) => o_ip_dout_rdy, |
-- probe0(59) => o_ip_data_last, |
|
-- probe0(255 downto 60) => (others => '0') |
-- ); |
|
|
end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/IP_TX.vhd
0,0 → 1,822
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
|
library work; |
--use work.signal_Package.all; |
|
|
entity IPv4_TX is |
generic ( |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF" |
); |
port ( |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
|
--for IP Header |
i_protocol : in std_logic_vector (7 downto 0); |
i_data_length : in std_logic_vector (15 downto 0); -- app data + 8(udp header) |
i_ip_tx_fragmantation : in std_logic_vector (15 downto 0):=x"4000"; --DF |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
i_our_mac_addr : in std_logic_vector (47 downto 0); |
i_dst_ip_addr : in std_logic_vector (31 downto 0); |
|
-- for receive data from udp layer |
i_ip_tx_start : in std_logic; |
o_ip_tx_ready : out std_logic; |
i_data_in : in std_logic_vector (7 downto 0); |
|
-- for transfer & receive data with arp block |
o_lookup_req : out std_logic; |
o_lookup_ip : out std_logic_vector (31 downto 0); |
i_lookup_mac_addr : in std_logic_vector (47 downto 0); |
i_lookup_mac_got : in std_logic; |
i_lookup_mac_err : in std_logic; |
|
-- for transfer data to mac layer |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0); |
s_TX_LL_SOF_N_0 : out std_logic; |
--error status |
o_ip_tx_err_out : out std_logic_vector (3 downto 0) |
|
); |
end IPv4_TX; |
|
|
architecture Behavioral of IPv4_TX is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
|
|
--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
|
|
--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
|
--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
|
--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
|
--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
|
|
--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
|
signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
|
|
|
--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
|
signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
|
|
--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
|
-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
|
-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
|
-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
|
|
|
--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
|
signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
|
signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
|
signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
|
|
|
signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
|
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|
--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
|
--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
|
|
--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
|
signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
|
|
signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
|
signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
|
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
|
|
--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
|
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
|
|
--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
|
|
--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
|
|
signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
|
signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
|
signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
|
|
signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
|
constant c_Flag_and_offset : std_logic_vector (15 downto 0):=x"4000"; -- Flag & offset |
|
signal s_ip_tx_fragmantation : std_logic_vector (15 downto 0):=x"0000"; |
|
|
--========================== Function for IP_Checksum Calculate ======================================== |
function inv_if_one(s1 : std_logic_vector; en : std_logic) return std_logic_vector is |
variable Z : std_logic_vector(s1'high downto s1'low); |
begin |
for i in (s1'low) to s1'high loop |
Z(i) := en xor s1(i); |
end loop; |
return Z; |
end inv_if_one; |
--====================================================================================================== |
|
begin |
--======================== immediate transfering data to mac & udp layers ============================== |
o_mac_tdata <= s_ip_header when (s_cnt_ip_tx<=34) else i_data_in when (s_cnt_ip_tx > 34 and s_cnt_ip_tx <=(34+i_data_length)) else (others=>'0'); |
o_ip_tx_ready <= i_mac_tready when (s_cnt_ip_tx >= 34 and s_cnt_ip_tx <(34+i_data_length)) else '0'; |
s_total_length <= std_logic_vector(unsigned(i_data_length) + 20); |
--====================================================================================================== |
--s_ip_tx_fragmantation <= "00" & i_ip_tx_fragmantation(13 downto 0); |
s_ip_tx_fragmantation <= i_ip_tx_fragmantation; |
--=================================== Transmit IP Data ================================================= |
p_transmission_data:process(i_tx_clk) |
begin |
if(rising_edge(i_tx_clk)) then |
if (i_reset='1') then |
|
st_tx_ip_state <=IDLE; |
s_cnt_ip_tx <=(others=>'0'); |
s_cal_cheksum <= '0'; |
|
--for arp |
o_lookup_req <= '0'; |
o_lookup_ip <=(others=>'0'); |
s_dst_mac_addr <=(others=>'0'); |
|
--for mac |
o_mac_tx_req <= '0'; |
o_mac_tvalid <= '0'; |
o_mac_tlast <= '0'; |
s_ip_header <=(others=>'0'); |
s_TX_LL_SOF_N_0 <= '1'; |
|
--Error status |
o_ip_tx_err_out <=(others=>'0'); |
|
else |
|
case st_tx_ip_state is |
when IDLE => |
|
s_cnt_ip_tx <=(others=>'0'); |
s_cal_cheksum <= '0'; |
|
--for arp |
o_lookup_req <= '0'; |
o_lookup_ip <=(others=>'0'); |
s_dst_mac_addr <=(others=>'0'); |
|
--for mac |
o_mac_tx_req <= '0'; |
o_mac_tvalid <= '0'; |
s_TX_LL_SOF_N_0 <= '1'; |
o_mac_tlast <= '0'; |
s_ip_header <=(others=>'0'); |
|
--error status |
o_ip_tx_err_out <=(others=>'0'); |
|
if i_ip_tx_start = '1' then |
s_cal_cheksum <= '1'; |
------------------------------------- |
if (i_dst_ip_addr = c_IP_BC_ADDR) then |
s_dst_mac_addr <= c_MAC_BC_ADDR; |
o_mac_tx_req <= '1'; |
st_tx_ip_state <= WAIT_CHN; |
else |
o_lookup_req <= '1'; |
o_lookup_ip <= i_dst_ip_addr; |
st_tx_ip_state <= WAIT_MAC_ADDR; |
end if; |
|
if (unsigned(i_data_length) > 1480) then |
o_ip_tx_err_out <= x"1"; |
s_cal_cheksum <= '0'; |
st_tx_ip_state <= IDLE; |
end if; |
-------------------------------------- |
end if; |
|
when WAIT_MAC_ADDR => -- wait for achieve s_dst_mac_addr by arp block |
|
s_cal_cheksum <= '0'; |
o_lookup_req <= '0'; |
|
--use ARP Block |
if (g_GENERATE_ARP_MODULE) then |
-- if i_lookup_mac_got = '1' then |
s_dst_mac_addr <= i_lookup_mac_addr; |
o_mac_tx_req <= '1'; |
st_tx_ip_state <= WAIT_CHN; |
-- end if; |
if i_lookup_mac_err = '1' then |
o_ip_tx_err_out <= x"2"; |
-- st_tx_ip_state <= IDLE; |
end if; |
|
--use Defualt MAC Addr |
else |
s_dst_mac_addr <= g_DEFAULT_DST_MAC_ADDR; |
o_mac_tx_req <= '1'; |
st_tx_ip_state <= WAIT_CHN; |
end if; |
|
when WAIT_CHN => |
|
s_cal_cheksum <= '0'; |
if i_mac_tx_granted = '1' then |
st_tx_ip_state <= SEND_DATA; |
end if; |
|
when SEND_DATA => |
|
s_TX_LL_SOF_N_0 <= '1'; |
|
if (s_cnt_ip_tx=x"0000") then |
s_ip_header <= s_dst_mac_addr (47 downto 40); |
s_cnt_ip_tx <= s_cnt_ip_tx+1; |
o_mac_tvalid <= '1'; |
s_TX_LL_SOF_N_0 <= '0'; |
|
end if; |
|
|
if (i_mac_tready='1') then |
--************************************************************************************** |
s_cnt_ip_tx <= s_cnt_ip_tx+1; |
case s_cnt_ip_tx is |
when X"0001" => s_ip_header <= s_dst_mac_addr (39 downto 32); |
when X"0002" => s_ip_header <= s_dst_mac_addr (31 downto 24); |
when X"0003" => s_ip_header <= s_dst_mac_addr (23 downto 16); |
when X"0004" => s_ip_header <= s_dst_mac_addr (15 downto 8); |
when X"0005" => s_ip_header <= s_dst_mac_addr (7 downto 0); |
when X"0006" => s_ip_header <= i_our_mac_addr (47 downto 40); |
when X"0007" => s_ip_header <= i_our_mac_addr (39 downto 32); |
when X"0008" => s_ip_header <= i_our_mac_addr (31 downto 24); |
when X"0009" => s_ip_header <= i_our_mac_addr (23 downto 16); |
when X"000A" => s_ip_header <= i_our_mac_addr (15 downto 8); |
when X"000B" => s_ip_header <= i_our_mac_addr (7 downto 0); |
when X"000C" => s_ip_header <= x"08"; --ip farme type |
when X"000D" => s_ip_header <= x"00"; --ip frame type |
when X"000E" => s_ip_header <= x"45"; --ip i_protocol type(ipv4) |
when X"000F" => s_ip_header <= x"00"; --identification |
when X"0010" => s_ip_header <= s_total_length(15 downto 8); --s_total_length is udpdata+20(ip header) |
when X"0011" => s_ip_header <= s_total_length(7 downto 0); --s_total_length is udpdata+20(ip header) |
when X"0012" => s_ip_header <= x"00"; --identification |
when X"0013" => s_ip_header <= x"00"; --identification |
when X"0014" => s_ip_header <= s_ip_tx_fragmantation (15 downto 8); --fragmention |
when X"0015" => s_ip_header <= s_ip_tx_fragmantation (7 downto 0); --fragmention |
when X"0016" => s_ip_header <= c_IP_TTL; --time to live |
when X"0017" => s_ip_header <= i_protocol; --udp i_protocol |
when X"0018" => s_ip_header <= s_tx_hdr_cks (15 downto 8); |
when X"0019" => s_ip_header <= s_tx_hdr_cks (7 downto 0); |
when X"001A" => s_ip_header <= i_our_ip_addr (31 downto 24); |
when X"001B" => s_ip_header <= i_our_ip_addr (23 downto 16); |
when X"001C" => s_ip_header <= i_our_ip_addr (15 downto 8); |
when X"001D" => s_ip_header <= i_our_ip_addr (7 downto 0); |
when X"001E" => s_ip_header <= i_dst_ip_addr (31 downto 24); |
when X"001F" => s_ip_header <= i_dst_ip_addr (23 downto 16); |
when X"0020" => s_ip_header <= i_dst_ip_addr (15 downto 8); |
when X"0021" => s_ip_header <= i_dst_ip_addr (7 downto 0); |
when others => null; |
end case; |
|
if (s_cnt_ip_tx=i_data_length+34-1) then --i_data_length is udp data length |
o_mac_tlast <= '1'; |
end if; |
--********************************************************************************************* |
end if; |
|
if (s_cnt_ip_tx=i_data_length+34) then |
s_cnt_ip_tx <= (others=>'0'); |
o_mac_tx_req <= '0'; |
o_mac_tvalid <= '0'; |
o_mac_tlast <= '0'; |
s_ip_header <= (others=>'0'); |
st_tx_ip_state <= IDLE; |
end if; |
|
END CASE; |
|
end if; |
end if; |
end process p_transmission_data; |
--=========================================================================================================================== |
|
--=========================== IP_Checksum Calculate ========================================================================= |
crc : process (i_tx_clk) |
begin |
if rising_edge(i_tx_clk) then |
if (i_reset='1') then |
st_crc_state <=IDLE; |
s_tx_hdr_cks <=(others=>'0'); |
else |
case st_crc_state is |
when IDLE => |
if s_cal_cheksum = '1' then |
s_tx_hdr_cks <= x"004500"; |
st_crc_state <= TOT_LEN; |
end if; |
|
when TOT_LEN => |
s_tx_hdr_cks <= std_logic_vector (unsigned(s_tx_hdr_cks) + unsigned(s_total_length)); |
st_crc_state <= ID; |
|
when ID => |
s_tx_hdr_cks <= (x"00"&x"0000") + s_tx_hdr_cks; |
st_crc_state <= FLAGS; |
|
when FLAGS => |
s_tx_hdr_cks <= (x"00"&s_ip_tx_fragmantation) + s_tx_hdr_cks; |
st_crc_state <= TTL; |
|
when TTL => |
s_tx_hdr_cks <= std_logic_vector (unsigned(s_tx_hdr_cks) + unsigned(c_IP_TTL & i_protocol)); |
st_crc_state <= CKS; |
|
when CKS => |
s_tx_hdr_cks <= s_tx_hdr_cks; |
st_crc_state <= SAH; |
|
when SAH => |
s_tx_hdr_cks <= std_logic_vector (unsigned(s_tx_hdr_cks) + unsigned(i_our_ip_addr(31 downto 16))); |
st_crc_state <= SAL; |
|
when SAL => |
s_tx_hdr_cks <= std_logic_vector (unsigned(s_tx_hdr_cks) + unsigned(i_our_ip_addr(15 downto 0))); |
st_crc_state <= DAH; |
|
when DAH => |
s_tx_hdr_cks <= std_logic_vector (unsigned(s_tx_hdr_cks) + unsigned(i_dst_ip_addr(31 downto 16))); |
st_crc_state <= DAL; |
|
when DAL => |
s_tx_hdr_cks <= std_logic_vector (unsigned(s_tx_hdr_cks) + unsigned(i_dst_ip_addr(15 downto 0))); |
st_crc_state <= ADDOVF; |
|
when ADDOVF => |
s_tx_hdr_cks <= std_logic_vector ((unsigned(s_tx_hdr_cks) and x"00ffff")+ unsigned(s_tx_hdr_cks(23 downto 16))); |
st_crc_state <= FINAL; |
|
when FINAL => |
s_tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(s_tx_hdr_cks) + unsigned(s_tx_hdr_cks(23 downto 16))), '1'); |
st_crc_state <= WAIT_END; |
|
when WAIT_END => |
s_tx_hdr_cks <= s_tx_hdr_cks; |
if s_cal_cheksum = '0' then |
st_crc_state <= IDLE; |
else |
st_crc_state <= WAIT_END; |
end if; |
|
end case; |
end if; |
end if; |
end process; |
--=========================================================================================================================== |
|
end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/IPv4.vhd
0,0 → 1,725
--**************************************************************************************** |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
|
library work; |
use work.signal_Package.all; |
|
entity IPv4 is |
generic ( |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF" |
); |
Port ( |
i_rx_clk : in STD_LOGIC; |
i_tx_clk : in STD_LOGIC; |
i_reset : in STD_LOGIC; |
|
--************************************ TX ********************************** |
-- Tx header construction |
i_ip_tx_src_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_dst_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_data_len : in std_logic_vector (15 downto 0); |
i_ip_tcp_tx_id : in std_logic_vector (15 downto 0):=(others => '0'); |
i_ip_tx_fragmantation : in std_logic_vector(15 downto 0); |
i_ip_tx_protocol : in std_logic_vector (7 downto 0); |
i_ip_tx_src_mac : in std_logic_vector (47 downto 0); |
|
-- TX Inputs |
i_ip_tx_start : in std_logic; |
o_ip_tx_rdy : out std_logic; |
i_ip_tx_din : in std_logic_vector (7 downto 0); |
|
-- TX Outputs |
i_mac_tx_tready : in std_logic; |
o_mac_tx_tvalid : out std_logic; |
o_mac_tx_tlast : out std_logic; |
o_mac_tx_tdata : out std_logic_vector (7 downto 0); |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
|
-- TX & ARP inouts |
o_lookup_req : out std_logic; |
o_lookup_ip : out std_logic_vector (31 downto 0); |
i_lookup_mac_addr : in std_logic_vector (47 downto 0); |
i_lookup_mac_got : in std_logic; |
i_lookup_mac_err : in std_logic; |
|
-- Error Status |
o_ip_tx_err_out : out std_logic_vector (3 downto 0); |
|
--******************************* RX *************************************** |
--RX Inputs |
i_mac_rx_tdata : in std_logic_vector(7 downto 0); |
i_mac_rx_tvalid : in std_logic; |
i_mac_rx_tlast : in std_logic; |
|
|
--RX Outputs |
o_ip_rx_dout : out std_logic_vector(7 downto 0); |
o_ip_rx_dout_rdy : out std_logic; |
o_ip_rx_dout_last : out std_logic; |
|
|
--RX Status Outputs |
o_ip_rx_src_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_dst_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_data_len : out std_logic_vector(15 downto 0); |
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
o_ip_rx_protocol : out std_logic_vector(7 downto 0); |
o_ip_rx_broadcast : out std_logic; |
|
-- Error Status |
o_no_ping_packet : out std_logic; |
o_ip_rx_err_out : out std_logic_vector (3 downto 0) |
|
--**************************************************************************** |
); |
end IPv4; |
|
architecture structural of IPv4 is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
|
|
--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
|
|
--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
|
--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
|
--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
|
--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
|
|
--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
|
signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
|
|
|
--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
|
signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
|
|
--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
|
-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
|
-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
|
-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
|
|
|
--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
|
signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
|
signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
|
signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
|
|
|
signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
|
|
signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
|
signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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--========================= IPv4_TX ============================================= |
COMPONENT IPv4_TX |
generic ( |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF" |
); |
PORT( |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
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-- IP header construction |
i_protocol : in std_logic_vector (7 downto 0); |
i_data_length : in std_logic_vector (15 downto 0); |
i_ip_tx_fragmantation : in std_logic_vector(15 downto 0); |
i_our_ip_addr : in std_logic_vector (31 downto 0); |
i_our_mac_addr : in std_logic_vector (47 downto 0); |
i_dst_ip_addr : in std_logic_vector (31 downto 0); |
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-- IP inputs |
i_ip_tx_start : in std_logic; |
o_ip_tx_ready : out std_logic; |
i_data_in : in std_logic_vector (7 downto 0); |
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-- IP & ARP inouts |
o_lookup_req : out std_logic; |
o_lookup_ip : out std_logic_vector (31 downto 0); |
i_lookup_mac_addr : in std_logic_vector (47 downto 0); |
i_lookup_mac_got : in std_logic; |
i_lookup_mac_err : in std_logic; |
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-- IP Outputs |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0); |
o_ip_tx_err_out : out std_logic_vector (3 downto 0) |
); |
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END COMPONENT; |
--=============================================================================== |
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--============================ IPv4_RX ======================================== |
COMPONENT IPv4_RX |
PORT( |
-- system signals |
i_rx_clk : in std_logic; |
i_reset : in std_logic; |
i_our_ip_address : in std_logic_vector (31 downto 0); |
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-- MAC layer RX inputs |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
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-- Outputs to udp layer |
o_ip_dout : out std_logic_vector(7 downto 0); |
o_ip_dout_rdy : out std_logic; |
o_ip_data_last : out std_logic; |
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--Status Outputs |
o_src_ip : out std_logic_vector(31 downto 0); |
o_dst_ip : out std_logic_vector(31 downto 0); |
o_data_len : out std_logic_vector(15 downto 0); |
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
o_protocol : out std_logic_vector(7 downto 0); |
o_broadcast : out std_logic; |
--error status |
o_no_ping_packet : out std_logic; |
o_ip_rx_err_out : out std_logic_vector (3 downto 0) |
); |
END COMPONENT; |
--====================================================================================== |
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begin |
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--========================= IPv4_TX ==================================================== |
inst_IPv4_TX :IPv4_TX |
generic map ( |
g_GENERATE_ARP_MODULE => g_GENERATE_ARP_MODULE, |
g_DEFAULT_DST_MAC_ADDR => g_DEFAULT_DST_MAC_ADDR |
) |
PORT MAP ( |
i_tx_clk => i_tx_clk, |
i_reset => i_reset, |
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-- IP header construction |
i_protocol => i_ip_tx_protocol, |
i_data_length => i_ip_tx_data_len, |
i_our_ip_addr => i_ip_tx_src_ip, |
i_ip_tx_fragmantation => i_ip_tx_fragmantation, |
i_our_mac_addr => i_ip_tx_src_mac, |
i_dst_ip_addr => i_ip_tx_dst_ip, |
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-- IP inputs |
i_ip_tx_start => i_ip_tx_start, |
o_ip_tx_ready => o_ip_tx_rdy, |
i_data_in => i_ip_tx_din, |
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-- IP & ARP inouts |
o_lookup_req => o_lookup_req, |
o_lookup_ip => o_lookup_ip, |
i_lookup_mac_addr => i_lookup_mac_addr, |
i_lookup_mac_got => i_lookup_mac_got, |
i_lookup_mac_err => i_lookup_mac_err, |
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-- IP Outputs |
i_mac_tready => i_mac_tx_tready, |
o_mac_tvalid => o_mac_tx_tvalid, |
o_mac_tlast => o_mac_tx_tlast, |
o_mac_tdata => o_mac_tx_tdata, |
o_mac_tx_req => o_mac_tx_req, |
i_mac_tx_granted => i_mac_tx_granted, |
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o_ip_tx_err_out => o_ip_tx_err_out |
); |
--===================================================================================== |
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--========================= IPv4_RX =================================================== |
inst_IPv4_RX :IPv4_RX PORT MAP ( |
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i_rx_clk => i_rx_clk, |
i_reset => i_reset, |
i_our_ip_address => i_ip_tx_src_ip, |
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i_mac_data_in => i_mac_rx_tdata, |
i_mac_data_in_valid => i_mac_rx_tvalid, |
i_mac_data_in_last => i_mac_rx_tlast, |
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o_ip_dout => o_ip_rx_dout, |
o_ip_dout_rdy => o_ip_rx_dout_rdy, |
o_ip_data_last => o_ip_rx_dout_last, |
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o_src_ip => o_ip_rx_src_ip, |
o_dst_ip => o_ip_rx_dst_ip, |
o_data_len => o_ip_rx_data_len, |
o_ip_rx_fragmantation => o_ip_rx_fragmantation, |
o_protocol => o_ip_rx_protocol, |
o_broadcast => o_ip_rx_broadcast, |
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o_ip_rx_err_out => o_ip_rx_err_out, |
o_no_ping_packet => o_no_ping_packet |
); |
--===================================================================================== |
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end structural; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/PING.vhd
0,0 → 1,862
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
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library work; |
use work.signal_Package.all; |
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entity ping is |
port ( |
-- system signals |
i_tx_clk : in std_logic; |
i_rx_clk : in std_logic; |
i_reset : in std_logic; |
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-- MAC layer RX inputs |
i_mac_data_in : in std_logic_vector (7 downto 0); |
i_mac_data_in_valid : in std_logic; |
i_mac_data_in_last : in std_logic; |
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-- IP_RX output and status |
i_ip_rx_err_in : in std_logic_vector(3 downto 0); |
i_no_ping_packet : in std_logic; |
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Status_indc : buffer std_logic_vector(7 downto 0):=x"BB"; |
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-- for transfer data to mac layer |
o_mac_tx_req : out std_logic; |
i_mac_tx_granted : in std_logic; |
i_mac_tready : in std_logic; |
o_mac_tvalid : out std_logic; |
o_mac_tlast : out std_logic; |
o_mac_tdata : out std_logic_vector (7 downto 0) |
); |
end ping; |
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architecture Behavioral of ping is |
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--======== FIFO for Saving Ping Data from Mac Layer ========================================== |
component ping_fifo IS |
PORT ( |
rst : IN STD_LOGIC; |
wr_clk : IN STD_LOGIC; |
rd_clk : IN STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
wr_en : IN STD_LOGIC; |
rd_en : IN STD_LOGIC; |
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
full : OUT STD_LOGIC; |
empty : OUT STD_LOGIC; |
valid : OUT STD_LOGIC |
); |
END component; |
--============================================================================================ |
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--=========Sync FIFO for Convert RX_CLK Domain Signals to TX_CLK Domain Signals=============== |
component sync_fifo_ping IS |
PORT ( |
rst : IN STD_LOGIC; |
wr_clk : IN STD_LOGIC; |
rd_clk : IN STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
wr_en : IN STD_LOGIC; |
rd_en : IN STD_LOGIC; |
dout : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
full : OUT STD_LOGIC; |
empty : OUT STD_LOGIC; |
valid : OUT STD_LOGIC |
); |
END component; |
--=========================================================================================== |
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--======== Ping Checksum Calculator ========================================================= |
component ping_cheksum_calc is |
port |
( |
i_clk : in std_logic; |
i_reset : in std_logic; |
i_din : in std_logic_vector(7 downto 0); |
i_din_rdy : in std_logic; |
i_start_calc : in std_logic; |
i_stop_calc : in std_logic; |
o_checksum_valid : out std_logic; |
o_checksum : out std_logic_vector(15 downto 0) |
); |
end component; |
--=========================================================================================== |
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--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
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--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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begin |
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---------------------------------------TX Data--------------------------------------- |
s_rd_en_fifo_ping <= (i_mac_tready or s_start_send) when (st_PING_STATE=SEND_DATA) else '0'; |
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--================== Swapping Address for Reply Ping Packet ========================= |
o_mac_tdata <= s_src_mac_ping(47 downto 40) when (s_rd_cnt=1) else |
s_src_mac_ping(39 downto 32) when (s_rd_cnt=2) else |
s_src_mac_ping(31 downto 24) when (s_rd_cnt=3) else |
s_src_mac_ping(23 downto 16) when (s_rd_cnt=4) else |
s_src_mac_ping(15 downto 8) when (s_rd_cnt=5) else |
s_src_mac_ping(7 downto 0) when (s_rd_cnt=6) else |
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s_dst_mac_ping(47 downto 40) when (s_rd_cnt=7) else |
s_dst_mac_ping(39 downto 32) when (s_rd_cnt=8) else |
s_dst_mac_ping(31 downto 24) when (s_rd_cnt=9) else |
s_dst_mac_ping(23 downto 16) when (s_rd_cnt=10) else |
s_dst_mac_ping(15 downto 8) when (s_rd_cnt=11) else |
s_dst_mac_ping(7 downto 0) when (s_rd_cnt=12) else |
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s_dst_ip_ping(31 downto 24) when (s_rd_cnt=27) else |
s_dst_ip_ping(23 downto 16) when (s_rd_cnt=28) else |
s_dst_ip_ping(15 downto 8) when (s_rd_cnt=29) else |
s_dst_ip_ping(7 downto 0) when (s_rd_cnt=30) else |
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s_src_ip_ping(31 downto 24) when (s_rd_cnt=31) else |
s_src_ip_ping(23 downto 16) when (s_rd_cnt=32) else |
s_src_ip_ping(15 downto 8) when (s_rd_cnt=33) else |
s_src_ip_ping(7 downto 0) when (s_rd_cnt=34) else |
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x"00" when (s_rd_cnt=35) else |
s_checksum_data_out(15 downto 8) when (s_rd_cnt=37) else |
s_checksum_data_out(7 downto 0) when (s_rd_cnt=38) else |
(s_dout_fifo_ping); |
--=================================================================================== |
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--========================== Checksum Trig & Data =================================== |
s_checksum_start_calc <= '1' when (s_wr_cnt=33) else '0'; |
s_checksum_stop_calc <= '1' when (s_mac_data_in_last_d='1') else '0'; |
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s_checksum_data_in <= x"00" when (s_wr_cnt=34) else |
x"00" when (s_wr_cnt=36) else |
x"00" when (s_wr_cnt=37) else |
s_mac_data_in; |
--=================================================================================== |
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--======================== Delay in Rx_Data ========================================= |
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p_delay:process(i_rx_clk) |
begin |
if rising_edge(i_rx_clk) then |
s_mac_data_in_r <= i_mac_data_in; |
s_mac_data_in_valid_r <= i_mac_data_in_valid; |
s_mac_data_in_last_r <= i_mac_data_in_last; |
end if; |
end process p_delay; |
--=================================================================================== |
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--======================= Sync_fifo ================================================= |
s_ip_rx_in <= i_ip_rx_err_in & i_no_ping_packet & s_mac_data_in_last_r & s_mac_data_in_valid_r & s_mac_data_in_r; |
s_ip_rx_err_in <= s_ip_rx_out(14 downto 11); |
s_no_ping_data <= s_ip_rx_out(10); |
s_mac_data_in_last <= s_ip_rx_out(9); |
s_mac_data_in <= s_ip_rx_out(7 downto 0); |
s_not_empty_sync_fifo <= not(s_empty_sync_fifo); |
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inst_sync_fifo_ping: sync_fifo_ping |
PORT map ( |
rst => i_reset, |
wr_clk => i_rx_clk, |
rd_clk => i_tx_clk, |
din => s_ip_rx_in, |
wr_en => s_mac_data_in_valid_r, |
rd_en => s_not_empty_sync_fifo, |
dout => s_ip_rx_out, |
full => open, |
empty => s_empty_sync_fifo, |
valid => s_mac_data_in_valid |
); |
--=================================================================================== |
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--======================== Acquire Src & Dst Address ================================ |
p_acquire_address:process(i_tx_clk) |
begin |
if rising_edge(i_tx_clk) then |
if ( s_mac_data_in_valid = '1') then |
case s_wr_cnt is |
--dst mac addr |
when x"00" => s_dst_mac_ping(47 downto 40) <= s_mac_data_in; |
when x"01" => s_dst_mac_ping(39 downto 32) <= s_mac_data_in; |
when x"02" => s_dst_mac_ping(31 downto 24) <= s_mac_data_in; |
when x"03" => s_dst_mac_ping(23 downto 16) <= s_mac_data_in; |
when x"04" => s_dst_mac_ping(15 downto 8) <= s_mac_data_in; |
when x"05" => s_dst_mac_ping(7 downto 0) <= s_mac_data_in; |
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--src mac addr |
when x"06" => s_src_mac_ping(47 downto 40) <= s_mac_data_in; |
when x"07" => s_src_mac_ping(39 downto 32) <= s_mac_data_in; |
when x"08" => s_src_mac_ping(31 downto 24) <= s_mac_data_in; |
when x"09" => s_src_mac_ping(23 downto 16) <= s_mac_data_in; |
when x"0a" => s_src_mac_ping(15 downto 8) <= s_mac_data_in; |
when x"0b" => s_src_mac_ping(7 downto 0) <= s_mac_data_in; |
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--src ip addr |
when x"1a" => s_src_ip_ping(31 downto 24) <= s_mac_data_in; |
when x"1b" => s_src_ip_ping(23 downto 16) <= s_mac_data_in; |
when x"1c" => s_src_ip_ping(15 downto 8) <= s_mac_data_in; |
when x"1d" => s_src_ip_ping(7 downto 0) <= s_mac_data_in; |
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--dst ip addr |
when x"1e" => s_dst_ip_ping(31 downto 24) <= s_mac_data_in; |
when x"1f" => s_dst_ip_ping(23 downto 16) <= s_mac_data_in; |
when x"20" => s_dst_ip_ping(15 downto 8) <= s_mac_data_in; |
when x"21" => s_dst_ip_ping(7 downto 0) <= s_mac_data_in; |
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when others => null; |
end case; |
end if; |
end if; |
end process p_acquire_address; |
--=================================================================================== |
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--================== Receive & Process & Transmit Ping Packets====================== |
p_recieve_transmit_ping_data:process(i_tx_clk) |
begin |
if(rising_edge(i_tx_clk)) then |
s_wr_en_fifo_ping <= '0'; |
s_rst_fifo_ping <= '0'; |
s_start_send <= '0'; |
s_mac_data_in_last_d <= s_mac_data_in_last; |
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Status_indc <= x"A1"; |
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if (i_reset='1') then |
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s_rst_fifo_ping <= '1'; |
s_wr_cnt <= (others=>'0'); |
s_rd_cnt <= (others=>'0'); |
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o_mac_tlast <= '0'; |
o_mac_tvalid <= '0'; |
o_mac_tx_req <= '0'; |
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st_PING_STATE <= IDLE; |
Status_indc <= x"FF"; |
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else |
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CASE st_PING_STATE IS |
--============================================================================================= |
WHEN IDLE => |
Status_indc <= x"01"; |
if (s_mac_data_in_valid = '1') then |
st_PING_STATE <= ACQUIRE_DATA; |
s_wr_en_fifo_ping <= '1'; |
s_din_fifo_ping <= s_mac_data_in; |
s_wr_cnt <= s_wr_cnt+1; |
end if; |
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---------------------------------------------------- |
WHEN ACQUIRE_DATA => |
Status_indc <= x"02"; |
if (s_mac_data_in_valid = '1') then |
s_wr_en_fifo_ping <= '1'; |
s_din_fifo_ping <= s_mac_data_in; |
s_wr_cnt <= s_wr_cnt+1; |
if (s_mac_data_in_last = '1') then |
st_PING_STATE <= WAIT_CHN; |
end if; |
if ((s_wr_cnt=34) and (s_mac_data_in/=x"08")) then |
s_rst_fifo_ping <= '1'; |
st_PING_STATE <= WAIT_END; |
end if; |
end if; |
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if (s_ip_rx_err_in/="0000") then |
s_rst_fifo_ping <= '1'; |
st_PING_STATE <= WAIT_END; |
if (s_mac_data_in_last = '1') then |
st_PING_STATE <= IDLE; |
end if; |
end if; |
|
if (s_no_ping_data='1') then |
s_rst_fifo_ping <= '1'; |
st_PING_STATE <= WAIT_END; |
if (s_mac_data_in_last = '1') then |
st_PING_STATE <= IDLE; |
end if; |
end if; |
|
----------------------------------------------------- |
WHEN WAIT_END => |
Status_indc <= x"03"; |
if (s_mac_data_in_valid = '1') then |
if (s_mac_data_in_last = '1') then |
s_wr_cnt <= (others=>'0'); |
s_rd_cnt <= (others=>'0'); |
st_PING_STATE <= IDLE; |
end if; |
end if; |
|
----------------------------------------------------- |
WHEN WAIT_CHN => |
Status_indc <= x"04"; |
o_mac_tx_req <= '1'; |
if (i_mac_tx_granted = '1') then |
st_PING_STATE <= SEND_DATA; |
s_start_send <= '1'; |
end if; |
|
------------------------------------------------------ |
WHEN SEND_DATA => |
Status_indc <= x"05"; |
if (s_rd_cnt=0) then |
s_rd_cnt <= s_rd_cnt+1; |
o_mac_tvalid <= '1'; |
end if; |
--------------------------------- |
if (i_mac_tready='1') then |
s_rd_cnt <= s_rd_cnt+1; |
if (s_rd_cnt=s_wr_cnt-1) then |
o_mac_tlast <= '1'; |
end if; |
end if; |
--------------------------------- |
if (s_rd_cnt=s_wr_cnt) then |
s_rst_fifo_ping <= '1'; |
s_wr_cnt <= (others=>'0'); |
s_rd_cnt <= (others=>'0'); |
o_mac_tx_req <= '0'; |
o_mac_tvalid <= '0'; |
o_mac_tlast <= '0'; |
st_PING_STATE <= IDLE; |
end if; |
|
END CASE; |
end if; |
end if; |
end process p_recieve_transmit_ping_data; |
--============================================================================================ |
|
--======== FIFO for Saving Ping Data from Mac Layer ========================================== |
inst_ping_fifo :ping_fifo |
PORT map |
( |
rst => s_rst_fifo_ping, |
wr_clk => i_tx_clk, |
rd_clk => i_tx_clk, |
din => s_din_fifo_ping, |
wr_en => s_wr_en_fifo_ping, |
rd_en => s_rd_en_fifo_ping, |
dout => s_dout_fifo_ping, |
full => open, |
empty => open, |
valid => open |
); |
--============================================================================================ |
|
--=========Sync FIFO for Convert RX_CLK Domain Signals to TX_CLK Domain Signals=============== |
inst_ping_cheksum_calc:ping_cheksum_calc |
port map |
( |
i_clk => i_tx_clk, |
i_reset => i_reset, |
i_din => s_checksum_data_in, |
i_din_rdy => s_mac_data_in_valid, |
i_start_calc => s_checksum_start_calc, |
i_stop_calc => s_checksum_stop_calc, |
o_checksum_valid => open, |
o_checksum => s_checksum_data_out |
); |
--============================================================================================ |
|
end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/UDP_KED.vhd
0,0 → 1,949
--**************************************************************************************** |
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.NUMERIC_STD.all; |
|
library work; |
use work.signal_Package.all; |
|
|
|
entity UDP_KED is |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900"; --20S |
g_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector(31 downto 0):= x"07735940"; --1S |
g_RE_SEND_ARP_REQUEST : std_logic_vector(3 downto 0):= x"A"; --10 |
g_GENERATE_PING_MODULE : boolean := true; |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF" |
); |
port ( |
|
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset_rx : in std_logic; |
i_reset_tx : in std_logic; |
|
--******************************* IP *************************************** |
-- IP to MAC TX Outputs |
i_mac_tx_tready : in std_logic; |
o_mac_tx_tdata : out std_logic_vector(7 downto 0); |
o_mac_tx_tvalid : out std_logic; |
o_mac_tx_tlast : out std_logic; |
|
-- MAC to IP RX Inputs |
i_mac_rx_tdata : in std_logic_vector(7 downto 0); |
i_mac_rx_tvalid : in std_logic; |
i_mac_rx_tlast : in std_logic; |
|
|
-- IP Status Outputs |
-- o_ip_rx_src_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_dst_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_data_len : out std_logic_vector(15 downto 0); |
o_ip_rx_protocol : out std_logic_vector(7 downto 0); |
-- o_ip_rx_broadcast : out std_logic; |
o_ip_rx_err_out : out std_logic_vector (3 downto 0); |
o_ip_tx_err_out : out std_logic_vector (3 downto 0); |
o_arp_rx_err_out : out std_logic_vector (3 downto 0); |
|
--************************** udp********************************************* |
-- udp & IP Tx header construction |
i_udp_tx_src_ip : in std_logic_vector (31 downto 0); |
i_udp_tx_dst_ip : in std_logic_vector (31 downto 0); |
i_udp_tx_data_len : in std_logic_vector (15 downto 0); |
i_udp_tx_protocol : in std_logic_vector (7 downto 0); |
i_udp_tx_src_mac : in std_logic_vector (47 downto 0); |
i_udp_tx_checksum : in std_logic_vector (15 downto 0); |
i_udp_tx_src_port : in std_logic_vector (15 downto 0); |
i_udp_tx_dst_port : in std_logic_vector (15 downto 0); |
|
|
i_ip_tx_fragmantation : in std_logic_vector(15 downto 0):=x"4000"; |
i_fragment_len : in std_logic_vector(16 - 1 downto 0):=x"4000"; |
-- udp TX Inpus |
i_udp_tx_start : in std_logic; |
o_udp_tx_ready : out std_logic; |
i_udp_tx_din : in std_logic_vector (7 downto 0); |
|
o_lookup_mac_err : out std_logic; |
-- udp RX Outputs |
o_udp_rx_dout : out std_logic_vector(7 downto 0); |
o_udp_rx_dout_rdy : out std_logic; |
o_udp_rx_dout_last : out std_logic; |
|
o_arp_addr_valid : out std_logic; |
|
-- udp RX Status Outputs |
|
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
|
o_udp_rx_src_ip : out std_logic_vector(31 downto 0); |
o_udp_rx_src_port : out std_logic_vector(15 downto 0); |
o_udp_rx_dst_port : out std_logic_vector(15 downto 0); |
o_udp_rx_data_len : out std_logic_vector(15 downto 0); |
o_udp_rx_err_out : out std_logic_vector(3 downto 0); |
o_udp_tx_err_out : out std_logic_vector(3 downto 0) |
|
); |
end UDP_KED; |
|
architecture structural of UDP_KED is |
|
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
|
|
--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
|
|
--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
|
--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
|
--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
|
--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
|
|
--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
|
signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
|
|
|
--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
|
signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
|
|
--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
|
-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
|
-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
|
-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
|
|
|
--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
|
signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
|
signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
|
signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
|
|
|
signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
|
|
|
|
|
|
|
|
|
|
|
|
--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
|
|
signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
|
signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
|
|
|
|
|
|
|
|
|
|
--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
|
|
|
|
|
|
|
|
|
|
|
--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
|
--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
|
|
--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
|
|
|
|
|
|
|
|
|
|
|
--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
|
signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
|
|
signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
|
|
|
|
|
|
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|
|
|
|
--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
|
signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
|
|
signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
|
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|
|
|
|
|
|
--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
|
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|
|
--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
|
|
--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
|
|
--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
|
|
--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
|
|
--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
|
|
signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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|
--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
|
signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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|
--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
|
signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
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signal s_ip_rx_fragmantation : std_logic_vector(15 downto 0); |
--========================================================================================================================= |
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--=============================== IP ======================================================== |
component IP_ARP_PING |
generic ( |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900"; --20S |
g_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector(31 downto 0):= x"07735940"; --1S |
g_RE_SEND_ARP_REQUEST : std_logic_vector(3 downto 0):= x"A"; --10 |
g_GENERATE_PING_MODULE : boolean := true; |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF" |
); |
port( |
i_rx_clk : in std_logic; |
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
|
--******************************* TX *************************************** |
-- Tx header construction |
i_ip_tx_src_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_dst_ip : in std_logic_vector (31 downto 0); |
i_ip_tx_data_len : in std_logic_vector (15 downto 0); |
i_ip_tx_protocol : in std_logic_vector (7 downto 0); |
i_ip_tx_src_mac : in std_logic_vector (47 downto 0); |
i_ip_tx_fragmantation : in std_logic_vector(15 downto 0); |
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-- TX Inputs |
i_ip_tx_start : in std_logic; |
o_ip_tx_rdy : out std_logic; |
i_ip_tx_din : in std_logic_vector (7 downto 0); |
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-- TX Outputs |
i_mac_tx_tready : in std_logic; |
o_mac_tx_tdata : out std_logic_vector(7 downto 0); |
o_mac_tx_tvalid : out std_logic; |
o_mac_tx_tlast : out std_logic; |
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-- Error Status |
o_ip_tx_err_out : out std_logic_vector (3 downto 0); |
o_lookup_mac_err : out std_logic; |
--******************************* RX *************************************** |
|
--RX Inputs |
i_mac_rx_tdata : in std_logic_vector(7 downto 0); |
i_mac_rx_tvalid : in std_logic; |
i_mac_rx_tlast : in std_logic; |
|
--RX Outputs |
o_ip_rx_dout : out std_logic_vector(7 downto 0); |
o_ip_rx_dout_rdy : out std_logic; |
o_ip_rx_dout_last : out std_logic; |
|
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--RX Status Outputs |
o_ip_rx_src_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_dst_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_data_len : out std_logic_vector(15 downto 0); |
o_ip_rx_protocol : out std_logic_vector(7 downto 0); |
o_ip_rx_broadcast : out std_logic; |
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
-- Error Status |
o_ip_rx_err_out : out std_logic_vector (3 downto 0); |
o_arp_rx_err_out : out std_logic_vector (3 downto 0) |
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); |
end component; |
--============================================================================================ |
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--====================================== udp RX ============================================== |
component udp_RX |
port ( |
|
-- system signals |
i_rx_clk : in std_logic; |
i_reset : in std_logic; |
|
-- IP layer RX inputs |
i_ip_data_in : in std_logic_vector (7 downto 0); |
i_ip_data_in_valid : in std_logic; |
i_ip_data_in_last : in std_logic; |
i_ip_protocol : in std_logic_vector (7 downto 0); |
i_ip_src_ip : in std_logic_vector (31 downto 0); |
i_fragmantation : in std_logic_vector (15 downto 0); |
|
-- Outputs |
o_udp_dout : out std_logic_vector(7 downto 0); |
o_udp_dout_rdy : out std_logic; |
o_udp_dout_last : out std_logic; |
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o_src_ip : out std_logic_vector(31 downto 0); |
o_src_port : out std_logic_vector(15 downto 0); |
o_dst_port : out std_logic_vector(15 downto 0); |
o_data_len : out std_logic_vector(15 downto 0); |
o_err_out : out std_logic_vector(3 downto 0) |
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); |
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end component; |
--============================================================================================= |
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--================================= udp TX ===================================================== |
component udp_TX |
port ( |
|
i_tx_clk : in std_logic; |
i_reset : in std_logic; |
|
----------------for IP header----------------------------- |
i_udp_src_ip : in std_logic_vector (31 downto 0); |
i_udp_dst_ip : in std_logic_vector (31 downto 0); |
i_udp_src_mac : in std_logic_vector (47 downto 0); |
i_udp_data_len : in std_logic_vector (15 downto 0); --application data length |
i_udp_protocol : in std_logic_vector (7 downto 0); --udp protocol, is x"11" |
i_fragmantation : in std_logic_vector(15 downto 0); |
i_fragment_len : in std_logic_vector(16 - 1 downto 0):=x"4000"; |
----------------for udp header----------------------------- |
i_udp_checksum : in std_logic_vector (15 downto 0); -- is x"00" |
i_udp_src_port : in std_logic_vector (15 downto 0); |
i_udp_dst_port : in std_logic_vector (15 downto 0); |
|
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----------------udp Data Path----------------------------- |
i_udp_start : in std_logic; |
o_udp_ready : out std_logic; |
i_udp_din : in std_logic_vector (7 downto 0); |
|
-----------------IP Data Path----------------------------- |
o_ip_start : out std_logic; |
i_ip_ready : in std_logic; |
o_ip_dout : out std_logic_vector (7 downto 0); |
|
----------------for IP header----------------------------- |
o_ip_src_ip : out std_logic_vector (31 downto 0); |
o_ip_dst_ip : out std_logic_vector (31 downto 0); |
o_ip_src_mac : out std_logic_vector (47 downto 0); |
o_ip_data_len : out std_logic_vector (15 downto 0); |
o_ip_protocol : out std_logic_vector (7 downto 0); |
----------------Error Status------------------------------- |
o_err_out : out std_logic_vector (3 downto 0) |
|
); |
end component; |
--========================================================================================= |
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begin |
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o_ip_rx_fragmantation <= s_ip_rx_fragmantation; |
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-- o_ip_rx_src_ip <= s_ip_rx_src_ip; |
o_ip_rx_dst_ip <= s_ip_rx_dst_ip; |
o_ip_rx_data_len <= s_ip_rx_data_len; |
o_ip_rx_protocol <= s_ip_rx_protocol; |
-- o_ip_rx_broadcast <= s_ip_rx_broadcast; |
o_ip_rx_err_out <= s_ip_rx_err_out_udp; |
o_ip_tx_err_out <= s_ip_tx_err_out_udp; |
o_arp_rx_err_out <= s_arp_rx_err_out_udp; |
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o_arp_addr_valid <= not s_arp_rx_err_out_udp(0); |
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--========================== IP ================================================ |
inst_IP_ARP_PING : IP_ARP_PING |
generic map( |
g_TIME_OUT_LOOKUP_TABLE_ARP => g_TIME_OUT_LOOKUP_TABLE_ARP, |
g_TIME_OUT_WAIT_FOR_ARP_REPLY => g_TIME_OUT_WAIT_FOR_ARP_REPLY, |
g_RE_SEND_ARP_REQUEST => g_RE_SEND_ARP_REQUEST, |
g_GENERATE_PING_MODULE => g_GENERATE_PING_MODULE, |
g_GENERATE_ARP_MODULE => g_GENERATE_ARP_MODULE, |
g_DEFAULT_DST_MAC_ADDR => g_DEFAULT_DST_MAC_ADDR |
) |
port map( |
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i_rx_clk => i_rx_clk, |
i_tx_clk => i_tx_clk, |
i_reset => i_reset_rx, |
|
--******************************* TX *************************************** |
-- Tx header construction |
i_ip_tx_src_ip => s_ip_tx_src_ip, |
i_ip_tx_dst_ip => s_ip_tx_dst_ip, |
i_ip_tx_data_len => s_ip_tx_data_len, |
i_ip_tx_protocol => s_ip_tx_protocol, |
i_ip_tx_src_mac => s_ip_tx_src_mac, |
o_ip_rx_fragmantation => s_ip_rx_fragmantation, |
|
-- TX Inputs |
i_ip_tx_start => s_ip_tx_start, |
o_ip_tx_rdy => s_ip_tx_rdy, |
i_ip_tx_din => s_ip_tx_din, |
|
-- TX Outputs |
i_mac_tx_tready => i_mac_tx_tready, |
o_mac_tx_tdata => o_mac_tx_tdata, |
o_mac_tx_tvalid => o_mac_tx_tvalid, |
o_mac_tx_tlast => o_mac_tx_tlast, |
|
o_lookup_mac_err => o_lookup_mac_err, |
|
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--********************** RX *************************************** |
--RX Inputs |
i_mac_rx_tdata => i_mac_rx_tdata, |
i_mac_rx_tvalid => i_mac_rx_tvalid, |
i_mac_rx_tlast => i_mac_rx_tlast, |
|
--RX Outputs |
o_ip_rx_dout => s_ip_rx_dout, |
o_ip_rx_dout_rdy => s_ip_rx_dout_rdy, |
o_ip_rx_dout_last => s_ip_rx_dout_last, |
|
--RX Status Outputs |
o_ip_rx_src_ip => s_ip_rx_src_ip, |
o_ip_rx_dst_ip => s_ip_rx_dst_ip, |
o_ip_rx_data_len => s_ip_rx_data_len, |
o_ip_rx_protocol => s_ip_rx_protocol, |
o_ip_rx_broadcast => s_ip_rx_broadcast, |
i_ip_tx_fragmantation => i_ip_tx_fragmantation, |
|
-- Error Status |
o_ip_rx_err_out => s_ip_rx_err_out_udp, |
o_ip_tx_err_out => s_ip_tx_err_out_udp, |
o_arp_rx_err_out => s_arp_rx_err_out_udp |
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); |
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--========================================================================================= |
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--============================ udp RX ==================================================== |
inst_udp_RX: udp_RX |
port map ( |
|
-- system signals |
i_rx_clk => i_rx_clk, |
i_reset => i_reset_rx, |
|
-- IP layer RX inputs |
i_ip_data_in => s_ip_rx_dout, |
i_ip_data_in_valid => s_ip_rx_dout_rdy, |
i_ip_data_in_last => s_ip_rx_dout_last, |
i_ip_protocol => s_ip_rx_protocol, |
i_ip_src_ip => s_ip_rx_src_ip, |
i_fragmantation => s_ip_rx_fragmantation, |
|
-- Outputs |
o_udp_dout => o_udp_rx_dout, |
o_udp_dout_rdy => o_udp_rx_dout_rdy, |
o_udp_dout_last => o_udp_rx_dout_last, |
|
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o_src_ip => o_udp_rx_src_ip, |
o_src_port => o_udp_rx_src_port, |
o_dst_port => o_udp_rx_dst_port, |
o_data_len => o_udp_rx_data_len, -- zero |
o_err_out => o_udp_rx_err_out |
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); |
--========================================================================================= |
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--================================ udp TX ================================================== |
inst_udp_TX: udp_TX |
port map( |
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i_tx_clk => i_tx_clk, |
i_reset => i_reset_tx, |
|
------------udp & IP Header-------------- |
i_udp_src_ip => i_udp_tx_src_ip, |
i_udp_dst_ip => i_udp_tx_dst_ip, |
i_udp_src_mac => i_udp_tx_src_mac, |
i_udp_data_len => i_udp_tx_data_len, |
i_udp_protocol => i_udp_tx_protocol, |
i_udp_checksum => i_udp_tx_checksum, |
i_udp_src_port => i_udp_tx_src_port, |
i_udp_dst_port => i_udp_tx_dst_port, |
i_fragmantation => i_ip_tx_fragmantation, |
i_fragment_len => i_fragment_len, |
-------------udp Data Path--------------- |
i_udp_start => i_udp_tx_start, |
o_udp_ready => o_udp_tx_ready, |
i_udp_din => i_udp_tx_din, |
|
-------------IP Data Path---------------- |
o_ip_start => s_ip_tx_start, |
i_ip_ready => s_ip_tx_rdy, |
o_ip_dout => s_ip_tx_din, |
|
-------------IP Header Path-------------- |
o_ip_src_ip => s_ip_tx_src_ip, |
o_ip_dst_ip => s_ip_tx_dst_ip, |
o_ip_src_mac => s_ip_tx_src_mac, |
o_ip_data_len => s_ip_tx_data_len, |
o_ip_protocol => s_ip_tx_protocol, |
----------------------------------------- |
o_err_out => o_udp_tx_err_out |
|
); |
--========================================================================================= |
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end structural; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/UDP_RX.vhd
0,0 → 1,884
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
|
library work; |
use work.signal_Package.all; |
|
|
entity UDP_RX is |
generic ( |
g_use_fragment : boolean:= false --true |
); |
port ( |
-- system signals |
i_rx_clk : in std_logic; |
i_reset : in std_logic; |
|
-- IP layer RX inputs |
i_ip_data_in : in std_logic_vector (7 downto 0); |
i_ip_data_in_valid : in std_logic; |
i_ip_data_in_last : in std_logic; |
i_ip_protocol : in std_logic_vector (7 downto 0); |
i_ip_src_ip : in std_logic_vector (31 downto 0); |
i_fragmantation : in std_logic_vector (15 downto 0); |
-- Outputs for application |
o_udp_dout : buffer std_logic_vector(7 downto 0); |
o_udp_dout_rdy : buffer std_logic; |
o_udp_dout_last : buffer std_logic; |
|
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o_src_ip : out std_logic_vector(31 downto 0); |
o_src_port : out std_logic_vector(15 downto 0); |
o_dst_port : out std_logic_vector(15 downto 0); |
o_data_len : out std_logic_vector(15 downto 0); --application data length (udp data length-8) |
o_err_out : out std_logic_vector(3 downto 0) |
); |
end UDP_RX; |
|
architecture Behavioral of UDP_RX is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
|
|
--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --udp Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --udp Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --udp Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --udp Dst Port(Value For This Constant is not Importanat) |
|
|
--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
|
--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
|
--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
|
--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
|
|
--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
|
signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
|
|
|
--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
|
signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
|
|
--================================ udp Signals ========================================================= |
-------- for transfer Rx data from IP to udp layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
|
-------- for transfer Rx status data from IP to udp layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
|
-------- for transfer Tx data from udp to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
|
-------- for transfer Tx header data from udp to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
|
|
|
--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
|
signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
|
signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ udp RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, udp_HDR, USER_DATA, WAIT_END); |
signal st_RX_udp_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
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signal s_udp_Seq_Num : std_logic_vector(31 downto 0); |
signal s_udp_Ack_Num : std_logic_vector(31 downto 0); |
signal s_udp_offset : std_logic_vector(7 downto 0) ; |
signal s_udp_udp_Flag : std_logic_vector(7 downto 0) ; |
signal s_udp_Window : std_logic_vector(15 downto 0) ; |
signal s_udp_checksum : std_logic_vector(15 downto 0) ; |
signal s_udp_Urg_point : std_logic_vector(15 downto 0) ; |
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--======================================================================================================================= |
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--============================ udp TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
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signal udp_header_len : integer:=8; |
constant udp_type_protocol : std_logic_vector(7 downto 0):=x"11"; |
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signal EnableTlast : std_logic:='1'; |
signal s_udp_dout_last : std_logic:='0'; |
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signal first_FG_flag, other_FG_flag, last_FG_flag : std_logic:='0'; |
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signal dntFragSet : std_logic:='0'; |
signal MoreFrag: std_logic:='0'; |
signal offset_fragment : std_logic_vector(12 downto 0):=(others=>'0'); |
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signal s_ip_data_len_pack : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal rst_cntr_FG : std_logic:='0'; |
signal s_cntr_FG_timout : std_logic_vector(23 downto 0):=(others=>'0'); |
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type paket_type_t is (Normal, first_FG, other_FG, last_FG); |
signal paket_type:paket_type_t; |
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signal CheckSum_calc_en : std_logic:= '0' ; |
signal rst_chk_sum : std_logic:= '0' ; |
signal sec_cal_sum : std_logic:= '0' ; |
signal Data_sum : std_logic_vector(15 downto 0) ; |
signal CheckSum_data : std_logic_vector(31 downto 0) ; |
signal CheckSum_data_r : std_logic_vector(31 downto 0) ; |
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signal s_chksum_udp_rx : std_logic_vector(31 downto 0) ; |
--========================================================================================================================= |
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--------------------------------------------------------------------- |
begin |
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dntFragSet <= i_fragmantation(14) When g_use_fragment else '1'; |
MoreFrag <= i_fragmantation(13); |
offset_fragment <= i_fragmantation(12 downto 0); |
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paket_type <= Normal When (dntFragSet = '1' OR (dntFragSet = '0' AND MoreFrag = '0' AND offset_fragment = 0)) else |
first_FG When (dntFragSet = '0' AND MoreFrag = '1' AND offset_fragment = 0) else |
other_FG When (dntFragSet = '0' AND MoreFrag = '1' AND offset_fragment /= 0) else |
last_FG When (dntFragSet = '0' AND MoreFrag = '0' AND offset_fragment /= 0) ; |
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--udp_header_len <= 8 When (paket_type = Normal) else |
-- 8 When (paket_type = first_FG) else |
-- 0; |
udp_header_len <= 8; |
--========================================================================================================================= |
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--================ Status Outputs =============================================================================== |
o_src_ip <= s_src_ip_udp_rx ; |
o_src_port <= s_src_port ; |
o_dst_port <= s_dst_port ; |
o_data_len <= s_data_len_udp_rx ; |
o_err_out <= s_err_out ; |
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o_udp_dout_last <= s_udp_dout_last AND EnableTlast; |
--=============================================================================================================== |
-- |
--Data_sum(7 downto 0) <= i_ip_data_in When sec_cal_sum= '1' else (others => '0') When rst_chk_sum ='1'; |
--Data_sum(15 downto 8) <= i_ip_data_in When sec_cal_sum= '0' else (others => '0') When rst_chk_sum ='1'; |
--CheckSum_data <= CheckSum_data_r + Data_sum; |
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--================ Process for Recieve udp Data from IP Layer ===================================================== |
p_recieve_udp_data:process(i_rx_clk) |
begin |
if(rising_edge(i_rx_clk)) then |
if (i_reset='1') then |
st_RX_udp_STATE <= IDLE; |
s_cnt_udp_rx <= x"0001"; |
--status |
s_src_ip_udp_rx <= (others => '0'); |
s_src_port <= (others => '0'); |
s_dst_port <= (others => '0'); |
s_data_len_udp_rx <= (others => '0'); |
s_err_out <= (others => '0'); |
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--output data for application |
o_udp_dout <= (others => '0'); |
o_udp_dout_rdy <= '0' ; |
s_udp_dout_last <= '0' ; |
else |
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o_udp_dout <= (others => '0'); |
o_udp_dout_rdy <= '0' ; |
s_udp_dout_last <= '0' ; |
-- if (sec_cal_sum = '1') then |
-- CheckSum_data_r <= CheckSum_data; |
-- end if; |
----------------------------------------------- |
if (CheckSum_calc_en = '1') then |
sec_cal_sum <= not sec_cal_sum; |
if (sec_cal_sum= '1') then |
Data_sum(7 downto 0) <= i_ip_data_in; |
else |
CheckSum_data <= CheckSum_data + Data_sum; |
Data_sum(15 downto 8) <= i_ip_data_in ; |
end if; |
end if; |
-------------------- |
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CASE st_RX_udp_STATE IS |
--************************************************************************************************************************************ |
WHEN IDLE => |
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-- s_cnt_udp_rx <= x"0001"; |
sec_cal_sum <= '0'; |
-- s_src_ip_udp_rx <= (others => '0'); |
-- s_src_port <= (others => '0'); |
-- s_dst_port <= (others => '0'); |
-- s_data_len_udp_rx <= (others => '0'); |
s_err_out <= (others => '0'); |
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if (rst_cntr_FG = '1') then |
s_cntr_FG_timout <= (others => '0'); |
else |
s_cntr_FG_timout <= s_cntr_FG_timout + 1; |
end if; |
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rst_cntr_FG <= '0'; |
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if (s_cntr_FG_timout = 125e5) then |
rst_cntr_FG <= '1'; |
first_FG_flag <= '0'; |
other_FG_flag <= '0'; |
last_FG_flag <= '0'; |
s_err_out <= x"6"; |
end if; |
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------------- Checking Type & Loading Source IP ------------------------------------------ |
case paket_type is |
When Normal => |
EnableTlast <= '1'; |
if (i_ip_data_in_valid = '1') then |
st_RX_udp_STATE <= WAIT_END; |
s_err_out <= x"1"; |
if(i_ip_protocol=udp_type_protocol) then |
--status |
s_src_ip_udp_rx <= i_ip_src_ip; |
s_src_port(15 downto 8) <= i_ip_data_in; |
------- |
-- s_cnt_udp_rx <= s_cnt_udp_rx+1; |
s_cnt_udp_rx <= x"0002"; |
s_err_out <= x"0"; |
first_FG_flag <= '0'; |
other_FG_flag <= '0'; |
last_FG_flag <= '0'; |
-- CheckSum_data_r <= (others => '0'); |
-- rst_chk_sum <= '1'; |
st_RX_udp_STATE <= udp_HDR; |
end if; |
end if; |
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When first_FG => |
EnableTlast <= '0'; |
if (i_ip_data_in_valid = '1') then |
st_RX_udp_STATE <= WAIT_END; |
s_err_out <= x"1"; |
if(i_ip_protocol=udp_type_protocol) then |
--status |
s_src_ip_udp_rx <= i_ip_src_ip; |
s_src_port(15 downto 8) <= i_ip_data_in; |
------- |
-- s_cnt_udp_rx <= s_cnt_udp_rx+1; |
s_cnt_udp_rx <= x"0002"; |
s_err_out <= x"0"; |
first_FG_flag <= '1'; |
other_FG_flag <= '0'; |
last_FG_flag <= '0'; |
rst_cntr_FG <= '1'; |
-- CheckSum_data_r <= (others => '0'); |
-- rst_chk_sum <= '1'; |
st_RX_udp_STATE <= udp_HDR; |
end if; |
end if; |
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When other_FG => |
EnableTlast <= '0'; |
if (i_ip_data_in_valid = '1') then |
st_RX_udp_STATE <= WAIT_END; |
s_err_out <= x"1"; |
if(i_ip_protocol=udp_type_protocol and (first_FG_flag = '1' or other_FG_flag='1')) then |
--status |
o_udp_dout <= i_ip_data_in; |
o_udp_dout_rdy <= i_ip_data_in_valid; |
s_udp_dout_last <= i_ip_data_in_last; |
s_cnt_udp_rx <= s_cnt_udp_rx+1; |
s_err_out <= x"0"; |
first_FG_flag <= '0'; |
other_FG_flag <= '1'; |
last_FG_flag <= '0'; |
rst_cntr_FG <= '1'; |
st_RX_udp_STATE <= USER_DATA; |
end if; |
end if; |
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When last_FG => |
EnableTlast <= '1'; |
if (i_ip_data_in_valid = '1') then |
st_RX_udp_STATE <= WAIT_END; |
s_err_out <= x"1"; |
if(i_ip_protocol=udp_type_protocol and other_FG_flag = '1') then |
--status |
o_udp_dout <= i_ip_data_in; |
o_udp_dout_rdy <= i_ip_data_in_valid; |
s_udp_dout_last <= i_ip_data_in_last; |
s_cnt_udp_rx <= s_cnt_udp_rx+1; |
s_err_out <= x"0"; |
first_FG_flag <= '0'; |
other_FG_flag <= '0'; |
last_FG_flag <= '1'; |
rst_cntr_FG <= '1'; |
st_RX_udp_STATE <= USER_DATA; |
end if; |
end if; |
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end case; |
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--************************************************************************************************************************************ |
WHEN udp_HDR => |
-- rst_chk_sum <= '0'; |
if (i_ip_data_in_valid = '1') then |
s_cnt_udp_rx <= s_cnt_udp_rx+1; |
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if(s_cnt_udp_rx= 2) then |
s_src_port(7 downto 0) <= i_ip_data_in; |
end if; |
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if(s_cnt_udp_rx= 3) then |
s_dst_port(15 downto 8) <= i_ip_data_in; |
end if; |
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if(s_cnt_udp_rx= 4) then |
s_dst_port(7 downto 0) <= i_ip_data_in; |
end if; |
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-- if (s_cnt_udp_rx = x"0005") then s_udp_Seq_Num(31 downto 24) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0006") then s_udp_Seq_Num(23 downto 16) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0007") then s_udp_Seq_Num(15 downto 8) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0008") then s_udp_Seq_Num(7 downto 0) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0009") then s_udp_Ack_Num(31 downto 24) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"000A") then s_udp_Ack_Num(23 downto 16) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"000B") then s_udp_Ack_Num(15 downto 8) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"000C") then s_udp_Ack_Num(7 downto 0) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"000D") then s_udp_offset (7 downto 0) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"000E") then s_udp_udp_Flag (7 downto 0) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"000F") then s_udp_Window(15 downto 8) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0010") then s_udp_Window(7 downto 0) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0011") then s_udp_checksum(15 downto 8) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0012") then s_udp_checksum(7 downto 0) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0013") then s_udp_Urg_point(15 downto 8) <= i_ip_data_in; end if; |
-- if (s_cnt_udp_rx = x"0014") then s_udp_Urg_point(7 downto 0) <= i_ip_data_in; end if; |
-- |
-- if (s_cnt_udp_rx = x"0014") then |
-- st_RX_udp_STATE <= USER_DATA; |
-- end if; |
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if(s_cnt_udp_rx= 5) then |
s_data_len_udp_rx(15 downto 8) <= i_ip_data_in; |
s_data_len_udp_rx(7 downto 0) <= (others=>'0'); |
end if; |
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if(s_cnt_udp_rx= 6) then |
s_data_len_udp_rx <= ((s_data_len_udp_rx(15 downto 8) & i_ip_data_in) - udp_header_len); |
if ((s_data_len_udp_rx(15 downto 8) & i_ip_data_in) < udp_header_len) then |
s_err_out <= x"3"; |
st_RX_udp_STATE <= WAIT_END; |
end if; |
end if; |
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if(s_cnt_udp_rx= 7) then |
s_chksum_udp_rx(15 downto 8) <= i_ip_data_in; |
s_chksum_udp_rx(7 downto 0) <= (others=>'0'); |
end if; |
if(s_cnt_udp_rx= 8) then |
s_chksum_udp_rx(7 downto 0) <= i_ip_data_in; |
end if; |
|
---------- Cheking Type ------------------------------ |
if(s_cnt_udp_rx= 8) then |
st_RX_udp_STATE <= USER_DATA; |
CheckSum_calc_en <= '1'; |
rst_chk_sum <= '0'; |
if (s_data_len_udp_rx=x"0000") then |
st_RX_udp_STATE <= WAIT_END; |
end if; |
end if; |
------------------------------------------------------ |
if ( i_ip_data_in_last = '1') then |
s_cnt_udp_rx <= x"0001"; |
--status |
-- s_src_ip_udp_rx <= (others => '0'); |
-- s_src_port <= (others => '0'); |
-- s_dst_port <= (others => '0'); |
-- s_data_len_udp_rx <= (others => '0'); |
s_err_out <= x"2"; |
st_RX_udp_STATE <= IDLE; |
end if; |
------------------------------------------------------ |
end if; |
|
--************************************************************************************************************************************ |
WHEN USER_DATA => |
o_udp_dout <= i_ip_data_in; |
o_udp_dout_rdy <= i_ip_data_in_valid; |
s_udp_dout_last <= i_ip_data_in_last; |
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if (i_ip_data_in_valid = '1') then |
----------------------------------------------- |
s_cnt_udp_rx <= s_cnt_udp_rx+1; |
-- if (s_cnt_udp_rx = (s_data_len_udp_rx+8)) then |
-- s_udp_dout_last <= '1'; |
-- st_RX_udp_STATE <= WAIT_END; |
-- end if; |
--------------------------- |
if (i_ip_data_in_last = '1') then |
-- s_cnt_udp_rx <= x"0001"; |
st_RX_udp_STATE <= IDLE; |
CheckSum_calc_en <= '0'; |
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if (s_cnt_udp_rx /= (s_data_len_udp_rx+udp_header_len) and EnableTlast='1') then |
s_err_out <= x"5"; |
end if; |
|
--status |
-- s_src_ip_udp_rx <= (others => '0'); |
-- s_src_port <= (others => '0'); |
-- s_dst_port <= (others => '0'); |
-- s_data_len_udp_rx <= (others => '0'); |
--error status |
-- if (s_cnt_udp_rx < (s_data_len_udp_rx+8)) then |
-- s_err_out <= x"2"; |
-- end if; |
end if; |
------------------------------------------------ |
end if; |
|
--******************************************************************************************************************************************* |
WHEN WAIT_END => |
if ( i_ip_data_in_valid = '1') then |
if (i_ip_data_in_last = '1') then |
-- s_cnt_udp_rx <= x"0001"; |
st_RX_udp_STATE <= IDLE; |
--status |
-- s_src_ip_udp_rx <= (others => '0'); |
-- s_src_port <= (others => '0'); |
-- s_dst_port <= (others => '0'); |
-- s_data_len_udp_rx <= (others => '0'); |
--error status |
s_err_out <= x"0"; |
end if; |
end if; |
|
END CASE; |
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end if; |
end if; |
end process p_recieve_udp_data; |
--=============================================================================================================== |
-- my_ila_Phy : entity work.ila_0 |
-- PORT MAP ( |
-- clk => i_rx_clk, |
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-- probe0(31 downto 0) => (others => '0'), |
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-- probe0(39 downto 32) => i_ip_protocol, |
-- probe0(40) => i_ip_data_in_last , |
-- probe0(41) => i_ip_data_in_valid , |
-- probe0(49 downto 42) => i_ip_data_in, |
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-- probe0(57 downto 50) => o_udp_dout, |
-- probe0(58) => o_udp_dout_rdy, |
-- probe0(59) => o_udp_dout_last, |
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-- probe0(255 downto 60) => (others => '0') |
-- ); |
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end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/UDP_TX.vhd
0,0 → 1,664
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
|
library work; |
use work.signal_Package.all; |
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entity UDP_TX is |
port ( |
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i_tx_clk : in std_logic; |
i_reset : in std_logic; |
|
----------------for IP header----------------------------- |
i_udp_src_ip : in std_logic_vector (31 downto 0); |
i_udp_dst_ip : in std_logic_vector (31 downto 0); |
i_udp_src_mac : in std_logic_vector (47 downto 0); |
i_udp_data_len : in std_logic_vector (15 downto 0); --application data length |
i_udp_protocol : in std_logic_vector (7 downto 0); --udp protocol, is x"11" |
----------------for udp header----------------------------- |
i_udp_checksum : in std_logic_vector (15 downto 0); -- is x"00" |
i_udp_src_port : in std_logic_vector (15 downto 0); |
i_udp_dst_port : in std_logic_vector (15 downto 0); |
i_fragmantation : in std_logic_vector(15 downto 0):=x"4000"; |
i_fragment_len : in std_logic_vector(16 - 1 downto 0):=x"4000"; |
----------------udp Data Path----------------------------- |
i_udp_start : in std_logic; |
o_udp_ready : out std_logic; |
i_udp_din : in std_logic_vector (7 downto 0); |
|
-----------------IP Data Path----------------------------- |
o_ip_start : out std_logic; |
i_ip_ready : in std_logic; |
o_ip_dout : out std_logic_vector (7 downto 0); |
|
----------------for IP header----------------------------- |
o_ip_src_ip : out std_logic_vector (31 downto 0); |
o_ip_dst_ip : out std_logic_vector (31 downto 0); |
o_ip_src_mac : out std_logic_vector (47 downto 0); |
o_ip_data_len : out std_logic_vector (15 downto 0); |
o_ip_protocol : out std_logic_vector (7 downto 0); |
----------------Error Status------------------------------- |
o_err_out : out std_logic_vector (3 downto 0) |
|
); |
end UDP_TX; |
|
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architecture Behavioral of UDP_TX is |
|
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
|
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --udp Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --udp Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --udp Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --udp Dst Port(Value For This Constant is not Importanat) |
|
|
--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
|
--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
|
--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
|
--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
|
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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|
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
|
|
--================================ udp Signals ========================================================= |
-------- for transfer Rx data from IP to udp layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to udp layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from udp to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from udp to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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|
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ udp RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, udp_HDR, USER_DATA, WAIT_END); |
signal st_RX_udp_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ udp TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
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signal udp_header_len : integer:=8; |
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signal dntFragSet : std_logic:='0'; |
signal MoreFrag: std_logic:='0'; |
signal offset_fragment : std_logic_vector(12 downto 0):=(others=>'0'); |
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signal s_ip_data_len_pack : std_logic_vector(15 downto 0):=(others=>'0'); |
--========================================================================================================================= |
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--------------------------------------------------------------------- |
begin |
dntFragSet <= i_fragmantation(14); |
MoreFrag <= i_fragmantation(13); |
offset_fragment <= i_fragmantation(12 downto 0); |
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udp_header_len <= 8 When (dntFragSet = '1') else |
8 When (offset_fragment = 0) else |
0; |
--=================== Status Outputs ============================================================================ |
o_ip_protocol <= i_udp_protocol; |
s_ip_data_len <= std_logic_vector(unsigned(i_udp_data_len) + udp_header_len); --s_ip_data_len is application data length + udp header |
o_ip_data_len <= s_ip_data_len; |
o_ip_src_ip <= i_udp_src_ip; |
o_ip_dst_ip <= i_udp_dst_ip; |
o_ip_src_mac <= i_udp_src_mac; |
--=============================================================================================================== |
s_ip_data_len_pack <= s_ip_data_len When (dntFragSet = '1') else |
i_fragment_len + udp_header_len; |
--==================================== Immediate Transfering Data to IP & Application Layers ==================== |
o_ip_dout <= s_udp_header when (s_cnt_udp_tx <= udp_header_len) else i_udp_din when (s_cnt_udp_tx > udp_header_len and s_cnt_udp_tx <=(udp_header_len+i_udp_data_len)) else (others=>'0'); |
o_udp_ready <= i_ip_ready when (s_cnt_udp_tx >=udp_header_len and s_cnt_udp_tx <(udp_header_len+i_udp_data_len)) else '0'; |
--=============================================================================================================== |
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--=================================== Process for Transmit udp Data to IP Layer ================================ |
p_transmit_udp_data:process(i_tx_clk) |
begin |
if(rising_edge(i_tx_clk)) then |
if (i_reset='1') then |
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st_tx_udp_state <=IDLE; |
s_cnt_udp_tx <=(others=>'0'); |
s_udp_header <=(others=>'0'); |
o_ip_start <= '0'; --start pulse for ip_tx block |
------------------------------------------------------------------- |
o_err_out <=(others=>'0'); |
else |
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case st_tx_udp_state is |
when IDLE => |
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s_cnt_udp_tx <=(others=>'0'); |
s_udp_header <=(others=>'0'); |
o_ip_start <= '0'; |
o_err_out <=(others=>'0'); |
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if i_udp_start = '1' then |
st_tx_udp_state <= SEND_DATA; |
o_ip_start <= '1'; |
if (unsigned(i_udp_data_len) > 1472) then |
o_ip_start <= '0'; |
o_err_out <="0001"; |
st_tx_udp_state <= IDLE; |
end if; |
end if; |
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when SEND_DATA => |
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o_ip_start <= '0'; |
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if (i_ip_ready='1') then --i_ip_ready determined that ip_tx block is ready for receive data |
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s_cnt_udp_tx <= s_cnt_udp_tx+1; |
--*************************************************************** |
case s_cnt_udp_tx is |
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when x"0000" => s_udp_header <= i_udp_src_port(15 downto 8); |
when x"0001" => s_udp_header <= i_udp_src_port(7 downto 0); |
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when x"0002" => s_udp_header <= i_udp_dst_port(15 downto 8); |
when x"0003" => s_udp_header <= i_udp_dst_port(7 downto 0); |
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when x"0004" => s_udp_header <= s_ip_data_len_pack(15 downto 8); |
when x"0005" => s_udp_header <= s_ip_data_len_pack(7 downto 0); |
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when x"0006" => s_udp_header <= i_udp_checksum(15 downto 8); |
when x"0007" => s_udp_header <= i_udp_checksum(7 downto 0); |
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when others => --null |
end case; |
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end if; |
--*************************************************************** |
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if(s_cnt_udp_tx = i_udp_data_len+udp_header_len) then |
o_ip_start <= '0'; |
s_udp_header <= (others=>'0'); |
s_cnt_udp_tx <= (others=>'0'); |
st_tx_udp_state <= IDLE; |
end if; |
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end case; |
end if; |
end if; |
end process p_transmit_udp_data; |
--======================================================================================================================================= |
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end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/ping_cheksum_calc.vhd
0,0 → 1,569
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
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library work; |
use work.signal_Package.all; |
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library unisim; |
use unisim.vcomponents.all; |
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entity ping_cheksum_calc is |
port |
( |
i_clk : in std_logic; |
i_reset : in std_logic; |
i_din : in std_logic_vector(7 downto 0); |
i_din_rdy : in std_logic; |
i_start_calc : in std_logic; |
i_stop_calc : in std_logic; |
o_checksum_valid : out std_logic; |
o_checksum : out std_logic_vector(15 downto 0) |
); |
end ping_cheksum_calc; |
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architecture Behavioral of ping_cheksum_calc is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
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--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
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signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
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signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
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signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
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begin |
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--==================== Ping Checksum Calculator ========================================================== |
p_checksum_calculator:process(i_clk) |
begin |
if rising_edge(i_clk) then |
if (i_reset='1') then |
st_checksum_state <= IDLE; |
s_flag <= '0'; |
s_sum <= (others=>'0'); |
o_checksum_valid <= '0'; |
o_checksum <= (others=>'0'); |
else |
case st_checksum_state is |
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WHEN IDLE => |
s_flag <= '0'; |
if (i_start_calc='1') then |
s_sum <= (others=>'0'); |
o_checksum_valid <= '0'; |
o_checksum <= (others=>'0'); |
st_checksum_state <= CALC; |
end if; |
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WHEN CALC => |
if (i_din_rdy='1') then |
s_din_r <= i_din; |
s_flag <= not s_flag; |
if (s_flag='1') then |
s_sum <= s_sum+(x"0000" & s_din_r & i_din); |
end if; |
end if; |
if (i_stop_calc='1') then |
o_checksum <= not(s_sum(31 downto 16) + s_sum(15 downto 0)); |
o_checksum_valid <= '1'; |
st_checksum_state <= IDLE; |
end if; |
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END CASE; |
end if; |
end if; |
end process p_checksum_calculator; |
--======================================================================================================== |
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end Behavioral; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/signal_package.vhd
0,0 → 1,19
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
--use IEEE.STD_LOGIC_ARITH.ALL; |
--use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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package signal_Package is |
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type array_8Xi_KED is array (0 to 50) of std_logic_vector (7 downto 0); |
type Arr_128X8_KED is array (0 to 7) of std_logic_vector(127 downto 0); |
type RandomArr_type is array (0 to 255) of std_logic_vector(127 downto 0); |
type TagArr_type is array (0 to 1023) of std_logic_vector(1 downto 0); |
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end signal_Package; |
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package body signal_Package is |
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end signal_Package; |
/gigabit_udp_mac/trunk/LAN/UDP_KED/tx_arbitrator.vhd
0,0 → 1,590
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
library work; |
use work.signal_Package.all; |
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entity tx_arbitrator is |
port ( |
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i_tx_clk : in std_logic; |
i_reset : in std_logic; |
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-- IP Inputs Path |
i_req_1 : in std_logic; |
o_grant_1 : out std_logic; |
i_data_1 : in std_logic_vector(7 downto 0); |
i_valid_1 : in std_logic; |
i_last_1 : in std_logic; |
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-- ARP Inpus Path |
i_req_2 : in std_logic; |
o_grant_2 : out std_logic; |
i_data_2 : in std_logic_vector(7 downto 0); |
i_valid_2 : in std_logic; |
i_last_2 : in std_logic; |
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-- PING Inpus Path |
i_req_3 : in std_logic; |
o_grant_3 : out std_logic; |
i_data_3 : in std_logic_vector(7 downto 0); |
i_valid_3 : in std_logic; |
i_last_3 : in std_logic; |
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-- Outputs Path |
o_data : out std_logic_vector(7 downto 0); |
o_valid : out std_logic; |
o_last : out std_logic |
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); |
end tx_arbitrator; |
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architecture Behavioral of tx_arbitrator is |
--================================= Constant =========================================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
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--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"C0A86403"; --192.168.100.3(FPGA IP Adress) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"C0A86402"; --192.168.100.2(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
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--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
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--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast MAC Address |
--====================================================================================================== |
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--===================== Reset_gen Signals ============================================================== |
signal s_cnt_rst : std_logic_vector(15 downto 0):=(others=>'0'); |
--====================================================================================================== |
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--================================ Ethernet 1g Signals ================================================= |
signal s_gtx_clk : std_logic; |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_rx_reset : std_logic; |
signal s_tx_reset : std_logic; |
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--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
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signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
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--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
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signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
--====================================================================================================== |
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--================================ UDP Signals ========================================================= |
-------- for transfer Rx data from IP to UDP layer---------------- |
signal s_ip_rx_dout : std_logic_vector(7 downto 0); |
signal s_ip_rx_dout_rdy : std_logic; |
signal s_ip_rx_dout_last : std_logic; |
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-------- for transfer Rx status data from IP to UDP layer--------- |
signal s_ip_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_rx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_rx_protocol : std_logic_vector(7 downto 0); |
signal s_ip_rx_broadcast : std_logic; |
signal s_ip_rx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_udp : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out_udp : std_logic_vector (3 downto 0); |
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-------- for transfer Tx data from UDP to IP layer--------------- |
signal s_ip_tx_start : std_logic; |
signal s_ip_tx_rdy : std_logic; |
signal s_ip_tx_din : std_logic_vector(7 downto 0); |
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-------- for transfer Tx header data from UDP to IP layer-------- |
signal s_ip_tx_src_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_dst_ip : std_logic_vector(31 downto 0); |
signal s_ip_tx_src_mac : std_logic_vector(47 downto 0); |
signal s_ip_tx_data_len : std_logic_vector(15 downto 0); |
signal s_ip_tx_protocol : std_logic_vector(7 downto 0); |
----------------------------------------------------------------- |
--====================================================================================================== |
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--============================= IP Signals ============================================================= |
signal s_ip_mac_tx_tvalid : std_logic; |
signal s_ip_mac_tx_tlast : std_logic; |
signal s_ip_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ip_mac_tx_req : std_logic; |
signal s_ip_mac_tx_granted : std_logic; |
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signal s_arp_mac_tx_tvalid : std_logic; |
signal s_arp_mac_tx_tlast : std_logic; |
signal s_arp_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_arp_mac_tx_req : std_logic; |
signal s_arp_mac_tx_granted : std_logic; |
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signal s_ping_mac_tx_tvalid : std_logic; |
signal s_ping_mac_tx_tlast : std_logic; |
signal s_ping_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_ping_mac_tx_req : std_logic; |
signal s_ping_mac_tx_granted : std_logic; |
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signal s_lookup_req : std_logic; |
signal s_lookup_ip : std_logic_vector(31 downto 0); |
signal s_lookup_mac_addr : std_logic_vector(47 downto 0); |
signal s_lookup_mac_got : std_logic; |
signal s_lookup_mac_err : std_logic; |
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signal s_no_ping_packet : std_logic; |
signal s_ip_rx_err_out : std_logic_vector(3 downto 0); |
--====================================================================================================== |
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--============================= IP4_TX Signals ========================================================== |
type t_tx_ip_state_type is (IDLE,WAIT_MAC_ADDR,WAIT_CHN,SEND_DATA); |
type t_crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END); |
signal st_crc_state : t_crc_state_type:=IDLE; |
signal s_tx_hdr_cks : std_logic_vector (23 downto 0):=(others=>'0'); |
signal s_cal_cheksum : std_logic:='0'; |
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signal st_tx_ip_state : t_tx_ip_state_type:=IDLE; |
signal s_cnt_ip_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_mac_addr : std_logic_vector (47 downto 0); -- arp block updats this signal |
signal s_total_length : std_logic_vector (15 downto 0); -- s_total_length is i_data_length+20(ip header) |
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signal s_ip_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--======================================================================================================== |
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--============================ IP4_RX Signals============================================================ |
type t_rx_ip_state_type is (IDLE,ETH_H,IP_H,USER_DATA,WAIT_END); |
signal st_RX_IP_STATE : t_rx_ip_state_type:=IDLE; |
signal s_cnt_ip_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_ip_ip_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_data_len_ip_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_protocol_ip_rx : std_logic_vector (7 downto 0) :=(others=>'0'); |
signal s_broadcast_ip_rx : std_logic; |
--======================================================================================================== |
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--==================================== ARP Signals ========================================================== |
type t_arp_state_type is (IDLE,LOOK_UP,WAIT_PC_REPLY); |
signal st_ARP_STATE : t_arp_state_type:=IDLE; |
signal s_timeout_wait_reply_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_error_cnt : std_logic_vector(3 downto 0):=(others=>'0'); |
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--ARP_TX Signals |
signal s_dst_ip_addr_pc : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr_pc : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_ip_addr_lookup : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_fpga_req_tx : std_logic:='0'; |
signal s_pc_req_tx : std_logic:='0'; |
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--ARP_RX Signals |
signal s_ip_addr0 : std_logic_vector(31 downto 0); |
signal s_mac_addr0 : std_logic_vector(47 downto 0); |
signal s_addr_valid0 : std_logic; |
signal s_pc_reply_rx : std_logic; |
signal s_pc_req_rx : std_logic; |
--=========================================================================================================== |
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--=============================== ARP RX Signals ============================================================ |
type t_rx_arp_state_type is (IDLE,ETH_H,ARP_DATA,WAIT_END); |
signal st_RX_ARP_STATE : t_rx_arp_state_type:=IDLE; |
signal s_cnt_arp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_dst_ip : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_operation : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_addr_valid : std_logic:='0'; |
signal s_pc_req : std_logic:='0'; |
signal s_pc_reply : std_logic:='0'; |
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signal s_src_mac_arp_rx : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_src_ip_arp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_addr_valid_pulse : std_logic:='0'; |
signal s_pc_req_pulse : std_logic:='0'; |
signal s_pc_reply_pulse : std_logic:='0'; |
signal s_trans_data_pulse : std_logic:='0'; |
--=========================================================================================================== |
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--=================================== ARP LOOKUP_TABLE Signals ============================================== |
signal s_timeout_lookup_table_cnt : std_logic_vector(31 downto 0):=(others=>'0'); |
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signal s_din : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_wr_en : std_logic; |
signal s_dout : std_logic_vector(82 downto 0):=(others=>'0'); |
signal s_valid : std_logic; |
signal s_empty : std_logic; |
signal s_notempty : std_logic; |
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signal s_mac_addr_out : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_ip_addr_out : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_addr_valid_out : std_logic:='0'; |
signal s_request_out : std_logic:='0'; |
signal s_reply_out : std_logic:='0'; |
--============================================================================================================ |
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--============================ ARP TX Signals ================================================================ |
type t_arp_tx_state_type is (IDLE,WAIT_CHN,SEND_DATA); |
signal st_tx_arp_state : t_arp_tx_state_type:=IDLE; |
signal s_cnt_arp_tx : std_logic_vector (7 downto 0):=(others=>'0'); |
signal s_arp_type : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_ip_addr : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_dst_mac_addr1 : std_logic_vector (47 downto 0):=(others=>'0'); |
signal s_dst_mac_addr2 : std_logic_vector (47 downto 0):=(others=>'0'); |
--============================================================================================================ |
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--============================== PING Signals ================================================================= |
--for Delayed Inputs |
signal s_mac_data_in_r : std_logic_vector (7 downto 0); |
signal s_mac_data_in_valid_r : std_logic; |
signal s_mac_data_in_last_r : std_logic; |
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--Sync_fifo_ping Signals |
signal s_ip_rx_in : std_logic_vector(14 downto 0); |
signal s_ip_rx_out : std_logic_vector(14 downto 0):=(others=>'0'); |
signal s_mac_data_in : std_logic_vector(7 downto 0); |
signal s_mac_data_in_valid : std_logic; |
signal s_mac_data_in_last : std_logic; |
signal s_mac_data_in_last_d : std_logic; |
signal s_ip_rx_err_in : std_logic_vector(3 downto 0); |
signal s_no_ping_data : std_logic; |
signal s_empty_sync_fifo : std_logic:='0'; |
signal s_not_empty_sync_fifo: std_logic; |
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--Data_fifo_ping Signals |
signal s_rst_fifo_ping : std_logic:='1'; |
signal s_wr_en_fifo_ping : std_logic:='0'; |
signal s_din_fifo_ping : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_fifo_ping : std_logic; |
signal s_dout_fifo_ping : std_logic_vector(7 downto 0); |
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--Checksum Signals |
signal s_checksum_data_out : std_logic_vector(15 downto 0); |
signal s_checksum_data_in : std_logic_vector(7 downto 0); |
signal s_checksum_start_calc : std_logic:='0'; |
signal s_checksum_stop_calc : std_logic:='0'; |
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--st_PING_STATE Machine Process Signals |
type t_ping_state is (IDLE,ACQUIRE_DATA,WAIT_END,WAIT_CHN,SEND_DATA); |
signal st_PING_STATE : t_ping_state:=IDLE; |
signal s_wr_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_cnt : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_start_send : std_logic; |
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signal s_src_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_dst_mac_ping : std_logic_vector(47 downto 0):=(others=>'0'); |
signal s_src_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_dst_ip_ping : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--================================= Ping Checksum Calc Signals ==================================================== |
type t_checksum_state is (IDLE,CALC); |
signal st_checksum_state : t_checksum_state:=IDLE; |
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signal s_flag : std_logic:='0'; |
signal s_din_r : std_logic_vector(7 downto 0); |
signal s_sum : std_logic_vector(31 downto 0):=(others=>'0'); |
--================================================================================================================= |
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--============================ TX_Arbitior Signals ===================================================================== |
type t_state_type is (IDLE,DATA_REQ,ARP_REQ,PING_REQ); |
signal st_STATE : t_state_type:=IDLE; |
--====================================================================================================================== |
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--============================ UDP RX Signals =========================================================================== |
type t_rx_udp_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END); |
signal st_RX_UDP_STATE : t_rx_udp_state_type:=IDLE; |
signal s_cnt_udp_rx : std_logic_vector (15 downto 0):=x"0001"; |
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signal s_src_ip_udp_rx : std_logic_vector (31 downto 0):=(others=>'0'); |
signal s_src_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_dst_port : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_data_len_udp_rx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_err_out : std_logic_vector (3 downto 0) :=(others=>'0'); |
--======================================================================================================================= |
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--============================ UDP TX Signals ============================================================================= |
type t_tx_udp_state_type is (IDLE,SEND_DATA); |
signal st_tx_udp_state : t_tx_udp_state_type:=IDLE; |
|
signal s_cnt_udp_tx : std_logic_vector (15 downto 0):=(others=>'0'); |
signal s_ip_data_len : std_logic_vector (15 downto 0); |
signal s_udp_header : std_logic_vector (7 downto 0):=(others=>'0'); |
--========================================================================================================================== |
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--============================ PHY_Interface Signals ======================================================================= |
signal s_gmii_col_reg : std_logic; |
signal s_gmii_col_reg_reg : std_logic; |
signal s_gmii_rx_clk : std_logic; |
--========================================================================================================================== |
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--=========================== Ping_Pong Fifo Signals ======================================================================= |
signal s_empty1 : std_logic; |
signal s_empty2 : std_logic; |
signal s_notempty1 : std_logic; |
signal s_notempty2 : std_logic; |
|
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signal s_data_m : std_logic_vector(7 downto 0); |
signal s_valid_m : std_logic; |
signal s_last_m : std_logic; |
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signal s_wr_en_a : std_logic:='0'; |
signal s_din_a : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_a : std_logic; |
signal s_dout_a : std_logic_vector(7 downto 0); |
signal s_valid_a : std_logic; |
signal s_empty_a : std_logic; |
|
signal s_wr_en_b : std_logic:='0'; |
signal s_din_b : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_rd_en_b : std_logic; |
signal s_dout_b : std_logic_vector(7 downto 0); |
signal s_valid_b : std_logic; |
signal s_empty_b : std_logic; |
|
|
signal s_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_a : std_logic_vector(15 downto 0):=(others=>'0'); |
signal s_rd_cnt_b : std_logic_vector(15 downto 0):=(others=>'0'); |
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signal s_busy_a : std_logic:='0'; |
signal s_busy_b : std_logic:='0'; |
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signal s_last_a : std_logic:='0'; |
signal s_last_b : std_logic:='0'; |
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signal s_dout_len : std_logic_vector(15 downto 0); |
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type t_pingpong_state is (wait_data,rd_fifo_a,rd_fifo_b); |
signal st_ping_pong_state : t_pingpong_state:=wait_data; |
--========================================================================================================================= |
|
|
begin |
|
--===== Process for Deliver Tx_Channel to IP or ARP or Ping Data ============================== |
p_priority:process(i_tx_clk) |
begin |
if (rising_edge(i_tx_clk)) then |
if (i_reset = '1') then |
st_STATE <= IDLE; |
else |
CASE st_STATE IS |
|
WHEN IDLE => |
if (i_req_1 = '1') then |
st_STATE <= DATA_REQ; |
elsif (i_req_2 = '1') then |
st_STATE <= ARP_REQ; |
elsif (i_req_3 = '1') then |
st_STATE <= PING_REQ; |
end if; |
|
WHEN DATA_REQ => |
if (i_req_1 = '0') then |
st_STATE <= IDLE; |
end if; |
|
WHEN ARP_REQ => |
if (i_req_2 = '0') then |
st_STATE <= IDLE; |
end if; |
|
WHEN PING_REQ => |
if (i_req_3 = '0') then |
st_STATE <= IDLE; |
end if; |
|
END CASE; |
end if; |
end if; |
end process p_priority; |
--========================================================================================== |
|
--========== Assign Data to Output ========================================================= |
o_data <= i_data_1 when (st_STATE=DATA_REQ) else i_data_2 when (st_STATE=ARP_REQ) else i_data_3 when (st_STATE=PING_REQ) else(others=>'0'); |
o_valid <= i_valid_1 when (st_STATE=DATA_REQ) else i_valid_2 when (st_STATE=ARP_REQ) else i_valid_3 when (st_STATE=PING_REQ) else '0'; |
o_last <= i_last_1 when (st_STATE=DATA_REQ) else i_last_2 when (st_STATE=ARP_REQ) else i_last_3 when (st_STATE=PING_REQ) else '0'; |
o_grant_1 <= '1' when (st_STATE=DATA_REQ) else '0'; |
o_grant_2 <= '1' when (st_STATE=ARP_REQ) else '0'; |
o_grant_3 <= '1' when (st_STATE=PING_REQ) else '0'; |
--========================================================================================== |
|
end Behavioral; |
/gigabit_udp_mac/trunk/LAN/Ethernet_1G.vhd
0,0 → 1,524
--**************************************************************************************** |
-- Company: |
-- Engineer: Mehran.HekmatPanah |
-- Create Date: 1393/01/18 |
-- Module Name: Ethernet_1G |
-- Project Name: Ethernet_1G |
-- Version: v0.0 |
-- Difference with Old Version: |
-- Target Devices: XC6VLX240t-1FF1156 |
-- Code Status: Final |
-- Operation Clock: Input:125MHz,Output:125MHz |
-- In/Out Rate: 1Gbps/1Gbps |
-- Block RAM Usage: |
-- Slice Usage: |
-- Block Technical Info: |
-- Additional Comments: |
|
--**************************************************************************************** |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
|
library unisim; |
use unisim.vcomponents.all; |
|
|
|
entity Ethernet_1g is |
generic ( |
LAN_Lable : string:="LAN_0"; |
IDELAY_GRP_Str : string:="Grp_KED"; |
IDELAY_GRP_Str_s : string:="<Grp_KED_tx>"; |
g_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector(31 downto 0):= x"9502F900"; --20S |
g_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector(31 downto 0):= x"07735940"; --1S |
g_RE_SEND_ARP_REQUEST : std_logic_vector(3 downto 0):= x"A"; --10 |
g_GENERATE_PING_MODULE : boolean := true; |
g_GENERATE_ARP_MODULE : boolean := true; |
g_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"AABBCCDDEEFF" |
|
); |
port |
( |
|
i_clk_125 : in STD_LOGIC ; |
|
rx_mac_aclk : out STD_LOGIC ; |
gmii_rx_clk : in STD_LOGIC ; |
gmii_tx_clk : out STD_LOGIC ; |
|
i_global_reset : in STD_LOGIC ; |
i_vector_reset : in STD_LOGIC ; |
refclk : in std_logic; |
i_Reset_tx : in STD_LOGIC ; |
i_Reset_rx : in STD_LOGIC ; |
o_tx_clk_out : out STD_LOGIC ; |
o_rx_clk_out : out STD_LOGIC ; |
|
------------------------- UDP ---------------------------- |
-- UDP & IP Tx header construction |
i_udp_tx_src_ip : in std_logic_vector (31 downto 0); |
i_udp_tx_dst_ip : in std_logic_vector (31 downto 0); |
i_udp_tx_data_len : in std_logic_vector (15 downto 0); |
i_udp_tx_protocol : in std_logic_vector (7 downto 0); |
i_udp_tx_src_mac : in std_logic_vector (47 downto 0); |
i_udp_tx_checksum : in std_logic_vector (15 downto 0); |
i_udp_tx_src_port : in std_logic_vector (15 downto 0); |
i_udp_tx_dst_port : in std_logic_vector (15 downto 0); |
i_ip_tx_fragmantation : in std_logic_vector(15 downto 0):=x"4000"; |
i_fragment_len : in std_logic_vector(16 - 1 downto 0):=x"4000"; |
-- UDP TX Inpus |
i_udp_tx_start : in std_logic; |
o_udp_tx_ready : out std_logic; |
o_mac_tx_tready : out std_logic; |
i_udp_tx_din : in std_logic_vector (7 downto 0); |
|
-- UDP RX Outputs |
o_udp_rx_dout : buffer std_logic_vector(7 downto 0); |
o_udp_rx_dout_rdy : buffer std_logic; |
o_udp_rx_dout_last : buffer std_logic; |
|
-- UDP RX Status Outputs |
o_udp_rx_src_ip : out std_logic_vector(31 downto 0); |
o_udp_rx_src_port : out std_logic_vector(15 downto 0); |
o_udp_rx_dst_port : out std_logic_vector(15 downto 0); |
o_udp_rx_data_len : out std_logic_vector(15 downto 0); |
o_udp_rx_err_out : out std_logic_vector(3 downto 0); |
o_udp_tx_err_out : out std_logic_vector(3 downto 0); |
o_arp_rx_err_out : out std_logic_vector(3 downto 0); |
o_ip_rx_fragmantation : out std_logic_vector(15 downto 0); |
|
o_arp_addr_valid : out std_logic; |
-- IP Status |
o_ip_rx_dst_ip : out std_logic_vector(31 downto 0); |
o_ip_rx_err_out : out std_logic_vector (3 downto 0); |
o_ip_tx_err_out : out std_logic_vector (3 downto 0); |
|
|
--------------------- PHY -------------------------------- |
-- o_Rgmii_txc : out std_logic; |
-- o_Rgmii_tx_ctrl : out std_logic; |
-- o_Rgmii_txd : out std_logic_vector(4 downto 0); |
|
-- i_Rgmii_rxc : in std_logic; |
-- i_Rgmii_rx_ctrl : in std_logic; |
-- i_Rgmii_rxd : in std_logic_vector(4 downto 0); |
|
o_gmii_tx_en : out std_logic; |
o_gmii_tx_er : out std_logic; |
o_gmii_txd : out std_logic_vector(7 downto 0); |
|
i_gmii_rx_dv : in std_logic; |
i_gmii_rx_er : in std_logic; |
i_gmii_rxd : in std_logic_vector(7 downto 0); |
|
|
i_gmii_crs : in std_logic; |
i_gmii_col : in std_logic |
|
|
); |
end Ethernet_1g; |
|
architecture Behavioral of Ethernet_1g is |
|
|
COMPONENT tri_mode_ethernet_mac_0 |
PORT ( |
gtx_clk : IN STD_LOGIC; |
glbl_rstn : IN STD_LOGIC; |
rx_axi_rstn : IN STD_LOGIC; |
tx_axi_rstn : IN STD_LOGIC; |
rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0); |
rx_statistics_valid : OUT STD_LOGIC; |
rx_mac_aclk : OUT STD_LOGIC; |
rx_reset : OUT STD_LOGIC; |
rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
rx_axis_mac_tvalid : OUT STD_LOGIC; |
rx_axis_mac_tlast : OUT STD_LOGIC; |
rx_axis_mac_tuser : OUT STD_LOGIC; |
tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
tx_statistics_valid : OUT STD_LOGIC; |
tx_mac_aclk : OUT STD_LOGIC; |
tx_reset : OUT STD_LOGIC; |
tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
tx_axis_mac_tvalid : IN STD_LOGIC; |
tx_axis_mac_tlast : IN STD_LOGIC; |
tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
tx_axis_mac_tready : OUT STD_LOGIC; |
pause_req : IN STD_LOGIC; |
pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
speedis100 : OUT STD_LOGIC; |
speedis10100 : OUT STD_LOGIC; |
gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
gmii_tx_en : OUT STD_LOGIC; |
gmii_tx_er : OUT STD_LOGIC; |
gmii_tx_clk : OUT STD_LOGIC; |
gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
gmii_rx_dv : IN STD_LOGIC; |
gmii_rx_er : IN STD_LOGIC; |
gmii_rx_clk : IN STD_LOGIC; |
rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0); |
tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0) |
); |
END COMPONENT; |
|
--========================================================================================= |
signal s_reset_txn : std_logic; |
signal s_reset_rxn : std_logic; |
|
|
--================================ Ethernet 1g Signals ================================================= |
signal s_tx_clk : std_logic; |
signal s_rx_clk : std_logic; |
signal s_rstn : std_logic; |
signal s_vecrstn : std_logic; |
|
|
|
--mac to gmii_if signals |
signal s_mac_gmii_rxd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_rx_dv : std_logic; |
signal s_mac_gmii_rx_er : std_logic; |
|
signal s_mac_gmii_txd : std_logic_vector(7 downto 0); |
signal s_mac_gmii_tx_en : std_logic; |
signal s_mac_gmii_tx_er : std_logic; |
|
|
|
--ip to mac signals |
signal s_mac_tx_tready : std_logic; |
signal s_mac_tx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_tx_tvalid : std_logic; |
signal s_mac_tx_tlast : std_logic; |
|
signal s_mac_rx_tdata : std_logic_vector(7 downto 0); |
signal s_mac_rx_tvalid : std_logic; |
signal s_mac_rx_tlast : std_logic; |
signal s_mac_gtx_clkout : std_logic; |
|
signal s_Rx_vector : std_logic_vector(80-1 downto 0); |
signal s_Tx_vector : std_logic_vector(80-1 downto 0); |
|
signal i_global_reset_r : std_logic; |
|
signal s_udp_rx_err_out : std_logic_vector (3 downto 0); |
signal s_udp_tx_err_out : std_logic_vector (3 downto 0); |
signal s_arp_rx_err_out : std_logic_vector (3 downto 0); |
--====================================================================================================== |
|
|
constant tx_ifg_delay : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00"; |
signal tx_reset : STD_LOGIC:='0'; |
signal rx_reset : STD_LOGIC:='0'; |
signal Reset_txn : STD_LOGIC:='0'; |
|
signal rx_configuration_vector : std_logic_vector(79 downto 0):=(others => '0'); |
signal tx_configuration_vector : std_logic_vector(79 downto 0):=(others => '0'); |
|
signal pause_req : std_logic; |
signal pause_val : std_logic_vector(15 downto 0); |
|
begin |
|
o_mac_tx_tready <= s_mac_tx_tready; |
|
o_udp_rx_err_out <= s_udp_rx_err_out; |
o_udp_tx_err_out <= s_udp_tx_err_out; |
o_arp_rx_err_out <= s_arp_rx_err_out; |
|
--========================= Clk & Reset =================================================== |
s_rstn <= not(i_global_reset); |
s_reset_txn <= not(i_reset_tx); |
s_reset_rxn <= not(i_reset_rx); |
|
o_tx_clk_out <= s_tx_clk; |
o_rx_clk_out <= s_rx_clk; |
--========================================================================================= |
|
process(i_clk_125) |
|
begin |
if(rising_edge(i_clk_125)) then |
i_global_reset_r <= i_global_reset; |
|
pause_req <= '0'; |
pause_val <= (others => '0'); |
end if; |
end process; |
|
|
--=============================== UDP ==================================================== |
--inst_UDP:UDP_NGC |
inst_UDP:entity work.UDP_KED |
|
|
generic map( |
g_TIME_OUT_LOOKUP_TABLE_ARP => g_TIME_OUT_LOOKUP_TABLE_ARP, |
g_TIME_OUT_WAIT_FOR_ARP_REPLY => g_TIME_OUT_WAIT_FOR_ARP_REPLY, |
g_RE_SEND_ARP_REQUEST => g_RE_SEND_ARP_REQUEST, |
g_GENERATE_PING_MODULE => g_GENERATE_PING_MODULE, |
g_GENERATE_ARP_MODULE => g_GENERATE_ARP_MODULE, |
g_DEFAULT_DST_MAC_ADDR => g_DEFAULT_DST_MAC_ADDR |
) |
port map |
( |
i_ip_tx_fragmantation => i_ip_tx_fragmantation, |
i_fragment_len => i_fragment_len, |
o_ip_rx_fragmantation => o_ip_rx_fragmantation, |
|
i_rx_clk => s_rx_clk, |
i_tx_clk => i_clk_125, --125MHz |
i_reset_tx => tx_reset,-- i_Reset_tx,-- |
i_reset_rx => rx_reset,-- i_Reset_rx,-- |
|
--******************************* IP *************************************** |
-- IP to MAC TX Outputs |
i_mac_tx_tready => s_mac_tx_tready, |
o_mac_tx_tdata => s_mac_tx_tdata, |
o_mac_tx_tvalid => s_mac_tx_tvalid, |
o_mac_tx_tlast => s_mac_tx_tlast, |
|
-- MAC to IP RX Inputs |
i_mac_rx_tdata => s_mac_rx_tdata, |
i_mac_rx_tvalid => s_mac_rx_tvalid, |
i_mac_rx_tlast => s_mac_rx_tlast, |
|
|
--IP Status |
o_ip_rx_dst_ip => o_ip_rx_dst_ip, |
o_ip_rx_err_out => o_ip_rx_err_out, |
o_ip_tx_err_out => o_ip_tx_err_out, |
o_arp_rx_err_out => s_arp_rx_err_out, |
|
--************************** UDP********************************************* |
-- UDP & IP Tx header construction |
i_udp_tx_src_ip => i_udp_tx_src_ip, |
i_udp_tx_dst_ip => i_udp_tx_dst_ip, |
i_udp_tx_data_len => i_udp_tx_data_len, |
i_udp_tx_protocol => i_udp_tx_protocol , |
i_udp_tx_src_mac => i_udp_tx_src_mac, |
i_udp_tx_checksum => i_udp_tx_checksum, |
i_udp_tx_src_port => i_udp_tx_src_port, |
i_udp_tx_dst_port => i_udp_tx_dst_port, |
-- UDP TX Inpus |
i_udp_tx_start => i_udp_tx_start, |
o_udp_tx_ready => o_udp_tx_ready, |
i_udp_tx_din => i_udp_tx_din, |
|
-- UDP RX Outputs |
o_udp_rx_dout => o_udp_rx_dout, |
o_udp_rx_dout_rdy => o_udp_rx_dout_rdy, |
o_udp_rx_dout_last => o_udp_rx_dout_last, |
|
-- UDP RX Status Outputs |
o_udp_rx_src_ip => o_udp_rx_src_ip, |
o_udp_rx_src_port => o_udp_rx_src_port, |
o_udp_rx_dst_port => o_udp_rx_dst_port, |
o_udp_rx_data_len => o_udp_rx_data_len , |
|
o_arp_addr_valid => o_arp_addr_valid, |
|
o_udp_rx_err_out => s_udp_rx_err_out, |
o_udp_tx_err_out => s_udp_tx_err_out |
|
); |
--========================================================================================= |
|
--LAN0_MAC: Entity Work.MAC_Controller |
--GENERIC MAP( |
-- PHY_ADDR => "00100", -- PHY_AD0/1 pulled-down by 1KOhm, PHY_AD2 pulled-up in .ucf file. |
-- CLK_FREQUENCY => 125 |
--) |
--PORT MAP( |
-- CLK => i_clk_125, |
-- IDELAYREFCLK200MHZ => refclk, |
-- ASYNC_RESET => i_Reset_tx, |
-- MAC_ADDR => x"0123456789ab", |
-- MAC_TX_CONFIG => X"0003", -- MAC must must provide pad + crc32 |
-- MAC_RX_CONFIG => x"000F", -- promiscuous mode, strip crc32, accept broadcast/multicast |
-- PHY_CONFIG_CHANGE => '1',--CONFIG_CHANGE_PULSE, |
-- PHY_RESET => '0', |
-- SPEED => "10", -- supersedes defaults within if PHY_CONFIG_CHANGE = '1' |
-- DUPLEX => '1', -- supersedes defaults within if PHY_CONFIG_CHANGE = '1' |
-- TEST_MODE => "00", -- supersedes defaults within if PHY_CONFIG_CHANGE = '1' |
-- POWER_DOWN => '0', -- supersedes defaults within if PHY_CONFIG_CHANGE = '1' |
-- MAC_TX_DATA => s_mac_tx_tdata, |
-- MAC_TX_DATA_VALID => s_mac_tx_tvalid, |
-- MAC_TX_EOF => s_mac_tx_tlast, |
-- MAC_TX_CTS => s_mac_tx_tready, |
-- MAC_RX_DATA => s_mac_rx_tdata, |
-- MAC_RX_DATA_VALID => s_mac_rx_tvalid, |
-- MAC_RX_SOF => open,--s_mac_rx_SOF, |
-- MAC_RX_EOF => s_mac_rx_tlast, |
-- MAC_RX_CTS => '1', -- follow-on processing is expected to always accept data even at max speed. |
-- RESET_N => OPEN,--o_LAN1G_RESETn1, |
-- GMII_MII_TXD => o_gmii_txd, |
-- GMII_MII_TX_EN => o_gmii_tx_en, |
-- GMII_MII_TX_ER => o_gmii_tx_er, |
-- GMII_MII_RX_CLK => i_clk_125, |
-- GMII_MII_RXD => i_gmii_rxd, |
-- GMII_MII_RX_DV => i_gmii_rx_dv, |
-- GMII_MII_RX_ER => i_gmii_rx_er, -- end of MII interface ------ |
|
-- PHY_ID => open |
--); |
Reset_txn <= not i_Reset_tx; |
|
LAN0_MAC : tri_mode_ethernet_mac_0 |
PORT MAP ( |
gtx_clk => i_clk_125, |
glbl_rstn => Reset_txn, |
rx_axi_rstn => '1', |
tx_axi_rstn => '1', |
rx_statistics_vector => open, |
rx_statistics_valid => open, |
rx_mac_aclk => rx_mac_aclk,--?? |
rx_reset => rx_reset, |
rx_axis_mac_tdata => s_mac_rx_tdata, |
rx_axis_mac_tvalid => s_mac_rx_tvalid, |
rx_axis_mac_tlast => s_mac_rx_tlast, |
rx_axis_mac_tuser => open, |
tx_ifg_delay => tx_ifg_delay, |
tx_statistics_vector => open, |
tx_statistics_valid => open, |
tx_mac_aclk => open,--?? |
tx_reset => tx_reset, |
tx_axis_mac_tdata => s_mac_tx_tdata, |
tx_axis_mac_tvalid => s_mac_tx_tvalid, |
tx_axis_mac_tlast => s_mac_tx_tlast, |
tx_axis_mac_tuser => "0", |
tx_axis_mac_tready => s_mac_tx_tready, |
pause_req => pause_req, |
pause_val => pause_val, |
speedis100 => open, |
speedis10100 => open, |
gmii_txd => o_gmii_txd, |
gmii_tx_en => o_gmii_tx_en, |
gmii_tx_er => o_gmii_tx_er, |
gmii_tx_clk => gmii_tx_clk,--?? |
gmii_rxd => i_gmii_rxd, |
gmii_rx_dv => i_gmii_rx_dv, |
gmii_rx_er => i_gmii_rx_er, |
gmii_rx_clk => gmii_rx_clk, |
rx_configuration_vector => rx_configuration_vector, |
tx_configuration_vector => tx_configuration_vector |
); |
|
|
rx_configuration_vector(13 downto 12) <= "10";--1G |
rx_configuration_vector(1) <= '1';--Enable |
|
tx_configuration_vector(13 downto 12) <= "10";--1G |
tx_configuration_vector(1) <= '1';--Enable |
-- -- //////////////////////////// |
|
-- inst_MAC_RGMII: entity work.tri_mode_ethernet_mac_1_example_design |
-- generic map( IDELAY_GRP_Str => IDELAY_GRP_Str ) |
-- port map ( |
-- -- asynchronous reset |
-- ---------------------------- |
-- glbl_rst => '0',--i_global_reset_r, |
|
-- -- 200MHz clock input from board |
-- refclk_bufg => refclk, |
-- -- 125 MHz clock |
-- gtx_clk_bufg => i_clk_125, |
|
-- phy_resetn => open, |
|
|
-- -- RGMII Interface |
-- ---------------------------- |
-- rgmii_txd => o_Rgmii_txd, |
-- rgmii_tx_ctl => o_Rgmii_tx_ctrl, |
-- rgmii_txc => o_Rgmii_txc, |
-- rgmii_rxd => i_Rgmii_rxd, |
-- rgmii_rx_ctl => i_Rgmii_rx_ctrl, |
-- rgmii_rxc => i_Rgmii_rxc, |
|
|
-- -------------------------------------- |
-- rx_axis_tdata => s_mac_rx_tdata , |
-- rx_axis_tvalid => s_mac_rx_tvalid , |
-- rx_axis_tlast => s_mac_rx_tlast , |
-- rx_axis_tready => '1',--s_mac_rx_tready , |
|
-- tx_axis_tdata => s_mac_tx_tdata , |
-- tx_axis_tvalid => s_mac_tx_tvalid , |
-- tx_axis_tlast => s_mac_tx_tlast , |
-- tx_axis_tready => s_mac_tx_tready , |
-- -------------------------------------- |
|
-- -- Serialised statistics vectors |
-- ---------------------------- |
-- tx_statistics_s => open, |
-- rx_statistics_s => open, |
|
-- -- Serialised Pause interface controls |
-- ---------------------------------- |
-- pause_req_s => '0', |
|
-- -- Main example design controls |
-- --------------------------- |
-- mac_speed => "10", |
-- update_speed => '0', |
-- config_board => '0', |
-- serial_response => open, |
-- gen_tx_data => '0', |
-- chk_tx_data => '0', |
-- reset_error => '0', |
-- frame_error => open, |
-- frame_errorn => open, |
-- activity_flash => open, |
-- activity_flashn => open |
-- ); |
-- -- //////////////////////////// |
|
|
s_tx_clk <= i_clk_125; |
s_rx_clk <= i_clk_125; |
|
|
|
-- my_ila_Phy : entity work.ila_0 |
-- PORT MAP ( |
-- clk => i_clk_125, |
|
-- probe0(3 downto 0) => "0000",--i_gmii_rxd, |
-- probe0(4) => i_gmii_rx_dv,--i_gmii_rx_ctrl, |
-- probe0(5) => i_gmii_rx_er,--i_gmii_rxc, |
-- probe0(13 downto 6) => s_mac_rx_tdata , |
-- probe0(14) => s_mac_rx_tvalid , |
-- probe0(15) => s_mac_rx_tlast , |
-- probe0(23 downto 16) => s_mac_tx_tdata , |
-- probe0(24) => s_mac_tx_tvalid , |
-- probe0(25) => s_mac_tx_tlast , |
-- probe0(26) => s_mac_tx_tready , |
-- probe0(30 downto 27) => s_udp_rx_err_out , |
-- probe0(34 downto 31) => s_udp_tx_err_out , |
-- probe0(38 downto 35) => s_arp_rx_err_out , |
-- probe0(39) => i_global_reset , |
-- probe0(40) => tx_reset , |
-- probe0(41) => rx_reset , |
|
-- probe0(49 downto 42) => i_gmii_rxd, |
-- probe0(57 downto 50) => o_udp_rx_dout, |
-- probe0(58) => o_udp_rx_dout_rdy, |
-- probe0(59) => o_udp_rx_dout_last, |
|
-- probe0(255 downto 60) => (others => '0') |
-- ); |
|
|
|
----//////////////////////// |
|
|
|
end Behavioral; |
|
/gigabit_udp_mac/trunk/LAN/GIGABYTE_LAN_Interface.vhd
0,0 → 1,445
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.STD_LOGIC_ARITH.ALL; |
library unisim; |
use unisim.vcomponents.all; |
|
|
|
|
entity GIGABYTE_LAN_Interface is |
generic ( |
LAN_Lable : string:="LAN_0"; |
IDELAY_GRP_Str : string:="Grp_KED"; |
IDELAY_GRP_Str_s : string:="<Grp_KED_tx>"; |
c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"AC1E0101"--x"C0A86403"; --172.30.01.01(FPGA IP Adress) |
-- c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
-- c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5" --UDP Src Port(Value For This Constant is not Importanat); |
|
); |
port( |
clk_125 : in std_logic; |
clk_200 : in std_logic; |
|
--------------------------------------------------------------- |
o_phy_rstn : out STD_LOGIC;--Reset to PHY |
rx_mac_aclk : out STD_LOGIC ; |
i_reset : in STD_LOGIC:='0' ; |
gmii_rx_clk : in STD_LOGIC ; |
gmii_tx_clk : out STD_LOGIC ; |
-- o_Rgmii_txc : out std_logic; |
-- o_Rgmii_tx_ctrl : out std_logic; |
-- o_Rgmii_txd : out std_logic_vector(4 downto 0); |
|
-- i_Rgmii_rxc : in std_logic; |
-- i_Rgmii_rx_ctrl : in std_logic; |
-- i_Rgmii_rxd : in std_logic_vector(4 downto 0); |
|
o_gmii_tx_en : out std_logic; |
o_gmii_tx_er : out std_logic; |
o_gmii_txd : out std_logic_vector(7 downto 0); |
|
i_gmii_rx_dv : in std_logic; |
i_gmii_rx_er : in std_logic; |
i_gmii_rxd : in std_logic_vector(7 downto 0); |
|
o_mac_tx_tready : out std_logic; |
|
i_udp_rx_src_ip : in std_logic_vector(31 downto 0); |
o_udp_rx_src_ip : out std_logic_vector(31 downto 0); |
|
|
o_mdc : out std_logic; |
io_mdio : inout std_logic; |
--------------------------------------------------------- |
--------------- user ------------------------------------ |
o_udp_rx_err_out : out std_logic_vector(3 downto 0); |
i_fragment_len : in std_logic_vector(16 - 1 downto 0):=x"4000"; |
LAN_clk : out std_logic; |
LAN_dout_rdy : out std_logic; |
LAN_dout_last : out std_logic; |
LAN_dout : out std_logic_vector(8 - 1 downto 0); |
LAN_din_rdy : in std_logic; |
LAN_din_last : in std_logic; |
LAN_din : in std_logic_vector(8 - 1 downto 0) |
|
|
); |
end GIGABYTE_LAN_Interface; |
|
architecture Behavioral of GIGABYTE_LAN_Interface is |
|
|
|
--=========================== Reset Generator ========================================== |
component reset_gen |
port |
( |
i_clk : in std_logic; |
i_reset : in std_logic; |
o_global_reset : out std_logic; |
o_vector_reset : out std_logic; |
o_phy_rstn : out std_logic |
|
); |
end component; |
--====================================================================================== |
|
|
|
--====================================================================================== |
component sync_fifo2 |
port |
( |
rst : IN STD_LOGIC; |
wr_clk : IN STD_LOGIC; --Maximum 125MHz |
wr_en : IN STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(10-1 DOWNTO 0); --(last & data) |
|
rd_clk : IN STD_LOGIC; --Tx_Clk(125MHz) |
rd_en : IN STD_LOGIC; |
dout : OUT STD_LOGIC_VECTOR(10-1 DOWNTO 0); |
valid : OUT STD_LOGIC; |
full : OUT STD_LOGIC; |
empty : OUT STD_LOGIC |
|
); |
end component; |
--====================================================================================== |
|
|
--================================= Constant =========================================== |
--Generate Block Conditional Constants |
constant c_GENERATE_PING_MODULE : boolean := true; --if Ping Block is not Used,Value is False |
constant c_GENERATE_ARP_MODULE : boolean := true; --if ARP Block is not Used,Value is False |
constant c_DEFAULT_DST_MAC_ADDR : std_logic_vector (47 downto 0) := x"F46D04962225"; --if ARP Block is not Used,Copy PC MAC Address to This Value |
|
|
--Application Layer Data Length |
constant c_PACKET_LENGTH : std_logic_vector (15 downto 0):= x"05c0"; --1472 (Maximum Application Layer Packet Length) |
--constant c_udp_tx_src_ip : std_logic_vector (31 downto 0):= x"AC1E0101";--x"C0A86403"; --172.30.01.01(FPGA IP Adress) |
--constant c_udp_tx_src_port : std_logic_vector (15 downto 0):= x"0401"; --UDP Src Port(Value For This Constant is not Importanat) |
constant c_udp_tx_dst_ip : std_logic_vector (31 downto 0):= x"AC1E0103";--x"C0A86402"; --172.30.01.03(PC IP Address) |
constant c_udp_tx_protocol : std_logic_vector (7 downto 0) := x"11"; --UDP Protocol |
constant c_udp_tx_src_mac : std_logic_vector (47 downto 0):= x"112233445566"; --FPGA MAC Address |
constant c_udp_tx_checksum : std_logic_vector (15 downto 0):= x"0000"; --UDP Checksum(Value For This Constant is not Importanat) |
--constant c_udp_tx_dst_port : std_logic_vector (15 downto 0):= x"0FF5"; --UDP Dst Port(Value For This Constant is not Importanat) |
|
--ARP Constants |
constant c_TIME_OUT_LOOKUP_TABLE_ARP : std_logic_vector (31 downto 0) := x"9502F900"; --20S(Value/125MHz = 20 ) |
constant c_TIME_OUT_WAIT_FOR_ARP_REPLY : std_logic_vector (31 downto 0) := x"07735940"; --1S (Value/125MHz = 1 ) |
constant c_RE_SEND_ARP_REQUEST : std_logic_vector (3 downto 0) := x"A"; --10 |
|
|
--IP Constants |
constant c_IP_TTL : std_logic_vector (7 downto 0) := x"80"; -- IP Packet Time to live |
constant c_IP_BC_ADDR : std_logic_vector (31 downto 0) := x"ffffffff"; -- Broadcast IP Address |
constant c_MAC_BC_ADDR : std_logic_vector (47 downto 0) := x"ffffffffffff"; -- Broadcast |
--======================================================================================== |
|
|
|
--============================== Signals ================================================= |
signal s_Reset_tx_for_eth : std_logic:='0'; |
signal s_Reset_rx_for_eth : std_logic:='0'; |
signal s_Reset_tx : std_logic:='0'; |
signal s_Reset_rx : std_logic:='0'; |
signal reset_reg : std_logic_vector(9 downto 0):=(others=>'0'); |
|
|
signal s_dout : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_dout_valid : std_logic:='0'; |
signal s_dout_last : std_logic:='0'; |
|
signal s_dout1 : std_logic_vector(7 downto 0):=(others=>'0'); |
signal s_dout_valid1 : std_logic:='0'; |
signal s_dout_last1 : std_logic:='0'; |
|
|
signal s_udp_rx_sigs : std_logic_vector(10-1 downto 0); |
signal s_udp_sigs : std_logic_vector(10-1 downto 0); |
signal s_udp_sigs_valid : std_logic:='0'; |
|
signal s_sync_fifo_empty : std_logic:='1'; |
signal s_not_sync_fifo_empty : std_logic:='0'; |
|
signal s_udp_data_in : std_logic_vector(8-1 downto 0):=(others=>'0'); |
signal s_udp_valid_in : std_logic:='0'; |
signal s_udp_last_in : std_logic:='0'; |
signal s_udp_last_in_r : std_logic:='0'; |
|
signal s_udp_rx_dout_last_reset : STD_LOGIC:='0'; |
signal s_udp_rx_dout_rdy_r : std_logic:='0'; |
signal internal_rst : std_logic; |
signal vector_rst : std_logic; |
|
signal s_udp_tx_data_len : std_logic_vector (15 downto 0):= c_PACKET_LENGTH; --1472 (Maximum Application Layer Packet Length) |
signal s_udp_tx_start : std_logic:='0'; |
signal s_udp_tx_ready : std_logic; |
signal s_udp_tx_din : std_logic_vector(7 downto 0); |
|
signal s_udp_rx_dout : std_logic_vector(7 downto 0); |
signal s_udp_rx_dout_rdy : std_logic; |
signal s_udp_rx_dout_last : std_logic; |
|
signal s_udp_rx_src_ip : std_logic_vector(31 downto 0); |
signal s_udp_rx_src_port : std_logic_vector(15 downto 0); |
signal s_udp_rx_dst_port : std_logic_vector(15 downto 0); |
signal s_udp_rx_data_len : std_logic_vector(15 downto 0); |
signal s_udp_rx_err_out_top : std_logic_vector(3 downto 0); |
signal s_udp_tx_err_out_top : std_logic_vector(3 downto 0); |
signal s_arp_rx_err_out_top : std_logic_vector(3 downto 0); |
signal s_ip_rx_dst_ip_top : std_logic_vector(31 downto 0); |
signal s_ip_rx_err_out_top : std_logic_vector (3 downto 0); |
signal s_ip_tx_err_out_top : std_logic_vector (3 downto 0); |
signal s_arp_addr_valid : std_logic:='0'; |
|
|
signal s_rx_clk_out : std_logic; |
signal s_tx_clk_out : std_logic; |
|
signal s_tx_fragmantation : std_logic_vector (15 downto 0):=x"4000"; |
|
|
|
|
|
--======================================================================================== |
|
begin |
|
o_mdc <= '0'; |
io_mdio <= '0'; |
|
|
o_udp_rx_err_out <=s_udp_rx_err_out_top; |
|
|
|
|
inst_reset_gen: reset_gen |
port map |
( |
i_clk => clk_125, |
i_reset => i_reset, |
o_global_reset => internal_rst, |
o_vector_reset => vector_rst, |
o_phy_rstn => o_phy_rstn |
); |
|
--========================================================================== |
s_Reset_tx_for_eth <= internal_rst or s_Reset_tx; |
s_Reset_rx_for_eth <= internal_rst or s_Reset_rx; |
|
|
|
|
--============================ Ethernet_1g ================================= |
inst_Ethernet_1g: entity work.Ethernet_1g |
generic map( |
LAN_Lable => LAN_Lable, |
IDELAY_GRP_Str => IDELAY_GRP_Str, |
IDELAY_GRP_Str_s => IDELAY_GRP_Str_s, |
g_TIME_OUT_LOOKUP_TABLE_ARP => c_TIME_OUT_LOOKUP_TABLE_ARP, |
g_TIME_OUT_WAIT_FOR_ARP_REPLY => c_TIME_OUT_WAIT_FOR_ARP_REPLY, |
g_RE_SEND_ARP_REQUEST => c_RE_SEND_ARP_REQUEST, |
g_GENERATE_PING_MODULE => c_GENERATE_PING_MODULE, |
g_GENERATE_ARP_MODULE => c_GENERATE_ARP_MODULE, |
g_DEFAULT_DST_MAC_ADDR => c_DEFAULT_DST_MAC_ADDR |
|
) |
port map |
( |
|
i_clk_125 => clk_125, --125MHz |
refclk => clk_200, --200MHz |
rx_mac_aclk => rx_mac_aclk , |
gmii_rx_clk => gmii_rx_clk , |
gmii_tx_clk => gmii_tx_clk , |
|
i_global_reset => internal_rst, --Active High |
i_vector_reset => vector_rst, --Active High |
i_Reset_tx => s_Reset_tx_for_eth, |
i_Reset_rx => s_Reset_rx_for_eth, |
o_tx_clk_out => open, --125MHz |
o_rx_clk_out => s_rx_clk_out, --125MHz |
|
--================= UDP ============================ |
-- UDP & IP Tx header |
i_udp_tx_src_ip => c_udp_tx_src_ip, |
i_udp_tx_dst_ip => i_udp_rx_src_ip,--c_udp_tx_dst_ip, |
i_udp_tx_data_len => s_udp_tx_data_len, |
i_udp_tx_protocol => c_udp_tx_protocol, |
i_udp_tx_src_mac => c_udp_tx_src_mac, |
i_udp_tx_checksum => c_udp_tx_checksum, |
i_udp_tx_src_port => s_udp_rx_dst_port,--c_udp_tx_src_port, |
i_udp_tx_dst_port => s_udp_rx_src_port,--c_udp_tx_dst_port,-- |
i_ip_tx_fragmantation => s_tx_fragmantation, |
i_fragment_len => i_fragment_len, |
-- UDP TX Inpus |
i_udp_tx_start => s_udp_tx_start, |
o_udp_tx_ready => s_udp_tx_ready, |
o_mac_tx_tready => open,--o_mac_tx_tready,-- |
i_udp_tx_din => s_udp_tx_din, |
|
-- UDP RX Outputs |
o_udp_rx_dout => s_udp_rx_dout, |
o_udp_rx_dout_rdy => s_udp_rx_dout_rdy, |
o_udp_rx_dout_last => s_udp_rx_dout_last, |
|
-- UDP RX Status Outp |
o_udp_rx_src_ip => o_udp_rx_src_ip, |
o_udp_rx_src_port => s_udp_rx_src_port, |
o_udp_rx_dst_port => s_udp_rx_dst_port, |
o_udp_rx_data_len => s_udp_rx_data_len, |
o_udp_rx_err_out => s_udp_rx_err_out_top, |
o_udp_tx_err_out => s_udp_tx_err_out_top, |
o_arp_rx_err_out => s_arp_rx_err_out_top, |
-- o_ip_rx_fragmantation => open,--o_ip_rx_fragmantation, |
o_arp_addr_valid => s_arp_addr_valid, |
-- IP Status |
o_ip_rx_dst_ip => s_ip_rx_dst_ip_top, |
o_ip_rx_err_out => s_ip_rx_err_out_top, |
o_ip_tx_err_out => s_ip_tx_err_out_top, |
|
|
--=============== PHY ========================== |
-- o_Rgmii_txc => o_Rgmii_txc, |
-- o_Rgmii_tx_ctrl => o_Rgmii_tx_ctrl, |
-- o_Rgmii_txd => o_Rgmii_txd, |
|
-- i_Rgmii_rxc => i_Rgmii_rxc, |
-- i_Rgmii_rx_ctrl => i_Rgmii_rx_ctrl, |
-- i_Rgmii_rxd => i_Rgmii_rxd, |
|
o_gmii_tx_en => o_gmii_tx_en , |
o_gmii_tx_er => o_gmii_tx_er , |
o_gmii_txd => o_gmii_txd , |
|
i_gmii_rx_dv => i_gmii_rx_dv , |
i_gmii_rx_er => i_gmii_rx_er , |
i_gmii_rxd => i_gmii_rxd , |
|
i_gmii_crs => '0', |
i_gmii_col => '0' |
); |
|
|
--================================================= |
|
|
|
|
----================================================================================ |
----process(s_rx_clk_out) |
----begin |
----if rising_edge(s_rx_clk_out) then |
---- s_udp_rx_dout_last_reset <= s_udp_rx_dout_last; |
---- if (s_udp_rx_dout_last_reset = '1') then |
---- reset_reg <= (others=>'1'); |
---- else |
---- reset_reg <= reset_reg(8 downto 0) & '0'; |
---- end if; |
----end if; |
----end process; |
|
----s_Reset_rx <= reset_reg(9); |
----================================================================================ |
|
|
|
|
----========================== Recieved UDP Data =================================== |
process(s_rx_clk_out) |
begin |
if rising_edge(s_rx_clk_out) then |
s_udp_rx_dout_rdy_r <= s_udp_rx_dout_rdy; |
s_udp_rx_sigs <= s_udp_rx_dout_last & s_udp_rx_dout_rdy & s_udp_rx_dout; |
end if; |
end process; |
|
|
|
inst_sync_fifo: sync_fifo2 |
port map |
( |
rst => '0', |
wr_clk => s_rx_clk_out, |
wr_en => s_udp_rx_dout_rdy_r, |
din => s_udp_rx_sigs, |
|
rd_clk => clk_125, |
rd_en => s_not_sync_fifo_empty, |
empty => s_sync_fifo_empty, |
dout => s_udp_sigs, |
valid => s_udp_sigs_valid, |
full => open |
|
|
); |
|
process(clk_125) |
begin |
if rising_edge(clk_125) then |
s_not_sync_fifo_empty <= not(s_sync_fifo_empty); |
|
if (s_udp_sigs_valid = '1') then |
s_udp_data_in <= s_udp_sigs(7 downto 0); |
s_udp_valid_in <= s_udp_sigs(8); |
s_udp_last_in <= s_udp_sigs(9); |
else |
s_udp_data_in <= (others=>'0'); |
s_udp_valid_in <= '0'; |
s_udp_last_in <= '0'; |
end if; |
|
end if; |
end process; |
|
----================================================================================== |
|
|
--======================= ping_pong fifo ========================== |
inst_ping_pong_fifo2: entity work.ping_pong_fifo2_KED |
generic map( |
g_PACKET_LENGTH => c_PACKET_LENGTH) |
port map ( |
i_clk => clk_125, |
i_rst => internal_rst, |
|
|
-- i_din => s_udp_data_in, |
-- i_din_valid => s_udp_valid_in, |
-- i_din_last => s_udp_last_in, |
|
i_din => LAN_din, |
i_din_valid => LAN_din_rdy, |
i_din_last => LAN_din_last, |
|
|
--to UDP |
i_rd_en => s_udp_tx_ready, |
o_dout => s_udp_tx_din, |
o_start_out => s_udp_tx_start, |
o_dout_len => s_udp_tx_data_len, |
o_fragment => s_tx_fragmantation, |
|
fifo_ready => o_mac_tx_tready,--open,-- |
full => open, |
o_wr_cnta => open, |
o_wr_cntb => open); |
|
|
LAN_clk <= clk_125; |
LAN_dout_rdy <= s_udp_valid_in; |
LAN_dout_last <= s_udp_last_in; |
LAN_dout <= s_udp_data_in; |
|
--======================= LAN TX Send Data ========================== |
|
|
end Behavioral; |
|
/gigabit_udp_mac/trunk/LAN/ping_pong_fifo_KED.vhd
0,0 → 1,476
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.STD_LOGIC_ARITH.ALL; |
|
|
|
entity ping_pong_fifo2_KED is |
generic ( |
g_PACKET_LENGTH : std_logic_vector(15 downto 0):= x"05c0"; --1472(maximum UDP Packet Length) |
g_use_fragment : boolean:= false |
); |
port |
( |
i_clk : in std_logic; --Tx_Clk (125MHz) |
i_rst : in std_logic; |
|
|
i_din : in std_logic_vector(8-1 downto 0); |
i_din_valid : in std_logic:='0'; |
i_din_last : in std_logic:='0'; |
|
--Read Clock |
o_dout_len : out std_logic_vector(15 downto 0):=(others=>'0'); |
o_start_out : out std_logic:='0'; --Start Pulse for Ethernet 1g Block |
i_rd_en : in std_logic; |
o_dout : out std_logic_vector(8-1 downto 0):=(others=>'0'); |
o_fragment : out std_logic_vector(16-1 downto 0):=x"4000"; |
|
fifo_ready : out std_logic; |
full : out std_logic; |
o_wr_cnta : out std_logic_vector(15 downto 0):=(others=>'0'); |
o_wr_cntb : out std_logic_vector(15 downto 0):=(others=>'0') |
|
|
); |
end ping_pong_fifo2_KED; |
|
architecture Behavioral of ping_pong_fifo2_KED is |
|
--============================================================================================== |
COMPONENT data_fifo_KED |
PORT ( |
clk : IN STD_LOGIC; |
srst : IN STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
wr_en : IN STD_LOGIC; |
rd_en : IN STD_LOGIC; |
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
full : OUT STD_LOGIC; |
empty : OUT STD_LOGIC; |
valid : OUT STD_LOGIC; |
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); |
prog_full : OUT STD_LOGIC |
); |
END COMPONENT; |
|
|
COMPONENT Arr_fifo_KED |
PORT ( |
clk : IN STD_LOGIC; |
srst : IN STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
wr_en : IN STD_LOGIC; |
rd_en : IN STD_LOGIC; |
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
full : OUT STD_LOGIC; |
empty : OUT STD_LOGIC; |
valid : OUT STD_LOGIC |
); |
END COMPONENT; |
--========================== Signals =========================================================== |
|
--Data fifo Signals |
signal s_dina :std_logic_vector(8-1 downto 0):=(others=>'0'); |
signal s_dinb :std_logic_vector(16-1 downto 0):=(others=>'0'); |
signal s_douta :std_logic_vector(8-1 downto 0); |
signal s_doutb :std_logic_vector(16-1 downto 0); |
signal s_wr_en_a :std_logic:='0'; |
signal s_wr_en_b :std_logic:='0'; |
signal s_rd_ena :std_logic:='0'; |
signal s_rd_enb :std_logic:='0'; |
signal s_rst_a :std_logic:='1'; |
signal s_rst_b :std_logic:='1'; |
signal s_empty_a :std_logic; |
signal s_empty_b :std_logic; |
|
|
--Control Signals |
signal s_line_busy_for_a :std_logic:='1'; |
signal s_line_busy_for_b :std_logic:='1'; |
|
signal s_wr_cnta :std_logic_vector(16-1 downto 0):=(others=>'0'); |
signal s_wr_cnta_r1 :std_logic_vector(16-1 downto 0):=(others=>'0'); |
signal s_wr_cnta_r2 :std_logic_vector(16-1 downto 0):=(others=>'0'); |
signal s_wr_cnta_r3 :std_logic_vector(16-1 downto 0):=(others=>'0'); |
signal s_wr_cntb :std_logic_vector(16-1 downto 0):=(others=>'0'); |
signal s_wd_cnt :std_logic_vector(16-1 downto 0):=(others=>'0'); --Watch Dog Timer |
signal s_req_cnt :std_logic_vector(5-1 downto 0):=(others=>'0'); --Watch Dog Timer |
|
signal s_start_out :std_logic:='0'; |
signal delay_cnt :std_logic_vector(8-1 downto 0):=(others=>'0'); |
|
signal s_prog_full_a :std_logic; |
signal s_prog_full_b :std_logic; |
|
signal s_full_a :std_logic; |
signal s_full_b :std_logic; |
|
--type t_state is (reset , idle , wr_in_a_rd_of_b , wait_4_free_line_from_b , wr_in_b_rd_of_a , wait_4_free_line_from_a); |
--signal st_state : t_state:=reset; |
|
signal reset : std_logic:='1'; |
signal idle : std_logic:='0'; |
signal wr_in_a_rd_of_b : std_logic:='0'; |
signal wait_4_free_line_from_b : std_logic:='0'; |
signal wr_in_b_rd_of_a : std_logic:='0'; |
signal wait_4_free_line_from_a : std_logic:='0'; |
|
signal s_dout_len : std_logic_vector(15 downto 0):=(others=>'0'); |
signal LED_state : std_logic_vector(7 downto 0):=(others=>'1'); |
|
signal s_fifo_valida : std_logic:='0'; |
signal s_fifo_validb : std_logic:='0'; |
|
signal prog_full1 : std_logic:='0'; |
signal prog_full2 : std_logic:='0'; |
|
signal s_mac_ready : std_logic:='0'; |
|
type General_State is (St_init,St_idle,St_0,St_1,St_1_2,St_2,St_3,St_4,St_5,St_6,St_7); |
signal St_ctrl: General_State:=St_idle; |
|
constant FrRSVD : std_logic:='0'; |
signal dntFragSet : std_logic:='0'; |
signal MoreFrag: std_logic:='0'; |
|
signal s_wd_cnt_rst: std_logic:='0'; |
|
signal offset_fragment : std_logic_vector(12 downto 0):=(others=>'0'); |
signal s_udp_header_len : std_logic_vector(3 downto 0):=x"1"; |
signal s_fragment : std_logic_vector(16-1 downto 0):=x"4000"; |
|
|
signal rdySetLast : std_logic:='0'; |
signal s_wr_en_b_r0 : std_logic:='0'; |
signal s_wr_en_b_r1 : std_logic:='0'; |
signal s_dinb_r0 :std_logic_vector(16-1 downto 0):=(others=>'0'); |
|
signal remain_len :std_logic_vector(16-1 downto 0):=(others=>'0'); |
|
signal data_fifo_cnt :std_logic_vector(10 downto 0):=(others=>'0'); |
signal LastPacket : std_logic:='0'; |
|
signal cntr_frag :std_logic_vector(7 downto 0):=(others=>'0'); |
signal Num_frag :std_logic_vector(7 downto 0):=(others=>'0'); |
signal Num_frag_rst : std_logic:='0'; |
signal remainPacket : std_logic:='0'; |
signal readyFornext : std_logic:='1'; |
signal cntr_wait :std_logic_vector(7 downto 0):=(others=>'0'); |
|
begin |
|
|
o_dout_len <= s_dout_len; |
o_start_out <= s_start_out; |
|
o_fragment <= s_fragment When g_use_fragment else x"4000"; |
|
s_mac_ready <= i_rd_en; |
s_rd_ena <= s_mac_ready; |
o_dout <= s_douta; |
|
|
--================= Process for Continues Writing and Discontinues Reading Data ================= |
process(i_clk) |
begin |
if rising_edge(i_clk) then |
s_rst_a <= i_rst; |
|
fifo_ready <= not(prog_full1);-- and readyFornext; |
s_dina <= i_din; |
s_wr_en_a <= i_din_valid; |
-- s_wr_cnta_r1 <= s_wr_cnta; |
-- s_wr_cnta_r2 <= s_wr_cnta_r1; |
|
-- s_wr_en_b_r0 <= i_din_last; |
-- s_wr_en_b_r1 <= s_wr_en_b_r0; |
---- s_wr_cnta_r3 <= s_wr_cnta_r2; |
|
---- if (s_wr_cnta>=g_PACKET_LENGTH-1) then |
---- s_dinb <= s_wr_cntb - g_PACKET_LENGTH + 1; |
---- else |
-- s_dinb <= s_wr_cntb + 1; |
---- end if; |
|
s_dinb <= s_wr_cntb + 1; |
s_wr_en_b <= i_din_last; |
-- s_dinb <= "00000" & data_fifo_cnt; |
-- s_wr_en_b <= s_wr_en_b_r1; |
|
-- if (s_wr_cnta < (g_PACKET_LENGTH & '0' )-1 and rdySetLast = '1') then |
-- s_dinb <= s_dinb_r0; |
-- s_wr_en_b <= s_wr_en_b_r0; |
-- s_wr_en_b_r0 <= '0'; |
-- rdySetLast <= '0'; |
-- else |
-- s_wr_en_b <= '0'; |
-- end if; |
|
-- if (i_din_last = '1') then |
-- s_dinb_r0 <= s_wr_cntb + 1; |
-- s_wr_en_b_r0 <= '1'; |
-- rdySetLast <= '1'; |
-- end if; |
|
if (s_rst_a = '1') then |
s_wr_cnta <= (others => '0'); |
s_wr_cntb <= (others => '0'); |
s_wd_cnt <= (others => '0'); |
Num_frag <= (others => '0'); |
Cntr_frag <= (others => '0'); |
remainPacket<= '0'; |
readyFornext<= '1'; |
dntFragSet <= '1'; |
MoreFrag <= '0'; |
offset_fragment <= (others => '0'); |
s_fragment <= x"4000"; |
s_udp_header_len <= x"1"; |
St_ctrl <= st_idle; |
-- elsif (i_din_valid = '1') then |
-- if (s_wd_cnt_rst = '1') then |
-- s_wr_cnta <= s_wr_cnta - s_dout_len +1; |
-- else |
-- s_wr_cnta <= s_wr_cnta + 1; |
-- end if; |
-- elsif (s_wd_cnt_rst = '1') then |
-- s_wr_cnta <= s_wr_cnta - s_dout_len; |
end if; |
|
if (i_din_last = '1') then |
s_wr_cntb <= (others => '0'); |
readyFornext<= '0'; |
-- if (data_fifo_cnt >= g_PACKET_LENGTH-1 ) then |
-- remainPacket <= '1'; |
-- end if; |
else |
if (i_din_valid = '1') then |
if (s_wr_cntb >= g_PACKET_LENGTH-1) then |
s_wr_cntb <= s_wr_cntb - g_PACKET_LENGTH + 1; |
-- Num_frag <= Num_frag+ 1; |
else |
s_wr_cntb <= s_wr_cntb + 1; |
end if; |
end if; |
end if; |
|
if (s_wd_cnt_rst = '1') then |
s_wd_cnt <= (others => '0'); |
elsif (s_mac_ready = '1') then |
s_wd_cnt <= s_wd_cnt + 1; |
end if; |
|
-- if (Num_frag_rst = '1') then |
-- Num_frag <= (others => '0'); |
-- end if; |
|
-- if (readyFornext = '0') then |
-- cntr_wait <= cntr_wait + 1; |
-- else |
-- cntr_wait <= (others => '0'); |
-- end if; |
|
-- if (cntr_wait = 100) then |
-- readyFornext<= '1'; |
-- end if; |
|
if (s_wd_cnt = s_dout_len -1) then |
s_wd_cnt_rst <= '1'; |
end if; |
|
-- Num_frag_rst <= '0'; |
|
case St_ctrl is |
When st_idle => |
LED_state <= x"FF"; |
s_start_out <= '0'; |
s_wd_cnt_rst <= '0'; |
|
-- if (remainPacket = '1') then |
-- St_ctrl <= st_0; |
-- remainPacket<= '0'; |
-- els |
if (s_empty_b = '0') then |
s_rd_enb <= '1'; |
St_ctrl <= st_1; |
-- elsif (Cntr_frag < Num_frag) then |
-- elsif (s_wr_cnta_r2 >= g_PACKET_LENGTH-1) then |
elsif (data_fifo_cnt >= g_PACKET_LENGTH-1) then |
St_ctrl <= st_0; |
end if; |
|
When st_0 => -- Befor LastPack |
LED_state <= x"00"; |
s_start_out <= '1'; |
s_udp_header_len<= x"0"; |
s_fragment <= "001" & offset_fragment;--FrRSVD & dntFragSet & MoreFrag & offset_fragment |
offset_fragment <= offset_fragment + g_PACKET_LENGTH(15 downto 3)+s_udp_header_len; |
s_dout_len <= g_PACKET_LENGTH; |
Cntr_frag <= Cntr_frag + 1; |
St_ctrl <= st_2; |
|
When st_1 => |
LED_state <= x"01"; |
s_rd_enb <= '0'; |
Cntr_frag <= (others => '0'); |
-- Num_frag_rst <= '1'; |
if (s_fifo_validb = '1') then |
-- if (s_doutb >= g_PACKET_LENGTH-1 ) then |
-- remain_len <= s_doutb - g_PACKET_LENGTH; |
-- LastPacket <= '1'; |
-- St_ctrl <= st_0; |
-- else |
-- St_ctrl <= st_1_2; |
-- s_dout_len <= s_doutb; |
-- end if; |
St_ctrl <= st_1_2; |
s_dout_len <= s_doutb; |
end if; |
|
When st_1_2 => --LastPack |
LED_state <= x"12"; |
s_start_out <= '1'; |
s_udp_header_len <= x"1"; |
s_fragment <= "000" & offset_fragment;--FrRSVD & dntFragSet & MoreFrag & offset_fragment |
offset_fragment <= (others => '0'); |
-- s_dout_len <= s_doutb; |
St_ctrl <= st_2; |
|
When st_2 => |
LED_state <= x"02"; |
if (s_mac_ready = '1') then |
St_ctrl <= st_3; |
if (s_wd_cnt = s_dout_len -1) then |
s_wd_cnt_rst <= '1'; |
s_start_out <= '0'; |
St_ctrl <= st_4; |
-- if (i_din_valid = '1') then |
-- s_wr_cnta <= s_wr_cnta - s_dout_len +1; |
-- else |
-- s_wr_cnta <= s_wr_cnta - s_dout_len; |
-- end if; |
end if; |
end if; |
|
When st_3 => |
LED_state <= x"03"; |
s_start_out <= '0'; |
-- if (s_mac_ready = '0') then |
if (s_wd_cnt = s_dout_len -1) then |
s_wd_cnt_rst <= '1'; |
St_ctrl <= st_idle;--st_4; |
-- if (i_din_valid = '1') then |
-- s_wr_cnta <= s_wr_cnta - s_dout_len +1; |
-- else |
-- s_wr_cnta <= s_wr_cnta - s_dout_len; |
-- end if; |
end if; |
|
When st_4 => |
LED_state <= x"04"; |
s_wd_cnt_rst <= '0'; |
St_ctrl <= st_5; |
|
When st_5 => |
LED_state <= x"05"; |
St_ctrl <= st_6; |
|
When st_6 => |
LED_state <= x"06"; |
St_ctrl <= st_7; |
|
When st_7 => |
LED_state <= x"07"; |
St_ctrl <= st_idle; |
|
When others => |
end case; |
|
|
end if; |
end process; |
|
|
|
--========================Fifo for Ping_Pong Writing and Reading Data ============================= |
inst_data_fifo:data_fifo_KED |
port map |
( |
clk => i_clk, |
srst => s_rst_a, |
wr_en => s_wr_en_a, |
din => s_dina, |
rd_en => s_rd_ena, |
dout => s_douta, |
valid => s_fifo_valida, |
data_count => data_fifo_cnt, |
prog_full => prog_full1, |
full => s_full_a, |
empty => s_empty_a |
); |
--========================Fifo for Ping_Pong Writing and Reading Data ============================= |
inst_Tlast_fifo:Arr_fifo_KED |
port map |
( |
clk => i_clk, |
srst => s_rst_a, |
wr_en => s_wr_en_b, |
din => s_dinb, |
rd_en => s_rd_enb, |
dout => s_doutb, |
valid => s_fifo_validb, |
full => s_full_b, |
empty => s_empty_b |
); |
|
--================================================================================================= |
--my_ila_ping_pong : entity work.ila_LAN |
--PORT MAP ( |
-- clk => i_clk, |
|
-- probe0(0) => s_rst_a, |
-- probe0(1) => s_wr_en_a, |
-- probe0(9 downto 2) => s_dina, |
-- probe0(10) => s_rd_ena, |
-- probe0(18 downto 11) => s_douta, |
-- probe0(19) => s_fifo_valida, |
-- probe0(20) => prog_full1, |
-- probe0(21) => s_full_a, |
-- probe0(22) => s_empty_a, |
-- probe0(23) => s_mac_ready, |
-- probe0(39 downto 24) => s_wd_cnt, |
-- probe0(55 downto 40) => s_wr_cnta, |
-- probe0(56) => i_din_valid, |
-- probe0(57) => i_din_last, |
|
-- probe0(58) => s_wr_en_b, |
-- probe0(74 downto 59) => s_dinb, |
-- probe0(75) => s_rd_enb, |
-- probe0(91 downto 76) => s_doutb, |
-- probe0(92) => s_fifo_validb, |
-- probe0(93) => s_full_b, |
-- probe0(94) => s_empty_b, |
|
-- probe0(102 downto 95) => LED_state, |
-- probe0(118 downto 103) => s_fragment, |
-- probe0(134 downto 119) => s_wr_cntb, |
-- probe0(135) => s_wd_cnt_rst, |
-- probe0(151 downto 136) => s_wr_cnta_r2, |
-- probe0(152) => s_wr_en_b_r0 , |
-- probe0(153) => s_wr_en_b_r1 , |
-- probe0(154) => Num_frag_rst ,-- LastPacket,-- , |
-- probe0(162 downto 155) => cntr_frag,--remain_len,--s_dinb_r0 , |
-- probe0(170 downto 163) => Num_frag,--data_fifo_cnt, |
-- probe0(181 downto 171) => data_fifo_cnt, |
-- probe0(182) => remainPacket, |
-- probe0(183) => readyFornext, |
|
-- probe0(255 downto 184) => (others => '0') |
--); |
--================================================================================================= |
|
|
end Behavioral; |
/gigabit_udp_mac/trunk/LAN/reset_gen.vhd
0,0 → 1,74
--**************************************************************************************** |
-- Engineer: Mehran.HekmatPanah |
-- Module Name: Reset_Gen |
-- Project Name: Ethernet_1G |
-- Version: v0.0 |
-- Difference with Old Version: |
-- Target Devices: XC6VLX240t-1FF1156 |
-- Code Status: Final |
-- Operation Clock: Input:100MHz,Output:100MHz |
-- In/Out Rate: -- |
-- Block RAM Usage: |
-- Slice Usage: |
-- Block Technical Info: |
-- Additional Comments: |
|
--**************************************************************************************** |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.NUMERIC_STD.all; |
use IEEE.std_logic_unsigned.all; |
|
--library work; |
--use work.signal_Package.all; |
|
entity reset_gen is |
port |
( |
i_clk : in std_logic; |
i_reset : in std_logic; |
o_global_reset : out std_logic:='1'; |
o_vector_reset : out std_logic:='1'; |
o_phy_rstn : out std_logic:='1' |
); |
end reset_gen; |
|
architecture Behavioral of reset_gen is |
|
signal s_cnt_rst : std_logic_vector(31 downto 0):=(others=>'0'); |
signal s_reset : std_logic:='1'; |
|
begin |
|
|
--================ Generate Reset's ======================= |
p_reset_generator: process(i_clk) |
begin |
if rising_edge(i_clk) then |
if(s_reset='1') then |
s_cnt_rst <= (others=>'0'); |
o_global_reset <= '1'; |
o_phy_rstn <= '1'; |
s_reset <= '0'; |
else |
s_cnt_rst <= s_cnt_rst+1; |
o_global_reset <= '1'; |
o_phy_rstn <= '1'; |
if (s_cnt_rst>=8000000) then --8ms |
s_cnt_rst <= x"007A1200"; --8000000 |
--s_cnt_rst <= x"00000320"; |
o_global_reset <= '0'; |
elsif (s_cnt_rst>7000000) then --40ms |
o_phy_rstn <= '1'; |
elsif (s_cnt_rst>2000000) then --16ms |
o_phy_rstn <= '0'; |
o_vector_reset <= '0'; |
end if; |
|
end if; |
end if; |
end process p_reset_generator; |
--========================================================== |
|
end Behavioral; |
|
/gigabit_udp_mac/trunk/MAC/GMII_MII_WRAPPER_V6.vhd
0,0 → 1,529
------------------------------------------------------------- |
-- Filename: GMII_MII_WRAPPER_V5.VHD |
-- Version: 1 |
-- Date last modified: 10/28/11 |
-- Inheritance: GMII_MII_WRAPPER.VHD, rev1 4-20-10 |
-- |
-- description: Wrapper between the MAC and the PHY (GMII/MII interface) |
-- 10/100 Mbps: Complies with the MII interface specification in the 802.3 standard clause 22 |
-- 1000 Mbps: Complies with the GMII interface specification in the 802.3 standard clause 35 |
-- Automatic detection of the rx speed. |
-- For Virtex-5 |
--------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
library UNISIM; |
use UNISIM.VComponents.all; |
|
entity GMII_MII_WRAPPER_V6 is |
Port ( |
--// CLK, RESET |
CLK: in std_logic; |
-- 125 MHz global reference clock (fixed, independent of the tx speed) |
IDELAYREFCLK200MHZ: in std_logic; |
-- 190-210 MHz clock required for implementing IO delay(s). |
SYNC_RESET: in std_logic; |
-- block the GMII/MII output signals to the PHY during the PHY reset. |
-- minimum width 50ns for Virtex 5 (IDELAYCTRL contraint) |
-- MANDATORY at power up. |
|
--// PHY GMII/MII Interface ---------------------------------------------------------------- |
-- Connect directly to FPGA pins |
TX_CLK: in std_logic; |
-- MII tx clock from PHY. Continuous clock. (10/100 Mbps only) |
-- 25 MHz (100 Mbps), or 2.5 MHz (10 Mbps) depending on speed |
-- accuracy: +/- 100ppm (MII) |
-- duty cycle between 35% and 65% inclusive (MII). |
GTX_CLK: out std_logic; |
-- GMII tx clock to PHY. Continuous clock. 125MHz (1000 Mbps only) |
-- 2ns delay inside (user adjustable). |
TXD: out std_logic_vector(7 downto 0); |
-- tx data (when TX_EN = '1' and TX_ER = '0') or special codes otherwise (carrier extend, |
-- carrier extend error, transmit error propagation). See 802.3 table 35-1 for definitions. |
TX_EN: out std_logic; |
-- |
TX_ER: out std_logic; |
-- to deliberately corrupt the contents of the frame (so as to be detected as such by the receiver) |
|
RX_CLK: in std_logic; |
-- continuous receive reference clock recovered by the PHY from the received signal |
-- 125/25/2.5 MHz +/- 50 ppm. |
-- Duty cycle better than 35%/65% (MII) |
-- 125 MHz must be delayed by 1.5 to 2.1 ns to prevent glitches (TBC. true for RGMII, but for GMII TOO???) |
|
RXD: in std_logic_vector(7 downto 0); |
-- rx data. 8-bit when 1000 Mbps. 4-bit nibble (3:0) when 10/100 Mbps. |
RX_DV: in std_logic; |
RX_ER: in std_logic; |
CRS: in std_logic; |
-- carrier sense |
COL: in std_logic; |
-- collision detection |
|
--// MAC Interface ---------------------------------------------------------------- |
MAC_RX_CLK: out std_logic; |
-- received clock (already a global clock, no need for any additional BUFG) |
-- 125 MHz (1000 Mbps), 25 MHz (100 Mbps) or 2.5 MHz (10 Mbps) |
-- receive signals are synchronous with the MAC_RX_CLK clock recovered by the PHY |
MAC_RXD: out std_logic_vector(7 downto 0); |
-- 8-bits of rx data |
MAC_RX_DV: out std_logic; |
MAC_RX_ER: out std_logic; |
MAC_RX_SAMPLE_CLK: out std_logic; |
-- read the above MAC_RX? signals at the rising edge of MAC_RX_CLK when MAC_RX_SAMPLE_CLK = '1'. |
-- Always '1' when the transmit speed is set at 1000 Mbps |
-- 1-CLK pulse once every (exactly) 2 CLKs when the transmit speed is set at 10 or 100 Mbps |
|
-- transmit signals are synchronous with the rising edge of the 125 MHz CLK |
MAC_TXD: in std_logic_vector(7 downto 0); |
-- 8-bits of tx data |
-- tx data (when MAC_TX_EN = '1' and MAC_TX_ER = '0') or special codes otherwise (carrier extend, |
-- carrier extend error, transmit error propagation). See 802.3 table 35-1 for definitions. |
MAC_TX_EN: in std_logic; |
-- The MAC is responsible for holding the tx enable low until it has verified that it |
-- operates at the same speed as the PHY (as reported in the SPEED_STATUS) |
MAC_TX_ER: in std_logic; |
-- use (MAC_TX_EN, MAC_TX_ER) as follows: |
-- 0,0 = transmit complete |
-- 0,1 and MAC_TXD = 0x0F = carrier extend |
-- 0,1 and MAC_TXD = 0x1F = carrier extend error |
-- 1,0 = normal transmission |
-- 1,1 = transmit error |
MAC_TX_SAMPLE_CLK: in std_logic; |
-- read the above MAC_TX? signals at the rising edge of CLK when MAC_TX_SAMPLE_CLK = '1'. |
-- MAC_TX_SAMPLE_CLK conveys the transmit speed information. |
-- Always '1' when the transmit speed is set at 1000 Mbps |
-- 1-CLK pulse once every (exactly) 10 CLKs when the transmit speed is set at 100 Mbps |
-- 1-CLK pulse once every (exactly) 100 CLKs when the transmit speed is set at 10 Mbps |
|
-- MAC monitoring and control |
MAC_TX_SPEED: in std_logic_vector(1 downto 0); |
-- 00/01/10 for 10/100/1000 Mbps transmit speed (not really a control, but this component |
-- needs to know what speed it should run at). |
MAC_CRS: out std_logic; |
-- carrier sense. Directly from PHY over MII. |
MAC_COL: out std_logic; |
-- collision detection. Directly from PHY over MII. |
|
--// PHY status |
-- optional in-band status (must be enabled at PHY) |
LINK_STATUS: out std_logic ; -- 0 = link down, 1 = link up |
SPEED_STATUS: out std_logic_vector(1 downto 0); |
-- Detected RX_CLK clock speed, 00 = 2.5 MHz, 01 = 25 MHz, 10 = 125 MHz, 11 = reserved |
DUPLEX_STATUS: out std_logic |
-- 0 = half duplex, 1 = full duplex |
|
); |
end entity; |
|
architecture Behavioral of GMII_MII_WRAPPER_V6 is |
-------------------------------------------------------- |
-- COMPONENTS |
-------------------------------------------------------- |
-------------------------------------------------------- |
-- SIGNALS |
-------------------------------------------------------- |
constant RXC_DELAY: integer range 0 to 31 := 20; -- adjust as needed. Here: 2ns |
constant TXC_DELAY: integer range 0 to 31 := 20; -- adjust as needed. Here: 2ns |
-- |
--signal RGMII_EN: std_logic; |
signal RX_CLK_IN: std_logic; |
signal RX_CLK_IN2: std_logic; |
signal RX_CLK_DELAYED: std_logic := '0'; |
signal RX_CLKG: std_logic := '0'; -- global clock, delayed 2ns w.r.t. received RXC. |
signal RX_CLKGA: std_logic := '0'; |
signal RX_DV_D: std_logic; |
signal RX_DV_D2: std_logic; |
signal RX_ER_D: std_logic; |
signal RXD_NIBBLE_TOGGLE: std_logic := '0'; |
signal RXD_D: std_logic_vector(7 downto 0); |
signal RX_SPEED: std_logic_vector(1 downto 0) := "10"; |
signal RX_CLK_COUNTER1: std_logic_vector(2 downto 0) := "000"; |
signal RX_CLK_COUNTER1_MSB_D: std_logic; |
signal RX_CLK_COUNTER1_MSB_D2: std_logic; |
signal RX_CLK_COUNTER2: std_logic_vector(9 downto 0) := "0000000000"; |
signal MAC_RX_ER_LOCAL: std_logic := '0'; |
signal rxd_delay : std_logic_vector(7 downto 0) := "00000000"; |
signal rx_er_delay : std_logic; |
signal rx_dv_delay : std_logic; |
signal TXC_COUNTER: std_logic_vector(5 downto 0) := "000010"; |
signal TX_CLK_D: std_logic; |
signal TX_CLK_D2: std_logic; |
signal TXC0: std_logic; |
signal MAC_TXD_D: std_logic_vector(7 downto 0); |
signal MAC_TX_EN_D: std_logic; |
signal MAC_TX_ER_D: std_logic; |
signal TXD_NIBBLE_TOGGLE: std_logic; |
|
-------------------------------------------------------- |
-- IMPLEMENTATION |
-------------------------------------------------------- |
begin |
|
--RGMII_EN <= not SYNC_RESET; |
-- -- disable the RGMII outputs while the PHY is being reset. |
-- |
--------------------------------------------- |
-- RECEIVE SECTION |
--------------------------------------------- |
-- force IBUF selection (otherwise tools may select the wrong primitive) |
--IBUF_001: IBUF port map( I => RX_CLK, O => RX_CLK_IN); |
|
---- delay the RX_CLK clock by 2ns so that the clock is always slightly AFTER the signal transition. |
-- IDELAYCTRL_inst : IDELAYCTRL |
-- port map ( |
-- RDY => open, -- 1-bit output indicates validity of the REFCLK |
-- REFCLK => IDELAYREFCLK200MHZ, -- 1-bit reference clock input 190-210 MHz |
-- RST => SYNC_RESET -- 1-bit reset input. Minimum width 50ns |
-- ); |
|
-- IDELAYE2_inst : IDELAYE2 |
-- generic map ( |
-- CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE) |
-- DELAY_SRC => "IDATAIN", -- Delay input (IDATAIN, DATAIN) |
-- HIGH_PERFORMANCE_MODE => "TRUE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE") |
-- IDELAY_TYPE => "FIXED", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE |
-- IDELAY_VALUE => 0, -- Input delay tap setting (0-31) |
-- PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE |
-- REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0). |
-- SIGNAL_PATTERN => "CLOCK" -- DATA, CLOCK input signal |
-- ) |
-- port map ( |
-- CNTVALUEOUT => open, -- 5-bit output: Counter value output |
-- DATAOUT => RX_CLK_DELAYED, -- 1-bit output: Delayed data output |
-- C => '0', -- 1-bit input: Clock input |
-- CE => '0', -- 1-bit input: Active high enable increment/decrement input |
-- CINVCTRL => '0', -- 1-bit input: Dynamic clock inversion input |
-- CNTVALUEIN => (OTHERS => '0'), -- 5-bit input: Counter value input |
-- DATAIN => '0', -- 1-bit input: Internal delay data input |
-- IDATAIN => RX_CLK_IN, -- 1-bit input: Data input from the I/O |
-- INC => '0', -- 1-bit input: Increment / Decrement tap delay input |
-- LD => '0', -- 1-bit input: Load IDELAY_VALUE input |
-- LDPIPEEN => '0', -- 1-bit input: Enable PIPELINE register to load data input |
-- REGRST => SYNC_RESET -- 1-bit input: Active-high reset tap-delay input |
-- ); |
|
-- delay_gmii_rx_dv : IODELAYE1 |
-- generic map ( |
-- IDELAY_TYPE => "FIXED", |
-- DELAY_SRC => "I" |
-- ) |
-- port map ( |
-- IDATAIN => rx_dv, |
-- ODATAIN => '0', |
-- DATAOUT => rx_dv_delay, |
-- DATAIN => '0', |
-- C => '0', |
-- T => '1', |
-- CE => '0', |
-- CINVCTRL => '0', |
-- CLKIN => '0', |
-- CNTVALUEIN => "00000", |
-- CNTVALUEOUT => open, |
-- INC => '0', |
-- RST => '0' |
-- ); |
rx_dv_delay <= rx_dv; |
--delay_gmii_rx_er : IODELAYE1 |
-- generic map ( |
-- IDELAY_TYPE => "FIXED", |
-- DELAY_SRC => "I" |
-- ) |
-- port map ( |
-- IDATAIN => rx_er, |
-- ODATAIN => '0', |
-- DATAOUT => rx_er_delay, |
-- DATAIN => '0', |
-- C => '0', |
-- T => '1', |
-- CE => '0', |
-- CINVCTRL => '0', |
-- CLKIN => '0', |
-- CNTVALUEIN => "00000", |
-- CNTVALUEOUT => open, |
-- INC => '0', |
-- RST => '0' |
-- ); |
|
rx_er_delay <= rx_er; |
-- rxdata_bus: for I in 7 downto 0 generate |
-- delay_gmii_rxd : IODELAYE1 |
-- generic map ( |
-- IDELAY_TYPE => "FIXED", |
-- DELAY_SRC => "I" |
-- ) |
-- port map ( |
-- IDATAIN => rxd(I), |
-- ODATAIN => '0', |
-- DATAOUT => rxd_delay(I), |
-- DATAIN => '0', |
-- C => '0', |
-- T => '1', |
-- CE => '0', |
-- CINVCTRL => '0', |
-- CLKIN => '0', |
-- CNTVALUEIN => "00000", |
-- CNTVALUEOUT => open, |
-- INC => '0', |
-- RST => '0' |
-- ); |
-- end generate; |
|
--------------- |
rxd_delay <= rxd; |
--------------- |
--IBUFG_inst : IBUF |
-- generic map ( |
-- IOSTANDARD => "DEFAULT" |
-- ) |
-- port map ( |
-- O => RX_CLKGA, -- Clock buffer output |
-- I => RX_CLK -- Clock buffer input (connect directly to top-level port) |
-- ); |
RX_CLKGA <= RX_CLK; |
-- delay RX clock, but only in the case of 125 MHz |
--RX_CLK_IN2 <= RX_CLK_DELAYED;-- when (RX_SPEED = "10") else RX_CLK_IN; |
|
-- TODO.. It may be better to control IODELAY2 delay because the mux above delays the clock. |
|
---- declare the RX clock as a global clock |
--BUFG_001 : BUF port map ( |
-- O => , -- Clock buffer output |
-- I => RX_CLKGA -- Clock buffer input |
--); |
|
RX_CLKG <= RX_CLKGA; |
------------------- |
-- immediately reclock rx input signals |
--RECLOCK_RX_001: process(RX_CLKG, RXD, RX_DV, RX_ER) |
RECLOCK_RX_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
RXD_D <= rxd_delay; |
RX_DV_D <= rx_dv_delay; |
RX_ER_D <= rx_er_delay; |
end if; |
end process; |
|
-- re-assemble 8-bit rx data (from 4-bit nibbles at 10/100 Mbps) |
RX8B_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
RX_DV_D2 <= RX_DV_D; |
|
if(RX_SPEED(1) = '0') and (RX_DV_D = '1') and (RX_DV_D2 = '0') then |
-- 10/100 Mbps. Start of new packet. Reset toggle |
RXD_NIBBLE_TOGGLE <= '1'; |
else |
RXD_NIBBLE_TOGGLE <= not RXD_NIBBLE_TOGGLE; |
end if; |
end if; |
end process; |
|
MAX_RX_OUT_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
MAC_CRS <= CRS; |
MAC_COL <= COL; |
|
if(RX_SPEED = "10") then |
-- 1000 Mbps |
MAC_RXD <= RXD_D; |
MAC_RX_DV <= RX_DV_D; |
MAC_RX_ER_LOCAL <= RX_ER_D; |
MAC_RX_SAMPLE_CLK <= '1'; |
LINK_STATUS <= '1'; |
elsif(RX_SPEED(1) = '0') and (RX_DV_D = '1') and (RX_DV_D2 = '0') then |
-- start of new packet. Reset toggle |
MAC_RXD(3 downto 0) <= RXD_D(3 downto 0); |
MAC_RX_DV <= RX_DV_D; |
MAC_RX_ER_LOCAL <= RX_ER_D; |
MAC_RX_SAMPLE_CLK <= '0'; -- waiting for the other half |
LINK_STATUS <= '1'; |
elsif(RX_SPEED(1) = '0') and (RXD_NIBBLE_TOGGLE = '0') then |
-- 1st nibble (1/2) |
MAC_RXD(3 downto 0) <= RXD_D(3 downto 0); |
MAC_RX_DV <= RX_DV_D; |
MAC_RX_ER_LOCAL <= RX_ER_D; |
MAC_RX_SAMPLE_CLK <= '0'; -- waiting for the other half |
LINK_STATUS <= '1'; |
elsif(RX_SPEED(1) = '0') and (RXD_NIBBLE_TOGGLE = '1') then |
-- 2nd nibble (2/2) |
MAC_RXD(7 downto 4) <= RXD_D(3 downto 0); |
MAC_RX_SAMPLE_CLK <= '1'; -- got a complete byte |
MAC_RX_ER_LOCAL <= MAC_RX_ER_LOCAL or RX_ER_D; -- RX_ER can be as short as one RX_CLKG. |
LINK_STATUS <= '1'; |
else |
MAC_RX_SAMPLE_CLK <= '0'; |
LINK_STATUS <= '0'; |
end if; |
end if; |
end process; |
|
-- outputs to MAC |
MAC_RX_CLK <= RX_CLKG; |
MAC_RX_ER <= MAC_RX_ER_LOCAL; |
|
--// RX_SPEED AUTODETECT ------------------------------------------ |
-- Automatically detect rx speed based on the RX_CLK. |
-- Algorithm: two counters, one based the variable frequency clock (RX_CLKG), the other |
-- based on the 125 MHz master clock. |
|
-- Modulo-8 counter. |
RX_CLK_COUNTER1_GEN: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
RX_CLK_COUNTER1 <= RX_CLK_COUNTER1 + 1; |
end if; |
end process; |
|
RX_CLK_COUNTER2_GEN: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
RX_CLK_COUNTER1_MSB_D <= RX_CLK_COUNTER1(2); -- reclock to make RX_CLK_COUNTER1 MSb synchronous with CLK |
RX_CLK_COUNTER1_MSB_D2 <= RX_CLK_COUNTER1_MSB_D; |
|
if(RX_CLK_COUNTER1_MSB_D2 = '0') and (RX_CLK_COUNTER1_MSB_D = '1') then |
-- reset RX_CLK_COUNTER2 every 8 RX_CLK_COUNTER1. |
RX_CLK_COUNTER2 <= (others => '0'); |
if(RX_CLK_COUNTER2(9 downto 4) = 0) then -- <16 |
RX_SPEED <= "10"; -- 1000 Mbps |
elsif(RX_CLK_COUNTER2(9 downto 6) = 0) then -- < 64 |
RX_SPEED <= "01"; -- 100 Mbps |
else |
RX_SPEED <= "00"; -- 10 Mbps |
end if; |
else |
RX_CLK_COUNTER2 <= RX_CLK_COUNTER2 + 1; |
end if; |
|
end if; |
end process; |
|
-- report rx speed to MAC |
SPEED_STATUS <= RX_SPEED; |
|
--------------------------------------------- |
-- TRANSMIT SECTION |
--------------------------------------------- |
-- Reclock TX signals so that they are stable during the entire period (we don't |
-- want any transition within a TXC clock period) |
RECLOCK_005: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(SYNC_RESET = '1') then |
MAC_TXD_D <= (others => '0'); |
MAC_TX_EN_D <= '0'; |
MAC_TX_ER_D <= '0'; |
TXD_NIBBLE_TOGGLE <= '0'; |
elsif (MAC_TX_SAMPLE_CLK = '1') then |
MAC_TXD_D <= MAC_TXD; |
MAC_TX_EN_D <= MAC_TX_EN; |
MAC_TX_ER_D <= MAC_TX_ER; |
TXD_NIBBLE_TOGGLE <= '0'; -- point to lower nibble (3:0) first |
elsif(MAC_TX_SPEED(1) = '0') and (TXC0 = '1')then -- 10/100 Mbps |
-- read another nibble. toggle upper/lower nibble pointer |
TXD_NIBBLE_TOGGLE <= not TXD_NIBBLE_TOGGLE; |
end if; |
end if; |
end process; |
|
-- two cases: @1000 Mbps, the GTX_CLK is an output. At other speeds, the TX_CLK in an input. |
|
-- Case 10/100 Mbps. Convert the TX_CLK input clock from the PHY into CLK-synchronous 8ns pulses. |
-- Poor-man's DLL to ensure that the clocks are spaced exactly 5 or 50 CLKs apart. |
TX_CLK_GEN_001: process(RX_CLKG, TX_CLK) |
begin |
if rising_edge(RX_CLKG) then |
TX_CLK_D <= TX_CLK; |
TX_CLK_D2 <= TX_CLK_D; |
|
-- TXC_COUNTER represents the phase of the clock replica. |
if(SYNC_RESET = '1') or (MAC_TX_SPEED(1) = '1') then |
TXC_COUNTER <= (others => '0'); |
elsif(MAC_TX_SPEED = "00") and (TXC_COUNTER = 0) then |
-- 10 Mbps: modulo-50 periodic counter |
TXC_COUNTER <= "110001"; -- 49 |
elsif(MAC_TX_SPEED = "01") and (TXC_COUNTER = 0) then |
-- 100 Mbps: modulo-5 periodic counter |
TXC_COUNTER <= "000100"; -- 4 |
elsif (TXC_COUNTER > 2) and (TX_CLK_D2 = '0') and (TX_CLK_D = '1') then |
-- re-adjust phase of clock replica (once at start-up) when phase error is too large |
-- 3 CLK margin. |
TXC_COUNTER <= "000001"; |
elsif(TXC_COUNTER > 0) then |
TXC_COUNTER <= TXC_COUNTER - 1; |
end if; |
|
if(TXC_COUNTER = 2) then |
TXC0 <= '1'; |
else |
TXC0 <= '0'; |
end if; |
|
end if; |
end process; |
|
|
TXD_OUTPUT_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(SYNC_RESET = '1') then |
-- disable all outputs while the component is being reset. |
TXD <= (others => '0'); |
TX_EN <= '0'; |
TX_ER <= '0'; |
elsif(MAC_TX_SPEED(1) = '0') and (TXC0 = '1')then -- 10/100 Mbps |
if(TXD_NIBBLE_TOGGLE = '0') then |
-- lower nibble (3:0) |
TXD <= MAC_TXD_D(3 downto 0) & MAC_TXD_D(3 downto 0); -- data |
else |
TXD <= MAC_TXD_D(7 downto 4) & MAC_TXD_D(7 downto 4); -- data |
end if; |
TX_EN <= MAC_TX_EN_D; |
TX_ER <= MAC_TX_ER_D; |
elsif(MAC_TX_SPEED = "10") then -- 1000 Mbps |
TXD <= MAC_TXD_D; -- data |
TX_EN <= MAC_TX_EN_D; |
TX_ER <= MAC_TX_ER_D; |
end if; |
end if; |
end process; |
|
|
-- delay the TX clock by 2ns so that the clock is always slightly AFTER the signal transition. |
-- Xilinx Virtex-5 IODELAY: Input and Output Fixed or Variable Delay Element |
-- IODELAY_001 : IODELAYE2 |
-- generic map ( |
-- CINVCTRL_SEL => FALSE, |
-- DELAY_SRC => "O", -- Specify which input port to be used |
---- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional |
-- HIGH_PERFORMANCE_MODE => TRUE, -- TRUE specifies lower jitter |
---- at expense of more power |
-- IDELAY_TYPE => "FIXED", -- "FIXED" or "VARIABLE" |
-- IDELAY_VALUE => 0, -- 0 to 63 tap values |
-- ODELAY_TYPE => "FIXED", |
-- ODELAY_VALUE => TXC_DELAY, -- 0 to 63 tap values |
-- REFCLK_FREQUENCY => 200.0, -- Frequency used for IDELAYCTRL |
---- 175.0 to 225.0 |
-- SIGNAL_PATTERN => "CLOCK") -- Input signal type, "CLOCK" or "DATA" |
-- port map ( |
-- CNTVALUEOUT => OPEN, |
-- DATAOUT => GTX_CLK, -- 1-bit delayed data output |
-- C => '0', -- 1-bit clock input |
-- CE => '0', -- 1-bit clock enable input |
-- CINVCTRL => '0', |
-- CLKIN => 'Z', |
-- CNTVALUEIN => (OTHERS => '0'), |
-- DATAIN => '0', -- 1-bit internal data input |
-- IDATAIN => '0', -- 1-bit input data input (connect to port) |
-- INC => '0', -- 1-bit increment/decrement input |
-- ODATAIN => CLK, -- 1-bit output data input |
-- RST => '0', -- 1-bit active high, synch reset input |
-- T => '0' -- 1-bit 3-state control input |
-- ); |
GTX_CLK <= RX_CLKG; |
end Behavioral; |
|
/gigabit_udp_mac/trunk/MAC/LFSR11C.VHD
0,0 → 1,95
---------------------------------------------- |
-- MSS copyright 2001-2005 |
-- Filename: LFSR11C.VHD |
-- Inheritance: LFSR11.VHD rev 4 and LFSR11B.VHD rev 4 |
-- Edit date: 9/28/05 |
-- Revision: 1 |
-- Description: |
-- pseudo random bit generation. based on 11-bit linear feedback |
-- shift register. A synchronous reset is provided to reset |
-- the PN sequence at frame boundaries. |
-- Includes seed initialization. |
--------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity LFSR11C is |
port ( |
ASYNC_RESET: in std_logic; |
-- asynchronous reset, active high |
CLK: in std_logic; |
-- clock synchronous |
BIT_CLK_REQ: in std_logic; |
-- request for output bit, |
-- read output bit at rising_edge of CLK and BIT_CLK_REQ_D = '1' |
SYNC_RESET: in std_logic; |
-- synchronous reset for linear feedback shift register. |
-- 1 CLK wide pulse aligned with BIT_CLK_REQ. |
SEED: in std_logic_vector(10 downto 0); |
-- linear feedback shift register initialization at reset |
-- (asynchronous and synchronous). |
|
LFSR_BIT: out std_logic; |
-- Linear feedback shift register output. Read at rising edge of CLK |
-- when BIT_CLK_OUT = '1' |
BIT_CLK_OUT: out std_logic; |
-- one CLK wide pulse indicating that the LFSR_BIT is ready. |
-- Latency w.r.t. BIT_CLK_REQ is one CLK. |
SOF_OUT: out std_logic; |
-- one CLK wide pulse indicating start of frame |
-- (i.e. '1' when LFSR register matches the SEED). |
-- aligned with BIT_CLK_OUT. |
LFSR_REG_OUT: out std_logic_vector(10 downto 0) |
|
); |
end entity; |
|
architecture behavior of LFSR11C is |
----------------------------------------------------------------- |
-- SIGNALS |
----------------------------------------------------------------- |
signal LFSR_REG : std_logic_vector(10 downto 0); |
|
----------------------------------------------------------------- |
-- IMPLEMENTATION |
----------------------------------------------------------------- |
begin |
|
-- linear feedback shift register |
LSFR_GEN: process(ASYNC_RESET, CLK, SEED) |
begin |
if (ASYNC_RESET = '1') then |
LFSR_REG <= SEED; |
LFSR_BIT <= '0'; |
SOF_OUT <= '0'; |
elsif rising_edge(CLK) then |
BIT_CLK_OUT <= BIT_CLK_REQ; |
|
if(SYNC_RESET = '1') then |
-- synchronous reset |
LFSR_REG <= SEED; |
LFSR_BIT <= '0'; |
SOF_OUT <= '0'; |
elsif(BIT_CLK_REQ = '1') then |
-- prepare next bit; used Xilinx XAP 052 Table 3 for taps |
LFSR_REG(10 downto 1) <= LFSR_REG(9 downto 0); |
LFSR_REG(0) <= not (LFSR_REG(10) xor LFSR_REG(8)); |
LFSR_BIT <= LFSR_REG(10); |
if(LFSR_REG = SEED) then |
SOF_OUT <= '1'; |
else |
SOF_OUT <= '0'; |
end if; |
else |
-- sample clocks are one CLK wide pulses. |
SOF_OUT <= '0'; |
end if; |
end if; |
end process; |
|
LFSR_REG_OUT <= LFSR_REG; |
|
end behavior; |
|
/gigabit_udp_mac/trunk/MAC/MAC_Controller.vhd
0,0 → 1,1792
------------------------------------------------------------- |
-- Filename: MAC_Controller.VHD |
-- Version: 5 |
-- Date last modified: 9/16/11 |
-- Inheritance: COM5401.VHD, rev5, 9/16/11 |
-- |
-- description: 10/100/1000 MAC |
-- Features include |
-- (a) Automatic appending of 32-bit CRC to tx packets. Users don't have to. |
-- (b) discarding of rx packets with bad CRC. |
-- |
-- Usage: the following KSZ9021RN strapping options MUST be set in the .ucf file |
-- pin35 RX_CLK/PHYAD2 pull-down LEFT_CONNECTOR_A(1),A(19),B(1),B(21) |
-- pins32,31,28,27 RXDx/MODEx pull-up, advertise all modes |
-- LEFT_CONNECTOR_A(2,4,5,6,21,22,23,24),B(3,4,6,7,23,24,25,26) |
-- pin33 RX_DV(RX_CTL)/CLK125_EN |
-- pull-down on all ICs. No need for an external 125 MHz clock (not very clean). |
-- LEFT_CONNECTOR_A(2) pullup, LEFT_CONNECTOR_A(20),B(2),B(22) pull-down |
-- pin41 CLK125_NDO/LED_MODE pulldown dual leds, tri-color. |
-- LEFT_CONNECTOR_A(13,31),_B(14,34) |
-- |
-- The transmit elastic buffer is large enough for 2 maximum size frame. The tx Clear To Send (MAC_TX_CTS) |
-- signal is raised when the the MAC is ready to accept one complete frame without interruption. |
-- In this case, MAC_TX_CTS may go low while the frame transfer has started, but there is guaranteed |
-- space for the entire frame. |
-- |
--------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
library UNISIM; |
use UNISIM.VComponents.all; |
|
entity MAC_Controller is |
generic ( |
PHY_ADDR: std_logic_vector(4 downto 0) := "00001"; |
-- PHY_AD0/1 pulled-down by 1KOhm, PHY_AD2 pulled-up in .ucf file. |
CLK_FREQUENCY: integer := 125 |
-- CLK frequency in MHz. Needed to compute actual delays. |
); |
Port ( |
--// CLK, RESET |
CLK: in std_logic; |
-- USER-side GLOBAL CLOCK |
IDELAYREFCLK200MHZ: in std_logic; |
-- 190-210 MHz clock required for implementing IO delay(s). |
ASYNC_RESET: in std_logic; |
-- reset pulse must be > slowest clock period (>400ns) |
-- minimum width 50ns for Virtex 5 (IDELAYCTRL contraint) |
-- MANDATORY at power up. |
|
--// MAC CONFIGURATION |
-- configuration signals are synchonous with the user-side CLK |
MAC_TX_CONFIG: in std_logic_vector(15 downto 0); |
-- bit 0: (1) Automatic padding of short frames. Requires that auto-CRC insertion be enabled too. |
-- (0) Skip padding. User is responsible for adding padding to meet the minimum 60 byte frame size |
-- bit 1: (1) Automatic appending of 32-bit CRC at the end of the frame |
-- (0) Skip CRC32 insertion. User is responsible for including the frame check sequence |
-- Note: use 0x03 when interfacing with COM-5402 IP/UDP/TCP stack. |
MAC_RX_CONFIG: in std_logic_vector(15 downto 0); |
-- bit 0: (1) promiscuous mode enabled (0) disabled, i.e. destination address is verified for each incoming packet |
-- bit 1: (1) accept broadcast rx packets (0) reject |
-- bit 2: (1) accept multi-cast rx packets (0) reject |
-- bit 3: (1) filter out the 4-byte CRC field (0) pass along the CRC field. |
-- Note2: use 0x0F when interfacing with COM-5402 IP/UDP/TCP stack. |
MAC_ADDR: in std_logic_vector(47 downto 0); |
-- This network node 48-bit MAC address. The receiver checks incoming packets for a match between |
-- the destination address field and this MAC address. |
|
-- Natural bit order: enter x0123456789ab for the MAC address 01:23:45:67:89:ab |
|
--// PHY CONFIGURATION |
-- configuration signals are synchonous with the user-side CLK. |
PHY_CONFIG_CHANGE: in std_logic; |
-- optional pulse to activate any configuration change below. |
-- Not needed if the default values are acceptable. |
-- Ignored if sent during the initial PHY reset (10ms after power up) |
PHY_RESET: in std_logic; |
-- 1 = PHY software reset (default), 0 = no reset |
SPEED: in std_logic_vector(1 downto 0); |
-- 00 = force 10 Mbps |
-- 01 = force 100 Mbps |
-- 10 = force 1000 Mbps |
-- 11 = auto-negotiation (default) |
DUPLEX: in std_logic; |
-- 1 = full-duplex (default), 0 = half-duplex |
TEST_MODE: in std_logic_vector(1 downto 0); |
-- 00 = normal mode (default) |
-- 01 = loopback mode (at the phy) |
-- 10 = remote loopback |
-- 11 = led test mode |
POWER_DOWN: in std_logic; |
-- software power down mode. 1 = enabled, 0 = disabled (default). |
|
--// USER -> Transmit MAC Interface |
-- 32-bit CRC is automatically appended. User should not supply it. |
-- Synchonous with the user-side CLK |
MAC_TX_DATA: in std_logic_vector(7 downto 0); |
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1' |
MAC_TX_DATA_VALID: in std_logic; |
-- data valid |
MAC_TX_EOF: in std_logic; |
-- '1' when sending the last byte in a packet to be transmitted. |
-- Aligned with MAC_TX_DATA_VALID |
MAC_TX_CTS: out std_logic; |
-- MAC-generated Clear To Send flow control signal, indicating room in the |
-- tx elastic buffer for a complete maximum size frame 1518B. |
-- The user should check that this signal is high before deciding to send |
-- sending the next frame. |
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it. |
|
--// Receive MAC -> USER Interface |
-- Valid rx packets only: packets with bad CRC or invalid address are discarded. |
-- Synchonous with the user-side CLK |
-- The short-frame padding is included . |
MAC_RX_DATA: out std_logic_vector(7 downto 0); |
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1' |
MAC_RX_DATA_VALID: out std_logic; |
-- data valid |
MAC_RX_SOF: out std_logic; |
-- '1' when sending the first byte in a received packet. |
-- Aligned with MAC_RX_DATA_VALID |
MAC_RX_EOF: out std_logic; |
-- '1' when sending the last byte in a received packet. |
-- Aligned with MAC_RX_DATA_VALID |
MAC_RX_CTS: in std_logic; |
-- User-generated Clear To Send flow control signal. The receive MAC checks that this |
-- signal is high before sending the next MAC_RX_DATA byte. |
|
|
|
--// RGMII PHY Interface (when RGMII is enabled. See MII_SEL generic flag above) |
RESET_N: out std_logic; |
-- PHY reset |
MCLK: out std_logic; |
MDIO: inout std_logic:='0'; -- (tri-state) |
-- serial interface |
|
--// GMII/MII PHY Interface (when GMII/MII is enabled. See MII_SEL generic flag above) |
MII_TX_CLK: in std_logic:='0'; |
-- MII tx clock from PHY. Continuous clock. (10/100 Mbps only) |
-- 25 MHz (100 Mbps), or 2.5 MHz (10 Mbps) depending on speed |
-- accuracy: +/- 100ppm (MII) |
-- duty cycle between 35% and 65% inclusive (MII). |
GMII_TX_CLK: out std_logic; |
-- GMII tx clock to PHY. Continuous clock. 125MHz (1000 Mbps only) |
-- 2ns delay inside (user adjustable). |
GMII_MII_TXD: out std_logic_vector(7 downto 0); -- tx data |
-- tx data (when TX_EN = '1' and TX_ER = '0') or special codes otherwise (carrier extend, |
-- carrier extend error, transmit error propagation). See 802.3 table 35-1 for definitions. |
GMII_MII_TX_EN: out std_logic; |
GMII_MII_TX_ER: out std_logic; |
-- to deliberately corrupt the contents of the frame (so as to be detected as such by the receiver) |
GMII_MII_CRS: in std_logic:='0'; |
GMII_MII_COL: in std_logic:='0'; |
|
GMII_MII_RX_CLK: in std_logic; |
-- continuous receive reference clock recovered by the PHY from the received signal |
-- 125/25/2.5 MHz +/- 50 ppm. |
-- Duty cycle better than 35%/65% (MII) |
-- 125 MHz must be delayed by 1.5 to 2.1 ns to prevent glitches (TBC. true for RGMII, but for GMII TOO???) |
|
GMII_MII_RXD: in std_logic_vector(7 downto 0); |
-- rx data. 8-bit when 1000 Mbps. 4-bit nibble (3:0) when 10/100 Mbps. |
GMII_MII_RX_DV: in std_logic; |
GMII_MII_RX_ER: in std_logic; |
|
|
--// PHY status |
-- The link, speed and duplex status are read from the RXD when RX_CTL is inactive |
-- synchronous with RXCG global clock |
LINK_STATUS: out std_logic; |
-- 0 = link down, 1 = link up |
SPEED_STATUS: out std_logic_vector(1 downto 0); |
-- RXC clock speed, 00 = 2.5 MHz, 01 = 25 MHz, 10 = 125 MHz, 11 = reserved |
DUPLEX_STATUS: out std_logic; |
-- 0 = half duplex, 1 = full duplex |
PHY_ID: out std_logic_vector(15 downto 0) |
|
); |
end entity; |
|
architecture Behavioral of MAC_Controller is |
-------------------------------------------------------- |
-- COMPONENTS |
-------------------------------------------------------- |
COMPONENT RESET_TIMER |
GENERIC ( |
CLK_FREQUENCY: in integer |
); |
PORT( |
CLK : IN std_logic; |
RESET_START : IN std_logic; |
RESET_COMPLETE : OUT std_logic; |
INITIAL_CONFIG_PULSE : OUT std_logic; |
RESET_N : OUT std_logic |
); |
END COMPONENT; |
|
COMPONENT PHY_CONFIG |
GENERIC ( |
PHY_ADDR: std_logic_vector(4 downto 0) |
); |
PORT( |
SYNC_RESET : IN std_logic; |
CLK : IN std_logic; |
CONFIG_CHANGE : IN std_logic; |
PHY_RESET : IN std_logic; |
SPEED : IN std_logic_vector(1 downto 0); |
DUPLEX : IN std_logic; |
TEST_MODE : IN std_logic_vector(1 downto 0); |
POWER_DOWN : IN std_logic; |
CLK_SKEW: in std_logic_vector(15 downto 0); |
SREG_READ_START : IN std_logic; |
SREG_REGAD : IN std_logic_vector(8 downto 0); |
LINK_STATUS: out std_logic; |
MDI: in std_logic; -- MDIO input |
MDO: out std_logic; -- MDIO output |
MDT: out std_logic; -- MDIO tri-state |
SREG_DATA : OUT std_logic_vector(15 downto 0); |
SREG_SAMPLE_CLK : OUT std_logic; |
MCLK : OUT std_logic |
); |
END COMPONENT; |
|
COMPONENT RGMII_WRAPPER_V6 |
GENERIC ( |
CLK_FREQUENCY: in integer |
); |
PORT( |
SYNC_RESET : IN std_logic; |
CLK : IN std_logic; |
IDELAYREFCLK200MHZ: in std_logic; |
RXC : IN std_logic; |
RXD : IN std_logic_vector(3 downto 0); |
RX_CTL : IN std_logic; |
MAC_TXD : IN std_logic_vector(7 downto 0); |
MAC_TX_EN : IN std_logic; |
MAC_TX_ER : IN std_logic; |
MAC_TX_SAMPLE_CLK : IN std_logic; |
TX_SPEED : IN std_logic_vector(1 downto 0); |
TXC : OUT std_logic; |
TXD : OUT std_logic_vector(3 downto 0); |
TX_CTL : OUT std_logic; |
MAC_RXD : OUT std_logic_vector(7 downto 0); |
MAC_RX_SAMPLE_CLK: OUT std_logic; |
MAC_RX_DV : OUT std_logic; |
MAC_RX_ER : OUT std_logic; |
RXCG_OUT : OUT std_logic; |
CRS : OUT std_logic; |
COL : OUT std_logic; |
LINK_STATUS : OUT std_logic; |
SPEED_STATUS : OUT std_logic_vector(1 downto 0); |
DUPLEX_STATUS : OUT std_logic; |
TP: out std_logic_vector(10 downto 1) |
); |
END COMPONENT; |
|
COMPONENT GMII_MII_WRAPPER_V6 |
PORT( |
SYNC_RESET : IN std_logic; |
CLK : IN std_logic; |
IDELAYREFCLK200MHZ: in std_logic; |
TX_CLK : IN std_logic; |
RX_CLK : IN std_logic; |
RXD : IN std_logic_vector(7 downto 0); |
RX_DV : IN std_logic; |
RX_ER : IN std_logic; |
CRS : IN std_logic; |
COL : IN std_logic; |
MAC_TXD : IN std_logic_vector(7 downto 0); |
MAC_TX_EN : IN std_logic; |
MAC_TX_ER : IN std_logic; |
MAC_TX_SAMPLE_CLK : IN std_logic; |
MAC_TX_SPEED : IN std_logic_vector(1 downto 0); |
GTX_CLK : OUT std_logic; |
TXD : OUT std_logic_vector(7 downto 0); |
TX_EN : OUT std_logic; |
TX_ER : OUT std_logic; |
MAC_RX_CLK : OUT std_logic; |
MAC_RXD : OUT std_logic_vector(7 downto 0); |
MAC_RX_DV : OUT std_logic; |
MAC_RX_ER : OUT std_logic; |
MAC_RX_SAMPLE_CLK : OUT std_logic; |
MAC_CRS : OUT std_logic; |
MAC_COL : OUT std_logic; |
LINK_STATUS : OUT std_logic; |
SPEED_STATUS : OUT std_logic_vector(1 downto 0); |
DUPLEX_STATUS : OUT std_logic |
); |
END COMPONENT; |
|
COMPONENT CRC32_8B |
PORT( |
SYNC_RESET : IN std_logic; |
CLK : IN std_logic; |
CRC32_IN : IN std_logic_vector(31 downto 0); |
DATA_IN : IN std_logic_vector(7 downto 0); |
SAMPLE_CLK_IN : IN std_logic; |
CRC32_OUT : OUT std_logic_vector(31 downto 0); |
CRC32_VALID : OUT std_logic |
); |
END COMPONENT; |
|
COMPONENT LFSR11C |
PORT( |
ASYNC_RESET : IN std_logic; |
CLK : IN std_logic; |
BIT_CLK_REQ : IN std_logic; |
SYNC_RESET : IN std_logic; |
SEED : IN std_logic_vector(10 downto 0); |
LFSR_BIT : OUT std_logic; |
BIT_CLK_OUT : OUT std_logic; |
SOF_OUT : OUT std_logic; |
LFSR_REG_OUT: OUT std_logic_vector(10 downto 0) |
); |
END COMPONENT; |
|
-------------------------------------------------------- |
-- SIGNALS |
-------------------------------------------------------- |
-- NOTATIONS: |
-- _E as one-CLK early sample |
-- _D as one-CLK delayed sample |
-- _D2 as two-CLKs delayed sample |
|
--// CLK & RESETS --------- |
signal RESETFLAG_D: std_logic := '0'; |
signal RESETFLAG_D2: std_logic := '0'; |
signal SYNC_RESET: std_logic := '0'; |
signal SYNC_RESETRX: std_logic := '0'; |
signal RESETRX_FLAG_D: std_logic := '0'; |
signal RESETRX_FLAG_D2: std_logic := '0'; |
|
|
--// PHY RESET AND CONFIGURATION ---------------------------------------------------------- |
signal RESET_N_LOCAL: std_logic := '0'; |
signal INITIAL_CONFIG_PULSE: std_logic := '1'; |
signal PHY_CONFIG_CHANGE_A: std_logic := '0'; |
signal PHY_RESET_A: std_logic := '0'; |
signal SPEED_A: std_logic_vector(1 downto 0); |
signal DUPLEX_A: std_logic := '0'; |
signal TEST_MODE_A: std_logic_vector(1 downto 0); |
signal POWER_DOWN_A: std_logic := '0'; |
signal CLK_SKEW_A: std_logic_vector(15 downto 0); |
signal MDI: std_logic := '0'; |
signal MDO: std_logic := '0'; |
signal MDT: std_logic := '0'; |
signal RESET_COMPLETE: std_logic := '0'; |
signal PHY_IF_WRAPPER_RESET: std_logic := '0'; |
signal SREG_READ_START: std_logic := '0'; |
signal SREG_SAMPLE_CLK: std_logic := '0'; |
signal PHY_ID_LOCAL: std_logic_vector(15 downto 0); |
signal LINK_STATUS_local: std_logic := '0'; |
signal DUPLEX_STATUS_local: std_logic := '0'; |
signal SPEED_STATUS_LOCAL: std_logic_vector(1 downto 0) := (others => '0'); |
signal TP_RGMII_WRAPPER: std_logic_vector(10 downto 1) := (others => '0'); |
|
--// PHY INTERFACE: GMII to RGMII CONVERSION ---------------------------------------------------------- |
signal CRS: std_logic := '0'; |
signal CRS_D: std_logic := '0'; |
signal COL: std_logic := '0'; |
signal MAC_TXD: std_logic_vector(7 downto 0) := (others => '0'); |
signal MAC_TX_EN: std_logic := '0'; |
signal MAC_TX_ER: std_logic := '0'; |
signal MAC_TX_SAMPLE_CLK: std_logic := '0'; |
signal MAC_RXD0: std_logic_vector(7 downto 0); |
signal MAC_RX_DV0: std_logic := '0'; |
signal MAC_RX_ER0: std_logic := '0'; |
signal MAC_RX_SAMPLE_CLK0: std_logic := '0'; |
signal MAC_RXD: std_logic_vector(7 downto 0); |
signal MAC_RX_DV: std_logic := '0'; |
signal MAC_RX_ER: std_logic := '0'; |
signal MAC_RX_SAMPLE_CLK: std_logic := '0'; |
|
|
--// TX ELASTIC BUFFER ---------------------------------------------------------- |
signal MAC_TX_DIA: std_logic_vector(31 downto 0) := (others => '0'); |
signal MAC_TX_DIPA: std_logic_vector(0 downto 0) := (others => '0'); |
signal MAC_TX_WPTR: std_logic_vector(11 downto 0) := (others => '0'); |
signal MAC_TX_WPTR_D: std_logic_vector(11 downto 0) := (others => '0'); |
signal MAC_TX_WPTR_D2: std_logic_vector(11 downto 0) := (others => '0'); |
signal MAC_TX_WPTR_D3: std_logic_vector(11 downto 0) := (others => '0'); |
signal MAC_TX_WPTR_STABLE: std_logic := '0'; |
signal MAC_TX_WPTR_STABLE_D: std_logic := '0'; |
signal TX_COUNTER8: std_logic_vector(2 downto 0) :=(others => '0'); |
signal MAC_TX_WEA: std_logic_vector(1 downto 0) := (others => '0'); |
signal MAC_TX_BUF_SIZE: std_logic_vector(11 downto 0) := (others => '0'); |
signal MAC_TX_RPTR: std_logic_vector(11 downto 0) := (others => '1'); |
signal MAC_TX_RPTR_D: std_logic_vector(11 downto 0) := (others => '1'); |
signal MAC_TX_RPTR_CONFIRMED: std_logic_vector(11 downto 0) := (others => '1'); |
signal MAC_TX_RPTR_CONFIRMED_D: std_logic_vector(11 downto 0) := (others => '1'); |
signal MAC_TX_SAMPLE2_CLK_E: std_logic := '0'; |
signal MAC_TX_SAMPLE2_CLK: std_logic := '0'; |
type DOBtype is array(integer range 0 to 1) of std_logic_vector(7 downto 0); |
signal MAC_TX_DOB: DOBtype; |
type DOPBtype is array(integer range 0 to 1) of std_logic_vector(0 downto 0); |
signal MAC_TX_DOPB: DOPBtype; |
signal MAC_TX_DATA2: std_logic_vector(7 downto 0) := (others => '0'); |
signal MAC_TX_EOF2: std_logic := '0'; |
signal MAC_TX_EOF2_D: std_logic := '0'; |
signal COMPLETE_TX_FRAMES_INBUF: std_logic_vector(7 downto 0) := x"00"; -- can't have more than 147 frames in a 16k buffer |
signal ATLEAST1_COMPLETE_TX_FRAME_INBUF: std_logic := '0'; |
signal MAC_TX_EOF_TOGGLE: std_logic := '0'; |
signal MAC_TX_EOF_TOGGLE_D: std_logic := '0'; |
signal MAC_TX_EOF_TOGGLE_D2: std_logic := '0'; |
signal MAC_TX_CTS_local: std_logic := '0'; |
|
--//-- TX FLOW CONTROL -------------------------------- |
signal TX_SUCCESS_TOGGLE: std_logic := '0'; |
signal TX_SUCCESS_TOGGLE_D: std_logic := '0'; |
signal TX_SUCCESS_TOGGLE_D2: std_logic := '0'; |
signal MAC_TX_BUF_FREE: std_logic_vector(11 downto 0) := (others => '0'); |
|
|
--// MAC TX STATE MACHINE ---------------------------------------------------------- |
signal TX_SPEED: std_logic_vector(1 downto 0) := (others => '0'); |
signal TX_CLK: std_logic := '0'; |
signal TX_BYTE_CLK: std_logic := '0'; |
signal TX_BYTE_CLK_D: std_logic := '0'; |
signal TX_HALF_BYTE_FLAG: std_logic := '0'; |
signal IPG: std_logic := '0'; |
signal IPG_CNTR: std_logic_vector(7 downto 0) := (others => '0'); -- TODO CHECK CONSISTENCY WITH TIMER VALUES |
signal TX_EVENT1: std_logic := '0'; |
signal TX_EVENT2: std_logic := '0'; |
signal TX_EVENT3: std_logic := '0'; |
signal TX_STATE: integer range 0 to 15 := 0; |
signal TX_BYTE_COUNTER: std_logic_vector(18 downto 0) := (others => '0'); -- large enough for counting 2000 bytes in max size packet |
signal TX_BYTE_COUNTER2: std_logic_vector(2 downto 0) := (others => '0'); -- small auxillary byte counter for small fields |
signal TX_PREAMBLE: std_logic_vector(7 downto 0) := (others => '0'); |
signal MAC_TX_SAMPLE4_CLK: std_logic := '0'; |
signal MAC_TX_DATA4: std_logic_vector(7 downto 0) := (others => '0'); |
signal MAC_TX_DATA4_D: std_logic_vector(7 downto 4) := (others => '0'); |
signal RETX_ATTEMPT_COUNTER: std_logic_vector(4 downto 0) := (others => '0'); -- re-transmission attempts counter |
signal RAND: std_logic_vector(10 downto 0) := (others => '0'); |
signal RETX_RANDOM_BKOFF: std_logic_vector(9 downto 0) := (others => '0'); |
signal TX_SUCCESS: std_logic := '0'; |
signal TX_EN: std_logic := '0'; |
signal TX_ER: std_logic := '0'; |
|
--// TX 32-BIT CRC COMPUTATION ------------------------------------------------------- |
signal TX_CRC32: std_logic_vector(31 downto 0) := (others => '0'); |
signal TX_CRC32_FLIPPED_INV: std_logic_vector(31 downto 0) := (others => '0'); |
signal TX_CRC32_RESET: std_logic := '0'; |
signal TX_FCS: std_logic_vector(7 downto 0) := (others => '0'); |
signal MAC_TX_SAMPLE3_CLK: std_logic := '0'; |
signal MAC_TX_DATA3: std_logic_vector(7 downto 0) := (others => '0'); |
|
--// MAC RX STATE MACHINE ---------------------------------------------------------- |
signal RX_CLKG: std_logic := '0'; |
signal RX_STATE: integer range 0 to 15 := 0; |
signal RX_EVENT1: std_logic := '0'; |
--signal RX_EVENT2: std_logic := '0'; |
signal RX_EVENT3: std_logic := '0'; |
signal RX_EVENT4: std_logic := '0'; |
signal RX_EVENT5: std_logic := '0'; |
signal RX_BYTE_COUNTER: std_logic_vector(18 downto 0); -- large enough for counting 2000 bytes in max size packet |
signal RX_BYTE_COUNTER_INC: std_logic_vector(18 downto 0); -- large enough for counting 2000 bytes in max size packet |
signal RX_TOO_SHORT: std_logic := '0'; |
signal RX_TOO_LONG: std_logic := '0'; |
signal RX_VALID_ADDR: std_logic := '0'; |
signal RX_LENGTH_ERR: std_logic := '0'; |
signal LAST6B: std_logic_vector(47 downto 0) := (others => '0'); |
signal RX_LENGTH: std_logic_vector(10 downto 0) := (others => '0'); |
signal RX_LENGTH_TYPEN: std_logic := '0'; |
signal RX_DIFF: std_logic_vector(11 downto 0) := (others => '0'); |
signal MAC_RXD_D: std_logic_vector(7 downto 0) := (others => '0'); |
signal MAC_RX_SAMPLE2_CLK: std_logic := '0'; |
|
--// RX 32-BIT CRC COMPUTATION ------------------------------------------------------- |
signal RX_CRC32_RESET: std_logic := '0'; |
signal RX_CRC32: std_logic_vector(31 downto 0) := (others => '0'); |
signal RX_CRC32_VALID: std_logic := '0'; |
signal RX_BAD_CRC: std_logic := '0'; |
|
--// PARSE RX DATA ------------------------------------------------------------------- |
signal MAC_RXD3: std_logic_vector(7 downto 0); |
signal MAC_RX_SAMPLE3_CLK: std_logic := '0'; |
--signal MAC_RX_SOF3: std_logic := '0'; |
signal MAC_RX_EOF3A: std_logic := '0'; |
signal MAC_RX_EOF3B: std_logic := '0'; |
signal MAC_RX_EOF3B_D: std_logic := '0'; |
signal MAC_RX_EOF3: std_logic := '0'; |
signal RX_FRAME_EN3: std_logic := '0'; |
|
--// RX INPUT ELASTIC BUFFER ---------------------------------------------------------- |
signal MAC_RX_DIPA: std_logic_vector(0 downto 0); |
signal MAC_RX_DOPB: std_logic_vector(0 downto 0); |
signal MAC_RX_WPTR: std_logic_vector(10 downto 0); |
signal MAC_RX_WPTR_D: std_logic_vector(10 downto 0); |
signal MAC_RX_WPTR_D2: std_logic_vector(10 downto 0); |
signal MAC_RX_WPTR_D3: std_logic_vector(10 downto 0); |
signal MAC_RX_WPTR_CONFIRMED: std_logic_vector(10 downto 0) := (others => '0'); |
signal MAC_RX_WPTR_STABLE: std_logic := '0'; |
signal MAC_RX_WPTR_STABLE_D: std_logic := '0'; |
signal RX_COUNTER8: std_logic_vector(2 downto 0) := "000"; |
signal MAC_RX_RPTR: std_logic_vector(10 downto 0); |
signal MAC_RXD4: std_logic_vector(7 downto 0); |
signal MAC_RX_SAMPLE4_CLK: std_logic := '0'; |
signal MAC_RX_SAMPLE4_CLK_E: std_logic := '0'; |
signal MAC_RX_EOF4: std_logic := '0'; |
signal MAC_RX_BUF_SIZE: std_logic_vector(10 downto 0); |
signal MAC_RX_EOF4_FLAG: std_logic := '1'; |
|
signal PHY_CONFIG_TP: std_logic_vector(10 downto 1); |
|
|
-------------------------------------------------------- |
-- IMPLEMENTATION |
-------------------------------------------------------- |
begin |
|
|
-- PHY-supplied RX global clock |
RECLOCK_003: process(ASYNC_RESET, RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
RESETRX_FLAG_D <= ASYNC_RESET; |
RESETRX_FLAG_D2 <= RESETRX_FLAG_D; |
|
-- 1-CLK clock synchronous reset pulse at the end of the async pulse |
if(RESETRX_FLAG_D = '0') and (RESETRX_FLAG_D2 = '1') then |
-- end of external reset pulse. generate a CLK synchronous reset |
SYNC_RESETRX <= '1'; |
else |
SYNC_RESETRX <= '0'; |
end if; |
end if; |
end process; |
|
|
--// PHY RESET AND CONFIGURATION ---------------------------------------------------------- |
-- First generate a RESET_N pulse 10ms long, then wait 50ms before programming the PHY |
-- We cannot assume that the 125 MHz reference clock is present. |
|
-- convert ASYNC_RESET to a CLK-synchronous RESET pulse |
RECLOCK_002: process(ASYNC_RESET, CLK) |
begin |
if rising_edge(CLK) then |
RESETFLAG_D <= ASYNC_RESET; |
RESETFLAG_D2 <= RESETFLAG_D; |
|
-- 1-CLK clock synchronous reset pulse at the end of the async pulse |
if(RESETFLAG_D = '0') and (RESETFLAG_D2 = '1') then |
-- end of external reset pulse. generate a CLK synchronous reset |
SYNC_RESET <= '1'; |
else |
SYNC_RESET <= '0'; |
end if; |
end if; |
end process; |
|
-- PHY reset at power up or SYNC_RESET |
-- Generates a 10ms RESET_N pulse followed by a TBD ms delay and a INITIAL_CONFIG_PULSE. |
-- The delay between RESET_N de-assertion and config pulse is 50ms (conservative. It takes time for PHY to configure. |
-- even though the specs states 100us is sufficient, we find that 40ms min is needed). |
Inst_RESET_TIMER: RESET_TIMER |
GENERIC MAP( |
CLK_FREQUENCY => CLK_FREQUENCY -- user clock frequency in MHz |
) |
PORT MAP( |
CLK => CLK, -- user clock, always present |
RESET_START => SYNC_RESET, |
RESET_COMPLETE => RESET_COMPLETE, |
INITIAL_CONFIG_PULSE => INITIAL_CONFIG_PULSE, -- config pulse 50ms after RESET_N deassertion |
RESET_N => RESET_N_LOCAL |
); |
|
RESET_N <= RESET_N_LOCAL; |
|
-- |
---- enact the configuration |
PHY_CONFIG_CHANGE_001: process(CLK) |
begin |
if rising_edge(CLK) then |
if(INITIAL_CONFIG_PULSE = '1') then |
-- A default configuration is loaded automatically after power up. |
PHY_CONFIG_CHANGE_A <= '1'; |
PHY_RESET_A <= '0'; -- no software PHY reset, we just did a hardware reset |
SPEED_A <= "11"; -- auto |
DUPLEX_A <= '1'; |
TEST_MODE_A <= "00"; |
POWER_DOWN_A <= '0'; |
elsif(PHY_CONFIG_CHANGE = '1') then |
-- PHY_CONFIG_CHANGE indicates a user-triggered configuration change. |
PHY_CONFIG_CHANGE_A <= '1'; |
PHY_RESET_A <= PHY_RESET; |
SPEED_A <= SPEED; |
DUPLEX_A <= DUPLEX; |
TEST_MODE_A <= TEST_MODE; |
POWER_DOWN_A <= POWER_DOWN; |
else |
PHY_CONFIG_CHANGE_A <= '0'; |
end if; |
end if; |
end process; |
|
|
-- PHY monitoring and control |
Inst_PHY_CONFIG: PHY_CONFIG |
GENERIC MAP( |
PHY_ADDR => PHY_ADDR |
) |
PORT MAP( |
SYNC_RESET => SYNC_RESET, |
CLK => CLK, |
CONFIG_CHANGE => PHY_CONFIG_CHANGE_A, |
PHY_RESET => PHY_RESET_A, |
SPEED => SPEED_A, |
DUPLEX => DUPLEX_A, |
TEST_MODE => TEST_MODE_A, |
POWER_DOWN => POWER_DOWN_A, |
CLK_SKEW => CLK_SKEW_A, |
SREG_READ_START => SREG_READ_START, |
SREG_REGAD => "000000010", -- register 2: PHY Identifier 1 |
SREG_DATA => PHY_ID_LOCAL, |
SREG_SAMPLE_CLK => SREG_SAMPLE_CLK, |
LINK_STATUS => LINK_STATUS_local, |
MCLK => MCLK, |
MDI => MDI, |
MDO => MDO, |
MDT => MDT |
); |
PHY_ID <= PHY_ID_LOCAL; |
|
---- tri-state MDIO port |
--IOBUF_inst : IOBUF |
--generic map ( |
-- DRIVE => 12, |
-- IOSTANDARD => "DEFAULT", |
-- SLEW => "SLOW") |
--port map ( |
-- O => MDI, -- Buffer output |
-- IO => MDIO, -- Buffer inout port (connect directly to top-level port) |
-- I => MDO, -- Buffer input |
-- T => MDT -- 3-state enable input, high=input, low=output |
--); |
|
|
-- read PHY identification once at power-up or reset (hardware self-test) |
PHY_STATUS_001: process(CLK) |
begin |
if rising_edge(CLK) then |
if(PHY_CONFIG_CHANGE_A = '1') then -- power-up/reset |
SREG_READ_START <= '1'; -- start asking for status register |
elsif(SREG_SAMPLE_CLK = '1') then |
SREG_READ_START <= '0'; |
end if; |
end if; |
end process; |
--// PHY INTERFACE: RGMII FORMATTING ---------------------------------------------------------- |
|
-- Translation RGMII (PHY interface) - GMII (MAC interface) |
-- Adjust the TXC and RXC clock 2ns delays within as needed. |
PHY_IF_WRAPPER_RESET <= SYNC_RESETRX; |
|
LINK_STATUS <= LINK_STATUS_local; |
DUPLEX_STATUS <= DUPLEX_STATUS_local; |
SPEED_STATUS <= SPEED_STATUS_LOCAL; |
|
--// PHY INTERFACE: GMII/MII FORMATTING ---------------------------------------------------------- |
-- TODO: make tx clk the same as rx clk (same RGMII_WRAPPER). |
Inst_GMII_MII_WRAPPER: GMII_MII_WRAPPER_V6 PORT MAP( |
SYNC_RESET => PHY_IF_WRAPPER_RESET, |
CLK => CLK, |
IDELAYREFCLK200MHZ => IDELAYREFCLK200MHZ, |
TX_CLK => MII_TX_CLK, -- MII tx clock from PHY |
GTX_CLK => GMII_TX_CLK, -- GMII tx clock to PHY |
TXD => GMII_MII_TXD, |
TX_EN => GMII_MII_TX_EN, |
TX_ER => GMII_MII_TX_ER, |
RX_CLK => GMII_MII_RX_CLK, |
RXD => GMII_MII_RXD, |
RX_DV => GMII_MII_RX_DV, |
RX_ER => GMII_MII_RX_ER, |
CRS => GMII_MII_CRS, |
COL => GMII_MII_COL, |
MAC_RX_CLK => RX_CLKG, |
MAC_RXD => MAC_RXD0, |
MAC_RX_DV => MAC_RX_DV0, |
MAC_RX_ER => MAC_RX_ER0, |
MAC_RX_SAMPLE_CLK => MAC_RX_SAMPLE_CLK0, |
MAC_TXD => MAC_TXD, |
MAC_TX_EN => MAC_TX_EN, |
MAC_TX_ER => MAC_TX_ER, |
MAC_TX_SAMPLE_CLK => MAC_TX_SAMPLE_CLK, |
MAC_TX_SPEED => TX_SPEED, |
MAC_CRS => CRS, |
MAC_COL => COL, |
LINK_STATUS => open,--LINK_STATUS_local, |
SPEED_STATUS => SPEED_STATUS_LOCAL, |
DUPLEX_STATUS => DUPLEX_STATUS_local |
); |
|
-- Vodoo code (Isim simulator is confused otherwise). Reclock RX signals. |
-- My guess: simulator does not like the BUFG or delay within the GMII_MII_WRAPPER. |
-- Small penalty: just a few Flip Flops. |
RX_RECLOCK_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
MAC_RXD <= MAC_RXD0; |
MAC_RX_DV <= MAC_RX_DV0; |
MAC_RX_ER <= MAC_RX_ER0; |
MAC_RX_SAMPLE_CLK <= MAC_RX_SAMPLE_CLK0; |
end if; |
end process; |
|
--// TX ELASTIC BUFFER ---------------------------------------------------------- |
-- The purpose of the elastic buffer is two-fold: |
-- (a) a transition between the CLK-synchronous user side, and the RX_CLKG synchronous PHY side |
-- (b) storage for Ethernet transmit frames, to absorb traffic peaks, minimize the number of |
-- UDP packets lost at high throughput. |
-- The tx elastic buffer is 16Kbits, large enough for TWO complete maximum size |
-- (14addr+1500data+4FCS = 1518B) frames. |
|
-- write pointer management |
MAC_TX_WPTR_001: process(ASYNC_RESET, CLK) |
begin |
if(ASYNC_RESET = '1') then |
MAC_TX_WPTR <= (others => '0'); |
elsif rising_edge(CLK) then |
TX_COUNTER8 <= TX_COUNTER8 + 1; |
|
if (SYNC_RESET = '1') then |
MAC_TX_WPTR <= (others => '0'); |
elsif(MAC_TX_DATA_VALID = '1') then |
MAC_TX_WPTR <= MAC_TX_WPTR + 1; |
end if; |
|
-- update WPTR_D once every 8 clocks. |
if(TX_COUNTER8 = 7) then |
MAC_TX_WPTR_D <= MAC_TX_WPTR; |
end if; |
|
-- allow WPTR reclocking with another clock, as long as it is away from the transition area |
if(TX_COUNTER8 < 6) then |
MAC_TX_WPTR_STABLE <= '1'; |
else |
MAC_TX_WPTR_STABLE <= '0'; |
end if; |
|
|
end if; |
end process; |
|
MAC_TX_DIPA(0) <= MAC_TX_EOF; -- indicates last byte in the tx packet |
|
-- select which RAMBlock to write to. |
MAC_TX_WEA(0) <= MAC_TX_DATA_VALID and (not MAC_TX_WPTR(11)); |
MAC_TX_WEA(1) <= MAC_TX_DATA_VALID and MAC_TX_WPTR(11); |
|
-- No need for initialization |
RAMB16_X: for I in 0 to 1 generate |
RAMB16_001: RAMB16_S9_S9 |
port map( |
DIA => MAC_TX_DATA, |
DIB => x"00", |
DIPA => MAC_TX_DIPA(0 downto 0), |
DIPB => "0", |
DOPA => open, |
DOPB => MAC_TX_DOPB(I)(0 downto 0), |
ENA => '1', |
ENB => '1', |
WEA => MAC_TX_WEA(I), |
WEB => '0', |
SSRA => '0', |
SSRB => '0', |
CLKA => CLK, |
CLKB => RX_CLKG, |
ADDRA => MAC_TX_WPTR(10 downto 0), |
ADDRB => MAC_TX_RPTR(10 downto 0), |
DOA => open, |
DOB => MAC_TX_DOB(I) |
); |
end generate; |
|
MAC_TX_DATA2 <= MAC_TX_DOB(conv_integer(MAC_TX_RPTR_D(11))); |
MAC_TX_EOF2 <= MAC_TX_DOPB(conv_integer(MAC_TX_RPTR_D(11)))(0); |
|
-- RX_CLKG zone. Reclock WPTR |
MAC_TX_WPTR_002: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
MAC_TX_WPTR_STABLE_D <= MAC_TX_WPTR_STABLE; |
MAC_TX_WPTR_D2 <= MAC_TX_WPTR_D; |
|
if(MAC_TX_WPTR_STABLE_D = '1') then |
-- WPTR is stable. OK to resample with the RX_CLKG clock. |
MAC_TX_WPTR_D3 <= MAC_TX_WPTR_D2; |
end if; |
end if; |
end process; |
|
MAC_TX_BUF_SIZE <= MAC_TX_WPTR_D3 + not(MAC_TX_RPTR); |
-- occupied tx buffer size for reading purposes (CLKG clock domain)( |
-- always lags, could be a bit more, never less. |
|
--//-- TX FLOW CONTROL -------------------------------- |
-- ask for more input data if there is room for at least 1K more input bytes |
-- Never write past the last confirmed read pointer location. |
|
-- read the last confirmed read pointer location and reclock in CLK domain when stable |
MAC_TX_CTS_001: process(CLK) |
begin |
if rising_edge(CLK) then |
TX_SUCCESS_TOGGLE_D <= TX_SUCCESS_TOGGLE; |
TX_SUCCESS_TOGGLE_D2 <= TX_SUCCESS_TOGGLE_D; |
if(TX_SUCCESS_TOGGLE_D2 /= TX_SUCCESS_TOGGLE_D) then |
-- shortly after successful packet transmission. |
MAC_TX_RPTR_CONFIRMED_D <= MAC_TX_RPTR_CONFIRMED; |
end if; |
end if; |
end process; |
|
-- Compute available room for more tx data |
MAC_TX_CTS_002: process(CLK) |
begin |
if rising_edge(CLK) then |
MAC_TX_BUF_FREE <= not (MAC_TX_WPTR_D2 + not MAC_TX_RPTR_CONFIRMED_D); |
end if; |
end process; |
-- Is there enough room for a complete max size frame? |
-- Don't cut it too close because user interface can flood the buffer very quickly (CLK @ 125 MHz clock) |
-- while we compute the buffer size with the possibly much slower RX_CLG (could be 2.5 MHz for 10Mbps). |
MAC_TX_CTS_003: process(CLK) |
begin |
if rising_edge(CLK) then |
if(SYNC_RESETRX = '1') then |
MAC_TX_CTS_local <= '0'; -- reset |
elsif(LINK_STATUS_local = '0') then |
-- don't ask the stack for data if there is no link |
MAC_TX_CTS_local <= '0'; -- reset |
elsif(MAC_TX_BUF_FREE(11) = '0') then |
-- room for less than 2KB. Activate flow control |
MAC_TX_CTS_local <= '0'; |
else |
MAC_TX_CTS_local <= '1'; |
end if; |
end if; |
end process; |
MAC_TX_CTS <= LINK_STATUS_local;--LINK_STATUS_local;--MAC_TX_CTS_local; |
|
|
-- manage read pointer |
MAC_TX_RPTR_001: process(ASYNC_RESET, RX_CLKG) |
begin |
if(ASYNC_RESET = '1') then |
MAC_TX_RPTR <= (others => '1'); |
MAC_TX_RPTR_D <= (others => '1'); |
elsif rising_edge(RX_CLKG) then |
MAC_TX_RPTR_D <= MAC_TX_RPTR; |
|
if(TX_STATE = 2) and (TX_BYTE_CLK = '1') and (MAC_TX_EOF2 = '1') then |
-- special case. Immediately block output sample clk because we have just read past the end of |
-- packet (nothing we could do about it). |
MAC_TX_SAMPLE2_CLK <= '0'; |
else |
-- regular case: 1 clk delay to extract data from ramb. |
-- aligned with MAC_TX_DATA2 byte. |
MAC_TX_SAMPLE2_CLK <= MAC_TX_SAMPLE2_CLK_E; |
end if; |
|
if(SYNC_RESETRX = '1') then |
MAC_TX_RPTR <= (others => '1'); |
elsif(TX_STATE = 1) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(2 downto 0) <= 1) then |
-- read the first byte(s) in advance (need 2 RX_CLKG to get the data out) |
-- Note: we may temporarily read past the write pointer (by one location) |
-- but will rewind immediately thereafter |
MAC_TX_SAMPLE2_CLK_E <= '1'; |
MAC_TX_RPTR <= MAC_TX_RPTR + 1; |
elsif(TX_STATE = 2) and (TX_EVENT3 = '1') then |
-- we are done reading the packet. rewind the read pointer, as we went past the end of packet. |
MAC_TX_SAMPLE2_CLK_E <= '0'; |
MAC_TX_RPTR <= MAC_TX_RPTR - 1; |
elsif(TX_STATE = 2) and (TX_BYTE_CLK = '1') then |
-- read the rest of the packet |
-- forward data from input elastic buffer to RGMII interface |
-- Note: we may temporarily read past the write pointer (by one location) |
-- but will rewind immediately thereafter |
MAC_TX_SAMPLE2_CLK_E <= '1'; |
MAC_TX_RPTR <= MAC_TX_RPTR + 1; |
elsif(TX_STATE = 6) then |
-- collision detected. rewind read pointer to the start of frame. |
MAC_TX_RPTR <= MAC_TX_RPTR_CONFIRMED; |
else |
MAC_TX_SAMPLE2_CLK_E <= '0'; |
end if; |
end if; |
end process; |
|
-- update confirmed read pointer after successful frame transmission |
MAC_TX_RPTR_002: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(SYNC_RESETRX = '1') then |
MAC_TX_RPTR_CONFIRMED <= (others => '1'); |
TX_SUCCESS_TOGGLE <= '0'; |
elsif(TX_SUCCESS = '1') then |
MAC_TX_RPTR_CONFIRMED <= MAC_TX_RPTR; |
TX_SUCCESS_TOGGLE <= not TX_SUCCESS_TOGGLE; |
end if; |
end if; |
end process; |
|
-- How many COMPLETE tx frames are available for transmission in the input elastic buffer? |
-- Transmission is triggered by the availability of a COMPLETE frame in the buffer (not just a few frame bytes) |
-- It is therefore important to keep track of the number of complete frames. |
-- At the elastic buffer input, a new complete frame is detected upon receiving the EOF pulse. |
COMPLETE_TX_FRAMES_001: process(ASYNC_RESET, CLK) |
begin |
if (ASYNC_RESET = '1') then |
MAC_TX_EOF_TOGGLE <= '0'; |
elsif rising_edge(CLK) then |
if(MAC_TX_DATA_VALID = '1') and (MAC_TX_EOF = '1') then |
MAC_TX_EOF_TOGGLE <= not MAC_TX_EOF_TOGGLE; -- Need toggle signal to generate copy in RX_CLKG clock domain |
end if; |
end if; |
end process; |
|
|
COMPLETE_TX_FRAMES_002: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
MAC_TX_EOF_TOGGLE_D <= MAC_TX_EOF_TOGGLE; -- reclock in RX_CLKG clock domain (to prevent glitches) |
MAC_TX_EOF_TOGGLE_D2 <= MAC_TX_EOF_TOGGLE_D; |
|
if (SYNC_RESETRX = '1') then |
COMPLETE_TX_FRAMES_INBUF <= (others => '0'); |
|
elsif(MAC_TX_EOF_TOGGLE_D2 /= MAC_TX_EOF_TOGGLE_D) and (TX_SUCCESS = '0') then |
-- just added another complete frame into the tx buffer (while no successful transmission concurrently) |
COMPLETE_TX_FRAMES_INBUF <= COMPLETE_TX_FRAMES_INBUF + 1; |
elsif(MAC_TX_EOF_TOGGLE_D2 = MAC_TX_EOF_TOGGLE_D) and (TX_SUCCESS = '1') |
and (ATLEAST1_COMPLETE_TX_FRAME_INBUF = '1') then |
-- a frame was successfully transmitted (and none was added at the very same instant) |
COMPLETE_TX_FRAMES_INBUF <= COMPLETE_TX_FRAMES_INBUF - 1; |
end if; |
end if; |
end process; |
|
-- Flag to indicate at least one complete tx frame in buffer. |
ATLEAST1_COMPLETE_TX_FRAME_INBUF <= '0' when (COMPLETE_TX_FRAMES_INBUF = 0) else '1'; |
|
|
DELAY_EOF2: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(TX_BYTE_CLK = '1') then |
-- delay by one byte |
MAC_TX_EOF2_D <= MAC_TX_EOF2; |
end if; |
end if; |
end process; |
|
|
--// MAC TX STATE MACHINE ---------------------------------------------------------- |
TX_SPEED <= SPEED_STATUS_LOCAL; -- transmit speed is as auto-negotiated by the rx PHY. |
-- test test test simulation at various LAN speeds |
--TX_SPEED <= "01"; |
|
-- Tx timers ------------------------ |
-- Generate transmit clock. Depends on the tx_speed. |
-- Clock is always enabled, even when not transmitting (reason: we need to be |
-- able to convey to the RGMII wrapper when to stop, etc). |
-- Important distinction between TX_CLK and TX_BYTE_CLK because GMII interface is 4-bit wide |
-- for 10/100 Mbps and 8-bit wide for 1000 Mbps. |
-- Thus, TX_BYTE_CLK is half the frequency of TX_CLK, but pulses are aligned. |
TX_CLK_GEN_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if (SYNC_RESETRX = '1') then |
TX_BYTE_CLK <= '0'; |
TX_HALF_BYTE_FLAG <= '0'; |
elsif (TX_SPEED = "10") then |
-- 1000 Mbps |
TX_BYTE_CLK <= '1'; |
elsif (TX_SPEED = "01") or (TX_SPEED = "00") then |
-- 10/100 Mbps. |
-- divide by two to get the byte clock when 10/100 Mbps |
TX_HALF_BYTE_FLAG <= not TX_HALF_BYTE_FLAG; |
if(TX_HALF_BYTE_FLAG = '1') then |
TX_BYTE_CLK <= '1'; |
else |
TX_BYTE_CLK <= '0'; |
end if; |
else |
TX_BYTE_CLK <= '0'; |
end if; |
end if; |
end process; |
|
|
-- 96-bit InterPacketGap (Interframe Delay) timer |
IPG_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if (SYNC_RESETRX = '1') then |
IPG_CNTR <= (others => '0'); |
CRS_D <= '0'; |
else |
CRS_D <= CRS; -- reclock with RX_CLKG |
|
if((CRS_D = '1') and (DUPLEX = '0')) or (TX_EN = '1') or (TX_STATE = 5) then |
-- detected passing packet (half-duplex only) or transmission is in progress |
-- or carrier extension in progress |
-- Arm InterPacketGap timer |
IPG_CNTR <= x"0C" ; -- 96 bits = 12 bytes 802.3 section 4.4.2 |
elsif(IPG_CNTR > 0) and (TX_BYTE_CLK = '1') then |
-- after end of passing packet, decrement counter downto to zero (InterPacketGap). |
IPG_CNTR <= IPG_CNTR - 1; |
end if; |
end if; |
end if; |
end process; |
IPG <= '1' when (IPG_CNTR = 0) else '0'; -- '1' last passing packet was more than InterPacketGap ago. OK to start tx. |
|
-- Events ------------------------ |
-- First tx packet trigger |
TX_EVENT1 <= '0' when (ATLEAST1_COMPLETE_TX_FRAME_INBUF = '0') else -- no COMPLETE frame in tx input buffer |
'0' when (MAC_TX_BUF_SIZE = 0) else -- no data in tx input buffer |
'0' when (IPG = '0') else -- medium is not clear. need to wait after the InterPacketGap. Deferring on. |
'0' when (TX_SUCCESS = '1') else -- don't act too quickly. It takes one RX_CLKG to update the complete_tx_frame_inbuf counter. |
'0' when (PHY_IF_WRAPPER_RESET = '1') else -- PHY/RGMII wrapper are being reset. Do not start tx. |
TX_BYTE_CLK; -- go ahead..start transmitting. align event pulse with TX_BYTE_CLK |
|
-- collision detection, half-duplex mode, within the timeSlot |
-- Timeslot is 64 bytes for 10/100 Mbps and 512 bytes for 1000 Mbps, starting at the preamble. |
TX_EVENT2 <= '1' when ((COL = '1') and (DUPLEX = '0') and (TX_SPEED = "10") and (TX_BYTE_COUNTER(10 downto 0) < 503)) else |
'1' when ((COL = '1') and (DUPLEX = '0') and (TX_SPEED(1) = '0') and (TX_BYTE_COUNTER(10 downto 0) < 55)) else |
'0'; |
|
-- end of frame detected at tx buffer output. |
-- Timing depends on the TX_SPEED (because of the delay in reading data from tx buffer output) |
TX_EVENT3 <= '1' when (TX_BYTE_CLK = '1') and (MAC_TX_EOF2 = '1') and (TX_SPEED = "10") else |
'1' when (TX_BYTE_CLK = '1') and (MAC_TX_EOF2_D = '1') and (TX_SPEED(1) = '0') else |
'0'; |
|
-- Tx state machine ------------------------ |
TX_STATE_GEN_001: process(RX_CLKG, MAC_ADDR) |
begin |
if rising_edge(RX_CLKG) then |
if (SYNC_RESETRX = '1') or (LINK_STATUS_local = '0') then |
TX_STATE <= 0; -- idle state |
TX_SUCCESS <= '0'; |
TX_BYTE_CLK_D <= '0'; |
RETX_ATTEMPT_COUNTER <= (Others => '0'); -- re-transmission attempts counter |
else |
|
TX_BYTE_CLK_D <= TX_BYTE_CLK; -- output byte ready one RX_CLKG later |
|
if(TX_STATE = 0) then |
TX_SUCCESS <= '0'; |
RETX_ATTEMPT_COUNTER <= (Others => '0'); -- reset re-transmission attempts counter |
if (TX_EVENT1 = '1') then |
-- start tx packet: send 1st byte of preamble |
TX_STATE <= 1; |
TX_BYTE_COUNTER2 <= "111"; -- 8-byte preamble + start of frame sequence |
end if; |
elsif(TX_STATE = 1) and (DUPLEX = '0') and (COL = '1') then |
-- collision sensing while in half-duplex mode. |
-- The packet header being transmitted is well within the slot time limit. |
TX_STATE <= 6; -- send jam |
TX_BYTE_COUNTER2 <= "011"; -- jamSize = 32 bits = 4 Bytes |
elsif(TX_STATE = 1) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(2 downto 0) /= 0) then |
-- counting through the preamble + start frame sequence |
TX_BYTE_COUNTER2 <= TX_BYTE_COUNTER2 - 1; |
elsif(TX_STATE = 1) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(2 downto 0) = 0) then |
-- end of preamble. start forwarding data from elastic buffer to RGMII wrapper |
TX_STATE <= 2; |
TX_BYTE_COUNTER <= (others => '0'); |
elsif(TX_STATE = 2) and (TX_EVENT2 = '1') then |
-- collision sensing while in half-duplex mode and within the specified slot time (starting at the preamble) |
TX_STATE <= 6; -- send jam |
TX_BYTE_COUNTER2 <= "011"; -- jamSize = 32 bits = 4 Bytes |
elsif(TX_STATE = 2) and (TX_BYTE_CLK = '1') and (TX_EVENT3 = '0') then |
-- keep track of the payload byte count (to detect the need for padding) |
TX_BYTE_COUNTER <= TX_BYTE_COUNTER + 1; |
elsif(TX_STATE = 2) and (TX_BYTE_CLK = '1') and (TX_EVENT3 = '1') then |
-- found end of frame |
TX_BYTE_COUNTER <= TX_BYTE_COUNTER + 1; |
if (TX_BYTE_COUNTER(10 downto 0) < 59) then |
if (MAC_TX_CONFIG(1 downto 0) = "11") then |
-- frame is too short: payload data does not meet minimum 60-byte size. |
-- user enabled automatic padding and automatic CRC32 insertion |
TX_STATE <= 3; |
else |
-- error: frame is too short. abort. |
TX_STATE <= 10; |
end if; |
elsif (MAC_TX_CONFIG(1) = '1') then |
-- user enabled auto-CRC32 insertion. Start inserting CRC |
TX_STATE <= 4; |
TX_BYTE_COUNTER2 <= "011"; -- 4-byte CRC(FCS) |
elsif (TX_BYTE_COUNTER(10 downto 0) >= 63) then |
-- complete packet (including user-supplied CRC) |
-- Carrier Extension? Applicable to 1000 Mbps half-duplex |
if(TX_SPEED = "10") and (DUPLEX = '0') and (TX_BYTE_COUNTER(10 downto 0) < 511) then |
-- Carrier extension to slotTime (512 bytes) as per 802.3 Section 4.2.3.4 |
TX_STATE <= 5; |
else |
-- we are done here |
TX_STATE <= 0; |
TX_SUCCESS <= '1'; -- completed frame transmission |
end if; |
else |
-- error. frame is too short (< 64 bytes including 4-byte CRC). abort. |
TX_STATE <= 10; |
end if; |
elsif(TX_STATE = 3) and (TX_EVENT2 = '1') then |
-- collision sensing while in half-duplex mode and within the specified slot time (starting at the preamble) |
TX_STATE <= 6; -- send jam |
TX_BYTE_COUNTER2 <= "011"; -- jamSize = 32 bits = 4 Bytes |
elsif(TX_STATE = 3) and (TX_BYTE_CLK = '1') then |
TX_BYTE_COUNTER <= TX_BYTE_COUNTER + 1; |
if(TX_BYTE_COUNTER(10 downto 0) < 59) then |
-- padding payload field to the minimum size. |
-- keep track of the byte count |
elsif (MAC_TX_CONFIG(1) = '1') then |
-- Completed padding. User enabled CRC32 insertion. Start inserting CRC |
TX_STATE <= 4; |
TX_BYTE_COUNTER2 <= "011"; -- 4-byte CRC(FCS) |
else |
-- error. Illegal user configuration. auto-pad requires auto-CRC. abort. |
TX_STATE <= 10; |
end if; |
elsif(TX_STATE = 4) and (TX_EVENT2 = '1') then |
-- collision sensing while in half-duplex mode and within the specified slot time (starting at the preamble) |
TX_STATE <= 6; -- send jam |
TX_BYTE_COUNTER2 <= "011"; -- jamSize = 32 bits = 4 Bytes |
elsif(TX_STATE = 4) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(1 downto 0) /= 0) then |
-- counting through the CRC/FCS sequence |
TX_BYTE_COUNTER2 <= TX_BYTE_COUNTER2 - 1; |
TX_BYTE_COUNTER <= TX_BYTE_COUNTER + 1; |
elsif(TX_STATE = 4) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(1 downto 0) = 0) then |
-- end of CRC/FCS. Packet is now complete. |
TX_BYTE_COUNTER <= TX_BYTE_COUNTER + 1; |
-- Carrier Extension? Applicable to 1000 Mbps half-duplex |
if(TX_SPEED = "10") and (DUPLEX = '0') and (TX_BYTE_COUNTER(10 downto 0) < 511) then |
-- Carrier extension to slotTime (512 bytes) as per 802.3 Section 4.2.3.4 |
TX_STATE <= 5; |
else |
-- we are done here |
TX_STATE <= 0; |
TX_SUCCESS <= '1'; -- completed frame transmission |
end if; |
elsif(TX_STATE = 5) and (TX_EVENT2 = '1') then |
-- collision sensing while in half-duplex mode and within the specified slot time (starting at the preamble) |
TX_STATE <= 6; -- send jam |
TX_BYTE_COUNTER2 <= "011"; -- jamSize = 32 bits = 4 Bytes |
elsif(TX_STATE = 5) and (TX_BYTE_CLK = '1') then |
-- Carrier extension |
TX_BYTE_COUNTER <= TX_BYTE_COUNTER + 1; |
if(TX_BYTE_COUNTER(10 downto 0) >= 511) then |
-- met slotTime requirement. |
TX_STATE <= 0; |
TX_SUCCESS <= '1'; -- completed frame transmission |
end if; |
elsif(TX_STATE = 6) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(1 downto 0) /= 0) then |
-- Jam . counting through the 4-byte jam |
TX_BYTE_COUNTER2 <= TX_BYTE_COUNTER2 - 1; |
elsif(TX_STATE = 6) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(1 downto 0) = 0) then |
-- end of Jam |
|
-- re-transmit? |
if(RETX_ATTEMPT_COUNTER < 16) then |
-- we have not yet reached the attemptLimit |
TX_STATE <= 7; -- backoff |
RETX_ATTEMPT_COUNTER <= RETX_ATTEMPT_COUNTER + 1; |
-- set backoff |
if(TX_SPEED = "10") then |
-- 1000 Mbps. Backoff is an integer multiple of slotTime: |
-- random * slotTime. slotTime = 512 Bytes |
TX_BYTE_COUNTER(8 downto 0) <= (others => '1'); |
TX_BYTE_COUNTER(18 downto 9) <= RETX_RANDOM_BKOFF; -- uniform random variable. range 0 - 1023 |
elsif(TX_SPEED(1) = '0') then |
-- 10/100 Mbps. Backoff is an integer multiple of slotTime: |
-- random * slotTime. slotTime = 64 Bytes |
TX_BYTE_COUNTER(5 downto 0) <= (others => '1'); |
TX_BYTE_COUNTER(15 downto 6) <= RETX_RANDOM_BKOFF; -- uniform random variable. range 0 - 1023; |
TX_BYTE_COUNTER(18 downto 16) <= (others => '0'); |
end if; |
else |
TX_STATE <= 10; -- error. could not transmit packet |
end if; |
elsif(TX_STATE = 7) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER /= 0) then |
-- backoff timer |
TX_BYTE_COUNTER <= TX_BYTE_COUNTER - 1; |
elsif(TX_STATE = 7) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER = 0) then |
-- backoff timer expired. try sending again |
-- start tx packet: send 1st byte of preamble |
TX_STATE <= 1; |
TX_BYTE_COUNTER2 <= "111"; -- 8-byte preamble + start of frame sequence |
end if; |
end if; |
end if; |
end process; |
|
-- Tx packet assembly ------------------------ |
-- generate 7-byte preamble, 1-byte start frame sequence |
-- TX_PREAMBLE is aligned with TX_BYTE_CLK_D |
PREAMBLE_GEN_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(TX_STATE = 1) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(2 downto 0) = 1) then |
TX_PREAMBLE <= "11010101"; -- start frame delimiter (SFD). |
-- [note: standard shows LSb D0 to the left, MSb D7 to the right, as per serial transmission sequence.] |
elsif(TX_BYTE_CLK = '1') then |
-- new packet or re-transmission |
TX_PREAMBLE <= "01010101"; -- preamble |
-- [note: standard shows LSb to the left, MSb to the right, as per serial transmission sequence.] |
end if; |
end if; |
end process; |
|
-- mux 4-byte frame check sequence |
-- TX_FCS is aligned with TX_BYTE_CLK_D |
FCS_GEN_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
-- send MSB first (802.11 Section 3.2.9). |
-- Don't have time to reclock TX_CRC32_FLIPPED_INV(31 downto 24): will be muxed without reclocking. |
if(TX_STATE = 4) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(1 downto 0) = 3) then |
TX_FCS <= TX_CRC32_FLIPPED_INV(23 downto 16); |
elsif(TX_STATE = 4) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(1 downto 0) = 2) then |
TX_FCS <= TX_CRC32_FLIPPED_INV(15 downto 8); |
elsif(TX_STATE = 4) and (TX_BYTE_CLK = '1') and (TX_BYTE_COUNTER2(1 downto 0) = 1) then |
TX_FCS <= TX_CRC32_FLIPPED_INV(7 downto 0); |
end if; |
end if; |
end process; |
|
|
TX_EN <= '0' when (TX_STATE = 0) else -- idle |
'1' when (TX_STATE < 5) else -- normal transmission |
'1' when (TX_STATE = 6) else -- 32-bit jam after collision detection |
'0'; |
|
TX_ER <= '1' when (TX_STATE = 5) else -- carrier extension |
'0'; |
|
-- mux preamble, start frame sequence, data, fcs, etc and forward to GMII tx interface |
-- MAC_TX_DATA4 is aligned with TX_BYTE_CLK_D |
TX_MUX_001: process(TX_STATE, TX_BYTE_COUNTER2, TX_PREAMBLE, MAC_TX_DATA2, TX_CRC32_FLIPPED_INV, TX_FCS) |
begin |
if(TX_STATE = 1) then |
-- 7-byte preamble and 1-byte start frame sequence |
MAC_TX_DATA4 <= TX_PREAMBLE; |
elsif(TX_STATE = 2) then |
-- payload data |
MAC_TX_DATA4 <= MAC_TX_DATA2; |
elsif(TX_STATE = 3) then |
-- padding |
MAC_TX_DATA4 <= x"00"; -- padding with zeros. |
elsif(TX_STATE = 4) and (TX_BYTE_COUNTER2(1 downto 0) = 3) then |
-- Frame Check Sequence |
MAC_TX_DATA4 <= TX_CRC32_FLIPPED_INV(31 downto 24); -- no time to reclock. need it now |
elsif(TX_STATE = 4) and (TX_BYTE_COUNTER2(1 downto 0) < 3) then |
-- Frame Check Sequence |
MAC_TX_DATA4 <= TX_FCS; |
elsif(TX_STATE = 5) then |
-- carrier extend |
MAC_TX_DATA4 <= x"0F"; |
else |
-- TODO tail end |
MAC_TX_DATA4 <= x"00"; |
end if; |
end process; |
|
MAC_TX_SAMPLE4_CLK <= TX_BYTE_CLK_D when (TX_STATE /= 0) else '0'; |
|
-- signal conditioning for the TX GMII interface |
GMII_TX_GEN: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if (SYNC_RESETRX = '1') then |
MAC_TXD <= (others => '0'); |
MAC_TX_EN <= '0'; |
MAC_TX_ER <= '0'; |
MAC_TX_SAMPLE_CLK <= '0'; |
MAC_TX_DATA4_D <= (others => '0'); |
elsif(TX_BYTE_CLK_D = '1') then |
MAC_TXD <= MAC_TX_DATA4; |
MAC_TX_EN <= TX_EN; |
MAC_TX_ER <= TX_ER; |
MAC_TX_SAMPLE_CLK <= '1'; |
else |
MAC_TX_SAMPLE_CLK <= '0'; |
end if; |
end if; |
end process; |
|
|
-- Tx random backoff ------------------------ |
-- Use LFSR11 as generator of a uniform random distribution of numbers between 0 and 2047 |
Inst_LFSR11C: LFSR11C PORT MAP( |
ASYNC_RESET => '0', |
CLK => RX_CLKG, |
BIT_CLK_REQ => TX_BYTE_CLK, -- keep generating new random number |
SYNC_RESET => SYNC_RESETRX, |
SEED => "00000000001", |
LFSR_BIT => open, |
BIT_CLK_OUT => open, |
SOF_OUT => open, |
LFSR_REG_OUT => RAND |
); |
|
|
|
-- limit the random number range depending on the number of transmission attempts |
-- see 802.3 standard section 4.2.3.2.5 for details. |
RETX_RAND_BKOFF_GEN: process(RAND, RETX_ATTEMPT_COUNTER) |
begin |
case RETX_ATTEMPT_COUNTER is |
when "00000" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0000000001"; -- first attempt: r = 0,1 |
when "00001" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0000000011"; -- second attempt: r = 0-3 |
when "00010" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0000000111"; -- third attempt: r = 0-7 |
when "00011" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0000001111"; -- etc |
when "00100" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0000011111"; |
when "00101" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0000111111"; |
when "00110" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0001111111"; |
when "00111" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0011111111"; |
when "01000" => RETX_RANDOM_BKOFF <= RAND(9 downto 0) and "0111111111"; |
when others => RETX_RANDOM_BKOFF <= RAND(9 downto 0); -- cap range to r = 0-1023 |
end case; |
end process; |
|
|
--// TX 32-BIT CRC COMPUTATION ------------------------------------------------------- |
-- 802.3 section 3.2.9: |
-- protected fields: payload data + padding (excludes preamble and start of frame sequence) |
MAC_TX_DATA3 <= MAC_TX_DATA2 when (TX_STATE = 2) else x"00"; -- padding with zeros |
MAC_TX_SAMPLE3_CLK <= TX_BYTE_CLK_D when ((TX_STATE = 2) or (TX_STATE = 3)) else '0'; |
|
TX_CRC32_RESET <= '1' when (TX_STATE = 1) else '0'; -- reset CRC2 during the packet preamble (covers the re-transmission case) |
|
-- latency 1 RX_CLKG |
TX_CRC32_8B: CRC32_8B PORT MAP( |
SYNC_RESET => TX_CRC32_RESET, |
CLK => RX_CLKG, |
CRC32_IN => TX_CRC32, -- feedback previous iteration |
DATA_IN => MAC_TX_DATA3, |
SAMPLE_CLK_IN => MAC_TX_SAMPLE3_CLK, |
CRC32_OUT => TX_CRC32, |
CRC32_VALID => open |
); |
|
-- flip LSb<->MSb and invert |
TX_CRC32_002: process(TX_CRC32) |
begin |
for I in 0 to 7 loop |
TX_CRC32_FLIPPED_INV(I) <= not TX_CRC32(7 - I); |
TX_CRC32_FLIPPED_INV(I + 8) <= not TX_CRC32(15 - I); |
TX_CRC32_FLIPPED_INV(I + 16) <= not TX_CRC32(23 - I); |
TX_CRC32_FLIPPED_INV(I + 24) <= not TX_CRC32(31 - I); |
end loop; |
end process; |
|
--// MAC RX STATE MACHINE ---------------------------------------------------------- |
-- remember the last rx byte |
RX_DELAY_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if (MAC_RX_SAMPLE_CLK = '1') then |
MAC_RXD_D <= MAC_RXD; |
end if; |
end if; |
end process; |
|
|
-- Rx events ------------------------ |
-- new packet. RX_DV is asserted and detected start of frame delimiter (SFD) |
RX_EVENT1 <= '1' when (MAC_RX_SAMPLE_CLK = '1') and (MAC_RX_DV = '1') and (MAC_RX_ER = '0') |
and (MAC_RXD_D = x"D5") else '0'; |
-- false carrier indication (TODO: what for???) xE for 10/1000, x0E for 1000 Mbps |
--RX_EVENT2 <= '1' when (MAC_RX_SAMPLE_CLK = '1') and (MAC_RX_DV = '0') and (MAC_RX_ER = '1') |
-- and (MAC_RXD(3 downto 0) = x"E") else '0'; |
|
-- end of frame delimiter |
RX_EVENT3 <= '1' when (MAC_RX_SAMPLE_CLK = '1') and (MAC_RX_DV = '0') else |
'0'; |
|
-- valid frame byte (data, padding, crc) |
RX_EVENT4 <= '1' when (MAC_RX_SAMPLE_CLK = '1') and (MAC_RX_DV = '1') and (MAC_RX_ER = '0') else |
'0'; |
|
-- frame complete, all checks complete |
RX_EVENT5 <= MAC_RX_EOF3B_D; |
|
|
|
-- Rx state machine ------------------------ |
RX_BYTE_COUNTER_INC <= RX_BYTE_COUNTER + 1; |
|
RX_STATE_GEN_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if (SYNC_RESETRX = '1') then |
RX_STATE <= 0; |
elsif(RX_STATE = 0) and (RX_EVENT1 = '1') then |
-- RX_DV is asserted and detected start of frame delimiter (SFD) |
-- Note: the preamble could be full, partial or entirely missing. |
RX_STATE <= 1; |
RX_BYTE_COUNTER <= (others => '0'); |
elsif(RX_STATE = 1) and (RX_EVENT3 = '1') then |
-- end of frame delimiter |
RX_STATE <= 2; |
elsif(RX_STATE = 1) and (RX_EVENT4 = '1') then |
-- count bytes within frame |
RX_BYTE_COUNTER <= RX_BYTE_COUNTER_INC; |
-- shift-in the last 6 bytes (efficient when decoding address field or length/type field) |
-- MSB (47 downto 40) is received first. |
LAST6B(47 downto 8) <= LAST6B(39 downto 0); |
LAST6B(7 downto 0) <= MAC_RXD_D; |
elsif(RX_STATE = 2) and (RX_EVENT5 = '1') then |
-- frame complete, all checks complete |
RX_STATE <= 0; |
end if; |
end if; |
end process; |
|
-- Assess whether rx frame is too short (collision) or too long? |
-- ready at RX_STATE 2 |
RX_TOO_SHORT_GEN: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(RX_STATE = 1) and (RX_EVENT3 = '1') then |
-- end of frame delimiter |
if(RX_BYTE_COUNTER_INC(18 downto 6) = 0) then -- < 64 bytes |
-- too short 6+6+2+46+4 = 64 |
RX_TOO_SHORT <= '1'; |
RX_TOO_LONG <= '0'; |
elsif(RX_BYTE_COUNTER_INC(18 downto 11) /= 0) or |
(RX_BYTE_COUNTER_INC(10 downto 0)> 1518) then -- > 1518 bytes |
-- too long. 6+6+2+1500+4 = 1418 |
RX_TOO_SHORT <= '0'; |
RX_TOO_LONG <= '1'; |
else |
RX_TOO_SHORT <= '0'; |
RX_TOO_LONG <= '0'; |
end if; |
end if; |
end if; |
end process; |
|
-- Destination address check |
ADDR_CHECK_GEN: process(RX_CLKG, MAC_RX_CONFIG, MAC_ADDR) |
begin |
if rising_edge(RX_CLKG) then |
if(MAC_RX_CONFIG(0) = '1') then |
-- promiscuous mode. No destination address check |
RX_VALID_ADDR <= '1'; |
elsif(RX_STATE = 1) and (RX_EVENT4 = '1') and (RX_BYTE_COUNTER = 6) then |
-- end of destination address field. Check address |
if(LAST6B = MAC_ADDR) then |
-- destination address matches |
RX_VALID_ADDR <= '1'; |
elsif (LAST6B = x"FFFFFFFFFFFF") and (MAC_RX_CONFIG(1) = '1') then |
-- accepts broadcast packets with the broadcast destination address FF:FF:FF:FF:FF:FF. |
RX_VALID_ADDR <= '1'; |
elsif (LAST6B(42) = '1') and (MAC_RX_CONFIG(2) = '1') then |
-- accept multicast packets with the multicast bit set in the destination address. |
-- '1' in the LSb of the first address byte. |
RX_VALID_ADDR <= '1'; |
else |
RX_VALID_ADDR <= '0'; |
end if; |
end if; |
end if; |
end process; |
|
-- Length/type field check |
LENGTH_CHECK_GEN: process(RX_CLKG, MAC_RX_CONFIG, MAC_ADDR) |
begin |
if rising_edge(RX_CLKG) then |
if(RX_EVENT1 = '1') then |
-- assume type field by default at the start of frame |
RX_LENGTH_TYPEN <= '0'; -- length/type field represents a type. ignore the length value. |
elsif(RX_STATE = 1) and (RX_EVENT4 = '1') and (RX_BYTE_COUNTER = 14) then |
-- end of length/type field |
if(LAST6B(15 downto 11) = 0) and (LAST6B(10 downto 0) <= 1500) then |
-- this field is interpreted as "Length" = client data field size |
-- MSB first (802.3 section 3.2.6) |
RX_LENGTH <= LAST6B(10 downto 0); |
RX_LENGTH_TYPEN <= '1'; -- length/type field represents a length |
else |
RX_LENGTH_TYPEN <= '0'; -- length/type field represents a type. ignore the length value. |
end if; |
end if; |
end if; |
end process; |
|
-- compute the difference between RX_BYTE_COUNTER and RX_LENGTH (meaningless, but help minimize gates) |
RX_DIFF <= RX_BYTE_COUNTER(11 downto 0) - ('0' & RX_LENGTH); |
|
-- Length field consistency with actual rx frame length. Check if the length/type field is 'length' |
RX_LENGTH_ERR_GEN: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(RX_LENGTH_TYPEN = '0') then |
-- type field. No explicit length info. Can't validate actual length. |
RX_LENGTH_ERR <= '0'; |
elsif(MAC_RX_EOF3B = '1') then |
if(RX_LENGTH <= 46) then |
-- short rx frame is padded to the minimum size of 60 bytes + 4 CRC |
if(RX_BYTE_COUNTER = 63) then |
-- correct answer. |
RX_LENGTH_ERR <= '0'; |
else |
-- inconsistency |
RX_LENGTH_ERR <= '1'; |
end if; |
else |
-- normal size frame. no pad. |
if(RX_DIFF = 17) then |
-- correct answer. |
RX_LENGTH_ERR <= '0'; |
else |
-- inconsistency |
RX_LENGTH_ERR <= '1'; |
end if; |
end if; |
end if; |
end if; |
end process; |
|
|
|
--// RX 32-BIT CRC COMPUTATION ------------------------------------------------------- |
-- 802.3 section 3.2.9: |
-- protected fields: payload data + optional pad + CRC (excludes preamble and start of frame sequence) |
MAC_RX_SAMPLE2_CLK <= '1' when (RX_STATE = 1) and (MAC_RX_SAMPLE_CLK = '1') else '0'; |
|
RX_CRC32_RESET <= '1' when (RX_STATE = 0) else '0'; -- reset CRC2 during the packet preamble |
|
-- latency 1 RX_CLKG |
RX_CRC32_8B: CRC32_8B PORT MAP( |
SYNC_RESET => RX_CRC32_RESET, |
CLK => RX_CLKG, |
CRC32_IN => RX_CRC32, -- feedback previous iteration |
DATA_IN => MAC_RXD_D, |
SAMPLE_CLK_IN => MAC_RX_SAMPLE2_CLK, |
CRC32_OUT => RX_CRC32, |
CRC32_VALID => RX_CRC32_VALID |
); |
|
-- assess whether the frame check sequence is valid |
-- ready one RX_CLKG after the start of RX_STATE 2 |
RX_BAD_CRC_GEN: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if(RX_STATE = 2) then |
-- end of frame delimiter |
RX_BAD_CRC <= not RX_CRC32_VALID; |
end if; |
end if; |
end process; |
|
--// PARSE RX DATA ------------------------------------------------------------------- |
-- Delay data by 1 byte (otherwise we will only know about EOF AFTER the last byte is received) |
MAC_RXD3 <= MAC_RXD_D; |
|
-- SOF |
--MAC_RX_SOF3 <= MAC_RX_SAMPLE_CLK when (RX_STATE = 1) and (RX_BYTE_COUNTER = 0) else '0'; |
|
-- EOF based on the length field (does not include pad nor CRC). Meaningless when the type/length field |
-- is used as type. |
MAC_RX_EOF3A <= '1' when (RX_STATE = 1) and (RX_EVENT4 = '1') and (RX_DIFF = 13) else '0'; |
|
-- EOF based on the RX_DV deassertion. |
MAC_RX_EOF3B <= '1' when (RX_STATE = 1) and (RX_EVENT3 = '1') else '0'; |
|
MAC_RX_EOF3 <= MAC_RX_EOF3B when (RX_LENGTH_TYPEN = '0') else MAC_RX_EOF3A; |
MAC_RX_SAMPLE3_CLK <= MAC_RX_SAMPLE_CLK and RX_FRAME_EN3; |
|
RX_FILTEROUT_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
if (SYNC_RESETRX = '1') then |
RX_FRAME_EN3 <= '0'; |
elsif(RX_STATE = 0) and (RX_EVENT1 = '1') then |
RX_FRAME_EN3 <= '1'; |
elsif(MAC_RX_EOF3 = '1') then |
RX_FRAME_EN3 <= '0'; |
end if; |
end if; |
end process; |
|
--// VALID RX FRAME? ---------------------------------------------------------- |
-- Is the rx frame valid? If so, confirm the wptr location. |
|
MAC_RX_VALID_001: process(RX_CLKG) |
begin |
if rising_edge(RX_CLKG) then |
-- wait one more CLK period until all validity checks are complete |
MAC_RX_EOF3B_D <= MAC_RX_EOF3B; |
|
if(SYNC_RESETRX = '1') then |
MAC_RX_WPTR_CONFIRMED <= (others => '0'); |
else |
if(RX_EVENT5 = '1') then |
-- frame complete, all checks complete |
if(RX_CRC32_VALID = '0') then |
-- BAD_CRC |
-- TODO error counter |
elsif(RX_TOO_SHORT = '1') then |
-- frame is too short (<64B) |
-- TODO error counter |
elsif(RX_TOO_LONG = '1') then |
-- frame is too long (>1518B) |
-- TODO error counter |
elsif(RX_VALID_ADDR = '0') then |
-- address does not match (and promiscuous mode is off) |
-- TODO counter |
elsif(RX_LENGTH_ERR = '1') then |
-- length field is inconsistent with actual rx frame length |
-- TODO counter |
else |
-- passed all checks |
-- update confirmed value for MAC_RX_WPTR |
if(MAC_RX_CONFIG(3) = '1') then |
-- filter out 4-byte CRC-32 |
MAC_RX_WPTR_CONFIRMED <= MAC_RX_WPTR - 4; |
else |
-- include 4-byte CRC-32 |
MAC_RX_WPTR_CONFIRMED <= MAC_RX_WPTR; |
end if; |
end if; |
|
end if; |
end if; |
end if; |
end process; |
|
|
|
--// RX INPUT ELASTIC BUFFER ---------------------------------------------------------- |
-- The purpose of the elastic buffer is two-fold: |
-- (a) a transition between the RX_CLKG synchronous PHY side and the CLK-synchronous user side. |
-- (b) storage for receive packets, to absorb traffic peaks, minimize the number of |
-- UDP packets lost at high throughput. |
-- The rx elastic buffer is 16Kbits, large enough for a complete maximum size (14addr+1500data+4FCS = 1518B) frame. |
|
-- write pointer management |
MAC_RX_WPTR_001: process(ASYNC_RESET, RX_CLKG) |
begin |
if(ASYNC_RESET = '1') then |
MAC_RX_WPTR <= (others => '0'); |
MAC_RX_WPTR_D <= (others => '0'); |
elsif rising_edge(RX_CLKG) then |
RX_COUNTER8 <= RX_COUNTER8 + 1; |
|
if(SYNC_RESETRX = '1') then |
MAC_RX_WPTR <= (others => '0'); |
elsif(RX_STATE = 0) then |
-- re-position the write pointer (same or rewind if previous frame was invalid |
MAC_RX_WPTR <= MAC_RX_WPTR_CONFIRMED; |
elsif(MAC_RX_SAMPLE3_CLK = '1') then |
MAC_RX_WPTR <= MAC_RX_WPTR + 1; |
end if; |
|
-- update WPTR_D once every 8 clocks. |
if(SYNC_RESETRX = '1') then |
MAC_RX_WPTR_D <= (others => '0'); |
elsif(RX_COUNTER8 = 7) then |
MAC_RX_WPTR_D <= MAC_RX_WPTR_CONFIRMED; |
end if; |
|
-- allow WPTR reclocking with another clock, as long as it is away from the transition area |
if(RX_COUNTER8 < 6) then |
MAC_RX_WPTR_STABLE <= '1'; |
else |
MAC_RX_WPTR_STABLE <= '0'; |
end if; |
|
|
end if; |
end process; |
|
|
|
MAC_RX_DIPA(0) <= MAC_RX_EOF3; -- indicates last byte in the rx packet |
|
-- No need for initialization |
RAMB16_002: RAMB16_S9_S9 |
port map( |
DIA => MAC_RXD3, |
DIB => x"00", |
DIPA => MAC_RX_DIPA(0 downto 0), |
DIPB => "0", |
DOPA => open, |
DOPB => MAC_RX_DOPB(0 downto 0), |
ENA => '1', |
ENB => '1', |
WEA => MAC_RX_SAMPLE3_CLK, |
WEB => '0', |
SSRA => '0', |
SSRB => '0', |
CLKA => RX_CLKG, |
CLKB => CLK, |
ADDRA => MAC_RX_WPTR, |
ADDRB => MAC_RX_RPTR, |
DOA => open, |
DOB => MAC_RXD4 |
); |
|
|
-- CLK zone. Reclock WPTR |
MAC_RX_WPTR_002: process(ASYNC_RESET, CLK) |
begin |
if(ASYNC_RESET = '1') then |
MAC_RX_WPTR_D2 <= (others => '0'); |
MAC_RX_WPTR_D3 <= (others => '0'); |
MAC_RX_WPTR_STABLE_D <= '0'; |
elsif rising_edge(CLK) then |
MAC_RX_WPTR_STABLE_D <= MAC_RX_WPTR_STABLE; |
MAC_RX_WPTR_D2 <= MAC_RX_WPTR_D; |
|
if(MAC_RX_WPTR_STABLE_D = '1') then |
-- WPTR is stable. OK to resample with the RX_CLKG clock. |
MAC_RX_WPTR_D3 <= MAC_RX_WPTR_D2; |
end if; |
end if; |
end process; |
|
MAC_RX_BUF_SIZE <= MAC_RX_WPTR_D3 + not(MAC_RX_RPTR); |
-- occupied tx buffer size |
|
-- manage read pointer |
MAC_RX_RPTR_001: process(ASYNC_RESET, CLK) |
begin |
if(ASYNC_RESET = '1') then |
MAC_RX_RPTR <= (others => '1'); |
elsif rising_edge(CLK) then |
MAC_RX_SAMPLE4_CLK <= MAC_RX_SAMPLE4_CLK_E; -- it takes one CLK to read data from the RAMB |
|
if(SYNC_RESET = '1') then |
MAC_RX_RPTR <= (others => '1'); |
MAC_RX_SAMPLE4_CLK_E <= '0'; |
MAC_RX_SAMPLE4_CLK <= '0'; |
elsif(MAC_RX_CTS = '1') and (MAC_RX_BUF_SIZE /= 0) then |
-- user requests data and the buffer is not empty |
MAC_RX_RPTR <= MAC_RX_RPTR + 1; |
MAC_RX_SAMPLE4_CLK_E <= '1'; |
else |
MAC_RX_SAMPLE4_CLK_E <= '0'; |
end if; |
end if; |
end process; |
|
-- reconstruct an EOF aligned with the last output byte |
EOF_GEN_001: process(ASYNC_RESET, CLK) |
begin |
if(ASYNC_RESET = '1') then |
MAC_RX_EOF4 <= '0'; |
elsif rising_edge(CLK) then |
if(SYNC_RESET = '1') then |
MAC_RX_EOF4 <= '0'; |
elsif(MAC_RX_SAMPLE4_CLK_E = '1') and (MAC_RX_BUF_SIZE = 0)then |
MAC_RX_EOF4 <= '1'; |
else |
MAC_RX_EOF4 <= '0'; |
end if; |
end if; |
end process; |
-- alternate code (does not work when CRC32 is stripped) |
-- MAC_RX_EOF4 <= MAC_RX_DOPB(0) and MAC_RX_SAMPLE4_CLK; -- reconstruct EOF pulse (1 CLK wide) |
|
-- reconstruct a SOF |
SOF_GEN_001: process(ASYNC_RESET, CLK) |
begin |
if(ASYNC_RESET = '1') then |
MAC_RX_EOF4_FLAG <= '1'; |
elsif rising_edge(CLK) then |
if(SYNC_RESET = '1') then |
MAC_RX_EOF4_FLAG <= '1'; |
elsif(MAC_RX_EOF4 = '1') then |
MAC_RX_EOF4_FLAG <= '1'; |
elsif(MAC_RX_SAMPLE4_CLK = '1') then |
MAC_RX_EOF4_FLAG <= '0'; |
end if; |
end if; |
end process; |
|
-- output to user |
MAC_RX_DATA <= MAC_RXD4; |
MAC_RX_DATA_VALID <= MAC_RX_SAMPLE4_CLK; |
MAC_RX_EOF <= MAC_RX_EOF4; |
MAC_RX_SOF <= MAC_RX_EOF4_FLAG and MAC_RX_SAMPLE4_CLK; |
|
end Behavioral; |
|
/gigabit_udp_mac/trunk/MAC/MII_MI _V6.vhd
0,0 → 1,225
------------------------------------------------------------- |
-- Filename: MII_MI_V5.VHD |
-- Version: 1 |
-- Date last modified: 1-30-11 |
-- Inheritance: MII_MI.VHD rev1 1-30-11 |
-- |
-- description: MII management interface. |
-- Writes and read registers to/from the PHY IC through |
-- the MDC & MDIO serial interface. |
-- The MCLK clock speed is set as a constant within (integer division of the reference clock CLK). |
-- USAGE: adjust the constant MCLK_COUNTER_DIV within to meet the MDC/MDIO timing requirements (see PHY specs). |
-- Virtex-5 use. |
--------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity MII_MI_V6 is |
generic ( |
PHY_ADDR: std_logic_vector(4 downto 0) |
-- PHY Address |
); |
Port ( |
--// CLK, RESET |
SYNC_RESET: in std_logic; |
CLK: in std_logic; |
|
MI_REGAD: in std_logic_vector(4 downto 0); |
-- 32 register address space for the PHY (ieee 802.3) |
-- 0 - 15 are standard PHY registers as per IEEE specification. |
-- 16 - 31 are vendor-specific registers |
MI_TX_DATA: in std_logic_vector(15 downto 0); |
MI_RX_DATA: out std_logic_vector(15 downto 0); |
MI_READ_START: in std_logic; |
-- 1 CLK wide pulse to start read transaction |
-- will be ignored if the previous transaction is yet to be completed. |
-- For reliable operation, the user must check MI_TRANSACTION_COMPLETE first. |
MI_WRITE_START: in std_logic; |
-- 1 CLK wide pulse to start write transaction |
-- will be ignored if the previous transaction is yet to be completed. |
-- For reliable operation, the user must check MI_TRANSACTION_COMPLETE first. |
|
MI_TRANSACTION_COMPLETE: out std_logic; |
-- '1' when transaction is complete |
|
--// serial interface. connect to PHY |
MCLK: out std_logic; |
MDI: in std_logic; -- MDIO input |
MDO: out std_logic; -- MDIO output |
MDT: out std_logic -- MDIO tri-state |
|
); |
end entity; |
|
architecture Behavioral of MII_MI_V6 is |
-------------------------------------------------------- |
-- COMPONENTS |
-------------------------------------------------------- |
-------------------------------------------------------- |
-- SIGNALS |
-------------------------------------------------------- |
signal STATE: std_logic_vector(7 downto 0) := x"00"; -- 0 is idle |
signal TXRX_FRAME: std_logic_vector(63 downto 0); --32-bit idle sequence + 32-bit MI serial port frame + 2 end bit |
signal MCLK_LOCAL: std_logic := '0'; |
signal MCLK_LOCAL_D: std_logic := '0'; |
signal MDOE: std_logic := '1'; |
signal MDI_DATA: std_logic := '0'; |
signal MDI_SAMPLE_CLK: std_logic := '0'; |
constant MCLK_COUNTER_DIV: std_logic_vector(7 downto 0) := x"17"; |
-- divide CLK by this 2*(value + 1) to generate a slower MCLK |
-- MCLK period (typ): 400 ns [Micrel KSZ9021] |
-- Example: 120 MHz clock, 400ns MCLK period => MCLK_COUNTER_DIV = 23 |
signal MCLK_COUNTER: std_logic_vector(7 downto 0) := x"00"; |
signal MI_SAMPLE_REQ: std_logic; |
|
-------------------------------------------------------- |
-- IMPLEMENTATION |
-------------------------------------------------------- |
begin |
|
------------------------------------------------------ |
-- MCLK GENERATION |
------------------------------------------------------ |
-- Divide CLK by MCLK_COUNTER_DIV |
MCLK_GEN_001: process(CLK) |
begin |
if rising_edge(CLK) then |
if(SYNC_RESET = '1') then |
MCLK_COUNTER <= (others => '0'); |
MI_SAMPLE_REQ <= '0'; |
elsif(STATE = 0) then |
-- idle. awaiting a start of transaction. |
MI_SAMPLE_REQ <= '0'; |
if(MI_WRITE_START = '1') or (MI_READ_START = '1') then |
-- get started. reset MCLK phase. |
MCLK_COUNTER <= (others => '0'); |
end if; |
else |
-- read/write transaction in progress |
if(MCLK_COUNTER = MCLK_COUNTER_DIV) then |
-- next sample |
MI_SAMPLE_REQ <= '1'; |
MCLK_COUNTER <= (others => '0'); |
else |
MI_SAMPLE_REQ <= '0'; |
MCLK_COUNTER <= MCLK_COUNTER + 1; |
end if; |
end if; |
end if; |
end process; |
|
------------------------------------------------------ |
-- OUTPUT TO PHY |
------------------------------------------------------ |
|
STATE_GEN_001: process(CLK) |
begin |
if rising_edge(CLK) then |
if(SYNC_RESET = '1') then |
STATE <= (others => '0'); |
MCLK_LOCAL <= '0'; |
MDOE <= '0'; |
elsif(STATE = 0) then |
if (MI_WRITE_START = '1') then |
-- was idle. start of write transaction. start counting |
STATE <= x"01"; |
MCLK_LOCAL <= '0'; |
MDOE <= '1'; |
elsif (MI_READ_START = '1') then |
-- was idle. start of read transaction. start counting |
STATE <= x"81"; |
MCLK_LOCAL <= '0'; |
MDOE <= '1'; |
end if; |
elsif (MI_SAMPLE_REQ = '1') then |
if (STATE = 128) then |
-- write transaction complete. set output enable to high impedance |
STATE <= x"00"; |
MCLK_LOCAL <= '0'; |
MDOE <= '0'; |
elsif (STATE = 220) then |
-- read transaction: finished writing addresses. switch to read mode |
STATE <= STATE + 1; |
MCLK_LOCAL <= not MCLK_LOCAL; |
MDOE <= '0'; |
elsif (STATE = 255) then |
-- read transaction complete. reset state. |
STATE <= x"00"; |
MCLK_LOCAL <= '0'; |
MI_RX_DATA <= TXRX_FRAME(15 downto 0); -- complete word read from PHY |
else |
STATE <= STATE + 1; |
MCLK_LOCAL <= not MCLK_LOCAL; |
end if; |
end if; |
end if; |
end process; |
|
-- immediate turn off the 'available' message as soon as a new transaction is triggered. |
MI_TRANSACTION_COMPLETE <= '0' when (STATE > 0) else |
'0' when (MI_WRITE_START = '1') else |
'0' when (MI_READ_START = '1') else |
'1'; |
|
-- send MCLK to output |
MCLK <= MCLK_LOCAL; |
|
TXRX_FRAME_GEN: process(CLK) |
begin |
if rising_edge(CLK) then |
if(SYNC_RESET = '1') then |
TXRX_FRAME <= (others => '0'); |
elsif(MI_WRITE_START = '1') then |
-- start of write transaction. |
-- Note: transmission sequence starts at bit 63 |
TXRX_FRAME(63 downto 32) <= x"FFFFFFFF"; -- preamble: idle sequence 32 '1's |
TXRX_FRAME(31 downto 23) <= "0101" & PHY_ADDR; |
TXRX_FRAME(22 downto 18) <= MI_REGAD; |
TXRX_FRAME(17 downto 16) <= "10"; |
TXRX_FRAME(15 downto 0) <= MI_TX_DATA; |
elsif(MI_READ_START = '1') then |
-- start of read transaction. |
-- Note: transmission sequence starts at bit 63 |
TXRX_FRAME(63 downto 32) <= x"FFFFFFFF"; -- preamble: idle sequence 32 '1's |
TXRX_FRAME(31 downto 23) <= "0110" & PHY_ADDR; |
TXRX_FRAME(22 downto 18) <= MI_REGAD; |
elsif(MI_SAMPLE_REQ = '1') and (STATE /= 0) and (STATE(0) = '0') and (MDOE = '1') then |
-- shift TXRX_FRAME 1 bit left every two clocks |
TXRX_FRAME(63 downto 1) <= TXRX_FRAME(62 downto 0); |
elsif(MDI_SAMPLE_CLK = '1') and (STATE /= 0) and (STATE(0) = '1') and (MDOE = '0') then |
-- shift MDIO into TXRX_FRAME 1 bit left every two clocks (read at the falling edge of MCLK) |
-- do this 16 times to collect the 16-bit response from the PHY. |
TXRX_FRAME(63 downto 1) <= TXRX_FRAME(62 downto 0); |
TXRX_FRAME(0) <= MDI_DATA; |
end if; |
end if; |
end process; |
|
-- select output bit. |
MDO <= TXRX_FRAME(63); |
MDT <= not MDOE; |
|
------------------------------------------------------ |
-- INPUT FROM PHY |
------------------------------------------------------ |
|
|
-- reclock MDI input at the falling edge of MCLK |
RX_RECLOCK_001: process(CLK) |
begin |
if rising_edge(CLK) then |
MCLK_LOCAL_D <= MCLK_LOCAL; |
|
if(MCLK_LOCAL = '0') and (MCLK_LOCAL_D = '1') then |
MDI_DATA <= MDI; |
MDI_SAMPLE_CLK <= '1'; |
else |
MDI_SAMPLE_CLK <= '0'; |
end if; |
end if; |
end process; |
|
|
end Behavioral; |
/gigabit_udp_mac/trunk/MAC/PHY_CONFIG_V6.vhd
0,0 → 1,276
------------------------------------------------------------- |
-- Filename: PHY_CONFIG_V5.VHD |
-- Version: 2 |
-- Date last modified: 2-4-11 |
-- Inheritance: PHY_CONFIG.VHD, rev2 2-4-11 |
-- |
-- description: Configures a PHY through a MDIO interface. |
---------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity PHY_CONFIG is |
generic ( |
PHY_ADDR: std_logic_vector(4 downto 0) -- PHY Address |
); |
Port ( |
--// CLK, RESET |
SYNC_RESET: in std_logic; |
CLK: in std_logic; |
|
--// CONTROLS |
CONFIG_CHANGE: in std_logic; |
-- 1 CLK-wide pulse to activate any configuration change below. |
-- Not needed if the default values are acceptable. |
PHY_RESET: in std_logic; |
-- 1 = PHY software reset, 0 = no reset |
SPEED: in std_logic_vector(1 downto 0); |
-- 00 = force 10 Mbps |
-- 01 = force 100 Mbps |
-- 10 = force 1000 Mbps |
-- 11 = auto-negotiation (default) |
DUPLEX: in std_logic; |
-- 1 = full-duplex (default), 0 = half-duplex |
TEST_MODE: in std_logic_vector(1 downto 0); |
-- 00 = normal mode (default) |
-- 01 = loopback mode |
-- 10 = remote loopback |
-- 11 = led test mode |
POWER_DOWN: in std_logic; |
-- software power down mode. 1 = enabled, 0 = disabled (default). |
CLK_SKEW: in std_logic_vector(15 downto 0); |
-- Register 260 RGMII clock and control pad skew |
|
--// MONITORING |
SREG_READ_START: in std_logic; |
-- 1 CLK wide pulse to start read transaction |
-- will be ignored if the previous transaction is yet to be completed. |
SREG_REGAD: in std_logic_vector(8 downto 0); |
-- 32 register address space for the PHY |
-- 0 - 15 are standard PHY registers as per IEEE specification. |
-- 16 - 31 are vendor-specific registers |
-- 256+ are extended registers |
SREG_DATA : OUT std_logic_vector(15 downto 0); |
-- 16-bit status register. Read when SREG_SAMPLE_CLK = '1' |
SREG_SAMPLE_CLK: out std_logic; |
|
--// BASIC STATUS REPORT (status register 1) |
LINK_STATUS: out std_logic; |
-- 0 = link down, 1 = link up |
--// serial interface. connect to PHY |
MCLK: out std_logic; |
MDI: in std_logic; -- MDIO input |
MDO: out std_logic; -- MDIO output |
MDT: out std_logic -- MDIO tri-state |
|
); |
end entity; |
|
architecture Behavioral of PHY_CONFIG is |
-------------------------------------------------------- |
-- COMPONENTS |
-------------------------------------------------------- |
COMPONENT MII_MI_V6 |
GENERIC ( |
PHY_ADDR: std_logic_vector(4 downto 0) |
); |
PORT( |
SYNC_RESET : IN std_logic; |
CLK : IN std_logic; |
MI_REGAD : IN std_logic_vector(4 downto 0); |
MI_TX_DATA : IN std_logic_vector(15 downto 0); |
MI_READ_START : IN std_logic; |
MI_WRITE_START : IN std_logic; |
MDI: in std_logic; -- MDIO input |
MDO: out std_logic; -- MDIO output |
MDT: out std_logic; -- MDIO tri-state |
MI_RX_DATA : OUT std_logic_vector(15 downto 0); |
MI_TRANSACTION_COMPLETE : OUT std_logic; |
MCLK : OUT std_logic |
); |
END COMPONENT; |
-------------------------------------------------------- |
-- SIGNALS |
-------------------------------------------------------- |
signal STATE: std_logic_vector(3 downto 0) := "0000"; |
signal MI_WRITE_START: std_logic := '0'; |
signal MI_REGAD: std_logic_vector(4 downto 0) := "00000"; |
signal MI_TX_DATA: std_logic_vector(15 downto 0); |
signal MI_READ_START: std_logic := '0'; |
signal MI_RX_DATA: std_logic_vector(15 downto 0); |
signal MI_TRANSACTION_COMPLETE: std_logic; |
signal PHY_RESET_D: std_logic; |
signal SPEED_D: std_logic_vector(1 downto 0); |
signal LOOPBACK_MODE: std_logic; |
signal AUTONEG: std_logic; |
signal POWER_DOWN_D: std_logic; |
signal DUPLEX_D: std_logic; |
signal REMOTE_LOOPBACK: std_logic; |
signal LED_TEST_MODE: std_logic; |
|
constant RGMII_INBAND_STATUS_EN: std_logic := '1'; -- enable in-band status reporting in RGMII |
signal SREG_SAMPLE_CLK_local: std_logic := '0'; |
-------------------------------------------------------- |
-- IMPLEMENTATION |
-------------------------------------------------------- |
begin |
|
---- save the configuration so that it does not change while the configuration is in progress |
RECLOCK_001: process(CLK) |
begin |
if rising_edge(CLK) then |
if(STATE = 0) and (CONFIG_CHANGE = '1') then |
PHY_RESET_D <= PHY_RESET; |
SPEED_D <= SPEED; |
DUPLEX_D <= DUPLEX; |
POWER_DOWN_D <= POWER_DOWN; |
|
if(SPEED = "11") then |
AUTONEG <= '1'; |
else |
AUTONEG <= '0'; |
end if; |
|
case TEST_MODE is |
when "00" => |
LOOPBACK_MODE <= '0'; |
REMOTE_LOOPBACK <= '0'; |
LED_TEST_MODE <= '0'; |
when "01" => |
LOOPBACK_MODE <= '1'; |
REMOTE_LOOPBACK <= '0'; |
LED_TEST_MODE <= '0'; |
when "10" => |
LOOPBACK_MODE <= '0'; |
REMOTE_LOOPBACK <= '1'; |
LED_TEST_MODE <= '0'; |
when others => |
LOOPBACK_MODE <= '0'; |
REMOTE_LOOPBACK <= '0'; |
LED_TEST_MODE <= '1'; |
end case; |
|
end if; |
end if; |
end process; |
-- state machine |
STATE_GEN: process(CLK) |
begin |
if rising_edge(CLK) then |
if(SYNC_RESET = '1') then |
STATE <= (others => '0'); |
MI_WRITE_START <= '0'; |
MI_READ_START <= '0'; |
|
-- WRITE ALL CONFIGURATION REGISTERS |
elsif(STATE = 0) and (CONFIG_CHANGE = '1') then |
-- triggers a PHY reconfiguration. await PHY MDIO availability |
STATE <= STATE + 1; |
|
elsif(STATE = 1) and (MI_TRANSACTION_COMPLETE = '1') then |
-- PHY is ready for next transaction. |
-- Register 0: basic control (applicable to all: GMII, MII, RGMII) |
STATE <= STATE + 1; |
MI_REGAD <= "00000"; |
MI_TX_DATA(15 downto 8) <= PHY_RESET_D & LOOPBACK_MODE & SPEED_D(0) & AUTONEG & POWER_DOWN_D & "00" & DUPLEX_D; |
MI_TX_DATA(7 downto 0) <= "0" & SPEED_D(1) & "000000"; |
MI_WRITE_START <= '1'; |
|
-- tested for Micrel KSZ90212RN ------- |
-- adjust as needed depending on the PHY (the extended registers vary depending on the manufacturer/model). |
elsif(STATE = 2) and (MI_TRANSACTION_COMPLETE = '1') then |
STATE <= (others => '0'); |
-- READ ONE STATUS REGISTER |
elsif(STATE = 0) and (SREG_READ_START = '1') and (SREG_REGAD(8) = '0') then |
-- triggers a PHY status read. await PHY MDIO availability |
STATE <= "1000"; |
elsif(STATE = 8) and (MI_TRANSACTION_COMPLETE = '1') and (SREG_REGAD(8) = '0') then |
-- PHY is ready for next transaction. |
STATE <= STATE + 1; |
MI_REGAD <= SREG_REGAD(4 downto 0); |
MI_READ_START <= '1'; |
elsif(STATE = 9) and (MI_TRANSACTION_COMPLETE = '1') then |
-- we are done reading a status register! Going back to idle. |
STATE <= (others => '0'); |
SREG_SAMPLE_CLK_local <= '1'; |
|
|
-- READ ONE EXTENDED REGISTER |
elsif(STATE = 0) and (SREG_READ_START = '1') and (SREG_REGAD(8) = '1') then |
-- Extended register (1/2) |
STATE <= "1000"; |
MI_REGAD <= "01011"; |
MI_TX_DATA <= "0000000" & SREG_REGAD; -- read extended register |
MI_WRITE_START <= '1'; |
elsif(STATE = 8) and (MI_TRANSACTION_COMPLETE = '1') and (SREG_REGAD(8) = '1') then |
-- triggers a PHY status read. await PHY MDIO availability |
STATE <= STATE + 1; |
MI_REGAD <= "01101"; |
MI_READ_START <= '1'; |
elsif(STATE = 9) and (MI_TRANSACTION_COMPLETE = '1') then |
-- we are done reading a status register! Going back to idle. |
STATE <= (others => '0'); |
SREG_SAMPLE_CLK_local <= '1'; |
|
-- PERIODIC READ BASIC STATUS: LINK |
elsif(STATE = 0) and (MI_TRANSACTION_COMPLETE = '1') then |
-- Register 1: basic status (applicable to all: GMII, MII, RGMII) |
STATE <= "1010"; |
MI_REGAD <= "10001"; |
MI_READ_START <= '1'; |
elsif(STATE = 10) and (MI_TRANSACTION_COMPLETE = '1') then |
-- we are done reading a status register! Going back to idle. |
STATE <= (others => '0'); |
-- LINK_STATUS <= MI_RX_DATA(2); commented by KED |
|
else |
MI_WRITE_START <= '0'; |
MI_READ_START <= '0'; |
SREG_SAMPLE_CLK_local <= '0'; |
|
end if; |
end if; |
end process; |
|
LINK_STATUS <= '1';--; Added by KED |
|
-- latch status register |
SREGOUT_001: process(CLK) |
begin |
if rising_edge(CLK) then |
SREG_SAMPLE_CLK <= SREG_SAMPLE_CLK_local; |
|
if(SREG_SAMPLE_CLK_local = '1') then |
SREG_DATA <= MI_RX_DATA; |
end if; |
end if; |
end process; |
|
Inst_MII_MI: MII_MI_V6 |
GENERIC MAP( |
PHY_ADDR => PHY_ADDR |
) |
PORT MAP( |
SYNC_RESET => SYNC_RESET, |
CLK => CLK, |
MI_REGAD => MI_REGAD, |
MI_TX_DATA => MI_TX_DATA, |
MI_RX_DATA => MI_RX_DATA, |
MI_READ_START => MI_READ_START, |
MI_WRITE_START => MI_WRITE_START, |
MI_TRANSACTION_COMPLETE => MI_TRANSACTION_COMPLETE, |
MCLK => MCLK, |
MDI => MDI, |
MDO => MDO, |
MDT => MDT |
); |
|
end Behavioral; |
|
/gigabit_udp_mac/trunk/MAC/RESET_TIMER.vhd
0,0 → 1,116
------------------------------------------------------------- |
-- Filename: RESET_TIMER.VHD |
-- Version: 1 |
-- Date last modified: 1-28-11 |
-- Inheritance: n/a |
-- |
-- description: |
-- 1. Generate a long (>10ms) negative RESET_N pulse at power up or after a RESET_START trigger. |
-- The timer to define the length of the RESET_N pulse is set at the time of HDL synthesis |
-- (see the constants within) |
-- 2. Generate a short INITIAL_CONFIG_PULSE, 50ms after the RESET_N deassertion |
-- to start configuring the PHY over the MDIO interface. |
-- Beware: as the PHY may turn off its 125 MHz while RESET_N is being asserted, one should |
-- not rely on the availability of this 125 MHz clock to generate RESET_N (circular logic). |
--------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity RESET_TIMER is |
generic ( |
CLK_FREQUENCY: integer := 120 |
-- CLK frequency in MHz. Needed to compute actual delays. |
); |
Port ( |
--// CLK |
CLK: in std_logic; |
-- GLOBAL CLOCK, always available, even during PHY reset. Used as time reference. |
|
RESET_START: in std_logic; |
-- 1-CLK pulse trigger to reset PHY IC and set the strapping options. |
-- This trigger is optional. This component will automatically generate a RESET_N |
-- long negative pulse at power up. Synchronous with CLK. |
RESET_COMPLETE: out std_logic; |
-- '1' to indicate the end of this reset transaction. '1' while transaction is in progress. |
-- synchronous with CLK |
|
--// OUTPUTS |
INITIAL_CONFIG_PULSE: out std_logic; |
-- 1-clk pulse to trigger the first-time PHY configuration over the MDIO interface. |
-- synchronous with CLK |
|
RESET_N: out std_logic |
-- PHY INTERFACE. long negative pulse at power up or after a RESET_START. |
-- hardware pin configurations are strapped-in at the de-assertion (rising edge) |
-- of RESET_N. > 10ms long. |
-- synchronous with CLK |
|
|
); |
end entity; |
|
architecture Behavioral of RESET_TIMER is |
-------------------------------------------------------- |
-- SIGNALS |
-------------------------------------------------------- |
signal STATE: integer range 0 to 3 := 0; |
signal TIMER1: std_logic_vector(23 downto 0) := x"000000"; |
constant TIMER1_VAL: integer := (CLK_FREQUENCY * 10000) -1; |
-- the objective is to generate a 10ms min RESET_N pulse. Adjust TIMER1_VAL as needed. |
-- Example: CLK = 125 MHz clock. The resulting TIMER1_VAL is 10E-2 * 125E6 -1 |
signal TIMER2: std_logic_vector(23 downto 0) := x"000000"; |
constant TIMER2_VAL: integer := (CLK_FREQUENCY * 50000) -1; |
-- Example: 100uS at 125MHz = 12499 |
|
signal RESET_STARTED: std_logic := '0'; |
signal POWER_UP: std_logic := '0'; |
|
|
-------------------------------------------------------- |
-- IMPLEMENTATION |
-------------------------------------------------------- |
begin |
|
RESET_N_GEN_001: process(CLK) |
begin |
if rising_edge(CLK) then |
if(RESET_START = '1') or (POWER_UP = '0') then |
-- initialize timer upon powerup or RESET_START |
POWER_UP <= '1'; |
INITIAL_CONFIG_PULSE <= '0'; |
TIMER1 <= (others => '0'); |
TIMER2 <= (others => '0'); |
STATE <= 1; |
elsif(STATE = 1) then |
if (TIMER1 < TIMER1_VAL) then |
-- count until TIMER1_VAL (timer expired) |
TIMER1 <= TIMER1 + 1; |
else |
-- timer1 expired |
STATE <= 2; |
end if; |
elsif(STATE = 2) then |
if (TIMER2 < TIMER2_VAL) then |
-- count until TIMER2_VAL (timer expired) |
TIMER2 <= TIMER2 + 1; |
else |
-- timer2 expired |
STATE <= 3; |
INITIAL_CONFIG_PULSE <= '1'; |
end if; |
elsif(STATE = 3) then |
INITIAL_CONFIG_PULSE <= '0'; |
end if; |
end if; |
end process; |
|
RESET_COMPLETE <= '1' when (STATE = 3) else '0'; |
|
|
--// OUTPUTS ---------------------- |
RESET_N <= '0' when (STATE = 0) or (STATE = 1) else '1'; -- active low reset |
|
end Behavioral; |
|
/gigabit_udp_mac/trunk/MAC/crc32_8b.vhd
0,0 → 1,220
------------------------------------------------------------- |
-- Filename: CRC32_8b.VHD |
-- Version: 1 |
-- Date last modified: 2-20-04 |
-- Inheritance: CRC16.VHD, 2-20-04 |
-- |
-- description: CRC32 verification for incoming data packets. |
-- + CRC32 generation for outgoing data packets. |
-- Data is entered one byte at a time. |
-- The CRC is computed iteratively. The Initial CRC32 value for the first message |
-- byte is all 1's. The final CRC32 value when the message is error-free is the residue below. |
-- Generator polynomial: x^32 + x^26 + x^23+ x^22+ x^16+ x^12+ x^11+ x^10+ x^8+ x^7+ x^5+ x^4+ x^2+ x + 1 |
-- as per 802.3 standard. |
-- The residue = 0xC704DD7B |
-- |
-- Validated by comparison with outputlogic.com |
--------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity CRC32_8B is |
port ( |
--// Clocks Resets |
SYNC_RESET: in std_logic; |
CLK: in std_logic; -- reference clock |
|
--// Inputs |
CRC32_IN: in std_logic_vector(31 downto 0); |
-- Initialize to all 1's for the first byte in the data packet |
-- (or use the SYNC_RESET PRIOR to the first input byte). |
-- For subsequent bytes use the previous CRC32_OUT value, as the |
-- CRC32 computation is iterative, byte by byte. |
DATA_IN: in std_logic_vector(7 downto 0); |
-- message from which the CRC32 is computed and/or checked. |
-- Entered byte by byte. |
SAMPLE_CLK_IN: in std_logic; |
-- 1 CLK wide pulse to indicate that DATA_IN and CRC32_IN are ready to be |
-- processed. |
|
--// Outputs |
CRC32_OUT: out std_logic_vector(31 downto 0); |
-- Computed CRC32. |
-- Latency: 1 CLK after SAMPLE_CLK_IN. |
-- If all bits are received without error, the 32-bit residual at |
-- the receiver will be 0. |
CRC32_VALID: out std_logic |
-- '1' when computed CRC32 = 0. |
-- valid only once the entire data packet is read. |
-- Latency: 1 CLK after SAMPLE_CLK_IN. |
-- Stays until start (first byte) of next message. |
); |
end entity; |
|
architecture behavioral of CRC32_8B is |
-------------------------------------------------------- |
-- COMPONENTS |
-------------------------------------------------------- |
-------------------------------------------------------- |
-- SIGNALS |
-------------------------------------------------------- |
signal CRC32_OUT_LOCAL: std_logic_vector(31 downto 0); |
signal DATA0: std_logic_vector(7 downto 0); |
------------------------------------------------------- |
-- IMPLEMENTATION |
-------------------------------------------------------- |
begin |
|
-- IMPORTANT: the CRC computation below is designed for DATA_IN(0) transmitted first. |
-- When re-using the code, please verify which bit is sent first into the CRC. Flip bit/byte order otherwise. |
|
-- Flip input byte |
--DATA0(7) <= DATA_IN(0); |
--DATA0(6) <= DATA_IN(1); |
--DATA0(5) <= DATA_IN(2); |
--DATA0(4) <= DATA_IN(3); |
--DATA0(3) <= DATA_IN(4); |
--DATA0(2) <= DATA_IN(5); |
--DATA0(1) <= DATA_IN(6); |
--DATA0(0) <= DATA_IN(7); |
DATA0 <= DATA_IN; |
|
|
CRC_COMPUTE_001: process(CLK, DATA0, SAMPLE_CLK_IN) |
begin |
if rising_edge(CLK) then |
if(SYNC_RESET = '1') then |
CRC32_OUT_LOCAL <= (others => '1'); |
elsif(SAMPLE_CLK_IN = '1') then |
-- new incoming byte |
CRC32_OUT_LOCAL(0) <= DATA0(1) xor DATA0(7) xor |
CRC32_IN(24) xor CRC32_IN(30); |
|
CRC32_OUT_LOCAL(1) <= DATA0(0) xor DATA0(1) xor DATA0(6) xor DATA0(7) xor |
CRC32_IN(24) xor CRC32_IN(25) xor CRC32_IN(30) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(2) <= DATA0(0) xor DATA0(1) xor DATA0(5) xor DATA0(6) xor |
DATA0(7) xor |
CRC32_IN(24) xor CRC32_IN(25) xor CRC32_IN(26) xor CRC32_IN(30) xor |
CRC32_IN(31); |
|
CRC32_OUT_LOCAL(3) <= DATA0(0) xor DATA0(4) xor DATA0(5) xor DATA0(6) xor |
CRC32_IN(25) xor CRC32_IN(26) xor CRC32_IN(27) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(4) <= DATA0(1) xor DATA0(3) xor DATA0(4) xor DATA0(5) xor |
DATA0(7) xor |
CRC32_IN(24) xor CRC32_IN(26) xor CRC32_IN(27) xor CRC32_IN(28) xor |
CRC32_IN(30); |
|
CRC32_OUT_LOCAL(5) <= DATA0(0) xor DATA0(1) xor DATA0(2) xor DATA0(3) xor |
DATA0(4) xor DATA0(6) xor DATA0(7) xor |
CRC32_IN(24) xor CRC32_IN(25) xor CRC32_IN(27) xor CRC32_IN(28) xor |
CRC32_IN(29) xor CRC32_IN(30) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(6) <= DATA0(0) xor DATA0(1) xor DATA0(2) xor DATA0(3) xor |
DATA0(5) xor DATA0(6) xor |
CRC32_IN(25) xor CRC32_IN(26) xor CRC32_IN(28) xor CRC32_IN(29) xor |
CRC32_IN(30) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(7) <= DATA0(0) xor DATA0(2) xor DATA0(4) xor DATA0(5) xor |
DATA0(7) xor |
CRC32_IN(24) xor CRC32_IN(26) xor CRC32_IN(27) xor CRC32_IN(29) xor |
CRC32_IN(31); |
|
CRC32_OUT_LOCAL(8) <= DATA0(3) xor DATA0(4) xor DATA0(6) xor DATA0(7) xor |
CRC32_IN(0) xor CRC32_IN(24) xor CRC32_IN(25) xor CRC32_IN(27) xor |
CRC32_IN(28); |
|
CRC32_OUT_LOCAL(9) <= DATA0(2) xor DATA0(3) xor DATA0(5) xor DATA0(6) xor |
CRC32_IN(1) xor CRC32_IN(25) xor CRC32_IN(26) xor CRC32_IN(28) xor |
CRC32_IN(29); |
|
CRC32_OUT_LOCAL(10) <= DATA0(2) xor DATA0(4) xor DATA0(5) xor DATA0(7) xor |
CRC32_IN(2) xor CRC32_IN(24) xor CRC32_IN(26) xor CRC32_IN(27) xor |
CRC32_IN(29); |
|
CRC32_OUT_LOCAL(11) <= DATA0(3) xor DATA0(4) xor DATA0(6) xor DATA0(7) xor |
CRC32_IN(3) xor CRC32_IN(24) xor CRC32_IN(25) xor CRC32_IN(27) xor |
CRC32_IN(28); |
|
CRC32_OUT_LOCAL(12) <= DATA0(1) xor DATA0(2) xor DATA0(3) xor DATA0(5) xor |
DATA0(6) xor DATA0(7) xor |
CRC32_IN(4) xor CRC32_IN(24) xor CRC32_IN(25) xor CRC32_IN(26) xor |
CRC32_IN(28) xor CRC32_IN(29) xor CRC32_IN(30); |
|
CRC32_OUT_LOCAL(13) <= DATA0(0) xor DATA0(1) xor DATA0(2) xor DATA0(4) xor |
DATA0(5) xor DATA0(6) xor |
CRC32_IN(5) xor CRC32_IN(25) xor CRC32_IN(26) xor CRC32_IN(27) xor |
CRC32_IN(29) xor CRC32_IN(30) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(14) <= DATA0(0) xor DATA0(1) xor DATA0(3) xor DATA0(4) xor |
DATA0(5) xor |
CRC32_IN(6) xor CRC32_IN(26) xor CRC32_IN(27) xor CRC32_IN(28) xor |
CRC32_IN(30) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(15) <= DATA0(0) xor DATA0(2) xor DATA0(3) xor DATA0(4) xor |
CRC32_IN(7) xor CRC32_IN(27) xor CRC32_IN(28) xor CRC32_IN(29) xor |
CRC32_IN(31); |
|
CRC32_OUT_LOCAL(16) <= DATA0(2) xor DATA0(3) xor DATA0(7) xor |
CRC32_IN(8) xor CRC32_IN(24) xor CRC32_IN(28) xor CRC32_IN(29); |
|
CRC32_OUT_LOCAL(17) <= DATA0(1) xor DATA0(2) xor DATA0(6) xor |
CRC32_IN(9) xor CRC32_IN(25) xor CRC32_IN(29) xor CRC32_IN(30); |
|
CRC32_OUT_LOCAL(18) <= DATA0(0) xor DATA0(1) xor DATA0(5) xor |
CRC32_IN(10) xor CRC32_IN(26) xor CRC32_IN(30) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(19) <= DATA0(0) xor DATA0(4) xor |
CRC32_IN(11) xor CRC32_IN(27) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(20) <= DATA0(3) xor |
CRC32_IN(12) xor CRC32_IN(28); |
|
CRC32_OUT_LOCAL(21) <= DATA0(2) xor |
CRC32_IN(13) xor CRC32_IN(29); |
|
CRC32_OUT_LOCAL(22) <= DATA0(7) xor |
CRC32_IN(14) xor CRC32_IN(24); |
|
CRC32_OUT_LOCAL(23) <= DATA0(1) xor DATA0(6) xor DATA0(7) xor |
CRC32_IN(15) xor CRC32_IN(24) xor CRC32_IN(25) xor CRC32_IN(30); |
|
CRC32_OUT_LOCAL(24) <= DATA0(0) xor DATA0(5) xor DATA0(6) xor |
CRC32_IN(16) xor CRC32_IN(25) xor CRC32_IN(26) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(25) <= DATA0(4) xor DATA0(5) xor |
CRC32_IN(17) xor CRC32_IN(26) xor CRC32_IN(27); |
|
CRC32_OUT_LOCAL(26) <= DATA0(1) xor DATA0(3) xor DATA0(4) xor DATA0(7) xor |
CRC32_IN(18) xor CRC32_IN(24) xor CRC32_IN(27) xor CRC32_IN(28) xor |
CRC32_IN(30); |
|
CRC32_OUT_LOCAL(27) <= DATA0(0) xor DATA0(2) xor DATA0(3) xor DATA0(6) xor |
CRC32_IN(19) xor CRC32_IN(25) xor CRC32_IN(28) xor CRC32_IN(29) xor |
CRC32_IN(31); |
|
CRC32_OUT_LOCAL(28) <= DATA0(1) xor DATA0(2) xor DATA0(5) xor |
CRC32_IN(20) xor CRC32_IN(26) xor CRC32_IN(29) xor CRC32_IN(30); |
|
CRC32_OUT_LOCAL(29) <= DATA0(0) xor DATA0(1) xor DATA0(4) xor |
CRC32_IN(21) xor CRC32_IN(27) xor CRC32_IN(30) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(30) <= DATA0(0) xor DATA0(3) xor |
CRC32_IN(22) xor CRC32_IN(28) xor CRC32_IN(31); |
|
CRC32_OUT_LOCAL(31) <= DATA0(2) xor |
CRC32_IN(23) xor CRC32_IN(29); |
|
end if; |
end if; |
end process; |
|
CRC32_OUT <= CRC32_OUT_LOCAL; |
|
CRC32_VALID <= '1' when (CRC32_OUT_LOCAL = x"C704DD7B") else '0'; |
|
end behavioral; |