Subversion Repositories hilbert_transformer

/trunk/sim/analytic_filter.cr.mti

trunk/sim/analytic_filter.cr.mti Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/WAVEFORMS/analytic_filter.do =================================================================== --- trunk/sim/WAVEFORMS/analytic_filter.do (nonexistent) +++ trunk/sim/WAVEFORMS/analytic_filter.do (revision 2) @@ -0,0 +1,34 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /analytic_filter_tb/clk +add wave -noupdate -format Logic /analytic_filter_tb/rst +add wave -noupdate -divider int +add wave -noupdate -format Literal -radix decimal /analytic_filter_tb/x +add wave -noupdate -format Literal -radix decimal /analytic_filter_tb/i +add wave -noupdate -format Literal -radix decimal /analytic_filter_tb/q +add wave -noupdate -format Logic /analytic_filter_tb/analytic_filter_inst/data_str_i +add wave -noupdate -format Logic /analytic_filter_tb/analytic_filter_inst/data_str_o +add wave -noupdate -divider real +add wave -noupdate -format Literal /analytic_filter_tb/x_real +add wave -noupdate -format Literal /analytic_filter_tb/i_real +add wave -noupdate -format Literal /analytic_filter_tb/q_real +add wave -noupdate -divider analog +add wave -noupdate -format Analog-Step -height 120 -offset 1.0 -scale 50.0 /analytic_filter_tb/x_real +add wave -noupdate -format Analog-Step -height 120 -offset 1.0 -scale 50.0 /analytic_filter_tb/i_real +add wave -noupdate -format Analog-Step -height 120 -offset 1.0 -scale 50.0 /analytic_filter_tb/q_real +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {65000 ps} 0} +configure wave -namecolwidth 274 +configure wave -valuecolwidth 39 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {10500 ns}

trunk/sim/WAVEFORMS/analytic_filter.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/analytic_filter.mpf =================================================================== --- trunk/sim/analytic_filter.mpf (nonexistent) +++ trunk/sim/analytic_filter.mpf (revision 2) @@ -0,0 +1,314 @@ +[Library] + +; Altera specific primitive library mappings + +vital2000 = $MODEL_TECH/../vital2000 +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +std = $MODEL_TECH/../std +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +apex20k = $MODEL_TECH/../altera/vhdl/apex20k +apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke +apexii = $MODEL_TECH/../altera/vhdl/apexii +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl +flex6000 = $MODEL_TECH/../altera/vhdl/flex6000 +flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke +max = $MODEL_TECH/../altera/vhdl/max +maxii = $MODEL_TECH/../altera/vhdl/maxii +stratix = $MODEL_TECH/../altera/vhdl/stratix +stratixii = $MODEL_TECH/../altera/vhdl/stratixii +cyclone = $MODEL_TECH/../altera/vhdl/cyclone +cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii +cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii +sgate = $MODEL_TECH/../altera/vhdl/sgate +apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k +apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke +apexii_ver = $MODEL_TECH/../altera/verilog/apexii +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl +flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000 +flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke +max_ver = $MODEL_TECH/../altera/verilog/max +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +stratix_ver = $MODEL_TECH/../altera/verilog/stratix +stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii +cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone +cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii +cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii +stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii + +work = work +[vcom] +; Turn on VHDL-1993 as the default. Normally is off. +; VHDL93 = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; .ini file has Explict enable so that std_logic_signed/unsigned +; will match synthesis tools behavior. + Explicit = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = false + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. + +; RequireConfigForAllDefaultBinding = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. Default is to include. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turns on incremental compilation of modules +; Incremental = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +resolution = 1ns + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +UserTimeUnit = default + +; Default run length +RunLength = 5 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; License = plus + +; Stop the simulator after an assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +;CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. For VHDL, PathSeparator = / +; for Verilog, PathSeparator = . +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, or deposit +; or in other terms, fixed, wired or charged. +; DefaultForceKind = freeze + +; If zero, open files when elaborated +; else open files on first read or write +; DelayFileOpen = 0 + +; Control VHDL files opened for write +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control number of VHDL files open concurrently +; This number should always be less then the +; current ulimit setting for max file descriptors +; 0 = unlimited +ConcurrentFileLimit = 40 + +; This controls the number of hierarchical regions displayed as +; part of a signal name shown in the waveform window. The default +; value or a value of zero tells VSIM to display the full name. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit +; packages. +; NumericStdNoWarnings = 1 + +; Control the format of a generate statement label. Don't quote it. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is to be compressed. +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl +[Project] +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 13 +Project_File_0 = ../vhdl/real_pole_filter_shift_reg.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1205777154 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_1 = ../vhdl/complex_fsf_filter_inv_c_m30_m150.vhd +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1205831828 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_2 = ../vhdl/fsf_comb_filter.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1205767658 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_3 = ../vhdl/complex_fsf_filter_c_90.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1205830100 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_4 = ../VHDL/hilbert_11_tap_opt.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230406760 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 voptflow 0 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_5 = ../vhdl/analytic_filter_h_a1.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230407440 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_6 = ../vhdl/resize_tools.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1205768358 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_7 = ../vhdl/analytic_filter_h_a2.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230406338 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_8 = ../vhdl/fsf_pole_filter.vhd +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1228832342 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_9 = ../vhdl/analytic_filter_h_a3.vhd +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230406482 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_10 = ../vhdl/const_delay.vhd +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1205768008 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_11 = ../vhdl/analytic_filter_h_a4.vhd +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230409121 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_12 = ../VHDL/analytic_filter_tb.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230408556 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 voptflow 0 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_Sim_Count = 1 +Project_Sim_0 = analytic_filter_tb +Project_Sim_P_0 = Generics {} timing default -std_output {} -nopsl 0 +notimingchecks 0 -L {} selected_du {} -hazards 0 -sdf {} ok 1 -0in 0 -nosva 0 folder {Top Level} +pulse_r {} -absentisempty 0 OtherArgs {} -multisource_delay {} +pulse_e {} vopt_env 0 -coverage 0 -sdfnoerror 0 +plusarg {} -vital2.2b 0 -t default -memprof 0 is_vopt_flow 0 additional_dus work.analytic_filter_tb -noglitch 0 -nofileshare 0 -wlf {} -assertdebug 0 +no_pulse_msg 0 -0in_options {} -assertfile {} -sdfnowarn 0 -Lf {} -std_input {} +Project_Folder_Count = 0 +Echo_Compile_Output = 1 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ReOpenSourceFiles = 1 +CloseSourceFiles = 1 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +EditorState = {tabbed horizontal 0} +Project_Major_Version = 6 +Project_Minor_Version = 3

trunk/sim/analytic_filter.mpf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property