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URL https://opencores.org/ocsvn/hive/hive/trunk

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/hive/trunk/v01.09/op_encode.h
0,0 → 1,97
`define ie 4'b0010
`define iez 4'b0011
`define il 4'b0100
`define ilz 4'b0101
`define ile 4'b0110
`define ilez 4'b0111
`define iug 4'b1000
`define igz 4'b1001
`define iuge 4'b1010
`define igez 4'b1011
`define igl 4'b1100
`define iglz 4'b1101
`define igle 3'b111
//
`define ez 3'b001
`define lz 3'b010
`define lez 3'b011
`define gz 3'b100
`define gez 3'b101
`define glz 3'b110
`define glez 3'b111
//
localparam OP_W = 10;
//
// immediate read & write - 64 codes
localparam [OP_W-1:0] op_rd_i = { 4'h0, 2'b00, 4'bxxxx }; // mem(B+I[3:0]) => A read immediate w/ offset (signed)
localparam [OP_W-1:0] op_rd_ix = { 4'h0, 2'b01, 4'bxxxx }; // {mem(B+I[3:0]), A[lo]} => A read immediate extended w/ offset
localparam [OP_W-1:0] op_wr_i = { 4'h0, 2'b10, 4'bxxxx }; // A[lo] => mem(B+I[3:0]) write immediate w/ offset
localparam [OP_W-1:0] op_wr_ix = { 4'h0, 2'b11, 4'bxxxx }; // A[hi] => mem(B+I[3:0]) write immediate extended w/ offset
// immediate conditional jump - 384 codes
localparam [OP_W-1:0] op_jmp_ie = { 1'b0, `ie, 5'bxxxxx }; // (A?B), (A?0) PC+I[4:0] => PC jump relative immediate conditional
localparam [OP_W-1:0] op_jmp_iez = { 1'b0, `iez, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_il = { 1'b0, `il, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_ilz = { 1'b0, `ilz, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_ile = { 1'b0, `ile, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_ilez = { 1'b0, `ilez, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_iug = { 1'b0, `iug, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_igz = { 1'b0, `igz, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_iuge = { 1'b0, `iuge, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_igez = { 1'b0, `igez, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_igl = { 1'b0, `igl, 5'bxxxxx };
localparam [OP_W-1:0] op_jmp_iglz = { 1'b0, `iglz, 5'bxxxxx };
// immediate unconditional jump - 64 codes
localparam [OP_W-1:0] op_jmp_i = { 1'b0, `igle, 6'bxxxxxx };
// immediate byte - 256 codes
localparam [OP_W-1:0] op_byt_i = { 2'b10, 8'bxxxxxxxx }; // I[7:0] => A byte immediate (signed)
// immediate shift - 128 codes
localparam [OP_W-1:0] op_shl_i = { 4'hc, 6'bxxxxxx }; // A<<I => A shift left A (signed) immediate
localparam [OP_W-1:0] op_shl_iu = { 4'hd, 6'bxxxxxx }; // 1<<I | A<<I => A shift left immediate unsigned
// immediate add - 64 codes
localparam [OP_W-1:0] op_add_i = { 4'he, 6'bxxxxxx }; // A+I[5:0] => A add immediate (I signed)
// conditional jump - 7 of 8 codes
localparam [OP_W-1:0] op_jmp_ez = { 4'hf, 3'b000, `ez }; // (A?0) PC+B[lo] => PC jump relative conditional
localparam [OP_W-1:0] op_jmp_lz = { 4'hf, 3'b000, `lz };
localparam [OP_W-1:0] op_jmp_lez = { 4'hf, 3'b000, `lez };
localparam [OP_W-1:0] op_jmp_gz = { 4'hf, 3'b000, `gz };
localparam [OP_W-1:0] op_jmp_gez = { 4'hf, 3'b000, `gez };
localparam [OP_W-1:0] op_jmp_glz = { 4'hf, 3'b000, `glz };
localparam [OP_W-1:0] op_jmp = { 4'hf, 3'b000, `glez };
// conditional goto - 7 of 8 codes
localparam [OP_W-1:0] op_gto_ez = { 4'hf, 3'b001, `ez }; // (A?0) B[lo] => PC jump absolute conditional
localparam [OP_W-1:0] op_gto_lz = { 4'hf, 3'b001, `lz };
localparam [OP_W-1:0] op_gto_lez = { 4'hf, 3'b001, `lez };
localparam [OP_W-1:0] op_gto_gz = { 4'hf, 3'b001, `gz };
localparam [OP_W-1:0] op_gto_gez = { 4'hf, 3'b001, `gez };
localparam [OP_W-1:0] op_gto_glz = { 4'hf, 3'b001, `glz };
localparam [OP_W-1:0] op_gto = { 4'hf, 3'b001, `glez };
// singles - 48 codes
localparam [OP_W-1:0] op_add = { 4'hf, 2'b01, 4'h0 }; // A+B => A add
localparam [OP_W-1:0] op_add_x = { 4'hf, 2'b01, 4'h2 }; // A+B => A add extended (signed)
localparam [OP_W-1:0] op_add_ux = { 4'hf, 2'b01, 4'h3 }; // A+B => A add extended unsigned
localparam [OP_W-1:0] op_sub = { 4'hf, 2'b01, 4'h4 }; // A-B => A subtract
localparam [OP_W-1:0] op_sub_x = { 4'hf, 2'b01, 4'h6 }; // A-B => A subtract extended (signed)
localparam [OP_W-1:0] op_sub_ux = { 4'hf, 2'b01, 4'h7 }; // A-B => A subtract extended unsigned
localparam [OP_W-1:0] op_mul = { 4'hf, 2'b01, 4'h8 }; // A*B => A multiply
localparam [OP_W-1:0] op_mul_x = { 4'hf, 2'b01, 4'ha }; // A*B => A multiply extended (signed)
localparam [OP_W-1:0] op_mul_ux = { 4'hf, 2'b01, 4'hb }; // A*B => A multiply extended unsigned
localparam [OP_W-1:0] op_shl = { 4'hf, 2'b01, 4'hc }; // A<<B => A shift left A (signed)
localparam [OP_W-1:0] op_shl_u = { 4'hf, 2'b01, 4'hd }; // 1<<B | A<<B => A 2^B | shift left A unsigned
//
localparam [OP_W-1:0] op_and = { 4'hf, 2'b10, 4'h0 }; // A&B => A logical AND
localparam [OP_W-1:0] op_or = { 4'hf, 2'b10, 4'h1 }; // A|B => A logical OR
localparam [OP_W-1:0] op_xor = { 4'hf, 2'b10, 4'h2 }; // A^B => A logical XOR
localparam [OP_W-1:0] op_not = { 4'hf, 2'b10, 4'h3 }; // ~B => A logical NOT
localparam [OP_W-1:0] op_and_b = { 4'hf, 2'b10, 4'h4 }; // &B => A logical AND bit reduction
localparam [OP_W-1:0] op_or_b = { 4'hf, 2'b10, 4'h5 }; // |B => A logical OR bit reduction
localparam [OP_W-1:0] op_xor_b = { 4'hf, 2'b10, 4'h6 }; // ^B => A logical XOR bit reduction
//
localparam [OP_W-1:0] op_lit = { 4'hf, 2'b11, 4'h0 }; // mem(PC) => A literal low (signed)
localparam [OP_W-1:0] op_lit_u = { 4'hf, 2'b11, 4'h1 }; // mem(PC) => A literal low unsigned
localparam [OP_W-1:0] op_lit_x = { 4'hf, 2'b11, 4'h2 }; // {mem(PC),A[lo]} => A literal extended
localparam [OP_W-1:0] op_cpy = { 4'hf, 2'b11, 4'h4 }; // B => A copy
localparam [OP_W-1:0] op_pc = { 4'hf, 2'b11, 4'h8 }; // PC => A read PC (unsigned)
localparam [OP_W-1:0] op_gsb = { 4'hf, 2'b11, 4'h9 }; // B[lo] => PC, PC => A subroutine call
localparam [OP_W-1:0] op_cls = { 4'hf, 2'b11, 4'hc }; // clear stacks
localparam [OP_W-1:0] op_pop = { 4'hf, 2'b11, 4'he }; // do nothing (but allow pops)
localparam [OP_W-1:0] op_nop = { 4'hf, 2'b11, 4'hf }; // do nothing (no pops either)
/hive/trunk/v01.09/boot_code.h
0,0 → 1,512
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
-------------------------
-- external parameters --
-------------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
 
/*
------------------------------------------------------------
-- defines that make programming code more human readable --
------------------------------------------------------------
*/
`define s0 2'd0
`define s1 2'd1
`define s2 2'd2
`define s3 2'd3
`define _ 1'b0
`define P 1'b1
//
`define op_rd_i op_rd_i[9:4]
`define op_rd_ix op_rd_ix[9:4]
`define op_wr_i op_wr_i[9:4]
`define op_wr_ix op_wr_ix[9:4]
//
`define op_jmp_ie op_jmp_ie[9:5]
`define op_jmp_iez op_jmp_iez[9:5]
`define op_jmp_il op_jmp_il[9:5]
`define op_jmp_ilz op_jmp_ilz[9:5]
`define op_jmp_ile op_jmp_ile[9:5]
`define op_jmp_ilez op_jmp_ilez[9:5]
`define op_jmp_iug op_jmp_iug[9:5]
`define op_jmp_igz op_jmp_igz[9:5]
`define op_jmp_iuge op_jmp_iuge[9:5]
`define op_jmp_igez op_jmp_igez[9:5]
`define op_jmp_igl op_jmp_igl[9:5]
`define op_jmp_iglz op_jmp_iglz[9:5]
//
`define op_jmp_i op_jmp_i[9:6]
//
`define op_byt_i op_byt_i[9:8]
//
`define op_shl_i op_shl_i[9:6]
`define op_shl_iu op_shl_iu[9:6]
//
`define op_add_i op_add_i[9:6]
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { op_nop, `_, `_, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test ALU logical functions
// Thread 1 : test ALU arithmetic functions
// Thread 2 : test ALU shift functions
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h100 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
// thread 1
i='h4; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h200 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
// thread 2
i='h8; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h300 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
// and the rest (are here on Gilligan's Isle)
i='hc; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
 
// test ALU logical functions, result in s0
// Correct functioning is s0 = 'd12 ('hc).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h100; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// load s1 & s2 values
i=i+1; ram[i] = { `op_byt_i, -8'h1, `_, `_, `s1, `s1 }; // -1 => s1
i=i+1; ram[i] = { `op_byt_i, 8'h1, `_, `_, `s2, `s2 }; // 1 => s2
// AND_B ( &(-1)=-1; &(1)= 0 )
i=i+1; ram[i] = { op_and_b, `_, `_, `s1, `s0 }; // &s1=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_and_b, `_, `_, `s2, `s0 }; // &s2=>s0
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// OR_B ( |(-1)=-1; |(1)=-1 )
i=i+1; ram[i] = { op_or_b, `_, `_, `s1, `s0 }; // |s1=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_or_b, `_, `_, `s2, `s0 }; // |s2=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// XOR_B ( ^(-1)= 0; ^(1)=-1 )
i=i+1; ram[i] = { op_xor_b, `_, `_, `s1, `s0 }; // ^s1=>s0
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_xor_b, `_, `_, `s2, `s0 }; // ^s2=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// clean up
i=i+1; ram[i] = { op_pop, `P, `P, `s2, `s1 }; // pop s2 & s1
// load s1 & s2 values
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
i=i+1; ram[i] = 16'ha53c ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
i=i+1; ram[i] = 16'h36c9 ; // hi data
//
i=i+1; ram[i] = { op_lit, `_, `_, `s2, `s2 }; // lit => s2
i=i+1; ram[i] = 16'hc396 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s2, `s2 }; // lit => s2, pop combine
i=i+1; ram[i] = 16'h5ca3 ; // hi data
// AND (s/b 'h1481,8114)
i=i+1; ram[i] = { op_and, `_, `_, `s2, `s1 }; // s1&s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h8114 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h1481 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// OR (s/b 'h7eeb,e7be)
i=i+1; ram[i] = { op_or, `_, `_, `s2, `s1 }; // s1|s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'he7be ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h7eeb ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// XOR (s/b 'h6a6a,66aa)
i=i+1; ram[i] = { op_xor, `_, `_, `s2, `s1 }; // s1^s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h66aa ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h6a6a ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// NOT (s/b 'hc936,5ac3)
i=i+1; ram[i] = { op_not, `_, `_, `s1, `s1 }; // ~s1=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h5ac3 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hc936 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
 
// test ALU arithmetic functions, result in s0
// Correct functioning is s0 = 'd13 ('hd).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h200; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// load s1 & s2 values
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h36c9 ; // hi data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
i=i+1; ram[i] = 16'ha53c ; // lo data
//
i=i+1; ram[i] = { op_lit, `_, `_, `s2, `s2 }; // lit => s2
i=i+1; ram[i] = 16'hc396 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s2, `s2 }; // lit => s2, pop combine
i=i+1; ram[i] = 16'h5ca3 ; // hi data
// ADD_I -32 (s/b 'ha53c,36a9)
i=i+1; ram[i] = { `op_add_i, -6'd32, `_, `_, `s1, `s1 }; // s1-32=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h36a9 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'ha53c ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD_I +31 (s/b 'ha53c,36e8)
i=i+1; ram[i] = { `op_add_i, 6'd31, `_, `_, `s1, `s1 }; // s1+31=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h36e8 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'ha53c ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD (s/b 'h01df,fa5f)
i=i+1; ram[i] = { op_add, `_, `_, `s2, `s1 }; // s1+s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hfa5f ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h01df ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD_X (s/b 0)
i=i+1; ram[i] = { op_add_x, `_, `_, `s2, `s1 }; // s1+s2=>s1
i=i+1; ram[i] = { `op_byt_i, 8'h0, `_, `_, `s0, `s0 }; // 0 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD_UX (s/b 1)
i=i+1; ram[i] = { op_add_ux, `_, `_, `s2, `s1 }; // s1+s2=>s1
i=i+1; ram[i] = { `op_byt_i, 8'h1, `_, `_, `s0, `s0 }; // 1 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SUB (s/b 'h4898,7333)
i=i+1; ram[i] = { op_sub, `_, `_, `s2, `s1 }; // s1-s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h7333 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h4898 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SUB_X (s/b -1)
i=i+1; ram[i] = { op_sub_x, `_, `_, `s2, `s1 }; // s1-s2=>s1
i=i+1; ram[i] = { `op_byt_i, -8'h1, `_, `_, `s0, `s0 }; // -1 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SUB_UX (s/b 0)
i=i+1; ram[i] = { op_sub_ux, `_, `_, `s2, `s1 }; // s1-s2=>s1
i=i+1; ram[i] = { `op_byt_i, 8'h0, `_, `_, `s0, `s0 }; // 0 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// MUL (s/b 'hccfe,34c6)
i=i+1; ram[i] = { op_mul, `_, `_, `s2, `s1 }; // s1*s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h34c6 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hccfe ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// MUL_X (s/b 'hdf27,93ae)
i=i+1; ram[i] = { op_mul_x, `_, `_, `s2, `s1 }; // s1*s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h93ae ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hdf27 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// MUL_UX (s/b 'h3bcb,5744)
i=i+1; ram[i] = { op_mul_ux, `_, `_, `s2, `s1 }; // s1*s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h5744 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h3bcb ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
// test ALU shift functions, result in s0
// Correct functioning is s0 = 'd10 ('ha).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h300; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// load s1 value 0xa53c36c9
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h36c9 ; // hi data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
i=i+1; ram[i] = 16'ha53c ; // lo data
// SHL_I -28 (s/b 'hffff,fffa)
i=i+1; ram[i] = { `op_shl_i, -6'd28, `_, `_, `s1, `s1 }; // s1<<-28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hfffa ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hffff ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_I +28 (s/b 'h9000,0000)
i=i+1; ram[i] = { `op_shl_i, 6'd28, `_, `_, `s1, `s1 }; // s1<<28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h0000 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h9000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_IU -28 (s/b 'h0000,000a)
i=i+1; ram[i] = { `op_shl_iu, -6'd28, `_, `_, `s1, `s1 }; // s1<<-28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h000a ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h0000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_IU +28 (s/b 'h1000,0000)
i=i+1; ram[i] = { `op_shl_iu, 6'd28, `_, `_, `s1, `s1 }; // 1<<28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h0000 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h1000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL -4 (s/b 'hfa53,c36c)
i=i+1; ram[i] = { `op_byt_i, -8'd4, `_, `_, `s2, `s2 }; // -4=>s2
i=i+1; ram[i] = { op_shl, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hc36c ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hfa53 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL +4 (s/b 'h53c3,6c90)
i=i+1; ram[i] = { `op_byt_i, 8'd4, `_, `_, `s2, `s2 }; // 4=>s2
i=i+1; ram[i] = { op_shl, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h6c90 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h53c3 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_U -4 (s/b 'h0a53,c36c)
i=i+1; ram[i] = { `op_byt_i, -8'd4, `_, `_, `s2, `s2 }; // -4=>s2
i=i+1; ram[i] = { op_shl_u, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hc36c ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h0a53 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL +4 (s/b 'h0000,0010)
i=i+1; ram[i] = { `op_byt_i, 8'd4, `_, `_, `s2, `s2 }; // 4=>s2
i=i+1; ram[i] = { op_shl_u, `P, `_, `s2, `s1 }; // 1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h0010 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h0000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : read & clear opcode errors for this thread => s0, return to (s3)
i='h900; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { `op_rd_i, OP_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, OP_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
// sub : read & clear stack errors for this thread => s0, return to (s3)
i='h910; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { op_cpy, `_, `_, `s0, `s3 }; // s0=>s3
i=i+1; ram[i] = { `op_shl_i, 6'd8, `_, `P, `s0, `s3 }; // s3<<8=>s3, pop s3
i=i+1; ram[i] = { op_or, `P, `P, `s3, `s0 }; // s0|s3=>s0, pop both
i=i+1; ram[i] = { `op_rd_i, STK_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, STK_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
 
end
/hive/trunk/v01.09/alu_mult_shift.v
0,0 → 1,196
/*
--------------------------------------------------------------------------------
 
Module : alu_mult_shift
 
--------------------------------------------------------------------------------
 
Function:
- Multiply & shift unit for a processor ALU.
 
Instantiates:
- functions.h (clog2)
- (1x) alu_multiply.v
- (1x) vector_sr.v (debug mode only)
- (3x) vector_sr.v
 
Notes:
- I/O optionally registered.
- 5 stage pipeline w/ 4 mid registers (not counting I/O registering).
- Shift left signed uses signed B to shift signed A left (B+) and right (B-).
- Shift left unsigned and B(0,+) gives 2^B (one-hot / power of 2).
- Shift left unsigned and B(-) gives unsigned A shift right.
- Shift takes precedence over multiply.
- Copy takes precedence over shift & multiply.
- Copy unsigned & signed unextended results s/b the same.
- Copy unsigned extended result s/b all zero.
- Copy signed extended result s/b all B sign.
- Debug mode for comparison to native signed multiplication, only use for
simulation as it consumes resources and negatively impacts top speed.
 
--------------------------------------------------------------------------------
*/
 
module alu_mult_shift
#(
parameter integer REGS_IN = 1, // in register option
parameter integer REGS_OUT = 1, // out register option
parameter integer DATA_W = 4, // data width
parameter integer DEBUG_MODE = 1 // 1=debug mode; 0=normal mode
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire shl_i, // 1=shift left
input wire cpy_i, // 1=copy b
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output wire [DATA_W-1:0] result_o, // result
// debug
output wire debug_o // 1=bad match
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
localparam integer SH_SEL_W = clog2( DATA_W );
localparam integer ZSX_W = DATA_W+1; // +1 extra bit
localparam integer DBL_W = DATA_W*2; // double width
//
wire [DATA_W-1:0] a, b;
wire cpy, shl, ext, sgn;
reg [DATA_W:0] a_mux, b_mux; // +1 extra bit
reg ext_mux;
wire ext_mux_r;
wire [DBL_W-1:0] res_dbl;
reg [DATA_W-1:0] result;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input regs
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( DATA_W+DATA_W+4 ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { a_i, b_i, cpy_i, shl_i, ext_i, sgn_i } ),
.data_o ( { a, b, cpy, shl, ext, sgn } )
);
 
 
// mux inputs and extended result selector
always @ ( * ) begin
casex ( { cpy, shl, sgn } )
'b000 : begin // unsigned multiply
a_mux <= a; // zero extend
b_mux <= b; // zero extend
ext_mux <= ext; // follow input
end
'b001 : begin // signed multiply
a_mux <= { a[DATA_W-1], a }; // sign extend
b_mux <= { b[DATA_W-1], b }; // sign extend
ext_mux <= ext; // follow input
end
'b010 : begin // unsigned shift / pow2
a_mux <= ( b[DATA_W-1] ) ? a : 1'b1; // a=1 for positive shifts
b_mux <= 1'b1 << b[SH_SEL_W-1:0]; // pow2
ext_mux <= b[DATA_W-1]; // sign selects output
end
'b011 : begin // signed shift
a_mux <= { a[DATA_W-1], a }; // sign extend
b_mux <= 1'b1 << b[SH_SEL_W-1:0]; // pow2
ext_mux <= b[DATA_W-1]; // sign selects output
end
'b1x0 : begin // unsigned copy b
a_mux <= 1'b1; // a=1
b_mux <= b; // zero extend
ext_mux <= ext; // follow input
end
'b1x1 : begin // signed copy b
a_mux <= 1'b1; // a=1
b_mux <= { b[DATA_W-1], b }; // sign extend
ext_mux <= ext; // follow input
end
endcase
end
 
 
// signed multiplier (4 registers deep)
alu_multiply
#(
.DATA_W ( ZSX_W ),
.DEBUG_MODE ( DEBUG_MODE )
)
alu_multiply
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.a_i ( a_mux ),
.b_i ( b_mux ),
.result_o ( res_dbl ),
.debug_o ( debug_o )
);
 
 
// pipeline extended result selector to match multiply
vector_sr
#(
.REGS ( 4 ),
.DATA_W ( 1 ),
.RESET_VAL ( 0 )
)
regs_ext
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( ext_mux ),
.data_o ( ext_mux_r )
);
 
 
// multiplex
always @ ( * ) begin
case ( ext_mux_r )
'b0 : result <= res_dbl[DATA_W-1:0];
'b1 : result <= res_dbl[DBL_W-1:DATA_W];
endcase
end
 
// optional output regs
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( result ),
.data_o ( result_o )
);
 
 
endmodule
/hive/trunk/v01.09/alu_multiply.v
0,0 → 1,155
/*
--------------------------------------------------------------------------------
 
Module : alu_multiply
 
--------------------------------------------------------------------------------
 
Function:
- Signed multiply unit for a processor ALU.
 
Instantiates:
- (1x) vector_sr.v (debug mode only)
 
Notes:
- 3 stage 4 register pipeline.
- Multiply stage I/O registers are likely free (part of multiplier fabric).
- Debug mode for comparison to native signed multiplication, only use for
simulation / verification as it consumes resources and negatively impacts
top speed.
 
--------------------------------------------------------------------------------
*/
 
module alu_multiply
#(
parameter integer DATA_W = 33, // data width
parameter integer DEBUG_MODE = 1 // 1=debug mode; 0=normal mode
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output reg [DATA_W*2-1:0] result_o, // = ( a_i * b_i )
// debug
output wire debug_o // 1=bad match
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer HI_W = DATA_W/2; // 16
localparam integer LO_W = DATA_W-HI_W; // 17
localparam integer MULT_W = LO_W*2; // 34
localparam integer DBL_W = DATA_W*2; // 66
//
reg signed [DATA_W-1:0] a, b;
wire signed [HI_W-1:0] a_hi, b_hi;
wire signed [LO_W:0] a_lo_ze, b_lo_ze; // 35 (extra zero MSB)
reg signed [MULT_W-1:0] mult_hi_hi, mult_hi_lo, mult_lo_hi, mult_lo_lo;
reg signed [DBL_W-1:0] inner_sum, outer_cat;
 
 
/*
================
== code start ==
================
*/
 
 
// input registering (likely free)
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
a <= 'b0;
b <= 'b0;
end else begin
a <= a_i;
b <= b_i;
end
end
// select & extend inputs
assign a_hi = a[DATA_W-1:LO_W];
assign b_hi = b[DATA_W-1:LO_W];
assign a_lo_ze = { 1'b0, a[LO_W-1:0] };
assign b_lo_ze = { 1'b0, b[LO_W-1:0] };
 
// do all multiplies & register (registers are likely free)
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
mult_hi_hi <= 'b0;
mult_hi_lo <= 'b0;
mult_lo_hi <= 'b0;
mult_lo_lo <= 'b0;
end else begin
mult_hi_hi <= a_hi * b_hi;
mult_hi_lo <= a_hi * b_lo_ze;
mult_lo_hi <= a_lo_ze * b_hi;
mult_lo_lo <= a_lo_ze * b_lo_ze;
end
end
 
// add and shift inner terms, concatenate outer terms, register
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
inner_sum <= 'b0;
outer_cat <= 'b0;
end else begin
inner_sum <= ( mult_hi_lo + mult_lo_hi ) << LO_W;
outer_cat <= { mult_hi_hi[HI_W*2-1:0], mult_lo_lo };
end
end
 
// final add & register
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
result_o <= 'b0;
end else begin
result_o <= outer_cat + inner_sum;
end
end
 
 
// optional debug mode
generate
if ( DEBUG_MODE ) begin
wire signed [DBL_W-1:0] debug_mult, debug_mult_r;
reg debug;
assign debug_mult = a * b;
// delay regs
vector_sr
#(
.REGS ( 3 ),
.DATA_W ( DBL_W ),
.RESET_VAL ( 0 )
)
regs_debug
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( debug_mult ),
.data_o ( debug_mult_r )
);
// compare & register
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
debug <= 'b0;
end else begin
debug <= ( debug_mult_r != result_o );
end
end
//
assign debug_o = debug;
end else begin
assign debug_o = 'b0;
end
endgenerate
 
 
endmodule
/hive/trunk/v01.09/stacks_mux.v
0,0 → 1,85
/*
--------------------------------------------------------------------------------
 
Module : stacks_mux.v
 
--------------------------------------------------------------------------------
 
Function:
- Output multiplexer for processor stacks.
 
Instantiates:
- (1x) vector_sr.v
 
Notes:
- Purely combinatorial.
 
--------------------------------------------------------------------------------
*/
 
module stacks_mux
#(
parameter integer DATA_W = 32, // data width
parameter integer STK_W = 2, // stack selector width
parameter integer IM_DATA_W = 8 // immediate data width
)
(
// control I/O
input wire [STK_W-1:0] a_sel_i, // stack selector
input wire [STK_W-1:0] b_sel_i, // stack selector
input wire imda_i, // 1=immediate data
// data I/O
input wire [DATA_W-1:0] pop_data0_i, // stack data
input wire [DATA_W-1:0] pop_data1_i, // stack data
input wire [DATA_W-1:0] pop_data2_i, // stack data
input wire [DATA_W-1:0] pop_data3_i, // stack data
input wire [IM_DATA_W-1:0] im_data_i, // immediate data
//
output wire [DATA_W-1:0] a_o, // results
output wire [DATA_W-1:0] b_o,
output wire [DATA_W-1:0] b_alu_o
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
reg [DATA_W-1:0] a, b;
 
 
/*
================
== code start ==
================
*/
 
 
// mux stack read data
always @ ( * ) begin
case ( a_sel_i )
'b00 : a <= pop_data0_i;
'b01 : a <= pop_data1_i;
'b10 : a <= pop_data2_i;
'b11 : a <= pop_data3_i;
endcase
end
// mux stack read data
always @ ( * ) begin
case ( b_sel_i )
'b00 : b <= pop_data0_i;
'b01 : b <= pop_data1_i;
'b10 : b <= pop_data2_i;
'b11 : b <= pop_data3_i;
endcase
end
// output
assign a_o = a;
assign b_o = b;
assign b_alu_o = ( imda_i ) ? $signed( im_data_i ) : $signed( b );
 
 
endmodule
/hive/trunk/v01.09/copyright.txt
0,0 → 1,2
Copyright (c) Eric David Wallin, 2013.
Permission to use, copy, modify, and/or distribute this design for any purpose without fee is hereby granted, provided it is not used for spying or "surveillance" uses, military or "defense" projects, weaponry, or other nefarious purposes. Furthermore the above copyright and this permission notice must appear in all copies.
/hive/trunk/v01.09/dp_ram_infer.v
0,0 → 1,137
/*
--------------------------------------------------------------------------------
 
Module: dp_ram_infer.v
 
Function:
- Infers a parameterized dual port synchronous RAM.
 
Instantiates:
- Nothing (block RAM will most likely be synthesized).
 
Notes:
- A & B sides are separate clock domains.
- Writes accept data after the address & write enable on the clock.
- Reads present data after the address on the clock.
- Configurable read-during-write mode (for the same port).
- Optional output data registering (likely an internal BRAM resource).
 
--------------------------------------------------------------------------------
*/
 
module dp_ram_infer
#(
parameter integer REG_A_OUT = 1, // 1=enable A output registering
parameter integer REG_B_OUT = 1, // 1=enable B output registering
parameter integer DATA_W = 16,
parameter integer ADDR_W = 8,
parameter RD_MODE = "WR_DATA" // options here are "MEM_DATA" and "WR_DATA"
)
(
// A side
input wire a_clk_i, // A clock
input wire [ADDR_W-1:0] a_addr_i, // A address
input wire a_wr_i, // A write enable, active high
input wire [DATA_W-1:0] a_data_i, // A write data
output wire [DATA_W-1:0] a_data_o, // A read data
// B side
input wire b_clk_i, // B clock
input wire [ADDR_W-1:0] b_addr_i, // B address
input wire b_wr_i, // B write enable, active high
input wire [DATA_W-1:0] b_data_i, // B write data
output wire [DATA_W-1:0] b_data_o // B read data
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer CAPACITY = 2**ADDR_W; // total words possible to store
reg [DATA_W-1:0] ram[0:CAPACITY-1]; // memory
reg [DATA_W-1:0] a_data, b_data;
`include "boot_code.h"
 
 
 
/*
================
== code start ==
================
*/
 
 
 
/*
------------
-- side A --
------------
*/
 
// write
always @ ( posedge a_clk_i ) begin
if ( a_wr_i ) begin
ram[a_addr_i] <= a_data_i;
end
end
 
// read
always @ ( posedge a_clk_i ) begin
if ( a_wr_i & RD_MODE == "WR_DATA" ) begin
a_data <= a_data_i;
end else begin
a_data <= ram[a_addr_i];
end
end
 
// optional output reg
generate
if ( REG_A_OUT ) begin
reg [DATA_W-1:0] a_data_r;
always @ ( posedge a_clk_i ) begin
a_data_r <= a_data;
end
assign a_data_o = a_data_r;
end else begin
assign a_data_o = a_data;
end
endgenerate
 
 
/*
------------
-- side B --
------------
*/
 
// write
always @ ( posedge b_clk_i ) begin
if ( b_wr_i ) begin
ram[b_addr_i] <= b_data_i;
end
end
 
// read
always @ ( posedge b_clk_i ) begin
if ( b_wr_i & RD_MODE == "WR_DATA" ) begin
b_data <= b_data_i;
end else begin
b_data <= ram[b_addr_i];
end
end
 
// optional output reg
generate
if ( REG_B_OUT ) begin
reg [DATA_W-1:0] b_data_r;
always @ ( posedge b_clk_i ) begin
b_data_r <= b_data;
end
assign b_data_o = b_data_r;
end else begin
assign b_data_o = b_data;
end
endgenerate
 
 
endmodule
/hive/trunk/v01.09/dq_ram_infer.v
0,0 → 1,85
/*
--------------------------------------------------------------------------------
 
Module: dq_ram_infer.v
 
Function:
- Infers a parameterized simple DQ synchronous RAM.
 
Instantiates:
- Nothing (block RAM will most likely be synthesized).
 
Notes:
- Writes accept data after the address & write enable on the clock.
- Reads present data after the address on the clock.
- Configurable read-during-write mode.
- Optional output data registering (likely an internal BRAM resource).
 
--------------------------------------------------------------------------------
*/
 
module dq_ram_infer
#(
parameter integer REG_OUT = 1, // 1=enable output registering
parameter integer DATA_W = 16,
parameter integer ADDR_W = 8,
parameter RD_MODE = "MEM_DATA" // options here are "MEM_DATA" and "WR_DATA"
)
(
input wire clk_i, // clock
input wire [ADDR_W-1:0] addr_i, // address
input wire wr_i, // write enable, active high
input wire [DATA_W-1:0] data_i, // write data
output wire [DATA_W-1:0] data_o // read data
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer CAPACITY = 2**ADDR_W; // total words possible to store
reg [DATA_W-1:0] ram[0:CAPACITY-1]; // memory
reg [DATA_W-1:0] data;
 
 
 
/*
================
== code start ==
================
*/
 
 
 
// write
always @ ( posedge clk_i ) begin
if ( wr_i ) begin
ram[addr_i] <= data_i;
end
end
 
// read
always @ ( posedge clk_i ) begin
if ( wr_i & RD_MODE == "WR_DATA" ) begin
data <= data_i;
end else begin
data <= ram[addr_i];
end
end
 
// optional output reg
generate
if ( REG_OUT == 1 ) begin
reg [DATA_W-1:0] data_r;
always @ ( posedge clk_i ) begin
data_r <= data;
end
assign data_o = data_r;
end else begin
assign data_o = data;
end
endgenerate
 
 
endmodule
/hive/trunk/v01.09/thread_ring.v
0,0 → 1,79
/*
--------------------------------------------------------------------------------
 
Module : thread_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor thread pipeline.
 
Instantiates:
- Nothing.
 
Notes:
- 8 stage pipeline.
- Counter in stage 0 ensures long-term correct operation.
 
--------------------------------------------------------------------------------
*/
 
module thread_ring
#(
parameter integer THRD_W = 3 // thread width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// threads
output reg [THRD_W-1:0] thrd_0_o,
output reg [THRD_W-1:0] thrd_1_o,
output reg [THRD_W-1:0] thrd_2_o,
output reg [THRD_W-1:0] thrd_3_o,
output reg [THRD_W-1:0] thrd_4_o,
output reg [THRD_W-1:0] thrd_5_o,
output reg [THRD_W-1:0] thrd_6_o,
output reg [THRD_W-1:0] thrd_7_o
);
 
/*
----------------------
-- internal signals --
----------------------
*/
 
 
/*
================
== code start ==
================
*/
 
 
// pipeline thread
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
thrd_0_o <= 'd5;
thrd_1_o <= 'd4;
thrd_2_o <= 'd3;
thrd_3_o <= 'd2;
thrd_4_o <= 'd1;
thrd_5_o <= 'd0;
thrd_6_o <= 'd7;
thrd_7_o <= 'd6;
end else begin
thrd_0_o <= thrd_0_o + 1'b1; // note: counter terminus
thrd_1_o <= thrd_0_o;
thrd_2_o <= thrd_1_o;
thrd_3_o <= thrd_2_o;
thrd_4_o <= thrd_3_o;
thrd_5_o <= thrd_4_o;
thrd_6_o <= thrd_5_o;
thrd_7_o <= thrd_6_o;
end
end
 
endmodule
/hive/trunk/v01.09/data_ring.v
0,0 → 1,251
/*
--------------------------------------------------------------------------------
 
Module : data_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor data path & data stacks.
 
Instantiates:
- (1x) stacks_mux.v
- (1x) alu_top.v
- (1x) pointer_ring.v
- (4x) dq_ram_infer.v
 
Notes:
- 8 stage data pipeline beginning and ending on four BRAM based LIFOs.
 
--------------------------------------------------------------------------------
*/
 
module data_ring
#(
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3, // thread selector width
parameter integer STACKS = 4, // stacks
parameter integer STK_W = 2, // stack selector width
parameter integer PNTR_W = 5, // stack pointer width
parameter integer IM_DATA_W = 8, // immediate data width
parameter integer LG_W = 2, // operation width
parameter integer POP_PROT = 1, // 1=error protection, 0=none
parameter integer PUSH_PROT = 1 // 1=error protection, 0=none
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [STK_W-1:0] a_sel_i, // stack selector
input wire [STK_W-1:0] b_sel_i, // stack selector
input wire imda_i, // 1=immediate data
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire [LG_W-1:0] lg_i, // see decode in notes above
input wire add_i, // 1=add
input wire sub_i, // 1=subtract
input wire mul_i, // 1=multiply
input wire shl_i, // 1=shift left
input wire cpy_i, // 1=copy b
input wire dm_i, // 1=data mem
input wire rtn_i, // 1=return pc
// stack I/O
input wire stk_clr_i, // stacks clear
input wire [STACKS-1:0] pop_i, // stacks pop
input wire [STACKS-1:0] push_i, // stacks push
input wire [THRD_W-1:0] thrd_6_i, // thread
// data I/O
input wire [IM_DATA_W-1:0] im_data_i, // immediate data
input wire [DATA_W/2-1:0] dm_data_i, // dmem read data
input wire [ADDR_W-1:0] pc_3_i, // program counter
output wire [DATA_W-1:0] a_o, // a
output wire [DATA_W-1:0] b_o, // b
// flags
output wire nez_o, // a != 0
output wire ne_o, // a != b
output wire ltz_o, // a < 0
output wire lt_o, // a < b
// errors
output wire [STACKS-1:0] pop_er_o, // pop when empty, active high
output wire [STACKS-1:0] push_er_o // push when full, active high
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire [DATA_W-1:0] b_alu;
wire [DATA_W-1:0] pop_data0, pop_data1, pop_data2, pop_data3, push_data;
wire [PNTR_W-1:0] pntr0, pntr1, pntr2, pntr3;
wire [STACKS-1:0] stk_wr;
 
 
 
/*
================
== code start ==
================
*/
 
 
 
// stacks output mux
stacks_mux
#(
.DATA_W ( DATA_W ),
.STK_W ( STK_W ),
.IM_DATA_W ( IM_DATA_W )
)
stacks_mux
(
.a_sel_i ( a_sel_i ),
.b_sel_i ( b_sel_i ),
.imda_i ( imda_i ),
.pop_data0_i ( pop_data0 ),
.pop_data1_i ( pop_data1 ),
.pop_data2_i ( pop_data2 ),
.pop_data3_i ( pop_data3 ),
.im_data_i ( im_data_i ),
.a_o ( a_o ),
.b_o ( b_o ),
.b_alu_o ( b_alu )
);
 
 
// ALU
alu_top
#(
.REGS_IN ( 1 ),
.REGS_OUT ( 1 ),
.REGS_FLG ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.LG_W ( LG_W )
)
alu_top
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_i ( sgn_i ),
.ext_i ( ext_i ),
.lg_i ( lg_i ),
.add_i ( add_i ),
.sub_i ( sub_i ),
.mul_i ( mul_i ),
.shl_i ( shl_i ),
.cpy_i ( cpy_i ),
.dm_i ( dm_i ),
.rtn_i ( rtn_i ),
.a_i ( a_o ),
.b_i ( b_alu ),
.dm_data_i ( dm_data_i ),
.pc_3_i ( pc_3_i ),
.result_o ( push_data ),
.nez_o ( nez_o ),
.ne_o ( ne_o ),
.ltz_o ( ltz_o ),
.lt_o ( lt_o )
);
 
 
// stack pointer generation & storage
pointer_ring
#(
.THREADS ( THREADS ),
.STACKS ( STACKS ),
.PNTR_W ( PNTR_W ),
.POP_PROT ( POP_PROT ),
.PUSH_PROT ( PUSH_PROT )
)
pointer_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.clr_i ( stk_clr_i ),
.pop_i ( pop_i ),
.push_i ( push_i ),
.pntr0_o ( pntr0 ),
.pntr1_o ( pntr1 ),
.pntr2_o ( pntr2 ),
.pntr3_o ( pntr3 ),
.wr_o ( stk_wr ),
.pop_er_o ( pop_er_o ),
.push_er_o ( push_er_o )
);
 
 
// LIFO stacks memory
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.RD_MODE ( "WR_DATA" )
)
stack0_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr0 } ),
.wr_i ( stk_wr[0] ),
.data_i ( push_data ),
.data_o ( pop_data0 )
);
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.RD_MODE ( "WR_DATA" )
)
stack1_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr1 } ),
.wr_i ( stk_wr[1] ),
.data_i ( push_data ),
.data_o ( pop_data1 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.RD_MODE ( "WR_DATA" )
)
stack2_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr2 } ),
.wr_i ( stk_wr[2] ),
.data_i ( push_data ),
.data_o ( pop_data2 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.RD_MODE ( "WR_DATA" )
)
stack3_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr3 } ),
.wr_i ( stk_wr[3] ),
.data_i ( push_data ),
.data_o ( pop_data3 )
);
 
endmodule
/hive/trunk/v01.09/functions.h
0,0 → 1,55
/*
--------------------------------------------------------------------------------
--
-- Module : functions.h
--
--------------------------------------------------------------------------------
--
-- Function:
-- - A bunch of functions for a stack processor.
--
-- Instantiates:
-- - Nothing.
--
--------------------------------------------------------------------------------
*/
 
 
/*
---------------
-- functions --
---------------
*/
 
 
// returns safe ceiling value of log2(n)
// (for vector sizing we never want less than 1)
// examples:
// clog2(0 thru 2) = 1,
// clog2(3 & 4) = 2,
// clog2(5 thru 8) = 3,
// clog2(9 thru 16) = 4, etc.
function integer clog2;
input integer n;
begin
clog2 = 1;
while ( n > 2 ) begin
n = ( n + 1 ) / 2;
clog2 = clog2 + 1;
end
end
endfunction
 
 
// returns the max of 2 values
function integer max_of_2;
input integer a, b;
begin
if ( a > b ) begin
max_of_2 = a;
end else begin
max_of_2 = b;
end
end
endfunction
 
/hive/trunk/v01.09/pointer_ring.v
0,0 → 1,177
/*
--------------------------------------------------------------------------------
 
Module : pointer_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor stack pointer storage ring.
 
Instantiates:
- (1x) vector_sr.v
 
Notes:
- 8 stage pointer storage ring for four BRAM based LIFOs:
0 : clear applied (& all inputs)
1 : pop applied
2 : push applied; pop errors output
3 : push errors output
6 : pointers & writes output
- Logic assumes pop | push will not be issued simultaneously with clear.
- Externally concatenate thread 6 & pointers to form stack memory addresses.
- Level width is PTR_W+1 to accomodate 0 to 2^n levels (1 + 2n states).
- Empty push is to address 1, full push is to address 0.
- Combo pop/push is accomodated with no net fullness/pointer change.
- Pop when empty is a pop error.
- Push when full is a push error.
- Pop/push when full is NOT an error.
- Pop/push when empty is a pop error ONLY.
- Parameterized stack error handling. If the associated protection is turned on
then pop/push errors are reported but otherwise not acted upon, i.e. errors
will not corrupt fullness/pointers.
 
--------------------------------------------------------------------------------
*/
 
module pointer_ring
#(
parameter integer THREADS = 8, // threads
parameter integer STACKS = 4, // stacks
parameter integer PNTR_W = 5, // stack pointer width
parameter integer POP_PROT = 1, // 1=error protection, 0=none
parameter integer PUSH_PROT = 1 // 1=error protection, 0=none
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire clr_i, // stacks clear
input wire [STACKS-1:0] pop_i, // stacks pop
input wire [STACKS-1:0] push_i, // stacks push
// pointers
output wire [PNTR_W-1:0] pntr0_o, // stack pointer
output wire [PNTR_W-1:0] pntr1_o, // stack pointer
output wire [PNTR_W-1:0] pntr2_o, // stack pointer
output wire [PNTR_W-1:0] pntr3_o, // stack pointer
// write enables
output wire [STACKS-1:0] wr_o, // write enables
// errors
output wire [STACKS-1:0] pop_er_o, // pop when empty, active high
output wire [STACKS-1:0] push_er_o // push when full, active high
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer LEVEL_W = PNTR_W+1; // +1 extra bit
localparam [LEVEL_W-1:0] EMPTY_VAL = 'b0; // empty value
localparam [LEVEL_W-1:0] FULL_VAL = 1'b1 << PNTR_W; // full value
//
integer s, t;
//
reg [LEVEL_W-1:0] level[0:STACKS-1][0:THREADS-1];
//
reg [STACKS-1:0] pop_1, push_1, push_2;
reg [STACKS-1:0] empty_1, full_2;
wire [STACKS-1:0] dec_1, inc_2;
reg [STACKS-1:0] pop_er_2, push_er_3;
 
 
/*
================
== code start ==
================
*/
 
 
// pipeline control signals
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
pop_1 <= 'b0;
push_1 <= 'b0;
push_2 <= 'b0;
end else begin
pop_1 <= pop_i;
push_1 <= push_i;
push_2 <= push_1;
end
end
 
// decode watermarks
always @ ( * ) begin
for ( s=0; s<STACKS; s=s+1 ) begin
empty_1[s] <= ( level[s][1] == EMPTY_VAL );
full_2[s] <= ( level[s][2] == FULL_VAL );
end
end
 
// prohibit pointer changes @ errors if configured to do so
assign dec_1 = ( POP_PROT ) ? pop_1 & ~empty_1 : pop_1;
assign inc_2 = ( PUSH_PROT ) ? push_2 & ~full_2 : push_2;
 
// decode & register errors - pop when empty, push when full
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
pop_er_2 <= 'b0;
push_er_3 <= 'b0;
end else begin
pop_er_2 <= pop_1 & empty_1;
push_er_3 <= push_2 & full_2;
end
end
 
// decode & pipeline levels
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
for ( s=0; s<STACKS; s=s+1 ) begin
for ( t=0; t<THREADS; t=t+1 ) begin
level[s][t] <= 'b0;
end
end
end else begin
for ( s=0; s<STACKS; s=s+1 ) begin
for ( t=0; t<THREADS; t=t+1 ) begin
if ( t == 0 ) level[s][t] <= level[s][THREADS-1]; // wrap around
else if ( t == 1 ) level[s][t] <= ( clr_i ) ? 1'b0 : level[s][t-1]; // clear
else if ( t == 2 ) level[s][t] <= ( dec_1[s] ) ? level[s][t-1] - 1'b1 : level[s][t-1]; // pop
else if ( t == 3 ) level[s][t] <= ( inc_2[s] ) ? level[s][t-1] + 1'b1 : level[s][t-1]; // push
else level[s][t] <= level[s][t-1];
end
end
end
end
 
 
// decode & pipeline write enables
vector_sr
#(
.REGS ( 4 ),
.DATA_W ( STACKS ),
.RESET_VAL ( 0 )
)
wr_pipe
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( inc_2 ),
.data_o ( wr_o )
);
 
 
// output pointers
assign pntr0_o = level[0][6][PNTR_W-1:0];
assign pntr1_o = level[1][6][PNTR_W-1:0];
assign pntr2_o = level[2][6][PNTR_W-1:0];
assign pntr3_o = level[3][6][PNTR_W-1:0];
// output errors
assign pop_er_o = pop_er_2;
assign push_er_o = push_er_3;
 
 
endmodule
/hive/trunk/v01.09/control_ring.v
0,0 → 1,292
/*
--------------------------------------------------------------------------------
 
Module : control_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor control path.
 
Instantiates:
- (1x) thread_ring.v
- (2x) event_ctrl.v
- (1x) cond_test.v
- (1x) op_decode.v
- (1x) pc_ring.v
 
Notes:
- 8 stage data pipeline consisting of several storage rings.
 
--------------------------------------------------------------------------------
*/
 
module control_ring
#(
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3, // thread width
parameter integer STACKS = 4, // number of stacks
parameter integer STK_W = 2, // stack selector width
parameter integer IM_DATA_W = 8, // immediate data width
parameter integer IM_ADDR_W = 6, // immediate data width
parameter integer OP_CODE_W = 16, // opcode width
parameter integer LG_W = 2, // logical operation width
parameter [ADDR_W-1:0] CLR_BASE = 'h0, // clear address base (concat)
parameter integer CLR_SPAN = 0, // clear address span (2^n)
parameter [ADDR_W-1:0] INTR_BASE = 'h8, // interrupt address base (concat)
parameter integer INTR_SPAN = 0 // interrupt address span (2^n)
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [THREADS-1:0] clr_req_i, // clear request, active high
output wire [THREADS-1:0] clr_ack_o, // clear ack, active high until serviced
input wire [THREADS-1:0] intr_en_i, // interrupt enable, active high
input wire [THREADS-1:0] intr_req_i, // interrupt request, active high
output wire [THREADS-1:0] intr_ack_o, // interrupt ack, active high until serviced
input wire [OP_CODE_W-1:0] op_code_i, // opcode
output wire op_code_er_o, // 1=illegal op code encountered
// ALU I/O
input wire [DATA_W/2-1:0] b_lo_i, // b_lo
output wire [IM_DATA_W-1:0] im_data_o, // immediate data
output wire [STK_W-1:0] a_sel_o, // stack selector
output wire [STK_W-1:0] b_sel_o, // stack selector
output wire imda_o, // 1=immediate data
output wire sgn_o, // 1=signed
output wire ext_o, // 1=extended
output wire [LG_W-1:0] lg_o, // see decode in notes
output wire add_o, // 1=add
output wire sub_o, // 1=subtract
output wire mul_o, // 1=multiply
output wire shl_o, // 1=shift left
output wire cpy_o, // 1=copy b
output wire dm_o, // 1=data mem
output wire rtn_o, // 1=return pc
output wire rd_o, // 1=read
output wire wr_o, // 1=write
// stack I/O
output wire stk_clr_o, // stacks clear
output wire [STACKS-1:0] pop_o, // stacks pop
output wire [STACKS-1:0] push_o, // stacks push
// flags
input wire nez_i, // a != 0
input wire ne_i, // a != b
input wire ltz_i, // a < 0
input wire lt_i, // a < b
// threads
output wire [THRD_W-1:0] thrd_0_o,
output wire [THRD_W-1:0] thrd_2_o,
output wire [THRD_W-1:0] thrd_3_o,
output wire [THRD_W-1:0] thrd_6_o,
// addresses
output wire [IM_ADDR_W-1:0] im_addr_o, // immediate address (offset)
output wire [ADDR_W-1:0] pc_1_o,
output wire [ADDR_W-1:0] pc_3_o,
output wire [ADDR_W-1:0] pc_4_o
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire pc_clr, lit, jmp, gto, intr, imad, tst_2;
wire stk_clr;
wire [STACKS-1:0] pop, push;
wire tst_eq, tst_lt, tst_gt, tst_ab;
wire thrd_clr, thrd_intr;
wire [THRD_W-1:0] thrd_5;
 
 
 
/*
================
== code start ==
================
*/
 
 
// establish threads
thread_ring
#(
.THRD_W ( THRD_W )
)
thread_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_0_o ( thrd_0_o ),
.thrd_1_o ( ),
.thrd_2_o ( thrd_2_o ),
.thrd_3_o ( thrd_3_o ),
.thrd_4_o ( ),
.thrd_5_o ( thrd_5 ),
.thrd_6_o ( thrd_6_o ),
.thrd_7_o ( )
);
 
 
// handle external thread clear requests
event_ctrl
#(
.REGS_REQ ( 0 ), // don't resync
.EDGE_REQ ( 1 ), // edge sensitive
.RESET_VAL ( { THREADS{ 1'b1 } } ), // clear threads @ power-up
.THREADS ( THREADS ),
.THRD_W ( THRD_W )
)
clr_event_ctrl
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_i ( thrd_5 ),
.en_i ( { THREADS{ 1'b1 } } ), // always enable
.req_i ( clr_req_i ),
.ack_o ( clr_ack_o ),
.event_o ( thrd_clr )
);
 
 
// handle external thread interrupt requests
event_ctrl
#(
.REGS_REQ ( 2 ), // resync
.EDGE_REQ ( 1 ), // edge sensitive
.RESET_VAL ( 0 ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W )
)
intr_event_ctrl
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_i ( thrd_5 ),
.en_i ( intr_en_i ),
.req_i ( intr_req_i ),
.ack_o ( intr_ack_o ),
.event_o ( thrd_intr )
);
 
 
// conditional jump etc. testing
cond_test
#(
.REGS_TST ( 2 ),
.REGS_OUT ( 0 )
)
cond_test
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.nez_i ( nez_i ),
.ne_i ( ne_i ),
.ltz_i ( ltz_i ),
.lt_i ( lt_i ),
.tst_eq_i ( tst_eq ),
.tst_lt_i ( tst_lt ),
.tst_gt_i ( tst_gt ),
.tst_ab_i ( tst_ab ),
.tst_o ( tst_2 )
);
 
 
// op_code decoding
op_decode
#(
.REGS_IN ( 0 ),
.REGS_OUT ( 1 ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.DATA_W ( DATA_W ),
.IM_DATA_W ( IM_DATA_W ),
.IM_ADDR_W ( IM_ADDR_W ),
.OP_CODE_W ( OP_CODE_W ),
.LG_W ( LG_W )
)
op_decode
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_clr_i ( thrd_clr ),
.thrd_intr_i ( thrd_intr ),
.op_code_i ( op_code_i ),
.op_code_er_o ( op_code_er_o ),
.im_data_o ( im_data_o ),
.im_addr_o ( im_addr_o ),
.pc_clr_o ( pc_clr ),
.lit_o ( lit ),
.jmp_o ( jmp ),
.gto_o ( gto ),
.intr_o ( intr ),
.tst_eq_o ( tst_eq ),
.tst_lt_o ( tst_lt ),
.tst_gt_o ( tst_gt ),
.tst_ab_o ( tst_ab ),
.stk_clr_o ( stk_clr_o ),
.pop_o ( pop_o ),
.push_o ( push_o ),
.a_sel_o ( a_sel_o ),
.b_sel_o ( b_sel_o ),
.imda_o ( imda_o ),
.imad_o ( imad ),
.sgn_o ( sgn_o ),
.ext_o ( ext_o ),
.lg_o ( lg_o ),
.add_o ( add_o ),
.sub_o ( sub_o ),
.mul_o ( mul_o ),
.shl_o ( shl_o ),
.cpy_o ( cpy_o ),
.dm_o ( dm_o ),
.rtn_o ( rtn_o ),
.rd_o ( rd_o ),
.wr_o ( wr_o )
);
 
 
// pc generation & storage
pc_ring
#(
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.IM_ADDR_W ( IM_ADDR_W ),
.CLR_BASE ( CLR_BASE ),
.CLR_SPAN ( CLR_SPAN ),
.INTR_BASE ( INTR_BASE ),
.INTR_SPAN ( INTR_SPAN )
)
pc_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_0_i ( thrd_0_o ),
.thrd_3_i ( thrd_3_o ),
.clr_i ( pc_clr ),
.lit_i ( lit ),
.jmp_i ( jmp ),
.gto_i ( gto ),
.intr_i ( intr ),
.imad_i ( imad ),
.tst_2_i ( tst_2 ),
.b_lo_i ( b_lo_i ),
.im_addr_i ( im_addr_o ),
.pc_0_o ( ),
.pc_1_o ( pc_1_o ),
.pc_2_o ( ),
.pc_3_o ( pc_3_o ),
.pc_4_o ( pc_4_o ),
.pc_5_o ( ),
.pc_6_o ( ),
.pc_7_o ( )
);
 
 
endmodule
/hive/trunk/v01.09/proc_reg.v
0,0 → 1,242
/*
--------------------------------------------------------------------------------
 
Module: proc_reg.v
 
Function:
- Single processor register w/ multiple type & input options (synchronous).
 
Instantiates:
- Nothing.
 
Notes:
- Init value for each latched bit.
- LIVE_MASK[i]=1 indicates live bit.
- LIVE_MASK[i]=0 indicates dead bit, reads zero.
- Optional resync (2x registering) of inputs.
- Optional edge detection (rising) of inputs.
- data_o is driven non-zero if there is an address match, regardless of
state of rd_i.
- Use large OR gate to combine multiple registers in a set.
 
OUT_MODE:
- "ZERO" : zero out
- "THRU" : no latch, direct connect
- "LTCH" : write latch
- "READ" : no latch, output selected read data
 
READ_MODE:
- "THRU" : no latch, direct connect
- "CORD" : set on input one, clear on read
- "COW1" : set on input one, clear on write one
- "DFFE" : D type flip flop with enable
- "OUT" : no latch, read selected out data
 
--------------------------------------------------------------------------------
*/
 
 
module proc_reg
#(
parameter integer DATA_W = 8, // data width (bits)
parameter integer ADDR_W = 4, // address width (bits)
parameter [ADDR_W-1:0] ADDRESS = 0, // address this register responds to
parameter OUT_MODE = "READ", // modes are: "ZERO", "THRU", "LTCH", "READ"
parameter READ_MODE = "COW1", // modes are: "THRU", "CORD", "COW1", "DFFE", "OUT"
parameter [DATA_W-1:0] LIVE_MASK = { DATA_W{ 1'b1 } }, // 1=live data bit, 0=dead (0)
parameter IN_RESYNC = 0, // 1=resync (double clock) input, 0=no resync
parameter IN_EDGE = 0, // 1=edge (rising) sensitive, 0=level sensitive
parameter [DATA_W-1:0] RESET_VAL = 0 // reset value of latched data
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// bus interface
input wire [ADDR_W-1:0] addr_i, // address
input wire wr_i, // data write enable, active high
input wire rd_i, // data read enable, active high
input wire [DATA_W-1:0] data_i, // write data
output wire [DATA_W-1:0] data_o, // read data
// register interface
output wire reg_wr_o, // reg write active, active high
output wire reg_rd_o, // reg read active, active high
input wire reg_en_i, // reg enable, active high ("DFF" mode only)
input wire [DATA_W-1:0] reg_data_i, // reg data in
output wire [DATA_W-1:0] reg_data_o // reg data out
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire addr_match;
genvar i;
wire [DATA_W-1:0] in_data, out_data, rd_data;
 
 
/*
================
== code start ==
================
*/
 
 
// check for address match
assign addr_match = ( addr_i == ADDRESS[ADDR_W-1:0] );
 
// decode read & write
assign reg_rd_o = ( rd_i & addr_match );
assign reg_wr_o = ( wr_i & addr_match );
 
 
// generate output logic based on mode
generate
for ( i=0; i<DATA_W; i=i+1 ) begin : output_loop
if ( LIVE_MASK[i] ) begin // live bit
case ( OUT_MODE )
"ZERO" : begin
assign out_data[i] = 1'b0;
end
"THRU" : begin
assign out_data[i] = data_i[i];
end
"LTCH" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else begin
if ( reg_wr_o ) begin
reg_bit <= data_i[i];
end
end
end
assign out_data[i] = reg_bit;
end
"READ" : begin
assign out_data[i] = rd_data[i];
end
default : begin // unknown mode!
initial $display ( "OUT_MODE %s does not exist!", OUT_MODE );
end
endcase
end else begin // dead bit
assign out_data[i] = 1'b0;
end
end
endgenerate
 
 
// generate optional input resync & edge detect logic
generate
for ( i=0; i<DATA_W; i=i+1 ) begin : input_processing_loop
if ( LIVE_MASK[i] ) begin // live bit
wire in_2;
if ( IN_RESYNC ) begin
reg in_0, in_1;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
in_0 <= 1'b0;
in_1 <= 1'b0;
end else begin
in_0 <= reg_data_i[i];
in_1 <= in_0;
end
end
assign in_2 = in_1;
end else begin
assign in_2 = reg_data_i[i];
end
//
if ( IN_EDGE ) begin
reg in_3;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
in_3 <= 1'b0;
end else begin
in_3 <= in_2;
end
end
assign in_data[i] = ( in_2 & ~in_3 );
end else begin
assign in_data[i] = in_2;
end
end else begin // dead bit
assign in_data[i] = 1'b0;
end // endif
end // endfor
endgenerate
 
 
// generate read logic based on mode
generate
for ( i=0; i<DATA_W; i=i+1 ) begin : read_loop
if ( LIVE_MASK[i] ) begin // live bit
case ( READ_MODE )
"THRU" : begin
assign rd_data[i] = in_data[i];
end
"CORD" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else begin
if ( reg_rd_o ) begin
reg_bit <= 1'b0;
end else begin
reg_bit <= reg_bit | in_data[i];
end
end
end
assign rd_data[i] = reg_bit;
end
"COW1" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else begin
if ( reg_wr_o ) begin
reg_bit <= reg_bit & ~data_i[i];
end else begin
reg_bit <= reg_bit | in_data[i];
end
end
end
assign rd_data[i] = reg_bit;
end
"DFFE" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else if ( reg_en_i ) begin
reg_bit <= in_data[i];
end
end
assign rd_data[i] = reg_bit;
end
"OUT" : begin
assign rd_data[i] = out_data[i];
end
default : begin // unknown mode!
initial $display ( "RD_MODE %s does not exist!", RD_MODE );
end
endcase
end else begin // dead bit
assign rd_data[i] = 1'b0;
end
end
endgenerate
 
 
// drive outputs
assign data_o = ( addr_match ) ? rd_data : 1'b0;
assign reg_data_o = out_data;
 
 
endmodule
/hive/trunk/v01.09/alu_top.v
0,0 → 1,203
/*
--------------------------------------------------------------------------------
 
Module : alu_top.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor ALU top level.
 
Instantiates:
- (2x) vector_sr.v
- (1x) alu_logical.v
- (4x) vector_sr.v
- (1x) alu_add_sub.v
- (4x) vector_sr.v
- (1x) alu_mult_shift.v
- (3x) vector_sr.v
- (1x) alu_multiply.v
- (1x) vector_sr.v (debug mode only)
- (1x) alu_mux.v
- (4x) vector_sr.v
 
Notes:
- I/O optionally registered.
- 5 stage pipeline w/ 4 mid registers (not counting I/O registering).
 
--------------------------------------------------------------------------------
*/
 
module alu_top
#(
parameter integer REGS_IN = 1, // register option for control and a & b inputs
parameter integer REGS_OUT = 1, // register option for outputs
parameter integer REGS_FLG = 1, // register option for flag outputs
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter integer LG_W = 2 // operation width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire [LG_W-1:0] lg_i, // see decode in notes above
input wire add_i, // 1=add
input wire sub_i, // 1=subtract
input wire mul_i, // 1=multiply
input wire shl_i, // 1=shift left
input wire cpy_i, // 1=copy b
input wire dm_i, // 1=data mem
input wire rtn_i, // 1=return pc
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
input wire [DATA_W/2-1:0] dm_data_i, // dmem read data
input wire [ADDR_W-1:0] pc_3_i, // program counter
output wire [DATA_W-1:0] result_o, // result
// flags
output wire nez_o, // a != 0
output wire ne_o, // a != b
output wire ltz_o, // a < 0
output wire lt_o // a < b
);
 
/*
----------------------
-- internal signals --
----------------------
*/
wire rtn, dm, cpy, shl, mul, sub, add, ext, sgn;
wire [LG_W-1:0] lg;
wire [DATA_W-1:0] a, b;
wire [DATA_W-1:0] res_lg, res_as, res_mid, res_ms;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input regs
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( DATA_W+DATA_W+7+LG_W+2 ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { a_i, b_i, rtn_i, dm_i, cpy_i, shl_i, mul_i, sub_i, add_i, lg_i, ext_i, sgn_i } ),
.data_o ( { a, b, rtn, dm, cpy, shl, mul, sub, add, lg, ext, sgn } )
);
 
 
// logical unit
alu_logical
#(
.REGS_IN ( 0 ),
.REGS_MID ( 1 ),
.REGS_OUT ( 0 ),
.REGS_FLG ( REGS_FLG ),
.DATA_W ( DATA_W ),
.LG_W ( LG_W )
)
alu_logical
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.ext_i ( ext ),
.lg_i ( lg ),
.a_i ( a ),
.b_i ( b ),
.result_o ( res_lg ),
.nez_o ( nez_o ),
.ne_o ( ne_o )
);
 
 
// add & subtract unit
alu_add_sub
#(
.REGS_IN ( 0 ),
.REGS_MID ( 1 ),
.REGS_OUT ( 0 ),
.REGS_FLG ( REGS_FLG ),
.DATA_W ( DATA_W )
)
alu_add_sub
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_i ( sgn ),
.ext_i ( ext ),
.sub_i ( sub ),
.a_i ( a ),
.b_i ( b ),
.result_o ( res_as ),
.ltz_o ( ltz_o ),
.lt_o ( lt_o )
);
 
 
// multiply & shift unit
alu_mult_shift
#(
.REGS_IN ( 0 ),
.REGS_OUT ( 0 ),
.DATA_W ( DATA_W )
)
alu_mult_shift
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_i ( sgn ),
.ext_i ( ext ),
.shl_i ( shl ),
.cpy_i ( cpy ),
.a_i ( a ),
.b_i ( b ),
.result_o ( res_ms )
);
 
 
// multiplexer
alu_mux
#(
.REGS_IN_A ( 1 ),
.REGS_A_B ( 1 ),
.REGS_B_C ( 1 ),
.REGS_C_D ( 1 ),
.REGS_D_OUT ( REGS_OUT ),
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W )
)
alu_mux
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_i ( sgn ),
.ext_i ( ext ),
.as_i ( sub | add ),
.dm_i ( dm ),
.rtn_i ( rtn ),
.ms_i ( cpy | shl | mul ),
.a_lo_i ( a[DATA_W/2-1:0] ),
.res_ms_i ( res_ms ),
.res_lg_i ( res_lg ),
.res_as_i ( res_as ),
.dm_data_i ( dm_data_i ),
.pc_i ( pc_3_i ),
.result_o ( result_o )
);
 
endmodule
/hive/trunk/v01.09/reg_set_addr.h
0,0 → 1,12
// internal register addresses
localparam [15:0] REG_BASE_ADDR = 'hFFF0;
localparam REG_ADDR_W = 4;
//
localparam [REG_ADDR_W-1:0] VER_ADDR = 'h0;
localparam [REG_ADDR_W-1:0] THRD_ID_ADDR = 'h1;
localparam [REG_ADDR_W-1:0] CLR_ADDR = 'h2;
localparam [REG_ADDR_W-1:0] INTR_EN_ADDR = 'h3;
localparam [REG_ADDR_W-1:0] OP_ER_ADDR = 'h4;
localparam [REG_ADDR_W-1:0] STK_ER_ADDR = 'h5;
localparam [REG_ADDR_W-1:0] IO_LO_ADDR = 'h8;
localparam [REG_ADDR_W-1:0] IO_HI_ADDR = 'h9;
/hive/trunk/v01.09/reg_set_shim.v
0,0 → 1,124
/*
--------------------------------------------------------------------------------
 
Module: reg_set_shim.v
 
Function:
- Shim to interface main memory and internal register set.
 
Instantiates:
- (2x) vector_sr.v
 
Notes:
- Address, data, and control I/O optionally registered.
- Register set is placed at the top of memory space, main mem at bottom.
 
--------------------------------------------------------------------------------
*/
 
module reg_set_shim
#(
parameter integer REGS_IN = 1, // register option for inputs
parameter integer REGS_OUT = 1, // register option for outputs
parameter integer DATA_W = 16, // data width (bits)
parameter integer ADDR_W = 8, // address width (bits)
parameter integer REG_ADDR_W = 4, // register set address width (bits)
parameter integer IM_ADDR_W = 4 // immediate address width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire ext_i, // 1=extended result
output wire [DATA_W/2-1:0] wr_data_o, // write data
// address I/O
input wire [DATA_W/2-1:0] b_lo_i, // operand
input wire [IM_ADDR_W-1:0] im_addr_i, // immediate address
input wire [ADDR_W-1:0] pc_1_i, // program counter
output wire [ADDR_W-1:0] addr_o, // address
// bus I/O
input wire wr_i, // data write enable, active high
input wire rd_i, // data read enable, active high
output wire regs_wr_o, // data write enable, active high
output wire regs_rd_o, // data read enable, active high
output wire dm_wr_o // data write enable, active high
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire [DATA_W-1:0] a;
wire [DATA_W/2-1:0] b_lo;
wire [IM_ADDR_W-1:0] im_addr;
wire wr, rd, ext;
wire [ADDR_W-1:0] rw_addr, addr;
wire regs_en, regs_wr, regs_rd, dm_wr;
wire [DATA_W/2-1:0] wr_data;
 
 
 
/*
================
== code start ==
================
*/
 
 
// optional input regs
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( DATA_W+DATA_W/2+IM_ADDR_W+3 ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { a_i, b_lo_i, im_addr_i, wr_i, rd_i, ext_i } ),
.data_o ( { a, b_lo, im_addr, wr, rd, ext } )
);
 
 
// read / write address
assign rw_addr = b_lo + im_addr;
 
// decode address
assign addr = ( rd | wr ) ? rw_addr : pc_1_i;
 
// decode register set address space (all upper bits set)
assign regs_en = &addr[ADDR_W-1:REG_ADDR_W];
// decode regs read & write
assign regs_wr = wr & regs_en;
assign regs_rd = rd & regs_en;
 
// decode dmem write
assign dm_wr = wr & ~regs_en;
 
// decode write data
assign wr_data = ( ext ) ? a[DATA_W-1:DATA_W/2] : a[DATA_W/2-1:0];
 
 
// optional output registers
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( ADDR_W+DATA_W/2+3 ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { addr, wr_data, regs_wr, regs_rd, dm_wr } ),
.data_o ( { addr_o, wr_data_o, regs_wr_o, regs_rd_o, dm_wr_o } )
);
 
 
endmodule
/hive/trunk/v01.09/alu_mux.v
0,0 → 1,192
/*
--------------------------------------------------------------------------------
 
Module : alu_mux.v
 
--------------------------------------------------------------------------------
 
Function:
- Multiplexer for processor ALU.
 
Instantiates:
- (4x) vector_sr.v
 
Notes:
- I/M/O optionally registered.
 
--------------------------------------------------------------------------------
*/
 
module alu_mux
#(
parameter integer REGS_IN_A = 0, // reg option input to mux a
parameter integer REGS_A_B = 0, // reg option mux a to mux b
parameter integer REGS_B_C = 0, // reg option mux b to mux c
parameter integer REGS_C_D = 0, // reg option mux c to mux d
parameter integer REGS_D_OUT = 0, // reg option mux d to output
parameter integer DATA_W = 8, // data width
parameter integer ADDR_W = 4 // address width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended
input wire as_i, // 1=add/subtract
input wire dm_i, // 1=read data
input wire rtn_i, // 1=return pc
input wire ms_i, // 1=multiply
// data I/O
input wire [DATA_W/2-1:0] a_lo_i, // operand
input wire [DATA_W-1:0] res_lg_i, // logical result
input wire [DATA_W-1:0] res_as_i, // add/subtract result
input wire [DATA_W-1:0] res_ms_i, // multiply/shift result
input wire [DATA_W/2-1:0] dm_data_i, // dmem read data
input wire [ADDR_W-1:0] pc_i, // program counter
output wire [DATA_W-1:0] result_o // selected result
);
 
/*
----------------------
-- internal signals --
----------------------
*/
wire ms_a, rtn_a, dm_a, as_a, ext_a, sgn_a;
wire ms_b, rtn_b, dm_b, as_b, ext_b, sgn_b;
wire ms_c, dm_c, as_c, ext_c, sgn_c;
wire ms_d;
wire [DATA_W/2-1:0] a_lo_a;
reg [DATA_W-1:0] mux_a, mux_b, mux_c, mux_d;
wire [DATA_W-1:0] mux_a_b, mux_b_c, mux_c_d;
 
 
/*
================
== code start ==
================
*/
 
 
// input to mux a regs
vector_sr
#(
.REGS ( REGS_IN_A ),
.DATA_W ( DATA_W/2+6 ),
.RESET_VAL ( 0 )
)
in_a_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { a_lo_i, ms_i, rtn_i, dm_i, as_i, ext_i, sgn_i } ),
.data_o ( { a_lo_a, ms_a, rtn_a, dm_a, as_a, ext_a, sgn_a } )
);
 
 
// mux a
always @ ( * ) begin
casex ( { dm_a, as_a } )
'b00 : mux_a <= res_lg_i;
'b01 : mux_a <= res_as_i;
'b1x : mux_a <= a_lo_a;
endcase
end
 
 
// mux a to mux b regs
vector_sr
#(
.REGS ( REGS_A_B ),
.DATA_W ( DATA_W+5 ),
.RESET_VAL ( 0 )
)
a_b_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { mux_a, ms_a, rtn_a, dm_a, ext_a, sgn_a } ),
.data_o ( { mux_a_b, ms_b, rtn_b, dm_b, ext_b, sgn_b } )
);
 
 
// mux b
always @ ( * ) begin
case ( rtn_b )
'b0 : mux_b <= mux_a_b;
'b1 : mux_b <= pc_i;
endcase
end
 
// mux b to mux c regs
vector_sr
#(
.REGS ( REGS_B_C ),
.DATA_W ( DATA_W+4 ),
.RESET_VAL ( 0 )
)
b_c_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { mux_b, ms_b, dm_b, ext_b, sgn_b } ),
.data_o ( { mux_b_c, ms_c, dm_c, ext_c, sgn_c } )
);
 
 
// mux c
always @ ( * ) begin
casex ( { dm_c, ext_c, sgn_c } )
'b0xx : mux_c <= mux_b_c;
'b100 : mux_c <= dm_data_i;
'b101 : mux_c <= $signed( dm_data_i );
'b11x : mux_c <= { dm_data_i, mux_b_c[DATA_W/2-1:0] };
endcase
end
 
 
// mux c to mux d regs
vector_sr
#(
.REGS ( REGS_C_D ),
.DATA_W ( DATA_W+1 ),
.RESET_VAL ( 0 )
)
c_d_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { mux_c, ms_c } ),
.data_o ( { mux_c_d, ms_d } )
);
 
 
// mux c
always @ ( * ) begin
case ( ms_d )
'b0 : mux_d <= mux_c_d;
'b1 : mux_d <= res_ms_i;
endcase
end
 
 
// mux d to output regs
vector_sr
#(
.REGS ( REGS_D_OUT ),
.DATA_W ( DATA_W ),
.RESET_VAL ( 0 )
)
d_out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( mux_d ),
.data_o ( result_o )
);
 
 
endmodule
/hive/trunk/v01.09/alu_logical.v
0,0 → 1,184
/*
--------------------------------------------------------------------------------
 
Module : alu_logical.v
 
--------------------------------------------------------------------------------
 
Function:
- Logic unit for a processor ALU.
 
Instantiates:
- (4x) vector_sr.v
 
Notes:
- IN/MID/OUT/FLG optionally registered.
- lg_i / result_o decode:
 
lg result
--- --
00 a and b
01 a or b
10 a xor b
11 not( b )
 
lg result (ext)
--- -----
00 and( b ) bit reduction
01 or( b ) bit reduction
1x xor( b ) bit reduction
 
--------------------------------------------------------------------------------
*/
 
module alu_logical
#(
parameter integer REGS_IN = 1, // register option for inputs
parameter integer REGS_MID = 1, // mid register option
parameter integer REGS_OUT = 1, // register option for outputs
parameter integer REGS_FLG = 1, // register option for flag outputs
parameter integer DATA_W = 2, // data width
parameter integer LG_W = 2 // operation width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire ext_i, // 1=extended result
input wire [LG_W-1:0] lg_i, // see decode in notes above
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output wire [DATA_W-1:0] result_o, // logical result
// flags
output wire nez_o, // a != 0
output wire ne_o // a != b
);
 
/*
----------------------
-- internal signals --
----------------------
*/
wire ext, ext_r;
wire [LG_W-1:0] lg;
wire [DATA_W-1:0] a, b;
reg [DATA_W-1:0] res;
wire [DATA_W-1:0] res_r;
reg res_bit;
wire res_bit_r;
reg [DATA_W-1:0] result;
wire [DATA_W-1:0] a_xor_b;
wire nez, ne;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input registers
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( DATA_W+DATA_W+LG_W+1 ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { a_i, b_i, lg_i, ext_i } ),
.data_o ( { a, b, lg, ext } )
);
 
 
// some intermediate results
assign a_xor_b = a ^ b;
 
// flags
assign nez = |a;
assign ne = |a_xor_b;
 
// multiplex results
always @ ( * ) begin
case ( lg )
'b00 : res <= a & b;
'b01 : res <= a | b;
'b10 : res <= a_xor_b;
'b11 : res <= ~b;
endcase
end
 
// multiplex results
always @ ( * ) begin
casex ( lg )
'b00 : res_bit <= &b;
'b01 : res_bit <= |b;
'b1x : res_bit <= ^b;
endcase
end
 
 
// optional flag regs
vector_sr
#(
.REGS ( REGS_FLG ),
.DATA_W ( 2 ),
.RESET_VAL ( 0 )
)
regs_flags
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { nez, ne } ),
.data_o ( { nez_o, ne_o } )
);
 
 
// optional mid regs
vector_sr
#(
.REGS ( REGS_MID ),
.DATA_W ( DATA_W+2 ),
.RESET_VAL ( 0 )
)
mid_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { res, res_bit, ext } ),
.data_o ( { res_r, res_bit_r, ext_r } )
);
 
 
// multiplex
always @ ( * ) begin
case ( ext_r )
'b0 : result <= res_r;
'b1 : result <= { DATA_W{ res_bit_r } };
endcase
end
 
 
// optional output regs
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( result ),
.data_o ( result_o )
);
 
 
endmodule
/hive/trunk/v01.09/core.qsf
0,0 → 1,63
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
# Date created = 18:34:00 June 06, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# core_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C5E144C8
set_global_assignment -name TOP_LEVEL_ENTITY core
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:34:00 JUNE 06, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VERILOG_FILE core.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE core.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/hive/trunk/v01.09/op_decode.v
0,0 → 1,588
/*
--------------------------------------------------------------------------------
 
Module : op_decode.v
 
--------------------------------------------------------------------------------
 
Function:
- Opcode decoder for processor.
 
Instantiates:
- (2x) vector_sr.v
 
Notes:
- I/O optionally registered.
- Middle register is always present.
- Operates on the current thread in the stage.
 
--------------------------------------------------------------------------------
*/
 
module op_decode
#(
parameter integer REGS_IN = 1, // register option for inputs
parameter integer REGS_OUT = 1, // register option for outputs
parameter integer STACKS = 4, // number of stacks
parameter integer STK_W = 2, // stack selector width
parameter integer DATA_W = 32, // data width
parameter integer IM_DATA_W = 8, // immediate data width
parameter integer IM_ADDR_W = 6, // immediate data width
parameter integer OP_CODE_W = 16, // op code width
parameter integer LG_W = 2 // logical operation width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// state I/O
input wire thrd_clr_i, // thread clear
input wire thrd_intr_i, // thread interrupt
input wire [OP_CODE_W-1:0] op_code_i, // op_code
output wire op_code_er_o, // 1=illegal op code encountered
// data I/O
output wire [IM_DATA_W-1:0] im_data_o, // immediate data
output wire [IM_ADDR_W-1:0] im_addr_o, // immediate address (offset)
// pc pipe control
output wire pc_clr_o, // pc clear
output wire lit_o, // 1 : pc=pc++ for lit
output wire jmp_o, // 1 : pc=pc+B for jump (cond)
output wire gto_o, // 1 : pc=B for goto / gosub (cond)
output wire intr_o, // 1 : pc=intr
// conditional masks
output wire tst_eq_o, // = test
output wire tst_lt_o, // < test
output wire tst_gt_o, // > test
output wire tst_ab_o, // 1=a/b test; 0=a/z test
// stacks control
output wire stk_clr_o, // stacks clear
output wire [STACKS-1:0] pop_o, // stacks pop
output wire [STACKS-1:0] push_o, // stacks push
// alu control
output wire [STK_W-1:0] a_sel_o, // stack selector
output wire [STK_W-1:0] b_sel_o, // stack selector
output wire imda_o, // 1=immediate data
output wire imad_o, // 1=immediate address
output wire sgn_o, // 1=signed
output wire ext_o, // 1=extended
output wire [LG_W-1:0] lg_o, // see decode in notes
output wire add_o, // 1=add
output wire sub_o, // 1=subtract
output wire mul_o, // 1=multiply
output wire shl_o, // 1=shift left
output wire cpy_o, // 1=copy b
output wire dm_o, // 1=data mem
output wire rtn_o, // 1=return pc
output wire rd_o, // 1=read
output wire wr_o // 1=write
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "op_encode.h"
wire thrd_clr, thrd_intr;
wire [OP_CODE_W-1:0] op_code;
reg op_ok, op_code_ok_lo, op_code_ok_hi;
wire op_code_er;
//
reg [IM_DATA_W-1:0] im_data;
reg [IM_ADDR_W-1:0] im_addr;
reg pc_clr;
reg intr, gto, jmp, lit;
reg tst_lo, tst_hi, tst_ab, tst_gt, tst_lt, tst_eq;
reg stk_clr;
reg a_pop, b_pop;
reg push_lo, push_hi;
wire [STACKS-1:0] pop, push;
reg [STK_W-1:0] a_sel, b_sel;
reg imad_6b, imad_5b;
reg imda_8b, imda_6b;
wire imad, imda;
reg rtn, dm, cpy, shl, mul, sub, add, ext, sgn;
reg [LG_W-1:0] lg;
reg rd, wr;
 
 
 
/*
================
== code start ==
================
*/
 
 
// optional input registers
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( 2+OP_CODE_W ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { thrd_clr_i, thrd_intr_i, op_code_i } ),
.data_o ( { thrd_clr, thrd_intr, op_code } )
);
 
 
// instantiate & split out op_code fields
wire [1:0] op_code_a_sel = op_code[1:0];
wire [1:0] op_code_b_sel = op_code[3:2];
wire op_code_a_pop = op_code[4];
wire op_code_b_pop = op_code[5];
wire [9:0] op_code_op = op_code[15:6];
wire [2:0] op_code_tst_hi = op_code[14:12];
wire [2:0] op_code_tst_lo = op_code[8:6];
wire [7:0] op_code_im = op_code[13:6];
//
reg [2:0] tst_hi_field, tst_lo_field;
reg [7:0] im_field;
 
 
// mid register for immediate and test fields
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
tst_hi_field <= 'b0;
tst_lo_field <= 'b0;
im_field <= 'b0;
end else begin
tst_hi_field <= op_code_tst_hi;
tst_lo_field <= op_code_tst_lo;
im_field <= op_code_im;
end
end
 
// mid register if & case: clear, interrupt, and op_code decode
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
op_ok <= 'b0;
op_code_ok_lo <= 'b0;
op_code_ok_hi <= 'b0;
pc_clr <= 'b0;
lit <= 'b0;
jmp <= 'b0;
gto <= 'b0;
intr <= 'b0;
tst_hi <= 'b0;
tst_lo <= 'b0;
tst_ab <= 'b0;
stk_clr <= 'b0;
a_pop <= 'b0;
b_pop <= 'b0;
push_lo <= 'b0;
push_hi <= 'b0;
a_sel <= 'b0;
b_sel <= 'b0;
imad_6b <= 'b0;
imad_5b <= 'b0;
imda_8b <= 'b0;
imda_6b <= 'b0;
sgn <= 'b0;
ext <= 'b0;
lg <= 'b0;
add <= 'b0;
sub <= 'b0;
mul <= 'b0;
shl <= 'b0;
cpy <= 'b0;
dm <= 'b0;
rtn <= 'b0;
rd <= 'b0;
wr <= 'b0;
end else begin
// default values
op_ok <= 'b0; // default is bad op
op_code_ok_lo <= 'b0; // default is bad opcode
op_code_ok_hi <= 'b0; // default is bad opcode
pc_clr <= 'b0; // default is no pc clear
lit <= 'b0; // default is no lit
jmp <= 'b0; // default is no jump
gto <= 'b0; // default is no goto
intr <= 'b0; // default is no interrupt
tst_hi <= 'b0; // default is no test
tst_lo <= 'b0; // default is no test
tst_ab <= 'b0; // default is comparison to zero
stk_clr <= 'b0; // default is no stack clear
a_pop <= op_code_a_pop; // default is op_code directive
b_pop <= op_code_b_pop; // default is op_code directive
push_lo <= 'b0; // default is no push
push_hi <= 'b0; // default is no push
a_sel <= op_code_a_sel; // default is op_code directive
b_sel <= op_code_b_sel; // default is op_code directive
imad_6b <= 'b0; // default is not immediate address
imad_5b <= 'b0; // default is not immediate address
imda_8b <= 'b0; // default is not immediate data
imda_6b <= 'b0; // default is not immediate data
sgn <= 'b1; // default is signed!
ext <= 'b0; // default is unextended
lg <= 'b0; // default is a&b
add <= 'b0; // default is logic
sub <= 'b0; // default is logic
mul <= 'b0; // default is logic
shl <= 'b0; // default is logic
cpy <= 'b0; // default is logic
dm <= 'b0; // default is logic
rtn <= 'b0; // default is logic
rd <= 'b0; // default is don't read
wr <= 'b0; // default is don't write
if ( thrd_clr ) begin
op_ok <= 'b1; // good op
pc_clr <= 'b1; // clear pc
stk_clr <= 'b1; // clear stacks
a_pop <= 'b0; // no pop
b_pop <= 'b0; // no pop
end else if ( thrd_intr ) begin
op_ok <= 'b1; // good op
intr <= 'b1; // don't inc PC
a_pop <= 'b0; // no pop
b_pop <= 'b0; // no pop
push_lo <= 'b1; // push
a_sel <= 'b0; // push return address to stack 0
rtn <= 'b1; // push pc
end else begin
casex ( op_code_op )
///////////////////////////////////////
// immediate read & write - 64 codes //
///////////////////////////////////////
op_rd_i : begin
op_code_ok_lo <= 'b1; // good opcode
push_lo <= 'b1; // push
dm <= 'b1; // dm
rd <= 'b1; // read
end
op_rd_ix : begin
op_code_ok_lo <= 'b1; // good opcode
push_lo <= 'b1; // push
dm <= 'b1; // dm
rd <= 'b1; // read
ext <= 'b1; // extended
end
op_wr_i : begin
op_code_ok_lo <= 'b1; // good opcode
wr <= 'b1; // write
end
op_wr_ix : begin
op_code_ok_lo <= 'b1; // good opcode
wr <= 'b1; // write
ext <= 'b1; // extended
end
////////////////////////////////////////////
// immediate conditional jump - 384 codes //
////////////////////////////////////////////
op_jmp_iez, op_jmp_ilz, op_jmp_ilez : begin
op_code_ok_lo <= 'b1; // good opcode
jmp <= 'b1; // jump
imad_5b <= 'b1; // immediate address
tst_hi <= 'b1; // high field
end
op_jmp_ie, op_jmp_il, op_jmp_ile : begin
op_code_ok_lo <= 'b1; // good opcode
jmp <= 'b1; // jump
imad_5b <= 'b1; // immediate address
tst_hi <= 'b1; // high field
tst_ab <= 'b1; // a & b comparison
end
op_jmp_igz, op_jmp_igez, op_jmp_iglz : begin
op_code_ok_lo <= 'b1; // good opcode
jmp <= 'b1; // jump
imad_5b <= 'b1; // immediate address
tst_hi <= 'b1; // high field
end
op_jmp_iug, op_jmp_iuge, op_jmp_igl : begin // gl is sign neutral
op_code_ok_lo <= 'b1; // good opcode
jmp <= 'b1; // jump
imad_5b <= 'b1; // immediate address
tst_hi <= 'b1; // high field
tst_ab <= 'b1; // a & b comparison
sgn <= 'b0; // unsigned
end
/////////////////////////////////////////////
// immediate unconditional jump - 64 codes //
/////////////////////////////////////////////
op_jmp_i : begin
op_code_ok_lo <= 'b1; // good opcode
jmp <= 'b1; // jump
imad_6b <= 'b1; // immediate address
end
////////////////////////////////
// immediate data - 256 codes //
////////////////////////////////
op_byt_i : begin
op_code_ok_lo <= 'b1; // good opcode
push_lo <= 'b1; // push
imda_8b <= 'b1; // immediate data
cpy <= 'b1; // copy
end
/////////////////////////////////
// immediate shift - 128 codes //
/////////////////////////////////
op_shl_i : begin
op_code_ok_lo <= 'b1; // good opcode
push_lo <= 'b1; // push
imda_6b <= 'b1; // immediate data
shl <= 'b1; // shift left
end
op_shl_iu : begin
op_code_ok_lo <= 'b1; // good opcode
push_lo <= 'b1; // push
imda_6b <= 'b1; // immediate data
shl <= 'b1; // shift left
sgn <= 'b0; // unsigned
end
//////////////////////////////
// immediate add - 64 codes //
//////////////////////////////
op_add_i : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
imda_6b <= 'b1; // immediate data
add <= 'b1; // add
end
/////////////////////////////////////
// conditional jump - 7 of 8 codes //
/////////////////////////////////////
op_jmp_ez, op_jmp_lz, op_jmp_lez, op_jmp_gz, op_jmp_gez, op_jmp_glz, op_jmp : begin
op_code_ok_lo <= 'b1; // good opcode
jmp <= 'b1; // jump
tst_lo <= 'b1; // low field
end
/////////////////////////////////////
// conditional goto - 7 of 8 codes //
/////////////////////////////////////
op_gto_ez, op_gto_lz, op_gto_lez, op_gto_gz, op_gto_gez, op_gto_glz, op_gto : begin
op_code_ok_lo <= 'b1; // good opcode
gto <= 'b1; // goto
tst_lo <= 'b1; // low field
end
////////////////////////
// singles - 48 codes //
////////////////////////
/////////////
// group 1 //
/////////////
op_add : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
add <= 'b1; // add
end
op_add_x : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
add <= 'b1; // add
ext <= 'b1; // extended
end
op_add_ux : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
add <= 'b1; // add
ext <= 'b1; // extended
sgn <= 'b0; // unsigned
end
op_sub : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
sub <= 'b1; // sub
end
op_sub_x : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
sub <= 'b1; // sub
ext <= 'b1; // extended
end
op_sub_ux : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
sub <= 'b1; // sub
ext <= 'b1; // extended
sgn <= 'b0; // unsigned
end
op_mul : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
mul <= 'b1; // multiply
end
op_mul_x : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
mul <= 'b1; // multiply
ext <= 'b1; // extended
end
op_mul_ux : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
mul <= 'b1; // multiply
ext <= 'b1; // extended
sgn <= 'b0; // unsigned
end
op_shl : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
shl <= 'b1; // shift left
end
op_shl_u : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
shl <= 'b1; // shift left
sgn <= 'b0; // unsigned
end
/////////////
// group 2 //
/////////////
op_and : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
end
op_or : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lg <= 'd1;
end
op_xor : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lg <= 'd2;
end
op_not : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lg <= 'd3;
end
op_and_b : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
ext <= 'b1; // extended
end
op_or_b : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lg <= 'd1;
ext <= 'b1; // extended
end
op_xor_b : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lg <= 'd2;
ext <= 'b1; // extended
end
/////////////
// group 3 //
/////////////
op_lit : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lit <= 'b1; // lit
dm <= 'b1; // dm
end
op_lit_u : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lit <= 'b1; // lit
dm <= 'b1; // dm
sgn <= 'b0; // unsigned
end
op_lit_x : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
lit <= 'b1; // lit
dm <= 'b1; // dm
ext <= 'b1; // extended
end
op_cpy : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
cpy <= 'b1; // copy
end
op_pc : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
rtn <= 'b1; // push pc
end
op_gsb : begin
op_code_ok_hi <= 'b1; // good opcode
push_hi <= 'b1; // push
gto <= 'b1; // goto
rtn <= 'b1; // push pc
end
op_cls : begin
op_code_ok_hi <= 'b1; // good opcode
stk_clr <= 'b1; // stack clear
a_pop <= 'b0; // no pop
b_pop <= 'b0; // no pop
end
op_pop : begin
op_code_ok_hi <= 'b1; // good opcode
end
op_nop : begin
op_code_ok_hi <= 'b1; // good opcode
a_pop <= 'b0; // no pop
b_pop <= 'b0; // no pop
end
default: begin
// nothing here
end
endcase
end
end
end
 
// decode test
always @ ( * ) begin
casex ( { tst_hi, tst_lo } )
2'b00 : { tst_gt, tst_lt, tst_eq } <= 3'b111; // default is always
2'b01 : { tst_gt, tst_lt, tst_eq } <= tst_lo_field;
2'b1x : { tst_gt, tst_lt, tst_eq } <= tst_hi_field;
endcase
end
 
// decode immediate data
always @ ( * ) begin
case ( imda_6b )
1'b0 : im_data <= im_field; // byte default
1'b1 : im_data <= $signed( im_field[5:0] ); // signed 6 bit
endcase
end
 
// decode immediate address
always @ ( * ) begin
case ( imad_5b )
1'b0 : im_addr <= im_field[IM_ADDR_W-1:0]; // 6 bit default
1'b1 : im_addr <= $signed( im_field[4:0] ); // signed 5 bit
endcase
end
 
// decode control
assign imda = imda_8b | imda_6b;
assign imad = imad_6b | imad_5b;
 
// decode pop & push
assign pop = ( a_pop << a_sel ) | ( b_pop << b_sel );
assign push = ( ( push_lo | push_hi ) << a_sel );
// decode errors
assign op_code_er = ~( op_ok | op_code_ok_lo | op_code_ok_hi );
 
 
// optional output registers
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( 1+IM_ADDR_W+IM_DATA_W+10+STACKS+STACKS+STK_W+STK_W+9+LG_W+4 ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { op_code_er, im_addr, im_data, pc_clr, intr, gto, jmp, lit, tst_gt, tst_lt, tst_eq, tst_ab, stk_clr, pop, push, a_sel, b_sel, imda, imad, rtn, dm, cpy, shl, mul, sub, add, lg, ext, sgn, rd, wr } ),
.data_o ( { op_code_er_o, im_addr_o, im_data_o, pc_clr_o, intr_o, gto_o, jmp_o, lit_o, tst_gt_o, tst_lt_o, tst_eq_o, tst_ab_o, stk_clr_o, pop_o, push_o, a_sel_o, b_sel_o, imda_o, imad_o, rtn_o, dm_o, cpy_o, shl_o, mul_o, sub_o, add_o, lg_o, ext_o, sgn_o, rd_o, wr_o } )
);
 
endmodule
/hive/trunk/v01.09/pc_ring.v
0,0 → 1,186
/*
--------------------------------------------------------------------------------
 
Module : pc_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor PC storage ring.
 
Instantiates:
- (2x) vector_sr.v
 
Notes:
- 8 stages.
- Loop feedback, so PC interstage pipe registering forms a storage ring.
 
--------------------------------------------------------------------------------
*/
 
module pc_ring
#(
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 2, // thread width
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter integer IM_ADDR_W = 5, // immediate data width
parameter [ADDR_W-1:0] CLR_BASE = 'h8, // clear address base (concat)
parameter integer CLR_SPAN = 0, // clear address span (2^n)
parameter [ADDR_W-1:0] INTR_BASE = 'h0, // interrupt address base (concat)
parameter integer INTR_SPAN = 0 // interrupt address span (2^n)
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [THRD_W-1:0] thrd_0_i, // thread
input wire [THRD_W-1:0] thrd_3_i, // thread
input wire clr_i, // 1=pc clear
input wire lit_i, // 1 : pc=pc++ for lit
input wire jmp_i, // 1 : pc=pc+B for jump (cond)
input wire gto_i, // 1 : pc=B for goto / gosub (cond)
input wire intr_i, // 1 : pc=int
input wire imad_i, // 1=immediate address
input wire tst_2_i, // 1=true; 0=false
// data I/O
input wire [DATA_W/2-1:0] b_lo_i, // b_lo
// address I/O
input wire [IM_ADDR_W-1:0] im_addr_i, // immediate address (offset)
output wire [ADDR_W-1:0] pc_0_o,
output wire [ADDR_W-1:0] pc_1_o,
output wire [ADDR_W-1:0] pc_2_o,
output wire [ADDR_W-1:0] pc_3_o,
output wire [ADDR_W-1:0] pc_4_o,
output wire [ADDR_W-1:0] pc_5_o,
output wire [ADDR_W-1:0] pc_6_o,
output wire [ADDR_W-1:0] pc_7_o
);
 
/*
----------------------
-- internal signals --
----------------------
*/
reg [ADDR_W-1:0] pc[0:THREADS-1];
//
wire [ADDR_W-1:0] clr_addr, intr_addr;
wire intr_2, gto_2, jmp_2, lit_2;
wire intr_3, gto_3;
wire tst_3;
wire signed [DATA_W/2-1:0] b_im, b_im_2, b_im_3;
reg [ADDR_W-1:0] pc_1_mux, pc_3_mux, pc_4_mux;
 
 
 
/*
================
== code start ==
================
*/
 
 
// form the clear address
assign clr_addr[ADDR_W-1:THRD_W+CLR_SPAN] = CLR_BASE[ADDR_W-1:THRD_W+CLR_SPAN];
assign clr_addr[THRD_W+CLR_SPAN-1:0] = thrd_0_i << CLR_SPAN;
 
// mux for clear, next
always @ ( * ) begin
casex ( { clr_i, intr_i } )
'b00 : pc_1_mux <= pc[0] + 1'b1; // inc for next
'b01 : pc_1_mux <= pc[0]; // no change for int
'b1x : pc_1_mux <= clr_addr; // clear
endcase
end
// decode immediate offset
assign b_im = ( imad_i ) ? $signed( im_addr_i ) : $signed( b_lo_i );
 
 
// in to 2 regs
vector_sr
#(
.REGS ( 2 ),
.DATA_W ( DATA_W/2+4 ),
.RESET_VAL ( 0 )
)
regs_in_2
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { b_im, intr_i, gto_i, jmp_i, lit_i } ),
.data_o ( { b_im_2, intr_2, gto_2, jmp_2, lit_2 } )
);
 
 
// mux for lit, jump
always @ ( * ) begin
casex ( { jmp_2, lit_2 } )
3'b00 : pc_3_mux <= pc[2]; // no change
3'b01 : pc_3_mux <= pc[2] + 1'b1; // inc for lit
3'b1x : pc_3_mux <= ( tst_2_i ) ? pc[2] + b_im_2 : pc[2]; // offset for jump
endcase
end
 
 
// 2 to 3 regs
vector_sr
#(
.REGS ( 1 ),
.DATA_W ( DATA_W/2+3 ),
.RESET_VAL ( 0 )
)
regs_2_3
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { b_im_2, intr_2, gto_2, tst_2_i } ),
.data_o ( { b_im_3, intr_3, gto_3, tst_3 } )
);
 
 
// form the interrupt address
assign intr_addr[ADDR_W-1:THRD_W+INTR_SPAN] = INTR_BASE[ADDR_W-1:THRD_W+INTR_SPAN];
assign intr_addr[THRD_W+INTR_SPAN-1:0] = thrd_3_i << INTR_SPAN;
 
// mux for goto, gosub, interrupt
always @ ( * ) begin
casex ( { intr_3, gto_3 } )
'b00 : pc_4_mux <= pc[3]; // no change
'b01 : pc_4_mux <= ( tst_3 ) ? b_im_3 : pc[3]; // absolute goto / gosub
'b1x : pc_4_mux <= intr_addr; // interrupt address
endcase
end
 
// pc storage ring
integer j;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
for ( j = 0; j < THREADS; j = j + 1 ) begin
pc[j] <= 'b0;
end
end else begin
for ( j = 0; j < THREADS; j = j + 1 ) begin
if ( j == 0 ) pc[j] <= pc[THREADS-1]; // wrap around
else if ( j == 1 ) pc[j] <= pc_1_mux;
else if ( j == 3 ) pc[j] <= pc_3_mux;
else if ( j == 4 ) pc[j] <= pc_4_mux;
else pc[j] <= pc[j-1];
end
end
end
 
// output pc
assign pc_0_o = pc[0];
assign pc_1_o = pc[1];
assign pc_2_o = pc[2];
assign pc_3_o = pc[3];
assign pc_4_o = pc[4];
assign pc_5_o = pc[5];
assign pc_6_o = pc[6];
assign pc_7_o = pc[7];
 
 
endmodule
/hive/trunk/v01.09/cond_test.v
0,0 → 1,115
/*
--------------------------------------------------------------------------------
 
Module : cond_test.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor tests for conditional jumps, etc.
 
Instantiates:
- (2x) vector_sr.v
 
Notes:
- Parameterized register(s) test inputs.
- Parameterized register(s) @ output.
 
--------------------------------------------------------------------------------
*/
 
module cond_test
#(
parameter integer REGS_TST = 0, // reg option input to test
parameter integer REGS_OUT = 0 // reg option test to output
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// flags (combinatorial)
input wire nez_i, // a != 0
input wire ne_i, // a != b
input wire ltz_i, // a < 0
input wire lt_i, // a < b
// tests (optionally registered)
input wire tst_gt_i, // > test
input wire tst_lt_i, // < test
input wire tst_eq_i, // = test
input wire tst_ab_i, // 1=a/b test; 0=a/z test
// output (optionally registered)
output wire tst_o // 1=true; 0=false
);
 
/*
----------------------
-- internal signals --
----------------------
*/
wire tst_ab, tst_gt, tst_lt, tst_eq;
wire eqz, gtz;
wire eq, gt;
wire [2:0] t_cat, az_cat, ab_cat;
wire res_az, res_ab, tst;
 
 
/*
================
== code start ==
================
*/
 
 
// input to test regs
vector_sr
#(
.REGS ( REGS_TST ),
.DATA_W ( 4 ),
.RESET_VAL ( 0 )
)
tst_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { tst_ab_i, tst_gt_i, tst_lt_i, tst_eq_i } ),
.data_o ( { tst_ab, tst_gt, tst_lt, tst_eq } )
);
 
// concat tests
assign t_cat = { tst_gt, tst_lt, tst_eq };
 
// decode conditionals, & mask, | bit reduction => results
assign eqz = ~nez_i;
assign gtz = ~( ltz_i | eqz );
assign az_cat = { gtz, ltz_i, eqz };
assign res_az = |( t_cat & az_cat );
//
assign eq = ~ne_i;
assign gt = ~( lt_i | eq );
assign ab_cat = { gt, lt_i, eq };
assign res_ab = |( t_cat & ab_cat );
 
// select result
assign tst = ( tst_ab ) ? res_ab : res_az;
 
 
// result to output regs
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( 1 ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( tst ),
.data_o ( tst_o )
);
 
 
endmodule
/hive/trunk/v01.09/core.vwf
0,0 → 1,4809
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
 
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
 
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 130000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 50.0;
GRID_DUTY_CYCLE = 50;
}
 
SIGNAL("clk_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("intr_req_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 8;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("intr_req_i[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("io_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 32;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("io_i[31]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[30]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[29]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[28]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[27]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[26]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[25]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[24]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[23]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[22]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[21]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[20]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[19]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[18]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[17]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[16]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[15]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[14]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[13]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[12]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[11]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[10]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[9]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[8]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_o")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 32;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("io_o[31]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[30]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[29]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[28]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[27]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[26]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[25]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[24]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[23]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[22]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[21]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[20]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[19]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[18]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[17]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[16]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[15]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[14]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[13]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[12]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[11]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[10]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[9]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[8]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("rst_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 681")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 477")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 1788")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 1264")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 1510")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|vector_sr:regs_in_2|stage[0][2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][45]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][46]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][47]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][48]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][49]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][31]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][30]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][29]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("divider 622")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 16;
LSB_INDEX = 0;
DIRECTION = BURIED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][15]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][14]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][13]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][12]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][11]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][10]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][9]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][8]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("control_ring:control_ring|pc_ring:pc_ring|pc[0][0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
}
 
SIGNAL("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = BURIED;
PARENT = "";
}
 
SIGNAL("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3]";
}
 
SIGNAL("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3]";
}
 
SIGNAL("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3]";
}
 
SIGNAL("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 32;
LSB_INDEX = 0;
DIRECTION = BURIED;
PARENT = "";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][31]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][30]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][29]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][28]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][27]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][26]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][25]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][24]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][23]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][22]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][21]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][20]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][19]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][18]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][17]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][16]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][15]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][14]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][13]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][12]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][11]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][10]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][9]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][8]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = BURIED;
PARENT = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][32]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][33]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][34]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|thread_ring:thread_ring|thrd_0_o")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 3;
LSB_INDEX = 0;
DIRECTION = REGISTERED;
PARENT = "";
}
 
SIGNAL("control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "control_ring:control_ring|thread_ring:thread_ring|thrd_0_o";
}
 
SIGNAL("control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "control_ring:control_ring|thread_ring:thread_ring|thrd_0_o";
}
 
SIGNAL("control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = REGISTERED;
PARENT = "control_ring:control_ring|thread_ring:thread_ring|thrd_0_o";
}
 
GROUP("io_o_char")
{
MEMBERS = "io_o[31]", "io_o[30]", "io_o[29]", "io_o[28]", "io_o[27]";
}
 
GROUP("io_o_mant")
{
MEMBERS = "io_o[26]", "io_o[25]", "io_o[24]", "io_o[23]", "io_o[22]", "io_o[21]", "io_o[20]", "io_o[19]", "io_o[18]", "io_o[17]", "io_o[16]", "io_o[15]", "io_o[14]", "io_o[13]", "io_o[12]", "io_o[11]", "io_o[10]", "io_o[9]", "io_o[8]", "io_o[7]", "io_o[6]", "io_o[5]", "io_o[4]", "io_o[3]", "io_o[2]", "io_o[1]", "io_o[0]";
}
 
GROUP("test")
{
MEMBERS = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][31]", "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][30]", "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][29]";
}
 
GROUP("im_addr")
{
MEMBERS = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][49]", "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][48]", "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][47]", "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][46]", "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][45]";
}
 
TRANSITION_LIST("clk_i")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 2600;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
 
TRANSITION_LIST("intr_req_i[7]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 12800.0;
LEVEL 1 FOR 49600.0;
LEVEL 0 FOR 25600.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 40400.0;
}
}
 
TRANSITION_LIST("intr_req_i[6]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 38400.0;
LEVEL 1 FOR 24000.0;
LEVEL 0 FOR 22400.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 43600.0;
}
}
 
TRANSITION_LIST("intr_req_i[5]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 57600.0;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 19200.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 46800.0;
}
}
 
TRANSITION_LIST("intr_req_i[4]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 51200.0;
LEVEL 1 FOR 11200.0;
LEVEL 0 FOR 16000.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 50000.0;
}
}
 
TRANSITION_LIST("intr_req_i[3]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 25600.0;
LEVEL 1 FOR 36800.0;
LEVEL 0 FOR 12800.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 53200.0;
}
}
 
TRANSITION_LIST("intr_req_i[2]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 32000.0;
LEVEL 1 FOR 30400.0;
LEVEL 0 FOR 9600.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 56400.0;
}
}
 
TRANSITION_LIST("intr_req_i[1]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 44800.0;
LEVEL 1 FOR 17600.0;
LEVEL 0 FOR 6400.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 59600.0;
}
}
 
TRANSITION_LIST("intr_req_i[0]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 19200.0;
LEVEL 1 FOR 43200.0;
LEVEL 0 FOR 3200.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 62800.0;
}
}
 
TRANSITION_LIST("io_i[31]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[30]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[29]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[28]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[27]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[26]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[25]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[24]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[23]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[22]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[21]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[20]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[19]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[18]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[17]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[16]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[15]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[14]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[13]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[12]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[11]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[10]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 5000.0;
LEVEL 1 FOR 120200.0;
}
}
 
TRANSITION_LIST("io_i[9]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[8]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[7]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[6]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[5]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[4]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 5000.0;
LEVEL 1 FOR 120200.0;
}
}
 
TRANSITION_LIST("io_i[3]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[2]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 5000.0;
LEVEL 1 FOR 120200.0;
}
}
 
TRANSITION_LIST("io_i[1]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 130000.0;
}
}
 
TRANSITION_LIST("io_i[0]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 5000.0;
LEVEL 1 FOR 120200.0;
}
}
 
TRANSITION_LIST("io_o[31]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[30]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[29]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[28]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[27]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[26]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[25]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[24]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[23]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[22]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[21]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[20]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[19]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[18]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[17]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[16]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[15]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[14]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[13]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[12]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[11]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[10]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[9]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[8]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[7]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[6]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[5]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[4]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("io_o[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 130000.0;
}
}
 
TRANSITION_LIST("rst_i")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 129950.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|vector_sr:regs_in_2|stage[0][2]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][45]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][46]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][47]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][48]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][49]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][31]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][30]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][29]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][15]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][14]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][13]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][12]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][11]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][10]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][9]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][8]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][7]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][6]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][5]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][4]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][3]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][2]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][1]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|pc_ring:pc_ring|pc[0][0]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][3]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][2]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][1]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][0]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][31]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][30]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][29]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][28]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][27]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][26]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][25]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][24]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][23]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][22]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][21]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][20]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][19]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][18]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][17]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][16]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][15]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][14]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][13]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][12]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][11]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][10]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][9]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][8]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][7]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][6]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][5]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][4]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][3]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][2]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][1]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][0]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][32]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][33]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][34]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[2]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[1]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
TRANSITION_LIST("control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[0]")
{
NODE
{
REPEAT = 1;
LEVEL U FOR 130000.0;
}
}
 
DISPLAY_LINE
{
CHANNEL = "rst_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "clk_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 681";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i";
EXPAND_STATUS = EXPANDED;
RADIX = Unsigned;
TREE_INDEX = 3;
TREE_LEVEL = 0;
CHILDREN = 4, 5, 6, 7, 8, 9, 10, 11;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 477";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 13;
TREE_LEVEL = 0;
CHILDREN = 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 15;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 16;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 17;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 18;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 19;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 20;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 21;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 22;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 23;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 24;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 25;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 26;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 27;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 28;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 29;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 30;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 31;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 32;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 33;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 34;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 35;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 36;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 37;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 38;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 39;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 40;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 41;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 42;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 43;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 44;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 45;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o_char";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 46;
TREE_LEVEL = 0;
CHILDREN = 47, 48, 49, 50, 51;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 47;
TREE_LEVEL = 1;
PARENT = 46;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 48;
TREE_LEVEL = 1;
PARENT = 46;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 49;
TREE_LEVEL = 1;
PARENT = 46;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 50;
TREE_LEVEL = 1;
PARENT = 46;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 51;
TREE_LEVEL = 1;
PARENT = 46;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o_mant";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 52;
TREE_LEVEL = 0;
CHILDREN = 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 53;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 54;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 55;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 56;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 57;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 58;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 59;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 60;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 61;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 62;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 63;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 64;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 65;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 66;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 67;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 68;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 69;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 70;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 71;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 72;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 73;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 74;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 75;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 76;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 77;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 78;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 79;
TREE_LEVEL = 1;
PARENT = 52;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 80;
TREE_LEVEL = 0;
CHILDREN = 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 81;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 82;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 83;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 84;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 85;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 86;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 87;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 88;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 89;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 90;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 91;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 92;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 93;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 94;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 95;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 96;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 97;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 98;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 99;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 100;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 101;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 102;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 103;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 104;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 105;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 106;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 107;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 108;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 109;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 110;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 111;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 112;
TREE_LEVEL = 1;
PARENT = 80;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 1788";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 113;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "im_addr";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 114;
TREE_LEVEL = 0;
CHILDREN = 115, 116, 117, 118, 119;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][49]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 115;
TREE_LEVEL = 1;
PARENT = 114;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][48]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 116;
TREE_LEVEL = 1;
PARENT = 114;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][47]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 117;
TREE_LEVEL = 1;
PARENT = 114;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][46]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 118;
TREE_LEVEL = 1;
PARENT = 114;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][45]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 119;
TREE_LEVEL = 1;
PARENT = 114;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 622";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 120;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "test";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 121;
TREE_LEVEL = 0;
CHILDREN = 122, 123, 124;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 122;
TREE_LEVEL = 1;
PARENT = 121;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 123;
TREE_LEVEL = 1;
PARENT = 121;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 124;
TREE_LEVEL = 1;
PARENT = 121;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|thread_ring:thread_ring|thrd_0_o";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 125;
TREE_LEVEL = 0;
CHILDREN = 126, 127, 128;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 126;
TREE_LEVEL = 1;
PARENT = 125;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 127;
TREE_LEVEL = 1;
PARENT = 125;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|thread_ring:thread_ring|thrd_0_o[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 128;
TREE_LEVEL = 1;
PARENT = 125;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 129;
TREE_LEVEL = 0;
CHILDREN = 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 130;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 131;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 132;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 133;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 134;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 135;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 136;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 137;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 138;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 139;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 140;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 141;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 142;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 143;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 144;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|pc[0][0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 145;
TREE_LEVEL = 1;
PARENT = 129;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 1264";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 146;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][34]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 147;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][33]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 148;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|op_decode:op_decode|vector_sr:out_regs|stage[0][32]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 149;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 1510";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 150;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "control_ring:control_ring|pc_ring:pc_ring|vector_sr:regs_in_2|stage[0][2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 151;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 152;
TREE_LEVEL = 0;
CHILDREN = 153, 154, 155, 156;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 153;
TREE_LEVEL = 1;
PARENT = 152;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 154;
TREE_LEVEL = 1;
PARENT = 152;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 155;
TREE_LEVEL = 1;
PARENT = 152;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|pointer_ring:pointer_ring|vector_sr:wr_pipe|stage[3][0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 156;
TREE_LEVEL = 1;
PARENT = 152;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 157;
TREE_LEVEL = 0;
CHILDREN = 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 158;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 159;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 160;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 161;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 162;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 163;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 164;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 165;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 166;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 167;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 168;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 169;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 170;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 171;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 172;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 173;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 174;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 175;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 176;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 177;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 178;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 179;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 180;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 181;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 182;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 183;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 184;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 185;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 186;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 187;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 188;
TREE_LEVEL = 1;
PARENT = 157;
}
 
DISPLAY_LINE
{
CHANNEL = "data_ring:data_ring|alu_top:alu_top|alu_mux:alu_mux|vector_sr:d_out_regs|stage[0][0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 189;
TREE_LEVEL = 1;
PARENT = 157;
}
 
TIME_BAR
{
TIME = 16850;
MASTER = TRUE;
}
;
/hive/trunk/v01.09/core.v
0,0 → 1,401
/*
--------------------------------------------------------------------------------
 
Module : core.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor core with 8 stage pipeline, 8 threads, and 4 stacks per thread.
 
Instantiates:
- control_ring.v
- data_ring.v
- reg_set.v
- reg_set_shim.v
- dp_ram_infer.v
 
 
--------------------
- Revision History -
--------------------
 
v01.09 - 2013-06-24
- First public release.
- Shuffled opcode encoding again:
- Unused never jmp_i fits read/write perfectly.
- Unused always jmp_i zero comparison allows for 1 bit immediate field
expansion of jmp_i(gle).
- Removed all skip instructions (redundant w/ jmp_i).
- All the above allows add_i immediate field expansion to 6 bits.
- Opcode encoding is now more straightforward with fewer immediate field sizes.
- Worked on pc_ring.v and pointer_ring.v, now use simple loops rather than
generate, the logic produced better tracks the module paramters.
- Removed "skp" control bit from pc_ring.v, op_decode.v, control_ring.v.
- Removed intr_ack_o from core I/O.
- Renamed "register_set*" => "reg_set*".
- (Considering adding a leading zero count opcode, it doesn't take many LEs.)
- Seeing a write to thread 7 stack 0 memory at startup, don't think it
means anything due to clearing.
- Passes boot code verification for:
- Interrupts.
- Stack ops, depth, error reporting (all threads).
- All branch / conditional ops.
- All logical / arithmetic / shift ops.
 
v01.08 - 2013-06-14
- Added parameter options for stack pointer error protections & brought them
to the top level.
- The unsigned restoring division subroutine works!
 
v01.07 - 2013-06-11
- Changed opcodes to make swapping of (A?B) operands cover all logical needs:
- op_skp_ul => op_skp_l
- op_skp_ge => op_skp_uge
- op_jmp_iul => op_jmp_il
- op_jmp_ige => op_jmp_iuge
- Changed verification boot code tests to reflect above (passes).
 
v01.06 - 2013-06-10
- Fixed latency of test fields in op_decode.v (were only registered 1x, s/b 2x).
- Fixed subtle immediate address offset sign issue in pc_ring.v.
- Fixed subtle immediate data sign issue in stacks_mux.v.
- Minor style edits to align port names @ vector_sr.v instances.
- The log2 subroutine works!
 
v01.05 - 2013-06-07
- Put the skip instructions back (for convenience & clarity).
- Changes to op_decode.v, separate immediate data and address decodes,
misc. edits to improve speed.
- Renamed "op_codes.h" => "op_encode.h".
- Lots of minor edits at the higher levels.
- Added "copyright.txt" to directory.
 
v01.04 - 2013-06-06
- Added op_jmp_i (A?B) instructions.
- Removed all skip instructions (redundant).
 
v01.03 - 2013-06-04
- Changed op_jmp_i to be conditional (A?0).
- Renamed "addr_regs.h" => "register_set_addr.h".
- New boot code does log2.
 
v01.02 (cont) - 2013-05-23
- Old boot code file renamed: "boot_code.h" => "boot_code_00.h".
- New boot code file tests all op_codes and gives final report.
 
v01.02 - 2013-05-22
- Memory writes now work, the fix was to swap pc/op_code ROM side A with
data RW side B of main memory "dp_ram_infer.v". It seems side A is
incorrectly used as the master mode for both ports.
- Renamed "alu_input_mux.v" => "stacks_mux.v".
- Removed enable from "register_set.v" and "register_set_shim.v".
- Monkeyed with "register_set_shim.v" a bit.
- Removed async resets from "dp_ram_infer.v" and "dq_ram_infer.v".
- Passes boot code tests 0, 1, 2, 3, 4.
 
v01.01 - 2013-05-22
- Added clear and interrupt BASE and SPAN parameters.
- Because BASE is a simple MSB concatenation, for it to be effective
make BASE >= 2^(THRD_W+SPAN). BASE LSBs below this point are ignored.
- Individual clear and interrupt address interspacing = 2^SPAN.
- Example:
CLR_BASE ='h0 positions thread 0 clear @ 0.
CLR_SPAN =2 positions thread 1 clear @ 4, thread 2 @ 8, etc.
INTR_BASE='h20 positions thread 0 interrupt @ 'd32.
INTR_SPAN=2 positions thread 1 interrupt @ 'd36, thread 2 @ 'd40, etc.
- Moved most core top port parameters to localparam.
- Modified boot code tests accordingly.
- Passes boot code tests 0, 1, 2.
- Memory writes still don't work!
 
v01.00 - 2013-05-21 - born
- EP3C5E144C8: ~180MHz, ~1785 LEs (34% of logic).
- Fixed immediate value bug (was only registered 1x in op_decode.v, s/b 2x).
- Passes boot code tests 0, 1, 2.
- Memory writes don't work!
 
--------------------------------------------------------------------------------
*/
 
module core
#(
parameter integer DATA_W = 32, // data width
parameter integer THREADS = 8, // threads
parameter [DATA_W/4-1:0] VER_MAJ = 'h01, // core version
parameter [DATA_W/4-1:0] VER_MIN = 'h09 // core version
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
//
input wire [THREADS-1:0] intr_req_i, // event request, active high
//
input wire [DATA_W-1:0] io_i, // gpio
output wire [DATA_W-1:0] io_o
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
//
localparam integer ADDR_W = 16; // address width
localparam integer PNTR_W = 5; // stack pointer width
localparam integer MEM_ADDR_W = 13; // main memory width
localparam [ADDR_W-1:0] CLR_BASE = 'h0; // clear address base (concat)
localparam integer CLR_SPAN = 2; // clear address span (2^n)
localparam [ADDR_W-1:0] INTR_BASE = 'h20; // interrupt address base (concat)
localparam integer INTR_SPAN = 2; // interrupt address span (2^n)
localparam integer THRD_W = clog2( THREADS );
localparam integer STACKS = 4; // number of stacks
localparam integer STK_W = clog2( STACKS );
localparam integer IM_DATA_W = 8; // immediate data width
localparam integer IM_ADDR_W = 6; // immediate address width
localparam integer LG_W = 2;
localparam integer OP_CODE_W = DATA_W/2;
localparam integer REG_ADDR_W = 4;
localparam integer IM_RW_W = 4;
localparam integer POP_PROT = 1; // 1=error protection, 0=none
localparam integer PUSH_PROT = 1; // 1=error protection, 0=none
//
wire [THREADS-1:0] clr_req;
wire [THREADS-1:0] intr_en;
wire [OP_CODE_W-1:0] op_code;
wire op_code_er;
wire [STK_W-1:0] a_sel, b_sel;
wire imda, sgn, ext;
wire [LG_W-1:0] lg;
wire add, sub, mul, shl, cpy, dm, rtn, rd, wr;
wire stk_clr;
wire [STACKS-1:0] pop, push, pop_er, push_er;
wire [DATA_W-1:0] a, b;
wire [IM_DATA_W-1:0] im_data;
wire [IM_ADDR_W-1:0] im_addr;
wire nez, ne, ltz, lt;
wire [THRD_W-1:0] thrd_0, thrd_2, thrd_3, thrd_6;
wire [ADDR_W-1:0] pc_1, pc_3, pc_4;
wire [DATA_W/2-1:0] dm_rd_data;
wire [DATA_W/2-1:0] rd_data, wr_data;
wire [ADDR_W-1:0] addr;
wire regs_wr, regs_rd, dm_wr;
 
 
/*
================
== code start ==
================
*/
 
 
// the control ring
control_ring
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.IM_DATA_W ( IM_DATA_W ),
.IM_ADDR_W ( IM_ADDR_W ),
.OP_CODE_W ( OP_CODE_W ),
.LG_W ( LG_W ),
.CLR_BASE ( CLR_BASE ),
.CLR_SPAN ( CLR_SPAN ),
.INTR_BASE ( INTR_BASE ),
.INTR_SPAN ( INTR_SPAN )
)
control_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.clr_req_i ( clr_req ),
.clr_ack_o ( ), // unused
.intr_en_i ( intr_en ),
.intr_req_i ( intr_req_i ),
.intr_ack_o ( ), // unused
.op_code_i ( op_code ),
.op_code_er_o ( op_code_er ),
.b_lo_i ( b[DATA_W/2-1:0] ),
.im_data_o ( im_data ),
.a_sel_o ( a_sel ),
.b_sel_o ( b_sel ),
.imda_o ( imda ),
.sgn_o ( sgn ),
.ext_o ( ext ),
.lg_o ( lg ),
.add_o ( add ),
.sub_o ( sub ),
.mul_o ( mul ),
.shl_o ( shl ),
.cpy_o ( cpy ),
.dm_o ( dm ),
.rtn_o ( rtn ),
.rd_o ( rd ),
.wr_o ( wr ),
.stk_clr_o ( stk_clr ),
.pop_o ( pop ),
.push_o ( push ),
.nez_i ( nez ),
.ne_i ( ne ),
.ltz_i ( ltz ),
.lt_i ( lt ),
.thrd_0_o ( thrd_0 ),
.thrd_2_o ( thrd_2 ),
.thrd_3_o ( thrd_3 ),
.thrd_6_o ( thrd_6 ),
.im_addr_o ( im_addr ),
.pc_1_o ( pc_1 ),
.pc_3_o ( pc_3 ),
.pc_4_o ( pc_4 )
);
 
 
// the data ring
data_ring
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.PNTR_W ( PNTR_W ),
.IM_DATA_W ( IM_DATA_W ),
.LG_W ( LG_W ),
.POP_PROT ( POP_PROT ),
.PUSH_PROT ( PUSH_PROT )
)
data_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.a_sel_i ( a_sel ),
.b_sel_i ( b_sel ),
.imda_i ( imda ),
.sgn_i ( sgn ),
.ext_i ( ext ),
.lg_i ( lg ),
.add_i ( add ),
.sub_i ( sub ),
.mul_i ( mul ),
.shl_i ( shl ),
.cpy_i ( cpy ),
.dm_i ( dm ),
.rtn_i ( rtn ),
.stk_clr_i ( stk_clr ),
.pop_i ( pop ),
.push_i ( push ),
.thrd_6_i ( thrd_6 ),
.im_data_i ( im_data ),
.dm_data_i ( rd_data ),
.pc_3_i ( pc_3 ),
.a_o ( a ),
.b_o ( b ),
.nez_o ( nez ),
.ne_o ( ne ),
.ltz_o ( ltz ),
.lt_o ( lt ),
.pop_er_o ( pop_er ),
.push_er_o ( push_er )
);
 
 
// shim for memory and register set access
reg_set_shim
#(
.REGS_IN ( 1 ),
.REGS_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.REG_ADDR_W ( REG_ADDR_W ),
.IM_ADDR_W ( IM_RW_W )
)
reg_set_shim
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.a_i ( a ),
.ext_i ( ext ),
.wr_data_o ( wr_data ),
.b_lo_i ( b[DATA_W/2-1:0] ),
.im_addr_i ( im_addr[IM_RW_W-1:0] ),
.pc_1_i ( pc_1 ),
.addr_o ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.regs_wr_o ( regs_wr ),
.regs_rd_o ( regs_rd ),
.dm_wr_o ( dm_wr )
);
 
 
// internal register set
reg_set
#(
.REGS_IN ( 1 ),
.REGS_OUT ( 1 ),
.DATA_W ( DATA_W/2 ),
.ADDR_W ( REG_ADDR_W ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.VER_MAJ ( VER_MAJ ),
.VER_MIN ( VER_MIN )
)
reg_set
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr[REG_ADDR_W-1:0] ),
.wr_i ( regs_wr ),
.rd_i ( regs_rd ),
.data_i ( wr_data ),
.data_o ( rd_data ),
.dm_data_i ( dm_rd_data ),
.clr_req_o ( clr_req ),
.intr_en_o ( intr_en ),
.thrd_0_i ( thrd_0 ),
.op_code_er_i ( op_code_er ),
.thrd_2_i ( thrd_2 ),
.pop_er_i ( pop_er ),
.thrd_3_i ( thrd_3 ),
.push_er_i ( push_er ),
.io_lo_i ( io_i[DATA_W/2-1:0] ),
.io_hi_i ( io_i[DATA_W-1:DATA_W/2] ),
.io_lo_o ( io_o[DATA_W/2-1:0] ),
.io_hi_o ( io_o[DATA_W-1:DATA_W/2] )
);
 
 
// instruction and data memory
dp_ram_infer
#(
.REG_A_OUT ( 1 ),
.REG_B_OUT ( 1 ),
.DATA_W ( OP_CODE_W ),
.ADDR_W ( MEM_ADDR_W ),
.RD_MODE ( "WR_DATA" ) // functional don't care
)
main_mem
(
.a_clk_i ( clk_i ),
.a_addr_i ( addr ),
.a_wr_i ( dm_wr ),
.a_data_i ( wr_data ),
.a_data_o ( dm_rd_data ),
.b_clk_i ( clk_i ),
.b_addr_i ( pc_4 ),
.b_wr_i ( 1'b0 ), // unused
.b_data_i ( ), // unused
.b_data_o ( op_code )
);
 
 
endmodule
/hive/trunk/v01.09/reg_set.v
0,0 → 1,501
/*
--------------------------------------------------------------------------------
 
Module: reg_set.v
 
Function:
- Internal register set for a processor.
 
Instantiates:
- (8x) proc_reg.v
- (2x) vector_sr.v
 
Notes:
- Processor bus IN/OUT optionally registered.
 
Decode:
- 0x0 : Core version register - ver_reg
- 0x1 : Thread ID register - thrd_id_reg
- 0x2 : Clear register - clr_reg
- 0x3 : Interrupt enable register - intr_en_reg
- 0x4 : Opcode error register - op_er_reg
- 0x5 : Stack error register - stk_er_reg
- 0x6 - 0x7 : UNUSED
- 0x8 : I/O low register - io_lo_reg
- 0x9 : I/O high register - io_hi_reg
- 0xA - 0xF : UNUSED
 
 
================================================================================
- 0x0 : Core version register - ver_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 ver_min[7:0] minor version info
15-8 ver_maj[7:0] major version info
 
Notes:
- Read-only.
- Nibbles S/B BCD (0-9; no A-F) to be easily human readable,
and to eliminate confusion between decimal and hex here.
- Major version changes when op_code binary decode changes (incompatibilty).
 
================================================================================
- 0x1 : Thread ID register - thrd_id_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
2-0 thrd_id[2:0] thread ID
15-3 - 0000000000000
 
Notes:
- Read-only.
- Threads can read this to discover their thread ID.
 
================================================================================
- 0x2 : Clear register - clr_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 clr[7:0] 0=>1 clear thread; 1=>0 no effect;
15-8 - 00000000
 
Notes:
- Read / write.
- Per thread clearing.
- All bits cleared on async reset.
 
================================================================================
- 0x3 : Interrupt enable register - intr_en_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 intr_en[7:0] 1=thread interrupt enable; 0=disable
15-8 - 00000000
 
Notes:
- Read / write.
- Per thread enabling of interrupts.
- All bits cleared on async reset.
 
================================================================================
- 0x4 : Opcode error register - op_er_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 op_er[7:0] 1=opcode error; 0=OK
15-8 - 00000000
 
Notes:
- Clear on write one.
- Per thread opcode error reporting.
 
================================================================================
- 0x5 : Stack error register - stk_er_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 pop_er[7:0] 1=lifo pop when empty; 0=OK
15-8 push_er[7:0] 1=lifo push when full; 0=OK
 
Notes:
- Clear on write one.
- Per thread LIFO stack error reporting.
 
================================================================================
- 0x6 - 0x7 : UNUSED
================================================================================
- 0x8 : I/O low register - io_lo_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
15-0 io_lo[15:0] I/O data
 
Notes:
- Separate read / write.
- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
read io_hi_reg for contiguous wide (32 bit) data reads.
- Writes function normally.
 
================================================================================
- 0x9 : I/O high register - io_hi_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
15-0 io_hi[15:0] I/O data
 
Notes:
- Separate read / write.
- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
read io_hi_reg for contiguous wide (32 bit) data reads.
- Writes function normally.
 
================================================================================
- 0xA - 0xF : UNUSED
================================================================================
*/
 
module reg_set
#(
parameter integer REGS_IN = 1, // bus in register option
parameter integer REGS_OUT = 1, // bus out register option
parameter integer DATA_W = 16, // data width (bits)
parameter integer ADDR_W = 4, // address width (bits)
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3, // thread selector width
parameter integer STACKS = 4, // stacks
parameter integer STK_W = 2, // stack selector width
//
parameter [DATA_W/2-1:0] VER_MAJ = 'h1, // core version
parameter [DATA_W/2-1:0] VER_MIN = 'h0
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// bus interface
input wire [ADDR_W-1:0] addr_i, // address
input wire wr_i, // data write enable, active high
input wire rd_i, // data read enable, active high
input wire [DATA_W-1:0] data_i, // write data
output wire [DATA_W-1:0] data_o, // read data
// data memory interface
input wire [DATA_W-1:0] dm_data_i, // dm read data
// clear
output wire [THREADS-1:0] clr_req_o, // clr request, active high
// interrupt
output wire [THREADS-1:0] intr_en_o, // interrupt enable, active high
// errors
input wire [THRD_W-1:0] thrd_0_i, // thread
input wire op_code_er_i, // 1=illegal op code encountered
input wire [THRD_W-1:0] thrd_2_i, // thread
input wire [STACKS-1:0] pop_er_i, // pop when empty, active high
input wire [THRD_W-1:0] thrd_3_i, // thread
input wire [STACKS-1:0] push_er_i, // push when full, active high
// I/O
input wire [DATA_W-1:0] io_lo_i, // gpio linked to io_hi_i
input wire [DATA_W-1:0] io_hi_i,
output wire [DATA_W-1:0] io_lo_o, // unlinked gpio
output wire [DATA_W-1:0] io_hi_o
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "reg_set_addr.h"
//
wire [ADDR_W-1:0] addr;
wire en, reg_en, wr, rd;
wire [DATA_W-1:0] rd_data, wr_data, reg_rd_data;
wire [DATA_W-1:0] ver_data,
thrd_id_data,
clr_data,
intr_en_data,
op_er_data,
stk_er_data,
io_lo_data,
io_hi_data;
//
wire io_lo_reg_rd;
wire [THREADS-1:0] op_code_errors, push_errors, pop_errors;
 
 
 
/*
================
== code start ==
================
*/
 
 
 
// optional bus input regs
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( ADDR_W+2+DATA_W ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { addr_i, wr_i, rd_i, data_i } ),
.data_o ( { addr, wr, rd, wr_data } )
);
 
 
// big ORing of read data
assign rd_data =
ver_data |
thrd_id_data |
clr_data |
intr_en_data |
op_er_data |
stk_er_data |
io_lo_data |
io_hi_data;
 
// decode enable
assign en = ( rd | wr );
 
 
// optional output regs
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( 1+DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { en, rd_data } ),
.data_o ( { reg_en, reg_rd_data } )
);
 
 
// output mux
assign data_o = ( reg_en ) ? reg_rd_data : dm_data_i;
 
 
/*
-------------
-- ver_reg --
-------------
*/
 
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( VER_ADDR ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "THRU" )
)
ver_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( ver_data ),
.reg_data_i ( { VER_MAJ, VER_MIN } )
);
 
 
/*
-----------------
-- thrd_id_reg --
-----------------
*/
 
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( THRD_ID_ADDR ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "THRU" ),
.LIVE_MASK ( { THRD_W{ 1'b1 } } )
)
thrd_id_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( thrd_id_data ),
.reg_data_i ( thrd_3_i )
);
 
 
/*
-------------
-- clr_reg --
-------------
*/
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( CLR_ADDR ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "OUT" ),
.LIVE_MASK ( { THREADS{ 1'b1 } } )
)
clr_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( clr_data ),
.reg_data_o ( clr_req_o )
);
 
/*
-----------------
-- intr_en_reg --
-----------------
*/
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( INTR_EN_ADDR ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "OUT" ),
.LIVE_MASK ( { THREADS{ 1'b1 } } )
)
intr_en_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( intr_en_data ),
.reg_data_o ( intr_en_o )
);
 
/*
---------------
-- op_er_reg --
---------------
*/
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( OP_ER_ADDR ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "COW1" ),
.LIVE_MASK ( { THREADS{ 1'b1 } } )
)
op_er_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( op_er_data ),
.reg_data_i ( op_code_errors )
);
 
// decode errors
assign op_code_errors = op_code_er_i << thrd_0_i;
 
 
/*
----------------
-- stk_er_reg --
----------------
*/
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( STK_ER_ADDR ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "COW1" ),
.LIVE_MASK ( { (THREADS+THREADS){ 1'b1 } } )
)
stk_er_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( stk_er_data ),
.reg_data_i ( { push_errors, pop_errors } )
);
 
// decode errors
assign push_errors = |push_er_i << thrd_3_i;
assign pop_errors = |pop_er_i << thrd_2_i;
 
/*
---------------
-- io_lo_reg --
---------------
*/
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( IO_LO_ADDR ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "THRU" )
)
io_lo_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( io_lo_data ),
.reg_rd_o ( io_lo_reg_rd ),
.reg_data_i ( io_lo_i ),
.reg_data_o ( io_lo_o )
);
 
 
/*
---------------
-- io_hi_reg --
---------------
*/
proc_reg
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( IO_HI_ADDR ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "DFFE" )
)
io_hi_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.data_i ( wr_data ),
.data_o ( io_hi_data ),
.reg_en_i ( io_lo_reg_rd ), // enable on lo read
.reg_data_i ( io_hi_i ),
.reg_data_o ( io_hi_o )
);
 
 
endmodule
/hive/trunk/v01.09/boot_code/boot_code_v_stacks.h
0,0 → 1,314
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
-------------------------
-- external parameters --
-------------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
 
/*
------------------------------------------------------------
-- defines that make programming code more human readable --
------------------------------------------------------------
*/
`define s0 2'd0
`define s1 2'd1
`define s2 2'd2
`define s3 2'd3
`define _ 1'b0
`define P 1'b1
//
`define op_rd_i op_rd_i[9:4]
`define op_rd_ix op_rd_ix[9:4]
`define op_wr_i op_wr_i[9:4]
`define op_wr_ix op_wr_ix[9:4]
//
`define op_jmp_ie op_jmp_ie[9:5]
`define op_jmp_iez op_jmp_iez[9:5]
`define op_jmp_il op_jmp_il[9:5]
`define op_jmp_ilz op_jmp_ilz[9:5]
`define op_jmp_ile op_jmp_ile[9:5]
`define op_jmp_ilez op_jmp_ilez[9:5]
`define op_jmp_iug op_jmp_iug[9:5]
`define op_jmp_igz op_jmp_igz[9:5]
`define op_jmp_iuge op_jmp_iuge[9:5]
`define op_jmp_igez op_jmp_igez[9:5]
`define op_jmp_igl op_jmp_igl[9:5]
`define op_jmp_iglz op_jmp_iglz[9:5]
//
`define op_jmp_i op_jmp_i[9:6]
//
`define op_byt_i op_byt_i[9:8]
//
`define op_shl_i op_shl_i[9:6]
`define op_shl_iu op_shl_iu[9:6]
//
`define op_add_i op_add_i[9:6]
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { op_nop, `_, `_, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test stack 1 for depth and error reporting
// Thread 1 : test stack 1 clear instruction
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h100 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
//
// thread 1
i='h4; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h200 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
// and the rest (are here on Gilligan's Isle)
i='h8; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
 
// test correct stack depth and error reporting, result in s0
// Correct functioning is s0 = 'd6 ('h6).
//
// s0 : final test result
// s1 : test stack
// s2 : sub addr
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h100; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// fill s1
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h940 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
// check for push error
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_shl_iu, -6'd8, `_, `P, `s0, `s0 }; // s0>>8=>s0, pop s0
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// pop&push s/b OK
i=i+1; ram[i] = { op_cpy, `_, `P, `s2, `s1 }; // s2=>s1
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// s/b one push over the line
i=i+1; ram[i] = { op_cpy, `_, `_, `s2, `s1 }; // s2=>s1
// check for a push error
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_shl_iu, -6'd8, `_, `P, `s0, `s0 }; // s0>>8=>s0, pop s0
i=i+1; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s0 }; // (s0<>0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// empty s1
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h950 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// s/b one pop under the line
i=i+1; ram[i] = { op_pop, `_, `P, `s0, `s1 }; // pop s1
// check for a pop error
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_shl_i, 6'd24, `_, `P, `s0, `s0 }; // s0<<24=>s0, pop s0
i=i+1; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s0 }; // (s0<>0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `P, `s3, `s0 }; // s3=>s0, pop both
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
// test stack clearing, result in s0
// Correct functioning is s0 = 'd2 ('h2).
//
// s0 : final test result
// s1 : test stack
// s2 : sub addr
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h200; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// fill s1
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h940 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
// save s3
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'ha00 ; // addr
i=i+1; ram[i] = { `op_wr_i, 4'd0, `P, `_, `s2, `s3 }; // write s3=>(s2+offset), pop s2
// clear all stacks
i=i+1; ram[i] = { op_cls, `_, `_, `s0, `s0 }; // clear stacks
// restore s3
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'ha00 ; // addr
i=i+1; ram[i] = { `op_rd_i, 4'd0, `P, `_, `s2, `s3 }; // read (s2+offset) => s3, pop s2
// fill s1 again
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h940 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `P, `s3, `s0 }; // s3=>s0, pop both
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : read & clear opcode errors for this thread => s0, return to (s3)
i='h900; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { `op_rd_i, OP_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, OP_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
// sub : read & clear stack errors for this thread => s0, return to (s3)
i='h910; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { op_cpy, `_, `_, `s0, `s3 }; // s0=>s3
i=i+1; ram[i] = { `op_shl_i, 6'd8, `_, `P, `s0, `s3 }; // s3<<8=>s3, pop s3
i=i+1; ram[i] = { op_or, `P, `P, `s3, `s0 }; // s0|s3=>s0, pop both
i=i+1; ram[i] = { `op_rd_i, STK_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, STK_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h920; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // read (s1+offset) => s0
i=i+1; ram[i] = { `op_rd_ix, IO_HI_ADDR, `P, `P, `s1, `s0 }; // read (s1+offset) => s0, pop s1 & s0
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h930; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_wr_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // write s0 => (s1+offset)
i=i+1; ram[i] = { `op_wr_ix, IO_HI_ADDR, `P, `_, `s1, `s0 }; // write s0 => (s1+offset), pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
// sub : loop until empty s1 is full, return to (s3)
// loop setup:
i='h940; ram[i] = { `op_byt_i, 8'd32, `_, `_, `s0, `s2 }; // 32=>s2
// loop
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s2 }; // s2--=>s2, pop s2
i=i+1; ram[i] = { op_cpy, `_, `_, `s2, `s1 }; // s2=>s1
i=i+1; ram[i] = { `op_jmp_igz, -5'd3, `_, `_, `s0, `s2 }; // (s2>0) ? do again
i=i+1; ram[i] = { op_gto, `P, `P, `s3, `s2 }; // return, pop s3 & s2
 
// sub : loop until full s1 is empty, return to (s3)
// loop setup:
i='h950; ram[i] = { `op_byt_i, 8'd32, `_, `_, `s0, `s2 }; // 32=>s2
// loop
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s2 }; // s2+1=>s2, pop s2
i=i+1; ram[i] = { op_pop, `_, `P, `s0, `s1 }; // pop s1
i=i+1; ram[i] = { `op_jmp_igz, -5'd3, `_, `_, `s0, `s2 }; // (s2>0) ? do again
i=i+1; ram[i] = { op_gto, `P, `P, `s3, `s2 }; // return, pop s3 & s2
 
 
end
/hive/trunk/v01.09/boot_code/boot_code_log2.h
0,0 → 1,223
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
-------------------------
-- external parameters --
-------------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
 
/*
------------------------------------------------------------
-- defines that make programming code more human readable --
------------------------------------------------------------
*/
`define s0 2'd0
`define s1 2'd1
`define s2 2'd2
`define s3 2'd3
`define _ 1'b0
`define P 1'b1
//
`define op_rd_i op_rd_i[9:4]
`define op_rd_ix op_rd_ix[9:4]
`define op_wr_i op_wr_i[9:4]
`define op_wr_ix op_wr_ix[9:4]
//
`define op_jmp_ie op_jmp_ie[9:5]
`define op_jmp_iez op_jmp_iez[9:5]
`define op_jmp_il op_jmp_il[9:5]
`define op_jmp_ilz op_jmp_ilz[9:5]
`define op_jmp_ile op_jmp_ile[9:5]
`define op_jmp_ilez op_jmp_ilez[9:5]
`define op_jmp_iug op_jmp_iug[9:5]
`define op_jmp_igz op_jmp_igz[9:5]
`define op_jmp_iuge op_jmp_iuge[9:5]
`define op_jmp_igez op_jmp_igez[9:5]
`define op_jmp_igl op_jmp_igl[9:5]
`define op_jmp_iglz op_jmp_iglz[9:5]
//
`define op_jmp_i op_jmp_i[9:6]
//
`define op_byt_i op_byt_i[9:8]
//
`define op_shl_i op_shl_i[9:6]
`define op_shl_iu op_shl_iu[9:6]
//
`define op_add_i op_add_i[9:6]
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { op_nop, `_, `_, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
/*
------------
-- TEST 0 --
------------
*/
 
// Log base 2
// Thread 0 : Get input 32 bit GPIO, calculate log2, output 32 bit GPIO.
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h040 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // goto, pop s1 (addr)
//
i='h4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
// read 32 bit GPIO data to s0
i='h40; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h050 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
 
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h058 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
 
// do log2 of s0
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h060 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
 
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h058 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
 
// loop forever
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h50; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // read (s1+offset) => s0
i=i+1; ram[i] = { `op_rd_ix, IO_HI_ADDR, `P, `P, `s1, `s0 }; // read (s1+offset) => s0, pop s1 & s0
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h58; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_wr_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // write s0 => (s1+offset)
i=i+1; ram[i] = { `op_wr_ix, IO_HI_ADDR, `P, `_, `s1, `s0 }; // write s0 => (s1+offset), pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
// sub : log2(s0)=>s0, return to (s3)
//
// s0 : input, normalize, square, output
// s1 : characteristic (5 MSBs of output) and mantissa (27 LSBs of output)
// s2 : loop index
// s3 : subroutine return address
//
// input 0 is an error, return
i='h60; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s0 }; // (s0!==0) ? skip return
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
// normalize binary search
i=i+1; ram[i] = { `op_byt_i, 8'd31, `_, `_, `s0, `s1 }; // 31=>s1, characteristic
//
i=i+1; ram[i] = { `op_shl_iu, -6'd16, `_, `_, `s0, `s0 }; // s0>>16=>s0
i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
i=i+1; ram[i] = { `op_shl_i, 6'd16, `_, `P, `s0, `s0 }; // s0<<16=>s0, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd16, `_, `P, `s0, `s1 }; // s1-16=>s1, pop s1
//
i=i+1; ram[i] = { `op_shl_iu, -6'd24, `_, `_, `s0, `s0 }; // s0>>24=>s0
i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
i=i+1; ram[i] = { `op_shl_i, 6'd8, `_, `P, `s0, `s0 }; // s0<<8=>s0, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd8, `_, `P, `s0, `s1 }; // s1-8=>s1, pop s1
//
i=i+1; ram[i] = { `op_shl_iu, -6'd28, `_, `_, `s0, `s0 }; // s0>>28=>s0
i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
i=i+1; ram[i] = { `op_shl_i, 6'd4, `_, `P, `s0, `s0 }; // s0<<4=>s0, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd4, `_, `P, `s0, `s1 }; // s1-4=>s1, pop s1
//
i=i+1; ram[i] = { `op_shl_iu, -6'd30, `_, `_, `s0, `s0 }; // s0>>30=>s0
i=i+1; ram[i] = { `op_jmp_iglz, 5'd2, `_, `P, `s0, `s0 }; // (s0<>0) ? jump, pop s0
i=i+1; ram[i] = { `op_shl_i, 6'd2, `_, `P, `s0, `s0 }; // s0<<2=>s0, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s1 }; // s1-2=>s1, pop s1
//
i=i+1; ram[i] = { `op_jmp_ilz, 5'd2, `_, `_, `s0, `s0 }; // (s0<0) ? jump
i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s0 }; // s0<<1=>s0, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s1 }; // s1-1=>s1, pop s1
// loop setup
i=i+1; ram[i] = { `op_byt_i, 8'd27, `_, `_, `s0, `s2 }; // 27=>s2
// square loop
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s2 }; // s2--=>s2, pop s2
i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s1 }; // s1<<1=>s1, pop s1
i=i+1; ram[i] = { op_mul_ux, `_, `P, `s0, `s0 }; // s0*s0=>s0, pop s0
i=i+1; ram[i] = { `op_jmp_igez, 5'd2, `_, `_, `s0, `s0 }; // (s0[31]==0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s1 }; // s1++=>s1, pop s1
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s0, `s0 }; // skip
i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s0 }; // s0<<1=>s0, pop s0
i=i+1; ram[i] = { `op_jmp_igz, -5'd8, `_, `_, `s3, `s2 }; // (s2>0) ? do again
// s1=>s0; cleanup, return
i=i+1; ram[i] = { op_cpy, `P, `P, `s1, `s0 }; // s1=>s0, pop both
i=i+1; ram[i] = { op_gto, `P, `P, `s3, `s2 }; // return, pop s3 & s2
// end sub
 
end
/hive/trunk/v01.09/boot_code/boot_code_divide.h
0,0 → 1,216
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
-------------------------
-- external parameters --
-------------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
 
/*
------------------------------------------------------------
-- defines that make programming code more human readable --
------------------------------------------------------------
*/
`define s0 2'd0
`define s1 2'd1
`define s2 2'd2
`define s3 2'd3
`define _ 1'b0
`define P 1'b1
//
`define op_rd_i op_rd_i[9:4]
`define op_rd_ix op_rd_ix[9:4]
`define op_wr_i op_wr_i[9:4]
`define op_wr_ix op_wr_ix[9:4]
//
`define op_jmp_ie op_jmp_ie[9:5]
`define op_jmp_iez op_jmp_iez[9:5]
`define op_jmp_il op_jmp_il[9:5]
`define op_jmp_ilz op_jmp_ilz[9:5]
`define op_jmp_ile op_jmp_ile[9:5]
`define op_jmp_ilez op_jmp_ilez[9:5]
`define op_jmp_iug op_jmp_iug[9:5]
`define op_jmp_igz op_jmp_igz[9:5]
`define op_jmp_iuge op_jmp_iuge[9:5]
`define op_jmp_igez op_jmp_igez[9:5]
`define op_jmp_igl op_jmp_igl[9:5]
`define op_jmp_iglz op_jmp_iglz[9:5]
//
`define op_jmp_i op_jmp_i[9:6]
//
`define op_byt_i op_byt_i[9:8]
//
`define op_shl_i op_shl_i[9:6]
`define op_shl_iu op_shl_iu[9:6]
//
`define op_add_i op_add_i[9:6]
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { op_nop, `_, `_, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
/*
------------
-- TEST 0 --
------------
*/
 
// Divide - restoring, both inputs positive.
// Thread 0 : Get input 32 bit GPIO 2x, divide, output 32 bit GPIO 2x.
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h040 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // goto, pop s1 (addr)
//
i='h4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
// read 32 bit GPIO data to s0
i='h40; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h060 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
 
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h068 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
 
// read 32 bit GPIO data to s0
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h060 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
 
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h068 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
 
// do s0/s1 divide
i=i+1; ram[i] = { op_cpy, `P, `_, `s0, `s1 }; // s0=>s1, pop s0
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h070 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
 
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h068 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
 
// write s1 data to 32 bit GPIO
i=i+1; ram[i] = { op_cpy, `P, `P, `s1, `s0 }; // s1=>s0, pop both
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h068 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
 
// loop forever
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h60; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // read (s1+offset) => s0
i=i+1; ram[i] = { `op_rd_ix, IO_HI_ADDR, `P, `P, `s1, `s0 }; // read (s1+offset) => s0, pop s1 & s0
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h68; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_wr_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // write s0 => (s1+offset)
i=i+1; ram[i] = { `op_wr_ix, IO_HI_ADDR, `P, `_, `s1, `s0 }; // write s0 => (s1+offset), pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
// sub : divide s0/s1 => result in s0, remainder in s1, return to (s3)
//
// s0 : A input, A/B output
// s1 : B input, A%B output
// s2 : loop index
// s3 : subroutine return address, A%B
//
// 0 input s1 is an error, return
i='h70; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s1 }; // (s1!==0) ? skip return
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
// loop setup
i=i+1; ram[i] = { `op_byt_i, 8'd32, `_, `_, `s0, `s2 }; // 32=>s2
i=i+1; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// divide loop
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s2 }; // s2--=>s2, pop s2
i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s3 }; // s3<<1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igez, 5'd1, `_, `_, `s0, `s0 }; // (s0[31]==0) ? skip
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3++=>s3, pop s3
i=i+1; ram[i] = { `op_shl_i, 6'd1, `_, `P, `s0, `s0 }; // s0<<1=>s0, pop s0
i=i+1; ram[i] = { `op_jmp_iug, 5'd2, `_, `_, `s3, `s1 }; // (s1u>s3) ? jump
i=i+1; ram[i] = { op_sub, `_, `P, `s1, `s3 }; // s3-s1=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s0 }; // s0++=>s0, pop s0
i=i+1; ram[i] = { `op_jmp_igz, -5'd9, `_, `_, `s0, `s2 }; // (s2>0) ? do again
// s3=>s1; cleanup, return
i=i+1; ram[i] = { op_cpy, `P, `P, `s3, `s1 }; // s3=>s1, pop both
i=i+1; ram[i] = { op_gto, `P, `P, `s3, `s2 }; // return to (s3), pop s3 & s2
// end sub
 
end
/hive/trunk/v01.09/boot_code/boot_code_v_interrupts.h
0,0 → 1,186
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
-------------------------
-- external parameters --
-------------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
 
/*
------------------------------------------------------------
-- defines that make programming code more human readable --
------------------------------------------------------------
*/
`define s0 2'd0
`define s1 2'd1
`define s2 2'd2
`define s3 2'd3
`define _ 1'b0
`define P 1'b1
//
`define op_rd_i op_rd_i[9:4]
`define op_rd_ix op_rd_ix[9:4]
`define op_wr_i op_wr_i[9:4]
`define op_wr_ix op_wr_ix[9:4]
//
`define op_jmp_ie op_jmp_ie[9:5]
`define op_jmp_iez op_jmp_iez[9:5]
`define op_jmp_il op_jmp_il[9:5]
`define op_jmp_ilz op_jmp_ilz[9:5]
`define op_jmp_ile op_jmp_ile[9:5]
`define op_jmp_ilez op_jmp_ilez[9:5]
`define op_jmp_iug op_jmp_iug[9:5]
`define op_jmp_igz op_jmp_igz[9:5]
`define op_jmp_iuge op_jmp_iuge[9:5]
`define op_jmp_igez op_jmp_igez[9:5]
`define op_jmp_igl op_jmp_igl[9:5]
`define op_jmp_iglz op_jmp_iglz[9:5]
//
`define op_jmp_i op_jmp_i[9:6]
//
`define op_byt_i op_byt_i[9:8]
//
`define op_shl_i op_shl_i[9:6]
`define op_shl_iu op_shl_iu[9:6]
//
`define op_add_i op_add_i[9:6]
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { op_nop, `_, `_, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : enable interrupts
// All threads : output thread ID @ interrupt
 
///////////////
// clr space //
///////////////
 
// thread 0 : enable interrupts & loop forever
i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h100 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
// all others : loop forever
i='h4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
// all threads : read and output thread ID
i='h20; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
//
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
//
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
//
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
//
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
//
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
//
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
//
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s3 }; // lit => s3
i=i+1; ram[i] = 16'h110 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
///////////////////////
// code & data space //
///////////////////////
 
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : enable all ints, return to (s3)
i='h100; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_byt_i, -8'd1, `_, `_, `s0, `s0 }; // -1=>s0
i=i+1; ram[i] = { `op_wr_i, INTR_EN_ADDR, `P, `P, `s1, `s0 }; // write s0 => (s1+offset), pop both
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
// sub : read thread ID, write to GPIO, pop, return to (s3)
i='h110; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s1, `s0 }; // read (s1+offset) => s0, pop s1
i=i+1; ram[i] = { `op_wr_i, IO_LO_ADDR, `P, `P, `s1, `s0 }; // write s0 => (s1+offset), pop both
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
end
/hive/trunk/v01.09/boot_code/boot_code_v_logic_arith_shift.h
0,0 → 1,512
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
-------------------------
-- external parameters --
-------------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
 
/*
------------------------------------------------------------
-- defines that make programming code more human readable --
------------------------------------------------------------
*/
`define s0 2'd0
`define s1 2'd1
`define s2 2'd2
`define s3 2'd3
`define _ 1'b0
`define P 1'b1
//
`define op_rd_i op_rd_i[9:4]
`define op_rd_ix op_rd_ix[9:4]
`define op_wr_i op_wr_i[9:4]
`define op_wr_ix op_wr_ix[9:4]
//
`define op_jmp_ie op_jmp_ie[9:5]
`define op_jmp_iez op_jmp_iez[9:5]
`define op_jmp_il op_jmp_il[9:5]
`define op_jmp_ilz op_jmp_ilz[9:5]
`define op_jmp_ile op_jmp_ile[9:5]
`define op_jmp_ilez op_jmp_ilez[9:5]
`define op_jmp_iug op_jmp_iug[9:5]
`define op_jmp_igz op_jmp_igz[9:5]
`define op_jmp_iuge op_jmp_iuge[9:5]
`define op_jmp_igez op_jmp_igez[9:5]
`define op_jmp_igl op_jmp_igl[9:5]
`define op_jmp_iglz op_jmp_iglz[9:5]
//
`define op_jmp_i op_jmp_i[9:6]
//
`define op_byt_i op_byt_i[9:8]
//
`define op_shl_i op_shl_i[9:6]
`define op_shl_iu op_shl_iu[9:6]
//
`define op_add_i op_add_i[9:6]
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { op_nop, `_, `_, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test ALU logical functions
// Thread 1 : test ALU arithmetic functions
// Thread 2 : test ALU shift functions
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h100 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
// thread 1
i='h4; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h200 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
// thread 2
i='h8; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h300 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s2, `s0 }; // goto, pop s2 (addr)
// and the rest (are here on Gilligan's Isle)
i='hc; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
 
// test ALU logical functions, result in s0
// Correct functioning is s0 = 'd12 ('hc).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h100; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// load s1 & s2 values
i=i+1; ram[i] = { `op_byt_i, -8'h1, `_, `_, `s1, `s1 }; // -1 => s1
i=i+1; ram[i] = { `op_byt_i, 8'h1, `_, `_, `s2, `s2 }; // 1 => s2
// AND_B ( &(-1)=-1; &(1)= 0 )
i=i+1; ram[i] = { op_and_b, `_, `_, `s1, `s0 }; // &s1=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_and_b, `_, `_, `s2, `s0 }; // &s2=>s0
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// OR_B ( |(-1)=-1; |(1)=-1 )
i=i+1; ram[i] = { op_or_b, `_, `_, `s1, `s0 }; // |s1=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_or_b, `_, `_, `s2, `s0 }; // |s2=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// XOR_B ( ^(-1)= 0; ^(1)=-1 )
i=i+1; ram[i] = { op_xor_b, `_, `_, `s1, `s0 }; // ^s1=>s0
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_xor_b, `_, `_, `s2, `s0 }; // ^s2=>s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `P, `s1, `s0 }; // (s0==-1) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// clean up
i=i+1; ram[i] = { op_pop, `P, `P, `s2, `s1 }; // pop s2 & s1
// load s1 & s2 values
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
i=i+1; ram[i] = 16'ha53c ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
i=i+1; ram[i] = 16'h36c9 ; // hi data
//
i=i+1; ram[i] = { op_lit, `_, `_, `s2, `s2 }; // lit => s2
i=i+1; ram[i] = 16'hc396 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s2, `s2 }; // lit => s2, pop combine
i=i+1; ram[i] = 16'h5ca3 ; // hi data
// AND (s/b 'h1481,8114)
i=i+1; ram[i] = { op_and, `_, `_, `s2, `s1 }; // s1&s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h8114 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h1481 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// OR (s/b 'h7eeb,e7be)
i=i+1; ram[i] = { op_or, `_, `_, `s2, `s1 }; // s1|s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'he7be ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h7eeb ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// XOR (s/b 'h6a6a,66aa)
i=i+1; ram[i] = { op_xor, `_, `_, `s2, `s1 }; // s1^s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h66aa ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h6a6a ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// NOT (s/b 'hc936,5ac3)
i=i+1; ram[i] = { op_not, `_, `_, `s1, `s1 }; // ~s1=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h5ac3 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hc936 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
 
// test ALU arithmetic functions, result in s0
// Correct functioning is s0 = 'd13 ('hd).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h200; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// load s1 & s2 values
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h36c9 ; // hi data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
i=i+1; ram[i] = 16'ha53c ; // lo data
//
i=i+1; ram[i] = { op_lit, `_, `_, `s2, `s2 }; // lit => s2
i=i+1; ram[i] = 16'hc396 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s2, `s2 }; // lit => s2, pop combine
i=i+1; ram[i] = 16'h5ca3 ; // hi data
// ADD_I -32 (s/b 'ha53c,36a9)
i=i+1; ram[i] = { `op_add_i, -6'd32, `_, `_, `s1, `s1 }; // s1-32=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h36a9 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'ha53c ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD_I +31 (s/b 'ha53c,36e8)
i=i+1; ram[i] = { `op_add_i, 6'd31, `_, `_, `s1, `s1 }; // s1+31=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h36e8 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'ha53c ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD (s/b 'h01df,fa5f)
i=i+1; ram[i] = { op_add, `_, `_, `s2, `s1 }; // s1+s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hfa5f ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h01df ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD_X (s/b 0)
i=i+1; ram[i] = { op_add_x, `_, `_, `s2, `s1 }; // s1+s2=>s1
i=i+1; ram[i] = { `op_byt_i, 8'h0, `_, `_, `s0, `s0 }; // 0 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// ADD_UX (s/b 1)
i=i+1; ram[i] = { op_add_ux, `_, `_, `s2, `s1 }; // s1+s2=>s1
i=i+1; ram[i] = { `op_byt_i, 8'h1, `_, `_, `s0, `s0 }; // 1 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SUB (s/b 'h4898,7333)
i=i+1; ram[i] = { op_sub, `_, `_, `s2, `s1 }; // s1-s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h7333 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h4898 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SUB_X (s/b -1)
i=i+1; ram[i] = { op_sub_x, `_, `_, `s2, `s1 }; // s1-s2=>s1
i=i+1; ram[i] = { `op_byt_i, -8'h1, `_, `_, `s0, `s0 }; // -1 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SUB_UX (s/b 0)
i=i+1; ram[i] = { op_sub_ux, `_, `_, `s2, `s1 }; // s1-s2=>s1
i=i+1; ram[i] = { `op_byt_i, 8'h0, `_, `_, `s0, `s0 }; // 0 => s0
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// MUL (s/b 'hccfe,34c6)
i=i+1; ram[i] = { op_mul, `_, `_, `s2, `s1 }; // s1*s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h34c6 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hccfe ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// MUL_X (s/b 'hdf27,93ae)
i=i+1; ram[i] = { op_mul_x, `_, `_, `s2, `s1 }; // s1*s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h93ae ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hdf27 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// MUL_UX (s/b 'h3bcb,5744)
i=i+1; ram[i] = { op_mul_ux, `_, `_, `s2, `s1 }; // s1*s2=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h5744 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h3bcb ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
// test ALU shift functions, result in s0
// Correct functioning is s0 = 'd10 ('ha).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h300; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 0=>s3
// load s1 value 0xa53c36c9
i=i+1; ram[i] = { op_lit, `_, `_, `s1, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h36c9 ; // hi data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s1, `s1 }; // lit => s1, pop combine
i=i+1; ram[i] = 16'ha53c ; // lo data
// SHL_I -28 (s/b 'hffff,fffa)
i=i+1; ram[i] = { `op_shl_i, -6'd28, `_, `_, `s1, `s1 }; // s1<<-28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hfffa ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hffff ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_I +28 (s/b 'h9000,0000)
i=i+1; ram[i] = { `op_shl_i, 6'd28, `_, `_, `s1, `s1 }; // s1<<28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h0000 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h9000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_IU -28 (s/b 'h0000,000a)
i=i+1; ram[i] = { `op_shl_iu, -6'd28, `_, `_, `s1, `s1 }; // s1<<-28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h000a ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h0000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_IU +28 (s/b 'h1000,0000)
i=i+1; ram[i] = { `op_shl_iu, 6'd28, `_, `_, `s1, `s1 }; // 1<<28=>s1
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h0000 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h1000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL -4 (s/b 'hfa53,c36c)
i=i+1; ram[i] = { `op_byt_i, -8'd4, `_, `_, `s2, `s2 }; // -4=>s2
i=i+1; ram[i] = { op_shl, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hc36c ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'hfa53 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL +4 (s/b 'h53c3,6c90)
i=i+1; ram[i] = { `op_byt_i, 8'd4, `_, `_, `s2, `s2 }; // 4=>s2
i=i+1; ram[i] = { op_shl, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h6c90 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h53c3 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL_U -4 (s/b 'h0a53,c36c)
i=i+1; ram[i] = { `op_byt_i, -8'd4, `_, `_, `s2, `s2 }; // -4=>s2
i=i+1; ram[i] = { op_shl_u, `P, `_, `s2, `s1 }; // s1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'hc36c ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h0a53 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// SHL +4 (s/b 'h0000,0010)
i=i+1; ram[i] = { `op_byt_i, 8'd4, `_, `_, `s2, `s2 }; // 4=>s2
i=i+1; ram[i] = { op_shl_u, `P, `_, `s2, `s1 }; // 1<<s2=>s1, pop s2
i=i+1; ram[i] = { op_lit, `_, `_, `s0, `s0 }; // lit => s0
i=i+1; ram[i] = 16'h0010 ; // lo data
i=i+1; ram[i] = { op_lit_x, `_, `P, `s0, `s0 }; // lit => s0, pop combine
i=i+1; ram[i] = 16'h0000 ; // hi data
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `P, `P, `s1, `s0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// check for no stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `P, `s0, `s0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// s3=>s0, loop forever
i=i+1; ram[i] = { op_cpy, `P, `_, `s3, `s0 }; // s3=>s0, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : read & clear opcode errors for this thread => s0, return to (s3)
i='h900; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { `op_rd_i, OP_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, OP_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
// sub : read & clear stack errors for this thread => s0, return to (s3)
i='h910; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { op_cpy, `_, `_, `s0, `s3 }; // s0=>s3
i=i+1; ram[i] = { `op_shl_i, 6'd8, `_, `P, `s0, `s3 }; // s3<<8=>s3, pop s3
i=i+1; ram[i] = { op_or, `P, `P, `s3, `s0 }; // s0|s3=>s0, pop both
i=i+1; ram[i] = { `op_rd_i, STK_ER_ADDR, `_, `_, `s2, `s3 }; // read (s2+offset)=>s3
i=i+1; ram[i] = { op_and, `P, `P, `s3, `s0 }; // s0&s3=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, STK_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
 
end
/hive/trunk/v01.09/boot_code/boot_code_v_branches.h
0,0 → 1,865
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
-------------------------
-- external parameters --
-------------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
 
/*
------------------------------------------------------------
-- defines that make programming code more human readable --
------------------------------------------------------------
*/
`define s0 2'd0
`define s1 2'd1
`define s2 2'd2
`define s3 2'd3
`define _ 1'b0
`define P 1'b1
//
`define op_rd_i op_rd_i[9:4]
`define op_rd_ix op_rd_ix[9:4]
`define op_wr_i op_wr_i[9:4]
`define op_wr_ix op_wr_ix[9:4]
//
`define op_jmp_ie op_jmp_ie[9:5]
`define op_jmp_iez op_jmp_iez[9:5]
`define op_jmp_il op_jmp_il[9:5]
`define op_jmp_ilz op_jmp_ilz[9:5]
`define op_jmp_ile op_jmp_ile[9:5]
`define op_jmp_ilez op_jmp_ilez[9:5]
`define op_jmp_iug op_jmp_iug[9:5]
`define op_jmp_igz op_jmp_igz[9:5]
`define op_jmp_iuge op_jmp_iuge[9:5]
`define op_jmp_igez op_jmp_igez[9:5]
`define op_jmp_igl op_jmp_igl[9:5]
`define op_jmp_iglz op_jmp_iglz[9:5]
//
`define op_jmp_i op_jmp_i[9:6]
//
`define op_byt_i op_byt_i[9:8]
//
`define op_shl_i op_shl_i[9:6]
`define op_shl_iu op_shl_iu[9:6]
//
`define op_add_i op_add_i[9:6]
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { op_nop, `_, `_, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test all jmp_i instructions
// Thread 1 : test all jmp instructions
// Thread 2 : test all gto instructions
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h040 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // goto, pop s1 (addr)
//
i='h4; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h044 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // goto, pop s1 (addr)
//
i='h8; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = 16'h048 ; // addr
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // goto, pop s1 (addr)
//
i='hc; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
i=i+4; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
// thread 0 : do jmp_i tests
i='h40; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h300 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
// loop forever
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
// thread 1 : do jmp tests
i='h44; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h500 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
// loop forever
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
// thread 2 : do gto tests
i='h48; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h700 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
// loop forever
i=i+1; ram[i] = { `op_jmp_i, -6'h1, `_, `_, `s0, `s0 }; // loop forever
 
 
/////////////////
// subroutines //
/////////////////
 
 
 
// sub : test all jmp_i instructions, result in s0, return to (s3)
// Correct functioning is s0 = 'd99 ('h63).
//
// s0 : 0 (ez), final test result
// s1 : +1 (gz)
// s2 : -2 (lz)
// s3 : running test result, subroutine return address
//
// setup test values and running test result:
i='h300; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s0 }; // 0=>s0
i=i+1; ram[i] = { `op_byt_i, 8'd1, `_, `_, `s0, `s1 }; // 1=>s1
i=i+1; ram[i] = { `op_byt_i, -8'd2, `_, `_, `s0, `s2 }; // -2=>s2
i=i+1; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 1=>s1
//
// distance testing
//
i=i+1; ram[i] = { `op_jmp_i, 6'd31, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (won't happen)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd26, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd22, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd18, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd14, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd10, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd6, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd2, `_, `_, `s0, `s1 }; // jump forward
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd16, `_, `_, `s0, `s1 }; // jump forward (and out)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd4, `_, `_, `s0, `s1 }; // jump back
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd8, `_, `_, `s0, `s1 }; // jump back
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd12, `_, `_, `s0, `s1 }; // jump back
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd16, `_, `_, `s0, `s1 }; // jump back
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd20, `_, `_, `s0, `s1 }; // jump back
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd24, `_, `_, `s0, `s1 }; // jump back
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd28, `_, `_, `s0, `s1 }; // jump back
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, -6'd32, `_, `_, `s0, `s1 }; // jump back
//
// unconditional testing
//
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s0, `s1 }; // jump (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s0, `s2 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s0, `s0 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s1, `s1 }; // jump (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s1, `s2 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s1, `s0 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s2, `s1 }; // jump (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s2, `s2 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_i, 6'd1, `_, `_, `s2, `s0 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
// (A?0) testing
// ez
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s1 }; // (s1==0) ? jump (NNY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s2 }; // (s2==0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// lz
i=i+1; ram[i] = { `op_jmp_ilz, 5'd1, `_, `_, `s0, `s1 }; // (s1<0) ? jump (NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ilz, 5'd1, `_, `_, `s0, `s2 }; // (s2<0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ilz, 5'd1, `_, `_, `s0, `s0 }; // (s0<0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// lez
i=i+1; ram[i] = { `op_jmp_ilez, 5'd1, `_, `_, `s0, `s1 }; // (s1<=0) ? jump (NYY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ilez, 5'd1, `_, `_, `s0, `s2 }; // (s2<=0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ilez, 5'd1, `_, `_, `s0, `s0 }; // (s0<=0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// gz
i=i+1; ram[i] = { `op_jmp_igz, 5'd1, `_, `_, `s0, `s1 }; // (s1>0) ? jump (YNN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igz, 5'd1, `_, `_, `s0, `s2 }; // (s2>0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igz, 5'd1, `_, `_, `s0, `s0 }; // (s0>0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// gez
i=i+1; ram[i] = { `op_jmp_igez, 5'd1, `_, `_, `s0, `s1 }; // (s1>=0) ? jump (YNY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igez, 5'd1, `_, `_, `s0, `s2 }; // (s2>=0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igez, 5'd1, `_, `_, `s0, `s0 }; // (s0>=0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// glz
i=i+1; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s1 }; // (s1<>0) ? jump (YYN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s2 }; // (s2<>0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iglz, 5'd1, `_, `_, `s0, `s0 }; // (s0<>0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
// (A?B) testing
//
// e
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s0, `s1 }; // (s1==s0) ? jump (NNY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s0, `s2 }; // (s2==s0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s0, `s0 }; // (s0==s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s1, `s1 }; // (s1==s1) ? jump (YNN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s1, `s2 }; // (s2==s1) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s1, `s0 }; // (s0==s1) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s2, `s1 }; // (s1==s2) ? jump (NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s2, `s2 }; // (s2==s2) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ie, 5'd1, `_, `_, `s2, `s0 }; // (s0==s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// l
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s0, `s1 }; // (s1<s0) ? jump (NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s0, `s2 }; // (s2<s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s0, `s0 }; // (s0<s0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s1, `s1 }; // (s1<s1) ? jump (NYY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s1, `s2 }; // (s2<s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s1, `s0 }; // (s0<s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s2, `s1 }; // (s1<s2) ? jump (NNN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s2, `s2 }; // (s2<s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_il, 5'd1, `_, `_, `s2, `s0 }; // (s0<s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// le
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s0, `s1 }; // (s1<=s0) ? jump (NYY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s0, `s2 }; // (s2<=s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s0, `s0 }; // (s0<=s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s1, `s1 }; // (s1<=s1) ? jump (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s1, `s2 }; // (s2<=s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s1, `s0 }; // (s0<=s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s2, `s1 }; // (s1<=s2) ? jump (NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s2, `s2 }; // (s2<=s2) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_ile, 5'd1, `_, `_, `s2, `s0 }; // (s0<=s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// ug
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s0, `s1 }; // (s1>s0) ? jump (YYN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s0, `s2 }; // (s2>s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s0, `s0 }; // (s0>s0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s1, `s1 }; // (s1>s1) ? jump (NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s1, `s2 }; // (s2>s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s1, `s0 }; // (s0>s1) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s2, `s1 }; // (s1>s2) ? jump (NNN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s2, `s2 }; // (s2>s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iug, 5'd1, `_, `_, `s2, `s0 }; // (s0>s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// uge
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s0, `s1 }; // (s1>=s0) ? jump (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s0, `s2 }; // (s2>=s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s0, `s0 }; // (s0>=s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s1, `s1 }; // (s1>=s1) ? jump (YYN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s1, `s2 }; // (s2>=s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s1, `s0 }; // (s0>=s1) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s2, `s1 }; // (s1>=s2) ? jump (NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s2, `s2 }; // (s2>=s2) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_iuge, 5'd1, `_, `_, `s2, `s0 }; // (s0>=s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// gl
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s0, `s1 }; // (s1<>s0) ? jump (YYN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s0, `s2 }; // (s2<>s0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s0, `s0 }; // (s0<>s0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s1, `s1 }; // (s1<>s1) ? jump (NYY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s1, `s2 }; // (s2<>s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s1, `s0 }; // (s0<>s1) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s2, `s1 }; // (s1<>s2) ? jump (YNY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s2, `s2 }; // (s2<>s2) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { `op_jmp_igl, 5'd1, `_, `_, `s2, `s0 }; // (s0<>s2) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// cleanup
i=i+1; ram[i] = { op_pop, `P, `P, `s2, `s1 }; // pop s1 & s2
// check for opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// check for stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// s3=>s0, return
i=i+1; ram[i] = { op_cpy, `P, `P, `s3, `s0 }; // s3=>s0, pop both
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
// end sub
 
// sub : test all jmp instructions, result in s0, return to (s3)
// Correct functioning is s0 = 'd29 ('h1D).
//
// s0 : 0 (ez), final test result
// s1 : +1 (gz)
// s2 : -2 (lz)
// s3 : running test result, subroutine return address
//
// setup test values and running test result:
i='h500; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s0 }; // 0=>s0
i=i+1; ram[i] = { `op_byt_i, 8'd1, `_, `_, `s0, `s1 }; // 1=>s1
i=i+1; ram[i] = { `op_byt_i, -8'd2, `_, `_, `s0, `s2 }; // -2=>s2
i=i+1; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 1=>s1
//
// distance testing
//
i=i+1; ram[i] = { `op_byt_i, 8'd15, `_, `_, `s0, `s2 }; // 15=>s2
i=i+1; ram[i] = { op_jmp, `P, `_, `s2, `s0 }; // jump forward, pop s2
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_byt_i, 8'd9, `_, `_, `s0, `s2 }; // 9=>s2
i=i+1; ram[i] = { op_jmp, `P, `_, `s2, `s0 }; // jump forward, pop s2
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_byt_i, 8'd3, `_, `_, `s0, `s2 }; // 3=>s2
i=i+1; ram[i] = { op_jmp, `P, `_, `s2, `s0 }; // jump forward, pop s2
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_byt_i, 8'd9, `_, `_, `s0, `s2 }; // 9=>s2
i=i+1; ram[i] = { op_jmp, `P, `_, `s2, `s0 }; // jump forward (and out), pop s2
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_byt_i, -8'd6, `_, `_, `s0, `s2 }; // -6=>s2
i=i+1; ram[i] = { op_jmp, `P, `_, `s2, `s0 }; // jump back, pop s2
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_byt_i, -8'd12, `_, `_, `s0, `s2 }; // -12=>s2
i=i+1; ram[i] = { op_jmp, `P, `_, `s2, `s0 }; // jump back, pop s2
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { `op_byt_i, -8'd18, `_, `_, `s0, `s2 }; // -18=>s2
i=i+1; ram[i] = { op_jmp, `P, `_, `s2, `s0 }; // jump back, pop s2
//
// unconditional testing
//
i=i+1; ram[i] = { op_jmp, `_, `_, `s1, `s1 }; // jump (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp, `_, `_, `s1, `s2 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp, `_, `_, `s1, `s0 }; // jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
// (A?0) testing
// ez
i=i+1; ram[i] = { op_jmp_ez, `_, `_, `s1, `s1 }; // (s1==0) ? jump (NNY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_ez, `_, `_, `s1, `s2 }; // (s2==0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_ez, `_, `_, `s1, `s0 }; // (s0==0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// lz
i=i+1; ram[i] = { op_jmp_lz, `_, `_, `s1, `s1 }; // (s1<0) ? jump (NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_lz, `_, `_, `s1, `s2 }; // (s2<0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_lz, `_, `_, `s1, `s0 }; // (s0<0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// lez
i=i+1; ram[i] = { op_jmp_lez, `_, `_, `s1, `s1 }; // (s1<=0) ? jump (NYY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_lez, `_, `_, `s1, `s2 }; // (s2<=0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_lez, `_, `_, `s1, `s0 }; // (s0<=0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// gz
i=i+1; ram[i] = { op_jmp_gz, `_, `_, `s1, `s1 }; // (s1>0) ? jump (YNN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_gz, `_, `_, `s1, `s2 }; // (s2>0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_gz, `_, `_, `s1, `s0 }; // (s0>0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// gez
i=i+1; ram[i] = { op_jmp_gez, `_, `_, `s1, `s1 }; // (s1>=0) ? jump (YNY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_gez, `_, `_, `s1, `s2 }; // (s2>=0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_gez, `_, `_, `s1, `s0 }; // (s0>=0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// glz
i=i+1; ram[i] = { op_jmp_glz, `_, `_, `s1, `s1 }; // (s1<>0) ? jump (YYN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_glz, `_, `_, `s1, `s2 }; // (s2<>0) ? jump
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_jmp_glz, `_, `_, `s1, `s0 }; // (s0<>0) ? jump
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// cleanup
i=i+1; ram[i] = { op_pop, `P, `P, `s2, `s1 }; // pop s1 & s2
// check for opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// check for stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// s3=>s0, return
i=i+1; ram[i] = { op_cpy, `P, `P, `s3, `s0 }; // s3=>s0, pop both
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
// end sub
 
 
// sub : test all gto instructions, result in s0, return to (s3)
// Correct functioning is s0 = 'd25 ('h19).
//
// s0 : 0 (ez), final test result
// s1 : PC (gz)
// s2 : -2 (lz)
// s3 : running test result, subroutine return address
//
// setup test values and running test result:
i='h700; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s0 }; // 0=>s0
i=i+1; ram[i] = { `op_byt_i, -8'd2, `_, `_, `s0, `s2 }; // -2=>s2
i=i+1; ram[i] = { `op_byt_i, 8'd0, `_, `_, `s0, `s3 }; // 1=>s1
//
// distance testing
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd6, `_, `P, `s0, `s1 }; // s1+6=>s1, pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // go forward, pop s1
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd6, `_, `P, `s0, `s1 }; // s1+6=>s1, pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // go forward, pop s1
//
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, -6'd6, `_, `P, `s0, `s1 }; // s1-6=>s1, pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // go back, pop s1
//
// unconditional testing
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s1 }; // go, pop s1 (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s2 }; // go, pop s1 (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s1, `s0 }; // go, pop s1 (YYY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
// (A?0) testing
// ez
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_ez, `P, `_, `s1, `s1 }; // (s1==0) ? go, pop s1(NNY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_ez, `P, `_, `s1, `s2 }; // (s2==0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_ez, `P, `_, `s1, `s0 }; // (s0==0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// lz
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_lz, `P, `_, `s1, `s1 }; // (s1<0) ? go, pop s1(NYN)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_lz, `P, `_, `s1, `s2 }; // (s2<0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_lz, `P, `_, `s1, `s0 }; // (s0<0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// lez
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_lez, `P, `_, `s1, `s1 }; // (s1<=0) ? go, pop s1(NYY)
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_lez, `P, `_, `s1, `s2 }; // (s2<=0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_lez, `P, `_, `s1, `s0 }; // (s0<=0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// gz
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_gz, `P, `_, `s1, `s1 }; // (s1>0) ? go, pop s1(YNN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_gz, `P, `_, `s1, `s2 }; // (s2>0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_gz, `P, `_, `s1, `s0 }; // (s0>0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// gez
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_gez, `P, `_, `s1, `s1 }; // (s1>=0) ? go, pop s1(YNY)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_gez, `P, `_, `s1, `s2 }; // (s2>=0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_gez, `P, `_, `s1, `s0 }; // (s0>=0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
// glz
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_glz, `P, `_, `s1, `s1 }; // (s1<>0) ? go, pop s1(YYN)
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_glz, `P, `_, `s1, `s2 }; // (s2<>0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `_, `P, `s0, `s3 }; // s3+1=>s3, pop s3
//
i=i+1; ram[i] = { op_pc, `_, `_, `s0, `s1 }; // pc => s1
i=i+1; ram[i] = { `op_add_i, 6'd3, `_, `P, `s0, `s1 }; // s1+3=>s1, pop s1
i=i+1; ram[i] = { op_gto_glz, `P, `_, `s1, `s0 }; // (s0<>0) ? go, pop s1
i=i+1; ram[i] = { `op_add_i, 6'd2, `_, `P, `s0, `s3 }; // s3+2=>s3, pop s3 (N)
i=i+1; ram[i] = { `op_add_i, -6'd1, `_, `P, `s0, `s3 }; // s3-1=>s3, pop s3
// cleanup
i=i+1; ram[i] = { op_pop, `_, `P, `s0, `s2 }; // pop s2
// check for opcode errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h900 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// check for stack errors
i=i+1; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = 16'h910 ; // addr
i=i+1; ram[i] = { op_gsb, `P, `_, `s2, `s3 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `op_jmp_iez, 5'd1, `_, `_, `s0, `s0 }; // (s0==0) ? skip
i=i+1; ram[i] = { `op_add_i, -6'd2, `_, `P, `s0, `s3 }; // s3-2=>s3, pop s3 (Y)
i=i+1; ram[i] = { `op_add_i, 6'd1, `P, `P, `s0, `s3 }; // s3+1=>s3, pop both
// s3=>s0, return
i=i+1; ram[i] = { op_cpy, `P, `P, `s3, `s0 }; // s3=>s0, pop both
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
// end sub
 
 
// sub : read & clear opcode errors for this thread => s0, return to (s3)
i='h900; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { `op_rd_i, OP_ER_ADDR, `_, `_, `s2, `s1 }; // read (s2+offset)=>s1
i=i+1; ram[i] = { op_and, `P, `P, `s1, `s0 }; // s0&s1=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, OP_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
// sub : read & clear stack errors for this thread => s0, return to (s3)
i='h910; ram[i] = { op_lit_u, `_, `_, `s0, `s2 }; // lit => s2
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, THRD_ID_ADDR, `_, `_, `s2, `s0 }; // read (s2+offset)=>s0
i=i+1; ram[i] = { op_shl_u, `_, `P, `s0, `s0 }; // 1<<s0=>s0, pop s0
i=i+1; ram[i] = { op_cpy, `_, `_, `s0, `s1 }; // s0=>s1
i=i+1; ram[i] = { `op_shl_i, 6'd8, `_, `P, `s0, `s1 }; // s1<<8=>s1, pop s1
i=i+1; ram[i] = { op_or, `P, `P, `s1, `s0 }; // s0|s1=>s0, pop both
i=i+1; ram[i] = { `op_rd_i, STK_ER_ADDR, `_, `_, `s2, `s1 }; // read (s2+offset)=>s1
i=i+1; ram[i] = { op_and, `P, `P, `s1, `s0 }; // s0&s1=>s0, pop both
i=i+1; ram[i] = { `op_wr_i, STK_ER_ADDR, `P, `_, `s2, `s0 }; // write s0=>(s2+offset), pop s2
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return to (s3), pop s3
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h920; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_rd_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // read (s1+offset) => s0
i=i+1; ram[i] = { `op_rd_ix, IO_HI_ADDR, `P, `P, `s1, `s0 }; // read (s1+offset) => s0, pop s1 & s0
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h930; ram[i] = { op_lit_u, `_, `_, `s0, `s1 }; // lit => s1
i=i+1; ram[i] = REG_BASE_ADDR ; // reg base addr
i=i+1; ram[i] = { `op_wr_i, IO_LO_ADDR, `_, `_, `s1, `s0 }; // write s0 => (s1+offset)
i=i+1; ram[i] = { `op_wr_ix, IO_HI_ADDR, `P, `_, `s1, `s0 }; // write s0 => (s1+offset), pop s1
i=i+1; ram[i] = { op_gto, `P, `_, `s3, `s0 }; // return, pop s3
 
 
end
/hive/trunk/v01.09/core.sdc
0,0 → 1,108
## Generated SDC file "core.sdc"
 
## Copyright (C) 1991-2010 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
 
 
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition"
 
## DATE "Wed May 15 09:26:03 2013"
 
##
## DEVICE "EP3C5E144C8"
##
 
 
#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name clk_i clk_i -period "200 MHz"
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
derive_clock_uncertainty
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
/hive/trunk/v01.09/core.qws
0,0 → 1,18
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[ProjectWorkspace.Frames.ChildFrames.Document-2]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0]
DocPathName=op_encode.h
DocumentCLSID={0b720e69-67da-11d0-bf4f-0000c08cb0c0}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
/hive/trunk/v01.09/unused/clz.vwf
0,0 → 1,4188
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
 
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
 
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 10000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 50.0;
GRID_DUTY_CYCLE = 50;
}
 
SIGNAL("clk_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("data_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 32;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("data_i[31]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[30]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[29]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[28]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[27]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[26]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[25]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[24]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[23]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[22]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[21]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[20]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[19]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[18]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[17]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[16]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[15]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[14]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[13]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[12]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[11]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[10]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[9]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[8]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("data_i[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "data_i";
}
 
SIGNAL("rst_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 518")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("clz_o")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 6;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("clz_o[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "clz_o";
}
 
SIGNAL("clz_o[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "clz_o";
}
 
SIGNAL("clz_o[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "clz_o";
}
 
SIGNAL("clz_o[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "clz_o";
}
 
SIGNAL("clz_o[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "clz_o";
}
 
SIGNAL("clz_o[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "clz_o";
}
 
TRANSITION_LIST("clk_i")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 200;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
 
TRANSITION_LIST("data_i[31]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1750.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 250.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 300.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 250.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 250.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 300.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 350.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 300.0;
}
}
 
TRANSITION_LIST("data_i[30]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1700.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 250.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 250.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 250.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
}
}
 
TRANSITION_LIST("data_i[29]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1650.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 250.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 300.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
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TRANSITION_LIST("data_i[28]")
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TRANSITION_LIST("data_i[27]")
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TRANSITION_LIST("data_i[26]")
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TRANSITION_LIST("data_i[25]")
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TRANSITION_LIST("data_i[24]")
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TRANSITION_LIST("data_i[23]")
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TRANSITION_LIST("data_i[22]")
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TRANSITION_LIST("data_i[21]")
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TRANSITION_LIST("data_i[20]")
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TRANSITION_LIST("data_i[19]")
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TRANSITION_LIST("data_i[18]")
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TRANSITION_LIST("data_i[17]")
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TRANSITION_LIST("data_i[16]")
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TRANSITION_LIST("data_i[15]")
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TRANSITION_LIST("data_i[14]")
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TRANSITION_LIST("data_i[13]")
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TRANSITION_LIST("data_i[12]")
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TRANSITION_LIST("data_i[11]")
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TRANSITION_LIST("data_i[10]")
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TRANSITION_LIST("data_i[9]")
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TRANSITION_LIST("data_i[8]")
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TRANSITION_LIST("data_i[7]")
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TRANSITION_LIST("data_i[6]")
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TRANSITION_LIST("data_i[5]")
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TRANSITION_LIST("data_i[4]")
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TRANSITION_LIST("data_i[3]")
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TRANSITION_LIST("data_i[2]")
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TRANSITION_LIST("data_i[1]")
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TRANSITION_LIST("data_i[0]")
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LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 300.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 300.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 350.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 300.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 250.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 300.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 150.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 350.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 100.0;
}
}
 
TRANSITION_LIST("rst_i")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 9950.0;
}
}
 
TRANSITION_LIST("clz_o[5]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
 
TRANSITION_LIST("clz_o[4]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
 
TRANSITION_LIST("clz_o[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
 
TRANSITION_LIST("clz_o[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
 
TRANSITION_LIST("clz_o[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
 
TRANSITION_LIST("clz_o[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 10000.0;
}
}
 
DISPLAY_LINE
{
CHANNEL = "rst_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "clk_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 518";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
CHILDREN = 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 15;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 16;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 17;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 18;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 19;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 20;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 21;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 22;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 23;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 24;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 25;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 26;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 27;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 28;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 29;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 30;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 31;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 32;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 33;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 34;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "data_i[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 35;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "clz_o";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 36;
TREE_LEVEL = 0;
CHILDREN = 37, 38, 39, 40, 41, 42;
}
 
DISPLAY_LINE
{
CHANNEL = "clz_o[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 37;
TREE_LEVEL = 1;
PARENT = 36;
}
 
DISPLAY_LINE
{
CHANNEL = "clz_o[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 38;
TREE_LEVEL = 1;
PARENT = 36;
}
 
DISPLAY_LINE
{
CHANNEL = "clz_o[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 39;
TREE_LEVEL = 1;
PARENT = 36;
}
 
DISPLAY_LINE
{
CHANNEL = "clz_o[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 40;
TREE_LEVEL = 1;
PARENT = 36;
}
 
DISPLAY_LINE
{
CHANNEL = "clz_o[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 41;
TREE_LEVEL = 1;
PARENT = 36;
}
 
DISPLAY_LINE
{
CHANNEL = "clz_o[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 42;
TREE_LEVEL = 1;
PARENT = 36;
}
 
TIME_BAR
{
TIME = 17275;
MASTER = TRUE;
}
;
/hive/trunk/v01.09/unused/clz.v
0,0 → 1,113
/*
--------------------------------------------------------------------------------
 
Module : clz.v
 
--------------------------------------------------------------------------------
 
Function:
- Count leading zeros.
 
Instantiates:
- (2x) vector_sr.v
 
Notes:
- IN/OUT optionally registered.
 
--------------------------------------------------------------------------------
*/
 
module clz
#(
parameter integer REGS_IN = 1, // in register option
parameter integer REGS_OUT = 1, // out register option
parameter integer DATA_W = 32, // data width
parameter integer CLZ_W = 6 // s/b clog2( DATA_W ) + 1;
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// data I/O
input wire [DATA_W-1:0] data_i, // input
output wire [CLZ_W-1:0] clz_o // result
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
//
localparam integer LOG2_W = clog2( DATA_W );
//
wire [DATA_W-1:0] data;
reg all_0;
reg [LOG2_W-1:0] hi_1;
wire [CLZ_W-1:0] clz;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input regs
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( DATA_W ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( data_i ),
.data_o ( data )
);
 
 
// looped priority encoder
integer j;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
hi_1 <= { LOG2_W{ 1'b1 } };
all_0 <= 'b1;
end else begin
hi_1 <= { LOG2_W{ 1'b1 } };
all_0 <= 'b1;
for ( j = 0; j < DATA_W; j = j + 1 ) begin
if ( data[j] ) begin
hi_1 <= j[LOG2_W-1:0];
all_0 <= 'b0;
end
end
end
end
// invert & concat to get zero count
assign clz = { all_0, ~hi_1 };
 
 
// optional output regs
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( CLZ_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( clz ),
.data_o ( clz_o )
);
 
 
endmodule
/hive/trunk/v01.09/alu_add_sub.v
0,0 → 1,165
/*
--------------------------------------------------------------------------------
 
Module : alu_add_sub.v
 
--------------------------------------------------------------------------------
 
Function:
- Add & subtract unit for a processor ALU.
 
Instantiates:
- (4x) vector_sr.v
 
Notes:
- IN/MID/OUT/FLG optionally registered.
 
--------------------------------------------------------------------------------
*/
 
module alu_add_sub
#(
parameter integer REGS_IN = 1, // in register option
parameter integer REGS_MID = 1, // mid register option
parameter integer REGS_OUT = 1, // out register option
parameter integer REGS_FLG = 1, // flag register option
parameter integer DATA_W = 3 // data width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire sub_i, // 1=subtract; 0=add
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output wire [DATA_W-1:0] result_o, // = ( a +/- b )
// flags
output wire ltz_o, // a < 0
output wire lt_o // a < b
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer ZSX_W = DATA_W+1; // +1 extra bit
localparam integer ADD_W = DATA_W+2; // +2 extra bits
localparam integer DBL_W = DATA_W*2; // double width
//
wire sgn, sub, ext, sub_r, ext_r;
wire signed [DATA_W-1:0] a, b;
wire signed [ZSX_W-1:0] a_zsx, b_zsx;
wire signed [ADD_W-1:0] ab_add, ab_sub, ab_add_r, ab_sub_r;
reg signed [DBL_W-1:0] res_dbl;
reg signed [DATA_W-1:0] result;
wire ltz, lt;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input regs
vector_sr
#(
.REGS ( REGS_IN ),
.DATA_W ( DATA_W+DATA_W+3 ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { a_i, b_i, sub_i, ext_i, sgn_i } ),
.data_o ( { a, b, sub, ext, sgn } )
);
 
// zero|sign extend results
assign a_zsx = { ( sgn & a[DATA_W-1] ), a };
assign b_zsx = { ( sgn & b[DATA_W-1] ), b };
 
// arithmetic results (signed)
assign ab_add = a_zsx + b_zsx;
assign ab_sub = a_zsx - b_zsx;
// flags
assign ltz = a[DATA_W-1];
assign lt = ab_sub[ZSX_W-1];
 
 
// optional flag regs
vector_sr
#(
.REGS ( REGS_FLG ),
.DATA_W ( 2 ),
.RESET_VAL ( 0 )
)
regs_flags
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { ltz, lt } ),
.data_o ( { ltz_o, lt_o } )
);
 
 
// optional mid regs
vector_sr
#(
.REGS ( REGS_MID ),
.DATA_W ( ADD_W+ADD_W+2 ),
.RESET_VAL ( 0 )
)
mid_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { ab_sub, ab_add, sub, ext } ),
.data_o ( { ab_sub_r, ab_add_r, sub_r, ext_r } )
);
 
 
// multiplex
always @ ( * ) begin
case ( sub_r )
'b0 : res_dbl <= ab_add_r;
'b1 : res_dbl <= ab_sub_r;
endcase
end
 
// multiplex & extend
always @ ( * ) begin
case ( ext_r )
'b0 : result <= res_dbl[DATA_W-1:0];
'b1 : result <= res_dbl[DBL_W-1:DATA_W];
endcase
end
 
 
// optional output regs
vector_sr
#(
.REGS ( REGS_OUT ),
.DATA_W ( DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( result ),
.data_o ( result_o )
);
 
 
endmodule
/hive/trunk/v01.09/event_ctrl.v
0,0 → 1,114
/*
--------------------------------------------------------------------------------
 
Module: event_ctrl.v
 
Function:
- Event (clear & interrupt) controller for multi-threaded processor.
 
Instantiates:
- (1x) vector_sr.v
 
Notes:
- Request is latched and acked until serviced.
- Event output is valid for the stage following this one.
- Optional req regs & resync.
- Optional req level / edge operation.
- For automatic clearing @ async reset, set RESET_VAL to 1.
 
--------------------------------------------------------------------------------
*/
 
module event_ctrl
#(
parameter integer REGS_REQ = 2, // input registers option
parameter integer EDGE_REQ = 0, // edge/level input option
parameter integer RESET_VAL = 1, // async reset value option
parameter integer THREADS = 4, // number of threads
parameter integer THRD_W = 2 // thread width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// I/O
input wire [THRD_W-1:0] thrd_i, // thread
input wire [THREADS-1:0] en_i, // event enable, active high
input wire [THREADS-1:0] req_i, // event request, active high
output reg [THREADS-1:0] ack_o, // event ack, active high until serviced
output reg event_o // event, active high for one clock
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire [THREADS-1:0] req_0, req_2, thread_flag;
 
 
 
/*
================
== code start ==
================
*/
 
 
// optional input req regs
vector_sr
#(
.REGS ( REGS_REQ ),
.DATA_W ( THREADS ),
.RESET_VAL ( 0 )
)
req_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( req_i ),
.data_o ( req_0 )
);
 
 
// optional input req edge detect
generate
if ( EDGE_REQ ) begin
reg [THREADS-1:0] req_1;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
req_1 <= 'b0;
end else begin
req_1 <= req_0;
end
end
assign req_2 = req_0 & ~req_1;
end else begin
assign req_2 = req_0;
end
endgenerate
 
// decode thread flags (one hot)
assign thread_flag = 1'b1 << thrd_i;
 
// register & latch events
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
ack_o <= { THREADS{ RESET_VAL[0] } };
end else begin
ack_o <= ( en_i & req_2 ) | ( ack_o & ~thread_flag );
end
end
 
// output event (use in following stage)
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
event_o <= 'b0;
end else begin
event_o <= |( ack_o & thread_flag );
end
end
 
 
endmodule
/hive/trunk/v01.09/vector_sr.v
0,0 → 1,71
/*
--------------------------------------------------------------------------------
 
Module: vector_sr.v
 
Function:
- Vector I/O shift register.
 
Instantiates:
- Nothing.
 
Notes:
- Parameters for regs depth, data width, and async reset value.
- REGS=0 generates a wire.
 
--------------------------------------------------------------------------------
*/
 
 
module vector_sr
#(
parameter integer REGS = 4, // number of registers
parameter integer DATA_W = 2, // I/O data width
parameter [DATA_W-1:0] RESET_VAL = 0 // regs async reset value
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// I/O
input wire [DATA_W-1:0] data_i, // data in
output wire [DATA_W-1:0] data_o // data out
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
genvar i;
 
 
/*
================
== code start ==
================
*/
 
 
// generate regs pipeline
generate
if ( REGS == 0 ) begin
assign data_o = data_i;
end else begin
reg [DATA_W-1:0] stage[0:REGS-1];
for ( i=0; i<REGS; i=i+1 ) begin : loop
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
stage[i] <= RESET_VAL;
end else begin
stage[i] <= ( i == REGS-1 ) ? data_i : stage[i+1];
end
end
end // endfor : loop
assign data_o = stage[0];
end
endgenerate
 
 
endmodule
/hive/trunk/v01.09/README.txt
0,0 → 1,16
* Hive soft processor core readme file *
 
- All *.v verilog and include *.h files are in a single directory,
where "core.v" is the top level entry.
- There are several boot code files in the "boot_code" directory,
to use one, bring it into the main directory and rename it
"boot_code.h".
- There is also an "unused" directory which contains files that aren't
currently part of the project but may be of interest.
- There is a "core.qpf" project file for Altera Quartus II9.1sp2 Web Edition.
With this tool you can compile to a target, and with the file "core.vwf" you
and simulate. I recommend functional simulation when fiddling around
because the compile is much faster.
- There is also a "core.sdc" file which sets the target top speed to
200 MHz in Quartus, and "core.qsf" which is a project settings file.
- Don't forget to assign pins for a real project.
/hive/trunk/v01.09/core.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
# Date created = 16:30:24 June 18, 2013
#
# -------------------------------------------------------------------------- #
 
QUARTUS_VERSION = "9.1"
DATE = "16:30:24 June 18, 2013"
 
# Revisions
 
PROJECT_REVISION = "core"

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