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URL https://opencores.org/ocsvn/i2sparalell/i2sparalell/trunk

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/trunk/I2SParalell.ucf
0,0 → 1,43
# Clock
NET "Xtal" PERIOD = 40; # 40ns = 25MHz
# A/D Fifo Interface
 
# FIFO CTRL
 
# ADC/DAC
 
# EOF
#PACE: Start of Constraints generated by PACE
 
#PACE: Start of PACE I/O Pin Assignments
NET "AdcData" LOC = "P2" | PULLUP ; #PullUp for I2S on CS5340; PullDn is LJ mode, which causes 1-bit timing error (volume/2)| #PullUp for I2S on CS5340; PullDn is LJ mode, which causes 1-bit timing error (volume/2)
NET "ADCSampleBus<0>" LOC = "P18" ; # AvrA7
NET "ADCSampleBus<1>" LOC = "P16" ; # AvrA6
NET "ADCSampleBus<2>" LOC = "P14" ; # AvrA5
NET "ADCSampleBus<3>" LOC = "P13" ; # AvrA4
NET "ADCSampleBus<4>" LOC = "P12" ; # AvrA3
NET "ADCSampleBus<6>" LOC = "P7" ; # AvrA1
NET "DacData" LOC = "P5" ;
NET "DACSampleBus<0>" LOC = "P19" ; # AvrC7
 
NET "DACSampleBus<1>" LOC = "P20" ; # AvrC6
NET "DACSampleBus<2>" LOC = "P21" ; # AvrC5
NET "DACSampleBus<3>" LOC = "P22" ; # AvrC4
NET "DACSampleBus<4>" LOC = "P23" ; # AvrC3
NET "DACSampleBus<6>" LOC = "P28" ; # AvrC1
NET "LDataStrobe" LOC = "P40" ; # alias e5
NET "LRClk" LOC = "P42" ;
NET "MClk" LOC = "P3" ;
NET "nDebugLoopBack" LOC = "P30" | PULLUP ;
NET "RDataStrobe" LOC = "P41" ; # alias e4
 
NET "SClk" LOC = "P4" ;
NET "Xtal" LOC = "P43" ; # Clock input - GCLK0
 
 
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE
/trunk/I2SParalell.ise
0,0 → 1,219
PK
__OBJSTORE__/PK
__OBJSTORE__/common/PK
__OBJSTORE__/ProjectNavigator/PK
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__REGISTRY__/bitgen/PK
 
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filter.filter
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synprovhd, virtex, VHDL.t_synthesize, 1134773090, TRUE
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p_CPLDFitunused
xstvhd, xpla3, Implementation.t_vm6File, 1058395051, Float
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p_impactConfigFileName
xstvhd, xpla3, Implementation.t_impactProgrammingTool, 1058541585, C:\Projects\Commutator\Firmware\commutatorports.jed
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p_impactConfigMode
xstvhd, xpla3, Implementation.t_impactProgrammingTool, 1058383577, Boundary Scan
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p_xstHierarchySeparator
xstvhd, xbr, Schematic.t_synthesize, 1134773090, _
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p_xstTristate2Logic
xstvhd, virtex, VHDL.t_synthesize, 1134773090, Yes
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PK
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WARNINGS,1134776131
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PK
 
JDF H
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// Created by Project Navigator ver 1.0
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DEVTOPLEVELMODULETYPE HDL
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TOPLEVELMODULETYPETIME 0
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DEVSYNTHESISTOOL XST (VHDL/Verilog)
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SYNTHESISTOOLTIME 0
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DEVSIMULATOR Other
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SIMULATORTIME 0
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DEVGENERATEDSIMULATIONMODEL VHDL
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GENERATEDSIMULATIONMODELTIME 0
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SOURCE AnalogBus.vhd
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SOURCE I2SParalell.vhd
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2
DEVFAM xbr
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SOURCE Clocks.vhd
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DEPASSOC i2sparalellports I2SParalell.ucf
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3
DEVFAMTIME 0
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4
DEVICE xc2c128
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5
DEVICETIME 1134776128
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DEVPKG TQ144
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DEVPKGTIME 1134775931
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DEVSPEED -7
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DEVSPEEDTIME 0
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NumEntries
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__REGISTRY__/runner/PK
 
_xmsgs/runner.xmsgs
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_xmsgs/taengine.xmsgs
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,,__REGISTRY__/trce/regkeysClientMessageOutputFile
_xmsgs/trce.xmsgs
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__REGISTRY__/tsim/PK
 
_xmsgs/tsim.xmsgs
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__REGISTRY__/vhpcomp/PK
 
_xmsgs/vhpcomp.xmsgs
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_xmsgs/vlogcomp.xmsgs
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_xmsgs/XSLTProcess.xmsgs
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_xmsgs/xst.xmsgs
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1.1
REGISTRY_VERSION
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OBJSTORE_VERSION
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PKR
/trunk/I2SParalell.vhd
0,0 → 1,109
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
--This has been tested on a Xilinx XC2C256 (Coolrunner-II 256) with
-- Cirrus CS5340 ADC's and CS4334 DAC's connected to an Atmel AVR AtMega128L uC.
 
entity I2SParalellPorts is
port (
Xtal : in std_logic;
--analog bus ports
AdcData : in std_logic;
DacData : out std_logic;
LRClk : out std_logic;
SClk : out std_logic;
MClk : out std_logic;
--digital bus ports
ADCSampleBus : out std_logic_vector(23 downto 0);
DACSampleBus : in std_logic_vector(23 downto 0);
LDataStrobe : out std_logic;
RDataStrobe : out std_logic;
 
--debug port
nDebugLoopBack : in std_logic --;
);
end I2SParalellPorts;
 
architecture I2SParalell of I2SParalellPorts is
 
component ClocksPorts
port (
Xtal : in std_logic; --main system oscillator
LRClk : out std_logic; --LR clock for analog serial bus
SClk : out std_logic; --Serial Bit clock for analog serial bus
MClk : out std_logic--; --Master clock for analog serial bus (runs DeltaSig hardware in converters)
);
end component;
 
component AnalogBusPorts
port (
SClk : in std_logic; --this whole schebang runs of the analog serial bus clock
LRClk : in std_logic; --which channel at the moment?
AdcData : in std_logic; --data coming in from adc
DacData : out std_logic; --data coming in from adc
SampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
nSampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
LastAdcSample : out std_logic_vector(23 downto 0); --buffer for fifo data
NextDacSample : in std_logic_vector(23 downto 0)--; --buffer for fifo data
);
end component;
 
signal LRClk_i : std_logic;
signal SClk_i : std_logic;
signal DacData_e : std_logic;
signal DacData_i : std_logic;
--signal count : std_logic_vector(24 downto 0);
begin
Clocks: ClocksPorts
port map (
Xtal=>Xtal,
LRClk=>LRClk_i,
SClk=>SClk_i,
MClk=>MClk--,
);
 
AnalogBus: AnalogBusPorts
port map (
SClk=>SClk_i,
LRClk=>LRClk_i,
AdcData=>AdcData,
DacData=>DacData_e,
SampleStrobe=>LDataStrobe,
nSampleStrobe=>RDataStrobe,
LastAdcSample=>ADCSampleBus,
NextDacSample=>DACSampleBus--,
);
 
LRClk <= LRClk_i;
SClk <= SClk_i;
DacData <= DacData_i;
 
process (Xtal)
begin
if (Xtal'event and Xtal = '1') then
 
if (nDebugLoopBack = '0') then
 
DacData_i <= AdcData;
 
else
 
DacData_i <= DacData_e;
 
end if;
 
end if; --if (Xtal'event ...
 
end process;
end I2SParalell;
/trunk/AnalogBus.vhd
0,0 → 1,102
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity AnalogBusPorts is
port (
SClk : in std_logic; --this whole schebang runs of the analog serial bus clock
LRClk : in std_logic; --which channel at the moment?
AdcData : in std_logic; --data coming in from adc
DacData : out std_logic; --
SampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
nSampleStrobe : out std_logic; --dump the contents of FifoData into the fifo on next clock
LastAdcSample : out std_logic_vector(23 downto 0); --buffer for fifo data
NextDacSample : in std_logic_vector(23 downto 0)--; --buffer for fifo data
);
end AnalogBusPorts;
 
architecture AnalogBus of AnalogBusPorts is
signal LastLRClk : std_logic; --to keep track of edges
--sample buffers
signal CurrentAdcSample : std_logic_vector(23 downto 0);
signal CurrentDacSample : std_logic_vector(23 downto 0);
signal AdcBitIndex : std_logic_vector(5 downto 0);
signal DacBitIndex : std_logic_vector(5 downto 0);
begin
 
process (SClk)
begin
 
if (SClk'event and SClk = '1') then
 
--move to next bit on each clock of the serial
AdcBitIndex <= AdcBitIndex + "000001";
DacBitIndex <= DacBitIndex + "000001";
--Just moved to the MSB of the other channel
if ( LRClk = (not(LastLRClk)) ) then
LastLRClk <= LRClk; --reset for next edge
if (LRClk = '1') then
AdcBitIndex <= "000000"; --reset at MSB of sample
DacBitIndex <= "000001"; --reset at MSB of sample
end if;
end if;
 
end if;
 
if (SClk'event and SClk = '0') then
--if we just finished a sample, better stick it in the adc fifo
 
--Left ADC Channel
if ( (AdcBitIndex = "111100") ) then --idx=60, which is in the middle of the 8 unused clocks for the R channel.
LastAdcSample <= CurrentAdcSample(23 downto 0);
CurrentDacSample(23 downto 0) <= NextDacSample;
end if;
 
--Right ADC Channel
if ( (AdcBitIndex = "011100") ) then --idx=28, which is in the middle of the 8 unused clocks for the L channel.
LastAdcSample <= CurrentAdcSample(23 downto 0);
CurrentDacSample(23 downto 0) <= NextDacSample;
end if;
 
if ( (AdcBitIndex = "000000") ) then
SampleStrobe <= '1';
nSampleStrobe <= '0';
end if;
 
if ( (AdcBitIndex = "100000") ) then
SampleStrobe <= '0'; --50% duty approx
nSampleStrobe <= '1';
end if;
 
--put each bit into/from the appropriate location in the sample buffer
if (AdcBitIndex(4 downto 0) < "11000") then --ignore the top 8 MSB's (24 bits of data in 32 bit transaction)
CurrentAdcSample(Conv_INTEGER(AdcBitIndex(4 downto 0))) <= AdcData;
end if;
 
if (DacBitIndex(4 downto 0) < "11000") then --ignore the top 8 MSB's (24 bits of data in 32 bit transaction)
DacData <= CurrentDacSample(Conv_INTEGER(DacBitIndex(4 downto 0)));
end if;
 
end if; --if (SClk'event and SClk = '1') then
 
end process; --process (SClk)
 
end AnalogBus;
/trunk/Clocks.vhd
0,0 → 1,59
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ClocksPorts is
port (
Xtal : in std_logic; --main system oscillator
LRClk : out std_logic; --LR clock for analog serial bus
SClk : out std_logic; --Serial Bit clock for analog serial bus
MClk : out std_logic--; --Master clock for analog serial bus (runs DeltaSig hardware in converters)
);
end ClocksPorts;
 
architecture Clocks of ClocksPorts is
 
signal XtalDiv : std_logic_vector(3 downto 0);
signal div256 : std_logic_vector(8 downto 0);
begin
 
MClk <= div256(0); --run at mclk (XtalDiv/2)
SClk <= div256(2); --divide MCLK by 4 to Get SCLK (64*Fs)
LRClk <= div256(8); --divide MCLK by 256 to Get LRCLK (1*Fs)
 
process (Xtal)
 
begin
 
if (Xtal'event and Xtal = '1') then
 
--the following divider calculations assume a Xtal input of 25MHz:
XtalDiv <= XtalDiv + "0001";
--if (XtalDiv = "1001") then --9: divide by 10 -> fs=4.833kHz
if (XtalDiv = "0101") then --5: divide by 6 -> fs=8.137kHz
--if (XtalDiv = "0100") then --4: divide by 5 -> fs=9.766kHz
--if (XtalDiv = "0011") then --3: divide by 4 -> fs=12kHz
--if (XtalDiv = "0010") then --2: divide by 3 -> fs=16kHz
--if (XtalDiv = "0001") then --1: divide by 2 -> fs=32kHz
--if 'this divider removed : divide by 1 -> fs=48kHz
 
--reset master divide counter
XtalDiv <= "0000";
--drive other dividers...
div256 <= div256 + "000000001";
 
end if; -- if (XtalDiv = ...
 
end if; --if (Xtal'event ...
 
end process;
 
end Clocks;
/trunk
trunk Property changes : Added: svn:ignore ## -0,0 +1,109 ## +*.dbk +*.obk +*.log +*.lis +Compiled +__projnav +_ngo +xst +*_html +*.hrpt +*.bgn +*.bld +*.cmd_log +*.dhp +*.err +*.gyd +*.iso +*.mfd +*.mrp +*.msk +*.nc1 +*.ncd +*.ngc +*.ngd +*.ngm +*.ngr +*.pad +*.pad_txt +*.par +*.pcf +*.placed_ncd_tracker +*.pnx +*.prj +*.prm +*.rbb +*.routed_ncd_tracker +*.sig +*.stx +*.syr +*.log +*.drc +*.rpt +*.tspec +*.twr +*.twx +*.untf +*.ut +*.vm6 +*.cmd +*.xml +*.xpi +*.lso +*.tpl +*_pad* +*._hrpt +*.filter +*.chk +*.blx +_* +__* +bak* +back* +BACK* +*back* +*bak* +Copy* +2003* +2004* +2005* +2006* +2007* +*.bin +*.elf +*.lst +*.o +*.map +*.srec +dependencies +Debug +Release +*.bsc +*.obj +*.sbr +*.pch +*.pdb +*.idb +*.aps +*.bin +*.elf +*.hex +*.map +*.srec +*.*svf +*.ncb +*.aps +*.clw +*.opt +*.plg +*.res +.dep +*.pnproj +*.lss +*.sym +*.map +*.lfp +*.cxt +*.data +*.mod +*.tim

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