URL
https://opencores.org/ocsvn/jpegencode/jpegencode/trunk
Subversion Repositories jpegencode
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/jpegencode/trunk/cr_huff.v
0,0 → 1,2254
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module is the Huffman encoder. It takes in the quantized outputs |
from the quantizer, and creates the Huffman codes from these value. The |
output from this module is the jpeg code of the actual pixel data. The jpeg |
file headers will need to be generated separately. The Huffman codes are constant, |
and they can be changed by changing the parameters in this module. */ |
|
`timescale 1ns / 100ps |
|
module cr_huff(clk, rst, enable, |
Cr11, Cr12, Cr13, Cr14, Cr15, Cr16, Cr17, Cr18, Cr21, Cr22, Cr23, Cr24, Cr25, Cr26, Cr27, Cr28, |
Cr31, Cr32, Cr33, Cr34, Cr35, Cr36, Cr37, Cr38, Cr41, Cr42, Cr43, Cr44, Cr45, Cr46, Cr47, Cr48, |
Cr51, Cr52, Cr53, Cr54, Cr55, Cr56, Cr57, Cr58, Cr61, Cr62, Cr63, Cr64, Cr65, Cr66, Cr67, Cr68, |
Cr71, Cr72, Cr73, Cr74, Cr75, Cr76, Cr77, Cr78, Cr81, Cr82, Cr83, Cr84, Cr85, Cr86, Cr87, Cr88, |
JPEG_bitstream, data_ready, output_reg_count, end_of_block_empty); |
input clk; |
input rst; |
input enable; |
input [10:0] Cr11, Cr12, Cr13, Cr14, Cr15, Cr16, Cr17, Cr18, Cr21, Cr22, Cr23, Cr24; |
input [10:0] Cr25, Cr26, Cr27, Cr28, Cr31, Cr32, Cr33, Cr34, Cr35, Cr36, Cr37, Cr38; |
input [10:0] Cr41, Cr42, Cr43, Cr44, Cr45, Cr46, Cr47, Cr48, Cr51, Cr52, Cr53, Cr54; |
input [10:0] Cr55, Cr56, Cr57, Cr58, Cr61, Cr62, Cr63, Cr64, Cr65, Cr66, Cr67, Cr68; |
input [10:0] Cr71, Cr72, Cr73, Cr74, Cr75, Cr76, Cr77, Cr78, Cr81, Cr82, Cr83, Cr84; |
input [10:0] Cr85, Cr86, Cr87, Cr88; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output output_reg_count; |
output end_of_block_empty; |
|
|
reg [7:0] block_counter; |
reg [11:0] Cr11_amp, Cr11_1_pos, Cr11_1_neg, Cr11_diff; |
reg [11:0] Cr11_previous, Cr11_1; |
reg [10:0] Cr12_amp, Cr12_pos, Cr12_neg; |
reg [10:0] Cr21_pos, Cr21_neg, Cr31_pos, Cr31_neg, Cr22_pos, Cr22_neg; |
reg [10:0] Cr13_pos, Cr13_neg, Cr14_pos, Cr14_neg, Cr15_pos, Cr15_neg; |
reg [10:0] Cr16_pos, Cr16_neg, Cr17_pos, Cr17_neg, Cr18_pos, Cr18_neg; |
reg [10:0] Cr23_pos, Cr23_neg, Cr24_pos, Cr24_neg, Cr25_pos, Cr25_neg; |
reg [10:0] Cr26_pos, Cr26_neg, Cr27_pos, Cr27_neg, Cr28_pos, Cr28_neg; |
reg [10:0] Cr32_pos, Cr32_neg; |
reg [10:0] Cr33_pos, Cr33_neg, Cr34_pos, Cr34_neg, Cr35_pos, Cr35_neg; |
reg [10:0] Cr36_pos, Cr36_neg, Cr37_pos, Cr37_neg, Cr38_pos, Cr38_neg; |
reg [10:0] Cr41_pos, Cr41_neg, Cr42_pos, Cr42_neg; |
reg [10:0] Cr43_pos, Cr43_neg, Cr44_pos, Cr44_neg, Cr45_pos, Cr45_neg; |
reg [10:0] Cr46_pos, Cr46_neg, Cr47_pos, Cr47_neg, Cr48_pos, Cr48_neg; |
reg [10:0] Cr51_pos, Cr51_neg, Cr52_pos, Cr52_neg; |
reg [10:0] Cr53_pos, Cr53_neg, Cr54_pos, Cr54_neg, Cr55_pos, Cr55_neg; |
reg [10:0] Cr56_pos, Cr56_neg, Cr57_pos, Cr57_neg, Cr58_pos, Cr58_neg; |
reg [10:0] Cr61_pos, Cr61_neg, Cr62_pos, Cr62_neg; |
reg [10:0] Cr63_pos, Cr63_neg, Cr64_pos, Cr64_neg, Cr65_pos, Cr65_neg; |
reg [10:0] Cr66_pos, Cr66_neg, Cr67_pos, Cr67_neg, Cr68_pos, Cr68_neg; |
reg [10:0] Cr71_pos, Cr71_neg, Cr72_pos, Cr72_neg; |
reg [10:0] Cr73_pos, Cr73_neg, Cr74_pos, Cr74_neg, Cr75_pos, Cr75_neg; |
reg [10:0] Cr76_pos, Cr76_neg, Cr77_pos, Cr77_neg, Cr78_pos, Cr78_neg; |
reg [10:0] Cr81_pos, Cr81_neg, Cr82_pos, Cr82_neg; |
reg [10:0] Cr83_pos, Cr83_neg, Cr84_pos, Cr84_neg, Cr85_pos, Cr85_neg; |
reg [10:0] Cr86_pos, Cr86_neg, Cr87_pos, Cr87_neg, Cr88_pos, Cr88_neg; |
reg [3:0] Cr11_bits_pos, Cr11_bits_neg, Cr11_bits, Cr11_bits_1; |
reg [3:0] Cr12_bits_pos, Cr12_bits_neg, Cr12_bits, Cr12_bits_1; |
reg [3:0] Cr12_bits_2, Cr12_bits_3; |
reg Cr11_msb, Cr12_msb, Cr12_msb_1, data_ready; |
reg enable_1, enable_2, enable_3, enable_4, enable_5, enable_6; |
reg enable_7, enable_8, enable_9, enable_10, enable_11, enable_12; |
reg enable_13, enable_module, enable_latch_7, enable_latch_8; |
reg Cr12_et_zero, rollover, rollover_1, rollover_2, rollover_3; |
reg rollover_4, rollover_5, rollover_6, rollover_7; |
reg Cr21_et_zero, Cr21_msb, Cr31_et_zero, Cr31_msb; |
reg Cr22_et_zero, Cr22_msb, Cr13_et_zero, Cr13_msb; |
reg Cr14_et_zero, Cr14_msb, Cr15_et_zero, Cr15_msb; |
reg Cr16_et_zero, Cr16_msb, Cr17_et_zero, Cr17_msb; |
reg Cr18_et_zero, Cr18_msb; |
reg Cr23_et_zero, Cr23_msb, Cr24_et_zero, Cr24_msb; |
reg Cr25_et_zero, Cr25_msb, Cr26_et_zero, Cr26_msb; |
reg Cr27_et_zero, Cr27_msb, Cr28_et_zero, Cr28_msb; |
reg Cr32_et_zero, Cr32_msb, Cr33_et_zero, Cr33_msb; |
reg Cr34_et_zero, Cr34_msb, Cr35_et_zero, Cr35_msb; |
reg Cr36_et_zero, Cr36_msb, Cr37_et_zero, Cr37_msb; |
reg Cr38_et_zero, Cr38_msb; |
reg Cr41_et_zero, Cr41_msb, Cr42_et_zero, Cr42_msb; |
reg Cr43_et_zero, Cr43_msb, Cr44_et_zero, Cr44_msb; |
reg Cr45_et_zero, Cr45_msb, Cr46_et_zero, Cr46_msb; |
reg Cr47_et_zero, Cr47_msb, Cr48_et_zero, Cr48_msb; |
reg Cr51_et_zero, Cr51_msb, Cr52_et_zero, Cr52_msb; |
reg Cr53_et_zero, Cr53_msb, Cr54_et_zero, Cr54_msb; |
reg Cr55_et_zero, Cr55_msb, Cr56_et_zero, Cr56_msb; |
reg Cr57_et_zero, Cr57_msb, Cr58_et_zero, Cr58_msb; |
reg Cr61_et_zero, Cr61_msb, Cr62_et_zero, Cr62_msb; |
reg Cr63_et_zero, Cr63_msb, Cr64_et_zero, Cr64_msb; |
reg Cr65_et_zero, Cr65_msb, Cr66_et_zero, Cr66_msb; |
reg Cr67_et_zero, Cr67_msb, Cr68_et_zero, Cr68_msb; |
reg Cr71_et_zero, Cr71_msb, Cr72_et_zero, Cr72_msb; |
reg Cr73_et_zero, Cr73_msb, Cr74_et_zero, Cr74_msb; |
reg Cr75_et_zero, Cr75_msb, Cr76_et_zero, Cr76_msb; |
reg Cr77_et_zero, Cr77_msb, Cr78_et_zero, Cr78_msb; |
reg Cr81_et_zero, Cr81_msb, Cr82_et_zero, Cr82_msb; |
reg Cr83_et_zero, Cr83_msb, Cr84_et_zero, Cr84_msb; |
reg Cr85_et_zero, Cr85_msb, Cr86_et_zero, Cr86_msb; |
reg Cr87_et_zero, Cr87_msb, Cr88_et_zero, Cr88_msb; |
reg Cr12_et_zero_1, Cr12_et_zero_2, Cr12_et_zero_3, Cr12_et_zero_4, Cr12_et_zero_5; |
reg [10:0] Cr_DC [11:0]; |
reg [3:0] Cr_DC_code_length [11:0]; |
reg [15:0] Cr_AC [161:0]; |
reg [4:0] Cr_AC_code_length [161:0]; |
reg [7:0] Cr_AC_run_code [250:0]; |
reg [10:0] Cr11_Huff, Cr11_Huff_1, Cr11_Huff_2; |
reg [15:0] Cr12_Huff, Cr12_Huff_1, Cr12_Huff_2; |
reg [3:0] Cr11_Huff_count, Cr11_Huff_shift, Cr11_Huff_shift_1, Cr11_amp_shift, Cr12_amp_shift; |
reg [3:0] Cr12_Huff_shift, Cr12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3; |
reg [4:0] Cr12_Huff_count, Cr12_Huff_count_1; |
reg [4:0] output_reg_count, Cr11_output_count, old_orc_1, old_orc_2; |
reg [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Cr12_oc_1; |
reg [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8; |
reg [4:0] Cr12_output_count; |
reg [4:0] Cr12_edge, Cr12_edge_1, Cr12_edge_2, Cr12_edge_3, Cr12_edge_4; |
reg [31:0] JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5; |
reg [31:0] JPEG_Cr12_bs, JPEG_Cr12_bs_1, JPEG_Cr12_bs_2, JPEG_Cr12_bs_3, JPEG_Cr12_bs_4; |
reg [31:0] JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4; |
reg [21:0] Cr11_JPEG_LSBs_3; |
reg [10:0] Cr11_JPEG_LSBs, Cr11_JPEG_LSBs_1, Cr11_JPEG_LSBs_2; |
reg [9:0] Cr12_JPEG_LSBs, Cr12_JPEG_LSBs_1, Cr12_JPEG_LSBs_2, Cr12_JPEG_LSBs_3; |
reg [25:0] Cr11_JPEG_bits, Cr11_JPEG_bits_1, Cr12_JPEG_bits, Cr12_JPEG_LSBs_4; |
reg [7:0] Cr12_code_entry; |
reg third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s; |
reg eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output; |
reg end_of_block_empty; |
|
wire [7:0] code_index = { zrl_2, Cr12_bits }; |
|
|
|
always @(posedge clk) |
begin |
if (rst) begin |
third_8_all_0s <= 0; fourth_8_all_0s <= 0; |
fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0; |
eighth_8_all_0s <= 0; |
end |
else if (enable_1) begin |
third_8_all_0s <= Cr25_et_zero & Cr34_et_zero & Cr43_et_zero & Cr52_et_zero |
& Cr61_et_zero & Cr71_et_zero & Cr62_et_zero & Cr53_et_zero; |
fourth_8_all_0s <= Cr44_et_zero & Cr35_et_zero & Cr26_et_zero & Cr17_et_zero |
& Cr18_et_zero & Cr27_et_zero & Cr36_et_zero & Cr45_et_zero; |
fifth_8_all_0s <= Cr54_et_zero & Cr63_et_zero & Cr72_et_zero & Cr81_et_zero |
& Cr82_et_zero & Cr73_et_zero & Cr64_et_zero & Cr55_et_zero; |
sixth_8_all_0s <= Cr46_et_zero & Cr37_et_zero & Cr28_et_zero & Cr38_et_zero |
& Cr47_et_zero & Cr56_et_zero & Cr65_et_zero & Cr74_et_zero; |
seventh_8_all_0s <= Cr83_et_zero & Cr84_et_zero & Cr75_et_zero & Cr66_et_zero |
& Cr57_et_zero & Cr48_et_zero & Cr58_et_zero & Cr67_et_zero; |
eighth_8_all_0s <= Cr76_et_zero & Cr85_et_zero & Cr86_et_zero & Cr77_et_zero |
& Cr68_et_zero & Cr78_et_zero & Cr87_et_zero & Cr88_et_zero; |
end |
end |
|
|
/* end_of_block checks to see if there are any nonzero elements left in the block |
If there aren't any nonzero elements left, then the last bits in the JPEG stream |
will be the end of block code. The purpose of this register is to determine if the |
zero run length code 15-0 should be used or not. It should be used if there are 15 or more |
zeros in a row, followed by a nonzero value. If there are only zeros left in the block, |
then end_of_block will be 1. If there are any nonzero values left in the block, end_of_block |
will be 0. */ |
|
always @(posedge clk) |
begin |
if (rst) |
end_of_block <= 0; |
else if (enable) |
end_of_block <= 0; |
else if (enable_module & block_counter < 32) |
end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s |
& sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s; |
else if (enable_module & block_counter < 48) |
end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s |
& eighth_8_all_0s; |
else if (enable_module & block_counter <= 64) |
end_of_block <= seventh_8_all_0s & eighth_8_all_0s; |
else if (enable_module & block_counter > 64) |
end_of_block <= 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
block_counter <= 0; |
end |
else if (enable) begin |
block_counter <= 0; |
end |
else if (enable_module) begin |
block_counter <= block_counter + 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
output_reg_count <= 0; |
end |
else if (end_of_block_output) begin |
output_reg_count <= 0; |
end |
else if (enable_6) begin |
output_reg_count <= output_reg_count + Cr11_output_count; |
end |
else if (enable_latch_7) begin |
output_reg_count <= output_reg_count + Cr12_oc_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
old_orc_1 <= 0; |
end |
else if (end_of_block_output) begin |
old_orc_1 <= 0; |
end |
else if (enable_module) begin |
old_orc_1 <= output_reg_count; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
rollover <= 0; rollover_1 <= 0; rollover_2 <= 0; |
rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0; |
rollover_6 <= 0; rollover_7 <= 0; |
old_orc_2 <= 0; |
orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0; |
orc_7 <= 0; orc_8 <= 0; data_ready <= 0; |
end_of_block_output <= 0; end_of_block_empty <= 0; |
end |
else if (enable_module) begin |
rollover <= (old_orc_1 > output_reg_count); |
rollover_1 <= rollover; |
rollover_2 <= rollover_1; |
rollover_3 <= rollover_2; |
rollover_4 <= rollover_3; |
rollover_5 <= rollover_4; |
rollover_6 <= rollover_5; |
rollover_7 <= rollover_6; |
old_orc_2 <= old_orc_1; |
orc_3 <= old_orc_2; |
orc_4 <= orc_3; orc_5 <= orc_4; |
orc_6 <= orc_5; orc_7 <= orc_6; |
orc_8 <= orc_7; |
data_ready <= rollover_6 | block_counter == 77; |
end_of_block_output <= block_counter == 77; |
end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0; |
end |
end |
|
|
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_5 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31]; |
JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30]; |
JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29]; |
JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28]; |
JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27]; |
JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26]; |
JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25]; |
JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24]; |
JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23]; |
JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22]; |
JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21]; |
JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20]; |
JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19]; |
JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18]; |
JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17]; |
JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16]; |
JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15]; |
JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14]; |
JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13]; |
JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12]; |
JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11]; |
JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10]; |
JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9]; |
JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8]; |
JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7]; |
JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6]; |
JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5]; |
JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4]; |
JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3]; |
JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2]; |
JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1]; |
JPEG_bs_5[0] <= JPEG_bs_4[0]; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3; |
JPEG_ro_bs_4 <= (Cr12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0; |
Cr12_edge_4 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2; |
old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5; |
JPEG_ro_bs_3 <= (Cr12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2; |
Cr12_edge_4 <= (Cr12_edge_3 <= 2) ? Cr12_edge_3 : Cr12_edge_3 - 2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0; |
Cr12_edge_3 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1; |
old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4; |
JPEG_ro_bs_2 <= (Cr12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1; |
Cr12_edge_3 <= (Cr12_edge_2 <= 4) ? Cr12_edge_2 : Cr12_edge_2 - 4; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0; |
Cr12_edge_2 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs; |
old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3; |
JPEG_ro_bs_1 <= (Cr12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs; |
Cr12_edge_2 <= (Cr12_edge_1 <= 8) ? Cr12_edge_1 : Cr12_edge_1 - 8; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0; |
Cr12_edge_1 <= 0; Cr11_JPEG_bits_1 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs <= (old_orc_2 >= 16) ? Cr11_JPEG_bits >> 10 : Cr11_JPEG_bits << 6; |
old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2; |
JPEG_ro_bs <= (Cr12_edge <= 16) ? Cr11_JPEG_bits_1 << 16 : Cr11_JPEG_bits_1; |
Cr12_edge_1 <= (Cr12_edge <= 16) ? Cr12_edge : Cr12_edge - 16; |
Cr11_JPEG_bits_1 <= Cr11_JPEG_bits; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_JPEG_bits <= 0; Cr12_edge <= 0; |
end |
else if (enable_module) begin |
Cr12_JPEG_bits[25] <= (Cr12_Huff_shift_1 >= 16) ? Cr12_JPEG_LSBs_4[25] : Cr12_Huff_2[15]; |
Cr12_JPEG_bits[24] <= (Cr12_Huff_shift_1 >= 15) ? Cr12_JPEG_LSBs_4[24] : Cr12_Huff_2[14]; |
Cr12_JPEG_bits[23] <= (Cr12_Huff_shift_1 >= 14) ? Cr12_JPEG_LSBs_4[23] : Cr12_Huff_2[13]; |
Cr12_JPEG_bits[22] <= (Cr12_Huff_shift_1 >= 13) ? Cr12_JPEG_LSBs_4[22] : Cr12_Huff_2[12]; |
Cr12_JPEG_bits[21] <= (Cr12_Huff_shift_1 >= 12) ? Cr12_JPEG_LSBs_4[21] : Cr12_Huff_2[11]; |
Cr12_JPEG_bits[20] <= (Cr12_Huff_shift_1 >= 11) ? Cr12_JPEG_LSBs_4[20] : Cr12_Huff_2[10]; |
Cr12_JPEG_bits[19] <= (Cr12_Huff_shift_1 >= 10) ? Cr12_JPEG_LSBs_4[19] : Cr12_Huff_2[9]; |
Cr12_JPEG_bits[18] <= (Cr12_Huff_shift_1 >= 9) ? Cr12_JPEG_LSBs_4[18] : Cr12_Huff_2[8]; |
Cr12_JPEG_bits[17] <= (Cr12_Huff_shift_1 >= 8) ? Cr12_JPEG_LSBs_4[17] : Cr12_Huff_2[7]; |
Cr12_JPEG_bits[16] <= (Cr12_Huff_shift_1 >= 7) ? Cr12_JPEG_LSBs_4[16] : Cr12_Huff_2[6]; |
Cr12_JPEG_bits[15] <= (Cr12_Huff_shift_1 >= 6) ? Cr12_JPEG_LSBs_4[15] : Cr12_Huff_2[5]; |
Cr12_JPEG_bits[14] <= (Cr12_Huff_shift_1 >= 5) ? Cr12_JPEG_LSBs_4[14] : Cr12_Huff_2[4]; |
Cr12_JPEG_bits[13] <= (Cr12_Huff_shift_1 >= 4) ? Cr12_JPEG_LSBs_4[13] : Cr12_Huff_2[3]; |
Cr12_JPEG_bits[12] <= (Cr12_Huff_shift_1 >= 3) ? Cr12_JPEG_LSBs_4[12] : Cr12_Huff_2[2]; |
Cr12_JPEG_bits[11] <= (Cr12_Huff_shift_1 >= 2) ? Cr12_JPEG_LSBs_4[11] : Cr12_Huff_2[1]; |
Cr12_JPEG_bits[10] <= (Cr12_Huff_shift_1 >= 1) ? Cr12_JPEG_LSBs_4[10] : Cr12_Huff_2[0]; |
Cr12_JPEG_bits[9:0] <= Cr12_JPEG_LSBs_4[9:0]; |
Cr12_edge <= old_orc_2 + 26; // 26 is the size of Cr11_JPEG_bits |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_JPEG_bits <= 0; |
end |
else if (enable_7) begin |
Cr11_JPEG_bits[25] <= (Cr11_Huff_shift_1 >= 11) ? Cr11_JPEG_LSBs_3[21] : Cr11_Huff_2[10]; |
Cr11_JPEG_bits[24] <= (Cr11_Huff_shift_1 >= 10) ? Cr11_JPEG_LSBs_3[20] : Cr11_Huff_2[9]; |
Cr11_JPEG_bits[23] <= (Cr11_Huff_shift_1 >= 9) ? Cr11_JPEG_LSBs_3[19] : Cr11_Huff_2[8]; |
Cr11_JPEG_bits[22] <= (Cr11_Huff_shift_1 >= 8) ? Cr11_JPEG_LSBs_3[18] : Cr11_Huff_2[7]; |
Cr11_JPEG_bits[21] <= (Cr11_Huff_shift_1 >= 7) ? Cr11_JPEG_LSBs_3[17] : Cr11_Huff_2[6]; |
Cr11_JPEG_bits[20] <= (Cr11_Huff_shift_1 >= 6) ? Cr11_JPEG_LSBs_3[16] : Cr11_Huff_2[5]; |
Cr11_JPEG_bits[19] <= (Cr11_Huff_shift_1 >= 5) ? Cr11_JPEG_LSBs_3[15] : Cr11_Huff_2[4]; |
Cr11_JPEG_bits[18] <= (Cr11_Huff_shift_1 >= 4) ? Cr11_JPEG_LSBs_3[14] : Cr11_Huff_2[3]; |
Cr11_JPEG_bits[17] <= (Cr11_Huff_shift_1 >= 3) ? Cr11_JPEG_LSBs_3[13] : Cr11_Huff_2[2]; |
Cr11_JPEG_bits[16] <= (Cr11_Huff_shift_1 >= 2) ? Cr11_JPEG_LSBs_3[12] : Cr11_Huff_2[1]; |
Cr11_JPEG_bits[15] <= (Cr11_Huff_shift_1 >= 1) ? Cr11_JPEG_LSBs_3[11] : Cr11_Huff_2[0]; |
Cr11_JPEG_bits[14:4] <= Cr11_JPEG_LSBs_3[10:0]; |
end |
else if (enable_latch_8) begin |
Cr11_JPEG_bits <= Cr12_JPEG_bits; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_oc_1 <= 0; Cr12_JPEG_LSBs_4 <= 0; |
Cr12_Huff_2 <= 0; Cr12_Huff_shift_1 <= 0; |
end |
else if (enable_module) begin |
Cr12_oc_1 <= (Cr12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 : |
Cr12_bits_3 + Cr12_Huff_count_1; |
Cr12_JPEG_LSBs_4 <= Cr12_JPEG_LSBs_3 << Cr12_Huff_shift; |
Cr12_Huff_2 <= Cr12_Huff_1; |
Cr12_Huff_shift_1 <= Cr12_Huff_shift; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_JPEG_LSBs_3 <= 0; Cr11_Huff_2 <= 0; |
Cr11_Huff_shift_1 <= 0; |
end |
else if (enable_6) begin |
Cr11_JPEG_LSBs_3 <= Cr11_JPEG_LSBs_2 << Cr11_Huff_shift; |
Cr11_Huff_2 <= Cr11_Huff_1; |
Cr11_Huff_shift_1 <= Cr11_Huff_shift; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_Huff_shift <= 0; |
Cr12_Huff_1 <= 0; Cr12_JPEG_LSBs_3 <= 0; Cr12_bits_3 <= 0; |
Cr12_Huff_count_1 <= 0; Cr12_et_zero_5 <= 0; code_15_0 <= 0; |
end |
else if (enable_module) begin |
Cr12_Huff_shift <= 16 - Cr12_Huff_count; |
Cr12_Huff_1 <= Cr12_Huff; |
Cr12_JPEG_LSBs_3 <= Cr12_JPEG_LSBs_2; |
Cr12_bits_3 <= Cr12_bits_2; |
Cr12_Huff_count_1 <= Cr12_Huff_count; |
Cr12_et_zero_5 <= Cr12_et_zero_4; |
code_15_0 <= zrl_et_15 & !end_of_block; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_output_count <= 0; Cr11_JPEG_LSBs_2 <= 0; Cr11_Huff_shift <= 0; |
Cr11_Huff_1 <= 0; |
end |
else if (enable_5) begin |
Cr11_output_count <= Cr11_bits_1 + Cr11_Huff_count; |
Cr11_JPEG_LSBs_2 <= Cr11_JPEG_LSBs_1 << Cr11_amp_shift; |
Cr11_Huff_shift <= 11 - Cr11_Huff_count; |
Cr11_Huff_1 <= Cr11_Huff; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_JPEG_LSBs_2 <= 0; |
Cr12_Huff <= 0; Cr12_Huff_count <= 0; Cr12_bits_2 <= 0; |
Cr12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0; |
end |
else if (enable_module) begin |
Cr12_JPEG_LSBs_2 <= Cr12_JPEG_LSBs_1 << Cr12_amp_shift; |
Cr12_Huff <= Cr_AC[Cr12_code_entry]; |
Cr12_Huff_count <= Cr_AC_code_length[Cr12_code_entry]; |
Cr12_bits_2 <= Cr12_bits_1; |
Cr12_et_zero_4 <= Cr12_et_zero_3; |
zrl_et_15 <= zrl_3 == 15; |
zrl_3 <= zrl_2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_Huff <= 0; Cr11_Huff_count <= 0; Cr11_amp_shift <= 0; |
Cr11_JPEG_LSBs_1 <= 0; Cr11_bits_1 <= 0; |
end |
else if (enable_4) begin |
Cr11_Huff[10:0] <= Cr_DC[Cr11_bits]; |
Cr11_Huff_count <= Cr_DC_code_length[Cr11_bits]; |
Cr11_amp_shift <= 11 - Cr11_bits; |
Cr11_JPEG_LSBs_1 <= Cr11_JPEG_LSBs; |
Cr11_bits_1 <= Cr11_bits; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_code_entry <= 0; Cr12_JPEG_LSBs_1 <= 0; Cr12_amp_shift <= 0; |
Cr12_bits_1 <= 0; Cr12_et_zero_3 <= 0; zrl_2 <= 0; |
end |
else if (enable_module) begin |
Cr12_code_entry <= Cr_AC_run_code[code_index]; |
Cr12_JPEG_LSBs_1 <= Cr12_JPEG_LSBs; |
Cr12_amp_shift <= 10 - Cr12_bits; |
Cr12_bits_1 <= Cr12_bits; |
Cr12_et_zero_3 <= Cr12_et_zero_2; |
zrl_2 <= zrl_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_bits <= 0; Cr11_JPEG_LSBs <= 0; |
end |
else if (enable_3) begin |
Cr11_bits <= Cr11_msb ? Cr11_bits_neg : Cr11_bits_pos; |
Cr11_JPEG_LSBs <= Cr11_amp[10:0]; // The top bit of Cr11_amp is the sign bit |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_bits <= 0; Cr12_JPEG_LSBs <= 0; zrl_1 <= 0; |
Cr12_et_zero_2 <= 0; |
end |
else if (enable_module) begin |
Cr12_bits <= Cr12_msb_1 ? Cr12_bits_neg : Cr12_bits_pos; |
Cr12_JPEG_LSBs <= Cr12_amp[9:0]; // The top bit of Cr12_amp is the sign bit |
zrl_1 <= block_counter == 62 & Cr12_et_zero ? 0 : zero_run_length; |
Cr12_et_zero_2 <= Cr12_et_zero_1; |
end |
end |
|
// Cr11_amp is the amplitude that will be represented in bits in the |
// JPEG code, following the run length code |
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_amp <= 0; |
end |
else if (enable_2) begin |
Cr11_amp <= Cr11_msb ? Cr11_1_neg : Cr11_1_pos; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) |
zero_run_length <= 0; |
else if (enable) |
zero_run_length <= 0; |
else if (enable_module) |
zero_run_length <= Cr12_et_zero ? zero_run_length + 1: 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_amp <= 0; |
Cr12_et_zero_1 <= 0; Cr12_msb_1 <= 0; |
end |
else if (enable_module) begin |
Cr12_amp <= Cr12_msb ? Cr12_neg : Cr12_pos; |
Cr12_et_zero_1 <= Cr12_et_zero; |
Cr12_msb_1 <= Cr12_msb; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_1_pos <= 0; Cr11_1_neg <= 0; Cr11_msb <= 0; |
Cr11_previous <= 0; |
end |
else if (enable_1) begin |
Cr11_1_pos <= Cr11_diff; |
Cr11_1_neg <= Cr11_diff - 1; |
Cr11_msb <= Cr11_diff[11]; |
Cr11_previous <= Cr11_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr12_pos <= 0; Cr12_neg <= 0; Cr12_msb <= 0; Cr12_et_zero <= 0; |
Cr13_pos <= 0; Cr13_neg <= 0; Cr13_msb <= 0; Cr13_et_zero <= 0; |
Cr14_pos <= 0; Cr14_neg <= 0; Cr14_msb <= 0; Cr14_et_zero <= 0; |
Cr15_pos <= 0; Cr15_neg <= 0; Cr15_msb <= 0; Cr15_et_zero <= 0; |
Cr16_pos <= 0; Cr16_neg <= 0; Cr16_msb <= 0; Cr16_et_zero <= 0; |
Cr17_pos <= 0; Cr17_neg <= 0; Cr17_msb <= 0; Cr17_et_zero <= 0; |
Cr18_pos <= 0; Cr18_neg <= 0; Cr18_msb <= 0; Cr18_et_zero <= 0; |
Cr21_pos <= 0; Cr21_neg <= 0; Cr21_msb <= 0; Cr21_et_zero <= 0; |
Cr22_pos <= 0; Cr22_neg <= 0; Cr22_msb <= 0; Cr22_et_zero <= 0; |
Cr23_pos <= 0; Cr23_neg <= 0; Cr23_msb <= 0; Cr23_et_zero <= 0; |
Cr24_pos <= 0; Cr24_neg <= 0; Cr24_msb <= 0; Cr24_et_zero <= 0; |
Cr25_pos <= 0; Cr25_neg <= 0; Cr25_msb <= 0; Cr25_et_zero <= 0; |
Cr26_pos <= 0; Cr26_neg <= 0; Cr26_msb <= 0; Cr26_et_zero <= 0; |
Cr27_pos <= 0; Cr27_neg <= 0; Cr27_msb <= 0; Cr27_et_zero <= 0; |
Cr28_pos <= 0; Cr28_neg <= 0; Cr28_msb <= 0; Cr28_et_zero <= 0; |
Cr31_pos <= 0; Cr31_neg <= 0; Cr31_msb <= 0; Cr31_et_zero <= 0; |
Cr32_pos <= 0; Cr32_neg <= 0; Cr32_msb <= 0; Cr32_et_zero <= 0; |
Cr33_pos <= 0; Cr33_neg <= 0; Cr33_msb <= 0; Cr33_et_zero <= 0; |
Cr34_pos <= 0; Cr34_neg <= 0; Cr34_msb <= 0; Cr34_et_zero <= 0; |
Cr35_pos <= 0; Cr35_neg <= 0; Cr35_msb <= 0; Cr35_et_zero <= 0; |
Cr36_pos <= 0; Cr36_neg <= 0; Cr36_msb <= 0; Cr36_et_zero <= 0; |
Cr37_pos <= 0; Cr37_neg <= 0; Cr37_msb <= 0; Cr37_et_zero <= 0; |
Cr38_pos <= 0; Cr38_neg <= 0; Cr38_msb <= 0; Cr38_et_zero <= 0; |
Cr41_pos <= 0; Cr41_neg <= 0; Cr41_msb <= 0; Cr41_et_zero <= 0; |
Cr42_pos <= 0; Cr42_neg <= 0; Cr42_msb <= 0; Cr42_et_zero <= 0; |
Cr43_pos <= 0; Cr43_neg <= 0; Cr43_msb <= 0; Cr43_et_zero <= 0; |
Cr44_pos <= 0; Cr44_neg <= 0; Cr44_msb <= 0; Cr44_et_zero <= 0; |
Cr45_pos <= 0; Cr45_neg <= 0; Cr45_msb <= 0; Cr45_et_zero <= 0; |
Cr46_pos <= 0; Cr46_neg <= 0; Cr46_msb <= 0; Cr46_et_zero <= 0; |
Cr47_pos <= 0; Cr47_neg <= 0; Cr47_msb <= 0; Cr47_et_zero <= 0; |
Cr48_pos <= 0; Cr48_neg <= 0; Cr48_msb <= 0; Cr48_et_zero <= 0; |
Cr51_pos <= 0; Cr51_neg <= 0; Cr51_msb <= 0; Cr51_et_zero <= 0; |
Cr52_pos <= 0; Cr52_neg <= 0; Cr52_msb <= 0; Cr52_et_zero <= 0; |
Cr53_pos <= 0; Cr53_neg <= 0; Cr53_msb <= 0; Cr53_et_zero <= 0; |
Cr54_pos <= 0; Cr54_neg <= 0; Cr54_msb <= 0; Cr54_et_zero <= 0; |
Cr55_pos <= 0; Cr55_neg <= 0; Cr55_msb <= 0; Cr55_et_zero <= 0; |
Cr56_pos <= 0; Cr56_neg <= 0; Cr56_msb <= 0; Cr56_et_zero <= 0; |
Cr57_pos <= 0; Cr57_neg <= 0; Cr57_msb <= 0; Cr57_et_zero <= 0; |
Cr58_pos <= 0; Cr58_neg <= 0; Cr58_msb <= 0; Cr58_et_zero <= 0; |
Cr61_pos <= 0; Cr61_neg <= 0; Cr61_msb <= 0; Cr61_et_zero <= 0; |
Cr62_pos <= 0; Cr62_neg <= 0; Cr62_msb <= 0; Cr62_et_zero <= 0; |
Cr63_pos <= 0; Cr63_neg <= 0; Cr63_msb <= 0; Cr63_et_zero <= 0; |
Cr64_pos <= 0; Cr64_neg <= 0; Cr64_msb <= 0; Cr64_et_zero <= 0; |
Cr65_pos <= 0; Cr65_neg <= 0; Cr65_msb <= 0; Cr65_et_zero <= 0; |
Cr66_pos <= 0; Cr66_neg <= 0; Cr66_msb <= 0; Cr66_et_zero <= 0; |
Cr67_pos <= 0; Cr67_neg <= 0; Cr67_msb <= 0; Cr67_et_zero <= 0; |
Cr68_pos <= 0; Cr68_neg <= 0; Cr68_msb <= 0; Cr68_et_zero <= 0; |
Cr71_pos <= 0; Cr71_neg <= 0; Cr71_msb <= 0; Cr71_et_zero <= 0; |
Cr72_pos <= 0; Cr72_neg <= 0; Cr72_msb <= 0; Cr72_et_zero <= 0; |
Cr73_pos <= 0; Cr73_neg <= 0; Cr73_msb <= 0; Cr73_et_zero <= 0; |
Cr74_pos <= 0; Cr74_neg <= 0; Cr74_msb <= 0; Cr74_et_zero <= 0; |
Cr75_pos <= 0; Cr75_neg <= 0; Cr75_msb <= 0; Cr75_et_zero <= 0; |
Cr76_pos <= 0; Cr76_neg <= 0; Cr76_msb <= 0; Cr76_et_zero <= 0; |
Cr77_pos <= 0; Cr77_neg <= 0; Cr77_msb <= 0; Cr77_et_zero <= 0; |
Cr78_pos <= 0; Cr78_neg <= 0; Cr78_msb <= 0; Cr78_et_zero <= 0; |
Cr81_pos <= 0; Cr81_neg <= 0; Cr81_msb <= 0; Cr81_et_zero <= 0; |
Cr82_pos <= 0; Cr82_neg <= 0; Cr82_msb <= 0; Cr82_et_zero <= 0; |
Cr83_pos <= 0; Cr83_neg <= 0; Cr83_msb <= 0; Cr83_et_zero <= 0; |
Cr84_pos <= 0; Cr84_neg <= 0; Cr84_msb <= 0; Cr84_et_zero <= 0; |
Cr85_pos <= 0; Cr85_neg <= 0; Cr85_msb <= 0; Cr85_et_zero <= 0; |
Cr86_pos <= 0; Cr86_neg <= 0; Cr86_msb <= 0; Cr86_et_zero <= 0; |
Cr87_pos <= 0; Cr87_neg <= 0; Cr87_msb <= 0; Cr87_et_zero <= 0; |
Cr88_pos <= 0; Cr88_neg <= 0; Cr88_msb <= 0; Cr88_et_zero <= 0; |
end |
else if (enable) begin |
Cr12_pos <= Cr12; |
Cr12_neg <= Cr12 - 1; |
Cr12_msb <= Cr12[10]; |
Cr12_et_zero <= !(|Cr12); |
Cr13_pos <= Cr13; |
Cr13_neg <= Cr13 - 1; |
Cr13_msb <= Cr13[10]; |
Cr13_et_zero <= !(|Cr13); |
Cr14_pos <= Cr14; |
Cr14_neg <= Cr14 - 1; |
Cr14_msb <= Cr14[10]; |
Cr14_et_zero <= !(|Cr14); |
Cr15_pos <= Cr15; |
Cr15_neg <= Cr15 - 1; |
Cr15_msb <= Cr15[10]; |
Cr15_et_zero <= !(|Cr15); |
Cr16_pos <= Cr16; |
Cr16_neg <= Cr16 - 1; |
Cr16_msb <= Cr16[10]; |
Cr16_et_zero <= !(|Cr16); |
Cr17_pos <= Cr17; |
Cr17_neg <= Cr17 - 1; |
Cr17_msb <= Cr17[10]; |
Cr17_et_zero <= !(|Cr17); |
Cr18_pos <= Cr18; |
Cr18_neg <= Cr18 - 1; |
Cr18_msb <= Cr18[10]; |
Cr18_et_zero <= !(|Cr18); |
Cr21_pos <= Cr21; |
Cr21_neg <= Cr21 - 1; |
Cr21_msb <= Cr21[10]; |
Cr21_et_zero <= !(|Cr21); |
Cr22_pos <= Cr22; |
Cr22_neg <= Cr22 - 1; |
Cr22_msb <= Cr22[10]; |
Cr22_et_zero <= !(|Cr22); |
Cr23_pos <= Cr23; |
Cr23_neg <= Cr23 - 1; |
Cr23_msb <= Cr23[10]; |
Cr23_et_zero <= !(|Cr23); |
Cr24_pos <= Cr24; |
Cr24_neg <= Cr24 - 1; |
Cr24_msb <= Cr24[10]; |
Cr24_et_zero <= !(|Cr24); |
Cr25_pos <= Cr25; |
Cr25_neg <= Cr25 - 1; |
Cr25_msb <= Cr25[10]; |
Cr25_et_zero <= !(|Cr25); |
Cr26_pos <= Cr26; |
Cr26_neg <= Cr26 - 1; |
Cr26_msb <= Cr26[10]; |
Cr26_et_zero <= !(|Cr26); |
Cr27_pos <= Cr27; |
Cr27_neg <= Cr27 - 1; |
Cr27_msb <= Cr27[10]; |
Cr27_et_zero <= !(|Cr27); |
Cr28_pos <= Cr28; |
Cr28_neg <= Cr28 - 1; |
Cr28_msb <= Cr28[10]; |
Cr28_et_zero <= !(|Cr28); |
Cr31_pos <= Cr31; |
Cr31_neg <= Cr31 - 1; |
Cr31_msb <= Cr31[10]; |
Cr31_et_zero <= !(|Cr31); |
Cr32_pos <= Cr32; |
Cr32_neg <= Cr32 - 1; |
Cr32_msb <= Cr32[10]; |
Cr32_et_zero <= !(|Cr32); |
Cr33_pos <= Cr33; |
Cr33_neg <= Cr33 - 1; |
Cr33_msb <= Cr33[10]; |
Cr33_et_zero <= !(|Cr33); |
Cr34_pos <= Cr34; |
Cr34_neg <= Cr34 - 1; |
Cr34_msb <= Cr34[10]; |
Cr34_et_zero <= !(|Cr34); |
Cr35_pos <= Cr35; |
Cr35_neg <= Cr35 - 1; |
Cr35_msb <= Cr35[10]; |
Cr35_et_zero <= !(|Cr35); |
Cr36_pos <= Cr36; |
Cr36_neg <= Cr36 - 1; |
Cr36_msb <= Cr36[10]; |
Cr36_et_zero <= !(|Cr36); |
Cr37_pos <= Cr37; |
Cr37_neg <= Cr37 - 1; |
Cr37_msb <= Cr37[10]; |
Cr37_et_zero <= !(|Cr37); |
Cr38_pos <= Cr38; |
Cr38_neg <= Cr38 - 1; |
Cr38_msb <= Cr38[10]; |
Cr38_et_zero <= !(|Cr38); |
Cr41_pos <= Cr41; |
Cr41_neg <= Cr41 - 1; |
Cr41_msb <= Cr41[10]; |
Cr41_et_zero <= !(|Cr41); |
Cr42_pos <= Cr42; |
Cr42_neg <= Cr42 - 1; |
Cr42_msb <= Cr42[10]; |
Cr42_et_zero <= !(|Cr42); |
Cr43_pos <= Cr43; |
Cr43_neg <= Cr43 - 1; |
Cr43_msb <= Cr43[10]; |
Cr43_et_zero <= !(|Cr43); |
Cr44_pos <= Cr44; |
Cr44_neg <= Cr44 - 1; |
Cr44_msb <= Cr44[10]; |
Cr44_et_zero <= !(|Cr44); |
Cr45_pos <= Cr45; |
Cr45_neg <= Cr45 - 1; |
Cr45_msb <= Cr45[10]; |
Cr45_et_zero <= !(|Cr45); |
Cr46_pos <= Cr46; |
Cr46_neg <= Cr46 - 1; |
Cr46_msb <= Cr46[10]; |
Cr46_et_zero <= !(|Cr46); |
Cr47_pos <= Cr47; |
Cr47_neg <= Cr47 - 1; |
Cr47_msb <= Cr47[10]; |
Cr47_et_zero <= !(|Cr47); |
Cr48_pos <= Cr48; |
Cr48_neg <= Cr48 - 1; |
Cr48_msb <= Cr48[10]; |
Cr48_et_zero <= !(|Cr48); |
Cr51_pos <= Cr51; |
Cr51_neg <= Cr51 - 1; |
Cr51_msb <= Cr51[10]; |
Cr51_et_zero <= !(|Cr51); |
Cr52_pos <= Cr52; |
Cr52_neg <= Cr52 - 1; |
Cr52_msb <= Cr52[10]; |
Cr52_et_zero <= !(|Cr52); |
Cr53_pos <= Cr53; |
Cr53_neg <= Cr53 - 1; |
Cr53_msb <= Cr53[10]; |
Cr53_et_zero <= !(|Cr53); |
Cr54_pos <= Cr54; |
Cr54_neg <= Cr54 - 1; |
Cr54_msb <= Cr54[10]; |
Cr54_et_zero <= !(|Cr54); |
Cr55_pos <= Cr55; |
Cr55_neg <= Cr55 - 1; |
Cr55_msb <= Cr55[10]; |
Cr55_et_zero <= !(|Cr55); |
Cr56_pos <= Cr56; |
Cr56_neg <= Cr56 - 1; |
Cr56_msb <= Cr56[10]; |
Cr56_et_zero <= !(|Cr56); |
Cr57_pos <= Cr57; |
Cr57_neg <= Cr57 - 1; |
Cr57_msb <= Cr57[10]; |
Cr57_et_zero <= !(|Cr57); |
Cr58_pos <= Cr58; |
Cr58_neg <= Cr58 - 1; |
Cr58_msb <= Cr58[10]; |
Cr58_et_zero <= !(|Cr58); |
Cr61_pos <= Cr61; |
Cr61_neg <= Cr61 - 1; |
Cr61_msb <= Cr61[10]; |
Cr61_et_zero <= !(|Cr61); |
Cr62_pos <= Cr62; |
Cr62_neg <= Cr62 - 1; |
Cr62_msb <= Cr62[10]; |
Cr62_et_zero <= !(|Cr62); |
Cr63_pos <= Cr63; |
Cr63_neg <= Cr63 - 1; |
Cr63_msb <= Cr63[10]; |
Cr63_et_zero <= !(|Cr63); |
Cr64_pos <= Cr64; |
Cr64_neg <= Cr64 - 1; |
Cr64_msb <= Cr64[10]; |
Cr64_et_zero <= !(|Cr64); |
Cr65_pos <= Cr65; |
Cr65_neg <= Cr65 - 1; |
Cr65_msb <= Cr65[10]; |
Cr65_et_zero <= !(|Cr65); |
Cr66_pos <= Cr66; |
Cr66_neg <= Cr66 - 1; |
Cr66_msb <= Cr66[10]; |
Cr66_et_zero <= !(|Cr66); |
Cr67_pos <= Cr67; |
Cr67_neg <= Cr67 - 1; |
Cr67_msb <= Cr67[10]; |
Cr67_et_zero <= !(|Cr67); |
Cr68_pos <= Cr68; |
Cr68_neg <= Cr68 - 1; |
Cr68_msb <= Cr68[10]; |
Cr68_et_zero <= !(|Cr68); |
Cr71_pos <= Cr71; |
Cr71_neg <= Cr71 - 1; |
Cr71_msb <= Cr71[10]; |
Cr71_et_zero <= !(|Cr71); |
Cr72_pos <= Cr72; |
Cr72_neg <= Cr72 - 1; |
Cr72_msb <= Cr72[10]; |
Cr72_et_zero <= !(|Cr72); |
Cr73_pos <= Cr73; |
Cr73_neg <= Cr73 - 1; |
Cr73_msb <= Cr73[10]; |
Cr73_et_zero <= !(|Cr73); |
Cr74_pos <= Cr74; |
Cr74_neg <= Cr74 - 1; |
Cr74_msb <= Cr74[10]; |
Cr74_et_zero <= !(|Cr74); |
Cr75_pos <= Cr75; |
Cr75_neg <= Cr75 - 1; |
Cr75_msb <= Cr75[10]; |
Cr75_et_zero <= !(|Cr75); |
Cr76_pos <= Cr76; |
Cr76_neg <= Cr76 - 1; |
Cr76_msb <= Cr76[10]; |
Cr76_et_zero <= !(|Cr76); |
Cr77_pos <= Cr77; |
Cr77_neg <= Cr77 - 1; |
Cr77_msb <= Cr77[10]; |
Cr77_et_zero <= !(|Cr77); |
Cr78_pos <= Cr78; |
Cr78_neg <= Cr78 - 1; |
Cr78_msb <= Cr78[10]; |
Cr78_et_zero <= !(|Cr78); |
Cr81_pos <= Cr81; |
Cr81_neg <= Cr81 - 1; |
Cr81_msb <= Cr81[10]; |
Cr81_et_zero <= !(|Cr81); |
Cr82_pos <= Cr82; |
Cr82_neg <= Cr82 - 1; |
Cr82_msb <= Cr82[10]; |
Cr82_et_zero <= !(|Cr82); |
Cr83_pos <= Cr83; |
Cr83_neg <= Cr83 - 1; |
Cr83_msb <= Cr83[10]; |
Cr83_et_zero <= !(|Cr83); |
Cr84_pos <= Cr84; |
Cr84_neg <= Cr84 - 1; |
Cr84_msb <= Cr84[10]; |
Cr84_et_zero <= !(|Cr84); |
Cr85_pos <= Cr85; |
Cr85_neg <= Cr85 - 1; |
Cr85_msb <= Cr85[10]; |
Cr85_et_zero <= !(|Cr85); |
Cr86_pos <= Cr86; |
Cr86_neg <= Cr86 - 1; |
Cr86_msb <= Cr86[10]; |
Cr86_et_zero <= !(|Cr86); |
Cr87_pos <= Cr87; |
Cr87_neg <= Cr87 - 1; |
Cr87_msb <= Cr87[10]; |
Cr87_et_zero <= !(|Cr87); |
Cr88_pos <= Cr88; |
Cr88_neg <= Cr88 - 1; |
Cr88_msb <= Cr88[10]; |
Cr88_et_zero <= !(|Cr88); |
end |
else if (enable_module) begin |
Cr12_pos <= Cr21_pos; |
Cr12_neg <= Cr21_neg; |
Cr12_msb <= Cr21_msb; |
Cr12_et_zero <= Cr21_et_zero; |
Cr21_pos <= Cr31_pos; |
Cr21_neg <= Cr31_neg; |
Cr21_msb <= Cr31_msb; |
Cr21_et_zero <= Cr31_et_zero; |
Cr31_pos <= Cr22_pos; |
Cr31_neg <= Cr22_neg; |
Cr31_msb <= Cr22_msb; |
Cr31_et_zero <= Cr22_et_zero; |
Cr22_pos <= Cr13_pos; |
Cr22_neg <= Cr13_neg; |
Cr22_msb <= Cr13_msb; |
Cr22_et_zero <= Cr13_et_zero; |
Cr13_pos <= Cr14_pos; |
Cr13_neg <= Cr14_neg; |
Cr13_msb <= Cr14_msb; |
Cr13_et_zero <= Cr14_et_zero; |
Cr14_pos <= Cr23_pos; |
Cr14_neg <= Cr23_neg; |
Cr14_msb <= Cr23_msb; |
Cr14_et_zero <= Cr23_et_zero; |
Cr23_pos <= Cr32_pos; |
Cr23_neg <= Cr32_neg; |
Cr23_msb <= Cr32_msb; |
Cr23_et_zero <= Cr32_et_zero; |
Cr32_pos <= Cr41_pos; |
Cr32_neg <= Cr41_neg; |
Cr32_msb <= Cr41_msb; |
Cr32_et_zero <= Cr41_et_zero; |
Cr41_pos <= Cr51_pos; |
Cr41_neg <= Cr51_neg; |
Cr41_msb <= Cr51_msb; |
Cr41_et_zero <= Cr51_et_zero; |
Cr51_pos <= Cr42_pos; |
Cr51_neg <= Cr42_neg; |
Cr51_msb <= Cr42_msb; |
Cr51_et_zero <= Cr42_et_zero; |
Cr42_pos <= Cr33_pos; |
Cr42_neg <= Cr33_neg; |
Cr42_msb <= Cr33_msb; |
Cr42_et_zero <= Cr33_et_zero; |
Cr33_pos <= Cr24_pos; |
Cr33_neg <= Cr24_neg; |
Cr33_msb <= Cr24_msb; |
Cr33_et_zero <= Cr24_et_zero; |
Cr24_pos <= Cr15_pos; |
Cr24_neg <= Cr15_neg; |
Cr24_msb <= Cr15_msb; |
Cr24_et_zero <= Cr15_et_zero; |
Cr15_pos <= Cr16_pos; |
Cr15_neg <= Cr16_neg; |
Cr15_msb <= Cr16_msb; |
Cr15_et_zero <= Cr16_et_zero; |
Cr16_pos <= Cr25_pos; |
Cr16_neg <= Cr25_neg; |
Cr16_msb <= Cr25_msb; |
Cr16_et_zero <= Cr25_et_zero; |
Cr25_pos <= Cr34_pos; |
Cr25_neg <= Cr34_neg; |
Cr25_msb <= Cr34_msb; |
Cr25_et_zero <= Cr34_et_zero; |
Cr34_pos <= Cr43_pos; |
Cr34_neg <= Cr43_neg; |
Cr34_msb <= Cr43_msb; |
Cr34_et_zero <= Cr43_et_zero; |
Cr43_pos <= Cr52_pos; |
Cr43_neg <= Cr52_neg; |
Cr43_msb <= Cr52_msb; |
Cr43_et_zero <= Cr52_et_zero; |
Cr52_pos <= Cr61_pos; |
Cr52_neg <= Cr61_neg; |
Cr52_msb <= Cr61_msb; |
Cr52_et_zero <= Cr61_et_zero; |
Cr61_pos <= Cr71_pos; |
Cr61_neg <= Cr71_neg; |
Cr61_msb <= Cr71_msb; |
Cr61_et_zero <= Cr71_et_zero; |
Cr71_pos <= Cr62_pos; |
Cr71_neg <= Cr62_neg; |
Cr71_msb <= Cr62_msb; |
Cr71_et_zero <= Cr62_et_zero; |
Cr62_pos <= Cr53_pos; |
Cr62_neg <= Cr53_neg; |
Cr62_msb <= Cr53_msb; |
Cr62_et_zero <= Cr53_et_zero; |
Cr53_pos <= Cr44_pos; |
Cr53_neg <= Cr44_neg; |
Cr53_msb <= Cr44_msb; |
Cr53_et_zero <= Cr44_et_zero; |
Cr44_pos <= Cr35_pos; |
Cr44_neg <= Cr35_neg; |
Cr44_msb <= Cr35_msb; |
Cr44_et_zero <= Cr35_et_zero; |
Cr35_pos <= Cr26_pos; |
Cr35_neg <= Cr26_neg; |
Cr35_msb <= Cr26_msb; |
Cr35_et_zero <= Cr26_et_zero; |
Cr26_pos <= Cr17_pos; |
Cr26_neg <= Cr17_neg; |
Cr26_msb <= Cr17_msb; |
Cr26_et_zero <= Cr17_et_zero; |
Cr17_pos <= Cr18_pos; |
Cr17_neg <= Cr18_neg; |
Cr17_msb <= Cr18_msb; |
Cr17_et_zero <= Cr18_et_zero; |
Cr18_pos <= Cr27_pos; |
Cr18_neg <= Cr27_neg; |
Cr18_msb <= Cr27_msb; |
Cr18_et_zero <= Cr27_et_zero; |
Cr27_pos <= Cr36_pos; |
Cr27_neg <= Cr36_neg; |
Cr27_msb <= Cr36_msb; |
Cr27_et_zero <= Cr36_et_zero; |
Cr36_pos <= Cr45_pos; |
Cr36_neg <= Cr45_neg; |
Cr36_msb <= Cr45_msb; |
Cr36_et_zero <= Cr45_et_zero; |
Cr45_pos <= Cr54_pos; |
Cr45_neg <= Cr54_neg; |
Cr45_msb <= Cr54_msb; |
Cr45_et_zero <= Cr54_et_zero; |
Cr54_pos <= Cr63_pos; |
Cr54_neg <= Cr63_neg; |
Cr54_msb <= Cr63_msb; |
Cr54_et_zero <= Cr63_et_zero; |
Cr63_pos <= Cr72_pos; |
Cr63_neg <= Cr72_neg; |
Cr63_msb <= Cr72_msb; |
Cr63_et_zero <= Cr72_et_zero; |
Cr72_pos <= Cr81_pos; |
Cr72_neg <= Cr81_neg; |
Cr72_msb <= Cr81_msb; |
Cr72_et_zero <= Cr81_et_zero; |
Cr81_pos <= Cr82_pos; |
Cr81_neg <= Cr82_neg; |
Cr81_msb <= Cr82_msb; |
Cr81_et_zero <= Cr82_et_zero; |
Cr82_pos <= Cr73_pos; |
Cr82_neg <= Cr73_neg; |
Cr82_msb <= Cr73_msb; |
Cr82_et_zero <= Cr73_et_zero; |
Cr73_pos <= Cr64_pos; |
Cr73_neg <= Cr64_neg; |
Cr73_msb <= Cr64_msb; |
Cr73_et_zero <= Cr64_et_zero; |
Cr64_pos <= Cr55_pos; |
Cr64_neg <= Cr55_neg; |
Cr64_msb <= Cr55_msb; |
Cr64_et_zero <= Cr55_et_zero; |
Cr55_pos <= Cr46_pos; |
Cr55_neg <= Cr46_neg; |
Cr55_msb <= Cr46_msb; |
Cr55_et_zero <= Cr46_et_zero; |
Cr46_pos <= Cr37_pos; |
Cr46_neg <= Cr37_neg; |
Cr46_msb <= Cr37_msb; |
Cr46_et_zero <= Cr37_et_zero; |
Cr37_pos <= Cr28_pos; |
Cr37_neg <= Cr28_neg; |
Cr37_msb <= Cr28_msb; |
Cr37_et_zero <= Cr28_et_zero; |
Cr28_pos <= Cr38_pos; |
Cr28_neg <= Cr38_neg; |
Cr28_msb <= Cr38_msb; |
Cr28_et_zero <= Cr38_et_zero; |
Cr38_pos <= Cr47_pos; |
Cr38_neg <= Cr47_neg; |
Cr38_msb <= Cr47_msb; |
Cr38_et_zero <= Cr47_et_zero; |
Cr47_pos <= Cr56_pos; |
Cr47_neg <= Cr56_neg; |
Cr47_msb <= Cr56_msb; |
Cr47_et_zero <= Cr56_et_zero; |
Cr56_pos <= Cr65_pos; |
Cr56_neg <= Cr65_neg; |
Cr56_msb <= Cr65_msb; |
Cr56_et_zero <= Cr65_et_zero; |
Cr65_pos <= Cr74_pos; |
Cr65_neg <= Cr74_neg; |
Cr65_msb <= Cr74_msb; |
Cr65_et_zero <= Cr74_et_zero; |
Cr74_pos <= Cr83_pos; |
Cr74_neg <= Cr83_neg; |
Cr74_msb <= Cr83_msb; |
Cr74_et_zero <= Cr83_et_zero; |
Cr83_pos <= Cr84_pos; |
Cr83_neg <= Cr84_neg; |
Cr83_msb <= Cr84_msb; |
Cr83_et_zero <= Cr84_et_zero; |
Cr84_pos <= Cr75_pos; |
Cr84_neg <= Cr75_neg; |
Cr84_msb <= Cr75_msb; |
Cr84_et_zero <= Cr75_et_zero; |
Cr75_pos <= Cr66_pos; |
Cr75_neg <= Cr66_neg; |
Cr75_msb <= Cr66_msb; |
Cr75_et_zero <= Cr66_et_zero; |
Cr66_pos <= Cr57_pos; |
Cr66_neg <= Cr57_neg; |
Cr66_msb <= Cr57_msb; |
Cr66_et_zero <= Cr57_et_zero; |
Cr57_pos <= Cr48_pos; |
Cr57_neg <= Cr48_neg; |
Cr57_msb <= Cr48_msb; |
Cr57_et_zero <= Cr48_et_zero; |
Cr48_pos <= Cr58_pos; |
Cr48_neg <= Cr58_neg; |
Cr48_msb <= Cr58_msb; |
Cr48_et_zero <= Cr58_et_zero; |
Cr58_pos <= Cr67_pos; |
Cr58_neg <= Cr67_neg; |
Cr58_msb <= Cr67_msb; |
Cr58_et_zero <= Cr67_et_zero; |
Cr67_pos <= Cr76_pos; |
Cr67_neg <= Cr76_neg; |
Cr67_msb <= Cr76_msb; |
Cr67_et_zero <= Cr76_et_zero; |
Cr76_pos <= Cr85_pos; |
Cr76_neg <= Cr85_neg; |
Cr76_msb <= Cr85_msb; |
Cr76_et_zero <= Cr85_et_zero; |
Cr85_pos <= Cr86_pos; |
Cr85_neg <= Cr86_neg; |
Cr85_msb <= Cr86_msb; |
Cr85_et_zero <= Cr86_et_zero; |
Cr86_pos <= Cr77_pos; |
Cr86_neg <= Cr77_neg; |
Cr86_msb <= Cr77_msb; |
Cr86_et_zero <= Cr77_et_zero; |
Cr77_pos <= Cr68_pos; |
Cr77_neg <= Cr68_neg; |
Cr77_msb <= Cr68_msb; |
Cr77_et_zero <= Cr68_et_zero; |
Cr68_pos <= Cr78_pos; |
Cr68_neg <= Cr78_neg; |
Cr68_msb <= Cr78_msb; |
Cr68_et_zero <= Cr78_et_zero; |
Cr78_pos <= Cr87_pos; |
Cr78_neg <= Cr87_neg; |
Cr78_msb <= Cr87_msb; |
Cr78_et_zero <= Cr87_et_zero; |
Cr87_pos <= Cr88_pos; |
Cr87_neg <= Cr88_neg; |
Cr87_msb <= Cr88_msb; |
Cr87_et_zero <= Cr88_et_zero; |
Cr88_pos <= 0; |
Cr88_neg <= 0; |
Cr88_msb <= 0; |
Cr88_et_zero <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cr11_diff <= 0; Cr11_1 <= 0; |
end |
else if (enable) begin // Need to sign extend Cr11 to 12 bits |
Cr11_diff <= {Cr11[10], Cr11} - Cr11_previous; |
Cr11_1 <= Cr11[10] ? { 1'b1, Cr11 } : { 1'b0, Cr11 }; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cr11_bits_pos <= 0; |
else if (Cr11_1_pos[10] == 1) |
Cr11_bits_pos <= 11; |
else if (Cr11_1_pos[9] == 1) |
Cr11_bits_pos <= 10; |
else if (Cr11_1_pos[8] == 1) |
Cr11_bits_pos <= 9; |
else if (Cr11_1_pos[7] == 1) |
Cr11_bits_pos <= 8; |
else if (Cr11_1_pos[6] == 1) |
Cr11_bits_pos <= 7; |
else if (Cr11_1_pos[5] == 1) |
Cr11_bits_pos <= 6; |
else if (Cr11_1_pos[4] == 1) |
Cr11_bits_pos <= 5; |
else if (Cr11_1_pos[3] == 1) |
Cr11_bits_pos <= 4; |
else if (Cr11_1_pos[2] == 1) |
Cr11_bits_pos <= 3; |
else if (Cr11_1_pos[1] == 1) |
Cr11_bits_pos <= 2; |
else if (Cr11_1_pos[0] == 1) |
Cr11_bits_pos <= 1; |
else |
Cr11_bits_pos <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cr11_bits_neg <= 0; |
else if (Cr11_1_neg[10] == 0) |
Cr11_bits_neg <= 11; |
else if (Cr11_1_neg[9] == 0) |
Cr11_bits_neg <= 10; |
else if (Cr11_1_neg[8] == 0) |
Cr11_bits_neg <= 9; |
else if (Cr11_1_neg[7] == 0) |
Cr11_bits_neg <= 8; |
else if (Cr11_1_neg[6] == 0) |
Cr11_bits_neg <= 7; |
else if (Cr11_1_neg[5] == 0) |
Cr11_bits_neg <= 6; |
else if (Cr11_1_neg[4] == 0) |
Cr11_bits_neg <= 5; |
else if (Cr11_1_neg[3] == 0) |
Cr11_bits_neg <= 4; |
else if (Cr11_1_neg[2] == 0) |
Cr11_bits_neg <= 3; |
else if (Cr11_1_neg[1] == 0) |
Cr11_bits_neg <= 2; |
else if (Cr11_1_neg[0] == 0) |
Cr11_bits_neg <= 1; |
else |
Cr11_bits_neg <= 0; |
end |
|
|
always @(posedge clk) |
begin |
if (rst) |
Cr12_bits_pos <= 0; |
else if (Cr12_pos[9] == 1) |
Cr12_bits_pos <= 10; |
else if (Cr12_pos[8] == 1) |
Cr12_bits_pos <= 9; |
else if (Cr12_pos[7] == 1) |
Cr12_bits_pos <= 8; |
else if (Cr12_pos[6] == 1) |
Cr12_bits_pos <= 7; |
else if (Cr12_pos[5] == 1) |
Cr12_bits_pos <= 6; |
else if (Cr12_pos[4] == 1) |
Cr12_bits_pos <= 5; |
else if (Cr12_pos[3] == 1) |
Cr12_bits_pos <= 4; |
else if (Cr12_pos[2] == 1) |
Cr12_bits_pos <= 3; |
else if (Cr12_pos[1] == 1) |
Cr12_bits_pos <= 2; |
else if (Cr12_pos[0] == 1) |
Cr12_bits_pos <= 1; |
else |
Cr12_bits_pos <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cr12_bits_neg <= 0; |
else if (Cr12_neg[9] == 0) |
Cr12_bits_neg <= 10; |
else if (Cr12_neg[8] == 0) |
Cr12_bits_neg <= 9; |
else if (Cr12_neg[7] == 0) |
Cr12_bits_neg <= 8; |
else if (Cr12_neg[6] == 0) |
Cr12_bits_neg <= 7; |
else if (Cr12_neg[5] == 0) |
Cr12_bits_neg <= 6; |
else if (Cr12_neg[4] == 0) |
Cr12_bits_neg <= 5; |
else if (Cr12_neg[3] == 0) |
Cr12_bits_neg <= 4; |
else if (Cr12_neg[2] == 0) |
Cr12_bits_neg <= 3; |
else if (Cr12_neg[1] == 0) |
Cr12_bits_neg <= 2; |
else if (Cr12_neg[0] == 0) |
Cr12_bits_neg <= 1; |
else |
Cr12_bits_neg <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_module <= 0; |
end |
else if (enable) begin |
enable_module <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_latch_7 <= 0; |
end |
else if (block_counter == 68) begin |
enable_latch_7 <= 0; |
end |
else if (enable_6) begin |
enable_latch_7 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_latch_8 <= 0; |
end |
else if (enable_7) begin |
enable_latch_8 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; |
enable_4 <= 0; enable_5 <= 0; enable_6 <= 0; |
enable_7 <= 0; enable_8 <= 0; enable_9 <= 0; |
enable_10 <= 0; enable_11 <= 0; enable_12 <= 0; |
enable_13 <= 0; |
end |
else begin |
enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2; |
enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5; |
enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8; |
enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11; |
enable_13 <= enable_12; |
end |
end |
|
/* These Cr DC and AC code lengths, run lengths, and bit codes |
were created from the Huffman table entries in the JPEG file header. |
For different Huffman tables for different images, these values |
below will need to be changed. I created a matlab file to automatically |
create these entries from the already encoded JPEG image. This matlab program |
won't be any help if you're starting from scratch with a .tif or other |
raw image file format. The values below come from a Huffman table, they |
do not actually create the Huffman table based on the probabilities of |
each code created from the image data. Crou will need another program to |
create the optimal Huffman table, or you can go with a generic Huffman table, |
which will have slightly less than the best compression.*/ |
|
|
always @(posedge clk) |
begin |
Cr_DC_code_length[0] <= 2; |
Cr_DC_code_length[1] <= 2; |
Cr_DC_code_length[2] <= 2; |
Cr_DC_code_length[3] <= 3; |
Cr_DC_code_length[4] <= 4; |
Cr_DC_code_length[5] <= 5; |
Cr_DC_code_length[6] <= 6; |
Cr_DC_code_length[7] <= 7; |
Cr_DC_code_length[8] <= 8; |
Cr_DC_code_length[9] <= 9; |
Cr_DC_code_length[10] <= 10; |
Cr_DC_code_length[11] <= 11; |
Cr_DC[0] <= 11'b00000000000; |
Cr_DC[1] <= 11'b01000000000; |
Cr_DC[2] <= 11'b10000000000; |
Cr_DC[3] <= 11'b11000000000; |
Cr_DC[4] <= 11'b11100000000; |
Cr_DC[5] <= 11'b11110000000; |
Cr_DC[6] <= 11'b11111000000; |
Cr_DC[7] <= 11'b11111100000; |
Cr_DC[8] <= 11'b11111110000; |
Cr_DC[9] <= 11'b11111111000; |
Cr_DC[10] <= 11'b11111111100; |
Cr_DC[11] <= 11'b11111111110; |
Cr_AC_code_length[0] <= 2; |
Cr_AC_code_length[1] <= 2; |
Cr_AC_code_length[2] <= 3; |
Cr_AC_code_length[3] <= 4; |
Cr_AC_code_length[4] <= 4; |
Cr_AC_code_length[5] <= 4; |
Cr_AC_code_length[6] <= 5; |
Cr_AC_code_length[7] <= 5; |
Cr_AC_code_length[8] <= 5; |
Cr_AC_code_length[9] <= 6; |
Cr_AC_code_length[10] <= 6; |
Cr_AC_code_length[11] <= 7; |
Cr_AC_code_length[12] <= 7; |
Cr_AC_code_length[13] <= 7; |
Cr_AC_code_length[14] <= 7; |
Cr_AC_code_length[15] <= 8; |
Cr_AC_code_length[16] <= 8; |
Cr_AC_code_length[17] <= 8; |
Cr_AC_code_length[18] <= 9; |
Cr_AC_code_length[19] <= 9; |
Cr_AC_code_length[20] <= 9; |
Cr_AC_code_length[21] <= 9; |
Cr_AC_code_length[22] <= 9; |
Cr_AC_code_length[23] <= 10; |
Cr_AC_code_length[24] <= 10; |
Cr_AC_code_length[25] <= 10; |
Cr_AC_code_length[26] <= 10; |
Cr_AC_code_length[27] <= 10; |
Cr_AC_code_length[28] <= 11; |
Cr_AC_code_length[29] <= 11; |
Cr_AC_code_length[30] <= 11; |
Cr_AC_code_length[31] <= 11; |
Cr_AC_code_length[32] <= 12; |
Cr_AC_code_length[33] <= 12; |
Cr_AC_code_length[34] <= 12; |
Cr_AC_code_length[35] <= 12; |
Cr_AC_code_length[36] <= 15; |
Cr_AC_code_length[37] <= 16; |
Cr_AC_code_length[38] <= 16; |
Cr_AC_code_length[39] <= 16; |
Cr_AC_code_length[40] <= 16; |
Cr_AC_code_length[41] <= 16; |
Cr_AC_code_length[42] <= 16; |
Cr_AC_code_length[43] <= 16; |
Cr_AC_code_length[44] <= 16; |
Cr_AC_code_length[45] <= 16; |
Cr_AC_code_length[46] <= 16; |
Cr_AC_code_length[47] <= 16; |
Cr_AC_code_length[48] <= 16; |
Cr_AC_code_length[49] <= 16; |
Cr_AC_code_length[50] <= 16; |
Cr_AC_code_length[51] <= 16; |
Cr_AC_code_length[52] <= 16; |
Cr_AC_code_length[53] <= 16; |
Cr_AC_code_length[54] <= 16; |
Cr_AC_code_length[55] <= 16; |
Cr_AC_code_length[56] <= 16; |
Cr_AC_code_length[57] <= 16; |
Cr_AC_code_length[58] <= 16; |
Cr_AC_code_length[59] <= 16; |
Cr_AC_code_length[60] <= 16; |
Cr_AC_code_length[61] <= 16; |
Cr_AC_code_length[62] <= 16; |
Cr_AC_code_length[63] <= 16; |
Cr_AC_code_length[64] <= 16; |
Cr_AC_code_length[65] <= 16; |
Cr_AC_code_length[66] <= 16; |
Cr_AC_code_length[67] <= 16; |
Cr_AC_code_length[68] <= 16; |
Cr_AC_code_length[69] <= 16; |
Cr_AC_code_length[70] <= 16; |
Cr_AC_code_length[71] <= 16; |
Cr_AC_code_length[72] <= 16; |
Cr_AC_code_length[73] <= 16; |
Cr_AC_code_length[74] <= 16; |
Cr_AC_code_length[75] <= 16; |
Cr_AC_code_length[76] <= 16; |
Cr_AC_code_length[77] <= 16; |
Cr_AC_code_length[78] <= 16; |
Cr_AC_code_length[79] <= 16; |
Cr_AC_code_length[80] <= 16; |
Cr_AC_code_length[81] <= 16; |
Cr_AC_code_length[82] <= 16; |
Cr_AC_code_length[83] <= 16; |
Cr_AC_code_length[84] <= 16; |
Cr_AC_code_length[85] <= 16; |
Cr_AC_code_length[86] <= 16; |
Cr_AC_code_length[87] <= 16; |
Cr_AC_code_length[88] <= 16; |
Cr_AC_code_length[89] <= 16; |
Cr_AC_code_length[90] <= 16; |
Cr_AC_code_length[91] <= 16; |
Cr_AC_code_length[92] <= 16; |
Cr_AC_code_length[93] <= 16; |
Cr_AC_code_length[94] <= 16; |
Cr_AC_code_length[95] <= 16; |
Cr_AC_code_length[96] <= 16; |
Cr_AC_code_length[97] <= 16; |
Cr_AC_code_length[98] <= 16; |
Cr_AC_code_length[99] <= 16; |
Cr_AC_code_length[100] <= 16; |
Cr_AC_code_length[101] <= 16; |
Cr_AC_code_length[102] <= 16; |
Cr_AC_code_length[103] <= 16; |
Cr_AC_code_length[104] <= 16; |
Cr_AC_code_length[105] <= 16; |
Cr_AC_code_length[106] <= 16; |
Cr_AC_code_length[107] <= 16; |
Cr_AC_code_length[108] <= 16; |
Cr_AC_code_length[109] <= 16; |
Cr_AC_code_length[110] <= 16; |
Cr_AC_code_length[111] <= 16; |
Cr_AC_code_length[112] <= 16; |
Cr_AC_code_length[113] <= 16; |
Cr_AC_code_length[114] <= 16; |
Cr_AC_code_length[115] <= 16; |
Cr_AC_code_length[116] <= 16; |
Cr_AC_code_length[117] <= 16; |
Cr_AC_code_length[118] <= 16; |
Cr_AC_code_length[119] <= 16; |
Cr_AC_code_length[120] <= 16; |
Cr_AC_code_length[121] <= 16; |
Cr_AC_code_length[122] <= 16; |
Cr_AC_code_length[123] <= 16; |
Cr_AC_code_length[124] <= 16; |
Cr_AC_code_length[125] <= 16; |
Cr_AC_code_length[126] <= 16; |
Cr_AC_code_length[127] <= 16; |
Cr_AC_code_length[128] <= 16; |
Cr_AC_code_length[129] <= 16; |
Cr_AC_code_length[130] <= 16; |
Cr_AC_code_length[131] <= 16; |
Cr_AC_code_length[132] <= 16; |
Cr_AC_code_length[133] <= 16; |
Cr_AC_code_length[134] <= 16; |
Cr_AC_code_length[135] <= 16; |
Cr_AC_code_length[136] <= 16; |
Cr_AC_code_length[137] <= 16; |
Cr_AC_code_length[138] <= 16; |
Cr_AC_code_length[139] <= 16; |
Cr_AC_code_length[140] <= 16; |
Cr_AC_code_length[141] <= 16; |
Cr_AC_code_length[142] <= 16; |
Cr_AC_code_length[143] <= 16; |
Cr_AC_code_length[144] <= 16; |
Cr_AC_code_length[145] <= 16; |
Cr_AC_code_length[146] <= 16; |
Cr_AC_code_length[147] <= 16; |
Cr_AC_code_length[148] <= 16; |
Cr_AC_code_length[149] <= 16; |
Cr_AC_code_length[150] <= 16; |
Cr_AC_code_length[151] <= 16; |
Cr_AC_code_length[152] <= 16; |
Cr_AC_code_length[153] <= 16; |
Cr_AC_code_length[154] <= 16; |
Cr_AC_code_length[155] <= 16; |
Cr_AC_code_length[156] <= 16; |
Cr_AC_code_length[157] <= 16; |
Cr_AC_code_length[158] <= 16; |
Cr_AC_code_length[159] <= 16; |
Cr_AC_code_length[160] <= 16; |
Cr_AC_code_length[161] <= 16; |
Cr_AC[0] <= 16'b0000000000000000; |
Cr_AC[1] <= 16'b0100000000000000; |
Cr_AC[2] <= 16'b1000000000000000; |
Cr_AC[3] <= 16'b1010000000000000; |
Cr_AC[4] <= 16'b1011000000000000; |
Cr_AC[5] <= 16'b1100000000000000; |
Cr_AC[6] <= 16'b1101000000000000; |
Cr_AC[7] <= 16'b1101100000000000; |
Cr_AC[8] <= 16'b1110000000000000; |
Cr_AC[9] <= 16'b1110100000000000; |
Cr_AC[10] <= 16'b1110110000000000; |
Cr_AC[11] <= 16'b1111000000000000; |
Cr_AC[12] <= 16'b1111001000000000; |
Cr_AC[13] <= 16'b1111010000000000; |
Cr_AC[14] <= 16'b1111011000000000; |
Cr_AC[15] <= 16'b1111100000000000; |
Cr_AC[16] <= 16'b1111100100000000; |
Cr_AC[17] <= 16'b1111101000000000; |
Cr_AC[18] <= 16'b1111101100000000; |
Cr_AC[19] <= 16'b1111101110000000; |
Cr_AC[20] <= 16'b1111110000000000; |
Cr_AC[21] <= 16'b1111110010000000; |
Cr_AC[22] <= 16'b1111110100000000; |
Cr_AC[23] <= 16'b1111110110000000; |
Cr_AC[24] <= 16'b1111110111000000; |
Cr_AC[25] <= 16'b1111111000000000; |
Cr_AC[26] <= 16'b1111111001000000; |
Cr_AC[27] <= 16'b1111111010000000; |
Cr_AC[28] <= 16'b1111111011000000; |
Cr_AC[29] <= 16'b1111111011100000; |
Cr_AC[30] <= 16'b1111111100000000; |
Cr_AC[31] <= 16'b1111111100100000; |
Cr_AC[32] <= 16'b1111111101000000; |
Cr_AC[33] <= 16'b1111111101010000; |
Cr_AC[34] <= 16'b1111111101100000; |
Cr_AC[35] <= 16'b1111111101110000; |
Cr_AC[36] <= 16'b1111111110000000; |
Cr_AC[37] <= 16'b1111111110000010; |
Cr_AC[38] <= 16'b1111111110000011; |
Cr_AC[39] <= 16'b1111111110000100; |
Cr_AC[40] <= 16'b1111111110000101; |
Cr_AC[41] <= 16'b1111111110000110; |
Cr_AC[42] <= 16'b1111111110000111; |
Cr_AC[43] <= 16'b1111111110001000; |
Cr_AC[44] <= 16'b1111111110001001; |
Cr_AC[45] <= 16'b1111111110001010; |
Cr_AC[46] <= 16'b1111111110001011; |
Cr_AC[47] <= 16'b1111111110001100; |
Cr_AC[48] <= 16'b1111111110001101; |
Cr_AC[49] <= 16'b1111111110001110; |
Cr_AC[50] <= 16'b1111111110001111; |
Cr_AC[51] <= 16'b1111111110010000; |
Cr_AC[52] <= 16'b1111111110010001; |
Cr_AC[53] <= 16'b1111111110010010; |
Cr_AC[54] <= 16'b1111111110010011; |
Cr_AC[55] <= 16'b1111111110010100; |
Cr_AC[56] <= 16'b1111111110010101; |
Cr_AC[57] <= 16'b1111111110010110; |
Cr_AC[58] <= 16'b1111111110010111; |
Cr_AC[59] <= 16'b1111111110011000; |
Cr_AC[60] <= 16'b1111111110011001; |
Cr_AC[61] <= 16'b1111111110011010; |
Cr_AC[62] <= 16'b1111111110011011; |
Cr_AC[63] <= 16'b1111111110011100; |
Cr_AC[64] <= 16'b1111111110011101; |
Cr_AC[65] <= 16'b1111111110011110; |
Cr_AC[66] <= 16'b1111111110011111; |
Cr_AC[67] <= 16'b1111111110100000; |
Cr_AC[68] <= 16'b1111111110100001; |
Cr_AC[69] <= 16'b1111111110100010; |
Cr_AC[70] <= 16'b1111111110100011; |
Cr_AC[71] <= 16'b1111111110100100; |
Cr_AC[72] <= 16'b1111111110100101; |
Cr_AC[73] <= 16'b1111111110100110; |
Cr_AC[74] <= 16'b1111111110100111; |
Cr_AC[75] <= 16'b1111111110101000; |
Cr_AC[76] <= 16'b1111111110101001; |
Cr_AC[77] <= 16'b1111111110101010; |
Cr_AC[78] <= 16'b1111111110101011; |
Cr_AC[79] <= 16'b1111111110101100; |
Cr_AC[80] <= 16'b1111111110101101; |
Cr_AC[81] <= 16'b1111111110101110; |
Cr_AC[82] <= 16'b1111111110101111; |
Cr_AC[83] <= 16'b1111111110110000; |
Cr_AC[84] <= 16'b1111111110110001; |
Cr_AC[85] <= 16'b1111111110110010; |
Cr_AC[86] <= 16'b1111111110110011; |
Cr_AC[87] <= 16'b1111111110110100; |
Cr_AC[88] <= 16'b1111111110110101; |
Cr_AC[89] <= 16'b1111111110110110; |
Cr_AC[90] <= 16'b1111111110110111; |
Cr_AC[91] <= 16'b1111111110111000; |
Cr_AC[92] <= 16'b1111111110111001; |
Cr_AC[93] <= 16'b1111111110111010; |
Cr_AC[94] <= 16'b1111111110111011; |
Cr_AC[95] <= 16'b1111111110111100; |
Cr_AC[96] <= 16'b1111111110111101; |
Cr_AC[97] <= 16'b1111111110111110; |
Cr_AC[98] <= 16'b1111111110111111; |
Cr_AC[99] <= 16'b1111111111000000; |
Cr_AC[100] <= 16'b1111111111000001; |
Cr_AC[101] <= 16'b1111111111000010; |
Cr_AC[102] <= 16'b1111111111000011; |
Cr_AC[103] <= 16'b1111111111000100; |
Cr_AC[104] <= 16'b1111111111000101; |
Cr_AC[105] <= 16'b1111111111000110; |
Cr_AC[106] <= 16'b1111111111000111; |
Cr_AC[107] <= 16'b1111111111001000; |
Cr_AC[108] <= 16'b1111111111001001; |
Cr_AC[109] <= 16'b1111111111001010; |
Cr_AC[110] <= 16'b1111111111001011; |
Cr_AC[111] <= 16'b1111111111001100; |
Cr_AC[112] <= 16'b1111111111001101; |
Cr_AC[113] <= 16'b1111111111001110; |
Cr_AC[114] <= 16'b1111111111001111; |
Cr_AC[115] <= 16'b1111111111010000; |
Cr_AC[116] <= 16'b1111111111010001; |
Cr_AC[117] <= 16'b1111111111010010; |
Cr_AC[118] <= 16'b1111111111010011; |
Cr_AC[119] <= 16'b1111111111010100; |
Cr_AC[120] <= 16'b1111111111010101; |
Cr_AC[121] <= 16'b1111111111010110; |
Cr_AC[122] <= 16'b1111111111010111; |
Cr_AC[123] <= 16'b1111111111011000; |
Cr_AC[124] <= 16'b1111111111011001; |
Cr_AC[125] <= 16'b1111111111011010; |
Cr_AC[126] <= 16'b1111111111011011; |
Cr_AC[127] <= 16'b1111111111011100; |
Cr_AC[128] <= 16'b1111111111011101; |
Cr_AC[129] <= 16'b1111111111011110; |
Cr_AC[130] <= 16'b1111111111011111; |
Cr_AC[131] <= 16'b1111111111100000; |
Cr_AC[132] <= 16'b1111111111100001; |
Cr_AC[133] <= 16'b1111111111100010; |
Cr_AC[134] <= 16'b1111111111100011; |
Cr_AC[135] <= 16'b1111111111100100; |
Cr_AC[136] <= 16'b1111111111100101; |
Cr_AC[137] <= 16'b1111111111100110; |
Cr_AC[138] <= 16'b1111111111100111; |
Cr_AC[139] <= 16'b1111111111101000; |
Cr_AC[140] <= 16'b1111111111101001; |
Cr_AC[141] <= 16'b1111111111101010; |
Cr_AC[142] <= 16'b1111111111101011; |
Cr_AC[143] <= 16'b1111111111101100; |
Cr_AC[144] <= 16'b1111111111101101; |
Cr_AC[145] <= 16'b1111111111101110; |
Cr_AC[146] <= 16'b1111111111101111; |
Cr_AC[147] <= 16'b1111111111110000; |
Cr_AC[148] <= 16'b1111111111110001; |
Cr_AC[149] <= 16'b1111111111110010; |
Cr_AC[150] <= 16'b1111111111110011; |
Cr_AC[151] <= 16'b1111111111110100; |
Cr_AC[152] <= 16'b1111111111110101; |
Cr_AC[153] <= 16'b1111111111110110; |
Cr_AC[154] <= 16'b1111111111110111; |
Cr_AC[155] <= 16'b1111111111111000; |
Cr_AC[156] <= 16'b1111111111111001; |
Cr_AC[157] <= 16'b1111111111111010; |
Cr_AC[158] <= 16'b1111111111111011; |
Cr_AC[159] <= 16'b1111111111111100; |
Cr_AC[160] <= 16'b1111111111111101; |
Cr_AC[161] <= 16'b1111111111111110; |
Cr_AC_run_code[1] <= 0; |
Cr_AC_run_code[2] <= 1; |
Cr_AC_run_code[3] <= 2; |
Cr_AC_run_code[0] <= 3; |
Cr_AC_run_code[4] <= 4; |
Cr_AC_run_code[17] <= 5; |
Cr_AC_run_code[5] <= 6; |
Cr_AC_run_code[18] <= 7; |
Cr_AC_run_code[33] <= 8; |
Cr_AC_run_code[49] <= 9; |
Cr_AC_run_code[65] <= 10; |
Cr_AC_run_code[6] <= 11; |
Cr_AC_run_code[19] <= 12; |
Cr_AC_run_code[81] <= 13; |
Cr_AC_run_code[97] <= 14; |
Cr_AC_run_code[7] <= 15; |
Cr_AC_run_code[34] <= 16; |
Cr_AC_run_code[113] <= 17; |
Cr_AC_run_code[20] <= 18; |
Cr_AC_run_code[50] <= 19; |
Cr_AC_run_code[129] <= 20; |
Cr_AC_run_code[145] <= 21; |
Cr_AC_run_code[161] <= 22; |
Cr_AC_run_code[8] <= 23; |
Cr_AC_run_code[35] <= 24; |
Cr_AC_run_code[66] <= 25; |
Cr_AC_run_code[177] <= 26; |
Cr_AC_run_code[193] <= 27; |
Cr_AC_run_code[21] <= 28; |
Cr_AC_run_code[82] <= 29; |
Cr_AC_run_code[209] <= 30; |
Cr_AC_run_code[240] <= 31; |
Cr_AC_run_code[36] <= 32; |
Cr_AC_run_code[51] <= 33; |
Cr_AC_run_code[98] <= 34; |
Cr_AC_run_code[114] <= 35; |
Cr_AC_run_code[130] <= 36; |
Cr_AC_run_code[9] <= 37; |
Cr_AC_run_code[10] <= 38; |
Cr_AC_run_code[22] <= 39; |
Cr_AC_run_code[23] <= 40; |
Cr_AC_run_code[24] <= 41; |
Cr_AC_run_code[25] <= 42; |
Cr_AC_run_code[26] <= 43; |
Cr_AC_run_code[37] <= 44; |
Cr_AC_run_code[38] <= 45; |
Cr_AC_run_code[39] <= 46; |
Cr_AC_run_code[40] <= 47; |
Cr_AC_run_code[41] <= 48; |
Cr_AC_run_code[42] <= 49; |
Cr_AC_run_code[52] <= 50; |
Cr_AC_run_code[53] <= 51; |
Cr_AC_run_code[54] <= 52; |
Cr_AC_run_code[55] <= 53; |
Cr_AC_run_code[56] <= 54; |
Cr_AC_run_code[57] <= 55; |
Cr_AC_run_code[58] <= 56; |
Cr_AC_run_code[67] <= 57; |
Cr_AC_run_code[68] <= 58; |
Cr_AC_run_code[69] <= 59; |
Cr_AC_run_code[70] <= 60; |
Cr_AC_run_code[71] <= 61; |
Cr_AC_run_code[72] <= 62; |
Cr_AC_run_code[73] <= 63; |
Cr_AC_run_code[74] <= 64; |
Cr_AC_run_code[83] <= 65; |
Cr_AC_run_code[84] <= 66; |
Cr_AC_run_code[85] <= 67; |
Cr_AC_run_code[86] <= 68; |
Cr_AC_run_code[87] <= 69; |
Cr_AC_run_code[88] <= 70; |
Cr_AC_run_code[89] <= 71; |
Cr_AC_run_code[90] <= 72; |
Cr_AC_run_code[99] <= 73; |
Cr_AC_run_code[100] <= 74; |
Cr_AC_run_code[101] <= 75; |
Cr_AC_run_code[102] <= 76; |
Cr_AC_run_code[103] <= 77; |
Cr_AC_run_code[104] <= 78; |
Cr_AC_run_code[105] <= 79; |
Cr_AC_run_code[106] <= 80; |
Cr_AC_run_code[115] <= 81; |
Cr_AC_run_code[116] <= 82; |
Cr_AC_run_code[117] <= 83; |
Cr_AC_run_code[118] <= 84; |
Cr_AC_run_code[119] <= 85; |
Cr_AC_run_code[120] <= 86; |
Cr_AC_run_code[121] <= 87; |
Cr_AC_run_code[122] <= 88; |
Cr_AC_run_code[131] <= 89; |
Cr_AC_run_code[132] <= 90; |
Cr_AC_run_code[133] <= 91; |
Cr_AC_run_code[134] <= 92; |
Cr_AC_run_code[135] <= 93; |
Cr_AC_run_code[136] <= 94; |
Cr_AC_run_code[137] <= 95; |
Cr_AC_run_code[138] <= 96; |
Cr_AC_run_code[146] <= 97; |
Cr_AC_run_code[147] <= 98; |
Cr_AC_run_code[148] <= 99; |
Cr_AC_run_code[149] <= 100; |
Cr_AC_run_code[150] <= 101; |
Cr_AC_run_code[151] <= 102; |
Cr_AC_run_code[152] <= 103; |
Cr_AC_run_code[153] <= 104; |
Cr_AC_run_code[154] <= 105; |
Cr_AC_run_code[162] <= 106; |
Cr_AC_run_code[163] <= 107; |
Cr_AC_run_code[164] <= 108; |
Cr_AC_run_code[165] <= 109; |
Cr_AC_run_code[166] <= 110; |
Cr_AC_run_code[167] <= 111; |
Cr_AC_run_code[168] <= 112; |
Cr_AC_run_code[169] <= 113; |
Cr_AC_run_code[170] <= 114; |
Cr_AC_run_code[178] <= 115; |
Cr_AC_run_code[179] <= 116; |
Cr_AC_run_code[180] <= 117; |
Cr_AC_run_code[181] <= 118; |
Cr_AC_run_code[182] <= 119; |
Cr_AC_run_code[183] <= 120; |
Cr_AC_run_code[184] <= 121; |
Cr_AC_run_code[185] <= 122; |
Cr_AC_run_code[186] <= 123; |
Cr_AC_run_code[194] <= 124; |
Cr_AC_run_code[195] <= 125; |
Cr_AC_run_code[196] <= 126; |
Cr_AC_run_code[197] <= 127; |
Cr_AC_run_code[198] <= 128; |
Cr_AC_run_code[199] <= 129; |
Cr_AC_run_code[200] <= 130; |
Cr_AC_run_code[201] <= 131; |
Cr_AC_run_code[202] <= 132; |
Cr_AC_run_code[210] <= 133; |
Cr_AC_run_code[211] <= 134; |
Cr_AC_run_code[212] <= 135; |
Cr_AC_run_code[213] <= 136; |
Cr_AC_run_code[214] <= 137; |
Cr_AC_run_code[215] <= 138; |
Cr_AC_run_code[216] <= 139; |
Cr_AC_run_code[217] <= 140; |
Cr_AC_run_code[218] <= 141; |
Cr_AC_run_code[225] <= 142; |
Cr_AC_run_code[226] <= 143; |
Cr_AC_run_code[227] <= 144; |
Cr_AC_run_code[228] <= 145; |
Cr_AC_run_code[229] <= 146; |
Cr_AC_run_code[230] <= 147; |
Cr_AC_run_code[231] <= 148; |
Cr_AC_run_code[232] <= 149; |
Cr_AC_run_code[233] <= 150; |
Cr_AC_run_code[234] <= 151; |
Cr_AC_run_code[241] <= 152; |
Cr_AC_run_code[242] <= 153; |
Cr_AC_run_code[243] <= 154; |
Cr_AC_run_code[244] <= 155; |
Cr_AC_run_code[245] <= 156; |
Cr_AC_run_code[246] <= 157; |
Cr_AC_run_code[247] <= 158; |
Cr_AC_run_code[248] <= 159; |
Cr_AC_run_code[249] <= 160; |
Cr_AC_run_code[250] <= 161; |
Cr_AC_run_code[16] <= 0; |
Cr_AC_run_code[32] <= 0; |
Cr_AC_run_code[48] <= 0; |
Cr_AC_run_code[64] <= 0; |
Cr_AC_run_code[80] <= 0; |
Cr_AC_run_code[96] <= 0; |
Cr_AC_run_code[112] <= 0; |
Cr_AC_run_code[128] <= 0; |
Cr_AC_run_code[144] <= 0; |
Cr_AC_run_code[160] <= 0; |
Cr_AC_run_code[176] <= 0; |
Cr_AC_run_code[192] <= 0; |
Cr_AC_run_code[208] <= 0; |
Cr_AC_run_code[224] <= 0; |
end |
|
|
|
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[31] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[31] <= JPEG_bs_5[31]; |
else if (enable_module && orc_8 == 0) |
JPEG_bitstream[31] <= JPEG_bs_5[31]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[30] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[30] <= JPEG_bs_5[30]; |
else if (enable_module && orc_8 <= 1) |
JPEG_bitstream[30] <= JPEG_bs_5[30]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[29] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[29] <= JPEG_bs_5[29]; |
else if (enable_module && orc_8 <= 2) |
JPEG_bitstream[29] <= JPEG_bs_5[29]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[28] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[28] <= JPEG_bs_5[28]; |
else if (enable_module && orc_8 <= 3) |
JPEG_bitstream[28] <= JPEG_bs_5[28]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[27] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[27] <= JPEG_bs_5[27]; |
else if (enable_module && orc_8 <= 4) |
JPEG_bitstream[27] <= JPEG_bs_5[27]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[26] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[26] <= JPEG_bs_5[26]; |
else if (enable_module && orc_8 <= 5) |
JPEG_bitstream[26] <= JPEG_bs_5[26]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[25] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[25] <= JPEG_bs_5[25]; |
else if (enable_module && orc_8 <= 6) |
JPEG_bitstream[25] <= JPEG_bs_5[25]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[24] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[24] <= JPEG_bs_5[24]; |
else if (enable_module && orc_8 <= 7) |
JPEG_bitstream[24] <= JPEG_bs_5[24]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[23] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[23] <= JPEG_bs_5[23]; |
else if (enable_module && orc_8 <= 8) |
JPEG_bitstream[23] <= JPEG_bs_5[23]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[22] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[22] <= JPEG_bs_5[22]; |
else if (enable_module && orc_8 <= 9) |
JPEG_bitstream[22] <= JPEG_bs_5[22]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[21] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[21] <= JPEG_bs_5[21]; |
else if (enable_module && orc_8 <= 10) |
JPEG_bitstream[21] <= JPEG_bs_5[21]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[20] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[20] <= JPEG_bs_5[20]; |
else if (enable_module && orc_8 <= 11) |
JPEG_bitstream[20] <= JPEG_bs_5[20]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[19] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[19] <= JPEG_bs_5[19]; |
else if (enable_module && orc_8 <= 12) |
JPEG_bitstream[19] <= JPEG_bs_5[19]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[18] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[18] <= JPEG_bs_5[18]; |
else if (enable_module && orc_8 <= 13) |
JPEG_bitstream[18] <= JPEG_bs_5[18]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[17] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[17] <= JPEG_bs_5[17]; |
else if (enable_module && orc_8 <= 14) |
JPEG_bitstream[17] <= JPEG_bs_5[17]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[16] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[16] <= JPEG_bs_5[16]; |
else if (enable_module && orc_8 <= 15) |
JPEG_bitstream[16] <= JPEG_bs_5[16]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[15] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[15] <= JPEG_bs_5[15]; |
else if (enable_module && orc_8 <= 16) |
JPEG_bitstream[15] <= JPEG_bs_5[15]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[14] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[14] <= JPEG_bs_5[14]; |
else if (enable_module && orc_8 <= 17) |
JPEG_bitstream[14] <= JPEG_bs_5[14]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[13] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[13] <= JPEG_bs_5[13]; |
else if (enable_module && orc_8 <= 18) |
JPEG_bitstream[13] <= JPEG_bs_5[13]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[12] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[12] <= JPEG_bs_5[12]; |
else if (enable_module && orc_8 <= 19) |
JPEG_bitstream[12] <= JPEG_bs_5[12]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[11] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[11] <= JPEG_bs_5[11]; |
else if (enable_module && orc_8 <= 20) |
JPEG_bitstream[11] <= JPEG_bs_5[11]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[10] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[10] <= JPEG_bs_5[10]; |
else if (enable_module && orc_8 <= 21) |
JPEG_bitstream[10] <= JPEG_bs_5[10]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[9] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[9] <= JPEG_bs_5[9]; |
else if (enable_module && orc_8 <= 22) |
JPEG_bitstream[9] <= JPEG_bs_5[9]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[8] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[8] <= JPEG_bs_5[8]; |
else if (enable_module && orc_8 <= 23) |
JPEG_bitstream[8] <= JPEG_bs_5[8]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[7] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[7] <= JPEG_bs_5[7]; |
else if (enable_module && orc_8 <= 24) |
JPEG_bitstream[7] <= JPEG_bs_5[7]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[6] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[6] <= JPEG_bs_5[6]; |
else if (enable_module && orc_8 <= 25) |
JPEG_bitstream[6] <= JPEG_bs_5[6]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[5] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[5] <= JPEG_bs_5[5]; |
else if (enable_module && orc_8 <= 26) |
JPEG_bitstream[5] <= JPEG_bs_5[5]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[4] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[4] <= JPEG_bs_5[4]; |
else if (enable_module && orc_8 <= 27) |
JPEG_bitstream[4] <= JPEG_bs_5[4]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[3] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[3] <= JPEG_bs_5[3]; |
else if (enable_module && orc_8 <= 28) |
JPEG_bitstream[3] <= JPEG_bs_5[3]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[2] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[2] <= JPEG_bs_5[2]; |
else if (enable_module && orc_8 <= 29) |
JPEG_bitstream[2] <= JPEG_bs_5[2]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[1] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[1] <= JPEG_bs_5[1]; |
else if (enable_module && orc_8 <= 30) |
JPEG_bitstream[1] <= JPEG_bs_5[1]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[0] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[0] <= JPEG_bs_5[0]; |
else if (enable_module && orc_8 <= 31) |
JPEG_bitstream[0] <= JPEG_bs_5[0]; |
end |
endmodule |
/jpegencode/trunk/cb_dct.v
0,0 → 1,846
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module converts the incoming Cb data. |
The incoming data is unsigned 8 bits, so the data is in the range of 0-255 |
Unlike a typical DCT, the data is not subtracted by 128 to center it around 0. |
It is only required for the first row, and instead of subtracting 128 from each |
pixel value, a total value can be subtracted at the end of the first row/column multiply, |
involving the 8 pixel values and the 8 DCT matrix values. |
For the other 7 rows of the DCT matrix, the values in each row add up to 0, |
so it is not necessary to subtract 128 from each Y, Cb, and Cr pixel value. |
Then the Discrete Cosine Transform is performed by multiplying the 8x8 pixel block values |
by the 8x8 DCT matrix. */ |
|
|
`timescale 1ns / 100ps |
|
module cb_dct(clk, rst, enable, data_in, |
Z11_final, Z12_final, Z13_final, Z14_final, Z15_final, Z16_final, Z17_final, Z18_final, |
Z21_final, Z22_final, Z23_final, Z24_final, Z25_final, Z26_final, Z27_final, Z28_final, |
Z31_final, Z32_final, Z33_final, Z34_final, Z35_final, Z36_final, Z37_final, Z38_final, |
Z41_final, Z42_final, Z43_final, Z44_final, Z45_final, Z46_final, Z47_final, Z48_final, |
Z51_final, Z52_final, Z53_final, Z54_final, Z55_final, Z56_final, Z57_final, Z58_final, |
Z61_final, Z62_final, Z63_final, Z64_final, Z65_final, Z66_final, Z67_final, Z68_final, |
Z71_final, Z72_final, Z73_final, Z74_final, Z75_final, Z76_final, Z77_final, Z78_final, |
Z81_final, Z82_final, Z83_final, Z84_final, Z85_final, Z86_final, Z87_final, Z88_final, |
output_enable); |
input clk; |
input rst; |
input enable; |
input [7:0] data_in; |
output [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
output [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
output [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
output [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
output [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
output [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
output [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
output [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
output [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
output [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
output [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
output [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
output [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
output [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
output [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
output [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
output output_enable; |
|
|
integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52; |
integer Ti1, Ti21, Ti22, Ti23, Ti24, Ti25, Ti26, Ti27, Ti28, Ti31, Ti32, Ti33, Ti34, Ti52; |
|
reg [24:0] Cb_temp_11; |
reg [24:0] Cb11, Cb21, Cb31, Cb41, Cb51, Cb61, Cb71, Cb81, Cb11_final; |
reg [31:0] Cb_temp_21, Cb_temp_31, Cb_temp_41, Cb_temp_51; |
reg [31:0] Cb_temp_61, Cb_temp_71, Cb_temp_81; |
reg [31:0] Z_temp_11, Z_temp_12, Z_temp_13, Z_temp_14; |
reg [31:0] Z_temp_15, Z_temp_16, Z_temp_17, Z_temp_18; |
reg [31:0] Z_temp_21, Z_temp_22, Z_temp_23, Z_temp_24; |
reg [31:0] Z_temp_25, Z_temp_26, Z_temp_27, Z_temp_28; |
reg [31:0] Z_temp_31, Z_temp_32, Z_temp_33, Z_temp_34; |
reg [31:0] Z_temp_35, Z_temp_36, Z_temp_37, Z_temp_38; |
reg [31:0] Z_temp_41, Z_temp_42, Z_temp_43, Z_temp_44; |
reg [31:0] Z_temp_45, Z_temp_46, Z_temp_47, Z_temp_48; |
reg [31:0] Z_temp_51, Z_temp_52, Z_temp_53, Z_temp_54; |
reg [31:0] Z_temp_55, Z_temp_56, Z_temp_57, Z_temp_58; |
reg [31:0] Z_temp_61, Z_temp_62, Z_temp_63, Z_temp_64; |
reg [31:0] Z_temp_65, Z_temp_66, Z_temp_67, Z_temp_68; |
reg [31:0] Z_temp_71, Z_temp_72, Z_temp_73, Z_temp_74; |
reg [31:0] Z_temp_75, Z_temp_76, Z_temp_77, Z_temp_78; |
reg [31:0] Z_temp_81, Z_temp_82, Z_temp_83, Z_temp_84; |
reg [31:0] Z_temp_85, Z_temp_86, Z_temp_87, Z_temp_88; |
reg [24:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18; |
reg [24:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28; |
reg [24:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38; |
reg [24:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48; |
reg [24:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58; |
reg [24:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68; |
reg [24:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78; |
reg [24:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88; |
reg [31:0] Cb11_final_2, Cb21_final_2, Cb11_final_3, Cb11_final_4, Cb31_final_2, Cb41_final_2; |
reg [31:0] Cb51_final_2, Cb61_final_2, Cb71_final_2, Cb81_final_2; |
reg [10:0] Cb11_final_1, Cb21_final_1, Cb31_final_1, Cb41_final_1; |
reg [10:0] Cb51_final_1, Cb61_final_1, Cb71_final_1, Cb81_final_1; |
reg [24:0] Cb21_final, Cb31_final, Cb41_final, Cb51_final; |
reg [24:0] Cb61_final, Cb71_final, Cb81_final; |
reg [24:0] Cb21_final_prev, Cb21_final_diff; |
reg [24:0] Cb31_final_prev, Cb31_final_diff; |
reg [24:0] Cb41_final_prev, Cb41_final_diff; |
reg [24:0] Cb51_final_prev, Cb51_final_diff; |
reg [24:0] Cb61_final_prev, Cb61_final_diff; |
reg [24:0] Cb71_final_prev, Cb71_final_diff; |
reg [24:0] Cb81_final_prev, Cb81_final_diff; |
reg [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
reg [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
reg [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
reg [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
reg [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
reg [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
reg [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
reg [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
reg [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
reg [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
reg [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
reg [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
reg [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
reg [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
reg [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
reg [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
reg [2:0] count; |
reg [2:0] count_of, count_of_copy; |
reg count_1, count_3, count_4, count_5, count_6, count_7, count_8, enable_1, output_enable; |
reg count_9, count_10; |
reg [7:0] data_1; |
integer Cb2_mul_input, Cb3_mul_input, Cb4_mul_input, Cb5_mul_input; |
integer Cb6_mul_input, Cb7_mul_input, Cb8_mul_input; |
integer Ti2_mul_input, Ti3_mul_input, Ti4_mul_input, Ti5_mul_input; |
integer Ti6_mul_input, Ti7_mul_input, Ti8_mul_input; |
|
always @(posedge clk) |
begin // DCT matrix entries |
T1 = 5793; // .3536 |
T21 = 8035; // .4904 |
T22 = 6811; // .4157 |
T23 = 4551; // .2778 |
T24 = 1598; // .0975 |
T25 = -1598; // -.0975 |
T26 = -4551; // -.2778 |
T27 = -6811; // -.4157 |
T28 = -8035; // -.4904 |
T31 = 7568; // .4619 |
T32 = 3135; // .1913 |
T33 = -3135; // -.1913 |
T34 = -7568; // -.4619 |
T52 = -5793; // -.3536 |
end |
|
always @(posedge clk) |
begin // The inverse DCT matrix entries |
Ti1 = 5793; // .3536 |
Ti21 = 8035; // .4904 |
Ti22 = 6811; // .4157 |
Ti23 = 4551; // .2778 |
Ti24 = 1598; // .0975 |
Ti25 = -1598; // -.0975 |
Ti26 = -4551; // -.2778 |
Ti27 = -6811; // -.4157 |
Ti28 = -8035; // -.4904 |
Ti31 = 7568; // .4619 |
Ti32 = 3135; // .1913 |
Ti33 = -3135; // -.1913 |
Ti34 = -7568; // -.4619 |
Ti52 = -5793; // -.3536 |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0; |
Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0; |
Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0; |
Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0; |
Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0; |
Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0; |
Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0; |
Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0; |
Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0; |
Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0; |
Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0; |
Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0; |
Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0; |
Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0; |
Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0; |
Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0; |
end |
else if (enable_1 & count_8) begin |
Z_temp_11 <= Cb11_final_4 * Ti1; Z_temp_12 <= Cb11_final_4 * Ti2_mul_input; |
Z_temp_13 <= Cb11_final_4 * Ti3_mul_input; Z_temp_14 <= Cb11_final_4 * Ti4_mul_input; |
Z_temp_15 <= Cb11_final_4 * Ti5_mul_input; Z_temp_16 <= Cb11_final_4 * Ti6_mul_input; |
Z_temp_17 <= Cb11_final_4 * Ti7_mul_input; Z_temp_18 <= Cb11_final_4 * Ti8_mul_input; |
Z_temp_21 <= Cb21_final_2 * Ti1; Z_temp_22 <= Cb21_final_2 * Ti2_mul_input; |
Z_temp_23 <= Cb21_final_2 * Ti3_mul_input; Z_temp_24 <= Cb21_final_2 * Ti4_mul_input; |
Z_temp_25 <= Cb21_final_2 * Ti5_mul_input; Z_temp_26 <= Cb21_final_2 * Ti6_mul_input; |
Z_temp_27 <= Cb21_final_2 * Ti7_mul_input; Z_temp_28 <= Cb21_final_2 * Ti8_mul_input; |
Z_temp_31 <= Cb31_final_2 * Ti1; Z_temp_32 <= Cb31_final_2 * Ti2_mul_input; |
Z_temp_33 <= Cb31_final_2 * Ti3_mul_input; Z_temp_34 <= Cb31_final_2 * Ti4_mul_input; |
Z_temp_35 <= Cb31_final_2 * Ti5_mul_input; Z_temp_36 <= Cb31_final_2 * Ti6_mul_input; |
Z_temp_37 <= Cb31_final_2 * Ti7_mul_input; Z_temp_38 <= Cb31_final_2 * Ti8_mul_input; |
Z_temp_41 <= Cb41_final_2 * Ti1; Z_temp_42 <= Cb41_final_2 * Ti2_mul_input; |
Z_temp_43 <= Cb41_final_2 * Ti3_mul_input; Z_temp_44 <= Cb41_final_2 * Ti4_mul_input; |
Z_temp_45 <= Cb41_final_2 * Ti5_mul_input; Z_temp_46 <= Cb41_final_2 * Ti6_mul_input; |
Z_temp_47 <= Cb41_final_2 * Ti7_mul_input; Z_temp_48 <= Cb41_final_2 * Ti8_mul_input; |
Z_temp_51 <= Cb51_final_2 * Ti1; Z_temp_52 <= Cb51_final_2 * Ti2_mul_input; |
Z_temp_53 <= Cb51_final_2 * Ti3_mul_input; Z_temp_54 <= Cb51_final_2 * Ti4_mul_input; |
Z_temp_55 <= Cb51_final_2 * Ti5_mul_input; Z_temp_56 <= Cb51_final_2 * Ti6_mul_input; |
Z_temp_57 <= Cb51_final_2 * Ti7_mul_input; Z_temp_58 <= Cb51_final_2 * Ti8_mul_input; |
Z_temp_61 <= Cb61_final_2 * Ti1; Z_temp_62 <= Cb61_final_2 * Ti2_mul_input; |
Z_temp_63 <= Cb61_final_2 * Ti3_mul_input; Z_temp_64 <= Cb61_final_2 * Ti4_mul_input; |
Z_temp_65 <= Cb61_final_2 * Ti5_mul_input; Z_temp_66 <= Cb61_final_2 * Ti6_mul_input; |
Z_temp_67 <= Cb61_final_2 * Ti7_mul_input; Z_temp_68 <= Cb61_final_2 * Ti8_mul_input; |
Z_temp_71 <= Cb71_final_2 * Ti1; Z_temp_72 <= Cb71_final_2 * Ti2_mul_input; |
Z_temp_73 <= Cb71_final_2 * Ti3_mul_input; Z_temp_74 <= Cb71_final_2 * Ti4_mul_input; |
Z_temp_75 <= Cb71_final_2 * Ti5_mul_input; Z_temp_76 <= Cb71_final_2 * Ti6_mul_input; |
Z_temp_77 <= Cb71_final_2 * Ti7_mul_input; Z_temp_78 <= Cb71_final_2 * Ti8_mul_input; |
Z_temp_81 <= Cb81_final_2 * Ti1; Z_temp_82 <= Cb81_final_2 * Ti2_mul_input; |
Z_temp_83 <= Cb81_final_2 * Ti3_mul_input; Z_temp_84 <= Cb81_final_2 * Ti4_mul_input; |
Z_temp_85 <= Cb81_final_2 * Ti5_mul_input; Z_temp_86 <= Cb81_final_2 * Ti6_mul_input; |
Z_temp_87 <= Cb81_final_2 * Ti7_mul_input; Z_temp_88 <= Cb81_final_2 * Ti8_mul_input; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; |
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; |
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; |
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; |
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; |
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; |
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; |
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; |
end |
else if (count_8 & count_of == 1) begin |
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; |
Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; |
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; |
Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; |
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; |
Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; |
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; |
Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; |
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; |
Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; |
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; |
Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; |
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; |
Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; |
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; |
Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; |
end |
else if (enable & count_9) begin |
Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14; |
Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18; |
Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24; |
Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28; |
Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34; |
Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38; |
Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44; |
Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48; |
Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54; |
Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58; |
Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64; |
Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68; |
Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74; |
Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78; |
Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84; |
Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0; |
Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0; |
Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0; |
Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0; |
Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0; |
Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0; |
Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0; |
Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0; |
Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0; |
Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0; |
Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0; |
Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0; |
Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0; |
Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0; |
Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0; |
Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0; |
end |
else if (count_10 & count_of == 0) begin |
Z11_final <= Z11[13] ? Z11[24:14] + 1 : Z11[24:14]; |
Z12_final <= Z12[13] ? Z12[24:14] + 1 : Z12[24:14]; |
Z13_final <= Z13[13] ? Z13[24:14] + 1 : Z13[24:14]; |
Z14_final <= Z14[13] ? Z14[24:14] + 1 : Z14[24:14]; |
Z15_final <= Z15[13] ? Z15[24:14] + 1 : Z15[24:14]; |
Z16_final <= Z16[13] ? Z16[24:14] + 1 : Z16[24:14]; |
Z17_final <= Z17[13] ? Z17[24:14] + 1 : Z17[24:14]; |
Z18_final <= Z18[13] ? Z18[24:14] + 1 : Z18[24:14]; |
Z21_final <= Z21[13] ? Z21[24:14] + 1 : Z21[24:14]; |
Z22_final <= Z22[13] ? Z22[24:14] + 1 : Z22[24:14]; |
Z23_final <= Z23[13] ? Z23[24:14] + 1 : Z23[24:14]; |
Z24_final <= Z24[13] ? Z24[24:14] + 1 : Z24[24:14]; |
Z25_final <= Z25[13] ? Z25[24:14] + 1 : Z25[24:14]; |
Z26_final <= Z26[13] ? Z26[24:14] + 1 : Z26[24:14]; |
Z27_final <= Z27[13] ? Z27[24:14] + 1 : Z27[24:14]; |
Z28_final <= Z28[13] ? Z28[24:14] + 1 : Z28[24:14]; |
Z31_final <= Z31[13] ? Z31[24:14] + 1 : Z31[24:14]; |
Z32_final <= Z32[13] ? Z32[24:14] + 1 : Z32[24:14]; |
Z33_final <= Z33[13] ? Z33[24:14] + 1 : Z33[24:14]; |
Z34_final <= Z34[13] ? Z34[24:14] + 1 : Z34[24:14]; |
Z35_final <= Z35[13] ? Z35[24:14] + 1 : Z35[24:14]; |
Z36_final <= Z36[13] ? Z36[24:14] + 1 : Z36[24:14]; |
Z37_final <= Z37[13] ? Z37[24:14] + 1 : Z37[24:14]; |
Z38_final <= Z38[13] ? Z38[24:14] + 1 : Z38[24:14]; |
Z41_final <= Z41[13] ? Z41[24:14] + 1 : Z41[24:14]; |
Z42_final <= Z42[13] ? Z42[24:14] + 1 : Z42[24:14]; |
Z43_final <= Z43[13] ? Z43[24:14] + 1 : Z43[24:14]; |
Z44_final <= Z44[13] ? Z44[24:14] + 1 : Z44[24:14]; |
Z45_final <= Z45[13] ? Z45[24:14] + 1 : Z45[24:14]; |
Z46_final <= Z46[13] ? Z46[24:14] + 1 : Z46[24:14]; |
Z47_final <= Z47[13] ? Z47[24:14] + 1 : Z47[24:14]; |
Z48_final <= Z48[13] ? Z48[24:14] + 1 : Z48[24:14]; |
Z51_final <= Z51[13] ? Z51[24:14] + 1 : Z51[24:14]; |
Z52_final <= Z52[13] ? Z52[24:14] + 1 : Z52[24:14]; |
Z53_final <= Z53[13] ? Z53[24:14] + 1 : Z53[24:14]; |
Z54_final <= Z54[13] ? Z54[24:14] + 1 : Z54[24:14]; |
Z55_final <= Z55[13] ? Z55[24:14] + 1 : Z55[24:14]; |
Z56_final <= Z56[13] ? Z56[24:14] + 1 : Z56[24:14]; |
Z57_final <= Z57[13] ? Z57[24:14] + 1 : Z57[24:14]; |
Z58_final <= Z58[13] ? Z58[24:14] + 1 : Z58[24:14]; |
Z61_final <= Z61[13] ? Z61[24:14] + 1 : Z61[24:14]; |
Z62_final <= Z62[13] ? Z62[24:14] + 1 : Z62[24:14]; |
Z63_final <= Z63[13] ? Z63[24:14] + 1 : Z63[24:14]; |
Z64_final <= Z64[13] ? Z64[24:14] + 1 : Z64[24:14]; |
Z65_final <= Z65[13] ? Z65[24:14] + 1 : Z65[24:14]; |
Z66_final <= Z66[13] ? Z66[24:14] + 1 : Z66[24:14]; |
Z67_final <= Z67[13] ? Z67[24:14] + 1 : Z67[24:14]; |
Z68_final <= Z68[13] ? Z68[24:14] + 1 : Z68[24:14]; |
Z71_final <= Z71[13] ? Z71[24:14] + 1 : Z71[24:14]; |
Z72_final <= Z72[13] ? Z72[24:14] + 1 : Z72[24:14]; |
Z73_final <= Z73[13] ? Z73[24:14] + 1 : Z73[24:14]; |
Z74_final <= Z74[13] ? Z74[24:14] + 1 : Z74[24:14]; |
Z75_final <= Z75[13] ? Z75[24:14] + 1 : Z75[24:14]; |
Z76_final <= Z76[13] ? Z76[24:14] + 1 : Z76[24:14]; |
Z77_final <= Z77[13] ? Z77[24:14] + 1 : Z77[24:14]; |
Z78_final <= Z78[13] ? Z78[24:14] + 1 : Z78[24:14]; |
Z81_final <= Z81[13] ? Z81[24:14] + 1 : Z81[24:14]; |
Z82_final <= Z82[13] ? Z82[24:14] + 1 : Z82[24:14]; |
Z83_final <= Z83[13] ? Z83[24:14] + 1 : Z83[24:14]; |
Z84_final <= Z84[13] ? Z84[24:14] + 1 : Z84[24:14]; |
Z85_final <= Z85[13] ? Z85[24:14] + 1 : Z85[24:14]; |
Z86_final <= Z86[13] ? Z86[24:14] + 1 : Z86[24:14]; |
Z87_final <= Z87[13] ? Z87[24:14] + 1 : Z87[24:14]; |
Z88_final <= Z88[13] ? Z88[24:14] + 1 : Z88[24:14]; |
end |
end |
|
// output_enable signals the next block, the quantizer, that the input data is ready |
always @(posedge clk) |
begin |
if (rst) |
output_enable <= 0; |
else if (!enable_1) |
output_enable <= 0; |
else if (count_10 == 0 | count_of) |
output_enable <= 0; |
else if (count_10 & count_of == 0) |
output_enable <= 1; |
end |
always @(posedge clk) |
begin |
if (rst) |
Cb_temp_11 <= 0; |
else if (enable) |
Cb_temp_11 <= data_in * T1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cb11 <= 0; |
else if (count == 1 & enable == 1) |
Cb11 <= Cb_temp_11; |
else if (enable) |
Cb11 <= Cb_temp_11 + Cb11; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb_temp_21 <= 0; |
Cb_temp_31 <= 0; |
Cb_temp_41 <= 0; |
Cb_temp_51 <= 0; |
Cb_temp_61 <= 0; |
Cb_temp_71 <= 0; |
Cb_temp_81 <= 0; |
end |
else if (!enable_1) begin |
Cb_temp_21 <= 0; |
Cb_temp_31 <= 0; |
Cb_temp_41 <= 0; |
Cb_temp_51 <= 0; |
Cb_temp_61 <= 0; |
Cb_temp_71 <= 0; |
Cb_temp_81 <= 0; |
end |
else if (enable_1) begin |
Cb_temp_21 <= data_1 * Cb2_mul_input; |
Cb_temp_31 <= data_1 * Cb3_mul_input; |
Cb_temp_41 <= data_1 * Cb4_mul_input; |
Cb_temp_51 <= data_1 * Cb5_mul_input; |
Cb_temp_61 <= data_1 * Cb6_mul_input; |
Cb_temp_71 <= data_1 * Cb7_mul_input; |
Cb_temp_81 <= data_1 * Cb8_mul_input; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb21 <= 0; |
Cb31 <= 0; |
Cb41 <= 0; |
Cb51 <= 0; |
Cb61 <= 0; |
Cb71 <= 0; |
Cb81 <= 0; |
end |
else if (!enable_1) begin |
Cb21 <= 0; |
Cb31 <= 0; |
Cb41 <= 0; |
Cb51 <= 0; |
Cb61 <= 0; |
Cb71 <= 0; |
Cb81 <= 0; |
end |
else if (enable_1) begin |
Cb21 <= Cb_temp_21 + Cb21; |
Cb31 <= Cb_temp_31 + Cb31; |
Cb41 <= Cb_temp_41 + Cb41; |
Cb51 <= Cb_temp_51 + Cb51; |
Cb61 <= Cb_temp_61 + Cb61; |
Cb71 <= Cb_temp_71 + Cb71; |
Cb81 <= Cb_temp_81 + Cb81; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; |
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; |
count_10 <= 0; |
end |
else if (!enable) begin |
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; |
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; |
count_10 <= 0; |
end |
else if (enable) begin |
count <= count + 1; count_3 <= count_1; count_4 <= count_3; |
count_5 <= count_4; count_6 <= count_5; count_7 <= count_6; |
count_8 <= count_7; count_9 <= count_8; count_10 <= count_9; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count_1 <= 0; |
end |
else if (count != 7 | !enable) begin |
count_1 <= 0; |
end |
else if (count == 7) begin |
count_1 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count_of <= 0; |
count_of_copy <= 0; |
end |
else if (!enable) begin |
count_of <= 0; |
count_of_copy <= 0; |
end |
else if (count_1 == 1) begin |
count_of <= count_of + 1; |
count_of_copy <= count_of_copy + 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_final <= 0; |
end |
else if (count_3 & enable_1) begin |
Cb11_final <= Cb11 - 25'd5932032; |
/* The Cb values weren't centered on 0 before doing the DCT |
128 needs to be subtracted from each Cb value before, or in this |
case, 362 is subtracted from the total, because this is the |
total obtained by subtracting 128 from each element |
and then multiplying by the weight |
assigned by the DCT matrix : 128*8*5793 = 5932032 |
This is only needed for the first row, the values in the rest of |
the rows add up to 0 */ |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb21_final <= 0; Cb21_final_prev <= 0; |
Cb31_final <= 0; Cb31_final_prev <= 0; |
Cb41_final <= 0; Cb41_final_prev <= 0; |
Cb51_final <= 0; Cb51_final_prev <= 0; |
Cb61_final <= 0; Cb61_final_prev <= 0; |
Cb71_final <= 0; Cb71_final_prev <= 0; |
Cb81_final <= 0; Cb81_final_prev <= 0; |
end |
else if (!enable_1) begin |
Cb21_final <= 0; Cb21_final_prev <= 0; |
Cb31_final <= 0; Cb31_final_prev <= 0; |
Cb41_final <= 0; Cb41_final_prev <= 0; |
Cb51_final <= 0; Cb51_final_prev <= 0; |
Cb61_final <= 0; Cb61_final_prev <= 0; |
Cb71_final <= 0; Cb71_final_prev <= 0; |
Cb81_final <= 0; Cb81_final_prev <= 0; |
end |
else if (count_4 & enable_1) begin |
Cb21_final <= Cb21; Cb21_final_prev <= Cb21_final; |
Cb31_final <= Cb31; Cb31_final_prev <= Cb31_final; |
Cb41_final <= Cb41; Cb41_final_prev <= Cb41_final; |
Cb51_final <= Cb51; Cb51_final_prev <= Cb51_final; |
Cb61_final <= Cb61; Cb61_final_prev <= Cb61_final; |
Cb71_final <= Cb71; Cb71_final_prev <= Cb71_final; |
Cb81_final <= Cb81; Cb81_final_prev <= Cb81_final; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb21_final_diff <= 0; Cb31_final_diff <= 0; |
Cb41_final_diff <= 0; Cb51_final_diff <= 0; |
Cb61_final_diff <= 0; Cb71_final_diff <= 0; |
Cb81_final_diff <= 0; |
end |
else if (count_5 & enable_1) begin |
Cb21_final_diff <= Cb21_final - Cb21_final_prev; |
Cb31_final_diff <= Cb31_final - Cb31_final_prev; |
Cb41_final_diff <= Cb41_final - Cb41_final_prev; |
Cb51_final_diff <= Cb51_final - Cb51_final_prev; |
Cb61_final_diff <= Cb61_final - Cb61_final_prev; |
Cb71_final_diff <= Cb71_final - Cb71_final_prev; |
Cb81_final_diff <= Cb81_final - Cb81_final_prev; |
end |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb2_mul_input <= T21; |
3'b001: Cb2_mul_input <= T22; |
3'b010: Cb2_mul_input <= T23; |
3'b011: Cb2_mul_input <= T24; |
3'b100: Cb2_mul_input <= T25; |
3'b101: Cb2_mul_input <= T26; |
3'b110: Cb2_mul_input <= T27; |
3'b111: Cb2_mul_input <= T28; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb3_mul_input <= T31; |
3'b001: Cb3_mul_input <= T32; |
3'b010: Cb3_mul_input <= T33; |
3'b011: Cb3_mul_input <= T34; |
3'b100: Cb3_mul_input <= T34; |
3'b101: Cb3_mul_input <= T33; |
3'b110: Cb3_mul_input <= T32; |
3'b111: Cb3_mul_input <= T31; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb4_mul_input <= T22; |
3'b001: Cb4_mul_input <= T25; |
3'b010: Cb4_mul_input <= T28; |
3'b011: Cb4_mul_input <= T26; |
3'b100: Cb4_mul_input <= T23; |
3'b101: Cb4_mul_input <= T21; |
3'b110: Cb4_mul_input <= T24; |
3'b111: Cb4_mul_input <= T27; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb5_mul_input <= T1; |
3'b001: Cb5_mul_input <= T52; |
3'b010: Cb5_mul_input <= T52; |
3'b011: Cb5_mul_input <= T1; |
3'b100: Cb5_mul_input <= T1; |
3'b101: Cb5_mul_input <= T52; |
3'b110: Cb5_mul_input <= T52; |
3'b111: Cb5_mul_input <= T1; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb6_mul_input <= T23; |
3'b001: Cb6_mul_input <= T28; |
3'b010: Cb6_mul_input <= T24; |
3'b011: Cb6_mul_input <= T22; |
3'b100: Cb6_mul_input <= T27; |
3'b101: Cb6_mul_input <= T25; |
3'b110: Cb6_mul_input <= T21; |
3'b111: Cb6_mul_input <= T26; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb7_mul_input <= T32; |
3'b001: Cb7_mul_input <= T34; |
3'b010: Cb7_mul_input <= T31; |
3'b011: Cb7_mul_input <= T33; |
3'b100: Cb7_mul_input <= T33; |
3'b101: Cb7_mul_input <= T31; |
3'b110: Cb7_mul_input <= T34; |
3'b111: Cb7_mul_input <= T32; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb8_mul_input <= T24; |
3'b001: Cb8_mul_input <= T26; |
3'b010: Cb8_mul_input <= T22; |
3'b011: Cb8_mul_input <= T28; |
3'b100: Cb8_mul_input <= T21; |
3'b101: Cb8_mul_input <= T27; |
3'b110: Cb8_mul_input <= T23; |
3'b111: Cb8_mul_input <= T25; |
endcase |
end |
|
// Inverse DCT matrix entries |
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti2_mul_input <= Ti28; |
3'b001: Ti2_mul_input <= Ti21; |
3'b010: Ti2_mul_input <= Ti22; |
3'b011: Ti2_mul_input <= Ti23; |
3'b100: Ti2_mul_input <= Ti24; |
3'b101: Ti2_mul_input <= Ti25; |
3'b110: Ti2_mul_input <= Ti26; |
3'b111: Ti2_mul_input <= Ti27; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti3_mul_input <= Ti31; |
3'b001: Ti3_mul_input <= Ti31; |
3'b010: Ti3_mul_input <= Ti32; |
3'b011: Ti3_mul_input <= Ti33; |
3'b100: Ti3_mul_input <= Ti34; |
3'b101: Ti3_mul_input <= Ti34; |
3'b110: Ti3_mul_input <= Ti33; |
3'b111: Ti3_mul_input <= Ti32; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti4_mul_input <= Ti27; |
3'b001: Ti4_mul_input <= Ti22; |
3'b010: Ti4_mul_input <= Ti25; |
3'b011: Ti4_mul_input <= Ti28; |
3'b100: Ti4_mul_input <= Ti26; |
3'b101: Ti4_mul_input <= Ti23; |
3'b110: Ti4_mul_input <= Ti21; |
3'b111: Ti4_mul_input <= Ti24; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti5_mul_input <= Ti1; |
3'b001: Ti5_mul_input <= Ti1; |
3'b010: Ti5_mul_input <= Ti52; |
3'b011: Ti5_mul_input <= Ti52; |
3'b100: Ti5_mul_input <= Ti1; |
3'b101: Ti5_mul_input <= Ti1; |
3'b110: Ti5_mul_input <= Ti52; |
3'b111: Ti5_mul_input <= Ti52; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti6_mul_input <= Ti26; |
3'b001: Ti6_mul_input <= Ti23; |
3'b010: Ti6_mul_input <= Ti28; |
3'b011: Ti6_mul_input <= Ti24; |
3'b100: Ti6_mul_input <= Ti22; |
3'b101: Ti6_mul_input <= Ti27; |
3'b110: Ti6_mul_input <= Ti25; |
3'b111: Ti6_mul_input <= Ti21; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti7_mul_input <= Ti32; |
3'b001: Ti7_mul_input <= Ti32; |
3'b010: Ti7_mul_input <= Ti34; |
3'b011: Ti7_mul_input <= Ti31; |
3'b100: Ti7_mul_input <= Ti33; |
3'b101: Ti7_mul_input <= Ti33; |
3'b110: Ti7_mul_input <= Ti31; |
3'b111: Ti7_mul_input <= Ti34; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti8_mul_input <= Ti25; |
3'b001: Ti8_mul_input <= Ti24; |
3'b010: Ti8_mul_input <= Ti26; |
3'b011: Ti8_mul_input <= Ti22; |
3'b100: Ti8_mul_input <= Ti28; |
3'b101: Ti8_mul_input <= Ti21; |
3'b110: Ti8_mul_input <= Ti27; |
3'b111: Ti8_mul_input <= Ti23; |
endcase |
end |
|
// Rounding stage |
always @(posedge clk) |
begin |
if (rst) begin |
data_1 <= 0; |
Cb11_final_1 <= 0; Cb21_final_1 <= 0; Cb31_final_1 <= 0; Cb41_final_1 <= 0; |
Cb51_final_1 <= 0; Cb61_final_1 <= 0; Cb71_final_1 <= 0; Cb81_final_1 <= 0; |
Cb11_final_2 <= 0; Cb21_final_2 <= 0; Cb31_final_2 <= 0; Cb41_final_2 <= 0; |
Cb51_final_2 <= 0; Cb61_final_2 <= 0; Cb71_final_2 <= 0; Cb81_final_2 <= 0; |
Cb11_final_3 <= 0; Cb11_final_4 <= 0; |
end |
else if (enable) begin |
data_1 <= data_in; |
Cb11_final_1 <= Cb11_final[13] ? Cb11_final[24:14] + 1 : Cb11_final[24:14]; |
Cb11_final_2[31:11] <= Cb11_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb11_final_2[10:0] <= Cb11_final_1; |
// Need to sign extend Cb11_final_1 and the other registers to store a negative |
// number as a twos complement number. If you don't sign extend, then a negative number |
// will be stored incorrectly as a positive number. For example, -215 would be stored |
// as 1833 without sign extending |
Cb11_final_3 <= Cb11_final_2; |
Cb11_final_4 <= Cb11_final_3; |
Cb21_final_1 <= Cb21_final_diff[13] ? Cb21_final_diff[24:14] + 1 : Cb21_final_diff[24:14]; |
Cb21_final_2[31:11] <= Cb21_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb21_final_2[10:0] <= Cb21_final_1; |
Cb31_final_1 <= Cb31_final_diff[13] ? Cb31_final_diff[24:14] + 1 : Cb31_final_diff[24:14]; |
Cb31_final_2[31:11] <= Cb31_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb31_final_2[10:0] <= Cb31_final_1; |
Cb41_final_1 <= Cb41_final_diff[13] ? Cb41_final_diff[24:14] + 1 : Cb41_final_diff[24:14]; |
Cb41_final_2[31:11] <= Cb41_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb41_final_2[10:0] <= Cb41_final_1; |
Cb51_final_1 <= Cb51_final_diff[13] ? Cb51_final_diff[24:14] + 1 : Cb51_final_diff[24:14]; |
Cb51_final_2[31:11] <= Cb51_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb51_final_2[10:0] <= Cb51_final_1; |
Cb61_final_1 <= Cb61_final_diff[13] ? Cb61_final_diff[24:14] + 1 : Cb61_final_diff[24:14]; |
Cb61_final_2[31:11] <= Cb61_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb61_final_2[10:0] <= Cb61_final_1; |
Cb71_final_1 <= Cb71_final_diff[13] ? Cb71_final_diff[24:14] + 1 : Cb71_final_diff[24:14]; |
Cb71_final_2[31:11] <= Cb71_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb71_final_2[10:0] <= Cb71_final_1; |
Cb81_final_1 <= Cb81_final_diff[13] ? Cb81_final_diff[24:14] + 1 : Cb81_final_diff[24:14]; |
Cb81_final_2[31:11] <= Cb81_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb81_final_2[10:0] <= Cb81_final_1; |
// The bit in place 13 is the fraction part, for rounding purposes |
// if it is 1, then you need to add 1 to the bits in 22-14, |
// if bit 13 is 0, then the bits in 22-14 won't change |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; |
end |
else begin |
enable_1 <= enable; |
end |
end |
|
endmodule |
/jpegencode/trunk/rgb2ycbcr.v
0,0 → 1,137
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module converts the incoming Red, Green, and Blue 8-bit pixel data |
into Y, Cb, and Cr 8-bit values. The output values will be unsigned |
in the range of 0 to 255. |
data_in contains the Red pixel value in bits [7:0], Green in bits [15:8], |
and Blue in bits [23:16]. |
data_out contains the Y value in bits [7:0], Cb value in bits [15:8], |
and Cr balue in bits [23:16].*/ |
|
`timescale 1ns / 100ps |
|
module RGB2YCBCR(clk, rst, enable, data_in, data_out, |
enable_out); |
input clk; |
input rst; |
input enable; |
input [23:0] data_in; |
output [23:0] data_out; |
output enable_out; |
|
|
wire [13:0] Y1 = 14'd4899; |
wire [13:0] Y2 = 14'd9617; |
wire [13:0] Y3 = 14'd1868; |
wire [13:0] CB1 = 14'd2764; |
wire [13:0] CB2 = 14'd5428; |
wire [13:0] CB3 = 14'd8192; |
wire [13:0] CR1 = 14'd8192; |
wire [13:0] CR2 = 14'd6860; |
wire [13:0] CR3 = 14'd1332; |
reg [21:0] Y_temp, CB_temp, CR_temp; |
reg [21:0] Y1_product, Y2_product, Y3_product; |
reg [21:0] CB1_product, CB2_product, CB3_product; |
reg [21:0] CR1_product, CR2_product, CR3_product; |
reg [7:0] Y, CB, CR; |
reg enable_1, enable_2, enable_out; |
wire [23:0] data_out = {CR, CB, Y}; |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y1_product <= 0; |
Y2_product <= 0; |
Y3_product <= 0; |
CB1_product <= 0; |
CB2_product <= 0; |
CB3_product <= 0; |
CR1_product <= 0; |
CR2_product <= 0; |
CR3_product <= 0; |
Y_temp <= 0; |
CB_temp <= 0; |
CR_temp <= 0; |
end |
else if (enable) begin |
Y1_product <= Y1 * data_in[7:0]; |
Y2_product <= Y2 * data_in[15:8]; |
Y3_product <= Y3 * data_in[23:16]; |
CB1_product <= CB1 * data_in[7:0]; |
CB2_product <= CB2 * data_in[15:8]; |
CB3_product <= CB3 * data_in[23:16]; |
CR1_product <= CR1 * data_in[7:0]; |
CR2_product <= CR2 * data_in[15:8]; |
CR3_product <= CR3 * data_in[23:16]; |
Y_temp <= Y1_product + Y2_product + Y3_product; |
CB_temp <= 22'd2097152 - CB1_product - CB2_product + CB3_product; |
CR_temp <= 22'd2097152 + CR1_product - CR2_product - CR3_product; |
end |
end |
|
/* Rounding of Y, CB, CR requires looking at bit 13. If there is a '1' in bit 13, |
then the value in bits [21:14] needs to be rounded up by adding 1 to the value |
in those bits */ |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y <= 0; |
CB <= 0; |
CR <= 0; |
end |
else if (enable) begin |
Y <= Y_temp[13] ? Y_temp[21:14] + 1: Y_temp[21:14]; |
CB <= CB_temp[13] & (CB_temp[21:14] != 8'd255) ? CB_temp[21:14] + 1: CB_temp[21:14]; |
CR <= CR_temp[13] & (CR_temp[21:14] != 8'd255) ? CR_temp[21:14] + 1: CR_temp[21:14]; |
// Need to avoid rounding if the value in the top 8 bits is 255, otherwise |
// the value would rollover from 255 to 0 |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; |
enable_2 <= 0; |
enable_out <= 0; |
end |
else begin |
enable_1 <= enable; |
enable_2 <= enable_1; |
enable_out <= enable_2; |
end |
end |
endmodule |
/jpegencode/trunk/ff_checker.v
0,0 → 1,644
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* |
This module takes the JPEG_bitstream as its input, and checks for any FF values in |
the bitstream. When it finds an FF in the bitstream, this module puts a 00 after the FF, |
and then continues with the rest of the bitstream after the 00, per the JPEG standard. |
*/ |
|
`timescale 1ns / 100ps |
|
module ff_checker(clk, rst, end_of_file_signal, JPEG_in, data_ready_in, orc_reg_in, |
JPEG_bitstream_1, data_ready_1, orc_reg, eof_data_partial_ready); |
input clk; |
input rst; |
input end_of_file_signal; |
input [31:0] JPEG_in; |
input data_ready_in; |
input [4:0] orc_reg_in; |
output [31:0] JPEG_bitstream_1; |
output data_ready_1; |
output [4:0] orc_reg; |
output eof_data_partial_ready; |
|
|
reg first_2bytes, second_2bytes, third_2bytes, fourth_2bytes; |
reg first_2bytes_eof, second_2bytes_eof, third_2bytes_eof; |
reg fourth_2bytes_eof, fifth_2bytes_eof, s2b, t2b; |
reg [79:0] JPEG_eof_6, JPEG_eof_7; |
reg [63:0] JPEG_5, JPEG_eof_5_1, JPEG_6, JPEG_7; |
reg [55:0] JPEG_4, JPEG_eof_3, JPEG_eof_4, JPEG_eof_5; |
reg [47:0] JPEG_3, JPEG_eof_2; |
reg [39:0] JPEG_2, JPEG_eof_1; |
reg [31:0] JPEG_1, JPEG_ro, JPEG_bitstream, JPEG_bitstream_1; |
reg [31:0] JPEG_eof, JPEG_eof_ro; |
reg [31:0] JPEG_bitstream_eof; |
reg [15:0] JPEG_eof_ro_ro; |
reg [87:0] JPEG_out, JPEG_out_1, JPEG_pf; |
reg [23:0] JPEG_ro_ro; |
reg dr_in_1, dr_in_2, dr_in_3, dr_in_4, dr_in_5, dr_in_6; |
reg dr_in_7, dr_in_8; |
reg rollover, rollover_1, rollover_2, rollover_3, rollover_4, rollover_5; |
reg rollover_pf, rpf_1; |
reg [1:0] FF_count, FF_count_1, FF_eof_shift; |
reg [2:0] count_total, ct_1; |
reg [1:0] ffc_1, ffc_2, ffc_3, ffc_4, ffc_5, ffc_6, ffc_7; |
reg [1:0] ffc_postfifo, count_total_eof; |
reg [4:0] orc_input; |
reg [4:0] orc_reg; |
reg [6:0] extra_bits_eof, extra_bits_eof_1; |
wire [90:0] read_data; |
wire [90:0] write_data = { JPEG_out_1, ffc_7, rollover_5 }; |
reg data_ready, data_ready_1, write_enable, read_req, rdv_1; |
reg end_of_file_enable, eof_count_enable; |
reg eof_data_partial_ready, eof_dpr_1, eof_dpr_2; |
reg end_of_file_enable_hold, eof_data_ready; |
reg eof_data_ready_1, eof_bits_1, eof_bits_2, eof_bits_3; |
reg [8:0] eof_count; |
wire fifo_empty, rdata_valid; |
|
sync_fifo_ff u18(.clk(clk), .rst(rst), .read_req(read_req), .write_data(write_data), |
.write_enable(write_enable), .rollover_write(rollover_5), |
.read_data(read_data), .fifo_empty(fifo_empty), |
.rdata_valid(rdata_valid)); |
|
// sync_fifo is the FIFO for the bitstream. A FIFO is needed because when a |
// total of 4 FF's have been found, then there will be a rollover of the |
// 32 bit set of JPEG bits. The JPEG bitstream input will need to be stored |
// for 1 clock cycle as the extra 00 put in after the FF will cause an |
// extra set of 32 bits to be put into the bitstream. |
|
always @(posedge clk) |
begin |
if (rst) |
eof_data_partial_ready <= 0; |
else if (eof_bits_1) |
eof_data_partial_ready <= (extra_bits_eof_1 > 0) && (extra_bits_eof_1 < 32); |
else |
eof_data_partial_ready <= eof_dpr_1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
eof_dpr_1 <= 0; |
else if (eof_bits_1) |
eof_dpr_1 <= (extra_bits_eof_1 > 32) && (extra_bits_eof_1 < 64); |
else |
eof_dpr_1 <= eof_dpr_2; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
eof_dpr_2 <= 0; |
else if (eof_bits_1) |
eof_dpr_2 <= extra_bits_eof_1 > 64; |
else |
eof_dpr_2 <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
eof_data_ready_1 <= 0; |
else if (end_of_file_enable) |
eof_data_ready_1 <= (extra_bits_eof_1 > 31); |
else if (eof_bits_1 || eof_bits_2) |
eof_data_ready_1 <= eof_data_ready; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
eof_data_ready <= 0; |
else if (end_of_file_enable) |
eof_data_ready <= (extra_bits_eof_1 > 63); |
else if (eof_bits_1) |
eof_data_ready <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
eof_bits_1 <= 0; eof_bits_2 <= 0; eof_bits_3 <= 0; |
end |
else begin |
eof_bits_1 <= end_of_file_enable; |
eof_bits_2 <= eof_bits_1; |
eof_bits_3 <= eof_bits_2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bitstream_eof <= 0; JPEG_eof_ro <= 0; |
end |
else if (end_of_file_enable) begin |
JPEG_bitstream_eof <= JPEG_eof_7[79:48]; |
JPEG_eof_ro <= JPEG_eof_7[47:16]; |
end |
else if (eof_bits_1 | eof_bits_2) begin |
JPEG_bitstream_eof <= JPEG_eof_ro; |
JPEG_eof_ro <= { JPEG_eof_ro_ro, {16{1'b0}} }; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_eof_ro_ro <= 0; |
else if (end_of_file_enable) |
JPEG_eof_ro_ro <= JPEG_eof_7[15:0]; |
end |
|
always @(posedge clk) |
begin // These registers combine the previous leftover bits with |
// the end of file bits |
if (rst) begin |
JPEG_eof_7 <= 0; JPEG_eof_6 <= 0; JPEG_eof_5_1 <= 0; |
FF_eof_shift <= 0; FF_count_1 <= 0; |
end |
else begin |
JPEG_eof_7[79:72] <= (FF_count_1 > 0) ? JPEG_ro[31:24] : JPEG_eof_6[79:72]; |
JPEG_eof_7[71:64] <= (FF_count_1 > 1) ? JPEG_ro[23:16] : JPEG_eof_6[71:64]; |
JPEG_eof_7[63:56] <= (FF_count_1 > 2) ? JPEG_ro[15:8] : JPEG_eof_6[63:56]; |
JPEG_eof_7[55:0] <= JPEG_eof_6[55:0]; |
JPEG_eof_6 <= JPEG_eof_5_1 << { FF_eof_shift[1], 4'b0000 }; |
JPEG_eof_5_1 <= JPEG_eof_5 << { FF_eof_shift[0], 3'b000 }; |
FF_eof_shift <= 2'b11 - FF_count; |
FF_count_1 <= FF_count; |
end |
end |
|
|
always @(posedge clk) |
begin // These registers generate the end of file bits |
if (rst) begin |
orc_reg <= 0; extra_bits_eof <= 0; |
extra_bits_eof_1 <= 0; count_total_eof <= 0; |
JPEG_eof_5 <= 0; fifth_2bytes_eof <= 0; |
JPEG_eof_4 <= 0; fourth_2bytes_eof <= 0; |
JPEG_eof_3 <= 0; third_2bytes_eof <= 0; |
JPEG_eof_2 <= 0; |
second_2bytes_eof <= 0; JPEG_eof_1 <= 0; |
first_2bytes_eof <= 0; s2b <= 0; |
t2b <= 0; orc_input <= 0; |
end |
else begin |
orc_reg <= extra_bits_eof_1[4:0]; |
extra_bits_eof <= { 2'b00, orc_input } + { 2'b00, FF_count, 3'b000 }; |
extra_bits_eof_1 <= extra_bits_eof + { 2'b00, count_total_eof, 3'b000 }; |
count_total_eof <= first_2bytes_eof + s2b + t2b; |
JPEG_eof_5[55:16] <= JPEG_eof_4[55:16]; |
JPEG_eof_5[15:8] <= fifth_2bytes_eof ? 8'b00000000 : JPEG_eof_4[15:8]; |
JPEG_eof_5[7:0] <= fifth_2bytes_eof ? JPEG_eof_4[15:8] : JPEG_eof_4[7:0]; |
fifth_2bytes_eof <= (JPEG_eof_4[23:16] == 8'b11111111); |
JPEG_eof_4[55:24] <= JPEG_eof_3[55:24]; |
JPEG_eof_4[23:16] <= fourth_2bytes_eof ? 8'b00000000 : JPEG_eof_3[23:16]; |
JPEG_eof_4[15:8] <= fourth_2bytes_eof ? JPEG_eof_3[23:16] : JPEG_eof_3[15:8]; |
JPEG_eof_4[7:0] <= fourth_2bytes_eof ? JPEG_eof_3[15:8] : JPEG_eof_3[7:0]; |
fourth_2bytes_eof <= (JPEG_eof_3[31:24] == 8'b11111111); |
JPEG_eof_3[55:32] <= JPEG_eof_2[47:24]; |
JPEG_eof_3[31:24] <= third_2bytes_eof ? 8'b00000000 : JPEG_eof_2[23:16]; |
JPEG_eof_3[23:16] <= third_2bytes_eof ? JPEG_eof_2[23:16] : JPEG_eof_2[15:8]; |
JPEG_eof_3[15:8] <= third_2bytes_eof ? JPEG_eof_2[15:8] : JPEG_eof_2[7:0]; |
JPEG_eof_3[7:0] <= third_2bytes_eof ? JPEG_eof_2[7:0] : 8'b00000000; |
third_2bytes_eof <= (JPEG_eof_2[31:24] == 8'b11111111); |
JPEG_eof_2[47:32] <= JPEG_eof_1[39:24]; |
JPEG_eof_2[31:24] <= second_2bytes_eof ? 8'b00000000 : JPEG_eof_1[23:16]; |
JPEG_eof_2[23:16] <= second_2bytes_eof ? JPEG_eof_1[23:16] : JPEG_eof_1[15:8]; |
JPEG_eof_2[15:8] <= second_2bytes_eof ? JPEG_eof_1[15:8] : JPEG_eof_1[7:0]; |
JPEG_eof_2[7:0] <= second_2bytes_eof ? JPEG_eof_1[7:0] : 8'b00000000; |
second_2bytes_eof <= (JPEG_eof_1[31:24] == 8'b11111111); |
JPEG_eof_1[39:32] <= JPEG_eof[31:24]; |
JPEG_eof_1[31:24] <= first_2bytes_eof ? 8'b00000000 : JPEG_eof[23:16]; |
JPEG_eof_1[23:16] <= first_2bytes_eof ? JPEG_eof[23:16] : JPEG_eof[15:8]; |
JPEG_eof_1[15:8] <= first_2bytes_eof ? JPEG_eof[15:8] : JPEG_eof[7:0]; |
JPEG_eof_1[7:0] <= first_2bytes_eof ? JPEG_eof[7:0] : 8'b00000000; |
first_2bytes_eof <= (JPEG_eof[31:24] == 8'b11111111); |
s2b <= (JPEG_eof[23:16] == 8'b11111111); |
t2b <= (JPEG_eof[15:8] == 8'b11111111); |
orc_input <= orc_reg_in; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_eof <= 0; |
end |
else begin |
JPEG_eof[31] <= (orc_reg_in > 5'b00000) ? JPEG_in[31] : 1'b0; |
JPEG_eof[30] <= (orc_reg_in > 5'b00001) ? JPEG_in[30] : 1'b0; |
JPEG_eof[29] <= (orc_reg_in > 5'b00010) ? JPEG_in[29] : 1'b0; |
JPEG_eof[28] <= (orc_reg_in > 5'b00011) ? JPEG_in[28] : 1'b0; |
JPEG_eof[27] <= (orc_reg_in > 5'b00100) ? JPEG_in[27] : 1'b0; |
JPEG_eof[26] <= (orc_reg_in > 5'b00101) ? JPEG_in[26] : 1'b0; |
JPEG_eof[25] <= (orc_reg_in > 5'b00110) ? JPEG_in[25] : 1'b0; |
JPEG_eof[24] <= (orc_reg_in > 5'b00111) ? JPEG_in[24] : 1'b0; |
JPEG_eof[23] <= (orc_reg_in > 5'b01000) ? JPEG_in[23] : 1'b0; |
JPEG_eof[22] <= (orc_reg_in > 5'b01001) ? JPEG_in[22] : 1'b0; |
JPEG_eof[21] <= (orc_reg_in > 5'b01010) ? JPEG_in[21] : 1'b0; |
JPEG_eof[20] <= (orc_reg_in > 5'b01011) ? JPEG_in[20] : 1'b0; |
JPEG_eof[19] <= (orc_reg_in > 5'b01100) ? JPEG_in[19] : 1'b0; |
JPEG_eof[18] <= (orc_reg_in > 5'b01101) ? JPEG_in[18] : 1'b0; |
JPEG_eof[17] <= (orc_reg_in > 5'b01110) ? JPEG_in[17] : 1'b0; |
JPEG_eof[16] <= (orc_reg_in > 5'b01111) ? JPEG_in[16] : 1'b0; |
JPEG_eof[15] <= (orc_reg_in > 5'b10000) ? JPEG_in[15] : 1'b0; |
JPEG_eof[14] <= (orc_reg_in > 5'b10001) ? JPEG_in[14] : 1'b0; |
JPEG_eof[13] <= (orc_reg_in > 5'b10010) ? JPEG_in[13] : 1'b0; |
JPEG_eof[12] <= (orc_reg_in > 5'b10011) ? JPEG_in[12] : 1'b0; |
JPEG_eof[11] <= (orc_reg_in > 5'b10100) ? JPEG_in[11] : 1'b0; |
JPEG_eof[10] <= (orc_reg_in > 5'b10101) ? JPEG_in[10] : 1'b0; |
JPEG_eof[9] <= (orc_reg_in > 5'b10110) ? JPEG_in[9] : 1'b0; |
JPEG_eof[8] <= (orc_reg_in > 5'b10111) ? JPEG_in[8] : 1'b0; |
JPEG_eof[7] <= (orc_reg_in > 5'b11000) ? JPEG_in[7] : 1'b0; |
JPEG_eof[6] <= (orc_reg_in > 5'b11001) ? JPEG_in[6] : 1'b0; |
JPEG_eof[5] <= (orc_reg_in > 5'b11010) ? JPEG_in[5] : 1'b0; |
JPEG_eof[4] <= (orc_reg_in > 5'b11011) ? JPEG_in[4] : 1'b0; |
JPEG_eof[3] <= (orc_reg_in > 5'b11100) ? JPEG_in[3] : 1'b0; |
JPEG_eof[2] <= (orc_reg_in > 5'b11101) ? JPEG_in[2] : 1'b0; |
JPEG_eof[1] <= (orc_reg_in > 5'b11110) ? JPEG_in[1] : 1'b0; |
JPEG_eof[0] <= 1'b0; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
eof_count_enable <= 0; |
else if (end_of_file_enable_hold) |
eof_count_enable <= 0; |
else if (end_of_file_signal) |
eof_count_enable <= 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
eof_count <= 0; |
else if (!eof_count_enable) |
eof_count <= 0; |
else if (eof_count_enable) |
eof_count <= eof_count + 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
end_of_file_enable <= 0; |
else if (eof_count != 9'b011110000) |
end_of_file_enable <= 0; |
else if (eof_count == 9'b011110000) |
end_of_file_enable <= 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
end_of_file_enable_hold <= 0; |
else if (end_of_file_enable) |
end_of_file_enable_hold <= 1; |
end |
|
// This ends the section dealing with the end of file. |
|
always @(posedge clk) |
begin |
if (rst) begin |
data_ready_1 <= 0; JPEG_bitstream_1 <= 0; |
end |
else begin |
data_ready_1 <= data_ready || eof_data_ready_1; |
JPEG_bitstream_1 <= (eof_bits_1 || eof_bits_2 || eof_bits_3) ? |
JPEG_bitstream_eof : JPEG_bitstream; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
data_ready <= 0; rdv_1 <= 0; rpf_1 <= 0; |
end |
else begin |
data_ready <= rdv_1 || rpf_1; |
rdv_1 <= rdata_valid; |
rpf_1 <= rollover_pf & !rpf_1; // there can't be 2 rollover's in a row |
// because after the first rollover, the next fifo entry is dummy data |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[31:24] <= 0; |
else if (rdv_1 && ffc_postfifo == 0 && !rpf_1) |
JPEG_bitstream[31:24] <= JPEG_pf[87:80]; |
else if (rpf_1 || (rdv_1 && ffc_postfifo > 0)) |
JPEG_bitstream[31:24] <= JPEG_ro[31:24]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[23:16] <= 0; |
else if (rdv_1 && ffc_postfifo < 2 && !rpf_1) |
JPEG_bitstream[23:16] <= JPEG_pf[79:72]; |
else if (rpf_1 || (rdv_1 && ffc_postfifo > 1)) |
JPEG_bitstream[23:16] <= JPEG_ro[23:16]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[15:8] <= 0; |
else if (rdv_1 && ffc_postfifo < 3 && !rpf_1) |
JPEG_bitstream[15:8] <= JPEG_pf[71:64]; |
else if (rpf_1 || (rdv_1 && ffc_postfifo == 3)) |
JPEG_bitstream[15:8] <= JPEG_ro[15:8]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[7:0] <= 0; |
else if (rdv_1 && !rpf_1) |
JPEG_bitstream[7:0] <= JPEG_pf[63:56]; |
else if (rpf_1) |
JPEG_bitstream[7:0] <= JPEG_ro[7:0]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_ro <= 0; |
else if (rdv_1 && !rpf_1) |
JPEG_ro <= JPEG_pf[55:24]; |
else if (rpf_1) |
JPEG_ro[31:8] <= JPEG_ro_ro; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_ro_ro <= 0; |
end |
else if (rdv_1) begin |
JPEG_ro_ro <= JPEG_pf[23:0]; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (fifo_empty) |
read_req <= 0; |
else if (!fifo_empty) |
read_req <= 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
rollover_pf <= 0; |
else if (!rdata_valid) |
rollover_pf <= 0; |
else if (rdata_valid) |
rollover_pf <= read_data[0]; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_pf <= 0; ffc_postfifo <= 0; |
end |
else if (rdata_valid) begin |
JPEG_pf <= read_data[90:3]; |
ffc_postfifo <= read_data[2:1]; |
// ffc_postfifo is the current count of how many FF's there have |
// been in the bitstream. This determines how the bitstream from the |
// FIFO is adjusted as it is put into the output bitstream. |
end |
end |
|
always @(posedge clk) |
begin |
if (!dr_in_8) |
write_enable <= 0; |
else if (dr_in_8) |
write_enable <= 1; |
// write_enable is the write enable to the FIFO |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_out_1 <= 0; ffc_7 <= 0; |
end |
else if (dr_in_8) begin |
JPEG_out_1 <= ffc_6[0] ? JPEG_out : JPEG_out << 8; |
ffc_7 <= ffc_6; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_out <= 0; ffc_6 <= 0; |
end |
else if (dr_in_7) begin |
JPEG_out <= ffc_5[1] ? JPEG_7 : JPEG_7 << 16; |
ffc_6 <= ffc_5; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_7 <= 0; ffc_5 <= 0; |
end |
else if (dr_in_6) begin |
JPEG_7[63:16] <= JPEG_6[63:16]; |
JPEG_7[15:8] <= (JPEG_6[23:16] == 8'b11111111) ? 8'b00000000 : JPEG_6[15:8]; |
JPEG_7[7:0] <= (JPEG_6[23:16] == 8'b11111111) ? JPEG_6[15:8] : JPEG_6[7:0]; |
ffc_5 <= ffc_4; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_6 <= 0; ffc_4 <= 0; |
end |
else if (dr_in_5) begin |
JPEG_6[63:24] <= JPEG_5[63:24]; |
JPEG_6[23:16] <= (JPEG_5[31:24] == 8'b11111111) ? 8'b00000000 : JPEG_5[23:16]; |
JPEG_6[15:8] <= (JPEG_5[31:24] == 8'b11111111) ? JPEG_5[23:16] : JPEG_5[15:8]; |
JPEG_6[7:0] <= (JPEG_5[31:24] == 8'b11111111) ? JPEG_5[15:8] : JPEG_5[7:0]; |
ffc_4 <= ffc_3; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_5 <= 0; ffc_3 <= 0; |
end |
else if (dr_in_4) begin |
JPEG_5[63:32] <= JPEG_4[55:24]; |
JPEG_5[31:24] <= (JPEG_4[31:24] == 8'b11111111) ? 8'b00000000 : JPEG_4[23:16]; |
JPEG_5[23:16] <= (JPEG_4[31:24] == 8'b11111111) ? JPEG_4[23:16] : JPEG_4[15:8]; |
JPEG_5[15:8] <= (JPEG_4[31:24] == 8'b11111111) ? JPEG_4[15:8] : JPEG_4[7:0]; |
JPEG_5[7:0] <= (JPEG_4[31:24] == 8'b11111111) ? JPEG_4[7:0] : 8'b00000000; |
ffc_3 <= ffc_2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_4 <= 0; ffc_2 <= 0; |
end |
else if (dr_in_3) begin |
JPEG_4[55:32] <= JPEG_3[47:24]; |
JPEG_4[31:24] <= (JPEG_3[31:24] == 8'b11111111) ? 8'b00000000 : JPEG_3[23:16]; |
JPEG_4[23:16] <= (JPEG_3[31:24] == 8'b11111111) ? JPEG_3[23:16] : JPEG_3[15:8]; |
JPEG_4[15:8] <= (JPEG_3[31:24] == 8'b11111111) ? JPEG_3[15:8] : JPEG_3[7:0]; |
JPEG_4[7:0] <= (JPEG_3[31:24] == 8'b11111111) ? JPEG_3[7:0] : 8'b00000000; |
ffc_2 <= ffc_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_3 <= 0; ct_1 <= 0; FF_count <= 0; |
ffc_1 <= 0; |
end |
else if (dr_in_2) begin |
JPEG_3[47:32] <= JPEG_2[39:24]; |
JPEG_3[31:24] <= (JPEG_2[31:24] == 8'b11111111) ? 8'b00000000 : JPEG_2[23:16]; |
JPEG_3[23:16] <= (JPEG_2[31:24] == 8'b11111111) ? JPEG_2[23:16] : JPEG_2[15:8]; |
JPEG_3[15:8] <= (JPEG_2[31:24] == 8'b11111111) ? JPEG_2[15:8] : JPEG_2[7:0]; |
JPEG_3[7:0] <= (JPEG_2[31:24] == 8'b11111111) ? JPEG_2[7:0] : 8'b00000000; |
ct_1 <= count_total; |
FF_count <= FF_count + count_total; |
ffc_1 <= FF_count; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_2 <= 0; count_total <= 0; |
end |
else if (dr_in_1) begin |
JPEG_2[39:32] <= JPEG_1[31:24]; |
JPEG_2[31:24] <= first_2bytes ? 8'b00000000 : JPEG_1[23:16]; |
JPEG_2[23:16] <= first_2bytes ? JPEG_1[23:16] : JPEG_1[15:8]; |
JPEG_2[15:8] <= first_2bytes ? JPEG_1[15:8] : JPEG_1[7:0]; |
JPEG_2[7:0] <= first_2bytes ? JPEG_1[7:0] : 8'b00000000; |
count_total <= first_2bytes + second_2bytes + third_2bytes + fourth_2bytes; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
first_2bytes <= 0; second_2bytes <= 0; |
third_2bytes <= 0; fourth_2bytes <= 0; |
JPEG_1 <= 0; |
end |
else if (data_ready_in) begin |
first_2bytes <= JPEG_in[31:24] == 8'b11111111; |
second_2bytes <= JPEG_in[23:16] == 8'b11111111; |
third_2bytes <= JPEG_in[15:8] == 8'b11111111; |
fourth_2bytes <= JPEG_in[7:0] == 8'b11111111; |
JPEG_1 <= JPEG_in; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
rollover_1 <= 0; rollover_2 <= 0; rollover_3 <= 0; |
rollover_4 <= 0; rollover_5 <= 0; |
end |
else begin |
rollover_1 <= rollover; rollover_2 <= rollover_1; |
rollover_3 <= rollover_2; rollover_4 <= rollover_3; |
rollover_5 <= rollover_4; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
rollover <= 0; |
else if (!dr_in_3) |
rollover <= 0; |
else if (dr_in_3) |
rollover <= (FF_count < ffc_1) | (ct_1 == 3'b100); |
// A rollover occurs whenever the next count is less than the current count. |
// FF_count is the next count of how many FF's have been found in the bitstream |
// The count rolls over at 4. A rollover could also occur if all 32 bits of the |
// are FF's, which would be 4 FF's in the bitstream. This is the condition where |
// ct_1 == 3'b100. This is highly unlikely, almost impossible, but it could |
// theoretically happen. |
// In that case, the next count would equal the current count, and by |
// comparing the two, you wouldn't get a rollover condition, so you need the extra |
// check of the condition ct_1 == 3'b100. |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
dr_in_1 <= 0; dr_in_2 <= 0; dr_in_3 <= 0; dr_in_4 <= 0; |
dr_in_5 <= 0; dr_in_6 <= 0; dr_in_7 <= 0; dr_in_8 <= 0; |
end |
else begin |
dr_in_1 <= data_ready_in; |
dr_in_2 <= dr_in_1; |
dr_in_3 <= dr_in_2; |
dr_in_4 <= dr_in_3; |
dr_in_5 <= dr_in_4; |
dr_in_6 <= dr_in_5; |
dr_in_7 <= dr_in_6; |
dr_in_8 <= dr_in_7; |
end |
end |
|
endmodule |
/jpegencode/trunk/cbd_q_h.v
0,0 → 1,138
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module combines the dct, quantizer, and huffman modules. */ |
|
|
`timescale 1ns / 100ps |
|
module cbd_q_h(clk, rst, enable, data_in, |
JPEG_bitstream, data_ready, cb_orc, |
end_of_block_empty); |
input clk; |
input rst; |
input enable; |
input [7:0] data_in; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output [4:0] cb_orc; |
output end_of_block_empty; |
|
wire dct_enable, quantizer_enable; |
wire [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
wire [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
wire [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
wire [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
wire [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
wire [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
wire [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
wire [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
wire [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
wire [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
wire [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
wire [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
wire [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
wire [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
wire [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
wire [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
wire [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18; |
wire [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28; |
wire [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
wire [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48; |
wire [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58; |
wire [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
wire [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78; |
wire [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88; |
|
cb_dct u5( |
.clk(clk),.rst(rst), .enable(enable), .data_in(data_in), |
.Z11_final(Z11_final), .Z12_final(Z12_final), |
.Z13_final(Z13_final), .Z14_final(Z14_final), .Z15_final(Z15_final), .Z16_final(Z16_final), |
.Z17_final(Z17_final), .Z18_final(Z18_final), .Z21_final(Z21_final), .Z22_final(Z22_final), |
.Z23_final(Z23_final), .Z24_final(Z24_final), .Z25_final(Z25_final), .Z26_final(Z26_final), |
.Z27_final(Z27_final), .Z28_final(Z28_final), .Z31_final(Z31_final), .Z32_final(Z32_final), |
.Z33_final(Z33_final), .Z34_final(Z34_final), .Z35_final(Z35_final), .Z36_final(Z36_final), |
.Z37_final(Z37_final), .Z38_final(Z38_final), .Z41_final(Z41_final), .Z42_final(Z42_final), |
.Z43_final(Z43_final), .Z44_final(Z44_final), .Z45_final(Z45_final), .Z46_final(Z46_final), |
.Z47_final(Z47_final), .Z48_final(Z48_final), .Z51_final(Z51_final), .Z52_final(Z52_final), |
.Z53_final(Z53_final), .Z54_final(Z54_final), .Z55_final(Z55_final), .Z56_final(Z56_final), |
.Z57_final(Z57_final), .Z58_final(Z58_final), .Z61_final(Z61_final), .Z62_final(Z62_final), |
.Z63_final(Z63_final), .Z64_final(Z64_final), .Z65_final(Z65_final), .Z66_final(Z66_final), |
.Z67_final(Z67_final), .Z68_final(Z68_final), .Z71_final(Z71_final), .Z72_final(Z72_final), |
.Z73_final(Z73_final), .Z74_final(Z74_final), .Z75_final(Z75_final), .Z76_final(Z76_final), |
.Z77_final(Z77_final), .Z78_final(Z78_final), .Z81_final(Z81_final), .Z82_final(Z82_final), |
.Z83_final(Z83_final), .Z84_final(Z84_final), .Z85_final(Z85_final), .Z86_final(Z86_final), |
.Z87_final(Z87_final), .Z88_final(Z88_final), .output_enable(dct_enable)); |
|
cb_quantizer u6( |
.clk(clk),.rst(rst),.enable(dct_enable), |
.Z11(Z11_final), .Z12(Z12_final), .Z13(Z13_final), .Z14(Z14_final), |
.Z15(Z15_final), .Z16(Z16_final), .Z17(Z17_final), .Z18(Z18_final), |
.Z21(Z21_final), .Z22(Z22_final), .Z23(Z23_final), .Z24(Z24_final), |
.Z25(Z25_final), .Z26(Z26_final), .Z27(Z27_final), .Z28(Z28_final), |
.Z31(Z31_final), .Z32(Z32_final), .Z33(Z33_final), .Z34(Z34_final), |
.Z35(Z35_final), .Z36(Z36_final), .Z37(Z37_final), .Z38(Z38_final), |
.Z41(Z41_final), .Z42(Z42_final), .Z43(Z43_final), .Z44(Z44_final), |
.Z45(Z45_final), .Z46(Z46_final), .Z47(Z47_final), .Z48(Z48_final), |
.Z51(Z51_final), .Z52(Z52_final), .Z53(Z53_final), .Z54(Z54_final), |
.Z55(Z55_final), .Z56(Z56_final), .Z57(Z57_final), .Z58(Z58_final), |
.Z61(Z61_final), .Z62(Z62_final), .Z63(Z63_final), .Z64(Z64_final), |
.Z65(Z65_final), .Z66(Z66_final), .Z67(Z67_final), .Z68(Z68_final), |
.Z71(Z71_final), .Z72(Z72_final), .Z73(Z73_final), .Z74(Z74_final), |
.Z75(Z75_final), .Z76(Z76_final), .Z77(Z77_final), .Z78(Z78_final), |
.Z81(Z81_final), .Z82(Z82_final), .Z83(Z83_final), .Z84(Z84_final), |
.Z85(Z85_final), .Z86(Z86_final), .Z87(Z87_final), .Z88(Z88_final), |
.Q11(Q11), .Q12(Q12), .Q13(Q13), .Q14(Q14), .Q15(Q15), .Q16(Q16), .Q17(Q17), .Q18(Q18), |
.Q21(Q21), .Q22(Q22), .Q23(Q23), .Q24(Q24), .Q25(Q25), .Q26(Q26), .Q27(Q27), .Q28(Q28), |
.Q31(Q31), .Q32(Q32), .Q33(Q33), .Q34(Q34), .Q35(Q35), .Q36(Q36), .Q37(Q37), .Q38(Q38), |
.Q41(Q41), .Q42(Q42), .Q43(Q43), .Q44(Q44), .Q45(Q45), .Q46(Q46), .Q47(Q47), .Q48(Q48), |
.Q51(Q51), .Q52(Q52), .Q53(Q53), .Q54(Q54), .Q55(Q55), .Q56(Q56), .Q57(Q57), .Q58(Q58), |
.Q61(Q61), .Q62(Q62), .Q63(Q63), .Q64(Q64), .Q65(Q65), .Q66(Q66), .Q67(Q67), .Q68(Q68), |
.Q71(Q71), .Q72(Q72), .Q73(Q73), .Q74(Q74), .Q75(Q75), .Q76(Q76), .Q77(Q77), .Q78(Q78), |
.Q81(Q81), .Q82(Q82), .Q83(Q83), .Q84(Q84), .Q85(Q85), .Q86(Q86), .Q87(Q87), .Q88(Q88), |
.out_enable(quantizer_enable)); |
|
cb_huff u7(.clk(clk), .rst(rst), .enable(quantizer_enable), |
.Cb11(Q11), .Cb12(Q21), .Cb13(Q31), .Cb14(Q41), .Cb15(Q51), .Cb16(Q61), .Cb17(Q71), .Cb18(Q81), |
.Cb21(Q12), .Cb22(Q22), .Cb23(Q32), .Cb24(Q42), .Cb25(Q52), .Cb26(Q62), .Cb27(Q72), .Cb28(Q82), |
.Cb31(Q13), .Cb32(Q23), .Cb33(Q33), .Cb34(Q43), .Cb35(Q53), .Cb36(Q63), .Cb37(Q73), .Cb38(Q83), |
.Cb41(Q14), .Cb42(Q24), .Cb43(Q34), .Cb44(Q44), .Cb45(Q54), .Cb46(Q64), .Cb47(Q74), .Cb48(Q84), |
.Cb51(Q15), .Cb52(Q25), .Cb53(Q35), .Cb54(Q45), .Cb55(Q55), .Cb56(Q65), .Cb57(Q75), .Cb58(Q85), |
.Cb61(Q16), .Cb62(Q26), .Cb63(Q36), .Cb64(Q46), .Cb65(Q56), .Cb66(Q66), .Cb67(Q76), .Cb68(Q86), |
.Cb71(Q17), .Cb72(Q27), .Cb73(Q37), .Cb74(Q47), .Cb75(Q57), .Cb76(Q67), .Cb77(Q77), .Cb78(Q87), |
.Cb81(Q18), .Cb82(Q28), .Cb83(Q38), .Cb84(Q48), .Cb85(Q58), .Cb86(Q68), .Cb87(Q78), .Cb88(Q88), |
.JPEG_bitstream(JPEG_bitstream), .data_ready(data_ready), .output_reg_count(cb_orc), |
.end_of_block_empty(end_of_block_empty)); |
|
|
endmodule |
/jpegencode/trunk/y_huff.v
0,0 → 1,2253
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module is the Huffman encoder. It takes in the quantized outputs |
from the quantizer, and creates the Huffman codes from these value. The |
output from this module is the jpeg code of the actual pixel data. The jpeg |
file headers will need to be generated separately. The Huffman codes are constant, |
and they can be changed by changing the parameters in this module. */ |
|
`timescale 1ns / 100ps |
|
module y_huff(clk, rst, enable, |
Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24, Y25, Y26, Y27, Y28, |
Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38, Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48, |
Y51, Y52, Y53, Y54, Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68, |
Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84, Y85, Y86, Y87, Y88, |
JPEG_bitstream, data_ready, output_reg_count, end_of_block_output, |
end_of_block_empty); |
input clk; |
input rst; |
input enable; |
input [10:0] Y11, Y12, Y13, Y14, Y15, Y16, Y17, Y18, Y21, Y22, Y23, Y24; |
input [10:0] Y25, Y26, Y27, Y28, Y31, Y32, Y33, Y34, Y35, Y36, Y37, Y38; |
input [10:0] Y41, Y42, Y43, Y44, Y45, Y46, Y47, Y48, Y51, Y52, Y53, Y54; |
input [10:0] Y55, Y56, Y57, Y58, Y61, Y62, Y63, Y64, Y65, Y66, Y67, Y68; |
input [10:0] Y71, Y72, Y73, Y74, Y75, Y76, Y77, Y78, Y81, Y82, Y83, Y84; |
input [10:0] Y85, Y86, Y87, Y88; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output output_reg_count; |
output end_of_block_output; |
output end_of_block_empty; |
|
reg [7:0] block_counter; |
reg [11:0] Y11_amp, Y11_1_pos, Y11_1_neg, Y11_diff; |
reg [11:0] Y11_previous, Y11_1; |
reg [10:0] Y12_amp, Y12_pos, Y12_neg; |
reg [10:0] Y21_pos, Y21_neg, Y31_pos, Y31_neg, Y22_pos, Y22_neg; |
reg [10:0] Y13_pos, Y13_neg, Y14_pos, Y14_neg, Y15_pos, Y15_neg; |
reg [10:0] Y16_pos, Y16_neg, Y17_pos, Y17_neg, Y18_pos, Y18_neg; |
reg [10:0] Y23_pos, Y23_neg, Y24_pos, Y24_neg, Y25_pos, Y25_neg; |
reg [10:0] Y26_pos, Y26_neg, Y27_pos, Y27_neg, Y28_pos, Y28_neg; |
reg [10:0] Y32_pos, Y32_neg; |
reg [10:0] Y33_pos, Y33_neg, Y34_pos, Y34_neg, Y35_pos, Y35_neg; |
reg [10:0] Y36_pos, Y36_neg, Y37_pos, Y37_neg, Y38_pos, Y38_neg; |
reg [10:0] Y41_pos, Y41_neg, Y42_pos, Y42_neg; |
reg [10:0] Y43_pos, Y43_neg, Y44_pos, Y44_neg, Y45_pos, Y45_neg; |
reg [10:0] Y46_pos, Y46_neg, Y47_pos, Y47_neg, Y48_pos, Y48_neg; |
reg [10:0] Y51_pos, Y51_neg, Y52_pos, Y52_neg; |
reg [10:0] Y53_pos, Y53_neg, Y54_pos, Y54_neg, Y55_pos, Y55_neg; |
reg [10:0] Y56_pos, Y56_neg, Y57_pos, Y57_neg, Y58_pos, Y58_neg; |
reg [10:0] Y61_pos, Y61_neg, Y62_pos, Y62_neg; |
reg [10:0] Y63_pos, Y63_neg, Y64_pos, Y64_neg, Y65_pos, Y65_neg; |
reg [10:0] Y66_pos, Y66_neg, Y67_pos, Y67_neg, Y68_pos, Y68_neg; |
reg [10:0] Y71_pos, Y71_neg, Y72_pos, Y72_neg; |
reg [10:0] Y73_pos, Y73_neg, Y74_pos, Y74_neg, Y75_pos, Y75_neg; |
reg [10:0] Y76_pos, Y76_neg, Y77_pos, Y77_neg, Y78_pos, Y78_neg; |
reg [10:0] Y81_pos, Y81_neg, Y82_pos, Y82_neg; |
reg [10:0] Y83_pos, Y83_neg, Y84_pos, Y84_neg, Y85_pos, Y85_neg; |
reg [10:0] Y86_pos, Y86_neg, Y87_pos, Y87_neg, Y88_pos, Y88_neg; |
reg [3:0] Y11_bits_pos, Y11_bits_neg, Y11_bits, Y11_bits_1; |
reg [3:0] Y12_bits_pos, Y12_bits_neg, Y12_bits, Y12_bits_1; |
reg [3:0] Y12_bits_2, Y12_bits_3; |
reg Y11_msb, Y12_msb, Y12_msb_1, data_ready; |
reg enable_1, enable_2, enable_3, enable_4, enable_5, enable_6; |
reg enable_7, enable_8, enable_9, enable_10, enable_11, enable_12; |
reg enable_13, enable_module, enable_latch_7, enable_latch_8; |
reg Y12_et_zero, rollover, rollover_1, rollover_2, rollover_3; |
reg rollover_4, rollover_5, rollover_6, rollover_7; |
reg Y21_et_zero, Y21_msb, Y31_et_zero, Y31_msb; |
reg Y22_et_zero, Y22_msb, Y13_et_zero, Y13_msb; |
reg Y14_et_zero, Y14_msb, Y15_et_zero, Y15_msb; |
reg Y16_et_zero, Y16_msb, Y17_et_zero, Y17_msb; |
reg Y18_et_zero, Y18_msb; |
reg Y23_et_zero, Y23_msb, Y24_et_zero, Y24_msb; |
reg Y25_et_zero, Y25_msb, Y26_et_zero, Y26_msb; |
reg Y27_et_zero, Y27_msb, Y28_et_zero, Y28_msb; |
reg Y32_et_zero, Y32_msb, Y33_et_zero, Y33_msb; |
reg Y34_et_zero, Y34_msb, Y35_et_zero, Y35_msb; |
reg Y36_et_zero, Y36_msb, Y37_et_zero, Y37_msb; |
reg Y38_et_zero, Y38_msb; |
reg Y41_et_zero, Y41_msb, Y42_et_zero, Y42_msb; |
reg Y43_et_zero, Y43_msb, Y44_et_zero, Y44_msb; |
reg Y45_et_zero, Y45_msb, Y46_et_zero, Y46_msb; |
reg Y47_et_zero, Y47_msb, Y48_et_zero, Y48_msb; |
reg Y51_et_zero, Y51_msb, Y52_et_zero, Y52_msb; |
reg Y53_et_zero, Y53_msb, Y54_et_zero, Y54_msb; |
reg Y55_et_zero, Y55_msb, Y56_et_zero, Y56_msb; |
reg Y57_et_zero, Y57_msb, Y58_et_zero, Y58_msb; |
reg Y61_et_zero, Y61_msb, Y62_et_zero, Y62_msb; |
reg Y63_et_zero, Y63_msb, Y64_et_zero, Y64_msb; |
reg Y65_et_zero, Y65_msb, Y66_et_zero, Y66_msb; |
reg Y67_et_zero, Y67_msb, Y68_et_zero, Y68_msb; |
reg Y71_et_zero, Y71_msb, Y72_et_zero, Y72_msb; |
reg Y73_et_zero, Y73_msb, Y74_et_zero, Y74_msb; |
reg Y75_et_zero, Y75_msb, Y76_et_zero, Y76_msb; |
reg Y77_et_zero, Y77_msb, Y78_et_zero, Y78_msb; |
reg Y81_et_zero, Y81_msb, Y82_et_zero, Y82_msb; |
reg Y83_et_zero, Y83_msb, Y84_et_zero, Y84_msb; |
reg Y85_et_zero, Y85_msb, Y86_et_zero, Y86_msb; |
reg Y87_et_zero, Y87_msb, Y88_et_zero, Y88_msb; |
reg Y12_et_zero_1, Y12_et_zero_2, Y12_et_zero_3, Y12_et_zero_4, Y12_et_zero_5; |
reg [10:0] Y_DC [11:0]; |
reg [3:0] Y_DC_code_length [11:0]; |
reg [15:0] Y_AC [161:0]; |
reg [4:0] Y_AC_code_length [161:0]; |
reg [7:0] Y_AC_run_code [250:0]; |
reg [10:0] Y11_Huff, Y11_Huff_1, Y11_Huff_2; |
reg [15:0] Y12_Huff, Y12_Huff_1, Y12_Huff_2; |
reg [3:0] Y11_Huff_count, Y11_Huff_shift, Y11_Huff_shift_1, Y11_amp_shift, Y12_amp_shift; |
reg [3:0] Y12_Huff_shift, Y12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3; |
reg [4:0] Y12_Huff_count, Y12_Huff_count_1; |
reg [4:0] output_reg_count, Y11_output_count, old_orc_1, old_orc_2; |
reg [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Y12_oc_1; |
reg [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8; |
reg [4:0] Y12_output_count; |
reg [4:0] Y12_edge, Y12_edge_1, Y12_edge_2, Y12_edge_3, Y12_edge_4; |
reg [31:0] JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5; |
reg [31:0] JPEG_Y12_bs, JPEG_Y12_bs_1, JPEG_Y12_bs_2, JPEG_Y12_bs_3, JPEG_Y12_bs_4; |
reg [31:0] JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4; |
reg [21:0] Y11_JPEG_LSBs_3; |
reg [10:0] Y11_JPEG_LSBs, Y11_JPEG_LSBs_1, Y11_JPEG_LSBs_2; |
reg [9:0] Y12_JPEG_LSBs, Y12_JPEG_LSBs_1, Y12_JPEG_LSBs_2, Y12_JPEG_LSBs_3; |
reg [25:0] Y11_JPEG_bits, Y11_JPEG_bits_1, Y12_JPEG_bits, Y12_JPEG_LSBs_4; |
reg [7:0] Y12_code_entry; |
reg third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s; |
reg eighth_8_all_0s, end_of_block, code_15_0, zrl_et_15, end_of_block_output; |
reg end_of_block_empty; |
|
wire [7:0] code_index = { zrl_2, Y12_bits }; |
|
|
|
always @(posedge clk) |
begin |
if (rst) begin |
third_8_all_0s <= 0; fourth_8_all_0s <= 0; |
fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0; |
eighth_8_all_0s <= 0; |
end |
else if (enable_1) begin |
third_8_all_0s <= Y25_et_zero & Y34_et_zero & Y43_et_zero & Y52_et_zero |
& Y61_et_zero & Y71_et_zero & Y62_et_zero & Y53_et_zero; |
fourth_8_all_0s <= Y44_et_zero & Y35_et_zero & Y26_et_zero & Y17_et_zero |
& Y18_et_zero & Y27_et_zero & Y36_et_zero & Y45_et_zero; |
fifth_8_all_0s <= Y54_et_zero & Y63_et_zero & Y72_et_zero & Y81_et_zero |
& Y82_et_zero & Y73_et_zero & Y64_et_zero & Y55_et_zero; |
sixth_8_all_0s <= Y46_et_zero & Y37_et_zero & Y28_et_zero & Y38_et_zero |
& Y47_et_zero & Y56_et_zero & Y65_et_zero & Y74_et_zero; |
seventh_8_all_0s <= Y83_et_zero & Y84_et_zero & Y75_et_zero & Y66_et_zero |
& Y57_et_zero & Y48_et_zero & Y58_et_zero & Y67_et_zero; |
eighth_8_all_0s <= Y76_et_zero & Y85_et_zero & Y86_et_zero & Y77_et_zero |
& Y68_et_zero & Y78_et_zero & Y87_et_zero & Y88_et_zero; |
end |
end |
|
|
/* end_of_block checks to see if there are any nonzero elements left in the block |
If there aren't any nonzero elements left, then the last bits in the JPEG stream |
will be the end of block code. The purpose of this register is to determine if the |
zero run length code 15-0 should be used or not. It should be used if there are 15 or more |
zeros in a row, followed by a nonzero value. If there are only zeros left in the block, |
then end_of_block will be 1. If there are any nonzero values left in the block, end_of_block |
will be 0. */ |
|
always @(posedge clk) |
begin |
if (rst) |
end_of_block <= 0; |
else if (enable) |
end_of_block <= 0; |
else if (enable_module & block_counter < 32) |
end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s |
& sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s; |
else if (enable_module & block_counter < 48) |
end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s |
& eighth_8_all_0s; |
else if (enable_module & block_counter <= 64) |
end_of_block <= seventh_8_all_0s & eighth_8_all_0s; |
else if (enable_module & block_counter > 64) |
end_of_block <= 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
block_counter <= 0; |
end |
else if (enable) begin |
block_counter <= 0; |
end |
else if (enable_module) begin |
block_counter <= block_counter + 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
output_reg_count <= 0; |
end |
else if (end_of_block_output) begin |
output_reg_count <= 0; |
end |
else if (enable_6) begin |
output_reg_count <= output_reg_count + Y11_output_count; |
end |
else if (enable_latch_7) begin |
output_reg_count <= output_reg_count + Y12_oc_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
old_orc_1 <= 0; |
end |
else if (end_of_block_output) begin |
old_orc_1 <= 0; |
end |
else if (enable_module) begin |
old_orc_1 <= output_reg_count; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
rollover <= 0; rollover_1 <= 0; rollover_2 <= 0; |
rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0; |
rollover_6 <= 0; rollover_7 <= 0; |
old_orc_2 <= 0; |
orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0; |
orc_7 <= 0; orc_8 <= 0; data_ready <= 0; |
end_of_block_output <= 0; end_of_block_empty <= 0; |
end |
else if (enable_module) begin |
rollover <= (old_orc_1 > output_reg_count); |
rollover_1 <= rollover; |
rollover_2 <= rollover_1; |
rollover_3 <= rollover_2; |
rollover_4 <= rollover_3; |
rollover_5 <= rollover_4; |
rollover_6 <= rollover_5; |
rollover_7 <= rollover_6; |
old_orc_2 <= old_orc_1; |
orc_3 <= old_orc_2; |
orc_4 <= orc_3; orc_5 <= orc_4; |
orc_6 <= orc_5; orc_7 <= orc_6; |
orc_8 <= orc_7; |
data_ready <= rollover_6 | block_counter == 77; |
end_of_block_output <= block_counter == 77; |
end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0; |
end |
end |
|
|
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_5 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31]; |
JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30]; |
JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29]; |
JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28]; |
JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27]; |
JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26]; |
JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25]; |
JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24]; |
JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23]; |
JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22]; |
JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21]; |
JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20]; |
JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19]; |
JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18]; |
JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17]; |
JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16]; |
JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15]; |
JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14]; |
JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13]; |
JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12]; |
JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11]; |
JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10]; |
JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9]; |
JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8]; |
JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7]; |
JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6]; |
JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5]; |
JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4]; |
JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3]; |
JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2]; |
JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1]; |
JPEG_bs_5[0] <= JPEG_bs_4[0]; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3; |
JPEG_ro_bs_4 <= (Y12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0; |
Y12_edge_4 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2; |
old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5; |
JPEG_ro_bs_3 <= (Y12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2; |
Y12_edge_4 <= (Y12_edge_3 <= 2) ? Y12_edge_3 : Y12_edge_3 - 2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0; |
Y12_edge_3 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1; |
old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4; |
JPEG_ro_bs_2 <= (Y12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1; |
Y12_edge_3 <= (Y12_edge_2 <= 4) ? Y12_edge_2 : Y12_edge_2 - 4; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0; |
Y12_edge_2 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs; |
old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3; |
JPEG_ro_bs_1 <= (Y12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs; |
Y12_edge_2 <= (Y12_edge_1 <= 8) ? Y12_edge_1 : Y12_edge_1 - 8; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0; |
Y12_edge_1 <= 0; Y11_JPEG_bits_1 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs <= (old_orc_2 >= 16) ? Y11_JPEG_bits >> 10 : Y11_JPEG_bits << 6; |
old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2; |
JPEG_ro_bs <= (Y12_edge <= 16) ? Y11_JPEG_bits_1 << 16 : Y11_JPEG_bits_1; |
Y12_edge_1 <= (Y12_edge <= 16) ? Y12_edge : Y12_edge - 16; |
Y11_JPEG_bits_1 <= Y11_JPEG_bits; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_JPEG_bits <= 0; Y12_edge <= 0; |
end |
else if (enable_module) begin |
Y12_JPEG_bits[25] <= (Y12_Huff_shift_1 >= 16) ? Y12_JPEG_LSBs_4[25] : Y12_Huff_2[15]; |
Y12_JPEG_bits[24] <= (Y12_Huff_shift_1 >= 15) ? Y12_JPEG_LSBs_4[24] : Y12_Huff_2[14]; |
Y12_JPEG_bits[23] <= (Y12_Huff_shift_1 >= 14) ? Y12_JPEG_LSBs_4[23] : Y12_Huff_2[13]; |
Y12_JPEG_bits[22] <= (Y12_Huff_shift_1 >= 13) ? Y12_JPEG_LSBs_4[22] : Y12_Huff_2[12]; |
Y12_JPEG_bits[21] <= (Y12_Huff_shift_1 >= 12) ? Y12_JPEG_LSBs_4[21] : Y12_Huff_2[11]; |
Y12_JPEG_bits[20] <= (Y12_Huff_shift_1 >= 11) ? Y12_JPEG_LSBs_4[20] : Y12_Huff_2[10]; |
Y12_JPEG_bits[19] <= (Y12_Huff_shift_1 >= 10) ? Y12_JPEG_LSBs_4[19] : Y12_Huff_2[9]; |
Y12_JPEG_bits[18] <= (Y12_Huff_shift_1 >= 9) ? Y12_JPEG_LSBs_4[18] : Y12_Huff_2[8]; |
Y12_JPEG_bits[17] <= (Y12_Huff_shift_1 >= 8) ? Y12_JPEG_LSBs_4[17] : Y12_Huff_2[7]; |
Y12_JPEG_bits[16] <= (Y12_Huff_shift_1 >= 7) ? Y12_JPEG_LSBs_4[16] : Y12_Huff_2[6]; |
Y12_JPEG_bits[15] <= (Y12_Huff_shift_1 >= 6) ? Y12_JPEG_LSBs_4[15] : Y12_Huff_2[5]; |
Y12_JPEG_bits[14] <= (Y12_Huff_shift_1 >= 5) ? Y12_JPEG_LSBs_4[14] : Y12_Huff_2[4]; |
Y12_JPEG_bits[13] <= (Y12_Huff_shift_1 >= 4) ? Y12_JPEG_LSBs_4[13] : Y12_Huff_2[3]; |
Y12_JPEG_bits[12] <= (Y12_Huff_shift_1 >= 3) ? Y12_JPEG_LSBs_4[12] : Y12_Huff_2[2]; |
Y12_JPEG_bits[11] <= (Y12_Huff_shift_1 >= 2) ? Y12_JPEG_LSBs_4[11] : Y12_Huff_2[1]; |
Y12_JPEG_bits[10] <= (Y12_Huff_shift_1 >= 1) ? Y12_JPEG_LSBs_4[10] : Y12_Huff_2[0]; |
Y12_JPEG_bits[9:0] <= Y12_JPEG_LSBs_4[9:0]; |
Y12_edge <= old_orc_2 + 26; // 26 is the size of Y11_JPEG_bits |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_JPEG_bits <= 0; |
end |
else if (enable_7) begin |
Y11_JPEG_bits[25] <= (Y11_Huff_shift_1 >= 11) ? Y11_JPEG_LSBs_3[21] : Y11_Huff_2[10]; |
Y11_JPEG_bits[24] <= (Y11_Huff_shift_1 >= 10) ? Y11_JPEG_LSBs_3[20] : Y11_Huff_2[9]; |
Y11_JPEG_bits[23] <= (Y11_Huff_shift_1 >= 9) ? Y11_JPEG_LSBs_3[19] : Y11_Huff_2[8]; |
Y11_JPEG_bits[22] <= (Y11_Huff_shift_1 >= 8) ? Y11_JPEG_LSBs_3[18] : Y11_Huff_2[7]; |
Y11_JPEG_bits[21] <= (Y11_Huff_shift_1 >= 7) ? Y11_JPEG_LSBs_3[17] : Y11_Huff_2[6]; |
Y11_JPEG_bits[20] <= (Y11_Huff_shift_1 >= 6) ? Y11_JPEG_LSBs_3[16] : Y11_Huff_2[5]; |
Y11_JPEG_bits[19] <= (Y11_Huff_shift_1 >= 5) ? Y11_JPEG_LSBs_3[15] : Y11_Huff_2[4]; |
Y11_JPEG_bits[18] <= (Y11_Huff_shift_1 >= 4) ? Y11_JPEG_LSBs_3[14] : Y11_Huff_2[3]; |
Y11_JPEG_bits[17] <= (Y11_Huff_shift_1 >= 3) ? Y11_JPEG_LSBs_3[13] : Y11_Huff_2[2]; |
Y11_JPEG_bits[16] <= (Y11_Huff_shift_1 >= 2) ? Y11_JPEG_LSBs_3[12] : Y11_Huff_2[1]; |
Y11_JPEG_bits[15] <= (Y11_Huff_shift_1 >= 1) ? Y11_JPEG_LSBs_3[11] : Y11_Huff_2[0]; |
Y11_JPEG_bits[14:4] <= Y11_JPEG_LSBs_3[10:0]; |
end |
else if (enable_latch_8) begin |
Y11_JPEG_bits <= Y12_JPEG_bits; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_oc_1 <= 0; Y12_JPEG_LSBs_4 <= 0; |
Y12_Huff_2 <= 0; Y12_Huff_shift_1 <= 0; |
end |
else if (enable_module) begin |
Y12_oc_1 <= (Y12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 : |
Y12_bits_3 + Y12_Huff_count_1; |
Y12_JPEG_LSBs_4 <= Y12_JPEG_LSBs_3 << Y12_Huff_shift; |
Y12_Huff_2 <= Y12_Huff_1; |
Y12_Huff_shift_1 <= Y12_Huff_shift; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_JPEG_LSBs_3 <= 0; Y11_Huff_2 <= 0; |
Y11_Huff_shift_1 <= 0; |
end |
else if (enable_6) begin |
Y11_JPEG_LSBs_3 <= Y11_JPEG_LSBs_2 << Y11_Huff_shift; |
Y11_Huff_2 <= Y11_Huff_1; |
Y11_Huff_shift_1 <= Y11_Huff_shift; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_Huff_shift <= 0; |
Y12_Huff_1 <= 0; Y12_JPEG_LSBs_3 <= 0; Y12_bits_3 <= 0; |
Y12_Huff_count_1 <= 0; Y12_et_zero_5 <= 0; code_15_0 <= 0; |
end |
else if (enable_module) begin |
Y12_Huff_shift <= 16 - Y12_Huff_count; |
Y12_Huff_1 <= Y12_Huff; |
Y12_JPEG_LSBs_3 <= Y12_JPEG_LSBs_2; |
Y12_bits_3 <= Y12_bits_2; |
Y12_Huff_count_1 <= Y12_Huff_count; |
Y12_et_zero_5 <= Y12_et_zero_4; |
code_15_0 <= zrl_et_15 & !end_of_block; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_output_count <= 0; Y11_JPEG_LSBs_2 <= 0; Y11_Huff_shift <= 0; |
Y11_Huff_1 <= 0; |
end |
else if (enable_5) begin |
Y11_output_count <= Y11_bits_1 + Y11_Huff_count; |
Y11_JPEG_LSBs_2 <= Y11_JPEG_LSBs_1 << Y11_amp_shift; |
Y11_Huff_shift <= 11 - Y11_Huff_count; |
Y11_Huff_1 <= Y11_Huff; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_JPEG_LSBs_2 <= 0; |
Y12_Huff <= 0; Y12_Huff_count <= 0; Y12_bits_2 <= 0; |
Y12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0; |
end |
else if (enable_module) begin |
Y12_JPEG_LSBs_2 <= Y12_JPEG_LSBs_1 << Y12_amp_shift; |
Y12_Huff <= Y_AC[Y12_code_entry]; |
Y12_Huff_count <= Y_AC_code_length[Y12_code_entry]; |
Y12_bits_2 <= Y12_bits_1; |
Y12_et_zero_4 <= Y12_et_zero_3; |
zrl_et_15 <= zrl_3 == 15; |
zrl_3 <= zrl_2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_Huff <= 0; Y11_Huff_count <= 0; Y11_amp_shift <= 0; |
Y11_JPEG_LSBs_1 <= 0; Y11_bits_1 <= 0; |
end |
else if (enable_4) begin |
Y11_Huff[10:0] <= Y_DC[Y11_bits]; |
Y11_Huff_count <= Y_DC_code_length[Y11_bits]; |
Y11_amp_shift <= 11 - Y11_bits; |
Y11_JPEG_LSBs_1 <= Y11_JPEG_LSBs; |
Y11_bits_1 <= Y11_bits; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_code_entry <= 0; Y12_JPEG_LSBs_1 <= 0; Y12_amp_shift <= 0; |
Y12_bits_1 <= 0; Y12_et_zero_3 <= 0; zrl_2 <= 0; |
end |
else if (enable_module) begin |
Y12_code_entry <= Y_AC_run_code[code_index]; |
Y12_JPEG_LSBs_1 <= Y12_JPEG_LSBs; |
Y12_amp_shift <= 10 - Y12_bits; |
Y12_bits_1 <= Y12_bits; |
Y12_et_zero_3 <= Y12_et_zero_2; |
zrl_2 <= zrl_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_bits <= 0; Y11_JPEG_LSBs <= 0; |
end |
else if (enable_3) begin |
Y11_bits <= Y11_msb ? Y11_bits_neg : Y11_bits_pos; |
Y11_JPEG_LSBs <= Y11_amp[10:0]; // The top bit of Y11_amp is the sign bit |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_bits <= 0; Y12_JPEG_LSBs <= 0; zrl_1 <= 0; |
Y12_et_zero_2 <= 0; |
end |
else if (enable_module) begin |
Y12_bits <= Y12_msb_1 ? Y12_bits_neg : Y12_bits_pos; |
Y12_JPEG_LSBs <= Y12_amp[9:0]; // The top bit of Y12_amp is the sign bit |
zrl_1 <= block_counter == 62 & Y12_et_zero ? 0 : zero_run_length; |
Y12_et_zero_2 <= Y12_et_zero_1; |
end |
end |
|
// Y11_amp is the amplitude that will be represented in bits in the |
// JPEG code, following the run length code |
always @(posedge clk) |
begin |
if (rst) begin |
Y11_amp <= 0; |
end |
else if (enable_2) begin |
Y11_amp <= Y11_msb ? Y11_1_neg : Y11_1_pos; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) |
zero_run_length <= 0; |
else if (enable) |
zero_run_length <= 0; |
else if (enable_module) |
zero_run_length <= Y12_et_zero ? zero_run_length + 1: 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_amp <= 0; |
Y12_et_zero_1 <= 0; Y12_msb_1 <= 0; |
end |
else if (enable_module) begin |
Y12_amp <= Y12_msb ? Y12_neg : Y12_pos; |
Y12_et_zero_1 <= Y12_et_zero; |
Y12_msb_1 <= Y12_msb; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_1_pos <= 0; Y11_1_neg <= 0; Y11_msb <= 0; |
Y11_previous <= 0; |
end |
else if (enable_1) begin |
Y11_1_pos <= Y11_diff; |
Y11_1_neg <= Y11_diff - 1; |
Y11_msb <= Y11_diff[11]; |
Y11_previous <= Y11_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y12_pos <= 0; Y12_neg <= 0; Y12_msb <= 0; Y12_et_zero <= 0; |
Y13_pos <= 0; Y13_neg <= 0; Y13_msb <= 0; Y13_et_zero <= 0; |
Y14_pos <= 0; Y14_neg <= 0; Y14_msb <= 0; Y14_et_zero <= 0; |
Y15_pos <= 0; Y15_neg <= 0; Y15_msb <= 0; Y15_et_zero <= 0; |
Y16_pos <= 0; Y16_neg <= 0; Y16_msb <= 0; Y16_et_zero <= 0; |
Y17_pos <= 0; Y17_neg <= 0; Y17_msb <= 0; Y17_et_zero <= 0; |
Y18_pos <= 0; Y18_neg <= 0; Y18_msb <= 0; Y18_et_zero <= 0; |
Y21_pos <= 0; Y21_neg <= 0; Y21_msb <= 0; Y21_et_zero <= 0; |
Y22_pos <= 0; Y22_neg <= 0; Y22_msb <= 0; Y22_et_zero <= 0; |
Y23_pos <= 0; Y23_neg <= 0; Y23_msb <= 0; Y23_et_zero <= 0; |
Y24_pos <= 0; Y24_neg <= 0; Y24_msb <= 0; Y24_et_zero <= 0; |
Y25_pos <= 0; Y25_neg <= 0; Y25_msb <= 0; Y25_et_zero <= 0; |
Y26_pos <= 0; Y26_neg <= 0; Y26_msb <= 0; Y26_et_zero <= 0; |
Y27_pos <= 0; Y27_neg <= 0; Y27_msb <= 0; Y27_et_zero <= 0; |
Y28_pos <= 0; Y28_neg <= 0; Y28_msb <= 0; Y28_et_zero <= 0; |
Y31_pos <= 0; Y31_neg <= 0; Y31_msb <= 0; Y31_et_zero <= 0; |
Y32_pos <= 0; Y32_neg <= 0; Y32_msb <= 0; Y32_et_zero <= 0; |
Y33_pos <= 0; Y33_neg <= 0; Y33_msb <= 0; Y33_et_zero <= 0; |
Y34_pos <= 0; Y34_neg <= 0; Y34_msb <= 0; Y34_et_zero <= 0; |
Y35_pos <= 0; Y35_neg <= 0; Y35_msb <= 0; Y35_et_zero <= 0; |
Y36_pos <= 0; Y36_neg <= 0; Y36_msb <= 0; Y36_et_zero <= 0; |
Y37_pos <= 0; Y37_neg <= 0; Y37_msb <= 0; Y37_et_zero <= 0; |
Y38_pos <= 0; Y38_neg <= 0; Y38_msb <= 0; Y38_et_zero <= 0; |
Y41_pos <= 0; Y41_neg <= 0; Y41_msb <= 0; Y41_et_zero <= 0; |
Y42_pos <= 0; Y42_neg <= 0; Y42_msb <= 0; Y42_et_zero <= 0; |
Y43_pos <= 0; Y43_neg <= 0; Y43_msb <= 0; Y43_et_zero <= 0; |
Y44_pos <= 0; Y44_neg <= 0; Y44_msb <= 0; Y44_et_zero <= 0; |
Y45_pos <= 0; Y45_neg <= 0; Y45_msb <= 0; Y45_et_zero <= 0; |
Y46_pos <= 0; Y46_neg <= 0; Y46_msb <= 0; Y46_et_zero <= 0; |
Y47_pos <= 0; Y47_neg <= 0; Y47_msb <= 0; Y47_et_zero <= 0; |
Y48_pos <= 0; Y48_neg <= 0; Y48_msb <= 0; Y48_et_zero <= 0; |
Y51_pos <= 0; Y51_neg <= 0; Y51_msb <= 0; Y51_et_zero <= 0; |
Y52_pos <= 0; Y52_neg <= 0; Y52_msb <= 0; Y52_et_zero <= 0; |
Y53_pos <= 0; Y53_neg <= 0; Y53_msb <= 0; Y53_et_zero <= 0; |
Y54_pos <= 0; Y54_neg <= 0; Y54_msb <= 0; Y54_et_zero <= 0; |
Y55_pos <= 0; Y55_neg <= 0; Y55_msb <= 0; Y55_et_zero <= 0; |
Y56_pos <= 0; Y56_neg <= 0; Y56_msb <= 0; Y56_et_zero <= 0; |
Y57_pos <= 0; Y57_neg <= 0; Y57_msb <= 0; Y57_et_zero <= 0; |
Y58_pos <= 0; Y58_neg <= 0; Y58_msb <= 0; Y58_et_zero <= 0; |
Y61_pos <= 0; Y61_neg <= 0; Y61_msb <= 0; Y61_et_zero <= 0; |
Y62_pos <= 0; Y62_neg <= 0; Y62_msb <= 0; Y62_et_zero <= 0; |
Y63_pos <= 0; Y63_neg <= 0; Y63_msb <= 0; Y63_et_zero <= 0; |
Y64_pos <= 0; Y64_neg <= 0; Y64_msb <= 0; Y64_et_zero <= 0; |
Y65_pos <= 0; Y65_neg <= 0; Y65_msb <= 0; Y65_et_zero <= 0; |
Y66_pos <= 0; Y66_neg <= 0; Y66_msb <= 0; Y66_et_zero <= 0; |
Y67_pos <= 0; Y67_neg <= 0; Y67_msb <= 0; Y67_et_zero <= 0; |
Y68_pos <= 0; Y68_neg <= 0; Y68_msb <= 0; Y68_et_zero <= 0; |
Y71_pos <= 0; Y71_neg <= 0; Y71_msb <= 0; Y71_et_zero <= 0; |
Y72_pos <= 0; Y72_neg <= 0; Y72_msb <= 0; Y72_et_zero <= 0; |
Y73_pos <= 0; Y73_neg <= 0; Y73_msb <= 0; Y73_et_zero <= 0; |
Y74_pos <= 0; Y74_neg <= 0; Y74_msb <= 0; Y74_et_zero <= 0; |
Y75_pos <= 0; Y75_neg <= 0; Y75_msb <= 0; Y75_et_zero <= 0; |
Y76_pos <= 0; Y76_neg <= 0; Y76_msb <= 0; Y76_et_zero <= 0; |
Y77_pos <= 0; Y77_neg <= 0; Y77_msb <= 0; Y77_et_zero <= 0; |
Y78_pos <= 0; Y78_neg <= 0; Y78_msb <= 0; Y78_et_zero <= 0; |
Y81_pos <= 0; Y81_neg <= 0; Y81_msb <= 0; Y81_et_zero <= 0; |
Y82_pos <= 0; Y82_neg <= 0; Y82_msb <= 0; Y82_et_zero <= 0; |
Y83_pos <= 0; Y83_neg <= 0; Y83_msb <= 0; Y83_et_zero <= 0; |
Y84_pos <= 0; Y84_neg <= 0; Y84_msb <= 0; Y84_et_zero <= 0; |
Y85_pos <= 0; Y85_neg <= 0; Y85_msb <= 0; Y85_et_zero <= 0; |
Y86_pos <= 0; Y86_neg <= 0; Y86_msb <= 0; Y86_et_zero <= 0; |
Y87_pos <= 0; Y87_neg <= 0; Y87_msb <= 0; Y87_et_zero <= 0; |
Y88_pos <= 0; Y88_neg <= 0; Y88_msb <= 0; Y88_et_zero <= 0; |
end |
else if (enable) begin |
Y12_pos <= Y12; |
Y12_neg <= Y12 - 1; |
Y12_msb <= Y12[10]; |
Y12_et_zero <= !(|Y12); |
Y13_pos <= Y13; |
Y13_neg <= Y13 - 1; |
Y13_msb <= Y13[10]; |
Y13_et_zero <= !(|Y13); |
Y14_pos <= Y14; |
Y14_neg <= Y14 - 1; |
Y14_msb <= Y14[10]; |
Y14_et_zero <= !(|Y14); |
Y15_pos <= Y15; |
Y15_neg <= Y15 - 1; |
Y15_msb <= Y15[10]; |
Y15_et_zero <= !(|Y15); |
Y16_pos <= Y16; |
Y16_neg <= Y16 - 1; |
Y16_msb <= Y16[10]; |
Y16_et_zero <= !(|Y16); |
Y17_pos <= Y17; |
Y17_neg <= Y17 - 1; |
Y17_msb <= Y17[10]; |
Y17_et_zero <= !(|Y17); |
Y18_pos <= Y18; |
Y18_neg <= Y18 - 1; |
Y18_msb <= Y18[10]; |
Y18_et_zero <= !(|Y18); |
Y21_pos <= Y21; |
Y21_neg <= Y21 - 1; |
Y21_msb <= Y21[10]; |
Y21_et_zero <= !(|Y21); |
Y22_pos <= Y22; |
Y22_neg <= Y22 - 1; |
Y22_msb <= Y22[10]; |
Y22_et_zero <= !(|Y22); |
Y23_pos <= Y23; |
Y23_neg <= Y23 - 1; |
Y23_msb <= Y23[10]; |
Y23_et_zero <= !(|Y23); |
Y24_pos <= Y24; |
Y24_neg <= Y24 - 1; |
Y24_msb <= Y24[10]; |
Y24_et_zero <= !(|Y24); |
Y25_pos <= Y25; |
Y25_neg <= Y25 - 1; |
Y25_msb <= Y25[10]; |
Y25_et_zero <= !(|Y25); |
Y26_pos <= Y26; |
Y26_neg <= Y26 - 1; |
Y26_msb <= Y26[10]; |
Y26_et_zero <= !(|Y26); |
Y27_pos <= Y27; |
Y27_neg <= Y27 - 1; |
Y27_msb <= Y27[10]; |
Y27_et_zero <= !(|Y27); |
Y28_pos <= Y28; |
Y28_neg <= Y28 - 1; |
Y28_msb <= Y28[10]; |
Y28_et_zero <= !(|Y28); |
Y31_pos <= Y31; |
Y31_neg <= Y31 - 1; |
Y31_msb <= Y31[10]; |
Y31_et_zero <= !(|Y31); |
Y32_pos <= Y32; |
Y32_neg <= Y32 - 1; |
Y32_msb <= Y32[10]; |
Y32_et_zero <= !(|Y32); |
Y33_pos <= Y33; |
Y33_neg <= Y33 - 1; |
Y33_msb <= Y33[10]; |
Y33_et_zero <= !(|Y33); |
Y34_pos <= Y34; |
Y34_neg <= Y34 - 1; |
Y34_msb <= Y34[10]; |
Y34_et_zero <= !(|Y34); |
Y35_pos <= Y35; |
Y35_neg <= Y35 - 1; |
Y35_msb <= Y35[10]; |
Y35_et_zero <= !(|Y35); |
Y36_pos <= Y36; |
Y36_neg <= Y36 - 1; |
Y36_msb <= Y36[10]; |
Y36_et_zero <= !(|Y36); |
Y37_pos <= Y37; |
Y37_neg <= Y37 - 1; |
Y37_msb <= Y37[10]; |
Y37_et_zero <= !(|Y37); |
Y38_pos <= Y38; |
Y38_neg <= Y38 - 1; |
Y38_msb <= Y38[10]; |
Y38_et_zero <= !(|Y38); |
Y41_pos <= Y41; |
Y41_neg <= Y41 - 1; |
Y41_msb <= Y41[10]; |
Y41_et_zero <= !(|Y41); |
Y42_pos <= Y42; |
Y42_neg <= Y42 - 1; |
Y42_msb <= Y42[10]; |
Y42_et_zero <= !(|Y42); |
Y43_pos <= Y43; |
Y43_neg <= Y43 - 1; |
Y43_msb <= Y43[10]; |
Y43_et_zero <= !(|Y43); |
Y44_pos <= Y44; |
Y44_neg <= Y44 - 1; |
Y44_msb <= Y44[10]; |
Y44_et_zero <= !(|Y44); |
Y45_pos <= Y45; |
Y45_neg <= Y45 - 1; |
Y45_msb <= Y45[10]; |
Y45_et_zero <= !(|Y45); |
Y46_pos <= Y46; |
Y46_neg <= Y46 - 1; |
Y46_msb <= Y46[10]; |
Y46_et_zero <= !(|Y46); |
Y47_pos <= Y47; |
Y47_neg <= Y47 - 1; |
Y47_msb <= Y47[10]; |
Y47_et_zero <= !(|Y47); |
Y48_pos <= Y48; |
Y48_neg <= Y48 - 1; |
Y48_msb <= Y48[10]; |
Y48_et_zero <= !(|Y48); |
Y51_pos <= Y51; |
Y51_neg <= Y51 - 1; |
Y51_msb <= Y51[10]; |
Y51_et_zero <= !(|Y51); |
Y52_pos <= Y52; |
Y52_neg <= Y52 - 1; |
Y52_msb <= Y52[10]; |
Y52_et_zero <= !(|Y52); |
Y53_pos <= Y53; |
Y53_neg <= Y53 - 1; |
Y53_msb <= Y53[10]; |
Y53_et_zero <= !(|Y53); |
Y54_pos <= Y54; |
Y54_neg <= Y54 - 1; |
Y54_msb <= Y54[10]; |
Y54_et_zero <= !(|Y54); |
Y55_pos <= Y55; |
Y55_neg <= Y55 - 1; |
Y55_msb <= Y55[10]; |
Y55_et_zero <= !(|Y55); |
Y56_pos <= Y56; |
Y56_neg <= Y56 - 1; |
Y56_msb <= Y56[10]; |
Y56_et_zero <= !(|Y56); |
Y57_pos <= Y57; |
Y57_neg <= Y57 - 1; |
Y57_msb <= Y57[10]; |
Y57_et_zero <= !(|Y57); |
Y58_pos <= Y58; |
Y58_neg <= Y58 - 1; |
Y58_msb <= Y58[10]; |
Y58_et_zero <= !(|Y58); |
Y61_pos <= Y61; |
Y61_neg <= Y61 - 1; |
Y61_msb <= Y61[10]; |
Y61_et_zero <= !(|Y61); |
Y62_pos <= Y62; |
Y62_neg <= Y62 - 1; |
Y62_msb <= Y62[10]; |
Y62_et_zero <= !(|Y62); |
Y63_pos <= Y63; |
Y63_neg <= Y63 - 1; |
Y63_msb <= Y63[10]; |
Y63_et_zero <= !(|Y63); |
Y64_pos <= Y64; |
Y64_neg <= Y64 - 1; |
Y64_msb <= Y64[10]; |
Y64_et_zero <= !(|Y64); |
Y65_pos <= Y65; |
Y65_neg <= Y65 - 1; |
Y65_msb <= Y65[10]; |
Y65_et_zero <= !(|Y65); |
Y66_pos <= Y66; |
Y66_neg <= Y66 - 1; |
Y66_msb <= Y66[10]; |
Y66_et_zero <= !(|Y66); |
Y67_pos <= Y67; |
Y67_neg <= Y67 - 1; |
Y67_msb <= Y67[10]; |
Y67_et_zero <= !(|Y67); |
Y68_pos <= Y68; |
Y68_neg <= Y68 - 1; |
Y68_msb <= Y68[10]; |
Y68_et_zero <= !(|Y68); |
Y71_pos <= Y71; |
Y71_neg <= Y71 - 1; |
Y71_msb <= Y71[10]; |
Y71_et_zero <= !(|Y71); |
Y72_pos <= Y72; |
Y72_neg <= Y72 - 1; |
Y72_msb <= Y72[10]; |
Y72_et_zero <= !(|Y72); |
Y73_pos <= Y73; |
Y73_neg <= Y73 - 1; |
Y73_msb <= Y73[10]; |
Y73_et_zero <= !(|Y73); |
Y74_pos <= Y74; |
Y74_neg <= Y74 - 1; |
Y74_msb <= Y74[10]; |
Y74_et_zero <= !(|Y74); |
Y75_pos <= Y75; |
Y75_neg <= Y75 - 1; |
Y75_msb <= Y75[10]; |
Y75_et_zero <= !(|Y75); |
Y76_pos <= Y76; |
Y76_neg <= Y76 - 1; |
Y76_msb <= Y76[10]; |
Y76_et_zero <= !(|Y76); |
Y77_pos <= Y77; |
Y77_neg <= Y77 - 1; |
Y77_msb <= Y77[10]; |
Y77_et_zero <= !(|Y77); |
Y78_pos <= Y78; |
Y78_neg <= Y78 - 1; |
Y78_msb <= Y78[10]; |
Y78_et_zero <= !(|Y78); |
Y81_pos <= Y81; |
Y81_neg <= Y81 - 1; |
Y81_msb <= Y81[10]; |
Y81_et_zero <= !(|Y81); |
Y82_pos <= Y82; |
Y82_neg <= Y82 - 1; |
Y82_msb <= Y82[10]; |
Y82_et_zero <= !(|Y82); |
Y83_pos <= Y83; |
Y83_neg <= Y83 - 1; |
Y83_msb <= Y83[10]; |
Y83_et_zero <= !(|Y83); |
Y84_pos <= Y84; |
Y84_neg <= Y84 - 1; |
Y84_msb <= Y84[10]; |
Y84_et_zero <= !(|Y84); |
Y85_pos <= Y85; |
Y85_neg <= Y85 - 1; |
Y85_msb <= Y85[10]; |
Y85_et_zero <= !(|Y85); |
Y86_pos <= Y86; |
Y86_neg <= Y86 - 1; |
Y86_msb <= Y86[10]; |
Y86_et_zero <= !(|Y86); |
Y87_pos <= Y87; |
Y87_neg <= Y87 - 1; |
Y87_msb <= Y87[10]; |
Y87_et_zero <= !(|Y87); |
Y88_pos <= Y88; |
Y88_neg <= Y88 - 1; |
Y88_msb <= Y88[10]; |
Y88_et_zero <= !(|Y88); |
end |
else if (enable_module) begin |
Y12_pos <= Y21_pos; |
Y12_neg <= Y21_neg; |
Y12_msb <= Y21_msb; |
Y12_et_zero <= Y21_et_zero; |
Y21_pos <= Y31_pos; |
Y21_neg <= Y31_neg; |
Y21_msb <= Y31_msb; |
Y21_et_zero <= Y31_et_zero; |
Y31_pos <= Y22_pos; |
Y31_neg <= Y22_neg; |
Y31_msb <= Y22_msb; |
Y31_et_zero <= Y22_et_zero; |
Y22_pos <= Y13_pos; |
Y22_neg <= Y13_neg; |
Y22_msb <= Y13_msb; |
Y22_et_zero <= Y13_et_zero; |
Y13_pos <= Y14_pos; |
Y13_neg <= Y14_neg; |
Y13_msb <= Y14_msb; |
Y13_et_zero <= Y14_et_zero; |
Y14_pos <= Y23_pos; |
Y14_neg <= Y23_neg; |
Y14_msb <= Y23_msb; |
Y14_et_zero <= Y23_et_zero; |
Y23_pos <= Y32_pos; |
Y23_neg <= Y32_neg; |
Y23_msb <= Y32_msb; |
Y23_et_zero <= Y32_et_zero; |
Y32_pos <= Y41_pos; |
Y32_neg <= Y41_neg; |
Y32_msb <= Y41_msb; |
Y32_et_zero <= Y41_et_zero; |
Y41_pos <= Y51_pos; |
Y41_neg <= Y51_neg; |
Y41_msb <= Y51_msb; |
Y41_et_zero <= Y51_et_zero; |
Y51_pos <= Y42_pos; |
Y51_neg <= Y42_neg; |
Y51_msb <= Y42_msb; |
Y51_et_zero <= Y42_et_zero; |
Y42_pos <= Y33_pos; |
Y42_neg <= Y33_neg; |
Y42_msb <= Y33_msb; |
Y42_et_zero <= Y33_et_zero; |
Y33_pos <= Y24_pos; |
Y33_neg <= Y24_neg; |
Y33_msb <= Y24_msb; |
Y33_et_zero <= Y24_et_zero; |
Y24_pos <= Y15_pos; |
Y24_neg <= Y15_neg; |
Y24_msb <= Y15_msb; |
Y24_et_zero <= Y15_et_zero; |
Y15_pos <= Y16_pos; |
Y15_neg <= Y16_neg; |
Y15_msb <= Y16_msb; |
Y15_et_zero <= Y16_et_zero; |
Y16_pos <= Y25_pos; |
Y16_neg <= Y25_neg; |
Y16_msb <= Y25_msb; |
Y16_et_zero <= Y25_et_zero; |
Y25_pos <= Y34_pos; |
Y25_neg <= Y34_neg; |
Y25_msb <= Y34_msb; |
Y25_et_zero <= Y34_et_zero; |
Y34_pos <= Y43_pos; |
Y34_neg <= Y43_neg; |
Y34_msb <= Y43_msb; |
Y34_et_zero <= Y43_et_zero; |
Y43_pos <= Y52_pos; |
Y43_neg <= Y52_neg; |
Y43_msb <= Y52_msb; |
Y43_et_zero <= Y52_et_zero; |
Y52_pos <= Y61_pos; |
Y52_neg <= Y61_neg; |
Y52_msb <= Y61_msb; |
Y52_et_zero <= Y61_et_zero; |
Y61_pos <= Y71_pos; |
Y61_neg <= Y71_neg; |
Y61_msb <= Y71_msb; |
Y61_et_zero <= Y71_et_zero; |
Y71_pos <= Y62_pos; |
Y71_neg <= Y62_neg; |
Y71_msb <= Y62_msb; |
Y71_et_zero <= Y62_et_zero; |
Y62_pos <= Y53_pos; |
Y62_neg <= Y53_neg; |
Y62_msb <= Y53_msb; |
Y62_et_zero <= Y53_et_zero; |
Y53_pos <= Y44_pos; |
Y53_neg <= Y44_neg; |
Y53_msb <= Y44_msb; |
Y53_et_zero <= Y44_et_zero; |
Y44_pos <= Y35_pos; |
Y44_neg <= Y35_neg; |
Y44_msb <= Y35_msb; |
Y44_et_zero <= Y35_et_zero; |
Y35_pos <= Y26_pos; |
Y35_neg <= Y26_neg; |
Y35_msb <= Y26_msb; |
Y35_et_zero <= Y26_et_zero; |
Y26_pos <= Y17_pos; |
Y26_neg <= Y17_neg; |
Y26_msb <= Y17_msb; |
Y26_et_zero <= Y17_et_zero; |
Y17_pos <= Y18_pos; |
Y17_neg <= Y18_neg; |
Y17_msb <= Y18_msb; |
Y17_et_zero <= Y18_et_zero; |
Y18_pos <= Y27_pos; |
Y18_neg <= Y27_neg; |
Y18_msb <= Y27_msb; |
Y18_et_zero <= Y27_et_zero; |
Y27_pos <= Y36_pos; |
Y27_neg <= Y36_neg; |
Y27_msb <= Y36_msb; |
Y27_et_zero <= Y36_et_zero; |
Y36_pos <= Y45_pos; |
Y36_neg <= Y45_neg; |
Y36_msb <= Y45_msb; |
Y36_et_zero <= Y45_et_zero; |
Y45_pos <= Y54_pos; |
Y45_neg <= Y54_neg; |
Y45_msb <= Y54_msb; |
Y45_et_zero <= Y54_et_zero; |
Y54_pos <= Y63_pos; |
Y54_neg <= Y63_neg; |
Y54_msb <= Y63_msb; |
Y54_et_zero <= Y63_et_zero; |
Y63_pos <= Y72_pos; |
Y63_neg <= Y72_neg; |
Y63_msb <= Y72_msb; |
Y63_et_zero <= Y72_et_zero; |
Y72_pos <= Y81_pos; |
Y72_neg <= Y81_neg; |
Y72_msb <= Y81_msb; |
Y72_et_zero <= Y81_et_zero; |
Y81_pos <= Y82_pos; |
Y81_neg <= Y82_neg; |
Y81_msb <= Y82_msb; |
Y81_et_zero <= Y82_et_zero; |
Y82_pos <= Y73_pos; |
Y82_neg <= Y73_neg; |
Y82_msb <= Y73_msb; |
Y82_et_zero <= Y73_et_zero; |
Y73_pos <= Y64_pos; |
Y73_neg <= Y64_neg; |
Y73_msb <= Y64_msb; |
Y73_et_zero <= Y64_et_zero; |
Y64_pos <= Y55_pos; |
Y64_neg <= Y55_neg; |
Y64_msb <= Y55_msb; |
Y64_et_zero <= Y55_et_zero; |
Y55_pos <= Y46_pos; |
Y55_neg <= Y46_neg; |
Y55_msb <= Y46_msb; |
Y55_et_zero <= Y46_et_zero; |
Y46_pos <= Y37_pos; |
Y46_neg <= Y37_neg; |
Y46_msb <= Y37_msb; |
Y46_et_zero <= Y37_et_zero; |
Y37_pos <= Y28_pos; |
Y37_neg <= Y28_neg; |
Y37_msb <= Y28_msb; |
Y37_et_zero <= Y28_et_zero; |
Y28_pos <= Y38_pos; |
Y28_neg <= Y38_neg; |
Y28_msb <= Y38_msb; |
Y28_et_zero <= Y38_et_zero; |
Y38_pos <= Y47_pos; |
Y38_neg <= Y47_neg; |
Y38_msb <= Y47_msb; |
Y38_et_zero <= Y47_et_zero; |
Y47_pos <= Y56_pos; |
Y47_neg <= Y56_neg; |
Y47_msb <= Y56_msb; |
Y47_et_zero <= Y56_et_zero; |
Y56_pos <= Y65_pos; |
Y56_neg <= Y65_neg; |
Y56_msb <= Y65_msb; |
Y56_et_zero <= Y65_et_zero; |
Y65_pos <= Y74_pos; |
Y65_neg <= Y74_neg; |
Y65_msb <= Y74_msb; |
Y65_et_zero <= Y74_et_zero; |
Y74_pos <= Y83_pos; |
Y74_neg <= Y83_neg; |
Y74_msb <= Y83_msb; |
Y74_et_zero <= Y83_et_zero; |
Y83_pos <= Y84_pos; |
Y83_neg <= Y84_neg; |
Y83_msb <= Y84_msb; |
Y83_et_zero <= Y84_et_zero; |
Y84_pos <= Y75_pos; |
Y84_neg <= Y75_neg; |
Y84_msb <= Y75_msb; |
Y84_et_zero <= Y75_et_zero; |
Y75_pos <= Y66_pos; |
Y75_neg <= Y66_neg; |
Y75_msb <= Y66_msb; |
Y75_et_zero <= Y66_et_zero; |
Y66_pos <= Y57_pos; |
Y66_neg <= Y57_neg; |
Y66_msb <= Y57_msb; |
Y66_et_zero <= Y57_et_zero; |
Y57_pos <= Y48_pos; |
Y57_neg <= Y48_neg; |
Y57_msb <= Y48_msb; |
Y57_et_zero <= Y48_et_zero; |
Y48_pos <= Y58_pos; |
Y48_neg <= Y58_neg; |
Y48_msb <= Y58_msb; |
Y48_et_zero <= Y58_et_zero; |
Y58_pos <= Y67_pos; |
Y58_neg <= Y67_neg; |
Y58_msb <= Y67_msb; |
Y58_et_zero <= Y67_et_zero; |
Y67_pos <= Y76_pos; |
Y67_neg <= Y76_neg; |
Y67_msb <= Y76_msb; |
Y67_et_zero <= Y76_et_zero; |
Y76_pos <= Y85_pos; |
Y76_neg <= Y85_neg; |
Y76_msb <= Y85_msb; |
Y76_et_zero <= Y85_et_zero; |
Y85_pos <= Y86_pos; |
Y85_neg <= Y86_neg; |
Y85_msb <= Y86_msb; |
Y85_et_zero <= Y86_et_zero; |
Y86_pos <= Y77_pos; |
Y86_neg <= Y77_neg; |
Y86_msb <= Y77_msb; |
Y86_et_zero <= Y77_et_zero; |
Y77_pos <= Y68_pos; |
Y77_neg <= Y68_neg; |
Y77_msb <= Y68_msb; |
Y77_et_zero <= Y68_et_zero; |
Y68_pos <= Y78_pos; |
Y68_neg <= Y78_neg; |
Y68_msb <= Y78_msb; |
Y68_et_zero <= Y78_et_zero; |
Y78_pos <= Y87_pos; |
Y78_neg <= Y87_neg; |
Y78_msb <= Y87_msb; |
Y78_et_zero <= Y87_et_zero; |
Y87_pos <= Y88_pos; |
Y87_neg <= Y88_neg; |
Y87_msb <= Y88_msb; |
Y87_et_zero <= Y88_et_zero; |
Y88_pos <= 0; |
Y88_neg <= 0; |
Y88_msb <= 0; |
Y88_et_zero <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_diff <= 0; Y11_1 <= 0; |
end |
else if (enable) begin // Need to sign extend Y11 to 12 bits |
Y11_diff <= {Y11[10], Y11} - Y11_previous; |
Y11_1 <= Y11[10] ? { 1'b1, Y11 } : { 1'b0, Y11 }; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Y11_bits_pos <= 0; |
else if (Y11_1_pos[10] == 1) |
Y11_bits_pos <= 11; |
else if (Y11_1_pos[9] == 1) |
Y11_bits_pos <= 10; |
else if (Y11_1_pos[8] == 1) |
Y11_bits_pos <= 9; |
else if (Y11_1_pos[7] == 1) |
Y11_bits_pos <= 8; |
else if (Y11_1_pos[6] == 1) |
Y11_bits_pos <= 7; |
else if (Y11_1_pos[5] == 1) |
Y11_bits_pos <= 6; |
else if (Y11_1_pos[4] == 1) |
Y11_bits_pos <= 5; |
else if (Y11_1_pos[3] == 1) |
Y11_bits_pos <= 4; |
else if (Y11_1_pos[2] == 1) |
Y11_bits_pos <= 3; |
else if (Y11_1_pos[1] == 1) |
Y11_bits_pos <= 2; |
else if (Y11_1_pos[0] == 1) |
Y11_bits_pos <= 1; |
else |
Y11_bits_pos <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Y11_bits_neg <= 0; |
else if (Y11_1_neg[10] == 0) |
Y11_bits_neg <= 11; |
else if (Y11_1_neg[9] == 0) |
Y11_bits_neg <= 10; |
else if (Y11_1_neg[8] == 0) |
Y11_bits_neg <= 9; |
else if (Y11_1_neg[7] == 0) |
Y11_bits_neg <= 8; |
else if (Y11_1_neg[6] == 0) |
Y11_bits_neg <= 7; |
else if (Y11_1_neg[5] == 0) |
Y11_bits_neg <= 6; |
else if (Y11_1_neg[4] == 0) |
Y11_bits_neg <= 5; |
else if (Y11_1_neg[3] == 0) |
Y11_bits_neg <= 4; |
else if (Y11_1_neg[2] == 0) |
Y11_bits_neg <= 3; |
else if (Y11_1_neg[1] == 0) |
Y11_bits_neg <= 2; |
else if (Y11_1_neg[0] == 0) |
Y11_bits_neg <= 1; |
else |
Y11_bits_neg <= 0; |
end |
|
|
always @(posedge clk) |
begin |
if (rst) |
Y12_bits_pos <= 0; |
else if (Y12_pos[9] == 1) |
Y12_bits_pos <= 10; |
else if (Y12_pos[8] == 1) |
Y12_bits_pos <= 9; |
else if (Y12_pos[7] == 1) |
Y12_bits_pos <= 8; |
else if (Y12_pos[6] == 1) |
Y12_bits_pos <= 7; |
else if (Y12_pos[5] == 1) |
Y12_bits_pos <= 6; |
else if (Y12_pos[4] == 1) |
Y12_bits_pos <= 5; |
else if (Y12_pos[3] == 1) |
Y12_bits_pos <= 4; |
else if (Y12_pos[2] == 1) |
Y12_bits_pos <= 3; |
else if (Y12_pos[1] == 1) |
Y12_bits_pos <= 2; |
else if (Y12_pos[0] == 1) |
Y12_bits_pos <= 1; |
else |
Y12_bits_pos <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Y12_bits_neg <= 0; |
else if (Y12_neg[9] == 0) |
Y12_bits_neg <= 10; |
else if (Y12_neg[8] == 0) |
Y12_bits_neg <= 9; |
else if (Y12_neg[7] == 0) |
Y12_bits_neg <= 8; |
else if (Y12_neg[6] == 0) |
Y12_bits_neg <= 7; |
else if (Y12_neg[5] == 0) |
Y12_bits_neg <= 6; |
else if (Y12_neg[4] == 0) |
Y12_bits_neg <= 5; |
else if (Y12_neg[3] == 0) |
Y12_bits_neg <= 4; |
else if (Y12_neg[2] == 0) |
Y12_bits_neg <= 3; |
else if (Y12_neg[1] == 0) |
Y12_bits_neg <= 2; |
else if (Y12_neg[0] == 0) |
Y12_bits_neg <= 1; |
else |
Y12_bits_neg <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_module <= 0; |
end |
else if (enable) begin |
enable_module <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_latch_7 <= 0; |
end |
else if (block_counter == 68) begin |
enable_latch_7 <= 0; |
end |
else if (enable_6) begin |
enable_latch_7 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_latch_8 <= 0; |
end |
else if (enable_7) begin |
enable_latch_8 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; |
enable_4 <= 0; enable_5 <= 0; enable_6 <= 0; |
enable_7 <= 0; enable_8 <= 0; enable_9 <= 0; |
enable_10 <= 0; enable_11 <= 0; enable_12 <= 0; |
enable_13 <= 0; |
end |
else begin |
enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2; |
enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5; |
enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8; |
enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11; |
enable_13 <= enable_12; |
end |
end |
|
/* These Y DC and AC code lengths, run lengths, and bit codes |
were created from the Huffman table entries in the JPEG file header. |
For different Huffman tables for different images, these values |
below will need to be changed. I created a matlab file to automatically |
create these entries from the already encoded JPEG image. This matlab program |
won't be any help if you're starting from scratch with a .tif or other |
raw image file format. The values below come from a Huffman table, they |
do not actually create the Huffman table based on the probabilities of |
each code created from the image data. You will need another program to |
create the optimal Huffman table, or you can go with a generic Huffman table, |
which will have slightly less than the best compression.*/ |
|
|
always @(posedge clk) |
begin |
Y_DC_code_length[0] <= 2; |
Y_DC_code_length[1] <= 2; |
Y_DC_code_length[2] <= 2; |
Y_DC_code_length[3] <= 3; |
Y_DC_code_length[4] <= 4; |
Y_DC_code_length[5] <= 5; |
Y_DC_code_length[6] <= 6; |
Y_DC_code_length[7] <= 7; |
Y_DC_code_length[8] <= 8; |
Y_DC_code_length[9] <= 9; |
Y_DC_code_length[10] <= 10; |
Y_DC_code_length[11] <= 11; |
Y_DC[0] <= 11'b00000000000; |
Y_DC[1] <= 11'b01000000000; |
Y_DC[2] <= 11'b10000000000; |
Y_DC[3] <= 11'b11000000000; |
Y_DC[4] <= 11'b11100000000; |
Y_DC[5] <= 11'b11110000000; |
Y_DC[6] <= 11'b11111000000; |
Y_DC[7] <= 11'b11111100000; |
Y_DC[8] <= 11'b11111110000; |
Y_DC[9] <= 11'b11111111000; |
Y_DC[10] <= 11'b11111111100; |
Y_DC[11] <= 11'b11111111110; |
Y_AC_code_length[0] <= 2; |
Y_AC_code_length[1] <= 2; |
Y_AC_code_length[2] <= 3; |
Y_AC_code_length[3] <= 4; |
Y_AC_code_length[4] <= 4; |
Y_AC_code_length[5] <= 4; |
Y_AC_code_length[6] <= 5; |
Y_AC_code_length[7] <= 5; |
Y_AC_code_length[8] <= 5; |
Y_AC_code_length[9] <= 6; |
Y_AC_code_length[10] <= 6; |
Y_AC_code_length[11] <= 7; |
Y_AC_code_length[12] <= 7; |
Y_AC_code_length[13] <= 7; |
Y_AC_code_length[14] <= 7; |
Y_AC_code_length[15] <= 8; |
Y_AC_code_length[16] <= 8; |
Y_AC_code_length[17] <= 8; |
Y_AC_code_length[18] <= 9; |
Y_AC_code_length[19] <= 9; |
Y_AC_code_length[20] <= 9; |
Y_AC_code_length[21] <= 9; |
Y_AC_code_length[22] <= 9; |
Y_AC_code_length[23] <= 10; |
Y_AC_code_length[24] <= 10; |
Y_AC_code_length[25] <= 10; |
Y_AC_code_length[26] <= 10; |
Y_AC_code_length[27] <= 10; |
Y_AC_code_length[28] <= 11; |
Y_AC_code_length[29] <= 11; |
Y_AC_code_length[30] <= 11; |
Y_AC_code_length[31] <= 11; |
Y_AC_code_length[32] <= 12; |
Y_AC_code_length[33] <= 12; |
Y_AC_code_length[34] <= 12; |
Y_AC_code_length[35] <= 12; |
Y_AC_code_length[36] <= 15; |
Y_AC_code_length[37] <= 16; |
Y_AC_code_length[38] <= 16; |
Y_AC_code_length[39] <= 16; |
Y_AC_code_length[40] <= 16; |
Y_AC_code_length[41] <= 16; |
Y_AC_code_length[42] <= 16; |
Y_AC_code_length[43] <= 16; |
Y_AC_code_length[44] <= 16; |
Y_AC_code_length[45] <= 16; |
Y_AC_code_length[46] <= 16; |
Y_AC_code_length[47] <= 16; |
Y_AC_code_length[48] <= 16; |
Y_AC_code_length[49] <= 16; |
Y_AC_code_length[50] <= 16; |
Y_AC_code_length[51] <= 16; |
Y_AC_code_length[52] <= 16; |
Y_AC_code_length[53] <= 16; |
Y_AC_code_length[54] <= 16; |
Y_AC_code_length[55] <= 16; |
Y_AC_code_length[56] <= 16; |
Y_AC_code_length[57] <= 16; |
Y_AC_code_length[58] <= 16; |
Y_AC_code_length[59] <= 16; |
Y_AC_code_length[60] <= 16; |
Y_AC_code_length[61] <= 16; |
Y_AC_code_length[62] <= 16; |
Y_AC_code_length[63] <= 16; |
Y_AC_code_length[64] <= 16; |
Y_AC_code_length[65] <= 16; |
Y_AC_code_length[66] <= 16; |
Y_AC_code_length[67] <= 16; |
Y_AC_code_length[68] <= 16; |
Y_AC_code_length[69] <= 16; |
Y_AC_code_length[70] <= 16; |
Y_AC_code_length[71] <= 16; |
Y_AC_code_length[72] <= 16; |
Y_AC_code_length[73] <= 16; |
Y_AC_code_length[74] <= 16; |
Y_AC_code_length[75] <= 16; |
Y_AC_code_length[76] <= 16; |
Y_AC_code_length[77] <= 16; |
Y_AC_code_length[78] <= 16; |
Y_AC_code_length[79] <= 16; |
Y_AC_code_length[80] <= 16; |
Y_AC_code_length[81] <= 16; |
Y_AC_code_length[82] <= 16; |
Y_AC_code_length[83] <= 16; |
Y_AC_code_length[84] <= 16; |
Y_AC_code_length[85] <= 16; |
Y_AC_code_length[86] <= 16; |
Y_AC_code_length[87] <= 16; |
Y_AC_code_length[88] <= 16; |
Y_AC_code_length[89] <= 16; |
Y_AC_code_length[90] <= 16; |
Y_AC_code_length[91] <= 16; |
Y_AC_code_length[92] <= 16; |
Y_AC_code_length[93] <= 16; |
Y_AC_code_length[94] <= 16; |
Y_AC_code_length[95] <= 16; |
Y_AC_code_length[96] <= 16; |
Y_AC_code_length[97] <= 16; |
Y_AC_code_length[98] <= 16; |
Y_AC_code_length[99] <= 16; |
Y_AC_code_length[100] <= 16; |
Y_AC_code_length[101] <= 16; |
Y_AC_code_length[102] <= 16; |
Y_AC_code_length[103] <= 16; |
Y_AC_code_length[104] <= 16; |
Y_AC_code_length[105] <= 16; |
Y_AC_code_length[106] <= 16; |
Y_AC_code_length[107] <= 16; |
Y_AC_code_length[108] <= 16; |
Y_AC_code_length[109] <= 16; |
Y_AC_code_length[110] <= 16; |
Y_AC_code_length[111] <= 16; |
Y_AC_code_length[112] <= 16; |
Y_AC_code_length[113] <= 16; |
Y_AC_code_length[114] <= 16; |
Y_AC_code_length[115] <= 16; |
Y_AC_code_length[116] <= 16; |
Y_AC_code_length[117] <= 16; |
Y_AC_code_length[118] <= 16; |
Y_AC_code_length[119] <= 16; |
Y_AC_code_length[120] <= 16; |
Y_AC_code_length[121] <= 16; |
Y_AC_code_length[122] <= 16; |
Y_AC_code_length[123] <= 16; |
Y_AC_code_length[124] <= 16; |
Y_AC_code_length[125] <= 16; |
Y_AC_code_length[126] <= 16; |
Y_AC_code_length[127] <= 16; |
Y_AC_code_length[128] <= 16; |
Y_AC_code_length[129] <= 16; |
Y_AC_code_length[130] <= 16; |
Y_AC_code_length[131] <= 16; |
Y_AC_code_length[132] <= 16; |
Y_AC_code_length[133] <= 16; |
Y_AC_code_length[134] <= 16; |
Y_AC_code_length[135] <= 16; |
Y_AC_code_length[136] <= 16; |
Y_AC_code_length[137] <= 16; |
Y_AC_code_length[138] <= 16; |
Y_AC_code_length[139] <= 16; |
Y_AC_code_length[140] <= 16; |
Y_AC_code_length[141] <= 16; |
Y_AC_code_length[142] <= 16; |
Y_AC_code_length[143] <= 16; |
Y_AC_code_length[144] <= 16; |
Y_AC_code_length[145] <= 16; |
Y_AC_code_length[146] <= 16; |
Y_AC_code_length[147] <= 16; |
Y_AC_code_length[148] <= 16; |
Y_AC_code_length[149] <= 16; |
Y_AC_code_length[150] <= 16; |
Y_AC_code_length[151] <= 16; |
Y_AC_code_length[152] <= 16; |
Y_AC_code_length[153] <= 16; |
Y_AC_code_length[154] <= 16; |
Y_AC_code_length[155] <= 16; |
Y_AC_code_length[156] <= 16; |
Y_AC_code_length[157] <= 16; |
Y_AC_code_length[158] <= 16; |
Y_AC_code_length[159] <= 16; |
Y_AC_code_length[160] <= 16; |
Y_AC_code_length[161] <= 16; |
Y_AC[0] <= 16'b0000000000000000; |
Y_AC[1] <= 16'b0100000000000000; |
Y_AC[2] <= 16'b1000000000000000; |
Y_AC[3] <= 16'b1010000000000000; |
Y_AC[4] <= 16'b1011000000000000; |
Y_AC[5] <= 16'b1100000000000000; |
Y_AC[6] <= 16'b1101000000000000; |
Y_AC[7] <= 16'b1101100000000000; |
Y_AC[8] <= 16'b1110000000000000; |
Y_AC[9] <= 16'b1110100000000000; |
Y_AC[10] <= 16'b1110110000000000; |
Y_AC[11] <= 16'b1111000000000000; |
Y_AC[12] <= 16'b1111001000000000; |
Y_AC[13] <= 16'b1111010000000000; |
Y_AC[14] <= 16'b1111011000000000; |
Y_AC[15] <= 16'b1111100000000000; |
Y_AC[16] <= 16'b1111100100000000; |
Y_AC[17] <= 16'b1111101000000000; |
Y_AC[18] <= 16'b1111101100000000; |
Y_AC[19] <= 16'b1111101110000000; |
Y_AC[20] <= 16'b1111110000000000; |
Y_AC[21] <= 16'b1111110010000000; |
Y_AC[22] <= 16'b1111110100000000; |
Y_AC[23] <= 16'b1111110110000000; |
Y_AC[24] <= 16'b1111110111000000; |
Y_AC[25] <= 16'b1111111000000000; |
Y_AC[26] <= 16'b1111111001000000; |
Y_AC[27] <= 16'b1111111010000000; |
Y_AC[28] <= 16'b1111111011000000; |
Y_AC[29] <= 16'b1111111011100000; |
Y_AC[30] <= 16'b1111111100000000; |
Y_AC[31] <= 16'b1111111100100000; |
Y_AC[32] <= 16'b1111111101000000; |
Y_AC[33] <= 16'b1111111101010000; |
Y_AC[34] <= 16'b1111111101100000; |
Y_AC[35] <= 16'b1111111101110000; |
Y_AC[36] <= 16'b1111111110000000; |
Y_AC[37] <= 16'b1111111110000010; |
Y_AC[38] <= 16'b1111111110000011; |
Y_AC[39] <= 16'b1111111110000100; |
Y_AC[40] <= 16'b1111111110000101; |
Y_AC[41] <= 16'b1111111110000110; |
Y_AC[42] <= 16'b1111111110000111; |
Y_AC[43] <= 16'b1111111110001000; |
Y_AC[44] <= 16'b1111111110001001; |
Y_AC[45] <= 16'b1111111110001010; |
Y_AC[46] <= 16'b1111111110001011; |
Y_AC[47] <= 16'b1111111110001100; |
Y_AC[48] <= 16'b1111111110001101; |
Y_AC[49] <= 16'b1111111110001110; |
Y_AC[50] <= 16'b1111111110001111; |
Y_AC[51] <= 16'b1111111110010000; |
Y_AC[52] <= 16'b1111111110010001; |
Y_AC[53] <= 16'b1111111110010010; |
Y_AC[54] <= 16'b1111111110010011; |
Y_AC[55] <= 16'b1111111110010100; |
Y_AC[56] <= 16'b1111111110010101; |
Y_AC[57] <= 16'b1111111110010110; |
Y_AC[58] <= 16'b1111111110010111; |
Y_AC[59] <= 16'b1111111110011000; |
Y_AC[60] <= 16'b1111111110011001; |
Y_AC[61] <= 16'b1111111110011010; |
Y_AC[62] <= 16'b1111111110011011; |
Y_AC[63] <= 16'b1111111110011100; |
Y_AC[64] <= 16'b1111111110011101; |
Y_AC[65] <= 16'b1111111110011110; |
Y_AC[66] <= 16'b1111111110011111; |
Y_AC[67] <= 16'b1111111110100000; |
Y_AC[68] <= 16'b1111111110100001; |
Y_AC[69] <= 16'b1111111110100010; |
Y_AC[70] <= 16'b1111111110100011; |
Y_AC[71] <= 16'b1111111110100100; |
Y_AC[72] <= 16'b1111111110100101; |
Y_AC[73] <= 16'b1111111110100110; |
Y_AC[74] <= 16'b1111111110100111; |
Y_AC[75] <= 16'b1111111110101000; |
Y_AC[76] <= 16'b1111111110101001; |
Y_AC[77] <= 16'b1111111110101010; |
Y_AC[78] <= 16'b1111111110101011; |
Y_AC[79] <= 16'b1111111110101100; |
Y_AC[80] <= 16'b1111111110101101; |
Y_AC[81] <= 16'b1111111110101110; |
Y_AC[82] <= 16'b1111111110101111; |
Y_AC[83] <= 16'b1111111110110000; |
Y_AC[84] <= 16'b1111111110110001; |
Y_AC[85] <= 16'b1111111110110010; |
Y_AC[86] <= 16'b1111111110110011; |
Y_AC[87] <= 16'b1111111110110100; |
Y_AC[88] <= 16'b1111111110110101; |
Y_AC[89] <= 16'b1111111110110110; |
Y_AC[90] <= 16'b1111111110110111; |
Y_AC[91] <= 16'b1111111110111000; |
Y_AC[92] <= 16'b1111111110111001; |
Y_AC[93] <= 16'b1111111110111010; |
Y_AC[94] <= 16'b1111111110111011; |
Y_AC[95] <= 16'b1111111110111100; |
Y_AC[96] <= 16'b1111111110111101; |
Y_AC[97] <= 16'b1111111110111110; |
Y_AC[98] <= 16'b1111111110111111; |
Y_AC[99] <= 16'b1111111111000000; |
Y_AC[100] <= 16'b1111111111000001; |
Y_AC[101] <= 16'b1111111111000010; |
Y_AC[102] <= 16'b1111111111000011; |
Y_AC[103] <= 16'b1111111111000100; |
Y_AC[104] <= 16'b1111111111000101; |
Y_AC[105] <= 16'b1111111111000110; |
Y_AC[106] <= 16'b1111111111000111; |
Y_AC[107] <= 16'b1111111111001000; |
Y_AC[108] <= 16'b1111111111001001; |
Y_AC[109] <= 16'b1111111111001010; |
Y_AC[110] <= 16'b1111111111001011; |
Y_AC[111] <= 16'b1111111111001100; |
Y_AC[112] <= 16'b1111111111001101; |
Y_AC[113] <= 16'b1111111111001110; |
Y_AC[114] <= 16'b1111111111001111; |
Y_AC[115] <= 16'b1111111111010000; |
Y_AC[116] <= 16'b1111111111010001; |
Y_AC[117] <= 16'b1111111111010010; |
Y_AC[118] <= 16'b1111111111010011; |
Y_AC[119] <= 16'b1111111111010100; |
Y_AC[120] <= 16'b1111111111010101; |
Y_AC[121] <= 16'b1111111111010110; |
Y_AC[122] <= 16'b1111111111010111; |
Y_AC[123] <= 16'b1111111111011000; |
Y_AC[124] <= 16'b1111111111011001; |
Y_AC[125] <= 16'b1111111111011010; |
Y_AC[126] <= 16'b1111111111011011; |
Y_AC[127] <= 16'b1111111111011100; |
Y_AC[128] <= 16'b1111111111011101; |
Y_AC[129] <= 16'b1111111111011110; |
Y_AC[130] <= 16'b1111111111011111; |
Y_AC[131] <= 16'b1111111111100000; |
Y_AC[132] <= 16'b1111111111100001; |
Y_AC[133] <= 16'b1111111111100010; |
Y_AC[134] <= 16'b1111111111100011; |
Y_AC[135] <= 16'b1111111111100100; |
Y_AC[136] <= 16'b1111111111100101; |
Y_AC[137] <= 16'b1111111111100110; |
Y_AC[138] <= 16'b1111111111100111; |
Y_AC[139] <= 16'b1111111111101000; |
Y_AC[140] <= 16'b1111111111101001; |
Y_AC[141] <= 16'b1111111111101010; |
Y_AC[142] <= 16'b1111111111101011; |
Y_AC[143] <= 16'b1111111111101100; |
Y_AC[144] <= 16'b1111111111101101; |
Y_AC[145] <= 16'b1111111111101110; |
Y_AC[146] <= 16'b1111111111101111; |
Y_AC[147] <= 16'b1111111111110000; |
Y_AC[148] <= 16'b1111111111110001; |
Y_AC[149] <= 16'b1111111111110010; |
Y_AC[150] <= 16'b1111111111110011; |
Y_AC[151] <= 16'b1111111111110100; |
Y_AC[152] <= 16'b1111111111110101; |
Y_AC[153] <= 16'b1111111111110110; |
Y_AC[154] <= 16'b1111111111110111; |
Y_AC[155] <= 16'b1111111111111000; |
Y_AC[156] <= 16'b1111111111111001; |
Y_AC[157] <= 16'b1111111111111010; |
Y_AC[158] <= 16'b1111111111111011; |
Y_AC[159] <= 16'b1111111111111100; |
Y_AC[160] <= 16'b1111111111111101; |
Y_AC[161] <= 16'b1111111111111110; |
Y_AC_run_code[1] <= 0; |
Y_AC_run_code[2] <= 1; |
Y_AC_run_code[3] <= 2; |
Y_AC_run_code[0] <= 3; |
Y_AC_run_code[4] <= 4; |
Y_AC_run_code[17] <= 5; |
Y_AC_run_code[5] <= 6; |
Y_AC_run_code[18] <= 7; |
Y_AC_run_code[33] <= 8; |
Y_AC_run_code[49] <= 9; |
Y_AC_run_code[65] <= 10; |
Y_AC_run_code[6] <= 11; |
Y_AC_run_code[19] <= 12; |
Y_AC_run_code[81] <= 13; |
Y_AC_run_code[97] <= 14; |
Y_AC_run_code[7] <= 15; |
Y_AC_run_code[34] <= 16; |
Y_AC_run_code[113] <= 17; |
Y_AC_run_code[20] <= 18; |
Y_AC_run_code[50] <= 19; |
Y_AC_run_code[129] <= 20; |
Y_AC_run_code[145] <= 21; |
Y_AC_run_code[161] <= 22; |
Y_AC_run_code[8] <= 23; |
Y_AC_run_code[35] <= 24; |
Y_AC_run_code[66] <= 25; |
Y_AC_run_code[177] <= 26; |
Y_AC_run_code[193] <= 27; |
Y_AC_run_code[21] <= 28; |
Y_AC_run_code[82] <= 29; |
Y_AC_run_code[209] <= 30; |
Y_AC_run_code[240] <= 31; |
Y_AC_run_code[36] <= 32; |
Y_AC_run_code[51] <= 33; |
Y_AC_run_code[98] <= 34; |
Y_AC_run_code[114] <= 35; |
Y_AC_run_code[130] <= 36; |
Y_AC_run_code[9] <= 37; |
Y_AC_run_code[10] <= 38; |
Y_AC_run_code[22] <= 39; |
Y_AC_run_code[23] <= 40; |
Y_AC_run_code[24] <= 41; |
Y_AC_run_code[25] <= 42; |
Y_AC_run_code[26] <= 43; |
Y_AC_run_code[37] <= 44; |
Y_AC_run_code[38] <= 45; |
Y_AC_run_code[39] <= 46; |
Y_AC_run_code[40] <= 47; |
Y_AC_run_code[41] <= 48; |
Y_AC_run_code[42] <= 49; |
Y_AC_run_code[52] <= 50; |
Y_AC_run_code[53] <= 51; |
Y_AC_run_code[54] <= 52; |
Y_AC_run_code[55] <= 53; |
Y_AC_run_code[56] <= 54; |
Y_AC_run_code[57] <= 55; |
Y_AC_run_code[58] <= 56; |
Y_AC_run_code[67] <= 57; |
Y_AC_run_code[68] <= 58; |
Y_AC_run_code[69] <= 59; |
Y_AC_run_code[70] <= 60; |
Y_AC_run_code[71] <= 61; |
Y_AC_run_code[72] <= 62; |
Y_AC_run_code[73] <= 63; |
Y_AC_run_code[74] <= 64; |
Y_AC_run_code[83] <= 65; |
Y_AC_run_code[84] <= 66; |
Y_AC_run_code[85] <= 67; |
Y_AC_run_code[86] <= 68; |
Y_AC_run_code[87] <= 69; |
Y_AC_run_code[88] <= 70; |
Y_AC_run_code[89] <= 71; |
Y_AC_run_code[90] <= 72; |
Y_AC_run_code[99] <= 73; |
Y_AC_run_code[100] <= 74; |
Y_AC_run_code[101] <= 75; |
Y_AC_run_code[102] <= 76; |
Y_AC_run_code[103] <= 77; |
Y_AC_run_code[104] <= 78; |
Y_AC_run_code[105] <= 79; |
Y_AC_run_code[106] <= 80; |
Y_AC_run_code[115] <= 81; |
Y_AC_run_code[116] <= 82; |
Y_AC_run_code[117] <= 83; |
Y_AC_run_code[118] <= 84; |
Y_AC_run_code[119] <= 85; |
Y_AC_run_code[120] <= 86; |
Y_AC_run_code[121] <= 87; |
Y_AC_run_code[122] <= 88; |
Y_AC_run_code[131] <= 89; |
Y_AC_run_code[132] <= 90; |
Y_AC_run_code[133] <= 91; |
Y_AC_run_code[134] <= 92; |
Y_AC_run_code[135] <= 93; |
Y_AC_run_code[136] <= 94; |
Y_AC_run_code[137] <= 95; |
Y_AC_run_code[138] <= 96; |
Y_AC_run_code[146] <= 97; |
Y_AC_run_code[147] <= 98; |
Y_AC_run_code[148] <= 99; |
Y_AC_run_code[149] <= 100; |
Y_AC_run_code[150] <= 101; |
Y_AC_run_code[151] <= 102; |
Y_AC_run_code[152] <= 103; |
Y_AC_run_code[153] <= 104; |
Y_AC_run_code[154] <= 105; |
Y_AC_run_code[162] <= 106; |
Y_AC_run_code[163] <= 107; |
Y_AC_run_code[164] <= 108; |
Y_AC_run_code[165] <= 109; |
Y_AC_run_code[166] <= 110; |
Y_AC_run_code[167] <= 111; |
Y_AC_run_code[168] <= 112; |
Y_AC_run_code[169] <= 113; |
Y_AC_run_code[170] <= 114; |
Y_AC_run_code[178] <= 115; |
Y_AC_run_code[179] <= 116; |
Y_AC_run_code[180] <= 117; |
Y_AC_run_code[181] <= 118; |
Y_AC_run_code[182] <= 119; |
Y_AC_run_code[183] <= 120; |
Y_AC_run_code[184] <= 121; |
Y_AC_run_code[185] <= 122; |
Y_AC_run_code[186] <= 123; |
Y_AC_run_code[194] <= 124; |
Y_AC_run_code[195] <= 125; |
Y_AC_run_code[196] <= 126; |
Y_AC_run_code[197] <= 127; |
Y_AC_run_code[198] <= 128; |
Y_AC_run_code[199] <= 129; |
Y_AC_run_code[200] <= 130; |
Y_AC_run_code[201] <= 131; |
Y_AC_run_code[202] <= 132; |
Y_AC_run_code[210] <= 133; |
Y_AC_run_code[211] <= 134; |
Y_AC_run_code[212] <= 135; |
Y_AC_run_code[213] <= 136; |
Y_AC_run_code[214] <= 137; |
Y_AC_run_code[215] <= 138; |
Y_AC_run_code[216] <= 139; |
Y_AC_run_code[217] <= 140; |
Y_AC_run_code[218] <= 141; |
Y_AC_run_code[225] <= 142; |
Y_AC_run_code[226] <= 143; |
Y_AC_run_code[227] <= 144; |
Y_AC_run_code[228] <= 145; |
Y_AC_run_code[229] <= 146; |
Y_AC_run_code[230] <= 147; |
Y_AC_run_code[231] <= 148; |
Y_AC_run_code[232] <= 149; |
Y_AC_run_code[233] <= 150; |
Y_AC_run_code[234] <= 151; |
Y_AC_run_code[241] <= 152; |
Y_AC_run_code[242] <= 153; |
Y_AC_run_code[243] <= 154; |
Y_AC_run_code[244] <= 155; |
Y_AC_run_code[245] <= 156; |
Y_AC_run_code[246] <= 157; |
Y_AC_run_code[247] <= 158; |
Y_AC_run_code[248] <= 159; |
Y_AC_run_code[249] <= 160; |
Y_AC_run_code[250] <= 161; |
Y_AC_run_code[16] <= 0; |
Y_AC_run_code[32] <= 0; |
Y_AC_run_code[48] <= 0; |
Y_AC_run_code[64] <= 0; |
Y_AC_run_code[80] <= 0; |
Y_AC_run_code[96] <= 0; |
Y_AC_run_code[112] <= 0; |
Y_AC_run_code[128] <= 0; |
Y_AC_run_code[144] <= 0; |
Y_AC_run_code[160] <= 0; |
Y_AC_run_code[176] <= 0; |
Y_AC_run_code[192] <= 0; |
Y_AC_run_code[208] <= 0; |
Y_AC_run_code[224] <= 0; |
end |
|
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[31] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[31] <= JPEG_bs_5[31]; |
else if (enable_module && orc_8 == 0) |
JPEG_bitstream[31] <= JPEG_bs_5[31]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[30] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[30] <= JPEG_bs_5[30]; |
else if (enable_module && orc_8 <= 1) |
JPEG_bitstream[30] <= JPEG_bs_5[30]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[29] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[29] <= JPEG_bs_5[29]; |
else if (enable_module && orc_8 <= 2) |
JPEG_bitstream[29] <= JPEG_bs_5[29]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[28] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[28] <= JPEG_bs_5[28]; |
else if (enable_module && orc_8 <= 3) |
JPEG_bitstream[28] <= JPEG_bs_5[28]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[27] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[27] <= JPEG_bs_5[27]; |
else if (enable_module && orc_8 <= 4) |
JPEG_bitstream[27] <= JPEG_bs_5[27]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[26] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[26] <= JPEG_bs_5[26]; |
else if (enable_module && orc_8 <= 5) |
JPEG_bitstream[26] <= JPEG_bs_5[26]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[25] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[25] <= JPEG_bs_5[25]; |
else if (enable_module && orc_8 <= 6) |
JPEG_bitstream[25] <= JPEG_bs_5[25]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[24] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[24] <= JPEG_bs_5[24]; |
else if (enable_module && orc_8 <= 7) |
JPEG_bitstream[24] <= JPEG_bs_5[24]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[23] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[23] <= JPEG_bs_5[23]; |
else if (enable_module && orc_8 <= 8) |
JPEG_bitstream[23] <= JPEG_bs_5[23]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[22] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[22] <= JPEG_bs_5[22]; |
else if (enable_module && orc_8 <= 9) |
JPEG_bitstream[22] <= JPEG_bs_5[22]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[21] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[21] <= JPEG_bs_5[21]; |
else if (enable_module && orc_8 <= 10) |
JPEG_bitstream[21] <= JPEG_bs_5[21]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[20] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[20] <= JPEG_bs_5[20]; |
else if (enable_module && orc_8 <= 11) |
JPEG_bitstream[20] <= JPEG_bs_5[20]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[19] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[19] <= JPEG_bs_5[19]; |
else if (enable_module && orc_8 <= 12) |
JPEG_bitstream[19] <= JPEG_bs_5[19]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[18] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[18] <= JPEG_bs_5[18]; |
else if (enable_module && orc_8 <= 13) |
JPEG_bitstream[18] <= JPEG_bs_5[18]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[17] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[17] <= JPEG_bs_5[17]; |
else if (enable_module && orc_8 <= 14) |
JPEG_bitstream[17] <= JPEG_bs_5[17]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[16] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[16] <= JPEG_bs_5[16]; |
else if (enable_module && orc_8 <= 15) |
JPEG_bitstream[16] <= JPEG_bs_5[16]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[15] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[15] <= JPEG_bs_5[15]; |
else if (enable_module && orc_8 <= 16) |
JPEG_bitstream[15] <= JPEG_bs_5[15]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[14] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[14] <= JPEG_bs_5[14]; |
else if (enable_module && orc_8 <= 17) |
JPEG_bitstream[14] <= JPEG_bs_5[14]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[13] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[13] <= JPEG_bs_5[13]; |
else if (enable_module && orc_8 <= 18) |
JPEG_bitstream[13] <= JPEG_bs_5[13]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[12] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[12] <= JPEG_bs_5[12]; |
else if (enable_module && orc_8 <= 19) |
JPEG_bitstream[12] <= JPEG_bs_5[12]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[11] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[11] <= JPEG_bs_5[11]; |
else if (enable_module && orc_8 <= 20) |
JPEG_bitstream[11] <= JPEG_bs_5[11]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[10] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[10] <= JPEG_bs_5[10]; |
else if (enable_module && orc_8 <= 21) |
JPEG_bitstream[10] <= JPEG_bs_5[10]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[9] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[9] <= JPEG_bs_5[9]; |
else if (enable_module && orc_8 <= 22) |
JPEG_bitstream[9] <= JPEG_bs_5[9]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[8] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[8] <= JPEG_bs_5[8]; |
else if (enable_module && orc_8 <= 23) |
JPEG_bitstream[8] <= JPEG_bs_5[8]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[7] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[7] <= JPEG_bs_5[7]; |
else if (enable_module && orc_8 <= 24) |
JPEG_bitstream[7] <= JPEG_bs_5[7]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[6] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[6] <= JPEG_bs_5[6]; |
else if (enable_module && orc_8 <= 25) |
JPEG_bitstream[6] <= JPEG_bs_5[6]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[5] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[5] <= JPEG_bs_5[5]; |
else if (enable_module && orc_8 <= 26) |
JPEG_bitstream[5] <= JPEG_bs_5[5]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[4] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[4] <= JPEG_bs_5[4]; |
else if (enable_module && orc_8 <= 27) |
JPEG_bitstream[4] <= JPEG_bs_5[4]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[3] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[3] <= JPEG_bs_5[3]; |
else if (enable_module && orc_8 <= 28) |
JPEG_bitstream[3] <= JPEG_bs_5[3]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[2] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[2] <= JPEG_bs_5[2]; |
else if (enable_module && orc_8 <= 29) |
JPEG_bitstream[2] <= JPEG_bs_5[2]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[1] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[1] <= JPEG_bs_5[1]; |
else if (enable_module && orc_8 <= 30) |
JPEG_bitstream[1] <= JPEG_bs_5[1]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[0] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[0] <= JPEG_bs_5[0]; |
else if (enable_module && orc_8 <= 31) |
JPEG_bitstream[0] <= JPEG_bs_5[0]; |
end |
endmodule |
/jpegencode/trunk/sync_fifo_32.v
0,0 → 1,97
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
`timescale 1ns / 100ps |
|
module sync_fifo_32 (clk, rst, read_req, write_data, write_enable, |
read_data, fifo_empty, rdata_valid); |
input clk; |
input rst; |
input read_req; |
input [31:0] write_data; |
input write_enable; |
output [31:0] read_data; |
output fifo_empty; |
output rdata_valid; |
|
reg [4:0] read_ptr; |
reg [4:0] write_ptr; |
reg [31:0] mem [0:15]; |
reg [31:0] read_data; |
reg rdata_valid; |
wire [3:0] write_addr = write_ptr[3:0]; |
wire [3:0] read_addr = read_ptr[3:0]; |
wire read_enable = read_req && (~fifo_empty); |
assign fifo_empty = (read_ptr == write_ptr); |
|
|
always @(posedge clk) |
begin |
if (rst) |
write_ptr <= {(5){1'b0}}; |
else if (write_enable) |
write_ptr <= write_ptr + {{4{1'b0}},1'b1}; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
rdata_valid <= 1'b0; |
else if (read_enable) |
rdata_valid <= 1'b1; |
else |
rdata_valid <= 1'b0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
read_ptr <= {(5){1'b0}}; |
else if (read_enable) |
read_ptr <= read_ptr + {{4{1'b0}},1'b1}; |
end |
|
// Mem write |
always @(posedge clk) |
begin |
if (write_enable) |
mem[write_addr] <= write_data; |
end |
// Mem Read |
always @(posedge clk) |
begin |
if (read_enable) |
read_data <= mem[read_addr]; |
end |
|
endmodule |
/jpegencode/trunk/cb_quantizer.v
0,0 → 1,631
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module comes after the dct module. The 64 matrix entries calculated after |
performing the 2D DCT are inputs to this quantization module. This module quantizes |
the entire 8x8 block of Cb values. The outputs from this module |
are the quantized Cb values for one 8x8 block. */ |
|
`timescale 1ns / 100ps |
|
module cb_quantizer(clk, rst, enable, |
Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, |
Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, |
Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68, |
Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88, |
Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, |
Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, |
Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68, |
Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88, |
out_enable); |
input clk; |
input rst; |
input enable; |
input [10:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24; |
input [10:0] Z25, Z26, Z27, Z28, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38; |
input [10:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z51, Z52, Z53, Z54; |
input [10:0] Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68; |
input [10:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84; |
input [10:0] Z85, Z86, Z87, Z88; |
output [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24; |
output [10:0] Q25, Q26, Q27, Q28, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
output [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q51, Q52, Q53, Q54; |
output [10:0] Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
output [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84; |
output [10:0] Q85, Q86, Q87, Q88; |
output out_enable; |
|
/* Below are the quantization values, these can be changed for different |
quantization levels. */ |
|
|
parameter Q1_1 = 1; |
parameter Q1_2 = 1; |
parameter Q1_3 = 1; |
parameter Q1_4 = 1; |
parameter Q1_5 = 1; |
parameter Q1_6 = 1; |
parameter Q1_7 = 1; |
parameter Q1_8 = 1; |
parameter Q2_1 = 1; |
parameter Q2_2 = 1; |
parameter Q2_3 = 1; |
parameter Q2_4 = 1; |
parameter Q2_5 = 1; |
parameter Q2_6 = 1; |
parameter Q2_7 = 1; |
parameter Q2_8 = 1; |
parameter Q3_1 = 1; |
parameter Q3_2 = 1; |
parameter Q3_3 = 1; |
parameter Q3_4 = 1; |
parameter Q3_5 = 1; |
parameter Q3_6 = 1; |
parameter Q3_7 = 1; |
parameter Q3_8 = 1; |
parameter Q4_1 = 1; |
parameter Q4_2 = 1; |
parameter Q4_3 = 1; |
parameter Q4_4 = 1; |
parameter Q4_5 = 1; |
parameter Q4_6 = 1; |
parameter Q4_7 = 1; |
parameter Q4_8 = 1; |
parameter Q5_1 = 1; |
parameter Q5_2 = 1; |
parameter Q5_3 = 1; |
parameter Q5_4 = 1; |
parameter Q5_5 = 1; |
parameter Q5_6 = 1; |
parameter Q5_7 = 1; |
parameter Q5_8 = 1; |
parameter Q6_1 = 1; |
parameter Q6_2 = 1; |
parameter Q6_3 = 1; |
parameter Q6_4 = 1; |
parameter Q6_5 = 1; |
parameter Q6_6 = 1; |
parameter Q6_7 = 1; |
parameter Q6_8 = 1; |
parameter Q7_1 = 1; |
parameter Q7_2 = 1; |
parameter Q7_3 = 1; |
parameter Q7_4 = 1; |
parameter Q7_5 = 1; |
parameter Q7_6 = 1; |
parameter Q7_7 = 1; |
parameter Q7_8 = 1; |
parameter Q8_1 = 1; |
parameter Q8_2 = 1; |
parameter Q8_3 = 1; |
parameter Q8_4 = 1; |
parameter Q8_5 = 1; |
parameter Q8_6 = 1; |
parameter Q8_7 = 1; |
parameter Q8_8 = 1; |
|
// End of Quantization Values |
|
/* The following parameters hold the values of 4096 divided by the corresponding |
individual quantization values. These values are needed to get around |
actually dividing the Y, Cb, and Cr values by the quantization values. |
Instead, you can multiply by the values below, and then divide by 4096 |
to get the same result. And 4096 = 2^12, so instead of dividing, you can |
just shift the bottom 12 bits out. This is a lossy process, as 4096/Q divided |
by 4096 doesn't always equal the same value as if you were just dividing by Q. But |
the quantization process is also lossy, so the additional loss of precision is |
negligible. To decrease the loss, you could use a larger number than 4096 to |
get around the actual use of division. Like take 8192/Q and then divide by 8192.*/ |
|
parameter QQ1_1 = 4096/Q1_1; |
parameter QQ1_2 = 4096/Q1_2; |
parameter QQ1_3 = 4096/Q1_3; |
parameter QQ1_4 = 4096/Q1_4; |
parameter QQ1_5 = 4096/Q1_5; |
parameter QQ1_6 = 4096/Q1_6; |
parameter QQ1_7 = 4096/Q1_7; |
parameter QQ1_8 = 4096/Q1_8; |
parameter QQ2_1 = 4096/Q2_1; |
parameter QQ2_2 = 4096/Q2_2; |
parameter QQ2_3 = 4096/Q2_3; |
parameter QQ2_4 = 4096/Q2_4; |
parameter QQ2_5 = 4096/Q2_5; |
parameter QQ2_6 = 4096/Q2_6; |
parameter QQ2_7 = 4096/Q2_7; |
parameter QQ2_8 = 4096/Q2_8; |
parameter QQ3_1 = 4096/Q3_1; |
parameter QQ3_2 = 4096/Q3_2; |
parameter QQ3_3 = 4096/Q3_3; |
parameter QQ3_4 = 4096/Q3_4; |
parameter QQ3_5 = 4096/Q3_5; |
parameter QQ3_6 = 4096/Q3_6; |
parameter QQ3_7 = 4096/Q3_7; |
parameter QQ3_8 = 4096/Q3_8; |
parameter QQ4_1 = 4096/Q4_1; |
parameter QQ4_2 = 4096/Q4_2; |
parameter QQ4_3 = 4096/Q4_3; |
parameter QQ4_4 = 4096/Q4_4; |
parameter QQ4_5 = 4096/Q4_5; |
parameter QQ4_6 = 4096/Q4_6; |
parameter QQ4_7 = 4096/Q4_7; |
parameter QQ4_8 = 4096/Q4_8; |
parameter QQ5_1 = 4096/Q5_1; |
parameter QQ5_2 = 4096/Q5_2; |
parameter QQ5_3 = 4096/Q5_3; |
parameter QQ5_4 = 4096/Q5_4; |
parameter QQ5_5 = 4096/Q5_5; |
parameter QQ5_6 = 4096/Q5_6; |
parameter QQ5_7 = 4096/Q5_7; |
parameter QQ5_8 = 4096/Q5_8; |
parameter QQ6_1 = 4096/Q6_1; |
parameter QQ6_2 = 4096/Q6_2; |
parameter QQ6_3 = 4096/Q6_3; |
parameter QQ6_4 = 4096/Q6_4; |
parameter QQ6_5 = 4096/Q6_5; |
parameter QQ6_6 = 4096/Q6_6; |
parameter QQ6_7 = 4096/Q6_7; |
parameter QQ6_8 = 4096/Q6_8; |
parameter QQ7_1 = 4096/Q7_1; |
parameter QQ7_2 = 4096/Q7_2; |
parameter QQ7_3 = 4096/Q7_3; |
parameter QQ7_4 = 4096/Q7_4; |
parameter QQ7_5 = 4096/Q7_5; |
parameter QQ7_6 = 4096/Q7_6; |
parameter QQ7_7 = 4096/Q7_7; |
parameter QQ7_8 = 4096/Q7_8; |
parameter QQ8_1 = 4096/Q8_1; |
parameter QQ8_2 = 4096/Q8_2; |
parameter QQ8_3 = 4096/Q8_3; |
parameter QQ8_4 = 4096/Q8_4; |
parameter QQ8_5 = 4096/Q8_5; |
parameter QQ8_6 = 4096/Q8_6; |
parameter QQ8_7 = 4096/Q8_7; |
parameter QQ8_8 = 4096/Q8_8; |
|
wire [12:0] QM1_1 = QQ1_1; |
wire [12:0] QM1_2 = QQ1_2; |
wire [12:0] QM1_3 = QQ1_3; |
wire [12:0] QM1_4 = QQ1_4; |
wire [12:0] QM1_5 = QQ1_5; |
wire [12:0] QM1_6 = QQ1_6; |
wire [12:0] QM1_7 = QQ1_7; |
wire [12:0] QM1_8 = QQ1_8; |
wire [12:0] QM2_1 = QQ2_1; |
wire [12:0] QM2_2 = QQ2_2; |
wire [12:0] QM2_3 = QQ2_3; |
wire [12:0] QM2_4 = QQ2_4; |
wire [12:0] QM2_5 = QQ2_5; |
wire [12:0] QM2_6 = QQ2_6; |
wire [12:0] QM2_7 = QQ2_7; |
wire [12:0] QM2_8 = QQ2_8; |
wire [12:0] QM3_1 = QQ3_1; |
wire [12:0] QM3_2 = QQ3_2; |
wire [12:0] QM3_3 = QQ3_3; |
wire [12:0] QM3_4 = QQ3_4; |
wire [12:0] QM3_5 = QQ3_5; |
wire [12:0] QM3_6 = QQ3_6; |
wire [12:0] QM3_7 = QQ3_7; |
wire [12:0] QM3_8 = QQ3_8; |
wire [12:0] QM4_1 = QQ4_1; |
wire [12:0] QM4_2 = QQ4_2; |
wire [12:0] QM4_3 = QQ4_3; |
wire [12:0] QM4_4 = QQ4_4; |
wire [12:0] QM4_5 = QQ4_5; |
wire [12:0] QM4_6 = QQ4_6; |
wire [12:0] QM4_7 = QQ4_7; |
wire [12:0] QM4_8 = QQ4_8; |
wire [12:0] QM5_1 = QQ5_1; |
wire [12:0] QM5_2 = QQ5_2; |
wire [12:0] QM5_3 = QQ5_3; |
wire [12:0] QM5_4 = QQ5_4; |
wire [12:0] QM5_5 = QQ5_5; |
wire [12:0] QM5_6 = QQ5_6; |
wire [12:0] QM5_7 = QQ5_7; |
wire [12:0] QM5_8 = QQ5_8; |
wire [12:0] QM6_1 = QQ6_1; |
wire [12:0] QM6_2 = QQ6_2; |
wire [12:0] QM6_3 = QQ6_3; |
wire [12:0] QM6_4 = QQ6_4; |
wire [12:0] QM6_5 = QQ6_5; |
wire [12:0] QM6_6 = QQ6_6; |
wire [12:0] QM6_7 = QQ6_7; |
wire [12:0] QM6_8 = QQ6_8; |
wire [12:0] QM7_1 = QQ7_1; |
wire [12:0] QM7_2 = QQ7_2; |
wire [12:0] QM7_3 = QQ7_3; |
wire [12:0] QM7_4 = QQ7_4; |
wire [12:0] QM7_5 = QQ7_5; |
wire [12:0] QM7_6 = QQ7_6; |
wire [12:0] QM7_7 = QQ7_7; |
wire [12:0] QM7_8 = QQ7_8; |
wire [12:0] QM8_1 = QQ8_1; |
wire [12:0] QM8_2 = QQ8_2; |
wire [12:0] QM8_3 = QQ8_3; |
wire [12:0] QM8_4 = QQ8_4; |
wire [12:0] QM8_5 = QQ8_5; |
wire [12:0] QM8_6 = QQ8_6; |
wire [12:0] QM8_7 = QQ8_7; |
wire [12:0] QM8_8 = QQ8_8; |
reg [22:0] Z11_temp, Z12_temp, Z13_temp, Z14_temp, Z15_temp, Z16_temp, Z17_temp, Z18_temp; |
reg [22:0] Z21_temp, Z22_temp, Z23_temp, Z24_temp, Z25_temp, Z26_temp, Z27_temp, Z28_temp; |
reg [22:0] Z31_temp, Z32_temp, Z33_temp, Z34_temp, Z35_temp, Z36_temp, Z37_temp, Z38_temp; |
reg [22:0] Z41_temp, Z42_temp, Z43_temp, Z44_temp, Z45_temp, Z46_temp, Z47_temp, Z48_temp; |
reg [22:0] Z51_temp, Z52_temp, Z53_temp, Z54_temp, Z55_temp, Z56_temp, Z57_temp, Z58_temp; |
reg [22:0] Z61_temp, Z62_temp, Z63_temp, Z64_temp, Z65_temp, Z66_temp, Z67_temp, Z68_temp; |
reg [22:0] Z71_temp, Z72_temp, Z73_temp, Z74_temp, Z75_temp, Z76_temp, Z77_temp, Z78_temp; |
reg [22:0] Z81_temp, Z82_temp, Z83_temp, Z84_temp, Z85_temp, Z86_temp, Z87_temp, Z88_temp; |
reg [22:0] Z11_temp_1, Z12_temp_1, Z13_temp_1, Z14_temp_1, Z15_temp_1, Z16_temp_1, Z17_temp_1, Z18_temp_1; |
reg [22:0] Z21_temp_1, Z22_temp_1, Z23_temp_1, Z24_temp_1, Z25_temp_1, Z26_temp_1, Z27_temp_1, Z28_temp_1; |
reg [22:0] Z31_temp_1, Z32_temp_1, Z33_temp_1, Z34_temp_1, Z35_temp_1, Z36_temp_1, Z37_temp_1, Z38_temp_1; |
reg [22:0] Z41_temp_1, Z42_temp_1, Z43_temp_1, Z44_temp_1, Z45_temp_1, Z46_temp_1, Z47_temp_1, Z48_temp_1; |
reg [22:0] Z51_temp_1, Z52_temp_1, Z53_temp_1, Z54_temp_1, Z55_temp_1, Z56_temp_1, Z57_temp_1, Z58_temp_1; |
reg [22:0] Z61_temp_1, Z62_temp_1, Z63_temp_1, Z64_temp_1, Z65_temp_1, Z66_temp_1, Z67_temp_1, Z68_temp_1; |
reg [22:0] Z71_temp_1, Z72_temp_1, Z73_temp_1, Z74_temp_1, Z75_temp_1, Z76_temp_1, Z77_temp_1, Z78_temp_1; |
reg [22:0] Z81_temp_1, Z82_temp_1, Z83_temp_1, Z84_temp_1, Z85_temp_1, Z86_temp_1, Z87_temp_1, Z88_temp_1; |
reg [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18; |
reg [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28; |
reg [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
reg [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48; |
reg [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58; |
reg [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
reg [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78; |
reg [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88; |
reg out_enable, enable_1, enable_2, enable_3; |
integer Z11_int, Z12_int, Z13_int, Z14_int, Z15_int, Z16_int, Z17_int, Z18_int; |
integer Z21_int, Z22_int, Z23_int, Z24_int, Z25_int, Z26_int, Z27_int, Z28_int; |
integer Z31_int, Z32_int, Z33_int, Z34_int, Z35_int, Z36_int, Z37_int, Z38_int; |
integer Z41_int, Z42_int, Z43_int, Z44_int, Z45_int, Z46_int, Z47_int, Z48_int; |
integer Z51_int, Z52_int, Z53_int, Z54_int, Z55_int, Z56_int, Z57_int, Z58_int; |
integer Z61_int, Z62_int, Z63_int, Z64_int, Z65_int, Z66_int, Z67_int, Z68_int; |
integer Z71_int, Z72_int, Z73_int, Z74_int, Z75_int, Z76_int, Z77_int, Z78_int; |
integer Z81_int, Z82_int, Z83_int, Z84_int, Z85_int, Z86_int, Z87_int, Z88_int; |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_int <= 0; Z12_int <= 0; Z13_int <= 0; Z14_int <= 0; |
Z15_int <= 0; Z16_int <= 0; Z17_int <= 0; Z18_int <= 0; |
Z21_int <= 0; Z22_int <= 0; Z23_int <= 0; Z24_int <= 0; |
Z25_int <= 0; Z26_int <= 0; Z27_int <= 0; Z28_int <= 0; |
Z31_int <= 0; Z32_int <= 0; Z33_int <= 0; Z34_int <= 0; |
Z35_int <= 0; Z36_int <= 0; Z37_int <= 0; Z38_int <= 0; |
Z41_int <= 0; Z42_int <= 0; Z43_int <= 0; Z44_int <= 0; |
Z45_int <= 0; Z46_int <= 0; Z47_int <= 0; Z48_int <= 0; |
Z51_int <= 0; Z52_int <= 0; Z53_int <= 0; Z54_int <= 0; |
Z55_int <= 0; Z56_int <= 0; Z57_int <= 0; Z58_int <= 0; |
Z61_int <= 0; Z62_int <= 0; Z63_int <= 0; Z64_int <= 0; |
Z65_int <= 0; Z66_int <= 0; Z67_int <= 0; Z68_int <= 0; |
Z71_int <= 0; Z72_int <= 0; Z73_int <= 0; Z74_int <= 0; |
Z75_int <= 0; Z76_int <= 0; Z77_int <= 0; Z78_int <= 0; |
Z81_int <= 0; Z82_int <= 0; Z83_int <= 0; Z84_int <= 0; |
Z85_int <= 0; Z86_int <= 0; Z87_int <= 0; Z88_int <= 0; |
end |
else if (enable) begin |
Z11_int[10:0] <= Z11; Z12_int[10:0] <= Z12; Z13_int[10:0] <= Z13; Z14_int[10:0] <= Z14; |
Z15_int[10:0] <= Z15; Z16_int[10:0] <= Z16; Z17_int[10:0] <= Z17; Z18_int[10:0] <= Z18; |
Z21_int[10:0] <= Z21; Z22_int[10:0] <= Z22; Z23_int[10:0] <= Z23; Z24_int[10:0] <= Z24; |
Z25_int[10:0] <= Z25; Z26_int[10:0] <= Z26; Z27_int[10:0] <= Z27; Z28_int[10:0] <= Z28; |
Z31_int[10:0] <= Z31; Z32_int[10:0] <= Z32; Z33_int[10:0] <= Z33; Z34_int[10:0] <= Z34; |
Z35_int[10:0] <= Z35; Z36_int[10:0] <= Z36; Z37_int[10:0] <= Z37; Z38_int[10:0] <= Z38; |
Z41_int[10:0] <= Z41; Z42_int[10:0] <= Z42; Z43_int[10:0] <= Z43; Z44_int[10:0] <= Z44; |
Z45_int[10:0] <= Z45; Z46_int[10:0] <= Z46; Z47_int[10:0] <= Z47; Z48_int[10:0] <= Z48; |
Z51_int[10:0] <= Z51; Z52_int[10:0] <= Z52; Z53_int[10:0] <= Z53; Z54_int[10:0] <= Z54; |
Z55_int[10:0] <= Z55; Z56_int[10:0] <= Z56; Z57_int[10:0] <= Z57; Z58_int[10:0] <= Z58; |
Z61_int[10:0] <= Z61; Z62_int[10:0] <= Z62; Z63_int[10:0] <= Z63; Z64_int[10:0] <= Z64; |
Z65_int[10:0] <= Z65; Z66_int[10:0] <= Z66; Z67_int[10:0] <= Z67; Z68_int[10:0] <= Z68; |
Z71_int[10:0] <= Z71; Z72_int[10:0] <= Z72; Z73_int[10:0] <= Z73; Z74_int[10:0] <= Z74; |
Z75_int[10:0] <= Z75; Z76_int[10:0] <= Z76; Z77_int[10:0] <= Z77; Z78_int[10:0] <= Z78; |
Z81_int[10:0] <= Z81; Z82_int[10:0] <= Z82; Z83_int[10:0] <= Z83; Z84_int[10:0] <= Z84; |
Z85_int[10:0] <= Z85; Z86_int[10:0] <= Z86; Z87_int[10:0] <= Z87; Z88_int[10:0] <= Z88; |
// sign extend to make Z11_int a twos complement representation of Z11 |
Z11_int[31:11] <= Z11[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z12_int[31:11] <= Z12[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z13_int[31:11] <= Z13[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z14_int[31:11] <= Z14[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z15_int[31:11] <= Z15[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z16_int[31:11] <= Z16[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z17_int[31:11] <= Z17[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z18_int[31:11] <= Z18[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z21_int[31:11] <= Z21[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z22_int[31:11] <= Z22[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z23_int[31:11] <= Z23[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z24_int[31:11] <= Z24[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z25_int[31:11] <= Z25[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z26_int[31:11] <= Z26[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z27_int[31:11] <= Z27[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z28_int[31:11] <= Z28[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z31_int[31:11] <= Z31[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z32_int[31:11] <= Z32[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z33_int[31:11] <= Z33[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z34_int[31:11] <= Z34[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z35_int[31:11] <= Z35[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z36_int[31:11] <= Z36[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z37_int[31:11] <= Z37[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z38_int[31:11] <= Z38[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z41_int[31:11] <= Z41[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z42_int[31:11] <= Z42[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z43_int[31:11] <= Z43[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z44_int[31:11] <= Z44[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z45_int[31:11] <= Z45[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z46_int[31:11] <= Z46[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z47_int[31:11] <= Z47[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z48_int[31:11] <= Z48[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z51_int[31:11] <= Z51[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z52_int[31:11] <= Z52[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z53_int[31:11] <= Z53[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z54_int[31:11] <= Z54[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z55_int[31:11] <= Z55[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z56_int[31:11] <= Z56[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z57_int[31:11] <= Z57[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z58_int[31:11] <= Z58[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z61_int[31:11] <= Z61[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z62_int[31:11] <= Z62[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z63_int[31:11] <= Z63[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z64_int[31:11] <= Z64[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z65_int[31:11] <= Z65[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z66_int[31:11] <= Z66[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z67_int[31:11] <= Z67[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z68_int[31:11] <= Z68[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z71_int[31:11] <= Z71[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z72_int[31:11] <= Z72[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z73_int[31:11] <= Z73[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z74_int[31:11] <= Z74[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z75_int[31:11] <= Z75[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z76_int[31:11] <= Z76[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z77_int[31:11] <= Z77[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z78_int[31:11] <= Z78[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z81_int[31:11] <= Z81[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z82_int[31:11] <= Z82[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z83_int[31:11] <= Z83[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z84_int[31:11] <= Z84[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z85_int[31:11] <= Z85[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z86_int[31:11] <= Z86[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z87_int[31:11] <= Z87[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z88_int[31:11] <= Z88[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_temp <= 0; Z12_temp <= 0; Z13_temp <= 0; Z14_temp <= 0; |
Z12_temp <= 0; Z16_temp <= 0; Z17_temp <= 0; Z18_temp <= 0; |
Z21_temp <= 0; Z22_temp <= 0; Z23_temp <= 0; Z24_temp <= 0; |
Z22_temp <= 0; Z26_temp <= 0; Z27_temp <= 0; Z28_temp <= 0; |
Z31_temp <= 0; Z32_temp <= 0; Z33_temp <= 0; Z34_temp <= 0; |
Z32_temp <= 0; Z36_temp <= 0; Z37_temp <= 0; Z38_temp <= 0; |
Z41_temp <= 0; Z42_temp <= 0; Z43_temp <= 0; Z44_temp <= 0; |
Z42_temp <= 0; Z46_temp <= 0; Z47_temp <= 0; Z48_temp <= 0; |
Z51_temp <= 0; Z52_temp <= 0; Z53_temp <= 0; Z54_temp <= 0; |
Z52_temp <= 0; Z56_temp <= 0; Z57_temp <= 0; Z58_temp <= 0; |
Z61_temp <= 0; Z62_temp <= 0; Z63_temp <= 0; Z64_temp <= 0; |
Z62_temp <= 0; Z66_temp <= 0; Z67_temp <= 0; Z68_temp <= 0; |
Z71_temp <= 0; Z72_temp <= 0; Z73_temp <= 0; Z74_temp <= 0; |
Z72_temp <= 0; Z76_temp <= 0; Z77_temp <= 0; Z78_temp <= 0; |
Z81_temp <= 0; Z82_temp <= 0; Z83_temp <= 0; Z84_temp <= 0; |
Z82_temp <= 0; Z86_temp <= 0; Z87_temp <= 0; Z88_temp <= 0; |
end |
else if (enable_1) begin |
Z11_temp <= Z11_int * QM1_1; Z12_temp <= Z12_int * QM1_2; |
Z13_temp <= Z13_int * QM1_3; Z14_temp <= Z14_int * QM1_4; |
Z15_temp <= Z15_int * QM1_5; Z16_temp <= Z16_int * QM1_6; |
Z17_temp <= Z17_int * QM1_7; Z18_temp <= Z18_int * QM1_8; |
Z21_temp <= Z21_int * QM2_1; Z22_temp <= Z22_int * QM2_2; |
Z23_temp <= Z23_int * QM2_3; Z24_temp <= Z24_int * QM2_4; |
Z25_temp <= Z25_int * QM2_5; Z26_temp <= Z26_int * QM2_6; |
Z27_temp <= Z27_int * QM2_7; Z28_temp <= Z28_int * QM2_8; |
Z31_temp <= Z31_int * QM3_1; Z32_temp <= Z32_int * QM3_2; |
Z33_temp <= Z33_int * QM3_3; Z34_temp <= Z34_int * QM3_4; |
Z35_temp <= Z35_int * QM3_5; Z36_temp <= Z36_int * QM3_6; |
Z37_temp <= Z37_int * QM3_7; Z38_temp <= Z38_int * QM3_8; |
Z41_temp <= Z41_int * QM4_1; Z42_temp <= Z42_int * QM4_2; |
Z43_temp <= Z43_int * QM4_3; Z44_temp <= Z44_int * QM4_4; |
Z45_temp <= Z45_int * QM4_5; Z46_temp <= Z46_int * QM4_6; |
Z47_temp <= Z47_int * QM4_7; Z48_temp <= Z48_int * QM4_8; |
Z51_temp <= Z51_int * QM5_1; Z52_temp <= Z52_int * QM5_2; |
Z53_temp <= Z53_int * QM5_3; Z54_temp <= Z54_int * QM5_4; |
Z55_temp <= Z55_int * QM5_5; Z56_temp <= Z56_int * QM5_6; |
Z57_temp <= Z57_int * QM5_7; Z58_temp <= Z58_int * QM5_8; |
Z61_temp <= Z61_int * QM6_1; Z62_temp <= Z62_int * QM6_2; |
Z63_temp <= Z63_int * QM6_3; Z64_temp <= Z64_int * QM6_4; |
Z65_temp <= Z65_int * QM6_5; Z66_temp <= Z66_int * QM6_6; |
Z67_temp <= Z67_int * QM6_7; Z68_temp <= Z68_int * QM6_8; |
Z71_temp <= Z71_int * QM7_1; Z72_temp <= Z72_int * QM7_2; |
Z73_temp <= Z73_int * QM7_3; Z74_temp <= Z74_int * QM7_4; |
Z75_temp <= Z75_int * QM7_5; Z76_temp <= Z76_int * QM7_6; |
Z77_temp <= Z77_int * QM7_7; Z78_temp <= Z78_int * QM7_8; |
Z81_temp <= Z81_int * QM8_1; Z82_temp <= Z82_int * QM8_2; |
Z83_temp <= Z83_int * QM8_3; Z84_temp <= Z84_int * QM8_4; |
Z85_temp <= Z85_int * QM8_5; Z86_temp <= Z86_int * QM8_6; |
Z87_temp <= Z87_int * QM8_7; Z88_temp <= Z88_int * QM8_8; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_temp_1 <= 0; Z12_temp_1 <= 0; Z13_temp_1 <= 0; Z14_temp_1 <= 0; |
Z12_temp_1 <= 0; Z16_temp_1 <= 0; Z17_temp_1 <= 0; Z18_temp_1 <= 0; |
Z21_temp_1 <= 0; Z22_temp_1 <= 0; Z23_temp_1 <= 0; Z24_temp_1 <= 0; |
Z22_temp_1 <= 0; Z26_temp_1 <= 0; Z27_temp_1 <= 0; Z28_temp_1 <= 0; |
Z31_temp_1 <= 0; Z32_temp_1 <= 0; Z33_temp_1 <= 0; Z34_temp_1 <= 0; |
Z32_temp_1 <= 0; Z36_temp_1 <= 0; Z37_temp_1 <= 0; Z38_temp_1 <= 0; |
Z41_temp_1 <= 0; Z42_temp_1 <= 0; Z43_temp_1 <= 0; Z44_temp_1 <= 0; |
Z42_temp_1 <= 0; Z46_temp_1 <= 0; Z47_temp_1 <= 0; Z48_temp_1 <= 0; |
Z51_temp_1 <= 0; Z52_temp_1 <= 0; Z53_temp_1 <= 0; Z54_temp_1 <= 0; |
Z52_temp_1 <= 0; Z56_temp_1 <= 0; Z57_temp_1 <= 0; Z58_temp_1 <= 0; |
Z61_temp_1 <= 0; Z62_temp_1 <= 0; Z63_temp_1 <= 0; Z64_temp_1 <= 0; |
Z62_temp_1 <= 0; Z66_temp_1 <= 0; Z67_temp_1 <= 0; Z68_temp_1 <= 0; |
Z71_temp_1 <= 0; Z72_temp_1 <= 0; Z73_temp_1 <= 0; Z74_temp_1 <= 0; |
Z72_temp_1 <= 0; Z76_temp_1 <= 0; Z77_temp_1 <= 0; Z78_temp_1 <= 0; |
Z81_temp_1 <= 0; Z82_temp_1 <= 0; Z83_temp_1 <= 0; Z84_temp_1 <= 0; |
Z82_temp_1 <= 0; Z86_temp_1 <= 0; Z87_temp_1 <= 0; Z88_temp_1 <= 0; |
end |
else if (enable_2) begin |
Z11_temp_1 <= Z11_temp; Z12_temp_1 <= Z12_temp; |
Z13_temp_1 <= Z13_temp; Z14_temp_1 <= Z14_temp; |
Z15_temp_1 <= Z15_temp; Z16_temp_1 <= Z16_temp; |
Z17_temp_1 <= Z17_temp; Z18_temp_1 <= Z18_temp; |
Z21_temp_1 <= Z21_temp; Z22_temp_1 <= Z22_temp; |
Z23_temp_1 <= Z23_temp; Z24_temp_1 <= Z24_temp; |
Z25_temp_1 <= Z25_temp; Z26_temp_1 <= Z26_temp; |
Z27_temp_1 <= Z27_temp; Z28_temp_1 <= Z28_temp; |
Z31_temp_1 <= Z31_temp; Z32_temp_1 <= Z32_temp; |
Z33_temp_1 <= Z33_temp; Z34_temp_1 <= Z34_temp; |
Z35_temp_1 <= Z35_temp; Z36_temp_1 <= Z36_temp; |
Z37_temp_1 <= Z37_temp; Z38_temp_1 <= Z38_temp; |
Z41_temp_1 <= Z41_temp; Z42_temp_1 <= Z42_temp; |
Z43_temp_1 <= Z43_temp; Z44_temp_1 <= Z44_temp; |
Z45_temp_1 <= Z45_temp; Z46_temp_1 <= Z46_temp; |
Z47_temp_1 <= Z47_temp; Z48_temp_1 <= Z48_temp; |
Z51_temp_1 <= Z51_temp; Z52_temp_1 <= Z52_temp; |
Z53_temp_1 <= Z53_temp; Z54_temp_1 <= Z54_temp; |
Z55_temp_1 <= Z55_temp; Z56_temp_1 <= Z56_temp; |
Z57_temp_1 <= Z57_temp; Z58_temp_1 <= Z58_temp; |
Z61_temp_1 <= Z61_temp; Z62_temp_1 <= Z62_temp; |
Z63_temp_1 <= Z63_temp; Z64_temp_1 <= Z64_temp; |
Z65_temp_1 <= Z65_temp; Z66_temp_1 <= Z66_temp; |
Z67_temp_1 <= Z67_temp; Z68_temp_1 <= Z68_temp; |
Z71_temp_1 <= Z71_temp; Z72_temp_1 <= Z72_temp; |
Z73_temp_1 <= Z73_temp; Z74_temp_1 <= Z74_temp; |
Z75_temp_1 <= Z75_temp; Z76_temp_1 <= Z76_temp; |
Z77_temp_1 <= Z77_temp; Z78_temp_1 <= Z78_temp; |
Z81_temp_1 <= Z81_temp; Z82_temp_1 <= Z82_temp; |
Z83_temp_1 <= Z83_temp; Z84_temp_1 <= Z84_temp; |
Z85_temp_1 <= Z85_temp; Z86_temp_1 <= Z86_temp; |
Z87_temp_1 <= Z87_temp; Z88_temp_1 <= Z88_temp; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Q11 <= 0; Q12 <= 0; Q13 <= 0; Q14 <= 0; Q15 <= 0; Q16 <= 0; Q17 <= 0; Q18 <= 0; |
Q21 <= 0; Q22 <= 0; Q23 <= 0; Q24 <= 0; Q25 <= 0; Q26 <= 0; Q27 <= 0; Q28 <= 0; |
Q31 <= 0; Q32 <= 0; Q33 <= 0; Q34 <= 0; Q35 <= 0; Q36 <= 0; Q37 <= 0; Q38 <= 0; |
Q41 <= 0; Q42 <= 0; Q43 <= 0; Q44 <= 0; Q45 <= 0; Q46 <= 0; Q47 <= 0; Q48 <= 0; |
Q51 <= 0; Q52 <= 0; Q53 <= 0; Q54 <= 0; Q55 <= 0; Q56 <= 0; Q57 <= 0; Q58 <= 0; |
Q61 <= 0; Q62 <= 0; Q63 <= 0; Q64 <= 0; Q65 <= 0; Q66 <= 0; Q67 <= 0; Q68 <= 0; |
Q71 <= 0; Q72 <= 0; Q73 <= 0; Q74 <= 0; Q75 <= 0; Q76 <= 0; Q77 <= 0; Q78 <= 0; |
Q81 <= 0; Q82 <= 0; Q83 <= 0; Q84 <= 0; Q85 <= 0; Q86 <= 0; Q87 <= 0; Q88 <= 0; |
end |
else if (enable_3) begin |
// rounding Q11 based on the bit in the 11th place of Z11_temp |
Q11 <= Z11_temp_1[11] ? Z11_temp_1[22:12] + 1 : Z11_temp_1[22:12]; |
Q12 <= Z12_temp_1[11] ? Z12_temp_1[22:12] + 1 : Z12_temp_1[22:12]; |
Q13 <= Z13_temp_1[11] ? Z13_temp_1[22:12] + 1 : Z13_temp_1[22:12]; |
Q14 <= Z14_temp_1[11] ? Z14_temp_1[22:12] + 1 : Z14_temp_1[22:12]; |
Q15 <= Z15_temp_1[11] ? Z15_temp_1[22:12] + 1 : Z15_temp_1[22:12]; |
Q16 <= Z16_temp_1[11] ? Z16_temp_1[22:12] + 1 : Z16_temp_1[22:12]; |
Q17 <= Z17_temp_1[11] ? Z17_temp_1[22:12] + 1 : Z17_temp_1[22:12]; |
Q18 <= Z18_temp_1[11] ? Z18_temp_1[22:12] + 1 : Z18_temp_1[22:12]; |
Q21 <= Z21_temp_1[11] ? Z21_temp_1[22:12] + 1 : Z21_temp_1[22:12]; |
Q22 <= Z22_temp_1[11] ? Z22_temp_1[22:12] + 1 : Z22_temp_1[22:12]; |
Q23 <= Z23_temp_1[11] ? Z23_temp_1[22:12] + 1 : Z23_temp_1[22:12]; |
Q24 <= Z24_temp_1[11] ? Z24_temp_1[22:12] + 1 : Z24_temp_1[22:12]; |
Q25 <= Z25_temp_1[11] ? Z25_temp_1[22:12] + 1 : Z25_temp_1[22:12]; |
Q26 <= Z26_temp_1[11] ? Z26_temp_1[22:12] + 1 : Z26_temp_1[22:12]; |
Q27 <= Z27_temp_1[11] ? Z27_temp_1[22:12] + 1 : Z27_temp_1[22:12]; |
Q28 <= Z28_temp_1[11] ? Z28_temp_1[22:12] + 1 : Z28_temp_1[22:12]; |
Q31 <= Z31_temp_1[11] ? Z31_temp_1[22:12] + 1 : Z31_temp_1[22:12]; |
Q32 <= Z32_temp_1[11] ? Z32_temp_1[22:12] + 1 : Z32_temp_1[22:12]; |
Q33 <= Z33_temp_1[11] ? Z33_temp_1[22:12] + 1 : Z33_temp_1[22:12]; |
Q34 <= Z34_temp_1[11] ? Z34_temp_1[22:12] + 1 : Z34_temp_1[22:12]; |
Q35 <= Z35_temp_1[11] ? Z35_temp_1[22:12] + 1 : Z35_temp_1[22:12]; |
Q36 <= Z36_temp_1[11] ? Z36_temp_1[22:12] + 1 : Z36_temp_1[22:12]; |
Q37 <= Z37_temp_1[11] ? Z37_temp_1[22:12] + 1 : Z37_temp_1[22:12]; |
Q38 <= Z38_temp_1[11] ? Z38_temp_1[22:12] + 1 : Z38_temp_1[22:12]; |
Q41 <= Z41_temp_1[11] ? Z41_temp_1[22:12] + 1 : Z41_temp_1[22:12]; |
Q42 <= Z42_temp_1[11] ? Z42_temp_1[22:12] + 1 : Z42_temp_1[22:12]; |
Q43 <= Z43_temp_1[11] ? Z43_temp_1[22:12] + 1 : Z43_temp_1[22:12]; |
Q44 <= Z44_temp_1[11] ? Z44_temp_1[22:12] + 1 : Z44_temp_1[22:12]; |
Q45 <= Z45_temp_1[11] ? Z45_temp_1[22:12] + 1 : Z45_temp_1[22:12]; |
Q46 <= Z46_temp_1[11] ? Z46_temp_1[22:12] + 1 : Z46_temp_1[22:12]; |
Q47 <= Z47_temp_1[11] ? Z47_temp_1[22:12] + 1 : Z47_temp_1[22:12]; |
Q48 <= Z48_temp_1[11] ? Z48_temp_1[22:12] + 1 : Z48_temp_1[22:12]; |
Q51 <= Z51_temp_1[11] ? Z51_temp_1[22:12] + 1 : Z51_temp_1[22:12]; |
Q52 <= Z52_temp_1[11] ? Z52_temp_1[22:12] + 1 : Z52_temp_1[22:12]; |
Q53 <= Z53_temp_1[11] ? Z53_temp_1[22:12] + 1 : Z53_temp_1[22:12]; |
Q54 <= Z54_temp_1[11] ? Z54_temp_1[22:12] + 1 : Z54_temp_1[22:12]; |
Q55 <= Z55_temp_1[11] ? Z55_temp_1[22:12] + 1 : Z55_temp_1[22:12]; |
Q56 <= Z56_temp_1[11] ? Z56_temp_1[22:12] + 1 : Z56_temp_1[22:12]; |
Q57 <= Z57_temp_1[11] ? Z57_temp_1[22:12] + 1 : Z57_temp_1[22:12]; |
Q58 <= Z58_temp_1[11] ? Z58_temp_1[22:12] + 1 : Z58_temp_1[22:12]; |
Q61 <= Z61_temp_1[11] ? Z61_temp_1[22:12] + 1 : Z61_temp_1[22:12]; |
Q62 <= Z62_temp_1[11] ? Z62_temp_1[22:12] + 1 : Z62_temp_1[22:12]; |
Q63 <= Z63_temp_1[11] ? Z63_temp_1[22:12] + 1 : Z63_temp_1[22:12]; |
Q64 <= Z64_temp_1[11] ? Z64_temp_1[22:12] + 1 : Z64_temp_1[22:12]; |
Q65 <= Z65_temp_1[11] ? Z65_temp_1[22:12] + 1 : Z65_temp_1[22:12]; |
Q66 <= Z66_temp_1[11] ? Z66_temp_1[22:12] + 1 : Z66_temp_1[22:12]; |
Q67 <= Z67_temp_1[11] ? Z67_temp_1[22:12] + 1 : Z67_temp_1[22:12]; |
Q68 <= Z68_temp_1[11] ? Z68_temp_1[22:12] + 1 : Z68_temp_1[22:12]; |
Q71 <= Z71_temp_1[11] ? Z71_temp_1[22:12] + 1 : Z71_temp_1[22:12]; |
Q72 <= Z72_temp_1[11] ? Z72_temp_1[22:12] + 1 : Z72_temp_1[22:12]; |
Q73 <= Z73_temp_1[11] ? Z73_temp_1[22:12] + 1 : Z73_temp_1[22:12]; |
Q74 <= Z74_temp_1[11] ? Z74_temp_1[22:12] + 1 : Z74_temp_1[22:12]; |
Q75 <= Z75_temp_1[11] ? Z75_temp_1[22:12] + 1 : Z75_temp_1[22:12]; |
Q76 <= Z76_temp_1[11] ? Z76_temp_1[22:12] + 1 : Z76_temp_1[22:12]; |
Q77 <= Z77_temp_1[11] ? Z77_temp_1[22:12] + 1 : Z77_temp_1[22:12]; |
Q78 <= Z78_temp_1[11] ? Z78_temp_1[22:12] + 1 : Z78_temp_1[22:12]; |
Q81 <= Z81_temp_1[11] ? Z81_temp_1[22:12] + 1 : Z81_temp_1[22:12]; |
Q82 <= Z82_temp_1[11] ? Z82_temp_1[22:12] + 1 : Z82_temp_1[22:12]; |
Q83 <= Z83_temp_1[11] ? Z83_temp_1[22:12] + 1 : Z83_temp_1[22:12]; |
Q84 <= Z84_temp_1[11] ? Z84_temp_1[22:12] + 1 : Z84_temp_1[22:12]; |
Q85 <= Z85_temp_1[11] ? Z85_temp_1[22:12] + 1 : Z85_temp_1[22:12]; |
Q86 <= Z86_temp_1[11] ? Z86_temp_1[22:12] + 1 : Z86_temp_1[22:12]; |
Q87 <= Z87_temp_1[11] ? Z87_temp_1[22:12] + 1 : Z87_temp_1[22:12]; |
Q88 <= Z88_temp_1[11] ? Z88_temp_1[22:12] + 1 : Z88_temp_1[22:12]; |
end |
end |
|
|
/* enable_1 is delayed one clock cycle from enable, and it's used to |
enable the logic that needs to execute on the clock cycle after enable goes high |
enable_2 is delayed two clock cycles, and out_enable signals the next module |
that its input data is ready*/ |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; |
out_enable <= 0; |
end |
else begin |
enable_1 <= enable; enable_2 <= enable_1; |
enable_3 <= enable_2; |
out_enable <= enable_3; |
end |
end |
|
endmodule |
/jpegencode/trunk/pre_fifo.v
0,0 → 1,81
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
|
/* This module combines the Y, Cb, and Cr blocks, and the RGB to Y, Cb, and Cr |
converter. */ |
|
`timescale 1ns / 100ps |
|
module pre_fifo(clk, rst, enable, data_in, cr_JPEG_bitstream, cr_data_ready, |
cr_orc, cb_JPEG_bitstream, cb_data_ready, cb_orc, y_JPEG_bitstream, |
y_data_ready, y_orc, y_eob_output, |
y_eob_empty, cb_eob_empty, cr_eob_empty); |
input clk, rst, enable; |
input [23:0] data_in; |
output [31:0] cr_JPEG_bitstream; |
output cr_data_ready; |
output [4:0] cr_orc; |
output [31:0] cb_JPEG_bitstream; |
output cb_data_ready; |
output [4:0] cb_orc; |
output [31:0] y_JPEG_bitstream; |
output y_data_ready; |
output [4:0] y_orc; |
output y_eob_output; |
output y_eob_empty, cb_eob_empty, cr_eob_empty; |
|
|
wire rgb_enable; |
wire [23:0] dct_data_in; |
|
|
RGB2YCBCR u4(.clk(clk), .rst(rst), .enable(enable), |
.data_in(data_in), .data_out(dct_data_in), .enable_out(rgb_enable)); |
|
crd_q_h u11(.clk(clk), .rst(rst), .enable(rgb_enable), .data_in(dct_data_in[23:16]), |
.JPEG_bitstream(cr_JPEG_bitstream), |
.data_ready(cr_data_ready), .cr_orc(cr_orc), |
.end_of_block_empty(cr_eob_empty)); |
|
cbd_q_h u12(.clk(clk), .rst(rst), .enable(rgb_enable), .data_in(dct_data_in[15:8]), |
.JPEG_bitstream(cb_JPEG_bitstream), |
.data_ready(cb_data_ready), .cb_orc(cb_orc), |
.end_of_block_empty(cb_eob_empty)); |
|
yd_q_h u13(.clk(clk), .rst(rst), .enable(rgb_enable), .data_in(dct_data_in[7:0]), |
.JPEG_bitstream(y_JPEG_bitstream), |
.data_ready(y_data_ready), .y_orc(y_orc), |
.end_of_block_output(y_eob_output), .end_of_block_empty(y_eob_empty)); |
|
endmodule |
/jpegencode/trunk/sync_fifo_ff.v
0,0 → 1,113
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This FIFO is used for the ff_checker module. */ |
|
`timescale 1ns / 100ps |
|
module sync_fifo_ff (clk, rst, read_req, write_data, write_enable, rollover_write, |
read_data, fifo_empty, rdata_valid); |
input clk; |
input rst; |
input read_req; |
input [90:0] write_data; |
input write_enable; |
input rollover_write; |
output [90:0] read_data; |
output fifo_empty; |
output rdata_valid; |
|
reg [4:0] read_ptr; |
reg [4:0] write_ptr; |
reg [90:0] mem [0:15]; |
reg [90:0] read_data; |
reg rdata_valid; |
wire [3:0] write_addr = write_ptr[3:0]; |
wire [3:0] read_addr = read_ptr[3:0]; |
wire read_enable = read_req && (~fifo_empty); |
assign fifo_empty = (read_ptr == write_ptr); |
|
|
always @(posedge clk) |
begin |
if (rst) |
write_ptr <= {(5){1'b0}}; |
else if (write_enable & !rollover_write) |
write_ptr <= write_ptr + {{4{1'b0}},1'b1}; |
else if (write_enable & rollover_write) |
write_ptr <= write_ptr + 5'b00010; |
// A rollover_write means that there have been a total of 4 FF's |
// that have been detected in the bitstream. So an extra set of 32 |
// bits will be put into the bitstream (due to the 4 extra 00's added |
// after the 4 FF's), and the input data will have to |
// be delayed by 1 clock cycle as it makes its way into the output |
// bitstream. So the write_ptr is incremented by 2 for a rollover, giving |
// the output the extra clock cycle it needs to write the |
// extra 32 bits to the bitstream. The output |
// will read the dummy data from the FIFO, but won't do anything with it, |
// it will be putting the extra set of 32 bits into the bitstream on that |
// clock cycle. |
end |
|
always @(posedge clk) |
begin |
if (rst) |
rdata_valid <= 1'b0; |
else if (read_enable) |
rdata_valid <= 1'b1; |
else |
rdata_valid <= 1'b0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
read_ptr <= {(5){1'b0}}; |
else if (read_enable) |
read_ptr <= read_ptr + {{4{1'b0}},1'b1}; |
end |
|
// Mem write |
always @(posedge clk) |
begin |
if (write_enable) |
mem[write_addr] <= write_data; |
end |
// Mem Read |
always @(posedge clk) |
begin |
if (read_enable) |
read_data <= mem[read_addr]; |
end |
|
endmodule |
/jpegencode/trunk/cb_huff.v
0,0 → 1,2253
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module is the Huffman encoder. It takes in the quantized outputs |
from the quantizer, and creates the Huffman codes from these value. The |
output from this module is the jpeg code of the actual pixel data. The jpeg |
file headers will need to be generated separately. The Huffman codes are constant, |
and they can be changed by changing the parameters in this module. */ |
|
`timescale 1ns / 100ps |
|
module cb_huff(clk, rst, enable, |
Cb11, Cb12, Cb13, Cb14, Cb15, Cb16, Cb17, Cb18, Cb21, Cb22, Cb23, Cb24, Cb25, Cb26, Cb27, Cb28, |
Cb31, Cb32, Cb33, Cb34, Cb35, Cb36, Cb37, Cb38, Cb41, Cb42, Cb43, Cb44, Cb45, Cb46, Cb47, Cb48, |
Cb51, Cb52, Cb53, Cb54, Cb55, Cb56, Cb57, Cb58, Cb61, Cb62, Cb63, Cb64, Cb65, Cb66, Cb67, Cb68, |
Cb71, Cb72, Cb73, Cb74, Cb75, Cb76, Cb77, Cb78, Cb81, Cb82, Cb83, Cb84, Cb85, Cb86, Cb87, Cb88, |
JPEG_bitstream, data_ready, output_reg_count, end_of_block_empty); |
input clk; |
input rst; |
input enable; |
input [10:0] Cb11, Cb12, Cb13, Cb14, Cb15, Cb16, Cb17, Cb18, Cb21, Cb22, Cb23, Cb24; |
input [10:0] Cb25, Cb26, Cb27, Cb28, Cb31, Cb32, Cb33, Cb34, Cb35, Cb36, Cb37, Cb38; |
input [10:0] Cb41, Cb42, Cb43, Cb44, Cb45, Cb46, Cb47, Cb48, Cb51, Cb52, Cb53, Cb54; |
input [10:0] Cb55, Cb56, Cb57, Cb58, Cb61, Cb62, Cb63, Cb64, Cb65, Cb66, Cb67, Cb68; |
input [10:0] Cb71, Cb72, Cb73, Cb74, Cb75, Cb76, Cb77, Cb78, Cb81, Cb82, Cb83, Cb84; |
input [10:0] Cb85, Cb86, Cb87, Cb88; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output [4:0] output_reg_count; |
output end_of_block_empty; |
|
|
reg [7:0] block_counter; |
reg [11:0] Cb11_amp, Cb11_1_pos, Cb11_1_neg, Cb11_diff; |
reg [11:0] Cb11_previous, Cb11_1; |
reg [10:0] Cb12_amp, Cb12_pos, Cb12_neg; |
reg [10:0] Cb21_pos, Cb21_neg, Cb31_pos, Cb31_neg, Cb22_pos, Cb22_neg; |
reg [10:0] Cb13_pos, Cb13_neg, Cb14_pos, Cb14_neg, Cb15_pos, Cb15_neg; |
reg [10:0] Cb16_pos, Cb16_neg, Cb17_pos, Cb17_neg, Cb18_pos, Cb18_neg; |
reg [10:0] Cb23_pos, Cb23_neg, Cb24_pos, Cb24_neg, Cb25_pos, Cb25_neg; |
reg [10:0] Cb26_pos, Cb26_neg, Cb27_pos, Cb27_neg, Cb28_pos, Cb28_neg; |
reg [10:0] Cb32_pos, Cb32_neg; |
reg [10:0] Cb33_pos, Cb33_neg, Cb34_pos, Cb34_neg, Cb35_pos, Cb35_neg; |
reg [10:0] Cb36_pos, Cb36_neg, Cb37_pos, Cb37_neg, Cb38_pos, Cb38_neg; |
reg [10:0] Cb41_pos, Cb41_neg, Cb42_pos, Cb42_neg; |
reg [10:0] Cb43_pos, Cb43_neg, Cb44_pos, Cb44_neg, Cb45_pos, Cb45_neg; |
reg [10:0] Cb46_pos, Cb46_neg, Cb47_pos, Cb47_neg, Cb48_pos, Cb48_neg; |
reg [10:0] Cb51_pos, Cb51_neg, Cb52_pos, Cb52_neg; |
reg [10:0] Cb53_pos, Cb53_neg, Cb54_pos, Cb54_neg, Cb55_pos, Cb55_neg; |
reg [10:0] Cb56_pos, Cb56_neg, Cb57_pos, Cb57_neg, Cb58_pos, Cb58_neg; |
reg [10:0] Cb61_pos, Cb61_neg, Cb62_pos, Cb62_neg; |
reg [10:0] Cb63_pos, Cb63_neg, Cb64_pos, Cb64_neg, Cb65_pos, Cb65_neg; |
reg [10:0] Cb66_pos, Cb66_neg, Cb67_pos, Cb67_neg, Cb68_pos, Cb68_neg; |
reg [10:0] Cb71_pos, Cb71_neg, Cb72_pos, Cb72_neg; |
reg [10:0] Cb73_pos, Cb73_neg, Cb74_pos, Cb74_neg, Cb75_pos, Cb75_neg; |
reg [10:0] Cb76_pos, Cb76_neg, Cb77_pos, Cb77_neg, Cb78_pos, Cb78_neg; |
reg [10:0] Cb81_pos, Cb81_neg, Cb82_pos, Cb82_neg; |
reg [10:0] Cb83_pos, Cb83_neg, Cb84_pos, Cb84_neg, Cb85_pos, Cb85_neg; |
reg [10:0] Cb86_pos, Cb86_neg, Cb87_pos, Cb87_neg, Cb88_pos, Cb88_neg; |
reg [3:0] Cb11_bits_pos, Cb11_bits_neg, Cb11_bits, Cb11_bits_1; |
reg [3:0] Cb12_bits_pos, Cb12_bits_neg, Cb12_bits, Cb12_bits_1; |
reg [3:0] Cb12_bits_2, Cb12_bits_3; |
reg Cb11_msb, Cb12_msb, Cb12_msb_1, data_ready; |
reg enable_1, enable_2, enable_3, enable_4, enable_5, enable_6; |
reg enable_7, enable_8, enable_9, enable_10, enable_11, enable_12; |
reg enable_13, enable_module, enable_latch_7, enable_latch_8; |
reg Cb12_et_zero, rollover, rollover_1, rollover_2, rollover_3; |
reg rollover_4, rollover_5, rollover_6, rollover_7; |
reg Cb21_et_zero, Cb21_msb, Cb31_et_zero, Cb31_msb; |
reg Cb22_et_zero, Cb22_msb, Cb13_et_zero, Cb13_msb; |
reg Cb14_et_zero, Cb14_msb, Cb15_et_zero, Cb15_msb; |
reg Cb16_et_zero, Cb16_msb, Cb17_et_zero, Cb17_msb; |
reg Cb18_et_zero, Cb18_msb; |
reg Cb23_et_zero, Cb23_msb, Cb24_et_zero, Cb24_msb; |
reg Cb25_et_zero, Cb25_msb, Cb26_et_zero, Cb26_msb; |
reg Cb27_et_zero, Cb27_msb, Cb28_et_zero, Cb28_msb; |
reg Cb32_et_zero, Cb32_msb, Cb33_et_zero, Cb33_msb; |
reg Cb34_et_zero, Cb34_msb, Cb35_et_zero, Cb35_msb; |
reg Cb36_et_zero, Cb36_msb, Cb37_et_zero, Cb37_msb; |
reg Cb38_et_zero, Cb38_msb; |
reg Cb41_et_zero, Cb41_msb, Cb42_et_zero, Cb42_msb; |
reg Cb43_et_zero, Cb43_msb, Cb44_et_zero, Cb44_msb; |
reg Cb45_et_zero, Cb45_msb, Cb46_et_zero, Cb46_msb; |
reg Cb47_et_zero, Cb47_msb, Cb48_et_zero, Cb48_msb; |
reg Cb51_et_zero, Cb51_msb, Cb52_et_zero, Cb52_msb; |
reg Cb53_et_zero, Cb53_msb, Cb54_et_zero, Cb54_msb; |
reg Cb55_et_zero, Cb55_msb, Cb56_et_zero, Cb56_msb; |
reg Cb57_et_zero, Cb57_msb, Cb58_et_zero, Cb58_msb; |
reg Cb61_et_zero, Cb61_msb, Cb62_et_zero, Cb62_msb; |
reg Cb63_et_zero, Cb63_msb, Cb64_et_zero, Cb64_msb; |
reg Cb65_et_zero, Cb65_msb, Cb66_et_zero, Cb66_msb; |
reg Cb67_et_zero, Cb67_msb, Cb68_et_zero, Cb68_msb; |
reg Cb71_et_zero, Cb71_msb, Cb72_et_zero, Cb72_msb; |
reg Cb73_et_zero, Cb73_msb, Cb74_et_zero, Cb74_msb; |
reg Cb75_et_zero, Cb75_msb, Cb76_et_zero, Cb76_msb; |
reg Cb77_et_zero, Cb77_msb, Cb78_et_zero, Cb78_msb; |
reg Cb81_et_zero, Cb81_msb, Cb82_et_zero, Cb82_msb; |
reg Cb83_et_zero, Cb83_msb, Cb84_et_zero, Cb84_msb; |
reg Cb85_et_zero, Cb85_msb, Cb86_et_zero, Cb86_msb; |
reg Cb87_et_zero, Cb87_msb, Cb88_et_zero, Cb88_msb; |
reg Cb12_et_zero_1, Cb12_et_zero_2, Cb12_et_zero_3, Cb12_et_zero_4, Cb12_et_zero_5; |
reg [10:0] Cb_DC [11:0]; |
reg [3:0] Cb_DC_code_length [11:0]; |
reg [15:0] Cb_AC [161:0]; |
reg [4:0] Cb_AC_code_length [161:0]; |
reg [7:0] Cb_AC_run_code [250:0]; |
reg [10:0] Cb11_Huff, Cb11_Huff_1, Cb11_Huff_2; |
reg [15:0] Cb12_Huff, Cb12_Huff_1, Cb12_Huff_2; |
reg [3:0] Cb11_Huff_count, Cb11_Huff_shift, Cb11_Huff_shift_1, Cb11_amp_shift, Cb12_amp_shift; |
reg [3:0] Cb12_Huff_shift, Cb12_Huff_shift_1, zero_run_length, zrl_1, zrl_2, zrl_3; |
reg [4:0] Cb12_Huff_count, Cb12_Huff_count_1; |
reg [4:0] output_reg_count, Cb11_output_count, old_orc_1, old_orc_2; |
reg [4:0] old_orc_3, old_orc_4, old_orc_5, old_orc_6, Cb12_oc_1; |
reg [4:0] orc_3, orc_4, orc_5, orc_6, orc_7, orc_8; |
reg [4:0] Cb12_output_count; |
reg [4:0] Cb12_edge, Cb12_edge_1, Cb12_edge_2, Cb12_edge_3, Cb12_edge_4; |
reg [31:0] JPEG_bitstream, JPEG_bs, JPEG_bs_1, JPEG_bs_2, JPEG_bs_3, JPEG_bs_4, JPEG_bs_5; |
reg [31:0] JPEG_Cb12_bs, JPEG_Cb12_bs_1, JPEG_Cb12_bs_2, JPEG_Cb12_bs_3, JPEG_Cb12_bs_4; |
reg [31:0] JPEG_ro_bs, JPEG_ro_bs_1, JPEG_ro_bs_2, JPEG_ro_bs_3, JPEG_ro_bs_4; |
reg [21:0] Cb11_JPEG_LSBs_3; |
reg [10:0] Cb11_JPEG_LSBs, Cb11_JPEG_LSBs_1, Cb11_JPEG_LSBs_2; |
reg [9:0] Cb12_JPEG_LSBs, Cb12_JPEG_LSBs_1, Cb12_JPEG_LSBs_2, Cb12_JPEG_LSBs_3; |
reg [25:0] Cb11_JPEG_bits, Cb11_JPEG_bits_1, Cb12_JPEG_bits, Cb12_JPEG_LSBs_4; |
reg [7:0] Cb12_code_entry; |
reg third_8_all_0s, fourth_8_all_0s, fifth_8_all_0s, sixth_8_all_0s, seventh_8_all_0s; |
reg eighth_8_all_0s, end_of_block, end_of_block_output, code_15_0, zrl_et_15; |
reg end_of_block_empty; |
|
wire [7:0] code_index = { zrl_2, Cb12_bits }; |
|
|
|
always @(posedge clk) |
begin |
if (rst) begin |
third_8_all_0s <= 0; fourth_8_all_0s <= 0; |
fifth_8_all_0s <= 0; sixth_8_all_0s <= 0; seventh_8_all_0s <= 0; |
eighth_8_all_0s <= 0; |
end |
else if (enable_1) begin |
third_8_all_0s <= Cb25_et_zero & Cb34_et_zero & Cb43_et_zero & Cb52_et_zero |
& Cb61_et_zero & Cb71_et_zero & Cb62_et_zero & Cb53_et_zero; |
fourth_8_all_0s <= Cb44_et_zero & Cb35_et_zero & Cb26_et_zero & Cb17_et_zero |
& Cb18_et_zero & Cb27_et_zero & Cb36_et_zero & Cb45_et_zero; |
fifth_8_all_0s <= Cb54_et_zero & Cb63_et_zero & Cb72_et_zero & Cb81_et_zero |
& Cb82_et_zero & Cb73_et_zero & Cb64_et_zero & Cb55_et_zero; |
sixth_8_all_0s <= Cb46_et_zero & Cb37_et_zero & Cb28_et_zero & Cb38_et_zero |
& Cb47_et_zero & Cb56_et_zero & Cb65_et_zero & Cb74_et_zero; |
seventh_8_all_0s <= Cb83_et_zero & Cb84_et_zero & Cb75_et_zero & Cb66_et_zero |
& Cb57_et_zero & Cb48_et_zero & Cb58_et_zero & Cb67_et_zero; |
eighth_8_all_0s <= Cb76_et_zero & Cb85_et_zero & Cb86_et_zero & Cb77_et_zero |
& Cb68_et_zero & Cb78_et_zero & Cb87_et_zero & Cb88_et_zero; |
end |
end |
|
|
/* end_of_block checks to see if there are any nonzero elements left in the block |
If there aren't any nonzero elements left, then the last bits in the JPEG stream |
will be the end of block code. The purpose of this register is to determine if the |
zero run length code 15-0 should be used or not. It should be used if there are 15 or more |
zeros in a row, followed by a nonzero value. If there are only zeros left in the block, |
then end_of_block will be 1. If there are any nonzero values left in the block, end_of_block |
will be 0. */ |
|
always @(posedge clk) |
begin |
if (rst) |
end_of_block <= 0; |
else if (enable) |
end_of_block <= 0; |
else if (enable_module & block_counter < 32) |
end_of_block <= third_8_all_0s & fourth_8_all_0s & fifth_8_all_0s |
& sixth_8_all_0s & seventh_8_all_0s & eighth_8_all_0s; |
else if (enable_module & block_counter < 48) |
end_of_block <= fifth_8_all_0s & sixth_8_all_0s & seventh_8_all_0s |
& eighth_8_all_0s; |
else if (enable_module & block_counter <= 64) |
end_of_block <= seventh_8_all_0s & eighth_8_all_0s; |
else if (enable_module & block_counter > 64) |
end_of_block <= 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
block_counter <= 0; |
end |
else if (enable) begin |
block_counter <= 0; |
end |
else if (enable_module) begin |
block_counter <= block_counter + 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
output_reg_count <= 0; |
end |
else if (end_of_block_output) begin |
output_reg_count <= 0; |
end |
else if (enable_6) begin |
output_reg_count <= output_reg_count + Cb11_output_count; |
end |
else if (enable_latch_7) begin |
output_reg_count <= output_reg_count + Cb12_oc_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
old_orc_1 <= 0; |
end |
else if (end_of_block_output) begin |
old_orc_1 <= 0; |
end |
else if (enable_module) begin |
old_orc_1 <= output_reg_count; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
rollover <= 0; rollover_1 <= 0; rollover_2 <= 0; |
rollover_3 <= 0; rollover_4 <= 0; rollover_5 <= 0; |
rollover_6 <= 0; rollover_7 <= 0; |
old_orc_2 <= 0; |
orc_3 <= 0; orc_4 <= 0; orc_5 <= 0; orc_6 <= 0; |
orc_7 <= 0; orc_8 <= 0; data_ready <= 0; |
end_of_block_output <= 0; end_of_block_empty <= 0; |
end |
else if (enable_module) begin |
rollover <= (old_orc_1 > output_reg_count); |
rollover_1 <= rollover; |
rollover_2 <= rollover_1; |
rollover_3 <= rollover_2; |
rollover_4 <= rollover_3; |
rollover_5 <= rollover_4; |
rollover_6 <= rollover_5; |
rollover_7 <= rollover_6; |
old_orc_2 <= old_orc_1; |
orc_3 <= old_orc_2; |
orc_4 <= orc_3; orc_5 <= orc_4; |
orc_6 <= orc_5; orc_7 <= orc_6; |
orc_8 <= orc_7; |
data_ready <= rollover_6 | block_counter == 77; |
end_of_block_output <= block_counter == 77; |
end_of_block_empty <= rollover_7 & block_counter == 77 & output_reg_count == 0; |
end |
end |
|
|
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_5 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_5[31] <= (rollover_6 & orc_7 > 0) ? JPEG_ro_bs_4[31] : JPEG_bs_4[31]; |
JPEG_bs_5[30] <= (rollover_6 & orc_7 > 1) ? JPEG_ro_bs_4[30] : JPEG_bs_4[30]; |
JPEG_bs_5[29] <= (rollover_6 & orc_7 > 2) ? JPEG_ro_bs_4[29] : JPEG_bs_4[29]; |
JPEG_bs_5[28] <= (rollover_6 & orc_7 > 3) ? JPEG_ro_bs_4[28] : JPEG_bs_4[28]; |
JPEG_bs_5[27] <= (rollover_6 & orc_7 > 4) ? JPEG_ro_bs_4[27] : JPEG_bs_4[27]; |
JPEG_bs_5[26] <= (rollover_6 & orc_7 > 5) ? JPEG_ro_bs_4[26] : JPEG_bs_4[26]; |
JPEG_bs_5[25] <= (rollover_6 & orc_7 > 6) ? JPEG_ro_bs_4[25] : JPEG_bs_4[25]; |
JPEG_bs_5[24] <= (rollover_6 & orc_7 > 7) ? JPEG_ro_bs_4[24] : JPEG_bs_4[24]; |
JPEG_bs_5[23] <= (rollover_6 & orc_7 > 8) ? JPEG_ro_bs_4[23] : JPEG_bs_4[23]; |
JPEG_bs_5[22] <= (rollover_6 & orc_7 > 9) ? JPEG_ro_bs_4[22] : JPEG_bs_4[22]; |
JPEG_bs_5[21] <= (rollover_6 & orc_7 > 10) ? JPEG_ro_bs_4[21] : JPEG_bs_4[21]; |
JPEG_bs_5[20] <= (rollover_6 & orc_7 > 11) ? JPEG_ro_bs_4[20] : JPEG_bs_4[20]; |
JPEG_bs_5[19] <= (rollover_6 & orc_7 > 12) ? JPEG_ro_bs_4[19] : JPEG_bs_4[19]; |
JPEG_bs_5[18] <= (rollover_6 & orc_7 > 13) ? JPEG_ro_bs_4[18] : JPEG_bs_4[18]; |
JPEG_bs_5[17] <= (rollover_6 & orc_7 > 14) ? JPEG_ro_bs_4[17] : JPEG_bs_4[17]; |
JPEG_bs_5[16] <= (rollover_6 & orc_7 > 15) ? JPEG_ro_bs_4[16] : JPEG_bs_4[16]; |
JPEG_bs_5[15] <= (rollover_6 & orc_7 > 16) ? JPEG_ro_bs_4[15] : JPEG_bs_4[15]; |
JPEG_bs_5[14] <= (rollover_6 & orc_7 > 17) ? JPEG_ro_bs_4[14] : JPEG_bs_4[14]; |
JPEG_bs_5[13] <= (rollover_6 & orc_7 > 18) ? JPEG_ro_bs_4[13] : JPEG_bs_4[13]; |
JPEG_bs_5[12] <= (rollover_6 & orc_7 > 19) ? JPEG_ro_bs_4[12] : JPEG_bs_4[12]; |
JPEG_bs_5[11] <= (rollover_6 & orc_7 > 20) ? JPEG_ro_bs_4[11] : JPEG_bs_4[11]; |
JPEG_bs_5[10] <= (rollover_6 & orc_7 > 21) ? JPEG_ro_bs_4[10] : JPEG_bs_4[10]; |
JPEG_bs_5[9] <= (rollover_6 & orc_7 > 22) ? JPEG_ro_bs_4[9] : JPEG_bs_4[9]; |
JPEG_bs_5[8] <= (rollover_6 & orc_7 > 23) ? JPEG_ro_bs_4[8] : JPEG_bs_4[8]; |
JPEG_bs_5[7] <= (rollover_6 & orc_7 > 24) ? JPEG_ro_bs_4[7] : JPEG_bs_4[7]; |
JPEG_bs_5[6] <= (rollover_6 & orc_7 > 25) ? JPEG_ro_bs_4[6] : JPEG_bs_4[6]; |
JPEG_bs_5[5] <= (rollover_6 & orc_7 > 26) ? JPEG_ro_bs_4[5] : JPEG_bs_4[5]; |
JPEG_bs_5[4] <= (rollover_6 & orc_7 > 27) ? JPEG_ro_bs_4[4] : JPEG_bs_4[4]; |
JPEG_bs_5[3] <= (rollover_6 & orc_7 > 28) ? JPEG_ro_bs_4[3] : JPEG_bs_4[3]; |
JPEG_bs_5[2] <= (rollover_6 & orc_7 > 29) ? JPEG_ro_bs_4[2] : JPEG_bs_4[2]; |
JPEG_bs_5[1] <= (rollover_6 & orc_7 > 30) ? JPEG_ro_bs_4[1] : JPEG_bs_4[1]; |
JPEG_bs_5[0] <= JPEG_bs_4[0]; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_4 <= 0; JPEG_ro_bs_4 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_4 <= (old_orc_6 == 1) ? JPEG_bs_3 >> 1 : JPEG_bs_3; |
JPEG_ro_bs_4 <= (Cb12_edge_4 <= 1) ? JPEG_ro_bs_3 << 1 : JPEG_ro_bs_3; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_3 <= 0; old_orc_6 <= 0; JPEG_ro_bs_3 <= 0; |
Cb12_edge_4 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_3 <= (old_orc_5 >= 2) ? JPEG_bs_2 >> 2 : JPEG_bs_2; |
old_orc_6 <= (old_orc_5 >= 2) ? old_orc_5 - 2 : old_orc_5; |
JPEG_ro_bs_3 <= (Cb12_edge_3 <= 2) ? JPEG_ro_bs_2 << 2 : JPEG_ro_bs_2; |
Cb12_edge_4 <= (Cb12_edge_3 <= 2) ? Cb12_edge_3 : Cb12_edge_3 - 2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_2 <= 0; old_orc_5 <= 0; JPEG_ro_bs_2 <= 0; |
Cb12_edge_3 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_2 <= (old_orc_4 >= 4) ? JPEG_bs_1 >> 4 : JPEG_bs_1; |
old_orc_5 <= (old_orc_4 >= 4) ? old_orc_4 - 4 : old_orc_4; |
JPEG_ro_bs_2 <= (Cb12_edge_2 <= 4) ? JPEG_ro_bs_1 << 4 : JPEG_ro_bs_1; |
Cb12_edge_3 <= (Cb12_edge_2 <= 4) ? Cb12_edge_2 : Cb12_edge_2 - 4; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs_1 <= 0; old_orc_4 <= 0; JPEG_ro_bs_1 <= 0; |
Cb12_edge_2 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs_1 <= (old_orc_3 >= 8) ? JPEG_bs >> 8 : JPEG_bs; |
old_orc_4 <= (old_orc_3 >= 8) ? old_orc_3 - 8 : old_orc_3; |
JPEG_ro_bs_1 <= (Cb12_edge_1 <= 8) ? JPEG_ro_bs << 8 : JPEG_ro_bs; |
Cb12_edge_2 <= (Cb12_edge_1 <= 8) ? Cb12_edge_1 : Cb12_edge_1 - 8; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
JPEG_bs <= 0; old_orc_3 <= 0; JPEG_ro_bs <= 0; |
Cb12_edge_1 <= 0; Cb11_JPEG_bits_1 <= 0; |
end |
else if (enable_module) begin |
JPEG_bs <= (old_orc_2 >= 16) ? Cb11_JPEG_bits >> 10 : Cb11_JPEG_bits << 6; |
old_orc_3 <= (old_orc_2 >= 16) ? old_orc_2 - 16 : old_orc_2; |
JPEG_ro_bs <= (Cb12_edge <= 16) ? Cb11_JPEG_bits_1 << 16 : Cb11_JPEG_bits_1; |
Cb12_edge_1 <= (Cb12_edge <= 16) ? Cb12_edge : Cb12_edge - 16; |
Cb11_JPEG_bits_1 <= Cb11_JPEG_bits; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_JPEG_bits <= 0; Cb12_edge <= 0; |
end |
else if (enable_module) begin |
Cb12_JPEG_bits[25] <= (Cb12_Huff_shift_1 >= 16) ? Cb12_JPEG_LSBs_4[25] : Cb12_Huff_2[15]; |
Cb12_JPEG_bits[24] <= (Cb12_Huff_shift_1 >= 15) ? Cb12_JPEG_LSBs_4[24] : Cb12_Huff_2[14]; |
Cb12_JPEG_bits[23] <= (Cb12_Huff_shift_1 >= 14) ? Cb12_JPEG_LSBs_4[23] : Cb12_Huff_2[13]; |
Cb12_JPEG_bits[22] <= (Cb12_Huff_shift_1 >= 13) ? Cb12_JPEG_LSBs_4[22] : Cb12_Huff_2[12]; |
Cb12_JPEG_bits[21] <= (Cb12_Huff_shift_1 >= 12) ? Cb12_JPEG_LSBs_4[21] : Cb12_Huff_2[11]; |
Cb12_JPEG_bits[20] <= (Cb12_Huff_shift_1 >= 11) ? Cb12_JPEG_LSBs_4[20] : Cb12_Huff_2[10]; |
Cb12_JPEG_bits[19] <= (Cb12_Huff_shift_1 >= 10) ? Cb12_JPEG_LSBs_4[19] : Cb12_Huff_2[9]; |
Cb12_JPEG_bits[18] <= (Cb12_Huff_shift_1 >= 9) ? Cb12_JPEG_LSBs_4[18] : Cb12_Huff_2[8]; |
Cb12_JPEG_bits[17] <= (Cb12_Huff_shift_1 >= 8) ? Cb12_JPEG_LSBs_4[17] : Cb12_Huff_2[7]; |
Cb12_JPEG_bits[16] <= (Cb12_Huff_shift_1 >= 7) ? Cb12_JPEG_LSBs_4[16] : Cb12_Huff_2[6]; |
Cb12_JPEG_bits[15] <= (Cb12_Huff_shift_1 >= 6) ? Cb12_JPEG_LSBs_4[15] : Cb12_Huff_2[5]; |
Cb12_JPEG_bits[14] <= (Cb12_Huff_shift_1 >= 5) ? Cb12_JPEG_LSBs_4[14] : Cb12_Huff_2[4]; |
Cb12_JPEG_bits[13] <= (Cb12_Huff_shift_1 >= 4) ? Cb12_JPEG_LSBs_4[13] : Cb12_Huff_2[3]; |
Cb12_JPEG_bits[12] <= (Cb12_Huff_shift_1 >= 3) ? Cb12_JPEG_LSBs_4[12] : Cb12_Huff_2[2]; |
Cb12_JPEG_bits[11] <= (Cb12_Huff_shift_1 >= 2) ? Cb12_JPEG_LSBs_4[11] : Cb12_Huff_2[1]; |
Cb12_JPEG_bits[10] <= (Cb12_Huff_shift_1 >= 1) ? Cb12_JPEG_LSBs_4[10] : Cb12_Huff_2[0]; |
Cb12_JPEG_bits[9:0] <= Cb12_JPEG_LSBs_4[9:0]; |
Cb12_edge <= old_orc_2 + 26; // 26 is the size of Cb11_JPEG_bits |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_JPEG_bits <= 0; |
end |
else if (enable_7) begin |
Cb11_JPEG_bits[25] <= (Cb11_Huff_shift_1 >= 11) ? Cb11_JPEG_LSBs_3[21] : Cb11_Huff_2[10]; |
Cb11_JPEG_bits[24] <= (Cb11_Huff_shift_1 >= 10) ? Cb11_JPEG_LSBs_3[20] : Cb11_Huff_2[9]; |
Cb11_JPEG_bits[23] <= (Cb11_Huff_shift_1 >= 9) ? Cb11_JPEG_LSBs_3[19] : Cb11_Huff_2[8]; |
Cb11_JPEG_bits[22] <= (Cb11_Huff_shift_1 >= 8) ? Cb11_JPEG_LSBs_3[18] : Cb11_Huff_2[7]; |
Cb11_JPEG_bits[21] <= (Cb11_Huff_shift_1 >= 7) ? Cb11_JPEG_LSBs_3[17] : Cb11_Huff_2[6]; |
Cb11_JPEG_bits[20] <= (Cb11_Huff_shift_1 >= 6) ? Cb11_JPEG_LSBs_3[16] : Cb11_Huff_2[5]; |
Cb11_JPEG_bits[19] <= (Cb11_Huff_shift_1 >= 5) ? Cb11_JPEG_LSBs_3[15] : Cb11_Huff_2[4]; |
Cb11_JPEG_bits[18] <= (Cb11_Huff_shift_1 >= 4) ? Cb11_JPEG_LSBs_3[14] : Cb11_Huff_2[3]; |
Cb11_JPEG_bits[17] <= (Cb11_Huff_shift_1 >= 3) ? Cb11_JPEG_LSBs_3[13] : Cb11_Huff_2[2]; |
Cb11_JPEG_bits[16] <= (Cb11_Huff_shift_1 >= 2) ? Cb11_JPEG_LSBs_3[12] : Cb11_Huff_2[1]; |
Cb11_JPEG_bits[15] <= (Cb11_Huff_shift_1 >= 1) ? Cb11_JPEG_LSBs_3[11] : Cb11_Huff_2[0]; |
Cb11_JPEG_bits[14:4] <= Cb11_JPEG_LSBs_3[10:0]; |
end |
else if (enable_latch_8) begin |
Cb11_JPEG_bits <= Cb12_JPEG_bits; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_oc_1 <= 0; Cb12_JPEG_LSBs_4 <= 0; |
Cb12_Huff_2 <= 0; Cb12_Huff_shift_1 <= 0; |
end |
else if (enable_module) begin |
Cb12_oc_1 <= (Cb12_et_zero_5 & !code_15_0 & block_counter != 67) ? 0 : |
Cb12_bits_3 + Cb12_Huff_count_1; |
Cb12_JPEG_LSBs_4 <= Cb12_JPEG_LSBs_3 << Cb12_Huff_shift; |
Cb12_Huff_2 <= Cb12_Huff_1; |
Cb12_Huff_shift_1 <= Cb12_Huff_shift; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_JPEG_LSBs_3 <= 0; Cb11_Huff_2 <= 0; |
Cb11_Huff_shift_1 <= 0; |
end |
else if (enable_6) begin |
Cb11_JPEG_LSBs_3 <= Cb11_JPEG_LSBs_2 << Cb11_Huff_shift; |
Cb11_Huff_2 <= Cb11_Huff_1; |
Cb11_Huff_shift_1 <= Cb11_Huff_shift; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_Huff_shift <= 0; |
Cb12_Huff_1 <= 0; Cb12_JPEG_LSBs_3 <= 0; Cb12_bits_3 <= 0; |
Cb12_Huff_count_1 <= 0; Cb12_et_zero_5 <= 0; code_15_0 <= 0; |
end |
else if (enable_module) begin |
Cb12_Huff_shift <= 16 - Cb12_Huff_count; |
Cb12_Huff_1 <= Cb12_Huff; |
Cb12_JPEG_LSBs_3 <= Cb12_JPEG_LSBs_2; |
Cb12_bits_3 <= Cb12_bits_2; |
Cb12_Huff_count_1 <= Cb12_Huff_count; |
Cb12_et_zero_5 <= Cb12_et_zero_4; |
code_15_0 <= zrl_et_15 & !end_of_block; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_output_count <= 0; Cb11_JPEG_LSBs_2 <= 0; Cb11_Huff_shift <= 0; |
Cb11_Huff_1 <= 0; |
end |
else if (enable_5) begin |
Cb11_output_count <= Cb11_bits_1 + Cb11_Huff_count; |
Cb11_JPEG_LSBs_2 <= Cb11_JPEG_LSBs_1 << Cb11_amp_shift; |
Cb11_Huff_shift <= 11 - Cb11_Huff_count; |
Cb11_Huff_1 <= Cb11_Huff; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_JPEG_LSBs_2 <= 0; |
Cb12_Huff <= 0; Cb12_Huff_count <= 0; Cb12_bits_2 <= 0; |
Cb12_et_zero_4 <= 0; zrl_et_15 <= 0; zrl_3 <= 0; |
end |
else if (enable_module) begin |
Cb12_JPEG_LSBs_2 <= Cb12_JPEG_LSBs_1 << Cb12_amp_shift; |
Cb12_Huff <= Cb_AC[Cb12_code_entry]; |
Cb12_Huff_count <= Cb_AC_code_length[Cb12_code_entry]; |
Cb12_bits_2 <= Cb12_bits_1; |
Cb12_et_zero_4 <= Cb12_et_zero_3; |
zrl_et_15 <= zrl_3 == 15; |
zrl_3 <= zrl_2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_Huff <= 0; Cb11_Huff_count <= 0; Cb11_amp_shift <= 0; |
Cb11_JPEG_LSBs_1 <= 0; Cb11_bits_1 <= 0; |
end |
else if (enable_4) begin |
Cb11_Huff[10:0] <= Cb_DC[Cb11_bits]; |
Cb11_Huff_count <= Cb_DC_code_length[Cb11_bits]; |
Cb11_amp_shift <= 11 - Cb11_bits; |
Cb11_JPEG_LSBs_1 <= Cb11_JPEG_LSBs; |
Cb11_bits_1 <= Cb11_bits; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_code_entry <= 0; Cb12_JPEG_LSBs_1 <= 0; Cb12_amp_shift <= 0; |
Cb12_bits_1 <= 0; Cb12_et_zero_3 <= 0; zrl_2 <= 0; |
end |
else if (enable_module) begin |
Cb12_code_entry <= Cb_AC_run_code[code_index]; |
Cb12_JPEG_LSBs_1 <= Cb12_JPEG_LSBs; |
Cb12_amp_shift <= 10 - Cb12_bits; |
Cb12_bits_1 <= Cb12_bits; |
Cb12_et_zero_3 <= Cb12_et_zero_2; |
zrl_2 <= zrl_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_bits <= 0; Cb11_JPEG_LSBs <= 0; |
end |
else if (enable_3) begin |
Cb11_bits <= Cb11_msb ? Cb11_bits_neg : Cb11_bits_pos; |
Cb11_JPEG_LSBs <= Cb11_amp[10:0]; // The top bit of Cb11_amp is the sign bit |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_bits <= 0; Cb12_JPEG_LSBs <= 0; zrl_1 <= 0; |
Cb12_et_zero_2 <= 0; |
end |
else if (enable_module) begin |
Cb12_bits <= Cb12_msb_1 ? Cb12_bits_neg : Cb12_bits_pos; |
Cb12_JPEG_LSBs <= Cb12_amp[9:0]; // The top bit of Cb12_amp is the sign bit |
zrl_1 <= block_counter == 62 & Cb12_et_zero ? 0 : zero_run_length; |
Cb12_et_zero_2 <= Cb12_et_zero_1; |
end |
end |
|
// Cb11_amp is the amplitude that will be represented in bits in the |
// JPEG code, following the run length code |
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_amp <= 0; |
end |
else if (enable_2) begin |
Cb11_amp <= Cb11_msb ? Cb11_1_neg : Cb11_1_pos; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) |
zero_run_length <= 0; |
else if (enable) |
zero_run_length <= 0; |
else if (enable_module) |
zero_run_length <= Cb12_et_zero ? zero_run_length + 1: 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_amp <= 0; |
Cb12_et_zero_1 <= 0; Cb12_msb_1 <= 0; |
end |
else if (enable_module) begin |
Cb12_amp <= Cb12_msb ? Cb12_neg : Cb12_pos; |
Cb12_et_zero_1 <= Cb12_et_zero; |
Cb12_msb_1 <= Cb12_msb; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_1_pos <= 0; Cb11_1_neg <= 0; Cb11_msb <= 0; |
Cb11_previous <= 0; |
end |
else if (enable_1) begin |
Cb11_1_pos <= Cb11_diff; |
Cb11_1_neg <= Cb11_diff - 1; |
Cb11_msb <= Cb11_diff[11]; |
Cb11_previous <= Cb11_1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb12_pos <= 0; Cb12_neg <= 0; Cb12_msb <= 0; Cb12_et_zero <= 0; |
Cb13_pos <= 0; Cb13_neg <= 0; Cb13_msb <= 0; Cb13_et_zero <= 0; |
Cb14_pos <= 0; Cb14_neg <= 0; Cb14_msb <= 0; Cb14_et_zero <= 0; |
Cb15_pos <= 0; Cb15_neg <= 0; Cb15_msb <= 0; Cb15_et_zero <= 0; |
Cb16_pos <= 0; Cb16_neg <= 0; Cb16_msb <= 0; Cb16_et_zero <= 0; |
Cb17_pos <= 0; Cb17_neg <= 0; Cb17_msb <= 0; Cb17_et_zero <= 0; |
Cb18_pos <= 0; Cb18_neg <= 0; Cb18_msb <= 0; Cb18_et_zero <= 0; |
Cb21_pos <= 0; Cb21_neg <= 0; Cb21_msb <= 0; Cb21_et_zero <= 0; |
Cb22_pos <= 0; Cb22_neg <= 0; Cb22_msb <= 0; Cb22_et_zero <= 0; |
Cb23_pos <= 0; Cb23_neg <= 0; Cb23_msb <= 0; Cb23_et_zero <= 0; |
Cb24_pos <= 0; Cb24_neg <= 0; Cb24_msb <= 0; Cb24_et_zero <= 0; |
Cb25_pos <= 0; Cb25_neg <= 0; Cb25_msb <= 0; Cb25_et_zero <= 0; |
Cb26_pos <= 0; Cb26_neg <= 0; Cb26_msb <= 0; Cb26_et_zero <= 0; |
Cb27_pos <= 0; Cb27_neg <= 0; Cb27_msb <= 0; Cb27_et_zero <= 0; |
Cb28_pos <= 0; Cb28_neg <= 0; Cb28_msb <= 0; Cb28_et_zero <= 0; |
Cb31_pos <= 0; Cb31_neg <= 0; Cb31_msb <= 0; Cb31_et_zero <= 0; |
Cb32_pos <= 0; Cb32_neg <= 0; Cb32_msb <= 0; Cb32_et_zero <= 0; |
Cb33_pos <= 0; Cb33_neg <= 0; Cb33_msb <= 0; Cb33_et_zero <= 0; |
Cb34_pos <= 0; Cb34_neg <= 0; Cb34_msb <= 0; Cb34_et_zero <= 0; |
Cb35_pos <= 0; Cb35_neg <= 0; Cb35_msb <= 0; Cb35_et_zero <= 0; |
Cb36_pos <= 0; Cb36_neg <= 0; Cb36_msb <= 0; Cb36_et_zero <= 0; |
Cb37_pos <= 0; Cb37_neg <= 0; Cb37_msb <= 0; Cb37_et_zero <= 0; |
Cb38_pos <= 0; Cb38_neg <= 0; Cb38_msb <= 0; Cb38_et_zero <= 0; |
Cb41_pos <= 0; Cb41_neg <= 0; Cb41_msb <= 0; Cb41_et_zero <= 0; |
Cb42_pos <= 0; Cb42_neg <= 0; Cb42_msb <= 0; Cb42_et_zero <= 0; |
Cb43_pos <= 0; Cb43_neg <= 0; Cb43_msb <= 0; Cb43_et_zero <= 0; |
Cb44_pos <= 0; Cb44_neg <= 0; Cb44_msb <= 0; Cb44_et_zero <= 0; |
Cb45_pos <= 0; Cb45_neg <= 0; Cb45_msb <= 0; Cb45_et_zero <= 0; |
Cb46_pos <= 0; Cb46_neg <= 0; Cb46_msb <= 0; Cb46_et_zero <= 0; |
Cb47_pos <= 0; Cb47_neg <= 0; Cb47_msb <= 0; Cb47_et_zero <= 0; |
Cb48_pos <= 0; Cb48_neg <= 0; Cb48_msb <= 0; Cb48_et_zero <= 0; |
Cb51_pos <= 0; Cb51_neg <= 0; Cb51_msb <= 0; Cb51_et_zero <= 0; |
Cb52_pos <= 0; Cb52_neg <= 0; Cb52_msb <= 0; Cb52_et_zero <= 0; |
Cb53_pos <= 0; Cb53_neg <= 0; Cb53_msb <= 0; Cb53_et_zero <= 0; |
Cb54_pos <= 0; Cb54_neg <= 0; Cb54_msb <= 0; Cb54_et_zero <= 0; |
Cb55_pos <= 0; Cb55_neg <= 0; Cb55_msb <= 0; Cb55_et_zero <= 0; |
Cb56_pos <= 0; Cb56_neg <= 0; Cb56_msb <= 0; Cb56_et_zero <= 0; |
Cb57_pos <= 0; Cb57_neg <= 0; Cb57_msb <= 0; Cb57_et_zero <= 0; |
Cb58_pos <= 0; Cb58_neg <= 0; Cb58_msb <= 0; Cb58_et_zero <= 0; |
Cb61_pos <= 0; Cb61_neg <= 0; Cb61_msb <= 0; Cb61_et_zero <= 0; |
Cb62_pos <= 0; Cb62_neg <= 0; Cb62_msb <= 0; Cb62_et_zero <= 0; |
Cb63_pos <= 0; Cb63_neg <= 0; Cb63_msb <= 0; Cb63_et_zero <= 0; |
Cb64_pos <= 0; Cb64_neg <= 0; Cb64_msb <= 0; Cb64_et_zero <= 0; |
Cb65_pos <= 0; Cb65_neg <= 0; Cb65_msb <= 0; Cb65_et_zero <= 0; |
Cb66_pos <= 0; Cb66_neg <= 0; Cb66_msb <= 0; Cb66_et_zero <= 0; |
Cb67_pos <= 0; Cb67_neg <= 0; Cb67_msb <= 0; Cb67_et_zero <= 0; |
Cb68_pos <= 0; Cb68_neg <= 0; Cb68_msb <= 0; Cb68_et_zero <= 0; |
Cb71_pos <= 0; Cb71_neg <= 0; Cb71_msb <= 0; Cb71_et_zero <= 0; |
Cb72_pos <= 0; Cb72_neg <= 0; Cb72_msb <= 0; Cb72_et_zero <= 0; |
Cb73_pos <= 0; Cb73_neg <= 0; Cb73_msb <= 0; Cb73_et_zero <= 0; |
Cb74_pos <= 0; Cb74_neg <= 0; Cb74_msb <= 0; Cb74_et_zero <= 0; |
Cb75_pos <= 0; Cb75_neg <= 0; Cb75_msb <= 0; Cb75_et_zero <= 0; |
Cb76_pos <= 0; Cb76_neg <= 0; Cb76_msb <= 0; Cb76_et_zero <= 0; |
Cb77_pos <= 0; Cb77_neg <= 0; Cb77_msb <= 0; Cb77_et_zero <= 0; |
Cb78_pos <= 0; Cb78_neg <= 0; Cb78_msb <= 0; Cb78_et_zero <= 0; |
Cb81_pos <= 0; Cb81_neg <= 0; Cb81_msb <= 0; Cb81_et_zero <= 0; |
Cb82_pos <= 0; Cb82_neg <= 0; Cb82_msb <= 0; Cb82_et_zero <= 0; |
Cb83_pos <= 0; Cb83_neg <= 0; Cb83_msb <= 0; Cb83_et_zero <= 0; |
Cb84_pos <= 0; Cb84_neg <= 0; Cb84_msb <= 0; Cb84_et_zero <= 0; |
Cb85_pos <= 0; Cb85_neg <= 0; Cb85_msb <= 0; Cb85_et_zero <= 0; |
Cb86_pos <= 0; Cb86_neg <= 0; Cb86_msb <= 0; Cb86_et_zero <= 0; |
Cb87_pos <= 0; Cb87_neg <= 0; Cb87_msb <= 0; Cb87_et_zero <= 0; |
Cb88_pos <= 0; Cb88_neg <= 0; Cb88_msb <= 0; Cb88_et_zero <= 0; |
end |
else if (enable) begin |
Cb12_pos <= Cb12; |
Cb12_neg <= Cb12 - 1; |
Cb12_msb <= Cb12[10]; |
Cb12_et_zero <= !(|Cb12); |
Cb13_pos <= Cb13; |
Cb13_neg <= Cb13 - 1; |
Cb13_msb <= Cb13[10]; |
Cb13_et_zero <= !(|Cb13); |
Cb14_pos <= Cb14; |
Cb14_neg <= Cb14 - 1; |
Cb14_msb <= Cb14[10]; |
Cb14_et_zero <= !(|Cb14); |
Cb15_pos <= Cb15; |
Cb15_neg <= Cb15 - 1; |
Cb15_msb <= Cb15[10]; |
Cb15_et_zero <= !(|Cb15); |
Cb16_pos <= Cb16; |
Cb16_neg <= Cb16 - 1; |
Cb16_msb <= Cb16[10]; |
Cb16_et_zero <= !(|Cb16); |
Cb17_pos <= Cb17; |
Cb17_neg <= Cb17 - 1; |
Cb17_msb <= Cb17[10]; |
Cb17_et_zero <= !(|Cb17); |
Cb18_pos <= Cb18; |
Cb18_neg <= Cb18 - 1; |
Cb18_msb <= Cb18[10]; |
Cb18_et_zero <= !(|Cb18); |
Cb21_pos <= Cb21; |
Cb21_neg <= Cb21 - 1; |
Cb21_msb <= Cb21[10]; |
Cb21_et_zero <= !(|Cb21); |
Cb22_pos <= Cb22; |
Cb22_neg <= Cb22 - 1; |
Cb22_msb <= Cb22[10]; |
Cb22_et_zero <= !(|Cb22); |
Cb23_pos <= Cb23; |
Cb23_neg <= Cb23 - 1; |
Cb23_msb <= Cb23[10]; |
Cb23_et_zero <= !(|Cb23); |
Cb24_pos <= Cb24; |
Cb24_neg <= Cb24 - 1; |
Cb24_msb <= Cb24[10]; |
Cb24_et_zero <= !(|Cb24); |
Cb25_pos <= Cb25; |
Cb25_neg <= Cb25 - 1; |
Cb25_msb <= Cb25[10]; |
Cb25_et_zero <= !(|Cb25); |
Cb26_pos <= Cb26; |
Cb26_neg <= Cb26 - 1; |
Cb26_msb <= Cb26[10]; |
Cb26_et_zero <= !(|Cb26); |
Cb27_pos <= Cb27; |
Cb27_neg <= Cb27 - 1; |
Cb27_msb <= Cb27[10]; |
Cb27_et_zero <= !(|Cb27); |
Cb28_pos <= Cb28; |
Cb28_neg <= Cb28 - 1; |
Cb28_msb <= Cb28[10]; |
Cb28_et_zero <= !(|Cb28); |
Cb31_pos <= Cb31; |
Cb31_neg <= Cb31 - 1; |
Cb31_msb <= Cb31[10]; |
Cb31_et_zero <= !(|Cb31); |
Cb32_pos <= Cb32; |
Cb32_neg <= Cb32 - 1; |
Cb32_msb <= Cb32[10]; |
Cb32_et_zero <= !(|Cb32); |
Cb33_pos <= Cb33; |
Cb33_neg <= Cb33 - 1; |
Cb33_msb <= Cb33[10]; |
Cb33_et_zero <= !(|Cb33); |
Cb34_pos <= Cb34; |
Cb34_neg <= Cb34 - 1; |
Cb34_msb <= Cb34[10]; |
Cb34_et_zero <= !(|Cb34); |
Cb35_pos <= Cb35; |
Cb35_neg <= Cb35 - 1; |
Cb35_msb <= Cb35[10]; |
Cb35_et_zero <= !(|Cb35); |
Cb36_pos <= Cb36; |
Cb36_neg <= Cb36 - 1; |
Cb36_msb <= Cb36[10]; |
Cb36_et_zero <= !(|Cb36); |
Cb37_pos <= Cb37; |
Cb37_neg <= Cb37 - 1; |
Cb37_msb <= Cb37[10]; |
Cb37_et_zero <= !(|Cb37); |
Cb38_pos <= Cb38; |
Cb38_neg <= Cb38 - 1; |
Cb38_msb <= Cb38[10]; |
Cb38_et_zero <= !(|Cb38); |
Cb41_pos <= Cb41; |
Cb41_neg <= Cb41 - 1; |
Cb41_msb <= Cb41[10]; |
Cb41_et_zero <= !(|Cb41); |
Cb42_pos <= Cb42; |
Cb42_neg <= Cb42 - 1; |
Cb42_msb <= Cb42[10]; |
Cb42_et_zero <= !(|Cb42); |
Cb43_pos <= Cb43; |
Cb43_neg <= Cb43 - 1; |
Cb43_msb <= Cb43[10]; |
Cb43_et_zero <= !(|Cb43); |
Cb44_pos <= Cb44; |
Cb44_neg <= Cb44 - 1; |
Cb44_msb <= Cb44[10]; |
Cb44_et_zero <= !(|Cb44); |
Cb45_pos <= Cb45; |
Cb45_neg <= Cb45 - 1; |
Cb45_msb <= Cb45[10]; |
Cb45_et_zero <= !(|Cb45); |
Cb46_pos <= Cb46; |
Cb46_neg <= Cb46 - 1; |
Cb46_msb <= Cb46[10]; |
Cb46_et_zero <= !(|Cb46); |
Cb47_pos <= Cb47; |
Cb47_neg <= Cb47 - 1; |
Cb47_msb <= Cb47[10]; |
Cb47_et_zero <= !(|Cb47); |
Cb48_pos <= Cb48; |
Cb48_neg <= Cb48 - 1; |
Cb48_msb <= Cb48[10]; |
Cb48_et_zero <= !(|Cb48); |
Cb51_pos <= Cb51; |
Cb51_neg <= Cb51 - 1; |
Cb51_msb <= Cb51[10]; |
Cb51_et_zero <= !(|Cb51); |
Cb52_pos <= Cb52; |
Cb52_neg <= Cb52 - 1; |
Cb52_msb <= Cb52[10]; |
Cb52_et_zero <= !(|Cb52); |
Cb53_pos <= Cb53; |
Cb53_neg <= Cb53 - 1; |
Cb53_msb <= Cb53[10]; |
Cb53_et_zero <= !(|Cb53); |
Cb54_pos <= Cb54; |
Cb54_neg <= Cb54 - 1; |
Cb54_msb <= Cb54[10]; |
Cb54_et_zero <= !(|Cb54); |
Cb55_pos <= Cb55; |
Cb55_neg <= Cb55 - 1; |
Cb55_msb <= Cb55[10]; |
Cb55_et_zero <= !(|Cb55); |
Cb56_pos <= Cb56; |
Cb56_neg <= Cb56 - 1; |
Cb56_msb <= Cb56[10]; |
Cb56_et_zero <= !(|Cb56); |
Cb57_pos <= Cb57; |
Cb57_neg <= Cb57 - 1; |
Cb57_msb <= Cb57[10]; |
Cb57_et_zero <= !(|Cb57); |
Cb58_pos <= Cb58; |
Cb58_neg <= Cb58 - 1; |
Cb58_msb <= Cb58[10]; |
Cb58_et_zero <= !(|Cb58); |
Cb61_pos <= Cb61; |
Cb61_neg <= Cb61 - 1; |
Cb61_msb <= Cb61[10]; |
Cb61_et_zero <= !(|Cb61); |
Cb62_pos <= Cb62; |
Cb62_neg <= Cb62 - 1; |
Cb62_msb <= Cb62[10]; |
Cb62_et_zero <= !(|Cb62); |
Cb63_pos <= Cb63; |
Cb63_neg <= Cb63 - 1; |
Cb63_msb <= Cb63[10]; |
Cb63_et_zero <= !(|Cb63); |
Cb64_pos <= Cb64; |
Cb64_neg <= Cb64 - 1; |
Cb64_msb <= Cb64[10]; |
Cb64_et_zero <= !(|Cb64); |
Cb65_pos <= Cb65; |
Cb65_neg <= Cb65 - 1; |
Cb65_msb <= Cb65[10]; |
Cb65_et_zero <= !(|Cb65); |
Cb66_pos <= Cb66; |
Cb66_neg <= Cb66 - 1; |
Cb66_msb <= Cb66[10]; |
Cb66_et_zero <= !(|Cb66); |
Cb67_pos <= Cb67; |
Cb67_neg <= Cb67 - 1; |
Cb67_msb <= Cb67[10]; |
Cb67_et_zero <= !(|Cb67); |
Cb68_pos <= Cb68; |
Cb68_neg <= Cb68 - 1; |
Cb68_msb <= Cb68[10]; |
Cb68_et_zero <= !(|Cb68); |
Cb71_pos <= Cb71; |
Cb71_neg <= Cb71 - 1; |
Cb71_msb <= Cb71[10]; |
Cb71_et_zero <= !(|Cb71); |
Cb72_pos <= Cb72; |
Cb72_neg <= Cb72 - 1; |
Cb72_msb <= Cb72[10]; |
Cb72_et_zero <= !(|Cb72); |
Cb73_pos <= Cb73; |
Cb73_neg <= Cb73 - 1; |
Cb73_msb <= Cb73[10]; |
Cb73_et_zero <= !(|Cb73); |
Cb74_pos <= Cb74; |
Cb74_neg <= Cb74 - 1; |
Cb74_msb <= Cb74[10]; |
Cb74_et_zero <= !(|Cb74); |
Cb75_pos <= Cb75; |
Cb75_neg <= Cb75 - 1; |
Cb75_msb <= Cb75[10]; |
Cb75_et_zero <= !(|Cb75); |
Cb76_pos <= Cb76; |
Cb76_neg <= Cb76 - 1; |
Cb76_msb <= Cb76[10]; |
Cb76_et_zero <= !(|Cb76); |
Cb77_pos <= Cb77; |
Cb77_neg <= Cb77 - 1; |
Cb77_msb <= Cb77[10]; |
Cb77_et_zero <= !(|Cb77); |
Cb78_pos <= Cb78; |
Cb78_neg <= Cb78 - 1; |
Cb78_msb <= Cb78[10]; |
Cb78_et_zero <= !(|Cb78); |
Cb81_pos <= Cb81; |
Cb81_neg <= Cb81 - 1; |
Cb81_msb <= Cb81[10]; |
Cb81_et_zero <= !(|Cb81); |
Cb82_pos <= Cb82; |
Cb82_neg <= Cb82 - 1; |
Cb82_msb <= Cb82[10]; |
Cb82_et_zero <= !(|Cb82); |
Cb83_pos <= Cb83; |
Cb83_neg <= Cb83 - 1; |
Cb83_msb <= Cb83[10]; |
Cb83_et_zero <= !(|Cb83); |
Cb84_pos <= Cb84; |
Cb84_neg <= Cb84 - 1; |
Cb84_msb <= Cb84[10]; |
Cb84_et_zero <= !(|Cb84); |
Cb85_pos <= Cb85; |
Cb85_neg <= Cb85 - 1; |
Cb85_msb <= Cb85[10]; |
Cb85_et_zero <= !(|Cb85); |
Cb86_pos <= Cb86; |
Cb86_neg <= Cb86 - 1; |
Cb86_msb <= Cb86[10]; |
Cb86_et_zero <= !(|Cb86); |
Cb87_pos <= Cb87; |
Cb87_neg <= Cb87 - 1; |
Cb87_msb <= Cb87[10]; |
Cb87_et_zero <= !(|Cb87); |
Cb88_pos <= Cb88; |
Cb88_neg <= Cb88 - 1; |
Cb88_msb <= Cb88[10]; |
Cb88_et_zero <= !(|Cb88); |
end |
else if (enable_module) begin |
Cb12_pos <= Cb21_pos; |
Cb12_neg <= Cb21_neg; |
Cb12_msb <= Cb21_msb; |
Cb12_et_zero <= Cb21_et_zero; |
Cb21_pos <= Cb31_pos; |
Cb21_neg <= Cb31_neg; |
Cb21_msb <= Cb31_msb; |
Cb21_et_zero <= Cb31_et_zero; |
Cb31_pos <= Cb22_pos; |
Cb31_neg <= Cb22_neg; |
Cb31_msb <= Cb22_msb; |
Cb31_et_zero <= Cb22_et_zero; |
Cb22_pos <= Cb13_pos; |
Cb22_neg <= Cb13_neg; |
Cb22_msb <= Cb13_msb; |
Cb22_et_zero <= Cb13_et_zero; |
Cb13_pos <= Cb14_pos; |
Cb13_neg <= Cb14_neg; |
Cb13_msb <= Cb14_msb; |
Cb13_et_zero <= Cb14_et_zero; |
Cb14_pos <= Cb23_pos; |
Cb14_neg <= Cb23_neg; |
Cb14_msb <= Cb23_msb; |
Cb14_et_zero <= Cb23_et_zero; |
Cb23_pos <= Cb32_pos; |
Cb23_neg <= Cb32_neg; |
Cb23_msb <= Cb32_msb; |
Cb23_et_zero <= Cb32_et_zero; |
Cb32_pos <= Cb41_pos; |
Cb32_neg <= Cb41_neg; |
Cb32_msb <= Cb41_msb; |
Cb32_et_zero <= Cb41_et_zero; |
Cb41_pos <= Cb51_pos; |
Cb41_neg <= Cb51_neg; |
Cb41_msb <= Cb51_msb; |
Cb41_et_zero <= Cb51_et_zero; |
Cb51_pos <= Cb42_pos; |
Cb51_neg <= Cb42_neg; |
Cb51_msb <= Cb42_msb; |
Cb51_et_zero <= Cb42_et_zero; |
Cb42_pos <= Cb33_pos; |
Cb42_neg <= Cb33_neg; |
Cb42_msb <= Cb33_msb; |
Cb42_et_zero <= Cb33_et_zero; |
Cb33_pos <= Cb24_pos; |
Cb33_neg <= Cb24_neg; |
Cb33_msb <= Cb24_msb; |
Cb33_et_zero <= Cb24_et_zero; |
Cb24_pos <= Cb15_pos; |
Cb24_neg <= Cb15_neg; |
Cb24_msb <= Cb15_msb; |
Cb24_et_zero <= Cb15_et_zero; |
Cb15_pos <= Cb16_pos; |
Cb15_neg <= Cb16_neg; |
Cb15_msb <= Cb16_msb; |
Cb15_et_zero <= Cb16_et_zero; |
Cb16_pos <= Cb25_pos; |
Cb16_neg <= Cb25_neg; |
Cb16_msb <= Cb25_msb; |
Cb16_et_zero <= Cb25_et_zero; |
Cb25_pos <= Cb34_pos; |
Cb25_neg <= Cb34_neg; |
Cb25_msb <= Cb34_msb; |
Cb25_et_zero <= Cb34_et_zero; |
Cb34_pos <= Cb43_pos; |
Cb34_neg <= Cb43_neg; |
Cb34_msb <= Cb43_msb; |
Cb34_et_zero <= Cb43_et_zero; |
Cb43_pos <= Cb52_pos; |
Cb43_neg <= Cb52_neg; |
Cb43_msb <= Cb52_msb; |
Cb43_et_zero <= Cb52_et_zero; |
Cb52_pos <= Cb61_pos; |
Cb52_neg <= Cb61_neg; |
Cb52_msb <= Cb61_msb; |
Cb52_et_zero <= Cb61_et_zero; |
Cb61_pos <= Cb71_pos; |
Cb61_neg <= Cb71_neg; |
Cb61_msb <= Cb71_msb; |
Cb61_et_zero <= Cb71_et_zero; |
Cb71_pos <= Cb62_pos; |
Cb71_neg <= Cb62_neg; |
Cb71_msb <= Cb62_msb; |
Cb71_et_zero <= Cb62_et_zero; |
Cb62_pos <= Cb53_pos; |
Cb62_neg <= Cb53_neg; |
Cb62_msb <= Cb53_msb; |
Cb62_et_zero <= Cb53_et_zero; |
Cb53_pos <= Cb44_pos; |
Cb53_neg <= Cb44_neg; |
Cb53_msb <= Cb44_msb; |
Cb53_et_zero <= Cb44_et_zero; |
Cb44_pos <= Cb35_pos; |
Cb44_neg <= Cb35_neg; |
Cb44_msb <= Cb35_msb; |
Cb44_et_zero <= Cb35_et_zero; |
Cb35_pos <= Cb26_pos; |
Cb35_neg <= Cb26_neg; |
Cb35_msb <= Cb26_msb; |
Cb35_et_zero <= Cb26_et_zero; |
Cb26_pos <= Cb17_pos; |
Cb26_neg <= Cb17_neg; |
Cb26_msb <= Cb17_msb; |
Cb26_et_zero <= Cb17_et_zero; |
Cb17_pos <= Cb18_pos; |
Cb17_neg <= Cb18_neg; |
Cb17_msb <= Cb18_msb; |
Cb17_et_zero <= Cb18_et_zero; |
Cb18_pos <= Cb27_pos; |
Cb18_neg <= Cb27_neg; |
Cb18_msb <= Cb27_msb; |
Cb18_et_zero <= Cb27_et_zero; |
Cb27_pos <= Cb36_pos; |
Cb27_neg <= Cb36_neg; |
Cb27_msb <= Cb36_msb; |
Cb27_et_zero <= Cb36_et_zero; |
Cb36_pos <= Cb45_pos; |
Cb36_neg <= Cb45_neg; |
Cb36_msb <= Cb45_msb; |
Cb36_et_zero <= Cb45_et_zero; |
Cb45_pos <= Cb54_pos; |
Cb45_neg <= Cb54_neg; |
Cb45_msb <= Cb54_msb; |
Cb45_et_zero <= Cb54_et_zero; |
Cb54_pos <= Cb63_pos; |
Cb54_neg <= Cb63_neg; |
Cb54_msb <= Cb63_msb; |
Cb54_et_zero <= Cb63_et_zero; |
Cb63_pos <= Cb72_pos; |
Cb63_neg <= Cb72_neg; |
Cb63_msb <= Cb72_msb; |
Cb63_et_zero <= Cb72_et_zero; |
Cb72_pos <= Cb81_pos; |
Cb72_neg <= Cb81_neg; |
Cb72_msb <= Cb81_msb; |
Cb72_et_zero <= Cb81_et_zero; |
Cb81_pos <= Cb82_pos; |
Cb81_neg <= Cb82_neg; |
Cb81_msb <= Cb82_msb; |
Cb81_et_zero <= Cb82_et_zero; |
Cb82_pos <= Cb73_pos; |
Cb82_neg <= Cb73_neg; |
Cb82_msb <= Cb73_msb; |
Cb82_et_zero <= Cb73_et_zero; |
Cb73_pos <= Cb64_pos; |
Cb73_neg <= Cb64_neg; |
Cb73_msb <= Cb64_msb; |
Cb73_et_zero <= Cb64_et_zero; |
Cb64_pos <= Cb55_pos; |
Cb64_neg <= Cb55_neg; |
Cb64_msb <= Cb55_msb; |
Cb64_et_zero <= Cb55_et_zero; |
Cb55_pos <= Cb46_pos; |
Cb55_neg <= Cb46_neg; |
Cb55_msb <= Cb46_msb; |
Cb55_et_zero <= Cb46_et_zero; |
Cb46_pos <= Cb37_pos; |
Cb46_neg <= Cb37_neg; |
Cb46_msb <= Cb37_msb; |
Cb46_et_zero <= Cb37_et_zero; |
Cb37_pos <= Cb28_pos; |
Cb37_neg <= Cb28_neg; |
Cb37_msb <= Cb28_msb; |
Cb37_et_zero <= Cb28_et_zero; |
Cb28_pos <= Cb38_pos; |
Cb28_neg <= Cb38_neg; |
Cb28_msb <= Cb38_msb; |
Cb28_et_zero <= Cb38_et_zero; |
Cb38_pos <= Cb47_pos; |
Cb38_neg <= Cb47_neg; |
Cb38_msb <= Cb47_msb; |
Cb38_et_zero <= Cb47_et_zero; |
Cb47_pos <= Cb56_pos; |
Cb47_neg <= Cb56_neg; |
Cb47_msb <= Cb56_msb; |
Cb47_et_zero <= Cb56_et_zero; |
Cb56_pos <= Cb65_pos; |
Cb56_neg <= Cb65_neg; |
Cb56_msb <= Cb65_msb; |
Cb56_et_zero <= Cb65_et_zero; |
Cb65_pos <= Cb74_pos; |
Cb65_neg <= Cb74_neg; |
Cb65_msb <= Cb74_msb; |
Cb65_et_zero <= Cb74_et_zero; |
Cb74_pos <= Cb83_pos; |
Cb74_neg <= Cb83_neg; |
Cb74_msb <= Cb83_msb; |
Cb74_et_zero <= Cb83_et_zero; |
Cb83_pos <= Cb84_pos; |
Cb83_neg <= Cb84_neg; |
Cb83_msb <= Cb84_msb; |
Cb83_et_zero <= Cb84_et_zero; |
Cb84_pos <= Cb75_pos; |
Cb84_neg <= Cb75_neg; |
Cb84_msb <= Cb75_msb; |
Cb84_et_zero <= Cb75_et_zero; |
Cb75_pos <= Cb66_pos; |
Cb75_neg <= Cb66_neg; |
Cb75_msb <= Cb66_msb; |
Cb75_et_zero <= Cb66_et_zero; |
Cb66_pos <= Cb57_pos; |
Cb66_neg <= Cb57_neg; |
Cb66_msb <= Cb57_msb; |
Cb66_et_zero <= Cb57_et_zero; |
Cb57_pos <= Cb48_pos; |
Cb57_neg <= Cb48_neg; |
Cb57_msb <= Cb48_msb; |
Cb57_et_zero <= Cb48_et_zero; |
Cb48_pos <= Cb58_pos; |
Cb48_neg <= Cb58_neg; |
Cb48_msb <= Cb58_msb; |
Cb48_et_zero <= Cb58_et_zero; |
Cb58_pos <= Cb67_pos; |
Cb58_neg <= Cb67_neg; |
Cb58_msb <= Cb67_msb; |
Cb58_et_zero <= Cb67_et_zero; |
Cb67_pos <= Cb76_pos; |
Cb67_neg <= Cb76_neg; |
Cb67_msb <= Cb76_msb; |
Cb67_et_zero <= Cb76_et_zero; |
Cb76_pos <= Cb85_pos; |
Cb76_neg <= Cb85_neg; |
Cb76_msb <= Cb85_msb; |
Cb76_et_zero <= Cb85_et_zero; |
Cb85_pos <= Cb86_pos; |
Cb85_neg <= Cb86_neg; |
Cb85_msb <= Cb86_msb; |
Cb85_et_zero <= Cb86_et_zero; |
Cb86_pos <= Cb77_pos; |
Cb86_neg <= Cb77_neg; |
Cb86_msb <= Cb77_msb; |
Cb86_et_zero <= Cb77_et_zero; |
Cb77_pos <= Cb68_pos; |
Cb77_neg <= Cb68_neg; |
Cb77_msb <= Cb68_msb; |
Cb77_et_zero <= Cb68_et_zero; |
Cb68_pos <= Cb78_pos; |
Cb68_neg <= Cb78_neg; |
Cb68_msb <= Cb78_msb; |
Cb68_et_zero <= Cb78_et_zero; |
Cb78_pos <= Cb87_pos; |
Cb78_neg <= Cb87_neg; |
Cb78_msb <= Cb87_msb; |
Cb78_et_zero <= Cb87_et_zero; |
Cb87_pos <= Cb88_pos; |
Cb87_neg <= Cb88_neg; |
Cb87_msb <= Cb88_msb; |
Cb87_et_zero <= Cb88_et_zero; |
Cb88_pos <= 0; |
Cb88_neg <= 0; |
Cb88_msb <= 0; |
Cb88_et_zero <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_diff <= 0; Cb11_1 <= 0; |
end |
else if (enable) begin // Need to sign extend Cb11 to 12 bits |
Cb11_diff <= {Cb11[10], Cb11} - Cb11_previous; |
Cb11_1 <= Cb11[10] ? { 1'b1, Cb11 } : { 1'b0, Cb11 }; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cb11_bits_pos <= 0; |
else if (Cb11_1_pos[10] == 1) |
Cb11_bits_pos <= 11; |
else if (Cb11_1_pos[9] == 1) |
Cb11_bits_pos <= 10; |
else if (Cb11_1_pos[8] == 1) |
Cb11_bits_pos <= 9; |
else if (Cb11_1_pos[7] == 1) |
Cb11_bits_pos <= 8; |
else if (Cb11_1_pos[6] == 1) |
Cb11_bits_pos <= 7; |
else if (Cb11_1_pos[5] == 1) |
Cb11_bits_pos <= 6; |
else if (Cb11_1_pos[4] == 1) |
Cb11_bits_pos <= 5; |
else if (Cb11_1_pos[3] == 1) |
Cb11_bits_pos <= 4; |
else if (Cb11_1_pos[2] == 1) |
Cb11_bits_pos <= 3; |
else if (Cb11_1_pos[1] == 1) |
Cb11_bits_pos <= 2; |
else if (Cb11_1_pos[0] == 1) |
Cb11_bits_pos <= 1; |
else |
Cb11_bits_pos <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cb11_bits_neg <= 0; |
else if (Cb11_1_neg[10] == 0) |
Cb11_bits_neg <= 11; |
else if (Cb11_1_neg[9] == 0) |
Cb11_bits_neg <= 10; |
else if (Cb11_1_neg[8] == 0) |
Cb11_bits_neg <= 9; |
else if (Cb11_1_neg[7] == 0) |
Cb11_bits_neg <= 8; |
else if (Cb11_1_neg[6] == 0) |
Cb11_bits_neg <= 7; |
else if (Cb11_1_neg[5] == 0) |
Cb11_bits_neg <= 6; |
else if (Cb11_1_neg[4] == 0) |
Cb11_bits_neg <= 5; |
else if (Cb11_1_neg[3] == 0) |
Cb11_bits_neg <= 4; |
else if (Cb11_1_neg[2] == 0) |
Cb11_bits_neg <= 3; |
else if (Cb11_1_neg[1] == 0) |
Cb11_bits_neg <= 2; |
else if (Cb11_1_neg[0] == 0) |
Cb11_bits_neg <= 1; |
else |
Cb11_bits_neg <= 0; |
end |
|
|
always @(posedge clk) |
begin |
if (rst) |
Cb12_bits_pos <= 0; |
else if (Cb12_pos[9] == 1) |
Cb12_bits_pos <= 10; |
else if (Cb12_pos[8] == 1) |
Cb12_bits_pos <= 9; |
else if (Cb12_pos[7] == 1) |
Cb12_bits_pos <= 8; |
else if (Cb12_pos[6] == 1) |
Cb12_bits_pos <= 7; |
else if (Cb12_pos[5] == 1) |
Cb12_bits_pos <= 6; |
else if (Cb12_pos[4] == 1) |
Cb12_bits_pos <= 5; |
else if (Cb12_pos[3] == 1) |
Cb12_bits_pos <= 4; |
else if (Cb12_pos[2] == 1) |
Cb12_bits_pos <= 3; |
else if (Cb12_pos[1] == 1) |
Cb12_bits_pos <= 2; |
else if (Cb12_pos[0] == 1) |
Cb12_bits_pos <= 1; |
else |
Cb12_bits_pos <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cb12_bits_neg <= 0; |
else if (Cb12_neg[9] == 0) |
Cb12_bits_neg <= 10; |
else if (Cb12_neg[8] == 0) |
Cb12_bits_neg <= 9; |
else if (Cb12_neg[7] == 0) |
Cb12_bits_neg <= 8; |
else if (Cb12_neg[6] == 0) |
Cb12_bits_neg <= 7; |
else if (Cb12_neg[5] == 0) |
Cb12_bits_neg <= 6; |
else if (Cb12_neg[4] == 0) |
Cb12_bits_neg <= 5; |
else if (Cb12_neg[3] == 0) |
Cb12_bits_neg <= 4; |
else if (Cb12_neg[2] == 0) |
Cb12_bits_neg <= 3; |
else if (Cb12_neg[1] == 0) |
Cb12_bits_neg <= 2; |
else if (Cb12_neg[0] == 0) |
Cb12_bits_neg <= 1; |
else |
Cb12_bits_neg <= 0; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_module <= 0; |
end |
else if (enable) begin |
enable_module <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_latch_7 <= 0; |
end |
else if (block_counter == 68) begin |
enable_latch_7 <= 0; |
end |
else if (enable_6) begin |
enable_latch_7 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_latch_8 <= 0; |
end |
else if (enable_7) begin |
enable_latch_8 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; |
enable_4 <= 0; enable_5 <= 0; enable_6 <= 0; |
enable_7 <= 0; enable_8 <= 0; enable_9 <= 0; |
enable_10 <= 0; enable_11 <= 0; enable_12 <= 0; |
enable_13 <= 0; |
end |
else begin |
enable_1 <= enable; enable_2 <= enable_1; enable_3 <= enable_2; |
enable_4 <= enable_3; enable_5 <= enable_4; enable_6 <= enable_5; |
enable_7 <= enable_6; enable_8 <= enable_7; enable_9 <= enable_8; |
enable_10 <= enable_9; enable_11 <= enable_10; enable_12 <= enable_11; |
enable_13 <= enable_12; |
end |
end |
|
/* These Cb DC and AC code lengths, run lengths, and bit codes |
were created from the Huffman table entries in the JPEG file header. |
For different Huffman tables for different images, these values |
below will need to be changed. I created a matlab file to automatically |
create these entries from the already encoded JPEG image. This matlab program |
won't be any help if you're starting from scratch with a .tif or other |
raw image file format. The values below come from a Huffman table, they |
do not actually create the Huffman table based on the probabilities of |
each code created from the image data. Cbou will need another program to |
create the optimal Huffman table, or you can go with a generic Huffman table, |
which will have slightly less than the best compression.*/ |
|
always @(posedge clk) |
begin |
Cb_DC_code_length[0] <= 2; |
Cb_DC_code_length[1] <= 2; |
Cb_DC_code_length[2] <= 2; |
Cb_DC_code_length[3] <= 3; |
Cb_DC_code_length[4] <= 4; |
Cb_DC_code_length[5] <= 5; |
Cb_DC_code_length[6] <= 6; |
Cb_DC_code_length[7] <= 7; |
Cb_DC_code_length[8] <= 8; |
Cb_DC_code_length[9] <= 9; |
Cb_DC_code_length[10] <= 10; |
Cb_DC_code_length[11] <= 11; |
Cb_DC[0] <= 11'b00000000000; |
Cb_DC[1] <= 11'b01000000000; |
Cb_DC[2] <= 11'b10000000000; |
Cb_DC[3] <= 11'b11000000000; |
Cb_DC[4] <= 11'b11100000000; |
Cb_DC[5] <= 11'b11110000000; |
Cb_DC[6] <= 11'b11111000000; |
Cb_DC[7] <= 11'b11111100000; |
Cb_DC[8] <= 11'b11111110000; |
Cb_DC[9] <= 11'b11111111000; |
Cb_DC[10] <= 11'b11111111100; |
Cb_DC[11] <= 11'b11111111110; |
Cb_AC_code_length[0] <= 2; |
Cb_AC_code_length[1] <= 2; |
Cb_AC_code_length[2] <= 3; |
Cb_AC_code_length[3] <= 4; |
Cb_AC_code_length[4] <= 4; |
Cb_AC_code_length[5] <= 4; |
Cb_AC_code_length[6] <= 5; |
Cb_AC_code_length[7] <= 5; |
Cb_AC_code_length[8] <= 5; |
Cb_AC_code_length[9] <= 6; |
Cb_AC_code_length[10] <= 6; |
Cb_AC_code_length[11] <= 7; |
Cb_AC_code_length[12] <= 7; |
Cb_AC_code_length[13] <= 7; |
Cb_AC_code_length[14] <= 7; |
Cb_AC_code_length[15] <= 8; |
Cb_AC_code_length[16] <= 8; |
Cb_AC_code_length[17] <= 8; |
Cb_AC_code_length[18] <= 9; |
Cb_AC_code_length[19] <= 9; |
Cb_AC_code_length[20] <= 9; |
Cb_AC_code_length[21] <= 9; |
Cb_AC_code_length[22] <= 9; |
Cb_AC_code_length[23] <= 10; |
Cb_AC_code_length[24] <= 10; |
Cb_AC_code_length[25] <= 10; |
Cb_AC_code_length[26] <= 10; |
Cb_AC_code_length[27] <= 10; |
Cb_AC_code_length[28] <= 11; |
Cb_AC_code_length[29] <= 11; |
Cb_AC_code_length[30] <= 11; |
Cb_AC_code_length[31] <= 11; |
Cb_AC_code_length[32] <= 12; |
Cb_AC_code_length[33] <= 12; |
Cb_AC_code_length[34] <= 12; |
Cb_AC_code_length[35] <= 12; |
Cb_AC_code_length[36] <= 15; |
Cb_AC_code_length[37] <= 16; |
Cb_AC_code_length[38] <= 16; |
Cb_AC_code_length[39] <= 16; |
Cb_AC_code_length[40] <= 16; |
Cb_AC_code_length[41] <= 16; |
Cb_AC_code_length[42] <= 16; |
Cb_AC_code_length[43] <= 16; |
Cb_AC_code_length[44] <= 16; |
Cb_AC_code_length[45] <= 16; |
Cb_AC_code_length[46] <= 16; |
Cb_AC_code_length[47] <= 16; |
Cb_AC_code_length[48] <= 16; |
Cb_AC_code_length[49] <= 16; |
Cb_AC_code_length[50] <= 16; |
Cb_AC_code_length[51] <= 16; |
Cb_AC_code_length[52] <= 16; |
Cb_AC_code_length[53] <= 16; |
Cb_AC_code_length[54] <= 16; |
Cb_AC_code_length[55] <= 16; |
Cb_AC_code_length[56] <= 16; |
Cb_AC_code_length[57] <= 16; |
Cb_AC_code_length[58] <= 16; |
Cb_AC_code_length[59] <= 16; |
Cb_AC_code_length[60] <= 16; |
Cb_AC_code_length[61] <= 16; |
Cb_AC_code_length[62] <= 16; |
Cb_AC_code_length[63] <= 16; |
Cb_AC_code_length[64] <= 16; |
Cb_AC_code_length[65] <= 16; |
Cb_AC_code_length[66] <= 16; |
Cb_AC_code_length[67] <= 16; |
Cb_AC_code_length[68] <= 16; |
Cb_AC_code_length[69] <= 16; |
Cb_AC_code_length[70] <= 16; |
Cb_AC_code_length[71] <= 16; |
Cb_AC_code_length[72] <= 16; |
Cb_AC_code_length[73] <= 16; |
Cb_AC_code_length[74] <= 16; |
Cb_AC_code_length[75] <= 16; |
Cb_AC_code_length[76] <= 16; |
Cb_AC_code_length[77] <= 16; |
Cb_AC_code_length[78] <= 16; |
Cb_AC_code_length[79] <= 16; |
Cb_AC_code_length[80] <= 16; |
Cb_AC_code_length[81] <= 16; |
Cb_AC_code_length[82] <= 16; |
Cb_AC_code_length[83] <= 16; |
Cb_AC_code_length[84] <= 16; |
Cb_AC_code_length[85] <= 16; |
Cb_AC_code_length[86] <= 16; |
Cb_AC_code_length[87] <= 16; |
Cb_AC_code_length[88] <= 16; |
Cb_AC_code_length[89] <= 16; |
Cb_AC_code_length[90] <= 16; |
Cb_AC_code_length[91] <= 16; |
Cb_AC_code_length[92] <= 16; |
Cb_AC_code_length[93] <= 16; |
Cb_AC_code_length[94] <= 16; |
Cb_AC_code_length[95] <= 16; |
Cb_AC_code_length[96] <= 16; |
Cb_AC_code_length[97] <= 16; |
Cb_AC_code_length[98] <= 16; |
Cb_AC_code_length[99] <= 16; |
Cb_AC_code_length[100] <= 16; |
Cb_AC_code_length[101] <= 16; |
Cb_AC_code_length[102] <= 16; |
Cb_AC_code_length[103] <= 16; |
Cb_AC_code_length[104] <= 16; |
Cb_AC_code_length[105] <= 16; |
Cb_AC_code_length[106] <= 16; |
Cb_AC_code_length[107] <= 16; |
Cb_AC_code_length[108] <= 16; |
Cb_AC_code_length[109] <= 16; |
Cb_AC_code_length[110] <= 16; |
Cb_AC_code_length[111] <= 16; |
Cb_AC_code_length[112] <= 16; |
Cb_AC_code_length[113] <= 16; |
Cb_AC_code_length[114] <= 16; |
Cb_AC_code_length[115] <= 16; |
Cb_AC_code_length[116] <= 16; |
Cb_AC_code_length[117] <= 16; |
Cb_AC_code_length[118] <= 16; |
Cb_AC_code_length[119] <= 16; |
Cb_AC_code_length[120] <= 16; |
Cb_AC_code_length[121] <= 16; |
Cb_AC_code_length[122] <= 16; |
Cb_AC_code_length[123] <= 16; |
Cb_AC_code_length[124] <= 16; |
Cb_AC_code_length[125] <= 16; |
Cb_AC_code_length[126] <= 16; |
Cb_AC_code_length[127] <= 16; |
Cb_AC_code_length[128] <= 16; |
Cb_AC_code_length[129] <= 16; |
Cb_AC_code_length[130] <= 16; |
Cb_AC_code_length[131] <= 16; |
Cb_AC_code_length[132] <= 16; |
Cb_AC_code_length[133] <= 16; |
Cb_AC_code_length[134] <= 16; |
Cb_AC_code_length[135] <= 16; |
Cb_AC_code_length[136] <= 16; |
Cb_AC_code_length[137] <= 16; |
Cb_AC_code_length[138] <= 16; |
Cb_AC_code_length[139] <= 16; |
Cb_AC_code_length[140] <= 16; |
Cb_AC_code_length[141] <= 16; |
Cb_AC_code_length[142] <= 16; |
Cb_AC_code_length[143] <= 16; |
Cb_AC_code_length[144] <= 16; |
Cb_AC_code_length[145] <= 16; |
Cb_AC_code_length[146] <= 16; |
Cb_AC_code_length[147] <= 16; |
Cb_AC_code_length[148] <= 16; |
Cb_AC_code_length[149] <= 16; |
Cb_AC_code_length[150] <= 16; |
Cb_AC_code_length[151] <= 16; |
Cb_AC_code_length[152] <= 16; |
Cb_AC_code_length[153] <= 16; |
Cb_AC_code_length[154] <= 16; |
Cb_AC_code_length[155] <= 16; |
Cb_AC_code_length[156] <= 16; |
Cb_AC_code_length[157] <= 16; |
Cb_AC_code_length[158] <= 16; |
Cb_AC_code_length[159] <= 16; |
Cb_AC_code_length[160] <= 16; |
Cb_AC_code_length[161] <= 16; |
Cb_AC[0] <= 16'b0000000000000000; |
Cb_AC[1] <= 16'b0100000000000000; |
Cb_AC[2] <= 16'b1000000000000000; |
Cb_AC[3] <= 16'b1010000000000000; |
Cb_AC[4] <= 16'b1011000000000000; |
Cb_AC[5] <= 16'b1100000000000000; |
Cb_AC[6] <= 16'b1101000000000000; |
Cb_AC[7] <= 16'b1101100000000000; |
Cb_AC[8] <= 16'b1110000000000000; |
Cb_AC[9] <= 16'b1110100000000000; |
Cb_AC[10] <= 16'b1110110000000000; |
Cb_AC[11] <= 16'b1111000000000000; |
Cb_AC[12] <= 16'b1111001000000000; |
Cb_AC[13] <= 16'b1111010000000000; |
Cb_AC[14] <= 16'b1111011000000000; |
Cb_AC[15] <= 16'b1111100000000000; |
Cb_AC[16] <= 16'b1111100100000000; |
Cb_AC[17] <= 16'b1111101000000000; |
Cb_AC[18] <= 16'b1111101100000000; |
Cb_AC[19] <= 16'b1111101110000000; |
Cb_AC[20] <= 16'b1111110000000000; |
Cb_AC[21] <= 16'b1111110010000000; |
Cb_AC[22] <= 16'b1111110100000000; |
Cb_AC[23] <= 16'b1111110110000000; |
Cb_AC[24] <= 16'b1111110111000000; |
Cb_AC[25] <= 16'b1111111000000000; |
Cb_AC[26] <= 16'b1111111001000000; |
Cb_AC[27] <= 16'b1111111010000000; |
Cb_AC[28] <= 16'b1111111011000000; |
Cb_AC[29] <= 16'b1111111011100000; |
Cb_AC[30] <= 16'b1111111100000000; |
Cb_AC[31] <= 16'b1111111100100000; |
Cb_AC[32] <= 16'b1111111101000000; |
Cb_AC[33] <= 16'b1111111101010000; |
Cb_AC[34] <= 16'b1111111101100000; |
Cb_AC[35] <= 16'b1111111101110000; |
Cb_AC[36] <= 16'b1111111110000000; |
Cb_AC[37] <= 16'b1111111110000010; |
Cb_AC[38] <= 16'b1111111110000011; |
Cb_AC[39] <= 16'b1111111110000100; |
Cb_AC[40] <= 16'b1111111110000101; |
Cb_AC[41] <= 16'b1111111110000110; |
Cb_AC[42] <= 16'b1111111110000111; |
Cb_AC[43] <= 16'b1111111110001000; |
Cb_AC[44] <= 16'b1111111110001001; |
Cb_AC[45] <= 16'b1111111110001010; |
Cb_AC[46] <= 16'b1111111110001011; |
Cb_AC[47] <= 16'b1111111110001100; |
Cb_AC[48] <= 16'b1111111110001101; |
Cb_AC[49] <= 16'b1111111110001110; |
Cb_AC[50] <= 16'b1111111110001111; |
Cb_AC[51] <= 16'b1111111110010000; |
Cb_AC[52] <= 16'b1111111110010001; |
Cb_AC[53] <= 16'b1111111110010010; |
Cb_AC[54] <= 16'b1111111110010011; |
Cb_AC[55] <= 16'b1111111110010100; |
Cb_AC[56] <= 16'b1111111110010101; |
Cb_AC[57] <= 16'b1111111110010110; |
Cb_AC[58] <= 16'b1111111110010111; |
Cb_AC[59] <= 16'b1111111110011000; |
Cb_AC[60] <= 16'b1111111110011001; |
Cb_AC[61] <= 16'b1111111110011010; |
Cb_AC[62] <= 16'b1111111110011011; |
Cb_AC[63] <= 16'b1111111110011100; |
Cb_AC[64] <= 16'b1111111110011101; |
Cb_AC[65] <= 16'b1111111110011110; |
Cb_AC[66] <= 16'b1111111110011111; |
Cb_AC[67] <= 16'b1111111110100000; |
Cb_AC[68] <= 16'b1111111110100001; |
Cb_AC[69] <= 16'b1111111110100010; |
Cb_AC[70] <= 16'b1111111110100011; |
Cb_AC[71] <= 16'b1111111110100100; |
Cb_AC[72] <= 16'b1111111110100101; |
Cb_AC[73] <= 16'b1111111110100110; |
Cb_AC[74] <= 16'b1111111110100111; |
Cb_AC[75] <= 16'b1111111110101000; |
Cb_AC[76] <= 16'b1111111110101001; |
Cb_AC[77] <= 16'b1111111110101010; |
Cb_AC[78] <= 16'b1111111110101011; |
Cb_AC[79] <= 16'b1111111110101100; |
Cb_AC[80] <= 16'b1111111110101101; |
Cb_AC[81] <= 16'b1111111110101110; |
Cb_AC[82] <= 16'b1111111110101111; |
Cb_AC[83] <= 16'b1111111110110000; |
Cb_AC[84] <= 16'b1111111110110001; |
Cb_AC[85] <= 16'b1111111110110010; |
Cb_AC[86] <= 16'b1111111110110011; |
Cb_AC[87] <= 16'b1111111110110100; |
Cb_AC[88] <= 16'b1111111110110101; |
Cb_AC[89] <= 16'b1111111110110110; |
Cb_AC[90] <= 16'b1111111110110111; |
Cb_AC[91] <= 16'b1111111110111000; |
Cb_AC[92] <= 16'b1111111110111001; |
Cb_AC[93] <= 16'b1111111110111010; |
Cb_AC[94] <= 16'b1111111110111011; |
Cb_AC[95] <= 16'b1111111110111100; |
Cb_AC[96] <= 16'b1111111110111101; |
Cb_AC[97] <= 16'b1111111110111110; |
Cb_AC[98] <= 16'b1111111110111111; |
Cb_AC[99] <= 16'b1111111111000000; |
Cb_AC[100] <= 16'b1111111111000001; |
Cb_AC[101] <= 16'b1111111111000010; |
Cb_AC[102] <= 16'b1111111111000011; |
Cb_AC[103] <= 16'b1111111111000100; |
Cb_AC[104] <= 16'b1111111111000101; |
Cb_AC[105] <= 16'b1111111111000110; |
Cb_AC[106] <= 16'b1111111111000111; |
Cb_AC[107] <= 16'b1111111111001000; |
Cb_AC[108] <= 16'b1111111111001001; |
Cb_AC[109] <= 16'b1111111111001010; |
Cb_AC[110] <= 16'b1111111111001011; |
Cb_AC[111] <= 16'b1111111111001100; |
Cb_AC[112] <= 16'b1111111111001101; |
Cb_AC[113] <= 16'b1111111111001110; |
Cb_AC[114] <= 16'b1111111111001111; |
Cb_AC[115] <= 16'b1111111111010000; |
Cb_AC[116] <= 16'b1111111111010001; |
Cb_AC[117] <= 16'b1111111111010010; |
Cb_AC[118] <= 16'b1111111111010011; |
Cb_AC[119] <= 16'b1111111111010100; |
Cb_AC[120] <= 16'b1111111111010101; |
Cb_AC[121] <= 16'b1111111111010110; |
Cb_AC[122] <= 16'b1111111111010111; |
Cb_AC[123] <= 16'b1111111111011000; |
Cb_AC[124] <= 16'b1111111111011001; |
Cb_AC[125] <= 16'b1111111111011010; |
Cb_AC[126] <= 16'b1111111111011011; |
Cb_AC[127] <= 16'b1111111111011100; |
Cb_AC[128] <= 16'b1111111111011101; |
Cb_AC[129] <= 16'b1111111111011110; |
Cb_AC[130] <= 16'b1111111111011111; |
Cb_AC[131] <= 16'b1111111111100000; |
Cb_AC[132] <= 16'b1111111111100001; |
Cb_AC[133] <= 16'b1111111111100010; |
Cb_AC[134] <= 16'b1111111111100011; |
Cb_AC[135] <= 16'b1111111111100100; |
Cb_AC[136] <= 16'b1111111111100101; |
Cb_AC[137] <= 16'b1111111111100110; |
Cb_AC[138] <= 16'b1111111111100111; |
Cb_AC[139] <= 16'b1111111111101000; |
Cb_AC[140] <= 16'b1111111111101001; |
Cb_AC[141] <= 16'b1111111111101010; |
Cb_AC[142] <= 16'b1111111111101011; |
Cb_AC[143] <= 16'b1111111111101100; |
Cb_AC[144] <= 16'b1111111111101101; |
Cb_AC[145] <= 16'b1111111111101110; |
Cb_AC[146] <= 16'b1111111111101111; |
Cb_AC[147] <= 16'b1111111111110000; |
Cb_AC[148] <= 16'b1111111111110001; |
Cb_AC[149] <= 16'b1111111111110010; |
Cb_AC[150] <= 16'b1111111111110011; |
Cb_AC[151] <= 16'b1111111111110100; |
Cb_AC[152] <= 16'b1111111111110101; |
Cb_AC[153] <= 16'b1111111111110110; |
Cb_AC[154] <= 16'b1111111111110111; |
Cb_AC[155] <= 16'b1111111111111000; |
Cb_AC[156] <= 16'b1111111111111001; |
Cb_AC[157] <= 16'b1111111111111010; |
Cb_AC[158] <= 16'b1111111111111011; |
Cb_AC[159] <= 16'b1111111111111100; |
Cb_AC[160] <= 16'b1111111111111101; |
Cb_AC[161] <= 16'b1111111111111110; |
Cb_AC_run_code[1] <= 0; |
Cb_AC_run_code[2] <= 1; |
Cb_AC_run_code[3] <= 2; |
Cb_AC_run_code[0] <= 3; |
Cb_AC_run_code[4] <= 4; |
Cb_AC_run_code[17] <= 5; |
Cb_AC_run_code[5] <= 6; |
Cb_AC_run_code[18] <= 7; |
Cb_AC_run_code[33] <= 8; |
Cb_AC_run_code[49] <= 9; |
Cb_AC_run_code[65] <= 10; |
Cb_AC_run_code[6] <= 11; |
Cb_AC_run_code[19] <= 12; |
Cb_AC_run_code[81] <= 13; |
Cb_AC_run_code[97] <= 14; |
Cb_AC_run_code[7] <= 15; |
Cb_AC_run_code[34] <= 16; |
Cb_AC_run_code[113] <= 17; |
Cb_AC_run_code[20] <= 18; |
Cb_AC_run_code[50] <= 19; |
Cb_AC_run_code[129] <= 20; |
Cb_AC_run_code[145] <= 21; |
Cb_AC_run_code[161] <= 22; |
Cb_AC_run_code[8] <= 23; |
Cb_AC_run_code[35] <= 24; |
Cb_AC_run_code[66] <= 25; |
Cb_AC_run_code[177] <= 26; |
Cb_AC_run_code[193] <= 27; |
Cb_AC_run_code[21] <= 28; |
Cb_AC_run_code[82] <= 29; |
Cb_AC_run_code[209] <= 30; |
Cb_AC_run_code[240] <= 31; |
Cb_AC_run_code[36] <= 32; |
Cb_AC_run_code[51] <= 33; |
Cb_AC_run_code[98] <= 34; |
Cb_AC_run_code[114] <= 35; |
Cb_AC_run_code[130] <= 36; |
Cb_AC_run_code[9] <= 37; |
Cb_AC_run_code[10] <= 38; |
Cb_AC_run_code[22] <= 39; |
Cb_AC_run_code[23] <= 40; |
Cb_AC_run_code[24] <= 41; |
Cb_AC_run_code[25] <= 42; |
Cb_AC_run_code[26] <= 43; |
Cb_AC_run_code[37] <= 44; |
Cb_AC_run_code[38] <= 45; |
Cb_AC_run_code[39] <= 46; |
Cb_AC_run_code[40] <= 47; |
Cb_AC_run_code[41] <= 48; |
Cb_AC_run_code[42] <= 49; |
Cb_AC_run_code[52] <= 50; |
Cb_AC_run_code[53] <= 51; |
Cb_AC_run_code[54] <= 52; |
Cb_AC_run_code[55] <= 53; |
Cb_AC_run_code[56] <= 54; |
Cb_AC_run_code[57] <= 55; |
Cb_AC_run_code[58] <= 56; |
Cb_AC_run_code[67] <= 57; |
Cb_AC_run_code[68] <= 58; |
Cb_AC_run_code[69] <= 59; |
Cb_AC_run_code[70] <= 60; |
Cb_AC_run_code[71] <= 61; |
Cb_AC_run_code[72] <= 62; |
Cb_AC_run_code[73] <= 63; |
Cb_AC_run_code[74] <= 64; |
Cb_AC_run_code[83] <= 65; |
Cb_AC_run_code[84] <= 66; |
Cb_AC_run_code[85] <= 67; |
Cb_AC_run_code[86] <= 68; |
Cb_AC_run_code[87] <= 69; |
Cb_AC_run_code[88] <= 70; |
Cb_AC_run_code[89] <= 71; |
Cb_AC_run_code[90] <= 72; |
Cb_AC_run_code[99] <= 73; |
Cb_AC_run_code[100] <= 74; |
Cb_AC_run_code[101] <= 75; |
Cb_AC_run_code[102] <= 76; |
Cb_AC_run_code[103] <= 77; |
Cb_AC_run_code[104] <= 78; |
Cb_AC_run_code[105] <= 79; |
Cb_AC_run_code[106] <= 80; |
Cb_AC_run_code[115] <= 81; |
Cb_AC_run_code[116] <= 82; |
Cb_AC_run_code[117] <= 83; |
Cb_AC_run_code[118] <= 84; |
Cb_AC_run_code[119] <= 85; |
Cb_AC_run_code[120] <= 86; |
Cb_AC_run_code[121] <= 87; |
Cb_AC_run_code[122] <= 88; |
Cb_AC_run_code[131] <= 89; |
Cb_AC_run_code[132] <= 90; |
Cb_AC_run_code[133] <= 91; |
Cb_AC_run_code[134] <= 92; |
Cb_AC_run_code[135] <= 93; |
Cb_AC_run_code[136] <= 94; |
Cb_AC_run_code[137] <= 95; |
Cb_AC_run_code[138] <= 96; |
Cb_AC_run_code[146] <= 97; |
Cb_AC_run_code[147] <= 98; |
Cb_AC_run_code[148] <= 99; |
Cb_AC_run_code[149] <= 100; |
Cb_AC_run_code[150] <= 101; |
Cb_AC_run_code[151] <= 102; |
Cb_AC_run_code[152] <= 103; |
Cb_AC_run_code[153] <= 104; |
Cb_AC_run_code[154] <= 105; |
Cb_AC_run_code[162] <= 106; |
Cb_AC_run_code[163] <= 107; |
Cb_AC_run_code[164] <= 108; |
Cb_AC_run_code[165] <= 109; |
Cb_AC_run_code[166] <= 110; |
Cb_AC_run_code[167] <= 111; |
Cb_AC_run_code[168] <= 112; |
Cb_AC_run_code[169] <= 113; |
Cb_AC_run_code[170] <= 114; |
Cb_AC_run_code[178] <= 115; |
Cb_AC_run_code[179] <= 116; |
Cb_AC_run_code[180] <= 117; |
Cb_AC_run_code[181] <= 118; |
Cb_AC_run_code[182] <= 119; |
Cb_AC_run_code[183] <= 120; |
Cb_AC_run_code[184] <= 121; |
Cb_AC_run_code[185] <= 122; |
Cb_AC_run_code[186] <= 123; |
Cb_AC_run_code[194] <= 124; |
Cb_AC_run_code[195] <= 125; |
Cb_AC_run_code[196] <= 126; |
Cb_AC_run_code[197] <= 127; |
Cb_AC_run_code[198] <= 128; |
Cb_AC_run_code[199] <= 129; |
Cb_AC_run_code[200] <= 130; |
Cb_AC_run_code[201] <= 131; |
Cb_AC_run_code[202] <= 132; |
Cb_AC_run_code[210] <= 133; |
Cb_AC_run_code[211] <= 134; |
Cb_AC_run_code[212] <= 135; |
Cb_AC_run_code[213] <= 136; |
Cb_AC_run_code[214] <= 137; |
Cb_AC_run_code[215] <= 138; |
Cb_AC_run_code[216] <= 139; |
Cb_AC_run_code[217] <= 140; |
Cb_AC_run_code[218] <= 141; |
Cb_AC_run_code[225] <= 142; |
Cb_AC_run_code[226] <= 143; |
Cb_AC_run_code[227] <= 144; |
Cb_AC_run_code[228] <= 145; |
Cb_AC_run_code[229] <= 146; |
Cb_AC_run_code[230] <= 147; |
Cb_AC_run_code[231] <= 148; |
Cb_AC_run_code[232] <= 149; |
Cb_AC_run_code[233] <= 150; |
Cb_AC_run_code[234] <= 151; |
Cb_AC_run_code[241] <= 152; |
Cb_AC_run_code[242] <= 153; |
Cb_AC_run_code[243] <= 154; |
Cb_AC_run_code[244] <= 155; |
Cb_AC_run_code[245] <= 156; |
Cb_AC_run_code[246] <= 157; |
Cb_AC_run_code[247] <= 158; |
Cb_AC_run_code[248] <= 159; |
Cb_AC_run_code[249] <= 160; |
Cb_AC_run_code[250] <= 161; |
Cb_AC_run_code[16] <= 0; |
Cb_AC_run_code[32] <= 0; |
Cb_AC_run_code[48] <= 0; |
Cb_AC_run_code[64] <= 0; |
Cb_AC_run_code[80] <= 0; |
Cb_AC_run_code[96] <= 0; |
Cb_AC_run_code[112] <= 0; |
Cb_AC_run_code[128] <= 0; |
Cb_AC_run_code[144] <= 0; |
Cb_AC_run_code[160] <= 0; |
Cb_AC_run_code[176] <= 0; |
Cb_AC_run_code[192] <= 0; |
Cb_AC_run_code[208] <= 0; |
Cb_AC_run_code[224] <= 0; |
|
end |
|
|
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[31] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[31] <= JPEG_bs_5[31]; |
else if (enable_module && orc_8 == 0) |
JPEG_bitstream[31] <= JPEG_bs_5[31]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[30] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[30] <= JPEG_bs_5[30]; |
else if (enable_module && orc_8 <= 1) |
JPEG_bitstream[30] <= JPEG_bs_5[30]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[29] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[29] <= JPEG_bs_5[29]; |
else if (enable_module && orc_8 <= 2) |
JPEG_bitstream[29] <= JPEG_bs_5[29]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[28] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[28] <= JPEG_bs_5[28]; |
else if (enable_module && orc_8 <= 3) |
JPEG_bitstream[28] <= JPEG_bs_5[28]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[27] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[27] <= JPEG_bs_5[27]; |
else if (enable_module && orc_8 <= 4) |
JPEG_bitstream[27] <= JPEG_bs_5[27]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[26] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[26] <= JPEG_bs_5[26]; |
else if (enable_module && orc_8 <= 5) |
JPEG_bitstream[26] <= JPEG_bs_5[26]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[25] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[25] <= JPEG_bs_5[25]; |
else if (enable_module && orc_8 <= 6) |
JPEG_bitstream[25] <= JPEG_bs_5[25]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[24] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[24] <= JPEG_bs_5[24]; |
else if (enable_module && orc_8 <= 7) |
JPEG_bitstream[24] <= JPEG_bs_5[24]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[23] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[23] <= JPEG_bs_5[23]; |
else if (enable_module && orc_8 <= 8) |
JPEG_bitstream[23] <= JPEG_bs_5[23]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[22] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[22] <= JPEG_bs_5[22]; |
else if (enable_module && orc_8 <= 9) |
JPEG_bitstream[22] <= JPEG_bs_5[22]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[21] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[21] <= JPEG_bs_5[21]; |
else if (enable_module && orc_8 <= 10) |
JPEG_bitstream[21] <= JPEG_bs_5[21]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[20] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[20] <= JPEG_bs_5[20]; |
else if (enable_module && orc_8 <= 11) |
JPEG_bitstream[20] <= JPEG_bs_5[20]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[19] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[19] <= JPEG_bs_5[19]; |
else if (enable_module && orc_8 <= 12) |
JPEG_bitstream[19] <= JPEG_bs_5[19]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[18] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[18] <= JPEG_bs_5[18]; |
else if (enable_module && orc_8 <= 13) |
JPEG_bitstream[18] <= JPEG_bs_5[18]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[17] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[17] <= JPEG_bs_5[17]; |
else if (enable_module && orc_8 <= 14) |
JPEG_bitstream[17] <= JPEG_bs_5[17]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[16] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[16] <= JPEG_bs_5[16]; |
else if (enable_module && orc_8 <= 15) |
JPEG_bitstream[16] <= JPEG_bs_5[16]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[15] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[15] <= JPEG_bs_5[15]; |
else if (enable_module && orc_8 <= 16) |
JPEG_bitstream[15] <= JPEG_bs_5[15]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[14] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[14] <= JPEG_bs_5[14]; |
else if (enable_module && orc_8 <= 17) |
JPEG_bitstream[14] <= JPEG_bs_5[14]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[13] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[13] <= JPEG_bs_5[13]; |
else if (enable_module && orc_8 <= 18) |
JPEG_bitstream[13] <= JPEG_bs_5[13]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[12] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[12] <= JPEG_bs_5[12]; |
else if (enable_module && orc_8 <= 19) |
JPEG_bitstream[12] <= JPEG_bs_5[12]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[11] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[11] <= JPEG_bs_5[11]; |
else if (enable_module && orc_8 <= 20) |
JPEG_bitstream[11] <= JPEG_bs_5[11]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[10] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[10] <= JPEG_bs_5[10]; |
else if (enable_module && orc_8 <= 21) |
JPEG_bitstream[10] <= JPEG_bs_5[10]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[9] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[9] <= JPEG_bs_5[9]; |
else if (enable_module && orc_8 <= 22) |
JPEG_bitstream[9] <= JPEG_bs_5[9]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[8] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[8] <= JPEG_bs_5[8]; |
else if (enable_module && orc_8 <= 23) |
JPEG_bitstream[8] <= JPEG_bs_5[8]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[7] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[7] <= JPEG_bs_5[7]; |
else if (enable_module && orc_8 <= 24) |
JPEG_bitstream[7] <= JPEG_bs_5[7]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[6] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[6] <= JPEG_bs_5[6]; |
else if (enable_module && orc_8 <= 25) |
JPEG_bitstream[6] <= JPEG_bs_5[6]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[5] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[5] <= JPEG_bs_5[5]; |
else if (enable_module && orc_8 <= 26) |
JPEG_bitstream[5] <= JPEG_bs_5[5]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[4] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[4] <= JPEG_bs_5[4]; |
else if (enable_module && orc_8 <= 27) |
JPEG_bitstream[4] <= JPEG_bs_5[4]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[3] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[3] <= JPEG_bs_5[3]; |
else if (enable_module && orc_8 <= 28) |
JPEG_bitstream[3] <= JPEG_bs_5[3]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[2] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[2] <= JPEG_bs_5[2]; |
else if (enable_module && orc_8 <= 29) |
JPEG_bitstream[2] <= JPEG_bs_5[2]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[1] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[1] <= JPEG_bs_5[1]; |
else if (enable_module && orc_8 <= 30) |
JPEG_bitstream[1] <= JPEG_bs_5[1]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[0] <= 0; |
else if (enable_module && rollover_7) |
JPEG_bitstream[0] <= JPEG_bs_5[0]; |
else if (enable_module && orc_8 <= 31) |
JPEG_bitstream[0] <= JPEG_bs_5[0]; |
end |
endmodule |
/jpegencode/trunk/cr_dct.v
0,0 → 1,846
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module converts the incoming Cr data. |
The incoming data is unsigned 8 bits, so the data is in the range of 0-255 |
Unlike a typical DCT, the data is not subtracted by 128 to center it around 0. |
It is only required for the first row, and instead of subtracting 128 from each |
pixel value, a total value can be subtracted at the end of the first row/column multiply, |
involving the 8 pixel values and the 8 DCT matrix values. |
For the other 7 rows of the DCT matrix, the values in each row add up to 0, |
so it is not necessary to subtract 128 from each Y, Cb, and Cr pixel value. |
Then the Discrete Cosine Transform is performed by multiplying the 8x8 pixel block values |
by the 8x8 DCT matrix. */ |
|
|
`timescale 1ns / 100ps |
|
module cr_dct(clk, rst, enable, data_in, |
Z11_final, Z12_final, Z13_final, Z14_final, Z15_final, Z16_final, Z17_final, Z18_final, |
Z21_final, Z22_final, Z23_final, Z24_final, Z25_final, Z26_final, Z27_final, Z28_final, |
Z31_final, Z32_final, Z33_final, Z34_final, Z35_final, Z36_final, Z37_final, Z38_final, |
Z41_final, Z42_final, Z43_final, Z44_final, Z45_final, Z46_final, Z47_final, Z48_final, |
Z51_final, Z52_final, Z53_final, Z54_final, Z55_final, Z56_final, Z57_final, Z58_final, |
Z61_final, Z62_final, Z63_final, Z64_final, Z65_final, Z66_final, Z67_final, Z68_final, |
Z71_final, Z72_final, Z73_final, Z74_final, Z75_final, Z76_final, Z77_final, Z78_final, |
Z81_final, Z82_final, Z83_final, Z84_final, Z85_final, Z86_final, Z87_final, Z88_final, |
output_enable); |
input clk; |
input rst; |
input enable; |
input [7:0] data_in; |
output [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
output [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
output [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
output [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
output [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
output [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
output [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
output [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
output [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
output [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
output [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
output [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
output [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
output [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
output [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
output [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
output output_enable; |
|
|
integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52; |
integer Ti1, Ti21, Ti22, Ti23, Ti24, Ti25, Ti26, Ti27, Ti28, Ti31, Ti32, Ti33, Ti34, Ti52; |
|
reg [24:0] Cb_temp_11; |
reg [24:0] Cb11, Cb21, Cb31, Cb41, Cb51, Cb61, Cb71, Cb81, Cb11_final; |
reg [31:0] Cb_temp_21, Cb_temp_31, Cb_temp_41, Cb_temp_51; |
reg [31:0] Cb_temp_61, Cb_temp_71, Cb_temp_81; |
reg [31:0] Z_temp_11, Z_temp_12, Z_temp_13, Z_temp_14; |
reg [31:0] Z_temp_15, Z_temp_16, Z_temp_17, Z_temp_18; |
reg [31:0] Z_temp_21, Z_temp_22, Z_temp_23, Z_temp_24; |
reg [31:0] Z_temp_25, Z_temp_26, Z_temp_27, Z_temp_28; |
reg [31:0] Z_temp_31, Z_temp_32, Z_temp_33, Z_temp_34; |
reg [31:0] Z_temp_35, Z_temp_36, Z_temp_37, Z_temp_38; |
reg [31:0] Z_temp_41, Z_temp_42, Z_temp_43, Z_temp_44; |
reg [31:0] Z_temp_45, Z_temp_46, Z_temp_47, Z_temp_48; |
reg [31:0] Z_temp_51, Z_temp_52, Z_temp_53, Z_temp_54; |
reg [31:0] Z_temp_55, Z_temp_56, Z_temp_57, Z_temp_58; |
reg [31:0] Z_temp_61, Z_temp_62, Z_temp_63, Z_temp_64; |
reg [31:0] Z_temp_65, Z_temp_66, Z_temp_67, Z_temp_68; |
reg [31:0] Z_temp_71, Z_temp_72, Z_temp_73, Z_temp_74; |
reg [31:0] Z_temp_75, Z_temp_76, Z_temp_77, Z_temp_78; |
reg [31:0] Z_temp_81, Z_temp_82, Z_temp_83, Z_temp_84; |
reg [31:0] Z_temp_85, Z_temp_86, Z_temp_87, Z_temp_88; |
reg [24:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18; |
reg [24:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28; |
reg [24:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38; |
reg [24:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48; |
reg [24:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58; |
reg [24:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68; |
reg [24:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78; |
reg [24:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88; |
reg [31:0] Cb11_final_2, Cb21_final_2, Cb11_final_3, Cb11_final_4, Cb31_final_2, Cb41_final_2; |
reg [31:0] Cb51_final_2, Cb61_final_2, Cb71_final_2, Cb81_final_2; |
reg [10:0] Cb11_final_1, Cb21_final_1, Cb31_final_1, Cb41_final_1; |
reg [10:0] Cb51_final_1, Cb61_final_1, Cb71_final_1, Cb81_final_1; |
reg [24:0] Cb21_final, Cb31_final, Cb41_final, Cb51_final; |
reg [24:0] Cb61_final, Cb71_final, Cb81_final; |
reg [24:0] Cb21_final_prev, Cb21_final_diff; |
reg [24:0] Cb31_final_prev, Cb31_final_diff; |
reg [24:0] Cb41_final_prev, Cb41_final_diff; |
reg [24:0] Cb51_final_prev, Cb51_final_diff; |
reg [24:0] Cb61_final_prev, Cb61_final_diff; |
reg [24:0] Cb71_final_prev, Cb71_final_diff; |
reg [24:0] Cb81_final_prev, Cb81_final_diff; |
reg [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
reg [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
reg [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
reg [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
reg [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
reg [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
reg [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
reg [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
reg [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
reg [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
reg [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
reg [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
reg [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
reg [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
reg [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
reg [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
reg [2:0] count; |
reg [2:0] count_of, count_of_copy; |
reg count_1, count_3, count_4, count_5, count_6, count_7, count_8, enable_1, output_enable; |
reg count_9, count_10; |
reg [7:0] data_1; |
integer Cb2_mul_input, Cb3_mul_input, Cb4_mul_input, Cb5_mul_input; |
integer Cb6_mul_input, Cb7_mul_input, Cb8_mul_input; |
integer Ti2_mul_input, Ti3_mul_input, Ti4_mul_input, Ti5_mul_input; |
integer Ti6_mul_input, Ti7_mul_input, Ti8_mul_input; |
|
always @(posedge clk) |
begin // DCT matrix entries |
T1 = 5793; // .3536 |
T21 = 8035; // .4904 |
T22 = 6811; // .4157 |
T23 = 4551; // .2778 |
T24 = 1598; // .0975 |
T25 = -1598; // -.0975 |
T26 = -4551; // -.2778 |
T27 = -6811; // -.4157 |
T28 = -8035; // -.4904 |
T31 = 7568; // .4619 |
T32 = 3135; // .1913 |
T33 = -3135; // -.1913 |
T34 = -7568; // -.4619 |
T52 = -5793; // -.3536 |
end |
|
always @(posedge clk) |
begin // The inverse DCT matrix entries |
Ti1 = 5793; // .3536 |
Ti21 = 8035; // .4904 |
Ti22 = 6811; // .4157 |
Ti23 = 4551; // .2778 |
Ti24 = 1598; // .0975 |
Ti25 = -1598; // -.0975 |
Ti26 = -4551; // -.2778 |
Ti27 = -6811; // -.4157 |
Ti28 = -8035; // -.4904 |
Ti31 = 7568; // .4619 |
Ti32 = 3135; // .1913 |
Ti33 = -3135; // -.1913 |
Ti34 = -7568; // -.4619 |
Ti52 = -5793; // -.3536 |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0; |
Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0; |
Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0; |
Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0; |
Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0; |
Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0; |
Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0; |
Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0; |
Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0; |
Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0; |
Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0; |
Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0; |
Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0; |
Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0; |
Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0; |
Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0; |
end |
else if (enable_1 & count_8) begin |
Z_temp_11 <= Cb11_final_4 * Ti1; Z_temp_12 <= Cb11_final_4 * Ti2_mul_input; |
Z_temp_13 <= Cb11_final_4 * Ti3_mul_input; Z_temp_14 <= Cb11_final_4 * Ti4_mul_input; |
Z_temp_15 <= Cb11_final_4 * Ti5_mul_input; Z_temp_16 <= Cb11_final_4 * Ti6_mul_input; |
Z_temp_17 <= Cb11_final_4 * Ti7_mul_input; Z_temp_18 <= Cb11_final_4 * Ti8_mul_input; |
Z_temp_21 <= Cb21_final_2 * Ti1; Z_temp_22 <= Cb21_final_2 * Ti2_mul_input; |
Z_temp_23 <= Cb21_final_2 * Ti3_mul_input; Z_temp_24 <= Cb21_final_2 * Ti4_mul_input; |
Z_temp_25 <= Cb21_final_2 * Ti5_mul_input; Z_temp_26 <= Cb21_final_2 * Ti6_mul_input; |
Z_temp_27 <= Cb21_final_2 * Ti7_mul_input; Z_temp_28 <= Cb21_final_2 * Ti8_mul_input; |
Z_temp_31 <= Cb31_final_2 * Ti1; Z_temp_32 <= Cb31_final_2 * Ti2_mul_input; |
Z_temp_33 <= Cb31_final_2 * Ti3_mul_input; Z_temp_34 <= Cb31_final_2 * Ti4_mul_input; |
Z_temp_35 <= Cb31_final_2 * Ti5_mul_input; Z_temp_36 <= Cb31_final_2 * Ti6_mul_input; |
Z_temp_37 <= Cb31_final_2 * Ti7_mul_input; Z_temp_38 <= Cb31_final_2 * Ti8_mul_input; |
Z_temp_41 <= Cb41_final_2 * Ti1; Z_temp_42 <= Cb41_final_2 * Ti2_mul_input; |
Z_temp_43 <= Cb41_final_2 * Ti3_mul_input; Z_temp_44 <= Cb41_final_2 * Ti4_mul_input; |
Z_temp_45 <= Cb41_final_2 * Ti5_mul_input; Z_temp_46 <= Cb41_final_2 * Ti6_mul_input; |
Z_temp_47 <= Cb41_final_2 * Ti7_mul_input; Z_temp_48 <= Cb41_final_2 * Ti8_mul_input; |
Z_temp_51 <= Cb51_final_2 * Ti1; Z_temp_52 <= Cb51_final_2 * Ti2_mul_input; |
Z_temp_53 <= Cb51_final_2 * Ti3_mul_input; Z_temp_54 <= Cb51_final_2 * Ti4_mul_input; |
Z_temp_55 <= Cb51_final_2 * Ti5_mul_input; Z_temp_56 <= Cb51_final_2 * Ti6_mul_input; |
Z_temp_57 <= Cb51_final_2 * Ti7_mul_input; Z_temp_58 <= Cb51_final_2 * Ti8_mul_input; |
Z_temp_61 <= Cb61_final_2 * Ti1; Z_temp_62 <= Cb61_final_2 * Ti2_mul_input; |
Z_temp_63 <= Cb61_final_2 * Ti3_mul_input; Z_temp_64 <= Cb61_final_2 * Ti4_mul_input; |
Z_temp_65 <= Cb61_final_2 * Ti5_mul_input; Z_temp_66 <= Cb61_final_2 * Ti6_mul_input; |
Z_temp_67 <= Cb61_final_2 * Ti7_mul_input; Z_temp_68 <= Cb61_final_2 * Ti8_mul_input; |
Z_temp_71 <= Cb71_final_2 * Ti1; Z_temp_72 <= Cb71_final_2 * Ti2_mul_input; |
Z_temp_73 <= Cb71_final_2 * Ti3_mul_input; Z_temp_74 <= Cb71_final_2 * Ti4_mul_input; |
Z_temp_75 <= Cb71_final_2 * Ti5_mul_input; Z_temp_76 <= Cb71_final_2 * Ti6_mul_input; |
Z_temp_77 <= Cb71_final_2 * Ti7_mul_input; Z_temp_78 <= Cb71_final_2 * Ti8_mul_input; |
Z_temp_81 <= Cb81_final_2 * Ti1; Z_temp_82 <= Cb81_final_2 * Ti2_mul_input; |
Z_temp_83 <= Cb81_final_2 * Ti3_mul_input; Z_temp_84 <= Cb81_final_2 * Ti4_mul_input; |
Z_temp_85 <= Cb81_final_2 * Ti5_mul_input; Z_temp_86 <= Cb81_final_2 * Ti6_mul_input; |
Z_temp_87 <= Cb81_final_2 * Ti7_mul_input; Z_temp_88 <= Cb81_final_2 * Ti8_mul_input; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; |
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; |
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; |
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; |
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; |
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; |
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; |
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; |
end |
else if (count_8 & count_of == 1) begin |
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; |
Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; |
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; |
Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; |
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; |
Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; |
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; |
Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; |
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; |
Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; |
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; |
Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; |
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; |
Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; |
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; |
Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; |
end |
else if (enable & count_9) begin |
Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14; |
Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18; |
Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24; |
Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28; |
Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34; |
Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38; |
Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44; |
Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48; |
Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54; |
Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58; |
Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64; |
Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68; |
Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74; |
Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78; |
Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84; |
Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0; |
Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0; |
Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0; |
Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0; |
Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0; |
Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0; |
Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0; |
Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0; |
Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0; |
Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0; |
Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0; |
Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0; |
Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0; |
Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0; |
Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0; |
Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0; |
end |
else if (count_10 & count_of == 0) begin |
Z11_final <= Z11[13] ? Z11[24:14] + 1 : Z11[24:14]; |
Z12_final <= Z12[13] ? Z12[24:14] + 1 : Z12[24:14]; |
Z13_final <= Z13[13] ? Z13[24:14] + 1 : Z13[24:14]; |
Z14_final <= Z14[13] ? Z14[24:14] + 1 : Z14[24:14]; |
Z15_final <= Z15[13] ? Z15[24:14] + 1 : Z15[24:14]; |
Z16_final <= Z16[13] ? Z16[24:14] + 1 : Z16[24:14]; |
Z17_final <= Z17[13] ? Z17[24:14] + 1 : Z17[24:14]; |
Z18_final <= Z18[13] ? Z18[24:14] + 1 : Z18[24:14]; |
Z21_final <= Z21[13] ? Z21[24:14] + 1 : Z21[24:14]; |
Z22_final <= Z22[13] ? Z22[24:14] + 1 : Z22[24:14]; |
Z23_final <= Z23[13] ? Z23[24:14] + 1 : Z23[24:14]; |
Z24_final <= Z24[13] ? Z24[24:14] + 1 : Z24[24:14]; |
Z25_final <= Z25[13] ? Z25[24:14] + 1 : Z25[24:14]; |
Z26_final <= Z26[13] ? Z26[24:14] + 1 : Z26[24:14]; |
Z27_final <= Z27[13] ? Z27[24:14] + 1 : Z27[24:14]; |
Z28_final <= Z28[13] ? Z28[24:14] + 1 : Z28[24:14]; |
Z31_final <= Z31[13] ? Z31[24:14] + 1 : Z31[24:14]; |
Z32_final <= Z32[13] ? Z32[24:14] + 1 : Z32[24:14]; |
Z33_final <= Z33[13] ? Z33[24:14] + 1 : Z33[24:14]; |
Z34_final <= Z34[13] ? Z34[24:14] + 1 : Z34[24:14]; |
Z35_final <= Z35[13] ? Z35[24:14] + 1 : Z35[24:14]; |
Z36_final <= Z36[13] ? Z36[24:14] + 1 : Z36[24:14]; |
Z37_final <= Z37[13] ? Z37[24:14] + 1 : Z37[24:14]; |
Z38_final <= Z38[13] ? Z38[24:14] + 1 : Z38[24:14]; |
Z41_final <= Z41[13] ? Z41[24:14] + 1 : Z41[24:14]; |
Z42_final <= Z42[13] ? Z42[24:14] + 1 : Z42[24:14]; |
Z43_final <= Z43[13] ? Z43[24:14] + 1 : Z43[24:14]; |
Z44_final <= Z44[13] ? Z44[24:14] + 1 : Z44[24:14]; |
Z45_final <= Z45[13] ? Z45[24:14] + 1 : Z45[24:14]; |
Z46_final <= Z46[13] ? Z46[24:14] + 1 : Z46[24:14]; |
Z47_final <= Z47[13] ? Z47[24:14] + 1 : Z47[24:14]; |
Z48_final <= Z48[13] ? Z48[24:14] + 1 : Z48[24:14]; |
Z51_final <= Z51[13] ? Z51[24:14] + 1 : Z51[24:14]; |
Z52_final <= Z52[13] ? Z52[24:14] + 1 : Z52[24:14]; |
Z53_final <= Z53[13] ? Z53[24:14] + 1 : Z53[24:14]; |
Z54_final <= Z54[13] ? Z54[24:14] + 1 : Z54[24:14]; |
Z55_final <= Z55[13] ? Z55[24:14] + 1 : Z55[24:14]; |
Z56_final <= Z56[13] ? Z56[24:14] + 1 : Z56[24:14]; |
Z57_final <= Z57[13] ? Z57[24:14] + 1 : Z57[24:14]; |
Z58_final <= Z58[13] ? Z58[24:14] + 1 : Z58[24:14]; |
Z61_final <= Z61[13] ? Z61[24:14] + 1 : Z61[24:14]; |
Z62_final <= Z62[13] ? Z62[24:14] + 1 : Z62[24:14]; |
Z63_final <= Z63[13] ? Z63[24:14] + 1 : Z63[24:14]; |
Z64_final <= Z64[13] ? Z64[24:14] + 1 : Z64[24:14]; |
Z65_final <= Z65[13] ? Z65[24:14] + 1 : Z65[24:14]; |
Z66_final <= Z66[13] ? Z66[24:14] + 1 : Z66[24:14]; |
Z67_final <= Z67[13] ? Z67[24:14] + 1 : Z67[24:14]; |
Z68_final <= Z68[13] ? Z68[24:14] + 1 : Z68[24:14]; |
Z71_final <= Z71[13] ? Z71[24:14] + 1 : Z71[24:14]; |
Z72_final <= Z72[13] ? Z72[24:14] + 1 : Z72[24:14]; |
Z73_final <= Z73[13] ? Z73[24:14] + 1 : Z73[24:14]; |
Z74_final <= Z74[13] ? Z74[24:14] + 1 : Z74[24:14]; |
Z75_final <= Z75[13] ? Z75[24:14] + 1 : Z75[24:14]; |
Z76_final <= Z76[13] ? Z76[24:14] + 1 : Z76[24:14]; |
Z77_final <= Z77[13] ? Z77[24:14] + 1 : Z77[24:14]; |
Z78_final <= Z78[13] ? Z78[24:14] + 1 : Z78[24:14]; |
Z81_final <= Z81[13] ? Z81[24:14] + 1 : Z81[24:14]; |
Z82_final <= Z82[13] ? Z82[24:14] + 1 : Z82[24:14]; |
Z83_final <= Z83[13] ? Z83[24:14] + 1 : Z83[24:14]; |
Z84_final <= Z84[13] ? Z84[24:14] + 1 : Z84[24:14]; |
Z85_final <= Z85[13] ? Z85[24:14] + 1 : Z85[24:14]; |
Z86_final <= Z86[13] ? Z86[24:14] + 1 : Z86[24:14]; |
Z87_final <= Z87[13] ? Z87[24:14] + 1 : Z87[24:14]; |
Z88_final <= Z88[13] ? Z88[24:14] + 1 : Z88[24:14]; |
end |
end |
|
// output_enable signals the next block, the quantizer, that the input data is ready |
always @(posedge clk) |
begin |
if (rst) |
output_enable <= 0; |
else if (!enable_1) |
output_enable <= 0; |
else if (count_10 == 0 | count_of) |
output_enable <= 0; |
else if (count_10 & count_of == 0) |
output_enable <= 1; |
end |
always @(posedge clk) |
begin |
if (rst) |
Cb_temp_11 <= 0; |
else if (enable) |
Cb_temp_11 <= data_in * T1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Cb11 <= 0; |
else if (count == 1 & enable == 1) |
Cb11 <= Cb_temp_11; |
else if (enable) |
Cb11 <= Cb_temp_11 + Cb11; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb_temp_21 <= 0; |
Cb_temp_31 <= 0; |
Cb_temp_41 <= 0; |
Cb_temp_51 <= 0; |
Cb_temp_61 <= 0; |
Cb_temp_71 <= 0; |
Cb_temp_81 <= 0; |
end |
else if (!enable_1) begin |
Cb_temp_21 <= 0; |
Cb_temp_31 <= 0; |
Cb_temp_41 <= 0; |
Cb_temp_51 <= 0; |
Cb_temp_61 <= 0; |
Cb_temp_71 <= 0; |
Cb_temp_81 <= 0; |
end |
else if (enable_1) begin |
Cb_temp_21 <= data_1 * Cb2_mul_input; |
Cb_temp_31 <= data_1 * Cb3_mul_input; |
Cb_temp_41 <= data_1 * Cb4_mul_input; |
Cb_temp_51 <= data_1 * Cb5_mul_input; |
Cb_temp_61 <= data_1 * Cb6_mul_input; |
Cb_temp_71 <= data_1 * Cb7_mul_input; |
Cb_temp_81 <= data_1 * Cb8_mul_input; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb21 <= 0; |
Cb31 <= 0; |
Cb41 <= 0; |
Cb51 <= 0; |
Cb61 <= 0; |
Cb71 <= 0; |
Cb81 <= 0; |
end |
else if (!enable_1) begin |
Cb21 <= 0; |
Cb31 <= 0; |
Cb41 <= 0; |
Cb51 <= 0; |
Cb61 <= 0; |
Cb71 <= 0; |
Cb81 <= 0; |
end |
else if (enable_1) begin |
Cb21 <= Cb_temp_21 + Cb21; |
Cb31 <= Cb_temp_31 + Cb31; |
Cb41 <= Cb_temp_41 + Cb41; |
Cb51 <= Cb_temp_51 + Cb51; |
Cb61 <= Cb_temp_61 + Cb61; |
Cb71 <= Cb_temp_71 + Cb71; |
Cb81 <= Cb_temp_81 + Cb81; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; |
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; |
count_10 <= 0; |
end |
else if (!enable) begin |
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; |
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; |
count_10 <= 0; |
end |
else if (enable) begin |
count <= count + 1; count_3 <= count_1; count_4 <= count_3; |
count_5 <= count_4; count_6 <= count_5; count_7 <= count_6; |
count_8 <= count_7; count_9 <= count_8; count_10 <= count_9; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count_1 <= 0; |
end |
else if (count != 7 | !enable) begin |
count_1 <= 0; |
end |
else if (count == 7) begin |
count_1 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count_of <= 0; |
count_of_copy <= 0; |
end |
else if (!enable) begin |
count_of <= 0; |
count_of_copy <= 0; |
end |
else if (count_1 == 1) begin |
count_of <= count_of + 1; |
count_of_copy <= count_of_copy + 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb11_final <= 0; |
end |
else if (count_3 & enable_1) begin |
Cb11_final <= Cb11 - 25'd5932032; |
/* The Cb values weren't centered on 0 before doing the DCT |
128 needs to be subtracted from each Cb value before, or in this |
case, 362 is subtracted from the total, because this is the |
total obtained by subtracting 128 from each element |
and then multiplying by the weight |
assigned by the DCT matrix : 128*8*5793 = 5932032 |
This is only needed for the first row, the values in the rest of |
the rows add up to 0 */ |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb21_final <= 0; Cb21_final_prev <= 0; |
Cb31_final <= 0; Cb31_final_prev <= 0; |
Cb41_final <= 0; Cb41_final_prev <= 0; |
Cb51_final <= 0; Cb51_final_prev <= 0; |
Cb61_final <= 0; Cb61_final_prev <= 0; |
Cb71_final <= 0; Cb71_final_prev <= 0; |
Cb81_final <= 0; Cb81_final_prev <= 0; |
end |
else if (!enable_1) begin |
Cb21_final <= 0; Cb21_final_prev <= 0; |
Cb31_final <= 0; Cb31_final_prev <= 0; |
Cb41_final <= 0; Cb41_final_prev <= 0; |
Cb51_final <= 0; Cb51_final_prev <= 0; |
Cb61_final <= 0; Cb61_final_prev <= 0; |
Cb71_final <= 0; Cb71_final_prev <= 0; |
Cb81_final <= 0; Cb81_final_prev <= 0; |
end |
else if (count_4 & enable_1) begin |
Cb21_final <= Cb21; Cb21_final_prev <= Cb21_final; |
Cb31_final <= Cb31; Cb31_final_prev <= Cb31_final; |
Cb41_final <= Cb41; Cb41_final_prev <= Cb41_final; |
Cb51_final <= Cb51; Cb51_final_prev <= Cb51_final; |
Cb61_final <= Cb61; Cb61_final_prev <= Cb61_final; |
Cb71_final <= Cb71; Cb71_final_prev <= Cb71_final; |
Cb81_final <= Cb81; Cb81_final_prev <= Cb81_final; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Cb21_final_diff <= 0; Cb31_final_diff <= 0; |
Cb41_final_diff <= 0; Cb51_final_diff <= 0; |
Cb61_final_diff <= 0; Cb71_final_diff <= 0; |
Cb81_final_diff <= 0; |
end |
else if (count_5 & enable_1) begin |
Cb21_final_diff <= Cb21_final - Cb21_final_prev; |
Cb31_final_diff <= Cb31_final - Cb31_final_prev; |
Cb41_final_diff <= Cb41_final - Cb41_final_prev; |
Cb51_final_diff <= Cb51_final - Cb51_final_prev; |
Cb61_final_diff <= Cb61_final - Cb61_final_prev; |
Cb71_final_diff <= Cb71_final - Cb71_final_prev; |
Cb81_final_diff <= Cb81_final - Cb81_final_prev; |
end |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb2_mul_input <= T21; |
3'b001: Cb2_mul_input <= T22; |
3'b010: Cb2_mul_input <= T23; |
3'b011: Cb2_mul_input <= T24; |
3'b100: Cb2_mul_input <= T25; |
3'b101: Cb2_mul_input <= T26; |
3'b110: Cb2_mul_input <= T27; |
3'b111: Cb2_mul_input <= T28; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb3_mul_input <= T31; |
3'b001: Cb3_mul_input <= T32; |
3'b010: Cb3_mul_input <= T33; |
3'b011: Cb3_mul_input <= T34; |
3'b100: Cb3_mul_input <= T34; |
3'b101: Cb3_mul_input <= T33; |
3'b110: Cb3_mul_input <= T32; |
3'b111: Cb3_mul_input <= T31; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb4_mul_input <= T22; |
3'b001: Cb4_mul_input <= T25; |
3'b010: Cb4_mul_input <= T28; |
3'b011: Cb4_mul_input <= T26; |
3'b100: Cb4_mul_input <= T23; |
3'b101: Cb4_mul_input <= T21; |
3'b110: Cb4_mul_input <= T24; |
3'b111: Cb4_mul_input <= T27; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb5_mul_input <= T1; |
3'b001: Cb5_mul_input <= T52; |
3'b010: Cb5_mul_input <= T52; |
3'b011: Cb5_mul_input <= T1; |
3'b100: Cb5_mul_input <= T1; |
3'b101: Cb5_mul_input <= T52; |
3'b110: Cb5_mul_input <= T52; |
3'b111: Cb5_mul_input <= T1; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb6_mul_input <= T23; |
3'b001: Cb6_mul_input <= T28; |
3'b010: Cb6_mul_input <= T24; |
3'b011: Cb6_mul_input <= T22; |
3'b100: Cb6_mul_input <= T27; |
3'b101: Cb6_mul_input <= T25; |
3'b110: Cb6_mul_input <= T21; |
3'b111: Cb6_mul_input <= T26; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb7_mul_input <= T32; |
3'b001: Cb7_mul_input <= T34; |
3'b010: Cb7_mul_input <= T31; |
3'b011: Cb7_mul_input <= T33; |
3'b100: Cb7_mul_input <= T33; |
3'b101: Cb7_mul_input <= T31; |
3'b110: Cb7_mul_input <= T34; |
3'b111: Cb7_mul_input <= T32; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Cb8_mul_input <= T24; |
3'b001: Cb8_mul_input <= T26; |
3'b010: Cb8_mul_input <= T22; |
3'b011: Cb8_mul_input <= T28; |
3'b100: Cb8_mul_input <= T21; |
3'b101: Cb8_mul_input <= T27; |
3'b110: Cb8_mul_input <= T23; |
3'b111: Cb8_mul_input <= T25; |
endcase |
end |
|
// Inverse DCT matrix entries |
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti2_mul_input <= Ti28; |
3'b001: Ti2_mul_input <= Ti21; |
3'b010: Ti2_mul_input <= Ti22; |
3'b011: Ti2_mul_input <= Ti23; |
3'b100: Ti2_mul_input <= Ti24; |
3'b101: Ti2_mul_input <= Ti25; |
3'b110: Ti2_mul_input <= Ti26; |
3'b111: Ti2_mul_input <= Ti27; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti3_mul_input <= Ti31; |
3'b001: Ti3_mul_input <= Ti31; |
3'b010: Ti3_mul_input <= Ti32; |
3'b011: Ti3_mul_input <= Ti33; |
3'b100: Ti3_mul_input <= Ti34; |
3'b101: Ti3_mul_input <= Ti34; |
3'b110: Ti3_mul_input <= Ti33; |
3'b111: Ti3_mul_input <= Ti32; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti4_mul_input <= Ti27; |
3'b001: Ti4_mul_input <= Ti22; |
3'b010: Ti4_mul_input <= Ti25; |
3'b011: Ti4_mul_input <= Ti28; |
3'b100: Ti4_mul_input <= Ti26; |
3'b101: Ti4_mul_input <= Ti23; |
3'b110: Ti4_mul_input <= Ti21; |
3'b111: Ti4_mul_input <= Ti24; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti5_mul_input <= Ti1; |
3'b001: Ti5_mul_input <= Ti1; |
3'b010: Ti5_mul_input <= Ti52; |
3'b011: Ti5_mul_input <= Ti52; |
3'b100: Ti5_mul_input <= Ti1; |
3'b101: Ti5_mul_input <= Ti1; |
3'b110: Ti5_mul_input <= Ti52; |
3'b111: Ti5_mul_input <= Ti52; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti6_mul_input <= Ti26; |
3'b001: Ti6_mul_input <= Ti23; |
3'b010: Ti6_mul_input <= Ti28; |
3'b011: Ti6_mul_input <= Ti24; |
3'b100: Ti6_mul_input <= Ti22; |
3'b101: Ti6_mul_input <= Ti27; |
3'b110: Ti6_mul_input <= Ti25; |
3'b111: Ti6_mul_input <= Ti21; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti7_mul_input <= Ti32; |
3'b001: Ti7_mul_input <= Ti32; |
3'b010: Ti7_mul_input <= Ti34; |
3'b011: Ti7_mul_input <= Ti31; |
3'b100: Ti7_mul_input <= Ti33; |
3'b101: Ti7_mul_input <= Ti33; |
3'b110: Ti7_mul_input <= Ti31; |
3'b111: Ti7_mul_input <= Ti34; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti8_mul_input <= Ti25; |
3'b001: Ti8_mul_input <= Ti24; |
3'b010: Ti8_mul_input <= Ti26; |
3'b011: Ti8_mul_input <= Ti22; |
3'b100: Ti8_mul_input <= Ti28; |
3'b101: Ti8_mul_input <= Ti21; |
3'b110: Ti8_mul_input <= Ti27; |
3'b111: Ti8_mul_input <= Ti23; |
endcase |
end |
|
// Rounding stage |
always @(posedge clk) |
begin |
if (rst) begin |
data_1 <= 0; |
Cb11_final_1 <= 0; Cb21_final_1 <= 0; Cb31_final_1 <= 0; Cb41_final_1 <= 0; |
Cb51_final_1 <= 0; Cb61_final_1 <= 0; Cb71_final_1 <= 0; Cb81_final_1 <= 0; |
Cb11_final_2 <= 0; Cb21_final_2 <= 0; Cb31_final_2 <= 0; Cb41_final_2 <= 0; |
Cb51_final_2 <= 0; Cb61_final_2 <= 0; Cb71_final_2 <= 0; Cb81_final_2 <= 0; |
Cb11_final_3 <= 0; Cb11_final_4 <= 0; |
end |
else if (enable) begin |
data_1 <= data_in; |
Cb11_final_1 <= Cb11_final[13] ? Cb11_final[24:14] + 1 : Cb11_final[24:14]; |
Cb11_final_2[31:11] <= Cb11_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb11_final_2[10:0] <= Cb11_final_1; |
// Need to sign extend Cb11_final_1 and the other registers to store a negative |
// number as a twos complement number. If you don't sign extend, then a negative number |
// will be stored incorrectly as a positive number. For example, -215 would be stored |
// as 1833 without sign extending |
Cb11_final_3 <= Cb11_final_2; |
Cb11_final_4 <= Cb11_final_3; |
Cb21_final_1 <= Cb21_final_diff[13] ? Cb21_final_diff[24:14] + 1 : Cb21_final_diff[24:14]; |
Cb21_final_2[31:11] <= Cb21_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb21_final_2[10:0] <= Cb21_final_1; |
Cb31_final_1 <= Cb31_final_diff[13] ? Cb31_final_diff[24:14] + 1 : Cb31_final_diff[24:14]; |
Cb31_final_2[31:11] <= Cb31_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb31_final_2[10:0] <= Cb31_final_1; |
Cb41_final_1 <= Cb41_final_diff[13] ? Cb41_final_diff[24:14] + 1 : Cb41_final_diff[24:14]; |
Cb41_final_2[31:11] <= Cb41_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb41_final_2[10:0] <= Cb41_final_1; |
Cb51_final_1 <= Cb51_final_diff[13] ? Cb51_final_diff[24:14] + 1 : Cb51_final_diff[24:14]; |
Cb51_final_2[31:11] <= Cb51_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb51_final_2[10:0] <= Cb51_final_1; |
Cb61_final_1 <= Cb61_final_diff[13] ? Cb61_final_diff[24:14] + 1 : Cb61_final_diff[24:14]; |
Cb61_final_2[31:11] <= Cb61_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb61_final_2[10:0] <= Cb61_final_1; |
Cb71_final_1 <= Cb71_final_diff[13] ? Cb71_final_diff[24:14] + 1 : Cb71_final_diff[24:14]; |
Cb71_final_2[31:11] <= Cb71_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb71_final_2[10:0] <= Cb71_final_1; |
Cb81_final_1 <= Cb81_final_diff[13] ? Cb81_final_diff[24:14] + 1 : Cb81_final_diff[24:14]; |
Cb81_final_2[31:11] <= Cb81_final_1[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Cb81_final_2[10:0] <= Cb81_final_1; |
// The bit in place 13 is the fraction part, for rounding purposes |
// if it is 1, then you need to add 1 to the bits in 22-14, |
// if bit 13 is 0, then the bits in 22-14 won't change |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; |
end |
else begin |
enable_1 <= enable; |
end |
end |
|
endmodule |
/jpegencode/trunk/crd_q_h.v
0,0 → 1,138
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module combines the dct, quantizer, and huffman modules. */ |
|
`timescale 1ns / 100ps |
|
module crd_q_h(clk, rst, enable, data_in, |
JPEG_bitstream, data_ready, cr_orc, |
end_of_block_empty); |
input clk; |
input rst; |
input enable; |
input [7:0] data_in; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output [4:0] cr_orc; |
output end_of_block_empty; |
|
|
wire dct_enable, quantizer_enable; |
wire [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
wire [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
wire [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
wire [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
wire [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
wire [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
wire [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
wire [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
wire [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
wire [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
wire [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
wire [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
wire [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
wire [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
wire [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
wire [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
wire [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18; |
wire [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28; |
wire [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
wire [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48; |
wire [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58; |
wire [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
wire [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78; |
wire [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88; |
|
cr_dct u8( |
.clk(clk),.rst(rst), .enable(enable), .data_in(data_in), |
.Z11_final(Z11_final), .Z12_final(Z12_final), |
.Z13_final(Z13_final), .Z14_final(Z14_final), .Z15_final(Z15_final), .Z16_final(Z16_final), |
.Z17_final(Z17_final), .Z18_final(Z18_final), .Z21_final(Z21_final), .Z22_final(Z22_final), |
.Z23_final(Z23_final), .Z24_final(Z24_final), .Z25_final(Z25_final), .Z26_final(Z26_final), |
.Z27_final(Z27_final), .Z28_final(Z28_final), .Z31_final(Z31_final), .Z32_final(Z32_final), |
.Z33_final(Z33_final), .Z34_final(Z34_final), .Z35_final(Z35_final), .Z36_final(Z36_final), |
.Z37_final(Z37_final), .Z38_final(Z38_final), .Z41_final(Z41_final), .Z42_final(Z42_final), |
.Z43_final(Z43_final), .Z44_final(Z44_final), .Z45_final(Z45_final), .Z46_final(Z46_final), |
.Z47_final(Z47_final), .Z48_final(Z48_final), .Z51_final(Z51_final), .Z52_final(Z52_final), |
.Z53_final(Z53_final), .Z54_final(Z54_final), .Z55_final(Z55_final), .Z56_final(Z56_final), |
.Z57_final(Z57_final), .Z58_final(Z58_final), .Z61_final(Z61_final), .Z62_final(Z62_final), |
.Z63_final(Z63_final), .Z64_final(Z64_final), .Z65_final(Z65_final), .Z66_final(Z66_final), |
.Z67_final(Z67_final), .Z68_final(Z68_final), .Z71_final(Z71_final), .Z72_final(Z72_final), |
.Z73_final(Z73_final), .Z74_final(Z74_final), .Z75_final(Z75_final), .Z76_final(Z76_final), |
.Z77_final(Z77_final), .Z78_final(Z78_final), .Z81_final(Z81_final), .Z82_final(Z82_final), |
.Z83_final(Z83_final), .Z84_final(Z84_final), .Z85_final(Z85_final), .Z86_final(Z86_final), |
.Z87_final(Z87_final), .Z88_final(Z88_final), .output_enable(dct_enable)); |
|
cr_quantizer u9( |
.clk(clk),.rst(rst),.enable(dct_enable), |
.Z11(Z11_final), .Z12(Z12_final), .Z13(Z13_final), .Z14(Z14_final), |
.Z15(Z15_final), .Z16(Z16_final), .Z17(Z17_final), .Z18(Z18_final), |
.Z21(Z21_final), .Z22(Z22_final), .Z23(Z23_final), .Z24(Z24_final), |
.Z25(Z25_final), .Z26(Z26_final), .Z27(Z27_final), .Z28(Z28_final), |
.Z31(Z31_final), .Z32(Z32_final), .Z33(Z33_final), .Z34(Z34_final), |
.Z35(Z35_final), .Z36(Z36_final), .Z37(Z37_final), .Z38(Z38_final), |
.Z41(Z41_final), .Z42(Z42_final), .Z43(Z43_final), .Z44(Z44_final), |
.Z45(Z45_final), .Z46(Z46_final), .Z47(Z47_final), .Z48(Z48_final), |
.Z51(Z51_final), .Z52(Z52_final), .Z53(Z53_final), .Z54(Z54_final), |
.Z55(Z55_final), .Z56(Z56_final), .Z57(Z57_final), .Z58(Z58_final), |
.Z61(Z61_final), .Z62(Z62_final), .Z63(Z63_final), .Z64(Z64_final), |
.Z65(Z65_final), .Z66(Z66_final), .Z67(Z67_final), .Z68(Z68_final), |
.Z71(Z71_final), .Z72(Z72_final), .Z73(Z73_final), .Z74(Z74_final), |
.Z75(Z75_final), .Z76(Z76_final), .Z77(Z77_final), .Z78(Z78_final), |
.Z81(Z81_final), .Z82(Z82_final), .Z83(Z83_final), .Z84(Z84_final), |
.Z85(Z85_final), .Z86(Z86_final), .Z87(Z87_final), .Z88(Z88_final), |
.Q11(Q11), .Q12(Q12), .Q13(Q13), .Q14(Q14), .Q15(Q15), .Q16(Q16), .Q17(Q17), .Q18(Q18), |
.Q21(Q21), .Q22(Q22), .Q23(Q23), .Q24(Q24), .Q25(Q25), .Q26(Q26), .Q27(Q27), .Q28(Q28), |
.Q31(Q31), .Q32(Q32), .Q33(Q33), .Q34(Q34), .Q35(Q35), .Q36(Q36), .Q37(Q37), .Q38(Q38), |
.Q41(Q41), .Q42(Q42), .Q43(Q43), .Q44(Q44), .Q45(Q45), .Q46(Q46), .Q47(Q47), .Q48(Q48), |
.Q51(Q51), .Q52(Q52), .Q53(Q53), .Q54(Q54), .Q55(Q55), .Q56(Q56), .Q57(Q57), .Q58(Q58), |
.Q61(Q61), .Q62(Q62), .Q63(Q63), .Q64(Q64), .Q65(Q65), .Q66(Q66), .Q67(Q67), .Q68(Q68), |
.Q71(Q71), .Q72(Q72), .Q73(Q73), .Q74(Q74), .Q75(Q75), .Q76(Q76), .Q77(Q77), .Q78(Q78), |
.Q81(Q81), .Q82(Q82), .Q83(Q83), .Q84(Q84), .Q85(Q85), .Q86(Q86), .Q87(Q87), .Q88(Q88), |
.out_enable(quantizer_enable)); |
|
cr_huff u10(.clk(clk), .rst(rst), .enable(quantizer_enable), |
.Cr11(Q11), .Cr12(Q21), .Cr13(Q31), .Cr14(Q41), .Cr15(Q51), .Cr16(Q61), .Cr17(Q71), .Cr18(Q81), |
.Cr21(Q12), .Cr22(Q22), .Cr23(Q32), .Cr24(Q42), .Cr25(Q52), .Cr26(Q62), .Cr27(Q72), .Cr28(Q82), |
.Cr31(Q13), .Cr32(Q23), .Cr33(Q33), .Cr34(Q43), .Cr35(Q53), .Cr36(Q63), .Cr37(Q73), .Cr38(Q83), |
.Cr41(Q14), .Cr42(Q24), .Cr43(Q34), .Cr44(Q44), .Cr45(Q54), .Cr46(Q64), .Cr47(Q74), .Cr48(Q84), |
.Cr51(Q15), .Cr52(Q25), .Cr53(Q35), .Cr54(Q45), .Cr55(Q55), .Cr56(Q65), .Cr57(Q75), .Cr58(Q85), |
.Cr61(Q16), .Cr62(Q26), .Cr63(Q36), .Cr64(Q46), .Cr65(Q56), .Cr66(Q66), .Cr67(Q76), .Cr68(Q86), |
.Cr71(Q17), .Cr72(Q27), .Cr73(Q37), .Cr74(Q47), .Cr75(Q57), .Cr76(Q67), .Cr77(Q77), .Cr78(Q87), |
.Cr81(Q18), .Cr82(Q28), .Cr83(Q38), .Cr84(Q48), .Cr85(Q58), .Cr86(Q68), .Cr87(Q78), .Cr88(Q88), |
.JPEG_bitstream(JPEG_bitstream), .data_ready(data_ready), .output_reg_count(cr_orc), |
.end_of_block_empty(end_of_block_empty)); |
|
|
endmodule |
/jpegencode/trunk/y_dct.v
0,0 → 1,844
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module converts the incoming Y data. |
The incoming data is unsigned 8 bits, so the data is in the range of 0-255 |
Unlike a typical DCT, the data is not subtracted by 128 to center it around 0. |
It is only required for the first row, and instead of subtracting 128 from each |
pixel value, a total value can be subtracted at the end of the first row/column multiply, |
involving the 8 pixel values and the 8 DCT matrix values. |
For the other 7 rows of the DCT matrix, the values in each row add up to 0, |
so it is not necessary to subtract 128 from each Y, Cb, and Cr pixel value. |
Then the Discrete Cosine Transform is performed by multiplying the 8x8 pixel block values |
by the 8x8 DCT matrix. */ |
|
`timescale 1ns / 100ps |
|
module y_dct(clk, rst, enable, data_in, |
Z11_final, Z12_final, Z13_final, Z14_final, Z15_final, Z16_final, Z17_final, Z18_final, |
Z21_final, Z22_final, Z23_final, Z24_final, Z25_final, Z26_final, Z27_final, Z28_final, |
Z31_final, Z32_final, Z33_final, Z34_final, Z35_final, Z36_final, Z37_final, Z38_final, |
Z41_final, Z42_final, Z43_final, Z44_final, Z45_final, Z46_final, Z47_final, Z48_final, |
Z51_final, Z52_final, Z53_final, Z54_final, Z55_final, Z56_final, Z57_final, Z58_final, |
Z61_final, Z62_final, Z63_final, Z64_final, Z65_final, Z66_final, Z67_final, Z68_final, |
Z71_final, Z72_final, Z73_final, Z74_final, Z75_final, Z76_final, Z77_final, Z78_final, |
Z81_final, Z82_final, Z83_final, Z84_final, Z85_final, Z86_final, Z87_final, Z88_final, |
output_enable); |
input clk; |
input rst; |
input enable; |
input [7:0] data_in; |
output [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
output [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
output [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
output [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
output [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
output [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
output [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
output [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
output [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
output [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
output [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
output [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
output [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
output [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
output [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
output [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
output output_enable; |
|
|
integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52; |
integer Ti1, Ti21, Ti22, Ti23, Ti24, Ti25, Ti26, Ti27, Ti28, Ti31, Ti32, Ti33, Ti34, Ti52; |
|
reg [24:0] Y_temp_11; |
reg [24:0] Y11, Y21, Y31, Y41, Y51, Y61, Y71, Y81, Y11_final; |
reg [31:0] Y_temp_21, Y_temp_31, Y_temp_41, Y_temp_51; |
reg [31:0] Y_temp_61, Y_temp_71, Y_temp_81; |
reg [31:0] Z_temp_11, Z_temp_12, Z_temp_13, Z_temp_14; |
reg [31:0] Z_temp_15, Z_temp_16, Z_temp_17, Z_temp_18; |
reg [31:0] Z_temp_21, Z_temp_22, Z_temp_23, Z_temp_24; |
reg [31:0] Z_temp_25, Z_temp_26, Z_temp_27, Z_temp_28; |
reg [31:0] Z_temp_31, Z_temp_32, Z_temp_33, Z_temp_34; |
reg [31:0] Z_temp_35, Z_temp_36, Z_temp_37, Z_temp_38; |
reg [31:0] Z_temp_41, Z_temp_42, Z_temp_43, Z_temp_44; |
reg [31:0] Z_temp_45, Z_temp_46, Z_temp_47, Z_temp_48; |
reg [31:0] Z_temp_51, Z_temp_52, Z_temp_53, Z_temp_54; |
reg [31:0] Z_temp_55, Z_temp_56, Z_temp_57, Z_temp_58; |
reg [31:0] Z_temp_61, Z_temp_62, Z_temp_63, Z_temp_64; |
reg [31:0] Z_temp_65, Z_temp_66, Z_temp_67, Z_temp_68; |
reg [31:0] Z_temp_71, Z_temp_72, Z_temp_73, Z_temp_74; |
reg [31:0] Z_temp_75, Z_temp_76, Z_temp_77, Z_temp_78; |
reg [31:0] Z_temp_81, Z_temp_82, Z_temp_83, Z_temp_84; |
reg [31:0] Z_temp_85, Z_temp_86, Z_temp_87, Z_temp_88; |
reg [26:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18; |
reg [26:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28; |
reg [26:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38; |
reg [26:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48; |
reg [26:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58; |
reg [26:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68; |
reg [26:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78; |
reg [26:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88; |
reg [31:0] Y11_final_2, Y21_final_2, Y11_final_3, Y11_final_4, Y31_final_2, Y41_final_2; |
reg [31:0] Y51_final_2, Y61_final_2, Y71_final_2, Y81_final_2; |
reg [12:0] Y11_final_1, Y21_final_1, Y31_final_1, Y41_final_1; |
reg [12:0] Y51_final_1, Y61_final_1, Y71_final_1, Y81_final_1; |
reg [24:0] Y21_final, Y31_final, Y41_final, Y51_final; |
reg [24:0] Y61_final, Y71_final, Y81_final; |
reg [24:0] Y21_final_prev, Y21_final_diff; |
reg [24:0] Y31_final_prev, Y31_final_diff; |
reg [24:0] Y41_final_prev, Y41_final_diff; |
reg [24:0] Y51_final_prev, Y51_final_diff; |
reg [24:0] Y61_final_prev, Y61_final_diff; |
reg [24:0] Y71_final_prev, Y71_final_diff; |
reg [24:0] Y81_final_prev, Y81_final_diff; |
reg [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
reg [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
reg [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
reg [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
reg [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
reg [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
reg [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
reg [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
reg [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
reg [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
reg [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
reg [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
reg [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
reg [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
reg [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
reg [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
reg [2:0] count; |
reg [2:0] count_of, count_of_copy; |
reg count_1, count_3, count_4, count_5, count_6, count_7, count_8, enable_1, output_enable; |
reg count_9, count_10; |
reg [7:0] data_1; |
integer Y2_mul_input, Y3_mul_input, Y4_mul_input, Y5_mul_input; |
integer Y6_mul_input, Y7_mul_input, Y8_mul_input; |
integer Ti2_mul_input, Ti3_mul_input, Ti4_mul_input, Ti5_mul_input; |
integer Ti6_mul_input, Ti7_mul_input, Ti8_mul_input; |
|
always @(posedge clk) |
begin // DCT matrix entries |
T1 = 5793; // .3536 |
T21 = 8035; // .4904 |
T22 = 6811; // .4157 |
T23 = 4551; // .2778 |
T24 = 1598; // .0975 |
T25 = -1598; // -.0975 |
T26 = -4551; // -.2778 |
T27 = -6811; // -.4157 |
T28 = -8035; // -.4904 |
T31 = 7568; // .4619 |
T32 = 3135; // .1913 |
T33 = -3135; // -.1913 |
T34 = -7568; // -.4619 |
T52 = -5793; // -.3536 |
end |
|
always @(posedge clk) |
begin // The inverse DCT matrix entries |
Ti1 = 5793; // .3536 |
Ti21 = 8035; // .4904 |
Ti22 = 6811; // .4157 |
Ti23 = 4551; // .2778 |
Ti24 = 1598; // .0975 |
Ti25 = -1598; // -.0975 |
Ti26 = -4551; // -.2778 |
Ti27 = -6811; // -.4157 |
Ti28 = -8035; // -.4904 |
Ti31 = 7568; // .4619 |
Ti32 = 3135; // .1913 |
Ti33 = -3135; // -.1913 |
Ti34 = -7568; // -.4619 |
Ti52 = -5793; // -.3536 |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0; |
Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0; |
Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0; |
Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0; |
Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0; |
Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0; |
Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0; |
Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0; |
Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0; |
Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0; |
Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0; |
Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0; |
Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0; |
Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0; |
Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0; |
Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0; |
end |
else if (enable_1 & count_8) begin |
Z_temp_11 <= Y11_final_4 * Ti1; Z_temp_12 <= Y11_final_4 * Ti2_mul_input; |
Z_temp_13 <= Y11_final_4 * Ti3_mul_input; Z_temp_14 <= Y11_final_4 * Ti4_mul_input; |
Z_temp_15 <= Y11_final_4 * Ti5_mul_input; Z_temp_16 <= Y11_final_4 * Ti6_mul_input; |
Z_temp_17 <= Y11_final_4 * Ti7_mul_input; Z_temp_18 <= Y11_final_4 * Ti8_mul_input; |
Z_temp_21 <= Y21_final_2 * Ti1; Z_temp_22 <= Y21_final_2 * Ti2_mul_input; |
Z_temp_23 <= Y21_final_2 * Ti3_mul_input; Z_temp_24 <= Y21_final_2 * Ti4_mul_input; |
Z_temp_25 <= Y21_final_2 * Ti5_mul_input; Z_temp_26 <= Y21_final_2 * Ti6_mul_input; |
Z_temp_27 <= Y21_final_2 * Ti7_mul_input; Z_temp_28 <= Y21_final_2 * Ti8_mul_input; |
Z_temp_31 <= Y31_final_2 * Ti1; Z_temp_32 <= Y31_final_2 * Ti2_mul_input; |
Z_temp_33 <= Y31_final_2 * Ti3_mul_input; Z_temp_34 <= Y31_final_2 * Ti4_mul_input; |
Z_temp_35 <= Y31_final_2 * Ti5_mul_input; Z_temp_36 <= Y31_final_2 * Ti6_mul_input; |
Z_temp_37 <= Y31_final_2 * Ti7_mul_input; Z_temp_38 <= Y31_final_2 * Ti8_mul_input; |
Z_temp_41 <= Y41_final_2 * Ti1; Z_temp_42 <= Y41_final_2 * Ti2_mul_input; |
Z_temp_43 <= Y41_final_2 * Ti3_mul_input; Z_temp_44 <= Y41_final_2 * Ti4_mul_input; |
Z_temp_45 <= Y41_final_2 * Ti5_mul_input; Z_temp_46 <= Y41_final_2 * Ti6_mul_input; |
Z_temp_47 <= Y41_final_2 * Ti7_mul_input; Z_temp_48 <= Y41_final_2 * Ti8_mul_input; |
Z_temp_51 <= Y51_final_2 * Ti1; Z_temp_52 <= Y51_final_2 * Ti2_mul_input; |
Z_temp_53 <= Y51_final_2 * Ti3_mul_input; Z_temp_54 <= Y51_final_2 * Ti4_mul_input; |
Z_temp_55 <= Y51_final_2 * Ti5_mul_input; Z_temp_56 <= Y51_final_2 * Ti6_mul_input; |
Z_temp_57 <= Y51_final_2 * Ti7_mul_input; Z_temp_58 <= Y51_final_2 * Ti8_mul_input; |
Z_temp_61 <= Y61_final_2 * Ti1; Z_temp_62 <= Y61_final_2 * Ti2_mul_input; |
Z_temp_63 <= Y61_final_2 * Ti3_mul_input; Z_temp_64 <= Y61_final_2 * Ti4_mul_input; |
Z_temp_65 <= Y61_final_2 * Ti5_mul_input; Z_temp_66 <= Y61_final_2 * Ti6_mul_input; |
Z_temp_67 <= Y61_final_2 * Ti7_mul_input; Z_temp_68 <= Y61_final_2 * Ti8_mul_input; |
Z_temp_71 <= Y71_final_2 * Ti1; Z_temp_72 <= Y71_final_2 * Ti2_mul_input; |
Z_temp_73 <= Y71_final_2 * Ti3_mul_input; Z_temp_74 <= Y71_final_2 * Ti4_mul_input; |
Z_temp_75 <= Y71_final_2 * Ti5_mul_input; Z_temp_76 <= Y71_final_2 * Ti6_mul_input; |
Z_temp_77 <= Y71_final_2 * Ti7_mul_input; Z_temp_78 <= Y71_final_2 * Ti8_mul_input; |
Z_temp_81 <= Y81_final_2 * Ti1; Z_temp_82 <= Y81_final_2 * Ti2_mul_input; |
Z_temp_83 <= Y81_final_2 * Ti3_mul_input; Z_temp_84 <= Y81_final_2 * Ti4_mul_input; |
Z_temp_85 <= Y81_final_2 * Ti5_mul_input; Z_temp_86 <= Y81_final_2 * Ti6_mul_input; |
Z_temp_87 <= Y81_final_2 * Ti7_mul_input; Z_temp_88 <= Y81_final_2 * Ti8_mul_input; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; |
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; |
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; |
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; |
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; |
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; |
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; |
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; |
end |
else if (count_8 & count_of == 1) begin |
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; |
Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0; |
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; |
Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0; |
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; |
Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0; |
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; |
Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0; |
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; |
Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0; |
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; |
Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0; |
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; |
Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0; |
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; |
Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0; |
end |
else if (enable & count_9) begin |
Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14; |
Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18; |
Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24; |
Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28; |
Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34; |
Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38; |
Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44; |
Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48; |
Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54; |
Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58; |
Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64; |
Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68; |
Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74; |
Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78; |
Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84; |
Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0; |
Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0; |
Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0; |
Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0; |
Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0; |
Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0; |
Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0; |
Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0; |
Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0; |
Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0; |
Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0; |
Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0; |
Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0; |
Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0; |
Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0; |
Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0; |
end |
else if (count_10 & count_of == 0) begin |
Z11_final <= Z11[15] ? Z11[26:16] + 1 : Z11[26:16]; |
Z12_final <= Z12[15] ? Z12[26:16] + 1 : Z12[26:16]; |
Z13_final <= Z13[15] ? Z13[26:16] + 1 : Z13[26:16]; |
Z14_final <= Z14[15] ? Z14[26:16] + 1 : Z14[26:16]; |
Z15_final <= Z15[15] ? Z15[26:16] + 1 : Z15[26:16]; |
Z16_final <= Z16[15] ? Z16[26:16] + 1 : Z16[26:16]; |
Z17_final <= Z17[15] ? Z17[26:16] + 1 : Z17[26:16]; |
Z18_final <= Z18[15] ? Z18[26:16] + 1 : Z18[26:16]; |
Z21_final <= Z21[15] ? Z21[26:16] + 1 : Z21[26:16]; |
Z22_final <= Z22[15] ? Z22[26:16] + 1 : Z22[26:16]; |
Z23_final <= Z23[15] ? Z23[26:16] + 1 : Z23[26:16]; |
Z24_final <= Z24[15] ? Z24[26:16] + 1 : Z24[26:16]; |
Z25_final <= Z25[15] ? Z25[26:16] + 1 : Z25[26:16]; |
Z26_final <= Z26[15] ? Z26[26:16] + 1 : Z26[26:16]; |
Z27_final <= Z27[15] ? Z27[26:16] + 1 : Z27[26:16]; |
Z28_final <= Z28[15] ? Z28[26:16] + 1 : Z28[26:16]; |
Z31_final <= Z31[15] ? Z31[26:16] + 1 : Z31[26:16]; |
Z32_final <= Z32[15] ? Z32[26:16] + 1 : Z32[26:16]; |
Z33_final <= Z33[15] ? Z33[26:16] + 1 : Z33[26:16]; |
Z34_final <= Z34[15] ? Z34[26:16] + 1 : Z34[26:16]; |
Z35_final <= Z35[15] ? Z35[26:16] + 1 : Z35[26:16]; |
Z36_final <= Z36[15] ? Z36[26:16] + 1 : Z36[26:16]; |
Z37_final <= Z37[15] ? Z37[26:16] + 1 : Z37[26:16]; |
Z38_final <= Z38[15] ? Z38[26:16] + 1 : Z38[26:16]; |
Z41_final <= Z41[15] ? Z41[26:16] + 1 : Z41[26:16]; |
Z42_final <= Z42[15] ? Z42[26:16] + 1 : Z42[26:16]; |
Z43_final <= Z43[15] ? Z43[26:16] + 1 : Z43[26:16]; |
Z44_final <= Z44[15] ? Z44[26:16] + 1 : Z44[26:16]; |
Z45_final <= Z45[15] ? Z45[26:16] + 1 : Z45[26:16]; |
Z46_final <= Z46[15] ? Z46[26:16] + 1 : Z46[26:16]; |
Z47_final <= Z47[15] ? Z47[26:16] + 1 : Z47[26:16]; |
Z48_final <= Z48[15] ? Z48[26:16] + 1 : Z48[26:16]; |
Z51_final <= Z51[15] ? Z51[26:16] + 1 : Z51[26:16]; |
Z52_final <= Z52[15] ? Z52[26:16] + 1 : Z52[26:16]; |
Z53_final <= Z53[15] ? Z53[26:16] + 1 : Z53[26:16]; |
Z54_final <= Z54[15] ? Z54[26:16] + 1 : Z54[26:16]; |
Z55_final <= Z55[15] ? Z55[26:16] + 1 : Z55[26:16]; |
Z56_final <= Z56[15] ? Z56[26:16] + 1 : Z56[26:16]; |
Z57_final <= Z57[15] ? Z57[26:16] + 1 : Z57[26:16]; |
Z58_final <= Z58[15] ? Z58[26:16] + 1 : Z58[26:16]; |
Z61_final <= Z61[15] ? Z61[26:16] + 1 : Z61[26:16]; |
Z62_final <= Z62[15] ? Z62[26:16] + 1 : Z62[26:16]; |
Z63_final <= Z63[15] ? Z63[26:16] + 1 : Z63[26:16]; |
Z64_final <= Z64[15] ? Z64[26:16] + 1 : Z64[26:16]; |
Z65_final <= Z65[15] ? Z65[26:16] + 1 : Z65[26:16]; |
Z66_final <= Z66[15] ? Z66[26:16] + 1 : Z66[26:16]; |
Z67_final <= Z67[15] ? Z67[26:16] + 1 : Z67[26:16]; |
Z68_final <= Z68[15] ? Z68[26:16] + 1 : Z68[26:16]; |
Z71_final <= Z71[15] ? Z71[26:16] + 1 : Z71[26:16]; |
Z72_final <= Z72[15] ? Z72[26:16] + 1 : Z72[26:16]; |
Z73_final <= Z73[15] ? Z73[26:16] + 1 : Z73[26:16]; |
Z74_final <= Z74[15] ? Z74[26:16] + 1 : Z74[26:16]; |
Z75_final <= Z75[15] ? Z75[26:16] + 1 : Z75[26:16]; |
Z76_final <= Z76[15] ? Z76[26:16] + 1 : Z76[26:16]; |
Z77_final <= Z77[15] ? Z77[26:16] + 1 : Z77[26:16]; |
Z78_final <= Z78[15] ? Z78[26:16] + 1 : Z78[26:16]; |
Z81_final <= Z81[15] ? Z81[26:16] + 1 : Z81[26:16]; |
Z82_final <= Z82[15] ? Z82[26:16] + 1 : Z82[26:16]; |
Z83_final <= Z83[15] ? Z83[26:16] + 1 : Z83[26:16]; |
Z84_final <= Z84[15] ? Z84[26:16] + 1 : Z84[26:16]; |
Z85_final <= Z85[15] ? Z85[26:16] + 1 : Z85[26:16]; |
Z86_final <= Z86[15] ? Z86[26:16] + 1 : Z86[26:16]; |
Z87_final <= Z87[15] ? Z87[26:16] + 1 : Z87[26:16]; |
Z88_final <= Z88[15] ? Z88[26:16] + 1 : Z88[26:16]; |
end |
end |
|
// output_enable signals the next block, the quantizer, that the input data is ready |
always @(posedge clk) |
begin |
if (rst) |
output_enable <= 0; |
else if (!enable_1) |
output_enable <= 0; |
else if (count_10 == 0 | count_of) |
output_enable <= 0; |
else if (count_10 & count_of == 0) |
output_enable <= 1; |
end |
always @(posedge clk) |
begin |
if (rst) |
Y_temp_11 <= 0; |
else if (enable) |
Y_temp_11 <= data_in * T1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
Y11 <= 0; |
else if (count == 1 & enable == 1) |
Y11 <= Y_temp_11; |
else if (enable) |
Y11 <= Y_temp_11 + Y11; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y_temp_21 <= 0; |
Y_temp_31 <= 0; |
Y_temp_41 <= 0; |
Y_temp_51 <= 0; |
Y_temp_61 <= 0; |
Y_temp_71 <= 0; |
Y_temp_81 <= 0; |
end |
else if (!enable_1) begin |
Y_temp_21 <= 0; |
Y_temp_31 <= 0; |
Y_temp_41 <= 0; |
Y_temp_51 <= 0; |
Y_temp_61 <= 0; |
Y_temp_71 <= 0; |
Y_temp_81 <= 0; |
end |
else if (enable_1) begin |
Y_temp_21 <= data_1 * Y2_mul_input; |
Y_temp_31 <= data_1 * Y3_mul_input; |
Y_temp_41 <= data_1 * Y4_mul_input; |
Y_temp_51 <= data_1 * Y5_mul_input; |
Y_temp_61 <= data_1 * Y6_mul_input; |
Y_temp_71 <= data_1 * Y7_mul_input; |
Y_temp_81 <= data_1 * Y8_mul_input; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y21 <= 0; |
Y31 <= 0; |
Y41 <= 0; |
Y51 <= 0; |
Y61 <= 0; |
Y71 <= 0; |
Y81 <= 0; |
end |
else if (!enable_1) begin |
Y21 <= 0; |
Y31 <= 0; |
Y41 <= 0; |
Y51 <= 0; |
Y61 <= 0; |
Y71 <= 0; |
Y81 <= 0; |
end |
else if (enable_1) begin |
Y21 <= Y_temp_21 + Y21; |
Y31 <= Y_temp_31 + Y31; |
Y41 <= Y_temp_41 + Y41; |
Y51 <= Y_temp_51 + Y51; |
Y61 <= Y_temp_61 + Y61; |
Y71 <= Y_temp_71 + Y71; |
Y81 <= Y_temp_81 + Y81; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; |
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; |
count_10 <= 0; |
end |
else if (!enable) begin |
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0; |
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0; |
count_10 <= 0; |
end |
else if (enable) begin |
count <= count + 1; count_3 <= count_1; count_4 <= count_3; |
count_5 <= count_4; count_6 <= count_5; count_7 <= count_6; |
count_8 <= count_7; count_9 <= count_8; count_10 <= count_9; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count_1 <= 0; |
end |
else if (count != 7 | !enable) begin |
count_1 <= 0; |
end |
else if (count == 7) begin |
count_1 <= 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
count_of <= 0; |
count_of_copy <= 0; |
end |
else if (!enable) begin |
count_of <= 0; |
count_of_copy <= 0; |
end |
else if (count_1 == 1) begin |
count_of <= count_of + 1; |
count_of_copy <= count_of_copy + 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y11_final <= 0; |
end |
else if (count_3 & enable_1) begin |
Y11_final <= Y11 - 25'd5932032; |
/* The Y values weren't centered on 0 before doing the DCT |
128 needs to be subtracted from each Y value before, or in this |
case, 362 is subtracted from the total, because this is the |
total obtained by subtracting 128 from each element |
and then multiplying by the weight |
assigned by the DCT matrix : 128*8*5793 = 5932032 |
This is only needed for the first row, the values in the rest of |
the rows add up to 0 */ |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Y21_final <= 0; Y21_final_prev <= 0; |
Y31_final <= 0; Y31_final_prev <= 0; |
Y41_final <= 0; Y41_final_prev <= 0; |
Y51_final <= 0; Y51_final_prev <= 0; |
Y61_final <= 0; Y61_final_prev <= 0; |
Y71_final <= 0; Y71_final_prev <= 0; |
Y81_final <= 0; Y81_final_prev <= 0; |
end |
else if (!enable_1) begin |
Y21_final <= 0; Y21_final_prev <= 0; |
Y31_final <= 0; Y31_final_prev <= 0; |
Y41_final <= 0; Y41_final_prev <= 0; |
Y51_final <= 0; Y51_final_prev <= 0; |
Y61_final <= 0; Y61_final_prev <= 0; |
Y71_final <= 0; Y71_final_prev <= 0; |
Y81_final <= 0; Y81_final_prev <= 0; |
end |
else if (count_4 & enable_1) begin |
Y21_final <= Y21; Y21_final_prev <= Y21_final; |
Y31_final <= Y31; Y31_final_prev <= Y31_final; |
Y41_final <= Y41; Y41_final_prev <= Y41_final; |
Y51_final <= Y51; Y51_final_prev <= Y51_final; |
Y61_final <= Y61; Y61_final_prev <= Y61_final; |
Y71_final <= Y71; Y71_final_prev <= Y71_final; |
Y81_final <= Y81; Y81_final_prev <= Y81_final; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Y21_final_diff <= 0; Y31_final_diff <= 0; |
Y41_final_diff <= 0; Y51_final_diff <= 0; |
Y61_final_diff <= 0; Y71_final_diff <= 0; |
Y81_final_diff <= 0; |
end |
else if (count_5 & enable_1) begin |
Y21_final_diff <= Y21_final - Y21_final_prev; |
Y31_final_diff <= Y31_final - Y31_final_prev; |
Y41_final_diff <= Y41_final - Y41_final_prev; |
Y51_final_diff <= Y51_final - Y51_final_prev; |
Y61_final_diff <= Y61_final - Y61_final_prev; |
Y71_final_diff <= Y71_final - Y71_final_prev; |
Y81_final_diff <= Y81_final - Y81_final_prev; |
end |
end |
always @(posedge clk) |
begin |
case (count) |
3'b000: Y2_mul_input <= T21; |
3'b001: Y2_mul_input <= T22; |
3'b010: Y2_mul_input <= T23; |
3'b011: Y2_mul_input <= T24; |
3'b100: Y2_mul_input <= T25; |
3'b101: Y2_mul_input <= T26; |
3'b110: Y2_mul_input <= T27; |
3'b111: Y2_mul_input <= T28; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Y3_mul_input <= T31; |
3'b001: Y3_mul_input <= T32; |
3'b010: Y3_mul_input <= T33; |
3'b011: Y3_mul_input <= T34; |
3'b100: Y3_mul_input <= T34; |
3'b101: Y3_mul_input <= T33; |
3'b110: Y3_mul_input <= T32; |
3'b111: Y3_mul_input <= T31; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Y4_mul_input <= T22; |
3'b001: Y4_mul_input <= T25; |
3'b010: Y4_mul_input <= T28; |
3'b011: Y4_mul_input <= T26; |
3'b100: Y4_mul_input <= T23; |
3'b101: Y4_mul_input <= T21; |
3'b110: Y4_mul_input <= T24; |
3'b111: Y4_mul_input <= T27; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Y5_mul_input <= T1; |
3'b001: Y5_mul_input <= T52; |
3'b010: Y5_mul_input <= T52; |
3'b011: Y5_mul_input <= T1; |
3'b100: Y5_mul_input <= T1; |
3'b101: Y5_mul_input <= T52; |
3'b110: Y5_mul_input <= T52; |
3'b111: Y5_mul_input <= T1; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Y6_mul_input <= T23; |
3'b001: Y6_mul_input <= T28; |
3'b010: Y6_mul_input <= T24; |
3'b011: Y6_mul_input <= T22; |
3'b100: Y6_mul_input <= T27; |
3'b101: Y6_mul_input <= T25; |
3'b110: Y6_mul_input <= T21; |
3'b111: Y6_mul_input <= T26; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Y7_mul_input <= T32; |
3'b001: Y7_mul_input <= T34; |
3'b010: Y7_mul_input <= T31; |
3'b011: Y7_mul_input <= T33; |
3'b100: Y7_mul_input <= T33; |
3'b101: Y7_mul_input <= T31; |
3'b110: Y7_mul_input <= T34; |
3'b111: Y7_mul_input <= T32; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count) |
3'b000: Y8_mul_input <= T24; |
3'b001: Y8_mul_input <= T26; |
3'b010: Y8_mul_input <= T22; |
3'b011: Y8_mul_input <= T28; |
3'b100: Y8_mul_input <= T21; |
3'b101: Y8_mul_input <= T27; |
3'b110: Y8_mul_input <= T23; |
3'b111: Y8_mul_input <= T25; |
endcase |
end |
|
// Inverse DCT matrix entries |
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti2_mul_input <= Ti28; |
3'b001: Ti2_mul_input <= Ti21; |
3'b010: Ti2_mul_input <= Ti22; |
3'b011: Ti2_mul_input <= Ti23; |
3'b100: Ti2_mul_input <= Ti24; |
3'b101: Ti2_mul_input <= Ti25; |
3'b110: Ti2_mul_input <= Ti26; |
3'b111: Ti2_mul_input <= Ti27; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti3_mul_input <= Ti31; |
3'b001: Ti3_mul_input <= Ti31; |
3'b010: Ti3_mul_input <= Ti32; |
3'b011: Ti3_mul_input <= Ti33; |
3'b100: Ti3_mul_input <= Ti34; |
3'b101: Ti3_mul_input <= Ti34; |
3'b110: Ti3_mul_input <= Ti33; |
3'b111: Ti3_mul_input <= Ti32; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti4_mul_input <= Ti27; |
3'b001: Ti4_mul_input <= Ti22; |
3'b010: Ti4_mul_input <= Ti25; |
3'b011: Ti4_mul_input <= Ti28; |
3'b100: Ti4_mul_input <= Ti26; |
3'b101: Ti4_mul_input <= Ti23; |
3'b110: Ti4_mul_input <= Ti21; |
3'b111: Ti4_mul_input <= Ti24; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti5_mul_input <= Ti1; |
3'b001: Ti5_mul_input <= Ti1; |
3'b010: Ti5_mul_input <= Ti52; |
3'b011: Ti5_mul_input <= Ti52; |
3'b100: Ti5_mul_input <= Ti1; |
3'b101: Ti5_mul_input <= Ti1; |
3'b110: Ti5_mul_input <= Ti52; |
3'b111: Ti5_mul_input <= Ti52; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti6_mul_input <= Ti26; |
3'b001: Ti6_mul_input <= Ti23; |
3'b010: Ti6_mul_input <= Ti28; |
3'b011: Ti6_mul_input <= Ti24; |
3'b100: Ti6_mul_input <= Ti22; |
3'b101: Ti6_mul_input <= Ti27; |
3'b110: Ti6_mul_input <= Ti25; |
3'b111: Ti6_mul_input <= Ti21; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti7_mul_input <= Ti32; |
3'b001: Ti7_mul_input <= Ti32; |
3'b010: Ti7_mul_input <= Ti34; |
3'b011: Ti7_mul_input <= Ti31; |
3'b100: Ti7_mul_input <= Ti33; |
3'b101: Ti7_mul_input <= Ti33; |
3'b110: Ti7_mul_input <= Ti31; |
3'b111: Ti7_mul_input <= Ti34; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (count_of_copy) |
3'b000: Ti8_mul_input <= Ti25; |
3'b001: Ti8_mul_input <= Ti24; |
3'b010: Ti8_mul_input <= Ti26; |
3'b011: Ti8_mul_input <= Ti22; |
3'b100: Ti8_mul_input <= Ti28; |
3'b101: Ti8_mul_input <= Ti21; |
3'b110: Ti8_mul_input <= Ti27; |
3'b111: Ti8_mul_input <= Ti23; |
endcase |
end |
|
// Rounding stage |
always @(posedge clk) |
begin |
if (rst) begin |
data_1 <= 0; |
Y11_final_1 <= 0; Y21_final_1 <= 0; Y31_final_1 <= 0; Y41_final_1 <= 0; |
Y51_final_1 <= 0; Y61_final_1 <= 0; Y71_final_1 <= 0; Y81_final_1 <= 0; |
Y11_final_2 <= 0; Y21_final_2 <= 0; Y31_final_2 <= 0; Y41_final_2 <= 0; |
Y51_final_2 <= 0; Y61_final_2 <= 0; Y71_final_2 <= 0; Y81_final_2 <= 0; |
Y11_final_3 <= 0; Y11_final_4 <= 0; |
end |
else if (enable) begin |
data_1 <= data_in; |
Y11_final_1 <= Y11_final[11] ? Y11_final[24:12] + 1 : Y11_final[24:12]; |
Y11_final_2[31:13] <= Y11_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y11_final_2[12:0] <= Y11_final_1; |
// Need to sign extend Y11_final_1 and the other registers to store a negative |
// number as a twos complement number. If you don't sign extend, then a negative number |
// will be stored incorrectly as a positive number. For example, -215 would be stored |
// as 1833 without sign extending |
Y11_final_3 <= Y11_final_2; |
Y11_final_4 <= Y11_final_3; |
Y21_final_1 <= Y21_final_diff[11] ? Y21_final_diff[24:12] + 1 : Y21_final_diff[24:12]; |
Y21_final_2[31:13] <= Y21_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y21_final_2[12:0] <= Y21_final_1; |
Y31_final_1 <= Y31_final_diff[11] ? Y31_final_diff[24:12] + 1 : Y31_final_diff[24:12]; |
Y31_final_2[31:13] <= Y31_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y31_final_2[12:0] <= Y31_final_1; |
Y41_final_1 <= Y41_final_diff[11] ? Y41_final_diff[24:12] + 1 : Y41_final_diff[24:12]; |
Y41_final_2[31:13] <= Y41_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y41_final_2[12:0] <= Y41_final_1; |
Y51_final_1 <= Y51_final_diff[11] ? Y51_final_diff[24:12] + 1 : Y51_final_diff[24:12]; |
Y51_final_2[31:13] <= Y51_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y51_final_2[12:0] <= Y51_final_1; |
Y61_final_1 <= Y61_final_diff[11] ? Y61_final_diff[24:12] + 1 : Y61_final_diff[24:12]; |
Y61_final_2[31:13] <= Y61_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y61_final_2[12:0] <= Y61_final_1; |
Y71_final_1 <= Y71_final_diff[11] ? Y71_final_diff[24:12] + 1 : Y71_final_diff[24:12]; |
Y71_final_2[31:13] <= Y71_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y71_final_2[12:0] <= Y71_final_1; |
Y81_final_1 <= Y81_final_diff[11] ? Y81_final_diff[24:12] + 1 : Y81_final_diff[24:12]; |
Y81_final_2[31:13] <= Y81_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Y81_final_2[12:0] <= Y81_final_1; |
// The bit in place 11 is the fraction part, for rounding purposes |
// if it is 1, then you need to add 1 to the bits in 24-12, |
// if bit 11 is 0, then the bits in 24-12 won't change |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; |
end |
else begin |
enable_1 <= enable; |
end |
end |
|
endmodule |
/jpegencode/trunk/yd_q_h.v
0,0 → 1,140
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module combines the dct, quantizer, and huffman modules. */ |
|
`timescale 1ns / 100ps |
|
module yd_q_h(clk, rst, enable, data_in, |
JPEG_bitstream, |
data_ready, y_orc, end_of_block_output, |
end_of_block_empty); |
input clk; |
input rst; |
input enable; |
input [7:0] data_in; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output [4:0] y_orc; |
output end_of_block_output; |
output end_of_block_empty; |
|
|
wire dct_enable, quantizer_enable; |
wire [10:0] Z11_final, Z12_final, Z13_final, Z14_final; |
wire [10:0] Z15_final, Z16_final, Z17_final, Z18_final; |
wire [10:0] Z21_final, Z22_final, Z23_final, Z24_final; |
wire [10:0] Z25_final, Z26_final, Z27_final, Z28_final; |
wire [10:0] Z31_final, Z32_final, Z33_final, Z34_final; |
wire [10:0] Z35_final, Z36_final, Z37_final, Z38_final; |
wire [10:0] Z41_final, Z42_final, Z43_final, Z44_final; |
wire [10:0] Z45_final, Z46_final, Z47_final, Z48_final; |
wire [10:0] Z51_final, Z52_final, Z53_final, Z54_final; |
wire [10:0] Z55_final, Z56_final, Z57_final, Z58_final; |
wire [10:0] Z61_final, Z62_final, Z63_final, Z64_final; |
wire [10:0] Z65_final, Z66_final, Z67_final, Z68_final; |
wire [10:0] Z71_final, Z72_final, Z73_final, Z74_final; |
wire [10:0] Z75_final, Z76_final, Z77_final, Z78_final; |
wire [10:0] Z81_final, Z82_final, Z83_final, Z84_final; |
wire [10:0] Z85_final, Z86_final, Z87_final, Z88_final; |
wire [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18; |
wire [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28; |
wire [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
wire [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48; |
wire [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58; |
wire [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
wire [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78; |
wire [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88; |
|
y_dct u1( |
.clk(clk),.rst(rst), .enable(enable), .data_in(data_in), |
.Z11_final(Z11_final), .Z12_final(Z12_final), |
.Z13_final(Z13_final), .Z14_final(Z14_final), .Z15_final(Z15_final), .Z16_final(Z16_final), |
.Z17_final(Z17_final), .Z18_final(Z18_final), .Z21_final(Z21_final), .Z22_final(Z22_final), |
.Z23_final(Z23_final), .Z24_final(Z24_final), .Z25_final(Z25_final), .Z26_final(Z26_final), |
.Z27_final(Z27_final), .Z28_final(Z28_final), .Z31_final(Z31_final), .Z32_final(Z32_final), |
.Z33_final(Z33_final), .Z34_final(Z34_final), .Z35_final(Z35_final), .Z36_final(Z36_final), |
.Z37_final(Z37_final), .Z38_final(Z38_final), .Z41_final(Z41_final), .Z42_final(Z42_final), |
.Z43_final(Z43_final), .Z44_final(Z44_final), .Z45_final(Z45_final), .Z46_final(Z46_final), |
.Z47_final(Z47_final), .Z48_final(Z48_final), .Z51_final(Z51_final), .Z52_final(Z52_final), |
.Z53_final(Z53_final), .Z54_final(Z54_final), .Z55_final(Z55_final), .Z56_final(Z56_final), |
.Z57_final(Z57_final), .Z58_final(Z58_final), .Z61_final(Z61_final), .Z62_final(Z62_final), |
.Z63_final(Z63_final), .Z64_final(Z64_final), .Z65_final(Z65_final), .Z66_final(Z66_final), |
.Z67_final(Z67_final), .Z68_final(Z68_final), .Z71_final(Z71_final), .Z72_final(Z72_final), |
.Z73_final(Z73_final), .Z74_final(Z74_final), .Z75_final(Z75_final), .Z76_final(Z76_final), |
.Z77_final(Z77_final), .Z78_final(Z78_final), .Z81_final(Z81_final), .Z82_final(Z82_final), |
.Z83_final(Z83_final), .Z84_final(Z84_final), .Z85_final(Z85_final), .Z86_final(Z86_final), |
.Z87_final(Z87_final), .Z88_final(Z88_final), .output_enable(dct_enable)); |
|
y_quantizer u2( |
.clk(clk),.rst(rst),.enable(dct_enable), |
.Z11(Z11_final), .Z12(Z12_final), .Z13(Z13_final), .Z14(Z14_final), |
.Z15(Z15_final), .Z16(Z16_final), .Z17(Z17_final), .Z18(Z18_final), |
.Z21(Z21_final), .Z22(Z22_final), .Z23(Z23_final), .Z24(Z24_final), |
.Z25(Z25_final), .Z26(Z26_final), .Z27(Z27_final), .Z28(Z28_final), |
.Z31(Z31_final), .Z32(Z32_final), .Z33(Z33_final), .Z34(Z34_final), |
.Z35(Z35_final), .Z36(Z36_final), .Z37(Z37_final), .Z38(Z38_final), |
.Z41(Z41_final), .Z42(Z42_final), .Z43(Z43_final), .Z44(Z44_final), |
.Z45(Z45_final), .Z46(Z46_final), .Z47(Z47_final), .Z48(Z48_final), |
.Z51(Z51_final), .Z52(Z52_final), .Z53(Z53_final), .Z54(Z54_final), |
.Z55(Z55_final), .Z56(Z56_final), .Z57(Z57_final), .Z58(Z58_final), |
.Z61(Z61_final), .Z62(Z62_final), .Z63(Z63_final), .Z64(Z64_final), |
.Z65(Z65_final), .Z66(Z66_final), .Z67(Z67_final), .Z68(Z68_final), |
.Z71(Z71_final), .Z72(Z72_final), .Z73(Z73_final), .Z74(Z74_final), |
.Z75(Z75_final), .Z76(Z76_final), .Z77(Z77_final), .Z78(Z78_final), |
.Z81(Z81_final), .Z82(Z82_final), .Z83(Z83_final), .Z84(Z84_final), |
.Z85(Z85_final), .Z86(Z86_final), .Z87(Z87_final), .Z88(Z88_final), |
.Q11(Q11), .Q12(Q12), .Q13(Q13), .Q14(Q14), .Q15(Q15), .Q16(Q16), .Q17(Q17), .Q18(Q18), |
.Q21(Q21), .Q22(Q22), .Q23(Q23), .Q24(Q24), .Q25(Q25), .Q26(Q26), .Q27(Q27), .Q28(Q28), |
.Q31(Q31), .Q32(Q32), .Q33(Q33), .Q34(Q34), .Q35(Q35), .Q36(Q36), .Q37(Q37), .Q38(Q38), |
.Q41(Q41), .Q42(Q42), .Q43(Q43), .Q44(Q44), .Q45(Q45), .Q46(Q46), .Q47(Q47), .Q48(Q48), |
.Q51(Q51), .Q52(Q52), .Q53(Q53), .Q54(Q54), .Q55(Q55), .Q56(Q56), .Q57(Q57), .Q58(Q58), |
.Q61(Q61), .Q62(Q62), .Q63(Q63), .Q64(Q64), .Q65(Q65), .Q66(Q66), .Q67(Q67), .Q68(Q68), |
.Q71(Q71), .Q72(Q72), .Q73(Q73), .Q74(Q74), .Q75(Q75), .Q76(Q76), .Q77(Q77), .Q78(Q78), |
.Q81(Q81), .Q82(Q82), .Q83(Q83), .Q84(Q84), .Q85(Q85), .Q86(Q86), .Q87(Q87), .Q88(Q88), |
.out_enable(quantizer_enable)); |
|
y_huff u3(.clk(clk), .rst(rst), .enable(quantizer_enable), |
.Y11(Q11), .Y12(Q21), .Y13(Q31), .Y14(Q41), .Y15(Q51), .Y16(Q61), .Y17(Q71), .Y18(Q81), |
.Y21(Q12), .Y22(Q22), .Y23(Q32), .Y24(Q42), .Y25(Q52), .Y26(Q62), .Y27(Q72), .Y28(Q82), |
.Y31(Q13), .Y32(Q23), .Y33(Q33), .Y34(Q43), .Y35(Q53), .Y36(Q63), .Y37(Q73), .Y38(Q83), |
.Y41(Q14), .Y42(Q24), .Y43(Q34), .Y44(Q44), .Y45(Q54), .Y46(Q64), .Y47(Q74), .Y48(Q84), |
.Y51(Q15), .Y52(Q25), .Y53(Q35), .Y54(Q45), .Y55(Q55), .Y56(Q65), .Y57(Q75), .Y58(Q85), |
.Y61(Q16), .Y62(Q26), .Y63(Q36), .Y64(Q46), .Y65(Q56), .Y66(Q66), .Y67(Q76), .Y68(Q86), |
.Y71(Q17), .Y72(Q27), .Y73(Q37), .Y74(Q47), .Y75(Q57), .Y76(Q67), .Y77(Q77), .Y78(Q87), |
.Y81(Q18), .Y82(Q28), .Y83(Q38), .Y84(Q48), .Y85(Q58), .Y86(Q68), .Y87(Q78), .Y88(Q88), |
.JPEG_bitstream(JPEG_bitstream), .data_ready(data_ready), .output_reg_count(y_orc), |
.end_of_block_output(end_of_block_output), |
.end_of_block_empty(end_of_block_empty)); |
|
endmodule |
/jpegencode/trunk/cr_quantizer.v
0,0 → 1,629
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module comes after the dct module. The 64 matrix entries calculated after |
performing the 2D DCT are inputs to this quantization module. This module quantizes |
the entire 8x8 block of Cr values. The outputs from this module |
are the quantized Cr values for one 8x8 block. */ |
|
`timescale 1ns / 100ps |
|
module cr_quantizer(clk, rst, enable, |
Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, |
Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, |
Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68, |
Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88, |
Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, |
Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, |
Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68, |
Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88, |
out_enable); |
input clk; |
input rst; |
input enable; |
input [10:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24; |
input [10:0] Z25, Z26, Z27, Z28, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38; |
input [10:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z51, Z52, Z53, Z54; |
input [10:0] Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68; |
input [10:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84; |
input [10:0] Z85, Z86, Z87, Z88; |
output [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24; |
output [10:0] Q25, Q26, Q27, Q28, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
output [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q51, Q52, Q53, Q54; |
output [10:0] Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
output [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84; |
output [10:0] Q85, Q86, Q87, Q88; |
output out_enable; |
|
/* Below are the quantization values, these can be changed for different |
quantization levels */ |
|
parameter Q1_1 = 1; |
parameter Q1_2 = 1; |
parameter Q1_3 = 1; |
parameter Q1_4 = 1; |
parameter Q1_5 = 1; |
parameter Q1_6 = 1; |
parameter Q1_7 = 1; |
parameter Q1_8 = 1; |
parameter Q2_1 = 1; |
parameter Q2_2 = 1; |
parameter Q2_3 = 1; |
parameter Q2_4 = 1; |
parameter Q2_5 = 1; |
parameter Q2_6 = 1; |
parameter Q2_7 = 1; |
parameter Q2_8 = 1; |
parameter Q3_1 = 1; |
parameter Q3_2 = 1; |
parameter Q3_3 = 1; |
parameter Q3_4 = 1; |
parameter Q3_5 = 1; |
parameter Q3_6 = 1; |
parameter Q3_7 = 1; |
parameter Q3_8 = 1; |
parameter Q4_1 = 1; |
parameter Q4_2 = 1; |
parameter Q4_3 = 1; |
parameter Q4_4 = 1; |
parameter Q4_5 = 1; |
parameter Q4_6 = 1; |
parameter Q4_7 = 1; |
parameter Q4_8 = 1; |
parameter Q5_1 = 1; |
parameter Q5_2 = 1; |
parameter Q5_3 = 1; |
parameter Q5_4 = 1; |
parameter Q5_5 = 1; |
parameter Q5_6 = 1; |
parameter Q5_7 = 1; |
parameter Q5_8 = 1; |
parameter Q6_1 = 1; |
parameter Q6_2 = 1; |
parameter Q6_3 = 1; |
parameter Q6_4 = 1; |
parameter Q6_5 = 1; |
parameter Q6_6 = 1; |
parameter Q6_7 = 1; |
parameter Q6_8 = 1; |
parameter Q7_1 = 1; |
parameter Q7_2 = 1; |
parameter Q7_3 = 1; |
parameter Q7_4 = 1; |
parameter Q7_5 = 1; |
parameter Q7_6 = 1; |
parameter Q7_7 = 1; |
parameter Q7_8 = 1; |
parameter Q8_1 = 1; |
parameter Q8_2 = 1; |
parameter Q8_3 = 1; |
parameter Q8_4 = 1; |
parameter Q8_5 = 1; |
parameter Q8_6 = 1; |
parameter Q8_7 = 1; |
parameter Q8_8 = 1; |
// End of Quantization Values |
|
/* The following parameters hold the values of 4096 divided by the corresponding |
individual quantization values. These values are needed to get around |
actually dividing the Y, Cb, and Cr values by the quantization values. |
Instead, you can multiply by the values below, and then divide by 4096 |
to get the same result. And 4096 = 2^12, so instead of dividing, you can |
just shift the bottom 12 bits out. This is a lossy process, as 4096/Q divided |
by 4096 doesn't always equal the same value as if you were just dividing by Q. But |
the quantization process is also lossy, so the additional loss of precision is |
negligible. To decrease the loss, you could use a larger number than 4096 to |
get around the actual use of division. Like take 8192/Q and then divide by 8192.*/ |
|
parameter QQ1_1 = 4096/Q1_1; |
parameter QQ1_2 = 4096/Q1_2; |
parameter QQ1_3 = 4096/Q1_3; |
parameter QQ1_4 = 4096/Q1_4; |
parameter QQ1_5 = 4096/Q1_5; |
parameter QQ1_6 = 4096/Q1_6; |
parameter QQ1_7 = 4096/Q1_7; |
parameter QQ1_8 = 4096/Q1_8; |
parameter QQ2_1 = 4096/Q2_1; |
parameter QQ2_2 = 4096/Q2_2; |
parameter QQ2_3 = 4096/Q2_3; |
parameter QQ2_4 = 4096/Q2_4; |
parameter QQ2_5 = 4096/Q2_5; |
parameter QQ2_6 = 4096/Q2_6; |
parameter QQ2_7 = 4096/Q2_7; |
parameter QQ2_8 = 4096/Q2_8; |
parameter QQ3_1 = 4096/Q3_1; |
parameter QQ3_2 = 4096/Q3_2; |
parameter QQ3_3 = 4096/Q3_3; |
parameter QQ3_4 = 4096/Q3_4; |
parameter QQ3_5 = 4096/Q3_5; |
parameter QQ3_6 = 4096/Q3_6; |
parameter QQ3_7 = 4096/Q3_7; |
parameter QQ3_8 = 4096/Q3_8; |
parameter QQ4_1 = 4096/Q4_1; |
parameter QQ4_2 = 4096/Q4_2; |
parameter QQ4_3 = 4096/Q4_3; |
parameter QQ4_4 = 4096/Q4_4; |
parameter QQ4_5 = 4096/Q4_5; |
parameter QQ4_6 = 4096/Q4_6; |
parameter QQ4_7 = 4096/Q4_7; |
parameter QQ4_8 = 4096/Q4_8; |
parameter QQ5_1 = 4096/Q5_1; |
parameter QQ5_2 = 4096/Q5_2; |
parameter QQ5_3 = 4096/Q5_3; |
parameter QQ5_4 = 4096/Q5_4; |
parameter QQ5_5 = 4096/Q5_5; |
parameter QQ5_6 = 4096/Q5_6; |
parameter QQ5_7 = 4096/Q5_7; |
parameter QQ5_8 = 4096/Q5_8; |
parameter QQ6_1 = 4096/Q6_1; |
parameter QQ6_2 = 4096/Q6_2; |
parameter QQ6_3 = 4096/Q6_3; |
parameter QQ6_4 = 4096/Q6_4; |
parameter QQ6_5 = 4096/Q6_5; |
parameter QQ6_6 = 4096/Q6_6; |
parameter QQ6_7 = 4096/Q6_7; |
parameter QQ6_8 = 4096/Q6_8; |
parameter QQ7_1 = 4096/Q7_1; |
parameter QQ7_2 = 4096/Q7_2; |
parameter QQ7_3 = 4096/Q7_3; |
parameter QQ7_4 = 4096/Q7_4; |
parameter QQ7_5 = 4096/Q7_5; |
parameter QQ7_6 = 4096/Q7_6; |
parameter QQ7_7 = 4096/Q7_7; |
parameter QQ7_8 = 4096/Q7_8; |
parameter QQ8_1 = 4096/Q8_1; |
parameter QQ8_2 = 4096/Q8_2; |
parameter QQ8_3 = 4096/Q8_3; |
parameter QQ8_4 = 4096/Q8_4; |
parameter QQ8_5 = 4096/Q8_5; |
parameter QQ8_6 = 4096/Q8_6; |
parameter QQ8_7 = 4096/Q8_7; |
parameter QQ8_8 = 4096/Q8_8; |
|
wire [12:0] QM1_1 = QQ1_1; |
wire [12:0] QM1_2 = QQ1_2; |
wire [12:0] QM1_3 = QQ1_3; |
wire [12:0] QM1_4 = QQ1_4; |
wire [12:0] QM1_5 = QQ1_5; |
wire [12:0] QM1_6 = QQ1_6; |
wire [12:0] QM1_7 = QQ1_7; |
wire [12:0] QM1_8 = QQ1_8; |
wire [12:0] QM2_1 = QQ2_1; |
wire [12:0] QM2_2 = QQ2_2; |
wire [12:0] QM2_3 = QQ2_3; |
wire [12:0] QM2_4 = QQ2_4; |
wire [12:0] QM2_5 = QQ2_5; |
wire [12:0] QM2_6 = QQ2_6; |
wire [12:0] QM2_7 = QQ2_7; |
wire [12:0] QM2_8 = QQ2_8; |
wire [12:0] QM3_1 = QQ3_1; |
wire [12:0] QM3_2 = QQ3_2; |
wire [12:0] QM3_3 = QQ3_3; |
wire [12:0] QM3_4 = QQ3_4; |
wire [12:0] QM3_5 = QQ3_5; |
wire [12:0] QM3_6 = QQ3_6; |
wire [12:0] QM3_7 = QQ3_7; |
wire [12:0] QM3_8 = QQ3_8; |
wire [12:0] QM4_1 = QQ4_1; |
wire [12:0] QM4_2 = QQ4_2; |
wire [12:0] QM4_3 = QQ4_3; |
wire [12:0] QM4_4 = QQ4_4; |
wire [12:0] QM4_5 = QQ4_5; |
wire [12:0] QM4_6 = QQ4_6; |
wire [12:0] QM4_7 = QQ4_7; |
wire [12:0] QM4_8 = QQ4_8; |
wire [12:0] QM5_1 = QQ5_1; |
wire [12:0] QM5_2 = QQ5_2; |
wire [12:0] QM5_3 = QQ5_3; |
wire [12:0] QM5_4 = QQ5_4; |
wire [12:0] QM5_5 = QQ5_5; |
wire [12:0] QM5_6 = QQ5_6; |
wire [12:0] QM5_7 = QQ5_7; |
wire [12:0] QM5_8 = QQ5_8; |
wire [12:0] QM6_1 = QQ6_1; |
wire [12:0] QM6_2 = QQ6_2; |
wire [12:0] QM6_3 = QQ6_3; |
wire [12:0] QM6_4 = QQ6_4; |
wire [12:0] QM6_5 = QQ6_5; |
wire [12:0] QM6_6 = QQ6_6; |
wire [12:0] QM6_7 = QQ6_7; |
wire [12:0] QM6_8 = QQ6_8; |
wire [12:0] QM7_1 = QQ7_1; |
wire [12:0] QM7_2 = QQ7_2; |
wire [12:0] QM7_3 = QQ7_3; |
wire [12:0] QM7_4 = QQ7_4; |
wire [12:0] QM7_5 = QQ7_5; |
wire [12:0] QM7_6 = QQ7_6; |
wire [12:0] QM7_7 = QQ7_7; |
wire [12:0] QM7_8 = QQ7_8; |
wire [12:0] QM8_1 = QQ8_1; |
wire [12:0] QM8_2 = QQ8_2; |
wire [12:0] QM8_3 = QQ8_3; |
wire [12:0] QM8_4 = QQ8_4; |
wire [12:0] QM8_5 = QQ8_5; |
wire [12:0] QM8_6 = QQ8_6; |
wire [12:0] QM8_7 = QQ8_7; |
wire [12:0] QM8_8 = QQ8_8; |
reg [22:0] Z11_temp, Z12_temp, Z13_temp, Z14_temp, Z15_temp, Z16_temp, Z17_temp, Z18_temp; |
reg [22:0] Z21_temp, Z22_temp, Z23_temp, Z24_temp, Z25_temp, Z26_temp, Z27_temp, Z28_temp; |
reg [22:0] Z31_temp, Z32_temp, Z33_temp, Z34_temp, Z35_temp, Z36_temp, Z37_temp, Z38_temp; |
reg [22:0] Z41_temp, Z42_temp, Z43_temp, Z44_temp, Z45_temp, Z46_temp, Z47_temp, Z48_temp; |
reg [22:0] Z51_temp, Z52_temp, Z53_temp, Z54_temp, Z55_temp, Z56_temp, Z57_temp, Z58_temp; |
reg [22:0] Z61_temp, Z62_temp, Z63_temp, Z64_temp, Z65_temp, Z66_temp, Z67_temp, Z68_temp; |
reg [22:0] Z71_temp, Z72_temp, Z73_temp, Z74_temp, Z75_temp, Z76_temp, Z77_temp, Z78_temp; |
reg [22:0] Z81_temp, Z82_temp, Z83_temp, Z84_temp, Z85_temp, Z86_temp, Z87_temp, Z88_temp; |
reg [22:0] Z11_temp_1, Z12_temp_1, Z13_temp_1, Z14_temp_1, Z15_temp_1, Z16_temp_1, Z17_temp_1, Z18_temp_1; |
reg [22:0] Z21_temp_1, Z22_temp_1, Z23_temp_1, Z24_temp_1, Z25_temp_1, Z26_temp_1, Z27_temp_1, Z28_temp_1; |
reg [22:0] Z31_temp_1, Z32_temp_1, Z33_temp_1, Z34_temp_1, Z35_temp_1, Z36_temp_1, Z37_temp_1, Z38_temp_1; |
reg [22:0] Z41_temp_1, Z42_temp_1, Z43_temp_1, Z44_temp_1, Z45_temp_1, Z46_temp_1, Z47_temp_1, Z48_temp_1; |
reg [22:0] Z51_temp_1, Z52_temp_1, Z53_temp_1, Z54_temp_1, Z55_temp_1, Z56_temp_1, Z57_temp_1, Z58_temp_1; |
reg [22:0] Z61_temp_1, Z62_temp_1, Z63_temp_1, Z64_temp_1, Z65_temp_1, Z66_temp_1, Z67_temp_1, Z68_temp_1; |
reg [22:0] Z71_temp_1, Z72_temp_1, Z73_temp_1, Z74_temp_1, Z75_temp_1, Z76_temp_1, Z77_temp_1, Z78_temp_1; |
reg [22:0] Z81_temp_1, Z82_temp_1, Z83_temp_1, Z84_temp_1, Z85_temp_1, Z86_temp_1, Z87_temp_1, Z88_temp_1; |
reg [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18; |
reg [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28; |
reg [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
reg [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48; |
reg [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58; |
reg [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
reg [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78; |
reg [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88; |
reg out_enable, enable_1, enable_2, enable_3; |
integer Z11_int, Z12_int, Z13_int, Z14_int, Z15_int, Z16_int, Z17_int, Z18_int; |
integer Z21_int, Z22_int, Z23_int, Z24_int, Z25_int, Z26_int, Z27_int, Z28_int; |
integer Z31_int, Z32_int, Z33_int, Z34_int, Z35_int, Z36_int, Z37_int, Z38_int; |
integer Z41_int, Z42_int, Z43_int, Z44_int, Z45_int, Z46_int, Z47_int, Z48_int; |
integer Z51_int, Z52_int, Z53_int, Z54_int, Z55_int, Z56_int, Z57_int, Z58_int; |
integer Z61_int, Z62_int, Z63_int, Z64_int, Z65_int, Z66_int, Z67_int, Z68_int; |
integer Z71_int, Z72_int, Z73_int, Z74_int, Z75_int, Z76_int, Z77_int, Z78_int; |
integer Z81_int, Z82_int, Z83_int, Z84_int, Z85_int, Z86_int, Z87_int, Z88_int; |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_int <= 0; Z12_int <= 0; Z13_int <= 0; Z14_int <= 0; |
Z15_int <= 0; Z16_int <= 0; Z17_int <= 0; Z18_int <= 0; |
Z21_int <= 0; Z22_int <= 0; Z23_int <= 0; Z24_int <= 0; |
Z25_int <= 0; Z26_int <= 0; Z27_int <= 0; Z28_int <= 0; |
Z31_int <= 0; Z32_int <= 0; Z33_int <= 0; Z34_int <= 0; |
Z35_int <= 0; Z36_int <= 0; Z37_int <= 0; Z38_int <= 0; |
Z41_int <= 0; Z42_int <= 0; Z43_int <= 0; Z44_int <= 0; |
Z45_int <= 0; Z46_int <= 0; Z47_int <= 0; Z48_int <= 0; |
Z51_int <= 0; Z52_int <= 0; Z53_int <= 0; Z54_int <= 0; |
Z55_int <= 0; Z56_int <= 0; Z57_int <= 0; Z58_int <= 0; |
Z61_int <= 0; Z62_int <= 0; Z63_int <= 0; Z64_int <= 0; |
Z65_int <= 0; Z66_int <= 0; Z67_int <= 0; Z68_int <= 0; |
Z71_int <= 0; Z72_int <= 0; Z73_int <= 0; Z74_int <= 0; |
Z75_int <= 0; Z76_int <= 0; Z77_int <= 0; Z78_int <= 0; |
Z81_int <= 0; Z82_int <= 0; Z83_int <= 0; Z84_int <= 0; |
Z85_int <= 0; Z86_int <= 0; Z87_int <= 0; Z88_int <= 0; |
end |
else if (enable) begin |
Z11_int[10:0] <= Z11; Z12_int[10:0] <= Z12; Z13_int[10:0] <= Z13; Z14_int[10:0] <= Z14; |
Z15_int[10:0] <= Z15; Z16_int[10:0] <= Z16; Z17_int[10:0] <= Z17; Z18_int[10:0] <= Z18; |
Z21_int[10:0] <= Z21; Z22_int[10:0] <= Z22; Z23_int[10:0] <= Z23; Z24_int[10:0] <= Z24; |
Z25_int[10:0] <= Z25; Z26_int[10:0] <= Z26; Z27_int[10:0] <= Z27; Z28_int[10:0] <= Z28; |
Z31_int[10:0] <= Z31; Z32_int[10:0] <= Z32; Z33_int[10:0] <= Z33; Z34_int[10:0] <= Z34; |
Z35_int[10:0] <= Z35; Z36_int[10:0] <= Z36; Z37_int[10:0] <= Z37; Z38_int[10:0] <= Z38; |
Z41_int[10:0] <= Z41; Z42_int[10:0] <= Z42; Z43_int[10:0] <= Z43; Z44_int[10:0] <= Z44; |
Z45_int[10:0] <= Z45; Z46_int[10:0] <= Z46; Z47_int[10:0] <= Z47; Z48_int[10:0] <= Z48; |
Z51_int[10:0] <= Z51; Z52_int[10:0] <= Z52; Z53_int[10:0] <= Z53; Z54_int[10:0] <= Z54; |
Z55_int[10:0] <= Z55; Z56_int[10:0] <= Z56; Z57_int[10:0] <= Z57; Z58_int[10:0] <= Z58; |
Z61_int[10:0] <= Z61; Z62_int[10:0] <= Z62; Z63_int[10:0] <= Z63; Z64_int[10:0] <= Z64; |
Z65_int[10:0] <= Z65; Z66_int[10:0] <= Z66; Z67_int[10:0] <= Z67; Z68_int[10:0] <= Z68; |
Z71_int[10:0] <= Z71; Z72_int[10:0] <= Z72; Z73_int[10:0] <= Z73; Z74_int[10:0] <= Z74; |
Z75_int[10:0] <= Z75; Z76_int[10:0] <= Z76; Z77_int[10:0] <= Z77; Z78_int[10:0] <= Z78; |
Z81_int[10:0] <= Z81; Z82_int[10:0] <= Z82; Z83_int[10:0] <= Z83; Z84_int[10:0] <= Z84; |
Z85_int[10:0] <= Z85; Z86_int[10:0] <= Z86; Z87_int[10:0] <= Z87; Z88_int[10:0] <= Z88; |
// sign extend to make Z11_int a twos complement representation of Z11 |
Z11_int[31:11] <= Z11[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z12_int[31:11] <= Z12[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z13_int[31:11] <= Z13[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z14_int[31:11] <= Z14[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z15_int[31:11] <= Z15[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z16_int[31:11] <= Z16[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z17_int[31:11] <= Z17[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z18_int[31:11] <= Z18[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z21_int[31:11] <= Z21[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z22_int[31:11] <= Z22[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z23_int[31:11] <= Z23[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z24_int[31:11] <= Z24[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z25_int[31:11] <= Z25[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z26_int[31:11] <= Z26[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z27_int[31:11] <= Z27[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z28_int[31:11] <= Z28[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z31_int[31:11] <= Z31[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z32_int[31:11] <= Z32[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z33_int[31:11] <= Z33[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z34_int[31:11] <= Z34[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z35_int[31:11] <= Z35[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z36_int[31:11] <= Z36[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z37_int[31:11] <= Z37[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z38_int[31:11] <= Z38[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z41_int[31:11] <= Z41[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z42_int[31:11] <= Z42[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z43_int[31:11] <= Z43[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z44_int[31:11] <= Z44[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z45_int[31:11] <= Z45[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z46_int[31:11] <= Z46[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z47_int[31:11] <= Z47[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z48_int[31:11] <= Z48[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z51_int[31:11] <= Z51[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z52_int[31:11] <= Z52[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z53_int[31:11] <= Z53[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z54_int[31:11] <= Z54[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z55_int[31:11] <= Z55[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z56_int[31:11] <= Z56[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z57_int[31:11] <= Z57[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z58_int[31:11] <= Z58[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z61_int[31:11] <= Z61[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z62_int[31:11] <= Z62[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z63_int[31:11] <= Z63[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z64_int[31:11] <= Z64[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z65_int[31:11] <= Z65[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z66_int[31:11] <= Z66[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z67_int[31:11] <= Z67[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z68_int[31:11] <= Z68[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z71_int[31:11] <= Z71[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z72_int[31:11] <= Z72[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z73_int[31:11] <= Z73[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z74_int[31:11] <= Z74[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z75_int[31:11] <= Z75[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z76_int[31:11] <= Z76[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z77_int[31:11] <= Z77[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z78_int[31:11] <= Z78[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z81_int[31:11] <= Z81[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z82_int[31:11] <= Z82[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z83_int[31:11] <= Z83[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z84_int[31:11] <= Z84[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z85_int[31:11] <= Z85[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z86_int[31:11] <= Z86[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z87_int[31:11] <= Z87[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z88_int[31:11] <= Z88[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_temp <= 0; Z12_temp <= 0; Z13_temp <= 0; Z14_temp <= 0; |
Z12_temp <= 0; Z16_temp <= 0; Z17_temp <= 0; Z18_temp <= 0; |
Z21_temp <= 0; Z22_temp <= 0; Z23_temp <= 0; Z24_temp <= 0; |
Z22_temp <= 0; Z26_temp <= 0; Z27_temp <= 0; Z28_temp <= 0; |
Z31_temp <= 0; Z32_temp <= 0; Z33_temp <= 0; Z34_temp <= 0; |
Z32_temp <= 0; Z36_temp <= 0; Z37_temp <= 0; Z38_temp <= 0; |
Z41_temp <= 0; Z42_temp <= 0; Z43_temp <= 0; Z44_temp <= 0; |
Z42_temp <= 0; Z46_temp <= 0; Z47_temp <= 0; Z48_temp <= 0; |
Z51_temp <= 0; Z52_temp <= 0; Z53_temp <= 0; Z54_temp <= 0; |
Z52_temp <= 0; Z56_temp <= 0; Z57_temp <= 0; Z58_temp <= 0; |
Z61_temp <= 0; Z62_temp <= 0; Z63_temp <= 0; Z64_temp <= 0; |
Z62_temp <= 0; Z66_temp <= 0; Z67_temp <= 0; Z68_temp <= 0; |
Z71_temp <= 0; Z72_temp <= 0; Z73_temp <= 0; Z74_temp <= 0; |
Z72_temp <= 0; Z76_temp <= 0; Z77_temp <= 0; Z78_temp <= 0; |
Z81_temp <= 0; Z82_temp <= 0; Z83_temp <= 0; Z84_temp <= 0; |
Z82_temp <= 0; Z86_temp <= 0; Z87_temp <= 0; Z88_temp <= 0; |
end |
else if (enable_1) begin |
Z11_temp <= Z11_int * QM1_1; Z12_temp <= Z12_int * QM1_2; |
Z13_temp <= Z13_int * QM1_3; Z14_temp <= Z14_int * QM1_4; |
Z15_temp <= Z15_int * QM1_5; Z16_temp <= Z16_int * QM1_6; |
Z17_temp <= Z17_int * QM1_7; Z18_temp <= Z18_int * QM1_8; |
Z21_temp <= Z21_int * QM2_1; Z22_temp <= Z22_int * QM2_2; |
Z23_temp <= Z23_int * QM2_3; Z24_temp <= Z24_int * QM2_4; |
Z25_temp <= Z25_int * QM2_5; Z26_temp <= Z26_int * QM2_6; |
Z27_temp <= Z27_int * QM2_7; Z28_temp <= Z28_int * QM2_8; |
Z31_temp <= Z31_int * QM3_1; Z32_temp <= Z32_int * QM3_2; |
Z33_temp <= Z33_int * QM3_3; Z34_temp <= Z34_int * QM3_4; |
Z35_temp <= Z35_int * QM3_5; Z36_temp <= Z36_int * QM3_6; |
Z37_temp <= Z37_int * QM3_7; Z38_temp <= Z38_int * QM3_8; |
Z41_temp <= Z41_int * QM4_1; Z42_temp <= Z42_int * QM4_2; |
Z43_temp <= Z43_int * QM4_3; Z44_temp <= Z44_int * QM4_4; |
Z45_temp <= Z45_int * QM4_5; Z46_temp <= Z46_int * QM4_6; |
Z47_temp <= Z47_int * QM4_7; Z48_temp <= Z48_int * QM4_8; |
Z51_temp <= Z51_int * QM5_1; Z52_temp <= Z52_int * QM5_2; |
Z53_temp <= Z53_int * QM5_3; Z54_temp <= Z54_int * QM5_4; |
Z55_temp <= Z55_int * QM5_5; Z56_temp <= Z56_int * QM5_6; |
Z57_temp <= Z57_int * QM5_7; Z58_temp <= Z58_int * QM5_8; |
Z61_temp <= Z61_int * QM6_1; Z62_temp <= Z62_int * QM6_2; |
Z63_temp <= Z63_int * QM6_3; Z64_temp <= Z64_int * QM6_4; |
Z65_temp <= Z65_int * QM6_5; Z66_temp <= Z66_int * QM6_6; |
Z67_temp <= Z67_int * QM6_7; Z68_temp <= Z68_int * QM6_8; |
Z71_temp <= Z71_int * QM7_1; Z72_temp <= Z72_int * QM7_2; |
Z73_temp <= Z73_int * QM7_3; Z74_temp <= Z74_int * QM7_4; |
Z75_temp <= Z75_int * QM7_5; Z76_temp <= Z76_int * QM7_6; |
Z77_temp <= Z77_int * QM7_7; Z78_temp <= Z78_int * QM7_8; |
Z81_temp <= Z81_int * QM8_1; Z82_temp <= Z82_int * QM8_2; |
Z83_temp <= Z83_int * QM8_3; Z84_temp <= Z84_int * QM8_4; |
Z85_temp <= Z85_int * QM8_5; Z86_temp <= Z86_int * QM8_6; |
Z87_temp <= Z87_int * QM8_7; Z88_temp <= Z88_int * QM8_8; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_temp_1 <= 0; Z12_temp_1 <= 0; Z13_temp_1 <= 0; Z14_temp_1 <= 0; |
Z12_temp_1 <= 0; Z16_temp_1 <= 0; Z17_temp_1 <= 0; Z18_temp_1 <= 0; |
Z21_temp_1 <= 0; Z22_temp_1 <= 0; Z23_temp_1 <= 0; Z24_temp_1 <= 0; |
Z22_temp_1 <= 0; Z26_temp_1 <= 0; Z27_temp_1 <= 0; Z28_temp_1 <= 0; |
Z31_temp_1 <= 0; Z32_temp_1 <= 0; Z33_temp_1 <= 0; Z34_temp_1 <= 0; |
Z32_temp_1 <= 0; Z36_temp_1 <= 0; Z37_temp_1 <= 0; Z38_temp_1 <= 0; |
Z41_temp_1 <= 0; Z42_temp_1 <= 0; Z43_temp_1 <= 0; Z44_temp_1 <= 0; |
Z42_temp_1 <= 0; Z46_temp_1 <= 0; Z47_temp_1 <= 0; Z48_temp_1 <= 0; |
Z51_temp_1 <= 0; Z52_temp_1 <= 0; Z53_temp_1 <= 0; Z54_temp_1 <= 0; |
Z52_temp_1 <= 0; Z56_temp_1 <= 0; Z57_temp_1 <= 0; Z58_temp_1 <= 0; |
Z61_temp_1 <= 0; Z62_temp_1 <= 0; Z63_temp_1 <= 0; Z64_temp_1 <= 0; |
Z62_temp_1 <= 0; Z66_temp_1 <= 0; Z67_temp_1 <= 0; Z68_temp_1 <= 0; |
Z71_temp_1 <= 0; Z72_temp_1 <= 0; Z73_temp_1 <= 0; Z74_temp_1 <= 0; |
Z72_temp_1 <= 0; Z76_temp_1 <= 0; Z77_temp_1 <= 0; Z78_temp_1 <= 0; |
Z81_temp_1 <= 0; Z82_temp_1 <= 0; Z83_temp_1 <= 0; Z84_temp_1 <= 0; |
Z82_temp_1 <= 0; Z86_temp_1 <= 0; Z87_temp_1 <= 0; Z88_temp_1 <= 0; |
end |
else if (enable_2) begin |
Z11_temp_1 <= Z11_temp; Z12_temp_1 <= Z12_temp; |
Z13_temp_1 <= Z13_temp; Z14_temp_1 <= Z14_temp; |
Z15_temp_1 <= Z15_temp; Z16_temp_1 <= Z16_temp; |
Z17_temp_1 <= Z17_temp; Z18_temp_1 <= Z18_temp; |
Z21_temp_1 <= Z21_temp; Z22_temp_1 <= Z22_temp; |
Z23_temp_1 <= Z23_temp; Z24_temp_1 <= Z24_temp; |
Z25_temp_1 <= Z25_temp; Z26_temp_1 <= Z26_temp; |
Z27_temp_1 <= Z27_temp; Z28_temp_1 <= Z28_temp; |
Z31_temp_1 <= Z31_temp; Z32_temp_1 <= Z32_temp; |
Z33_temp_1 <= Z33_temp; Z34_temp_1 <= Z34_temp; |
Z35_temp_1 <= Z35_temp; Z36_temp_1 <= Z36_temp; |
Z37_temp_1 <= Z37_temp; Z38_temp_1 <= Z38_temp; |
Z41_temp_1 <= Z41_temp; Z42_temp_1 <= Z42_temp; |
Z43_temp_1 <= Z43_temp; Z44_temp_1 <= Z44_temp; |
Z45_temp_1 <= Z45_temp; Z46_temp_1 <= Z46_temp; |
Z47_temp_1 <= Z47_temp; Z48_temp_1 <= Z48_temp; |
Z51_temp_1 <= Z51_temp; Z52_temp_1 <= Z52_temp; |
Z53_temp_1 <= Z53_temp; Z54_temp_1 <= Z54_temp; |
Z55_temp_1 <= Z55_temp; Z56_temp_1 <= Z56_temp; |
Z57_temp_1 <= Z57_temp; Z58_temp_1 <= Z58_temp; |
Z61_temp_1 <= Z61_temp; Z62_temp_1 <= Z62_temp; |
Z63_temp_1 <= Z63_temp; Z64_temp_1 <= Z64_temp; |
Z65_temp_1 <= Z65_temp; Z66_temp_1 <= Z66_temp; |
Z67_temp_1 <= Z67_temp; Z68_temp_1 <= Z68_temp; |
Z71_temp_1 <= Z71_temp; Z72_temp_1 <= Z72_temp; |
Z73_temp_1 <= Z73_temp; Z74_temp_1 <= Z74_temp; |
Z75_temp_1 <= Z75_temp; Z76_temp_1 <= Z76_temp; |
Z77_temp_1 <= Z77_temp; Z78_temp_1 <= Z78_temp; |
Z81_temp_1 <= Z81_temp; Z82_temp_1 <= Z82_temp; |
Z83_temp_1 <= Z83_temp; Z84_temp_1 <= Z84_temp; |
Z85_temp_1 <= Z85_temp; Z86_temp_1 <= Z86_temp; |
Z87_temp_1 <= Z87_temp; Z88_temp_1 <= Z88_temp; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Q11 <= 0; Q12 <= 0; Q13 <= 0; Q14 <= 0; Q15 <= 0; Q16 <= 0; Q17 <= 0; Q18 <= 0; |
Q21 <= 0; Q22 <= 0; Q23 <= 0; Q24 <= 0; Q25 <= 0; Q26 <= 0; Q27 <= 0; Q28 <= 0; |
Q31 <= 0; Q32 <= 0; Q33 <= 0; Q34 <= 0; Q35 <= 0; Q36 <= 0; Q37 <= 0; Q38 <= 0; |
Q41 <= 0; Q42 <= 0; Q43 <= 0; Q44 <= 0; Q45 <= 0; Q46 <= 0; Q47 <= 0; Q48 <= 0; |
Q51 <= 0; Q52 <= 0; Q53 <= 0; Q54 <= 0; Q55 <= 0; Q56 <= 0; Q57 <= 0; Q58 <= 0; |
Q61 <= 0; Q62 <= 0; Q63 <= 0; Q64 <= 0; Q65 <= 0; Q66 <= 0; Q67 <= 0; Q68 <= 0; |
Q71 <= 0; Q72 <= 0; Q73 <= 0; Q74 <= 0; Q75 <= 0; Q76 <= 0; Q77 <= 0; Q78 <= 0; |
Q81 <= 0; Q82 <= 0; Q83 <= 0; Q84 <= 0; Q85 <= 0; Q86 <= 0; Q87 <= 0; Q88 <= 0; |
end |
else if (enable_3) begin |
// rounding Q11 based on the bit in the 11th place of Z11_temp |
Q11 <= Z11_temp_1[11] ? Z11_temp_1[22:12] + 1 : Z11_temp_1[22:12]; |
Q12 <= Z12_temp_1[11] ? Z12_temp_1[22:12] + 1 : Z12_temp_1[22:12]; |
Q13 <= Z13_temp_1[11] ? Z13_temp_1[22:12] + 1 : Z13_temp_1[22:12]; |
Q14 <= Z14_temp_1[11] ? Z14_temp_1[22:12] + 1 : Z14_temp_1[22:12]; |
Q15 <= Z15_temp_1[11] ? Z15_temp_1[22:12] + 1 : Z15_temp_1[22:12]; |
Q16 <= Z16_temp_1[11] ? Z16_temp_1[22:12] + 1 : Z16_temp_1[22:12]; |
Q17 <= Z17_temp_1[11] ? Z17_temp_1[22:12] + 1 : Z17_temp_1[22:12]; |
Q18 <= Z18_temp_1[11] ? Z18_temp_1[22:12] + 1 : Z18_temp_1[22:12]; |
Q21 <= Z21_temp_1[11] ? Z21_temp_1[22:12] + 1 : Z21_temp_1[22:12]; |
Q22 <= Z22_temp_1[11] ? Z22_temp_1[22:12] + 1 : Z22_temp_1[22:12]; |
Q23 <= Z23_temp_1[11] ? Z23_temp_1[22:12] + 1 : Z23_temp_1[22:12]; |
Q24 <= Z24_temp_1[11] ? Z24_temp_1[22:12] + 1 : Z24_temp_1[22:12]; |
Q25 <= Z25_temp_1[11] ? Z25_temp_1[22:12] + 1 : Z25_temp_1[22:12]; |
Q26 <= Z26_temp_1[11] ? Z26_temp_1[22:12] + 1 : Z26_temp_1[22:12]; |
Q27 <= Z27_temp_1[11] ? Z27_temp_1[22:12] + 1 : Z27_temp_1[22:12]; |
Q28 <= Z28_temp_1[11] ? Z28_temp_1[22:12] + 1 : Z28_temp_1[22:12]; |
Q31 <= Z31_temp_1[11] ? Z31_temp_1[22:12] + 1 : Z31_temp_1[22:12]; |
Q32 <= Z32_temp_1[11] ? Z32_temp_1[22:12] + 1 : Z32_temp_1[22:12]; |
Q33 <= Z33_temp_1[11] ? Z33_temp_1[22:12] + 1 : Z33_temp_1[22:12]; |
Q34 <= Z34_temp_1[11] ? Z34_temp_1[22:12] + 1 : Z34_temp_1[22:12]; |
Q35 <= Z35_temp_1[11] ? Z35_temp_1[22:12] + 1 : Z35_temp_1[22:12]; |
Q36 <= Z36_temp_1[11] ? Z36_temp_1[22:12] + 1 : Z36_temp_1[22:12]; |
Q37 <= Z37_temp_1[11] ? Z37_temp_1[22:12] + 1 : Z37_temp_1[22:12]; |
Q38 <= Z38_temp_1[11] ? Z38_temp_1[22:12] + 1 : Z38_temp_1[22:12]; |
Q41 <= Z41_temp_1[11] ? Z41_temp_1[22:12] + 1 : Z41_temp_1[22:12]; |
Q42 <= Z42_temp_1[11] ? Z42_temp_1[22:12] + 1 : Z42_temp_1[22:12]; |
Q43 <= Z43_temp_1[11] ? Z43_temp_1[22:12] + 1 : Z43_temp_1[22:12]; |
Q44 <= Z44_temp_1[11] ? Z44_temp_1[22:12] + 1 : Z44_temp_1[22:12]; |
Q45 <= Z45_temp_1[11] ? Z45_temp_1[22:12] + 1 : Z45_temp_1[22:12]; |
Q46 <= Z46_temp_1[11] ? Z46_temp_1[22:12] + 1 : Z46_temp_1[22:12]; |
Q47 <= Z47_temp_1[11] ? Z47_temp_1[22:12] + 1 : Z47_temp_1[22:12]; |
Q48 <= Z48_temp_1[11] ? Z48_temp_1[22:12] + 1 : Z48_temp_1[22:12]; |
Q51 <= Z51_temp_1[11] ? Z51_temp_1[22:12] + 1 : Z51_temp_1[22:12]; |
Q52 <= Z52_temp_1[11] ? Z52_temp_1[22:12] + 1 : Z52_temp_1[22:12]; |
Q53 <= Z53_temp_1[11] ? Z53_temp_1[22:12] + 1 : Z53_temp_1[22:12]; |
Q54 <= Z54_temp_1[11] ? Z54_temp_1[22:12] + 1 : Z54_temp_1[22:12]; |
Q55 <= Z55_temp_1[11] ? Z55_temp_1[22:12] + 1 : Z55_temp_1[22:12]; |
Q56 <= Z56_temp_1[11] ? Z56_temp_1[22:12] + 1 : Z56_temp_1[22:12]; |
Q57 <= Z57_temp_1[11] ? Z57_temp_1[22:12] + 1 : Z57_temp_1[22:12]; |
Q58 <= Z58_temp_1[11] ? Z58_temp_1[22:12] + 1 : Z58_temp_1[22:12]; |
Q61 <= Z61_temp_1[11] ? Z61_temp_1[22:12] + 1 : Z61_temp_1[22:12]; |
Q62 <= Z62_temp_1[11] ? Z62_temp_1[22:12] + 1 : Z62_temp_1[22:12]; |
Q63 <= Z63_temp_1[11] ? Z63_temp_1[22:12] + 1 : Z63_temp_1[22:12]; |
Q64 <= Z64_temp_1[11] ? Z64_temp_1[22:12] + 1 : Z64_temp_1[22:12]; |
Q65 <= Z65_temp_1[11] ? Z65_temp_1[22:12] + 1 : Z65_temp_1[22:12]; |
Q66 <= Z66_temp_1[11] ? Z66_temp_1[22:12] + 1 : Z66_temp_1[22:12]; |
Q67 <= Z67_temp_1[11] ? Z67_temp_1[22:12] + 1 : Z67_temp_1[22:12]; |
Q68 <= Z68_temp_1[11] ? Z68_temp_1[22:12] + 1 : Z68_temp_1[22:12]; |
Q71 <= Z71_temp_1[11] ? Z71_temp_1[22:12] + 1 : Z71_temp_1[22:12]; |
Q72 <= Z72_temp_1[11] ? Z72_temp_1[22:12] + 1 : Z72_temp_1[22:12]; |
Q73 <= Z73_temp_1[11] ? Z73_temp_1[22:12] + 1 : Z73_temp_1[22:12]; |
Q74 <= Z74_temp_1[11] ? Z74_temp_1[22:12] + 1 : Z74_temp_1[22:12]; |
Q75 <= Z75_temp_1[11] ? Z75_temp_1[22:12] + 1 : Z75_temp_1[22:12]; |
Q76 <= Z76_temp_1[11] ? Z76_temp_1[22:12] + 1 : Z76_temp_1[22:12]; |
Q77 <= Z77_temp_1[11] ? Z77_temp_1[22:12] + 1 : Z77_temp_1[22:12]; |
Q78 <= Z78_temp_1[11] ? Z78_temp_1[22:12] + 1 : Z78_temp_1[22:12]; |
Q81 <= Z81_temp_1[11] ? Z81_temp_1[22:12] + 1 : Z81_temp_1[22:12]; |
Q82 <= Z82_temp_1[11] ? Z82_temp_1[22:12] + 1 : Z82_temp_1[22:12]; |
Q83 <= Z83_temp_1[11] ? Z83_temp_1[22:12] + 1 : Z83_temp_1[22:12]; |
Q84 <= Z84_temp_1[11] ? Z84_temp_1[22:12] + 1 : Z84_temp_1[22:12]; |
Q85 <= Z85_temp_1[11] ? Z85_temp_1[22:12] + 1 : Z85_temp_1[22:12]; |
Q86 <= Z86_temp_1[11] ? Z86_temp_1[22:12] + 1 : Z86_temp_1[22:12]; |
Q87 <= Z87_temp_1[11] ? Z87_temp_1[22:12] + 1 : Z87_temp_1[22:12]; |
Q88 <= Z88_temp_1[11] ? Z88_temp_1[22:12] + 1 : Z88_temp_1[22:12]; |
end |
end |
|
|
/* enable_1 is delayed one clock cycle from enable, and it's used to |
enable the logic that needs to execute on the clock cycle after enable goes high |
enable_2 is delayed two clock cycles, and out_enable signals the next module |
that its input data is ready*/ |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; |
out_enable <= 0; |
end |
else begin |
enable_1 <= enable; enable_2 <= enable_1; |
enable_3 <= enable_2; |
out_enable <= enable_3; |
end |
end |
|
endmodule |
/jpegencode/trunk/jpeg_top.v
0,0 → 1,73
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This is the top level module of the JPEG Encoder Core. |
This module takes the output from the fifo_out module and sends it |
to the ff_checker module to check for FF's in the bitstream. When it finds an |
FF, it puts a 00 after it, and then continues with the rest of the bitstream. |
At the end of the file, if there is not a full 32 bit set of JPEG data, then the |
signal "eof_data_partial_ready" will go high, to indicate there |
are less than 32 valid JPEG bits in the bitstream. The number of valid bits in the |
last JPEG_bitstream value is written to the signal "end_of_file_bitstream_count". |
*/ |
|
`timescale 1ns / 100ps |
|
module jpeg_top(clk, rst, end_of_file_signal, enable, data_in, JPEG_bitstream, |
data_ready, end_of_file_bitstream_count, eof_data_partial_ready); |
input clk; |
input rst; |
input end_of_file_signal; |
input enable; |
input [23:0] data_in; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output [4:0] end_of_file_bitstream_count; |
output eof_data_partial_ready; |
|
wire [31:0] JPEG_FF; |
wire data_ready_FF; |
wire [4:0] orc_reg_in; |
|
|
fifo_out u19 (.clk(clk), .rst(rst), .enable(enable), .data_in(data_in), |
.JPEG_bitstream(JPEG_FF), .data_ready(data_ready_FF), .orc_reg(orc_reg_in)); |
|
ff_checker u20 (.clk(clk), .rst(rst), |
.end_of_file_signal(end_of_file_signal), .JPEG_in(JPEG_FF), |
.data_ready_in(data_ready_FF), .orc_reg_in(orc_reg_in), |
.JPEG_bitstream_1(JPEG_bitstream), |
.data_ready_1(data_ready), .orc_reg(end_of_file_bitstream_count), |
.eof_data_partial_ready(eof_data_partial_ready)); |
|
endmodule |
/jpegencode/trunk/fifo_out.v
0,0 → 1,801
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module takes the y, cb, and cr inputs from the pre_fifo module, |
and it combines the bits into the jpeg_bitstream. It uses 3 FIFO's to |
write the y, cb, and cr data while it's processing the data. The output |
of this module goes to the input of the ff_checker module, to check for |
any FF's in the bitstream. |
*/ |
`timescale 1ns / 100ps |
|
module fifo_out(clk, rst, enable, data_in, JPEG_bitstream, data_ready, orc_reg); |
input clk, rst, enable; |
input [23:0] data_in; |
output [31:0] JPEG_bitstream; |
output data_ready; |
output [4:0] orc_reg; |
|
wire [31:0] cb_JPEG_bitstream, cr_JPEG_bitstream, y_JPEG_bitstream; |
wire [4:0] cr_orc, cb_orc, y_orc; |
wire [31:0] cr_bits_out, cb_bits_out, y_bits_out; |
wire cr_out_enable, cb_out_enable, y_out_enable; |
wire cb_data_ready, cr_data_ready, y_data_ready; |
wire end_of_block_output, y_eob_empty; |
wire cb_eob_empty, cr_eob_empty; |
wire cb_fifo_empty, cr_fifo_empty, y_fifo_empty; |
reg [4:0] orc, orc_reg, orc_cb, orc_cr, old_orc_reg, sorc_reg, roll_orc_reg; |
reg [4:0] orc_1, orc_2, orc_3, orc_4, orc_5, orc_reg_delay; |
reg [4:0] static_orc_1, static_orc_2, static_orc_3, static_orc_4, static_orc_5; |
reg [4:0] static_orc_6; |
reg [4:0] edge_ro_1, edge_ro_2, edge_ro_3, edge_ro_4, edge_ro_5; |
reg [31:0] jpeg_ro_1, jpeg_ro_2, jpeg_ro_3, jpeg_ro_4, jpeg_ro_5, jpeg_delay; |
reg [31:0] jpeg, jpeg_1, jpeg_2, jpeg_3, jpeg_4, jpeg_5, jpeg_6, JPEG_bitstream; |
reg [4:0] cr_orc_1, cb_orc_1, y_orc_1; |
reg cr_out_enable_1, cb_out_enable_1, y_out_enable_1, eob_1; |
reg eob_2, eob_3, eob_4; |
reg enable_1, enable_2, enable_3, enable_4, enable_5; |
reg enable_6, enable_7, enable_8, enable_9, enable_10; |
reg enable_11, enable_12, enable_13, enable_14, enable_15; |
reg enable_16, enable_17, enable_18, enable_19, enable_20; |
reg enable_21, enable_22, enable_23, enable_24, enable_25; |
reg enable_26, enable_27, enable_28, enable_29, enable_30; |
reg enable_31, enable_32, enable_33, enable_34, enable_35; |
reg [2:0] bits_mux, old_orc_mux, read_mux; |
reg bits_ready, br_1, br_2, br_3, br_4, br_5, br_6, br_7, br_8; |
reg rollover, rollover_1, rollover_2, rollover_3, rollover_eob; |
reg rollover_4, rollover_5, rollover_6, rollover_7; |
reg data_ready, eobe_1, cb_read_req, cr_read_req, y_read_req; |
reg eob_early_out_enable; |
wire cb_write_enable = cb_data_ready && !cb_eob_empty; |
wire cr_write_enable = cr_data_ready && !cr_eob_empty; |
wire y_write_enable = y_data_ready && !y_eob_empty; |
|
pre_fifo u14(.clk(clk), .rst(rst), .enable(enable), .data_in(data_in), |
.cr_JPEG_bitstream(cr_JPEG_bitstream), .cr_data_ready(cr_data_ready), |
.cr_orc(cr_orc), .cb_JPEG_bitstream(cb_JPEG_bitstream), |
.cb_data_ready(cb_data_ready), .cb_orc(cb_orc), |
.y_JPEG_bitstream(y_JPEG_bitstream), .y_data_ready(y_data_ready), .y_orc(y_orc), |
.y_eob_output(end_of_block_output), .y_eob_empty(y_eob_empty), |
.cb_eob_empty(cb_eob_empty), .cr_eob_empty(cr_eob_empty)); |
|
sync_fifo_32 u15(.clk(clk), .rst(rst), .read_req(cb_read_req), |
.write_data(cb_JPEG_bitstream), .write_enable(cb_write_enable), |
.read_data(cb_bits_out), |
.fifo_empty(cb_fifo_empty), .rdata_valid(cb_out_enable)); |
|
sync_fifo_32 u16(.clk(clk), .rst(rst), .read_req(cr_read_req), |
.write_data(cr_JPEG_bitstream), .write_enable(cr_write_enable), |
.read_data(cr_bits_out), |
.fifo_empty(cr_fifo_empty), .rdata_valid(cr_out_enable)); |
|
sync_fifo_32 u17(.clk(clk), .rst(rst), .read_req(y_read_req), |
.write_data(y_JPEG_bitstream), .write_enable(y_write_enable), |
.read_data(y_bits_out), |
.fifo_empty(y_fifo_empty), .rdata_valid(y_out_enable)); |
|
always @(posedge clk) |
begin |
if (y_fifo_empty || read_mux != 3'b001) |
y_read_req <= 0; |
else if (!y_fifo_empty && read_mux == 3'b001) |
y_read_req <= 1; |
end |
|
always @(posedge clk) |
begin |
if (cb_fifo_empty || read_mux != 3'b010) |
cb_read_req <= 0; |
else if (!cb_fifo_empty && read_mux == 3'b010) |
cb_read_req <= 1; |
end |
|
always @(posedge clk) |
begin |
if (cr_fifo_empty || read_mux != 3'b100) |
cr_read_req <= 0; |
else if (!cr_fifo_empty && read_mux == 3'b100) |
cr_read_req <= 1; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
br_1 <= 0; br_2 <= 0; br_3 <= 0; br_4 <= 0; br_5 <= 0; br_6 <= 0; |
br_7 <= 0; br_8 <= 0; |
static_orc_1 <= 0; static_orc_2 <= 0; static_orc_3 <= 0; |
static_orc_4 <= 0; static_orc_5 <= 0; static_orc_6 <= 0; |
data_ready <= 0; eobe_1 <= 0; |
end |
else begin |
br_1 <= bits_ready & !eobe_1; br_2 <= br_1; br_3 <= br_2; |
br_4 <= br_3; br_5 <= br_4; br_6 <= br_5; |
br_7 <= br_6; br_8 <= br_7; |
static_orc_1 <= sorc_reg; static_orc_2 <= static_orc_1; |
static_orc_3 <= static_orc_2; static_orc_4 <= static_orc_3; |
static_orc_5 <= static_orc_4; static_orc_6 <= static_orc_5; |
data_ready <= br_6 & rollover_5; |
eobe_1 <= y_eob_empty; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
rollover_eob <= 0; |
else if (br_3) |
rollover_eob <= old_orc_reg >= roll_orc_reg; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
rollover_1 <= 0; rollover_2 <= 0; rollover_3 <= 0; |
rollover_4 <= 0; rollover_5 <= 0; rollover_6 <= 0; |
rollover_7 <= 0; eob_1 <= 0; eob_2 <= 0; |
eob_3 <= 0; eob_4 <= 0; |
eob_early_out_enable <= 0; |
end |
else begin |
rollover_1 <= rollover; rollover_2 <= rollover_1; |
rollover_3 <= rollover_2; |
rollover_4 <= rollover_3 | rollover_eob; |
rollover_5 <= rollover_4; rollover_6 <= rollover_5; |
rollover_7 <= rollover_6; eob_1 <= end_of_block_output; |
eob_2 <= eob_1; eob_3 <= eob_2; eob_4 <= eob_3; |
eob_early_out_enable <= y_out_enable & y_out_enable_1 & eob_2; |
end |
end |
|
always @(posedge clk) |
begin |
case (bits_mux) |
3'b001: rollover <= y_out_enable_1 & !eob_4 & !eob_early_out_enable; |
3'b010: rollover <= cb_out_enable_1 & cb_out_enable; |
3'b100: rollover <= cr_out_enable_1 & cr_out_enable; |
default: rollover <= y_out_enable_1 & !eob_4; |
endcase |
end |
|
always @(posedge clk) |
begin |
if (rst) |
orc <= 0; |
else if (enable_20) |
orc <= orc_cr + cr_orc_1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
orc_cb <= 0; |
else if (eob_1) |
orc_cb <= orc + y_orc_1; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
orc_cr <= 0; |
else if (enable_5) |
orc_cr <= orc_cb + cb_orc_1; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
cr_out_enable_1 <= 0; cb_out_enable_1 <= 0; y_out_enable_1 <= 0; |
end |
else begin |
cr_out_enable_1 <= cr_out_enable; |
cb_out_enable_1 <= cb_out_enable; |
y_out_enable_1 <= y_out_enable; |
end |
end |
|
always @(posedge clk) |
begin |
case (bits_mux) |
3'b001: jpeg <= y_bits_out; |
3'b010: jpeg <= cb_bits_out; |
3'b100: jpeg <= cr_bits_out; |
default: jpeg <= y_bits_out; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (bits_mux) |
3'b001: bits_ready <= y_out_enable; |
3'b010: bits_ready <= cb_out_enable; |
3'b100: bits_ready <= cr_out_enable; |
default: bits_ready <= y_out_enable; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (bits_mux) |
3'b001: sorc_reg <= orc; |
3'b010: sorc_reg <= orc_cb; |
3'b100: sorc_reg <= orc_cr; |
default: sorc_reg <= orc; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (old_orc_mux) |
3'b001: roll_orc_reg <= orc; |
3'b010: roll_orc_reg <= orc_cb; |
3'b100: roll_orc_reg <= orc_cr; |
default: roll_orc_reg <= orc; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (bits_mux) |
3'b001: orc_reg <= orc; |
3'b010: orc_reg <= orc_cb; |
3'b100: orc_reg <= orc_cr; |
default: orc_reg <= orc; |
endcase |
end |
|
always @(posedge clk) |
begin |
case (old_orc_mux) |
3'b001: old_orc_reg <= orc_cr; |
3'b010: old_orc_reg <= orc; |
3'b100: old_orc_reg <= orc_cb; |
default: old_orc_reg <= orc_cr; |
endcase |
end |
|
always @(posedge clk) |
begin |
if (rst) |
bits_mux <= 3'b001; // Y |
else if (enable_3) |
bits_mux <= 3'b010; // Cb |
else if (enable_19) |
bits_mux <= 3'b100; // Cr |
else if (enable_35) |
bits_mux <= 3'b001; // Y |
end |
|
always @(posedge clk) |
begin |
if (rst) |
old_orc_mux <= 3'b001; // Y |
else if (enable_1) |
old_orc_mux <= 3'b010; // Cb |
else if (enable_6) |
old_orc_mux <= 3'b100; // Cr |
else if (enable_22) |
old_orc_mux <= 3'b001; // Y |
end |
|
always @(posedge clk) |
begin |
if (rst) |
read_mux <= 3'b001; // Y |
else if (enable_1) |
read_mux <= 3'b010; // Cb |
else if (enable_17) |
read_mux <= 3'b100; // Cr |
else if (enable_33) |
read_mux <= 3'b001; // Y |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
cr_orc_1 <= 0; cb_orc_1 <= 0; y_orc_1 <= 0; |
end |
else if (end_of_block_output) begin |
cr_orc_1 <= cr_orc; |
cb_orc_1 <= cb_orc; |
y_orc_1 <= y_orc; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
jpeg_ro_5 <= 0; edge_ro_5 <= 0; |
end |
else if (br_5) begin |
jpeg_ro_5 <= (edge_ro_4 <= 1) ? jpeg_ro_4 << 1 : jpeg_ro_4; |
edge_ro_5 <= (edge_ro_4 <= 1) ? edge_ro_4 : edge_ro_4 - 1; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
jpeg_5 <= 0; orc_5 <= 0; jpeg_ro_4 <= 0; edge_ro_4 <= 0; |
end |
else if (br_4) begin |
jpeg_5 <= (orc_4 >= 1) ? jpeg_4 >> 1 : jpeg_4; |
orc_5 <= (orc_4 >= 1) ? orc_4 - 1 : orc_4; |
jpeg_ro_4 <= (edge_ro_3 <= 2) ? jpeg_ro_3 << 2 : jpeg_ro_3; |
edge_ro_4 <= (edge_ro_3 <= 2) ? edge_ro_3 : edge_ro_3 - 2; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
jpeg_4 <= 0; orc_4 <= 0; jpeg_ro_3 <= 0; edge_ro_3 <= 0; |
end |
else if (br_3) begin |
jpeg_4 <= (orc_3 >= 2) ? jpeg_3 >> 2 : jpeg_3; |
orc_4 <= (orc_3 >= 2) ? orc_3 - 2 : orc_3; |
jpeg_ro_3 <= (edge_ro_2 <= 4) ? jpeg_ro_2 << 4 : jpeg_ro_2; |
edge_ro_3 <= (edge_ro_2 <= 4) ? edge_ro_2 : edge_ro_2 - 4; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
jpeg_3 <= 0; orc_3 <= 0; jpeg_ro_2 <= 0; edge_ro_2 <= 0; |
end |
else if (br_2) begin |
jpeg_3 <= (orc_2 >= 4) ? jpeg_2 >> 4 : jpeg_2; |
orc_3 <= (orc_2 >= 4) ? orc_2 - 4 : orc_2; |
jpeg_ro_2 <= (edge_ro_1 <= 8) ? jpeg_ro_1 << 8 : jpeg_ro_1; |
edge_ro_2 <= (edge_ro_1 <= 8) ? edge_ro_1 : edge_ro_1 - 8; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
jpeg_2 <= 0; orc_2 <= 0; jpeg_ro_1 <= 0; edge_ro_1 <= 0; |
end |
else if (br_1) begin |
jpeg_2 <= (orc_1 >= 8) ? jpeg_1 >> 8 : jpeg_1; |
orc_2 <= (orc_1 >= 8) ? orc_1 - 8 : orc_1; |
jpeg_ro_1 <= (orc_reg_delay <= 16) ? jpeg_delay << 16 : jpeg_delay; |
edge_ro_1 <= (orc_reg_delay <= 16) ? orc_reg_delay : orc_reg_delay - 16; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
jpeg_1 <= 0; orc_1 <= 0; jpeg_delay <= 0; orc_reg_delay <= 0; |
end |
else if (bits_ready) begin |
jpeg_1 <= (orc_reg >= 16) ? jpeg >> 16 : jpeg; |
orc_1 <= (orc_reg >= 16) ? orc_reg - 16 : orc_reg; |
jpeg_delay <= jpeg; |
orc_reg_delay <= orc_reg; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; enable_4 <= 0; enable_5 <= 0; |
enable_6 <= 0; enable_7 <= 0; enable_8 <= 0; enable_9 <= 0; enable_10 <= 0; |
enable_11 <= 0; enable_12 <= 0; enable_13 <= 0; enable_14 <= 0; enable_15 <= 0; |
enable_16 <= 0; enable_17 <= 0; enable_18 <= 0; enable_19 <= 0; enable_20 <= 0; |
enable_21 <= 0; enable_22 <= 0; enable_23 <= 0; enable_24 <= 0; enable_25 <= 0; |
enable_26 <= 0; enable_27 <= 0; enable_28 <= 0; enable_29 <= 0; enable_30 <= 0; |
enable_31 <= 0; enable_32 <= 0; enable_33 <= 0; enable_34 <= 0; enable_35 <= 0; |
end |
else begin |
enable_1 <= end_of_block_output; enable_2 <= enable_1; |
enable_3 <= enable_2; enable_4 <= enable_3; enable_5 <= enable_4; |
enable_6 <= enable_5; enable_7 <= enable_6; enable_8 <= enable_7; |
enable_9 <= enable_8; enable_10 <= enable_9; enable_11 <= enable_10; |
enable_12 <= enable_11; enable_13 <= enable_12; enable_14 <= enable_13; |
enable_15 <= enable_14; enable_16 <= enable_15; enable_17 <= enable_16; |
enable_18 <= enable_17; enable_19 <= enable_18; enable_20 <= enable_19; |
enable_21 <= enable_20; |
enable_22 <= enable_21; enable_23 <= enable_22; enable_24 <= enable_23; |
enable_25 <= enable_24; enable_26 <= enable_25; enable_27 <= enable_26; |
enable_28 <= enable_27; enable_29 <= enable_28; enable_30 <= enable_29; |
enable_31 <= enable_30; |
enable_32 <= enable_31; enable_33 <= enable_32; enable_34 <= enable_33; |
enable_35 <= enable_34; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[31] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[31] <= jpeg_6[31]; |
else if (br_6 && static_orc_6 == 0) |
JPEG_bitstream[31] <= jpeg_6[31]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[30] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[30] <= jpeg_6[30]; |
else if (br_6 && static_orc_6 <= 1) |
JPEG_bitstream[30] <= jpeg_6[30]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[29] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[29] <= jpeg_6[29]; |
else if (br_6 && static_orc_6 <= 2) |
JPEG_bitstream[29] <= jpeg_6[29]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[28] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[28] <= jpeg_6[28]; |
else if (br_6 && static_orc_6 <= 3) |
JPEG_bitstream[28] <= jpeg_6[28]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[27] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[27] <= jpeg_6[27]; |
else if (br_6 && static_orc_6 <= 4) |
JPEG_bitstream[27] <= jpeg_6[27]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[26] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[26] <= jpeg_6[26]; |
else if (br_6 && static_orc_6 <= 5) |
JPEG_bitstream[26] <= jpeg_6[26]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[25] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[25] <= jpeg_6[25]; |
else if (br_6 && static_orc_6 <= 6) |
JPEG_bitstream[25] <= jpeg_6[25]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[24] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[24] <= jpeg_6[24]; |
else if (br_6 && static_orc_6 <= 7) |
JPEG_bitstream[24] <= jpeg_6[24]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[23] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[23] <= jpeg_6[23]; |
else if (br_6 && static_orc_6 <= 8) |
JPEG_bitstream[23] <= jpeg_6[23]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[22] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[22] <= jpeg_6[22]; |
else if (br_6 && static_orc_6 <= 9) |
JPEG_bitstream[22] <= jpeg_6[22]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[21] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[21] <= jpeg_6[21]; |
else if (br_6 && static_orc_6 <= 10) |
JPEG_bitstream[21] <= jpeg_6[21]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[20] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[20] <= jpeg_6[20]; |
else if (br_6 && static_orc_6 <= 11) |
JPEG_bitstream[20] <= jpeg_6[20]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[19] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[19] <= jpeg_6[19]; |
else if (br_6 && static_orc_6 <= 12) |
JPEG_bitstream[19] <= jpeg_6[19]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[18] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[18] <= jpeg_6[18]; |
else if (br_6 && static_orc_6 <= 13) |
JPEG_bitstream[18] <= jpeg_6[18]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[17] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[17] <= jpeg_6[17]; |
else if (br_6 && static_orc_6 <= 14) |
JPEG_bitstream[17] <= jpeg_6[17]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[16] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[16] <= jpeg_6[16]; |
else if (br_6 && static_orc_6 <= 15) |
JPEG_bitstream[16] <= jpeg_6[16]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[15] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[15] <= jpeg_6[15]; |
else if (br_6 && static_orc_6 <= 16) |
JPEG_bitstream[15] <= jpeg_6[15]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[14] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[14] <= jpeg_6[14]; |
else if (br_6 && static_orc_6 <= 17) |
JPEG_bitstream[14] <= jpeg_6[14]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[13] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[13] <= jpeg_6[13]; |
else if (br_6 && static_orc_6 <= 18) |
JPEG_bitstream[13] <= jpeg_6[13]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[12] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[12] <= jpeg_6[12]; |
else if (br_6 && static_orc_6 <= 19) |
JPEG_bitstream[12] <= jpeg_6[12]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[11] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[11] <= jpeg_6[11]; |
else if (br_6 && static_orc_6 <= 20) |
JPEG_bitstream[11] <= jpeg_6[11]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[10] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[10] <= jpeg_6[10]; |
else if (br_6 && static_orc_6 <= 21) |
JPEG_bitstream[10] <= jpeg_6[10]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[9] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[9] <= jpeg_6[9]; |
else if (br_6 && static_orc_6 <= 22) |
JPEG_bitstream[9] <= jpeg_6[9]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[8] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[8] <= jpeg_6[8]; |
else if (br_6 && static_orc_6 <= 23) |
JPEG_bitstream[8] <= jpeg_6[8]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[7] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[7] <= jpeg_6[7]; |
else if (br_6 && static_orc_6 <= 24) |
JPEG_bitstream[7] <= jpeg_6[7]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[6] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[6] <= jpeg_6[6]; |
else if (br_6 && static_orc_6 <= 25) |
JPEG_bitstream[6] <= jpeg_6[6]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[5] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[5] <= jpeg_6[5]; |
else if (br_6 && static_orc_6 <= 26) |
JPEG_bitstream[5] <= jpeg_6[5]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[4] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[4] <= jpeg_6[4]; |
else if (br_6 && static_orc_6 <= 27) |
JPEG_bitstream[4] <= jpeg_6[4]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[3] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[3] <= jpeg_6[3]; |
else if (br_6 && static_orc_6 <= 28) |
JPEG_bitstream[3] <= jpeg_6[3]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[2] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[2] <= jpeg_6[2]; |
else if (br_6 && static_orc_6 <= 29) |
JPEG_bitstream[2] <= jpeg_6[2]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[1] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[1] <= jpeg_6[1]; |
else if (br_6 && static_orc_6 <= 30) |
JPEG_bitstream[1] <= jpeg_6[1]; |
end |
|
always @(posedge clk) |
begin |
if (rst) |
JPEG_bitstream[0] <= 0; |
else if (br_7 & rollover_6) |
JPEG_bitstream[0] <= jpeg_6[0]; |
else if (br_6 && static_orc_6 <= 31) |
JPEG_bitstream[0] <= jpeg_6[0]; |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
jpeg_6 <= 0; |
end |
else if (br_5 | br_6) begin |
jpeg_6[31] <= (rollover_5 & static_orc_5 > 0) ? jpeg_ro_5[31] : jpeg_5[31]; |
jpeg_6[30] <= (rollover_5 & static_orc_5 > 1) ? jpeg_ro_5[30] : jpeg_5[30]; |
jpeg_6[29] <= (rollover_5 & static_orc_5 > 2) ? jpeg_ro_5[29] : jpeg_5[29]; |
jpeg_6[28] <= (rollover_5 & static_orc_5 > 3) ? jpeg_ro_5[28] : jpeg_5[28]; |
jpeg_6[27] <= (rollover_5 & static_orc_5 > 4) ? jpeg_ro_5[27] : jpeg_5[27]; |
jpeg_6[26] <= (rollover_5 & static_orc_5 > 5) ? jpeg_ro_5[26] : jpeg_5[26]; |
jpeg_6[25] <= (rollover_5 & static_orc_5 > 6) ? jpeg_ro_5[25] : jpeg_5[25]; |
jpeg_6[24] <= (rollover_5 & static_orc_5 > 7) ? jpeg_ro_5[24] : jpeg_5[24]; |
jpeg_6[23] <= (rollover_5 & static_orc_5 > 8) ? jpeg_ro_5[23] : jpeg_5[23]; |
jpeg_6[22] <= (rollover_5 & static_orc_5 > 9) ? jpeg_ro_5[22] : jpeg_5[22]; |
jpeg_6[21] <= (rollover_5 & static_orc_5 > 10) ? jpeg_ro_5[21] : jpeg_5[21]; |
jpeg_6[20] <= (rollover_5 & static_orc_5 > 11) ? jpeg_ro_5[20] : jpeg_5[20]; |
jpeg_6[19] <= (rollover_5 & static_orc_5 > 12) ? jpeg_ro_5[19] : jpeg_5[19]; |
jpeg_6[18] <= (rollover_5 & static_orc_5 > 13) ? jpeg_ro_5[18] : jpeg_5[18]; |
jpeg_6[17] <= (rollover_5 & static_orc_5 > 14) ? jpeg_ro_5[17] : jpeg_5[17]; |
jpeg_6[16] <= (rollover_5 & static_orc_5 > 15) ? jpeg_ro_5[16] : jpeg_5[16]; |
jpeg_6[15] <= (rollover_5 & static_orc_5 > 16) ? jpeg_ro_5[15] : jpeg_5[15]; |
jpeg_6[14] <= (rollover_5 & static_orc_5 > 17) ? jpeg_ro_5[14] : jpeg_5[14]; |
jpeg_6[13] <= (rollover_5 & static_orc_5 > 18) ? jpeg_ro_5[13] : jpeg_5[13]; |
jpeg_6[12] <= (rollover_5 & static_orc_5 > 19) ? jpeg_ro_5[12] : jpeg_5[12]; |
jpeg_6[11] <= (rollover_5 & static_orc_5 > 20) ? jpeg_ro_5[11] : jpeg_5[11]; |
jpeg_6[10] <= (rollover_5 & static_orc_5 > 21) ? jpeg_ro_5[10] : jpeg_5[10]; |
jpeg_6[9] <= (rollover_5 & static_orc_5 > 22) ? jpeg_ro_5[9] : jpeg_5[9]; |
jpeg_6[8] <= (rollover_5 & static_orc_5 > 23) ? jpeg_ro_5[8] : jpeg_5[8]; |
jpeg_6[7] <= (rollover_5 & static_orc_5 > 24) ? jpeg_ro_5[7] : jpeg_5[7]; |
jpeg_6[6] <= (rollover_5 & static_orc_5 > 25) ? jpeg_ro_5[6] : jpeg_5[6]; |
jpeg_6[5] <= (rollover_5 & static_orc_5 > 26) ? jpeg_ro_5[5] : jpeg_5[5]; |
jpeg_6[4] <= (rollover_5 & static_orc_5 > 27) ? jpeg_ro_5[4] : jpeg_5[4]; |
jpeg_6[3] <= (rollover_5 & static_orc_5 > 28) ? jpeg_ro_5[3] : jpeg_5[3]; |
jpeg_6[2] <= (rollover_5 & static_orc_5 > 29) ? jpeg_ro_5[2] : jpeg_5[2]; |
jpeg_6[1] <= (rollover_5 & static_orc_5 > 30) ? jpeg_ro_5[1] : jpeg_5[1]; |
jpeg_6[0] <= jpeg_5[0]; |
end |
end |
|
endmodule |
/jpegencode/trunk/y_quantizer.v
0,0 → 1,629
///////////////////////////////////////////////////////////////////// |
//// //// |
//// JPEG Encoder Core - Verilog //// |
//// //// |
//// Author: David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 David Lundgren //// |
//// davidklun@gmail.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
/* This module comes after the dct module. The 64 matrix entries calculated after |
performing the 2D DCT are inputs to this quantization module. This module quantizes |
the entire 8x8 block of Y values. The outputs from this module |
are the quantized Y values for one 8x8 block. */ |
|
`timescale 1ns / 100ps |
|
module y_quantizer(clk, rst, enable, |
Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, |
Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, |
Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68, |
Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88, |
Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, |
Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, |
Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68, |
Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88, |
out_enable); |
input clk; |
input rst; |
input enable; |
input [10:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z21, Z22, Z23, Z24; |
input [10:0] Z25, Z26, Z27, Z28, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38; |
input [10:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z51, Z52, Z53, Z54; |
input [10:0] Z55, Z56, Z57, Z58, Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68; |
input [10:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78, Z81, Z82, Z83, Z84; |
input [10:0] Z85, Z86, Z87, Z88; |
output [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q21, Q22, Q23, Q24; |
output [10:0] Q25, Q26, Q27, Q28, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
output [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q51, Q52, Q53, Q54; |
output [10:0] Q55, Q56, Q57, Q58, Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
output [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78, Q81, Q82, Q83, Q84; |
output [10:0] Q85, Q86, Q87, Q88; |
output out_enable; |
|
/* Below are the quantization values, these can be changed for different |
quantization levels. */ |
|
parameter Q1_1 = 1; |
parameter Q1_2 = 1; |
parameter Q1_3 = 1; |
parameter Q1_4 = 1; |
parameter Q1_5 = 1; |
parameter Q1_6 = 1; |
parameter Q1_7 = 1; |
parameter Q1_8 = 1; |
parameter Q2_1 = 1; |
parameter Q2_2 = 1; |
parameter Q2_3 = 1; |
parameter Q2_4 = 1; |
parameter Q2_5 = 1; |
parameter Q2_6 = 1; |
parameter Q2_7 = 1; |
parameter Q2_8 = 1; |
parameter Q3_1 = 1; |
parameter Q3_2 = 1; |
parameter Q3_3 = 1; |
parameter Q3_4 = 1; |
parameter Q3_5 = 1; |
parameter Q3_6 = 1; |
parameter Q3_7 = 1; |
parameter Q3_8 = 1; |
parameter Q4_1 = 1; |
parameter Q4_2 = 1; |
parameter Q4_3 = 1; |
parameter Q4_4 = 1; |
parameter Q4_5 = 1; |
parameter Q4_6 = 1; |
parameter Q4_7 = 1; |
parameter Q4_8 = 1; |
parameter Q5_1 = 1; |
parameter Q5_2 = 1; |
parameter Q5_3 = 1; |
parameter Q5_4 = 1; |
parameter Q5_5 = 1; |
parameter Q5_6 = 1; |
parameter Q5_7 = 1; |
parameter Q5_8 = 1; |
parameter Q6_1 = 1; |
parameter Q6_2 = 1; |
parameter Q6_3 = 1; |
parameter Q6_4 = 1; |
parameter Q6_5 = 1; |
parameter Q6_6 = 1; |
parameter Q6_7 = 1; |
parameter Q6_8 = 1; |
parameter Q7_1 = 1; |
parameter Q7_2 = 1; |
parameter Q7_3 = 1; |
parameter Q7_4 = 1; |
parameter Q7_5 = 1; |
parameter Q7_6 = 1; |
parameter Q7_7 = 1; |
parameter Q7_8 = 1; |
parameter Q8_1 = 1; |
parameter Q8_2 = 1; |
parameter Q8_3 = 1; |
parameter Q8_4 = 1; |
parameter Q8_5 = 1; |
parameter Q8_6 = 1; |
parameter Q8_7 = 1; |
parameter Q8_8 = 1; |
// End of Quantization Values |
|
/* The following parameters hold the values of 4096 divided by the corresponding |
individual quantization values. These values are needed to get around |
actually dividing the Y, Cb, and Cr values by the quantization values. |
Instead, you can multiply by the values below, and then divide by 4096 |
to get the same result. And 4096 = 2^12, so instead of dividing, you can |
just shift the bottom 12 bits out. This is a lossy process, as 4096/Q divided |
by 4096 doesn't always equal the same value as if you were just dividing by Q. But |
the quantization process is also lossy, so the additional loss of precision is |
negligible. To decrease the loss, you could use a larger number than 4096 to |
get around the actual use of division. Like take 8192/Q and then divide by 8192.*/ |
|
parameter QQ1_1 = 4096/Q1_1; |
parameter QQ1_2 = 4096/Q1_2; |
parameter QQ1_3 = 4096/Q1_3; |
parameter QQ1_4 = 4096/Q1_4; |
parameter QQ1_5 = 4096/Q1_5; |
parameter QQ1_6 = 4096/Q1_6; |
parameter QQ1_7 = 4096/Q1_7; |
parameter QQ1_8 = 4096/Q1_8; |
parameter QQ2_1 = 4096/Q2_1; |
parameter QQ2_2 = 4096/Q2_2; |
parameter QQ2_3 = 4096/Q2_3; |
parameter QQ2_4 = 4096/Q2_4; |
parameter QQ2_5 = 4096/Q2_5; |
parameter QQ2_6 = 4096/Q2_6; |
parameter QQ2_7 = 4096/Q2_7; |
parameter QQ2_8 = 4096/Q2_8; |
parameter QQ3_1 = 4096/Q3_1; |
parameter QQ3_2 = 4096/Q3_2; |
parameter QQ3_3 = 4096/Q3_3; |
parameter QQ3_4 = 4096/Q3_4; |
parameter QQ3_5 = 4096/Q3_5; |
parameter QQ3_6 = 4096/Q3_6; |
parameter QQ3_7 = 4096/Q3_7; |
parameter QQ3_8 = 4096/Q3_8; |
parameter QQ4_1 = 4096/Q4_1; |
parameter QQ4_2 = 4096/Q4_2; |
parameter QQ4_3 = 4096/Q4_3; |
parameter QQ4_4 = 4096/Q4_4; |
parameter QQ4_5 = 4096/Q4_5; |
parameter QQ4_6 = 4096/Q4_6; |
parameter QQ4_7 = 4096/Q4_7; |
parameter QQ4_8 = 4096/Q4_8; |
parameter QQ5_1 = 4096/Q5_1; |
parameter QQ5_2 = 4096/Q5_2; |
parameter QQ5_3 = 4096/Q5_3; |
parameter QQ5_4 = 4096/Q5_4; |
parameter QQ5_5 = 4096/Q5_5; |
parameter QQ5_6 = 4096/Q5_6; |
parameter QQ5_7 = 4096/Q5_7; |
parameter QQ5_8 = 4096/Q5_8; |
parameter QQ6_1 = 4096/Q6_1; |
parameter QQ6_2 = 4096/Q6_2; |
parameter QQ6_3 = 4096/Q6_3; |
parameter QQ6_4 = 4096/Q6_4; |
parameter QQ6_5 = 4096/Q6_5; |
parameter QQ6_6 = 4096/Q6_6; |
parameter QQ6_7 = 4096/Q6_7; |
parameter QQ6_8 = 4096/Q6_8; |
parameter QQ7_1 = 4096/Q7_1; |
parameter QQ7_2 = 4096/Q7_2; |
parameter QQ7_3 = 4096/Q7_3; |
parameter QQ7_4 = 4096/Q7_4; |
parameter QQ7_5 = 4096/Q7_5; |
parameter QQ7_6 = 4096/Q7_6; |
parameter QQ7_7 = 4096/Q7_7; |
parameter QQ7_8 = 4096/Q7_8; |
parameter QQ8_1 = 4096/Q8_1; |
parameter QQ8_2 = 4096/Q8_2; |
parameter QQ8_3 = 4096/Q8_3; |
parameter QQ8_4 = 4096/Q8_4; |
parameter QQ8_5 = 4096/Q8_5; |
parameter QQ8_6 = 4096/Q8_6; |
parameter QQ8_7 = 4096/Q8_7; |
parameter QQ8_8 = 4096/Q8_8; |
|
wire [12:0] QM1_1 = QQ1_1; |
wire [12:0] QM1_2 = QQ1_2; |
wire [12:0] QM1_3 = QQ1_3; |
wire [12:0] QM1_4 = QQ1_4; |
wire [12:0] QM1_5 = QQ1_5; |
wire [12:0] QM1_6 = QQ1_6; |
wire [12:0] QM1_7 = QQ1_7; |
wire [12:0] QM1_8 = QQ1_8; |
wire [12:0] QM2_1 = QQ2_1; |
wire [12:0] QM2_2 = QQ2_2; |
wire [12:0] QM2_3 = QQ2_3; |
wire [12:0] QM2_4 = QQ2_4; |
wire [12:0] QM2_5 = QQ2_5; |
wire [12:0] QM2_6 = QQ2_6; |
wire [12:0] QM2_7 = QQ2_7; |
wire [12:0] QM2_8 = QQ2_8; |
wire [12:0] QM3_1 = QQ3_1; |
wire [12:0] QM3_2 = QQ3_2; |
wire [12:0] QM3_3 = QQ3_3; |
wire [12:0] QM3_4 = QQ3_4; |
wire [12:0] QM3_5 = QQ3_5; |
wire [12:0] QM3_6 = QQ3_6; |
wire [12:0] QM3_7 = QQ3_7; |
wire [12:0] QM3_8 = QQ3_8; |
wire [12:0] QM4_1 = QQ4_1; |
wire [12:0] QM4_2 = QQ4_2; |
wire [12:0] QM4_3 = QQ4_3; |
wire [12:0] QM4_4 = QQ4_4; |
wire [12:0] QM4_5 = QQ4_5; |
wire [12:0] QM4_6 = QQ4_6; |
wire [12:0] QM4_7 = QQ4_7; |
wire [12:0] QM4_8 = QQ4_8; |
wire [12:0] QM5_1 = QQ5_1; |
wire [12:0] QM5_2 = QQ5_2; |
wire [12:0] QM5_3 = QQ5_3; |
wire [12:0] QM5_4 = QQ5_4; |
wire [12:0] QM5_5 = QQ5_5; |
wire [12:0] QM5_6 = QQ5_6; |
wire [12:0] QM5_7 = QQ5_7; |
wire [12:0] QM5_8 = QQ5_8; |
wire [12:0] QM6_1 = QQ6_1; |
wire [12:0] QM6_2 = QQ6_2; |
wire [12:0] QM6_3 = QQ6_3; |
wire [12:0] QM6_4 = QQ6_4; |
wire [12:0] QM6_5 = QQ6_5; |
wire [12:0] QM6_6 = QQ6_6; |
wire [12:0] QM6_7 = QQ6_7; |
wire [12:0] QM6_8 = QQ6_8; |
wire [12:0] QM7_1 = QQ7_1; |
wire [12:0] QM7_2 = QQ7_2; |
wire [12:0] QM7_3 = QQ7_3; |
wire [12:0] QM7_4 = QQ7_4; |
wire [12:0] QM7_5 = QQ7_5; |
wire [12:0] QM7_6 = QQ7_6; |
wire [12:0] QM7_7 = QQ7_7; |
wire [12:0] QM7_8 = QQ7_8; |
wire [12:0] QM8_1 = QQ8_1; |
wire [12:0] QM8_2 = QQ8_2; |
wire [12:0] QM8_3 = QQ8_3; |
wire [12:0] QM8_4 = QQ8_4; |
wire [12:0] QM8_5 = QQ8_5; |
wire [12:0] QM8_6 = QQ8_6; |
wire [12:0] QM8_7 = QQ8_7; |
wire [12:0] QM8_8 = QQ8_8; |
reg [22:0] Z11_temp, Z12_temp, Z13_temp, Z14_temp, Z15_temp, Z16_temp, Z17_temp, Z18_temp; |
reg [22:0] Z21_temp, Z22_temp, Z23_temp, Z24_temp, Z25_temp, Z26_temp, Z27_temp, Z28_temp; |
reg [22:0] Z31_temp, Z32_temp, Z33_temp, Z34_temp, Z35_temp, Z36_temp, Z37_temp, Z38_temp; |
reg [22:0] Z41_temp, Z42_temp, Z43_temp, Z44_temp, Z45_temp, Z46_temp, Z47_temp, Z48_temp; |
reg [22:0] Z51_temp, Z52_temp, Z53_temp, Z54_temp, Z55_temp, Z56_temp, Z57_temp, Z58_temp; |
reg [22:0] Z61_temp, Z62_temp, Z63_temp, Z64_temp, Z65_temp, Z66_temp, Z67_temp, Z68_temp; |
reg [22:0] Z71_temp, Z72_temp, Z73_temp, Z74_temp, Z75_temp, Z76_temp, Z77_temp, Z78_temp; |
reg [22:0] Z81_temp, Z82_temp, Z83_temp, Z84_temp, Z85_temp, Z86_temp, Z87_temp, Z88_temp; |
reg [22:0] Z11_temp_1, Z12_temp_1, Z13_temp_1, Z14_temp_1, Z15_temp_1, Z16_temp_1, Z17_temp_1, Z18_temp_1; |
reg [22:0] Z21_temp_1, Z22_temp_1, Z23_temp_1, Z24_temp_1, Z25_temp_1, Z26_temp_1, Z27_temp_1, Z28_temp_1; |
reg [22:0] Z31_temp_1, Z32_temp_1, Z33_temp_1, Z34_temp_1, Z35_temp_1, Z36_temp_1, Z37_temp_1, Z38_temp_1; |
reg [22:0] Z41_temp_1, Z42_temp_1, Z43_temp_1, Z44_temp_1, Z45_temp_1, Z46_temp_1, Z47_temp_1, Z48_temp_1; |
reg [22:0] Z51_temp_1, Z52_temp_1, Z53_temp_1, Z54_temp_1, Z55_temp_1, Z56_temp_1, Z57_temp_1, Z58_temp_1; |
reg [22:0] Z61_temp_1, Z62_temp_1, Z63_temp_1, Z64_temp_1, Z65_temp_1, Z66_temp_1, Z67_temp_1, Z68_temp_1; |
reg [22:0] Z71_temp_1, Z72_temp_1, Z73_temp_1, Z74_temp_1, Z75_temp_1, Z76_temp_1, Z77_temp_1, Z78_temp_1; |
reg [22:0] Z81_temp_1, Z82_temp_1, Z83_temp_1, Z84_temp_1, Z85_temp_1, Z86_temp_1, Z87_temp_1, Z88_temp_1; |
reg [10:0] Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18; |
reg [10:0] Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28; |
reg [10:0] Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38; |
reg [10:0] Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48; |
reg [10:0] Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58; |
reg [10:0] Q61, Q62, Q63, Q64, Q65, Q66, Q67, Q68; |
reg [10:0] Q71, Q72, Q73, Q74, Q75, Q76, Q77, Q78; |
reg [10:0] Q81, Q82, Q83, Q84, Q85, Q86, Q87, Q88; |
reg out_enable, enable_1, enable_2, enable_3; |
integer Z11_int, Z12_int, Z13_int, Z14_int, Z15_int, Z16_int, Z17_int, Z18_int; |
integer Z21_int, Z22_int, Z23_int, Z24_int, Z25_int, Z26_int, Z27_int, Z28_int; |
integer Z31_int, Z32_int, Z33_int, Z34_int, Z35_int, Z36_int, Z37_int, Z38_int; |
integer Z41_int, Z42_int, Z43_int, Z44_int, Z45_int, Z46_int, Z47_int, Z48_int; |
integer Z51_int, Z52_int, Z53_int, Z54_int, Z55_int, Z56_int, Z57_int, Z58_int; |
integer Z61_int, Z62_int, Z63_int, Z64_int, Z65_int, Z66_int, Z67_int, Z68_int; |
integer Z71_int, Z72_int, Z73_int, Z74_int, Z75_int, Z76_int, Z77_int, Z78_int; |
integer Z81_int, Z82_int, Z83_int, Z84_int, Z85_int, Z86_int, Z87_int, Z88_int; |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_int <= 0; Z12_int <= 0; Z13_int <= 0; Z14_int <= 0; |
Z15_int <= 0; Z16_int <= 0; Z17_int <= 0; Z18_int <= 0; |
Z21_int <= 0; Z22_int <= 0; Z23_int <= 0; Z24_int <= 0; |
Z25_int <= 0; Z26_int <= 0; Z27_int <= 0; Z28_int <= 0; |
Z31_int <= 0; Z32_int <= 0; Z33_int <= 0; Z34_int <= 0; |
Z35_int <= 0; Z36_int <= 0; Z37_int <= 0; Z38_int <= 0; |
Z41_int <= 0; Z42_int <= 0; Z43_int <= 0; Z44_int <= 0; |
Z45_int <= 0; Z46_int <= 0; Z47_int <= 0; Z48_int <= 0; |
Z51_int <= 0; Z52_int <= 0; Z53_int <= 0; Z54_int <= 0; |
Z55_int <= 0; Z56_int <= 0; Z57_int <= 0; Z58_int <= 0; |
Z61_int <= 0; Z62_int <= 0; Z63_int <= 0; Z64_int <= 0; |
Z65_int <= 0; Z66_int <= 0; Z67_int <= 0; Z68_int <= 0; |
Z71_int <= 0; Z72_int <= 0; Z73_int <= 0; Z74_int <= 0; |
Z75_int <= 0; Z76_int <= 0; Z77_int <= 0; Z78_int <= 0; |
Z81_int <= 0; Z82_int <= 0; Z83_int <= 0; Z84_int <= 0; |
Z85_int <= 0; Z86_int <= 0; Z87_int <= 0; Z88_int <= 0; |
end |
else if (enable) begin |
Z11_int[10:0] <= Z11; Z12_int[10:0] <= Z12; Z13_int[10:0] <= Z13; Z14_int[10:0] <= Z14; |
Z15_int[10:0] <= Z15; Z16_int[10:0] <= Z16; Z17_int[10:0] <= Z17; Z18_int[10:0] <= Z18; |
Z21_int[10:0] <= Z21; Z22_int[10:0] <= Z22; Z23_int[10:0] <= Z23; Z24_int[10:0] <= Z24; |
Z25_int[10:0] <= Z25; Z26_int[10:0] <= Z26; Z27_int[10:0] <= Z27; Z28_int[10:0] <= Z28; |
Z31_int[10:0] <= Z31; Z32_int[10:0] <= Z32; Z33_int[10:0] <= Z33; Z34_int[10:0] <= Z34; |
Z35_int[10:0] <= Z35; Z36_int[10:0] <= Z36; Z37_int[10:0] <= Z37; Z38_int[10:0] <= Z38; |
Z41_int[10:0] <= Z41; Z42_int[10:0] <= Z42; Z43_int[10:0] <= Z43; Z44_int[10:0] <= Z44; |
Z45_int[10:0] <= Z45; Z46_int[10:0] <= Z46; Z47_int[10:0] <= Z47; Z48_int[10:0] <= Z48; |
Z51_int[10:0] <= Z51; Z52_int[10:0] <= Z52; Z53_int[10:0] <= Z53; Z54_int[10:0] <= Z54; |
Z55_int[10:0] <= Z55; Z56_int[10:0] <= Z56; Z57_int[10:0] <= Z57; Z58_int[10:0] <= Z58; |
Z61_int[10:0] <= Z61; Z62_int[10:0] <= Z62; Z63_int[10:0] <= Z63; Z64_int[10:0] <= Z64; |
Z65_int[10:0] <= Z65; Z66_int[10:0] <= Z66; Z67_int[10:0] <= Z67; Z68_int[10:0] <= Z68; |
Z71_int[10:0] <= Z71; Z72_int[10:0] <= Z72; Z73_int[10:0] <= Z73; Z74_int[10:0] <= Z74; |
Z75_int[10:0] <= Z75; Z76_int[10:0] <= Z76; Z77_int[10:0] <= Z77; Z78_int[10:0] <= Z78; |
Z81_int[10:0] <= Z81; Z82_int[10:0] <= Z82; Z83_int[10:0] <= Z83; Z84_int[10:0] <= Z84; |
Z85_int[10:0] <= Z85; Z86_int[10:0] <= Z86; Z87_int[10:0] <= Z87; Z88_int[10:0] <= Z88; |
// sign extend to make Z11_int a twos complement representation of Z11 |
Z11_int[31:11] <= Z11[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z12_int[31:11] <= Z12[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z13_int[31:11] <= Z13[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z14_int[31:11] <= Z14[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z15_int[31:11] <= Z15[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z16_int[31:11] <= Z16[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z17_int[31:11] <= Z17[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z18_int[31:11] <= Z18[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z21_int[31:11] <= Z21[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z22_int[31:11] <= Z22[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z23_int[31:11] <= Z23[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z24_int[31:11] <= Z24[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z25_int[31:11] <= Z25[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z26_int[31:11] <= Z26[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z27_int[31:11] <= Z27[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z28_int[31:11] <= Z28[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z31_int[31:11] <= Z31[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z32_int[31:11] <= Z32[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z33_int[31:11] <= Z33[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z34_int[31:11] <= Z34[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z35_int[31:11] <= Z35[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z36_int[31:11] <= Z36[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z37_int[31:11] <= Z37[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z38_int[31:11] <= Z38[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z41_int[31:11] <= Z41[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z42_int[31:11] <= Z42[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z43_int[31:11] <= Z43[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z44_int[31:11] <= Z44[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z45_int[31:11] <= Z45[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z46_int[31:11] <= Z46[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z47_int[31:11] <= Z47[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z48_int[31:11] <= Z48[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z51_int[31:11] <= Z51[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z52_int[31:11] <= Z52[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z53_int[31:11] <= Z53[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z54_int[31:11] <= Z54[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z55_int[31:11] <= Z55[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z56_int[31:11] <= Z56[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z57_int[31:11] <= Z57[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z58_int[31:11] <= Z58[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z61_int[31:11] <= Z61[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z62_int[31:11] <= Z62[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z63_int[31:11] <= Z63[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z64_int[31:11] <= Z64[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z65_int[31:11] <= Z65[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z66_int[31:11] <= Z66[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z67_int[31:11] <= Z67[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z68_int[31:11] <= Z68[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z71_int[31:11] <= Z71[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z72_int[31:11] <= Z72[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z73_int[31:11] <= Z73[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z74_int[31:11] <= Z74[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z75_int[31:11] <= Z75[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z76_int[31:11] <= Z76[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z77_int[31:11] <= Z77[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z78_int[31:11] <= Z78[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z81_int[31:11] <= Z81[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z82_int[31:11] <= Z82[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z83_int[31:11] <= Z83[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z84_int[31:11] <= Z84[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z85_int[31:11] <= Z85[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z86_int[31:11] <= Z86[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z87_int[31:11] <= Z87[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
Z88_int[31:11] <= Z88[10] ? 21'b111111111111111111111 : 21'b000000000000000000000; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_temp <= 0; Z12_temp <= 0; Z13_temp <= 0; Z14_temp <= 0; |
Z12_temp <= 0; Z16_temp <= 0; Z17_temp <= 0; Z18_temp <= 0; |
Z21_temp <= 0; Z22_temp <= 0; Z23_temp <= 0; Z24_temp <= 0; |
Z22_temp <= 0; Z26_temp <= 0; Z27_temp <= 0; Z28_temp <= 0; |
Z31_temp <= 0; Z32_temp <= 0; Z33_temp <= 0; Z34_temp <= 0; |
Z32_temp <= 0; Z36_temp <= 0; Z37_temp <= 0; Z38_temp <= 0; |
Z41_temp <= 0; Z42_temp <= 0; Z43_temp <= 0; Z44_temp <= 0; |
Z42_temp <= 0; Z46_temp <= 0; Z47_temp <= 0; Z48_temp <= 0; |
Z51_temp <= 0; Z52_temp <= 0; Z53_temp <= 0; Z54_temp <= 0; |
Z52_temp <= 0; Z56_temp <= 0; Z57_temp <= 0; Z58_temp <= 0; |
Z61_temp <= 0; Z62_temp <= 0; Z63_temp <= 0; Z64_temp <= 0; |
Z62_temp <= 0; Z66_temp <= 0; Z67_temp <= 0; Z68_temp <= 0; |
Z71_temp <= 0; Z72_temp <= 0; Z73_temp <= 0; Z74_temp <= 0; |
Z72_temp <= 0; Z76_temp <= 0; Z77_temp <= 0; Z78_temp <= 0; |
Z81_temp <= 0; Z82_temp <= 0; Z83_temp <= 0; Z84_temp <= 0; |
Z82_temp <= 0; Z86_temp <= 0; Z87_temp <= 0; Z88_temp <= 0; |
end |
else if (enable_1) begin |
Z11_temp <= Z11_int * QM1_1; Z12_temp <= Z12_int * QM1_2; |
Z13_temp <= Z13_int * QM1_3; Z14_temp <= Z14_int * QM1_4; |
Z15_temp <= Z15_int * QM1_5; Z16_temp <= Z16_int * QM1_6; |
Z17_temp <= Z17_int * QM1_7; Z18_temp <= Z18_int * QM1_8; |
Z21_temp <= Z21_int * QM2_1; Z22_temp <= Z22_int * QM2_2; |
Z23_temp <= Z23_int * QM2_3; Z24_temp <= Z24_int * QM2_4; |
Z25_temp <= Z25_int * QM2_5; Z26_temp <= Z26_int * QM2_6; |
Z27_temp <= Z27_int * QM2_7; Z28_temp <= Z28_int * QM2_8; |
Z31_temp <= Z31_int * QM3_1; Z32_temp <= Z32_int * QM3_2; |
Z33_temp <= Z33_int * QM3_3; Z34_temp <= Z34_int * QM3_4; |
Z35_temp <= Z35_int * QM3_5; Z36_temp <= Z36_int * QM3_6; |
Z37_temp <= Z37_int * QM3_7; Z38_temp <= Z38_int * QM3_8; |
Z41_temp <= Z41_int * QM4_1; Z42_temp <= Z42_int * QM4_2; |
Z43_temp <= Z43_int * QM4_3; Z44_temp <= Z44_int * QM4_4; |
Z45_temp <= Z45_int * QM4_5; Z46_temp <= Z46_int * QM4_6; |
Z47_temp <= Z47_int * QM4_7; Z48_temp <= Z48_int * QM4_8; |
Z51_temp <= Z51_int * QM5_1; Z52_temp <= Z52_int * QM5_2; |
Z53_temp <= Z53_int * QM5_3; Z54_temp <= Z54_int * QM5_4; |
Z55_temp <= Z55_int * QM5_5; Z56_temp <= Z56_int * QM5_6; |
Z57_temp <= Z57_int * QM5_7; Z58_temp <= Z58_int * QM5_8; |
Z61_temp <= Z61_int * QM6_1; Z62_temp <= Z62_int * QM6_2; |
Z63_temp <= Z63_int * QM6_3; Z64_temp <= Z64_int * QM6_4; |
Z65_temp <= Z65_int * QM6_5; Z66_temp <= Z66_int * QM6_6; |
Z67_temp <= Z67_int * QM6_7; Z68_temp <= Z68_int * QM6_8; |
Z71_temp <= Z71_int * QM7_1; Z72_temp <= Z72_int * QM7_2; |
Z73_temp <= Z73_int * QM7_3; Z74_temp <= Z74_int * QM7_4; |
Z75_temp <= Z75_int * QM7_5; Z76_temp <= Z76_int * QM7_6; |
Z77_temp <= Z77_int * QM7_7; Z78_temp <= Z78_int * QM7_8; |
Z81_temp <= Z81_int * QM8_1; Z82_temp <= Z82_int * QM8_2; |
Z83_temp <= Z83_int * QM8_3; Z84_temp <= Z84_int * QM8_4; |
Z85_temp <= Z85_int * QM8_5; Z86_temp <= Z86_int * QM8_6; |
Z87_temp <= Z87_int * QM8_7; Z88_temp <= Z88_int * QM8_8; |
end |
end |
|
|
always @(posedge clk) |
begin |
if (rst) begin |
Z11_temp_1 <= 0; Z12_temp_1 <= 0; Z13_temp_1 <= 0; Z14_temp_1 <= 0; |
Z12_temp_1 <= 0; Z16_temp_1 <= 0; Z17_temp_1 <= 0; Z18_temp_1 <= 0; |
Z21_temp_1 <= 0; Z22_temp_1 <= 0; Z23_temp_1 <= 0; Z24_temp_1 <= 0; |
Z22_temp_1 <= 0; Z26_temp_1 <= 0; Z27_temp_1 <= 0; Z28_temp_1 <= 0; |
Z31_temp_1 <= 0; Z32_temp_1 <= 0; Z33_temp_1 <= 0; Z34_temp_1 <= 0; |
Z32_temp_1 <= 0; Z36_temp_1 <= 0; Z37_temp_1 <= 0; Z38_temp_1 <= 0; |
Z41_temp_1 <= 0; Z42_temp_1 <= 0; Z43_temp_1 <= 0; Z44_temp_1 <= 0; |
Z42_temp_1 <= 0; Z46_temp_1 <= 0; Z47_temp_1 <= 0; Z48_temp_1 <= 0; |
Z51_temp_1 <= 0; Z52_temp_1 <= 0; Z53_temp_1 <= 0; Z54_temp_1 <= 0; |
Z52_temp_1 <= 0; Z56_temp_1 <= 0; Z57_temp_1 <= 0; Z58_temp_1 <= 0; |
Z61_temp_1 <= 0; Z62_temp_1 <= 0; Z63_temp_1 <= 0; Z64_temp_1 <= 0; |
Z62_temp_1 <= 0; Z66_temp_1 <= 0; Z67_temp_1 <= 0; Z68_temp_1 <= 0; |
Z71_temp_1 <= 0; Z72_temp_1 <= 0; Z73_temp_1 <= 0; Z74_temp_1 <= 0; |
Z72_temp_1 <= 0; Z76_temp_1 <= 0; Z77_temp_1 <= 0; Z78_temp_1 <= 0; |
Z81_temp_1 <= 0; Z82_temp_1 <= 0; Z83_temp_1 <= 0; Z84_temp_1 <= 0; |
Z82_temp_1 <= 0; Z86_temp_1 <= 0; Z87_temp_1 <= 0; Z88_temp_1 <= 0; |
end |
else if (enable_2) begin |
Z11_temp_1 <= Z11_temp; Z12_temp_1 <= Z12_temp; |
Z13_temp_1 <= Z13_temp; Z14_temp_1 <= Z14_temp; |
Z15_temp_1 <= Z15_temp; Z16_temp_1 <= Z16_temp; |
Z17_temp_1 <= Z17_temp; Z18_temp_1 <= Z18_temp; |
Z21_temp_1 <= Z21_temp; Z22_temp_1 <= Z22_temp; |
Z23_temp_1 <= Z23_temp; Z24_temp_1 <= Z24_temp; |
Z25_temp_1 <= Z25_temp; Z26_temp_1 <= Z26_temp; |
Z27_temp_1 <= Z27_temp; Z28_temp_1 <= Z28_temp; |
Z31_temp_1 <= Z31_temp; Z32_temp_1 <= Z32_temp; |
Z33_temp_1 <= Z33_temp; Z34_temp_1 <= Z34_temp; |
Z35_temp_1 <= Z35_temp; Z36_temp_1 <= Z36_temp; |
Z37_temp_1 <= Z37_temp; Z38_temp_1 <= Z38_temp; |
Z41_temp_1 <= Z41_temp; Z42_temp_1 <= Z42_temp; |
Z43_temp_1 <= Z43_temp; Z44_temp_1 <= Z44_temp; |
Z45_temp_1 <= Z45_temp; Z46_temp_1 <= Z46_temp; |
Z47_temp_1 <= Z47_temp; Z48_temp_1 <= Z48_temp; |
Z51_temp_1 <= Z51_temp; Z52_temp_1 <= Z52_temp; |
Z53_temp_1 <= Z53_temp; Z54_temp_1 <= Z54_temp; |
Z55_temp_1 <= Z55_temp; Z56_temp_1 <= Z56_temp; |
Z57_temp_1 <= Z57_temp; Z58_temp_1 <= Z58_temp; |
Z61_temp_1 <= Z61_temp; Z62_temp_1 <= Z62_temp; |
Z63_temp_1 <= Z63_temp; Z64_temp_1 <= Z64_temp; |
Z65_temp_1 <= Z65_temp; Z66_temp_1 <= Z66_temp; |
Z67_temp_1 <= Z67_temp; Z68_temp_1 <= Z68_temp; |
Z71_temp_1 <= Z71_temp; Z72_temp_1 <= Z72_temp; |
Z73_temp_1 <= Z73_temp; Z74_temp_1 <= Z74_temp; |
Z75_temp_1 <= Z75_temp; Z76_temp_1 <= Z76_temp; |
Z77_temp_1 <= Z77_temp; Z78_temp_1 <= Z78_temp; |
Z81_temp_1 <= Z81_temp; Z82_temp_1 <= Z82_temp; |
Z83_temp_1 <= Z83_temp; Z84_temp_1 <= Z84_temp; |
Z85_temp_1 <= Z85_temp; Z86_temp_1 <= Z86_temp; |
Z87_temp_1 <= Z87_temp; Z88_temp_1 <= Z88_temp; |
end |
end |
|
always @(posedge clk) |
begin |
if (rst) begin |
Q11 <= 0; Q12 <= 0; Q13 <= 0; Q14 <= 0; Q15 <= 0; Q16 <= 0; Q17 <= 0; Q18 <= 0; |
Q21 <= 0; Q22 <= 0; Q23 <= 0; Q24 <= 0; Q25 <= 0; Q26 <= 0; Q27 <= 0; Q28 <= 0; |
Q31 <= 0; Q32 <= 0; Q33 <= 0; Q34 <= 0; Q35 <= 0; Q36 <= 0; Q37 <= 0; Q38 <= 0; |
Q41 <= 0; Q42 <= 0; Q43 <= 0; Q44 <= 0; Q45 <= 0; Q46 <= 0; Q47 <= 0; Q48 <= 0; |
Q51 <= 0; Q52 <= 0; Q53 <= 0; Q54 <= 0; Q55 <= 0; Q56 <= 0; Q57 <= 0; Q58 <= 0; |
Q61 <= 0; Q62 <= 0; Q63 <= 0; Q64 <= 0; Q65 <= 0; Q66 <= 0; Q67 <= 0; Q68 <= 0; |
Q71 <= 0; Q72 <= 0; Q73 <= 0; Q74 <= 0; Q75 <= 0; Q76 <= 0; Q77 <= 0; Q78 <= 0; |
Q81 <= 0; Q82 <= 0; Q83 <= 0; Q84 <= 0; Q85 <= 0; Q86 <= 0; Q87 <= 0; Q88 <= 0; |
end |
else if (enable_3) begin |
// rounding Q11 based on the bit in the 11th place of Z11_temp |
Q11 <= Z11_temp_1[11] ? Z11_temp_1[22:12] + 1 : Z11_temp_1[22:12]; |
Q12 <= Z12_temp_1[11] ? Z12_temp_1[22:12] + 1 : Z12_temp_1[22:12]; |
Q13 <= Z13_temp_1[11] ? Z13_temp_1[22:12] + 1 : Z13_temp_1[22:12]; |
Q14 <= Z14_temp_1[11] ? Z14_temp_1[22:12] + 1 : Z14_temp_1[22:12]; |
Q15 <= Z15_temp_1[11] ? Z15_temp_1[22:12] + 1 : Z15_temp_1[22:12]; |
Q16 <= Z16_temp_1[11] ? Z16_temp_1[22:12] + 1 : Z16_temp_1[22:12]; |
Q17 <= Z17_temp_1[11] ? Z17_temp_1[22:12] + 1 : Z17_temp_1[22:12]; |
Q18 <= Z18_temp_1[11] ? Z18_temp_1[22:12] + 1 : Z18_temp_1[22:12]; |
Q21 <= Z21_temp_1[11] ? Z21_temp_1[22:12] + 1 : Z21_temp_1[22:12]; |
Q22 <= Z22_temp_1[11] ? Z22_temp_1[22:12] + 1 : Z22_temp_1[22:12]; |
Q23 <= Z23_temp_1[11] ? Z23_temp_1[22:12] + 1 : Z23_temp_1[22:12]; |
Q24 <= Z24_temp_1[11] ? Z24_temp_1[22:12] + 1 : Z24_temp_1[22:12]; |
Q25 <= Z25_temp_1[11] ? Z25_temp_1[22:12] + 1 : Z25_temp_1[22:12]; |
Q26 <= Z26_temp_1[11] ? Z26_temp_1[22:12] + 1 : Z26_temp_1[22:12]; |
Q27 <= Z27_temp_1[11] ? Z27_temp_1[22:12] + 1 : Z27_temp_1[22:12]; |
Q28 <= Z28_temp_1[11] ? Z28_temp_1[22:12] + 1 : Z28_temp_1[22:12]; |
Q31 <= Z31_temp_1[11] ? Z31_temp_1[22:12] + 1 : Z31_temp_1[22:12]; |
Q32 <= Z32_temp_1[11] ? Z32_temp_1[22:12] + 1 : Z32_temp_1[22:12]; |
Q33 <= Z33_temp_1[11] ? Z33_temp_1[22:12] + 1 : Z33_temp_1[22:12]; |
Q34 <= Z34_temp_1[11] ? Z34_temp_1[22:12] + 1 : Z34_temp_1[22:12]; |
Q35 <= Z35_temp_1[11] ? Z35_temp_1[22:12] + 1 : Z35_temp_1[22:12]; |
Q36 <= Z36_temp_1[11] ? Z36_temp_1[22:12] + 1 : Z36_temp_1[22:12]; |
Q37 <= Z37_temp_1[11] ? Z37_temp_1[22:12] + 1 : Z37_temp_1[22:12]; |
Q38 <= Z38_temp_1[11] ? Z38_temp_1[22:12] + 1 : Z38_temp_1[22:12]; |
Q41 <= Z41_temp_1[11] ? Z41_temp_1[22:12] + 1 : Z41_temp_1[22:12]; |
Q42 <= Z42_temp_1[11] ? Z42_temp_1[22:12] + 1 : Z42_temp_1[22:12]; |
Q43 <= Z43_temp_1[11] ? Z43_temp_1[22:12] + 1 : Z43_temp_1[22:12]; |
Q44 <= Z44_temp_1[11] ? Z44_temp_1[22:12] + 1 : Z44_temp_1[22:12]; |
Q45 <= Z45_temp_1[11] ? Z45_temp_1[22:12] + 1 : Z45_temp_1[22:12]; |
Q46 <= Z46_temp_1[11] ? Z46_temp_1[22:12] + 1 : Z46_temp_1[22:12]; |
Q47 <= Z47_temp_1[11] ? Z47_temp_1[22:12] + 1 : Z47_temp_1[22:12]; |
Q48 <= Z48_temp_1[11] ? Z48_temp_1[22:12] + 1 : Z48_temp_1[22:12]; |
Q51 <= Z51_temp_1[11] ? Z51_temp_1[22:12] + 1 : Z51_temp_1[22:12]; |
Q52 <= Z52_temp_1[11] ? Z52_temp_1[22:12] + 1 : Z52_temp_1[22:12]; |
Q53 <= Z53_temp_1[11] ? Z53_temp_1[22:12] + 1 : Z53_temp_1[22:12]; |
Q54 <= Z54_temp_1[11] ? Z54_temp_1[22:12] + 1 : Z54_temp_1[22:12]; |
Q55 <= Z55_temp_1[11] ? Z55_temp_1[22:12] + 1 : Z55_temp_1[22:12]; |
Q56 <= Z56_temp_1[11] ? Z56_temp_1[22:12] + 1 : Z56_temp_1[22:12]; |
Q57 <= Z57_temp_1[11] ? Z57_temp_1[22:12] + 1 : Z57_temp_1[22:12]; |
Q58 <= Z58_temp_1[11] ? Z58_temp_1[22:12] + 1 : Z58_temp_1[22:12]; |
Q61 <= Z61_temp_1[11] ? Z61_temp_1[22:12] + 1 : Z61_temp_1[22:12]; |
Q62 <= Z62_temp_1[11] ? Z62_temp_1[22:12] + 1 : Z62_temp_1[22:12]; |
Q63 <= Z63_temp_1[11] ? Z63_temp_1[22:12] + 1 : Z63_temp_1[22:12]; |
Q64 <= Z64_temp_1[11] ? Z64_temp_1[22:12] + 1 : Z64_temp_1[22:12]; |
Q65 <= Z65_temp_1[11] ? Z65_temp_1[22:12] + 1 : Z65_temp_1[22:12]; |
Q66 <= Z66_temp_1[11] ? Z66_temp_1[22:12] + 1 : Z66_temp_1[22:12]; |
Q67 <= Z67_temp_1[11] ? Z67_temp_1[22:12] + 1 : Z67_temp_1[22:12]; |
Q68 <= Z68_temp_1[11] ? Z68_temp_1[22:12] + 1 : Z68_temp_1[22:12]; |
Q71 <= Z71_temp_1[11] ? Z71_temp_1[22:12] + 1 : Z71_temp_1[22:12]; |
Q72 <= Z72_temp_1[11] ? Z72_temp_1[22:12] + 1 : Z72_temp_1[22:12]; |
Q73 <= Z73_temp_1[11] ? Z73_temp_1[22:12] + 1 : Z73_temp_1[22:12]; |
Q74 <= Z74_temp_1[11] ? Z74_temp_1[22:12] + 1 : Z74_temp_1[22:12]; |
Q75 <= Z75_temp_1[11] ? Z75_temp_1[22:12] + 1 : Z75_temp_1[22:12]; |
Q76 <= Z76_temp_1[11] ? Z76_temp_1[22:12] + 1 : Z76_temp_1[22:12]; |
Q77 <= Z77_temp_1[11] ? Z77_temp_1[22:12] + 1 : Z77_temp_1[22:12]; |
Q78 <= Z78_temp_1[11] ? Z78_temp_1[22:12] + 1 : Z78_temp_1[22:12]; |
Q81 <= Z81_temp_1[11] ? Z81_temp_1[22:12] + 1 : Z81_temp_1[22:12]; |
Q82 <= Z82_temp_1[11] ? Z82_temp_1[22:12] + 1 : Z82_temp_1[22:12]; |
Q83 <= Z83_temp_1[11] ? Z83_temp_1[22:12] + 1 : Z83_temp_1[22:12]; |
Q84 <= Z84_temp_1[11] ? Z84_temp_1[22:12] + 1 : Z84_temp_1[22:12]; |
Q85 <= Z85_temp_1[11] ? Z85_temp_1[22:12] + 1 : Z85_temp_1[22:12]; |
Q86 <= Z86_temp_1[11] ? Z86_temp_1[22:12] + 1 : Z86_temp_1[22:12]; |
Q87 <= Z87_temp_1[11] ? Z87_temp_1[22:12] + 1 : Z87_temp_1[22:12]; |
Q88 <= Z88_temp_1[11] ? Z88_temp_1[22:12] + 1 : Z88_temp_1[22:12]; |
end |
end |
|
|
/* enable_1 is delayed one clock cycle from enable, and it's used to |
enable the logic that needs to execute on the clock cycle after enable goes high |
enable_2 is delayed two clock cycles, and out_enable signals the next module |
that its input data is ready*/ |
|
always @(posedge clk) |
begin |
if (rst) begin |
enable_1 <= 0; enable_2 <= 0; enable_3 <= 0; |
out_enable <= 0; |
end |
else begin |
enable_1 <= enable; enable_2 <= enable_1; |
enable_3 <= enable_2; |
out_enable <= enable_3; |
end |
end |
|
endmodule |