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/trunk/ucode/light8080.m80
0,0 → 1,756
////////////////////////////////////////////////////////////////////////////////
// LIGHT8080 CORE MICROCODE (V.1 November 1st 2007)
////////////////////////////////////////////////////////////////////////////////
// NOTE: Except for bug fixing, there's no need to tinker with the microcode.
// Once the microcode table has been generated, this file is is not needed to
// synthesize or use the core.
////////////////////////////////////////////////////////////////////////////////
//
// ***** FORMAT AND OPERATION:
//
// operation 1 ; operation 2 ; flags
//
// Operation 1 sets up the ALU input registers; operation 2 takes the ALU result
// and writes it back somewhere; and the flags group all other microinstruction
// control signals.
//
// For any given instruction, operation 2 takes place in the cycle following
// operation 1. It happens concurrently with the next instruction's operation 1,
// so whenever a register is written to in an operation 2 it will NOT be
// available for the next instruction.
//
// In operation 1, you may load any one of T1 or T2 from the register bank or
// from DI which is simply the unregistered signal data_in.
//
// In operation 2, you specify the ALU operation and assign the ALU result to
// the register bank or the register DO, which feeds the signal data_out.
//
// You cannot address two different registers from the register bank in
// operations 1 and 2 (see the design notes on this).
//
// *** Some other elements found in the microcode source:
//
// labels: must be in a line by themselves, otherwise work like any assembler.
// __code pragmas: used by assembler to automatically generate the decode table.
// __asm pragmas: not used, but can be handy as a reference.
//
//
// ***** FLAGS:
//
// Note: '1st cycle' and '2nd cycle' denote both cycles of the present
// microinstruction (m.i.); cycle 2 of m.i. N overlaps cycle 1 of m.i. N+1.
//
// #ld_al : Load AL register with register bank output as read by operation 1.
// (used in memory and io access).
// #ld_addr : Load address register (H byte = register bank output as read by
// operation 1, L byte = AL).
// Activate vma signal for 1st cycle.
// #auxcy : Use aux carry instead of regular carry for this operation.
// #setacy : Set aux carry at the start of 1st cycle (used for ++).
// #end : Jump to microinstruction address 3 after the present m.i.
// #ret : Jump to address saved by the last JST or TJSR m.i.
// #rd : Activate rd signal for the 2nd cycle.
// #wr : Activate wr signal for the 2nd cycle.
// #fp_r : This instruction updates all PSW flags except for C.
// #fp_c : This instruction updates only the C flag in the PSW.
// #fp_rc : This instruction updates all the flags in the PSW.
// #clrt1 : Clear T1 at the end of 1st cycle.
// #io : Activate io signal for 1st cycle.
// #ei : Set interrupt enable register.
// #di : Reset interrupt enable register.
// #halt : Jump to microcode address 0x07 without saving return value.
//
////////////////////////////////////////////////////////////////////////////////
 
// RESET ucode: from 0 to 2, but uinst at address 0 is never executed
__reset
 
NOP ; NOP
NOP ; _pl = AND ; // T1 & T2 = 0x00
NOP ; _ph = AND ; // T1 & T2 = 0x00
 
// FETCH ucode: from 3 to 6
// (executed in INTA cycles too, with pc increment inhibited to preserve PC)
__fetch
 
T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy
T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy
NOP ; NOP ; #decode
 
// free uinst slot
NOP ; NOP ;
 
// HALT ucode: address 7
__halt
NOP ; NOP ; #halt, #end
 
 
// NOTE: ALU single_operand ops work on T1
// ALU 2-operands work with 'A' on T2 (e.g. SUB == T2 - T1)
 
 
__code "01dddsss"
__asm MOV {d},{s}
 
T1 = {s} ; NOP
NOP ; {d} = T1 ; #end
 
 
__code "01ddd110"
__asm MOV {d},M
 
JSR read_m ;
NOP ; {d} = T1 ; #end
 
 
__code "01110sss"
__asm MOV M,{s}
 
T1 = {s} ; DO = T1
JSR write_m // does not return
 
 
__code "00ddd110"
__asm MVI {d},#imm
 
JSR read_imm
NOP ; {d} = T1 ; #end
 
 
__code "00110110"
__asm MVI M,#imm
 
JSR read_imm
JSR write_m
 
 
__code "00pp0001"
__asm LXI [p]
 
JSR read_imm
NOP ; {p}1 = T1
JSR read_imm
NOP ; {p}0 = T1 ; #end
 
 
__code "00111010"
__asm LDA addr
 
JSR read_imm_wz
JSR read_wz
NOP ; _a = T1 ; #end
 
 
__code "00110010"
__asm STA addr
 
JSR read_imm_wz
T1 = _a ; DO = T1 ;
JSR write_wz //does not return
 
 
__code "00101010"
__asm LHLD
 
 
JSR read_imm_wz
T1 = _z ; _z = ADC ; #ld_al, #auxcy, #setacy // L = (WZ++)
T1 = _w ; _w = ADC ; #ld_addr, #rd, #auxcy
T1 = DI ; _l = T1
JSR read_wz // H = (WZ)
NOP ; _h = T1 ; #end
 
 
__code "00100010"
__asm SHLD
 
JSR read_imm_wz
T1 = _l ; DO = T1
T1 = _z ; _z = ADC ; #ld_al, #auxcy, #setacy
T1 = _w ; _w = ADC ; #ld_addr, #wr, #auxcy
T1 = _h ; DO = T1
JSR write_wz
 
 
__code "00pp1010"
__asm LDAX [p]
 
JSR read_p
NOP ; _a = T1 ; #end
 
 
__code "00pp0010"
__asm STAX [p]
 
T1 = _a ; DO = T1
JSR write_p
 
 
__code "11101011"
__asm XCHG
 
// 16 T cycles vs. 10 for the original 8080...
T1 = _d ; NOP
NOP ; _x = T1
T1 = _e ; NOP
NOP ; _y = T1
T1 = _h ; NOP
NOP ; _d = T1
T1 = _l ; NOP
NOP ; _e = T1
T1 = _x ; NOP
NOP ; _h = T1
T1 = _y ; NOP
NOP ; _l = T1 ; #end
 
 
__code "11000110"
__asm ADI #imm
 
JSR read_imm
T2 = _a ; _a = ADD ; #end, #fp_rc
 
__code "11001110"
__asm ACI #imm
 
JSR read_imm
T2 = _a ; _a = ADC ; #end, #fp_rc
 
__code "11010110"
__asm SUI #imm
 
JSR read_imm
T2 = _a ; _a = SUB ; #end, #fp_rc
 
__code "11011110"
__asm SBI #imm
 
JSR read_imm
T2 = _a ; _a = SBB ; #end, #fp_rc
 
 
__code "11100110"
__asm ANI #imm
 
JSR read_imm
T2 = _a ; _a = AND ; #end, #fp_rc
 
__code "11101110"
__asm XRI #imm
 
JSR read_imm
T2 = _a ; _a = XRL ; #end, #fp_rc
 
 
__code "11110110"
__asm ORI #imm
 
JSR read_imm
T2 = _a ; _a = ORL ; #end, #fp_rc
 
 
__code "11111110"
__asm CPI #imm
 
JSR read_imm
T2 = _a ; DO = SUB ; #end, #fp_rc
 
 
 
__code "10000sss"
__asm ADD {s}
 
T1 = {s} ; NOP
T2 = _a ; _a = ADD ; #end, #fp_rc
 
__code "10001sss"
__asm ADC {s}
 
T1 = {s} ; NOP
T2 = _a ; _a = ADC ; #end, #fp_rc
 
__code "10010sss"
__asm SUB {s}
 
T1 = {s} ; NOP
T2 = _a ; _a = SUB ; #end, #fp_rc
 
__code "10011sss"
__asm SBB {s}
 
T1 = {s} ; NOP
T2 = _a ; _a = SBB ; #end, #fp_rc
 
__code "10100sss"
__asm ANA {s}
 
T1 = {s} ; NOP
T2 = _a ; _a = AND ; #end, #fp_rc
 
__code "10101sss"
__asm XRA {s}
 
T1 = {s} ; NOP
T2 = _a ; _a = XRL ; #end, #fp_rc
 
__code "10110sss"
__asm ORA {s}
 
T1 = {s} ; NOP
T2 = _a ; _a = ORL ; #end, #fp_rc
 
__code "10111sss"
__asm CMP {s}
 
T1 = {s} ; NOP
T2 = _a ; DO = SUB ; #end, #fp_rc
 
 
__code "10000110"
__asm ADD M
 
JSR read_m
T2 = _a ; _a = ADD ; #end, #fp_rc
 
__code "10001110"
__asm ADC M
 
JSR read_m
T2 = _a ; _a = ADC ; #end, #fp_rc
 
__code "10010110"
__asm SUB M
 
JSR read_m
T2 = _a ; _a = SUB ; #end, #fp_rc
 
__code "10011110"
__asm SBB M
 
JSR read_m
T2 = _a ; _a = SBB ; #end, #fp_rc
 
__code "10100110"
__asm ANA M
 
JSR read_m
T2 = _a ; _a = AND ; #end, #fp_rc
 
__code "10101110"
__asm XRA M
 
JSR read_m
T2 = _a ; _a = XRL ; #end, #fp_rc
 
__code "10110110"
__asm ORA M
 
JSR read_m
T2 = _a ; _a = ORL ; #end, #fp_rc
 
 
__code "10111110"
__asm CMP M
 
JSR read_m
T2 = _a ; DO = SUB ; #end, #fp_rc
 
 
__code "00ddd100"
__asm INR {d}
 
T1 = {d} ; {d} = ADC ; #auxcy, #setacy, #fp_r
NOP ; NOP ; #end // extra line, flag clash
 
 
__code "00110100"
__asm INR M
 
JSR read_m
NOP ; DO = ADC ; #auxcy, #fp_r
JSR write_m
 
 
__code "00ddd101"
__asm DCR {d}
 
T2 = {d} ; {d} = SBB ; #auxcy, #setacy, #fp_r
NOP ; NOP ; #end // extra line, flag clash
 
 
__code "00110101"
__asm DCR M
 
JSR read_m // T1 = _x = (HL); but we need it in T2!
NOP ; NOP ; #clrt1 // flag clash
T2 = _x ; DO = SBB ; #auxcy, #setacy, #fp_r
JSR write_m
 
 
__code "00pp0011"
__asm INX [p]
 
T1 = {p}1 ; {p}1 = ADC ; #auxcy, #setacy
T1 = {p}0 ; {p}0 = ADC ; #end, #auxcy
 
 
__code "00pp1011"
__asm DCX [p]
 
T2 = {p}1 ; {p}1 = SBB ; #auxcy, #setacy // T2 because SUB -> T2 - T1
T2 = {p}0 ; {p}0 = SBB ; #end, #auxcy
 
 
__code "00pp1001"
__asm DAD [p]
 
T2 = {p}1 ; NOP
T1 = _l ; _l = ADD ; #fp_c // we need this cy
T2 = {p}0 ; NOP ;
T1 = _h ; _h = ADC ; #end, #fp_c
 
 
__code "00100111"
__asm DAA
 
// DAA result is only valid after the 2nd cycle;
T1 = _a ; DO = DAA ; //DO value ignored
T1 = _a ; _a = DAA ; #end, #fp_rc
 
 
__code "00000111"
__asm RLC
 
T1 = _a ; _a = rla ; #end, #fp_c
 
 
__code "00001111"
__asm RRC
 
T1 = _a ; _a = rra ; #end, #fp_c
 
 
__code "00010111"
__asm RAL
 
T1 = _a ; _a = rlca ; #end, #fp_c
 
 
__code "00011111"
__asm RAR
 
T1 = _a ; _a = rrca ; #end, #fp_c
 
 
__code "00101111"
__asm CMA
 
T1 = _a ; _a = NOT ; #end
 
 
__code "00111111"
__asm CMC
 
NOP ; cpc ; #end, #fp_c
 
 
__code "00110111"
__asm STC
 
NOP ; sec ; #end, #fp_c
 
 
__code "11000011"
__asm JMP addr
 
JSR read_imm_wz
:jmp_addr
T1 = _z ; NOP
NOP ; _pl = T1
T1 = _w ; NOP
NOP ; _ph = T1 ; #end
 
 
 
__code "00000000"
__asm NOP
 
NOP ; NOP ; #end
 
 
__code "11ccc010"
__asm {JZ,JNZ,JC,JNC,JPO,JPE,JP,JM} addr
 
JSR read_imm_wz
TJSR jmp_addr // TJSR does the JSR or does #end the instruction.
 
 
__code "11001101"
__asm CALL addr
 
//:call_addr
JSR read_imm_wz
:call_addr //@@
T1 = _ph ; DO = T1 ; #clrt1
JSR push
T1 = _pl ; DO = T1 ; #clrt1
JSR push
T1 = _z ; NOP
NOP ; _pl = T1
T1 = _w ; NOP
NOP ; _ph = T1 ; #end
 
 
 
__code "11ccc100"
__asm {CZ,CNZ,CC,CNC,CPO,CPE,CP,CM} addr
 
JSR read_imm_wz // skip next 2 bytes
TJSR call_addr // TJSR does the JSR or does #end the instruction.
 
 
__code "11001001"
__asm RET
 
:ret
JSR pop
NOP ; _pl = T1
JSR pop
NOP ; _ph = T1 ; #end
 
 
__code "11ccc000"
__asm {RZ,RNZ,RC,RNC,RPO,RPE,RP,RM}
 
 
TJSR ret // TJSR does the JSR or does #end the instruction.
 
 
 
__code "11nnn111"
__asm {RST 0h,RST 8h,RST 10h,RST 18h,RST 20h,RST 28h,RST 30h,RST 38h}
 
T1 = _ph ; DO = T1 ; #clrt1
JSR push
T1 = _pl ; DO = T1 ; #clrt1
JSR push
NOP ; _pl = rst ; #clrt1
NOP ; _ph = AND ; #end // T1 & T2 = 0, because T2=0
// No extra cycle needed, _ph is not used in the next instruction
 
__code "11101001"
__asm PCHL
 
T1 = _l ; NOP
NOP ; _pl = T1
T1 = _h ; NOP
NOP ; _ph = T1 ; #end
 
 
__code "11pp0101" //Except for PUSH PSW
__asm PUSH [p]
 
T1 = {p}0 ; DO = T1 ; #clrt1 // H first...
JSR push
T1 = {p}1 ; DO = T1 ; #clrt1 // ...L last
JSR push
NOP ; NOP ; #end
 
 
__code "11110101"
__asm PUSH PSW
 
T1 = _a ; DO = T1 ; #clrt1
JSR push
NOP ; DO = PSW ; #clrt1
JSR push
NOP ; NOP ; #end
 
 
__code "11pp0001" //Except for POP PSW
__asm POP [p]
 
JSR pop
NOP ; {p}1 = T1
JSR pop
NOP ; {p}0 = T1 ; #end
 
 
__code "11110001"
__asm POP PSW
 
JSR pop
NOP ; _f = T1 ; #fp_rc //F<-(SP); F f-fs load automatically
JSR pop
NOP ; _a = T1 ; #end
 
 
__code "11100011"
__asm XTHL
 
JSR pop
NOP ; _z = T1
JSR pop
NOP ; _w = T1
T1 = _h ; DO = T1 ; #clrt1
JSR push
T1 = _l ; DO = T1 ; #clrt1
JSR push
T1 = _z ; NOP
NOP ; _l = T1
T1 = _w ; NOP
NOP ; _h = T1 ; #end
 
 
__code "11111001"
__asm SPHL
 
T1 = _l ; NOP
NOP ; _sl = T1
T1 = _h ; NOP
NOP ; _sh = T1 ; #end
 
 
__code "11111011"
__asm EI
 
NOP ; NOP ; #ei, #end
 
 
__code "11110011"
__asm DI
 
NOP ; NOP ; #di, #end
 
 
__code "11011011"
__asm IN port
 
NOP ; _w = T1 // _w = 0
JSR read_imm // T1 = port
NOP ; _z = T1 // #ld_al reads from mux...
NOP ; NOP
T1 = _z ; NOP ; #ld_al
T1 = _w ; NOP ; #ld_addr, #rd, #io
T1 = DI ; _a = T1 ; #end
 
 
// Can be reduced to 11 states by removing 1st uinst
// Then, _b might be put on high addr byte as in the original...
__code "11010011"
__asm OUT port
 
 
NOP ; _w = T1 // _w = 0, put on high byte of io address
JSR read_imm // T1 = port
NOP ; _z = T1 // #ld_al reads from mux...
T1 = _a ; DO = T1
T1 = _z ; NOP ; #ld_al
T1 = _w ; NOP ; #ld_addr, #wr, #io
NOP ; NOP ; #end
 
 
__code "01110110"
__asm HLT
//TODO doc: #halt has to be in the same cycle as #end
NOP ; NOP ; #halt, #end
 
 
 
 
//********************************************
 
// T1 = (HL)
 
:read_m
 
T1 = _l ; NOP ; #ld_al
T1 = _h ; NOP ; #ld_addr, #rd
T1 = DI ; _x = T1 ; #ret
 
// (HL) = DO, does not return
// TODO extra uinst is for wait state, which is not implemented
 
:write_m
 
T1 = _l ; NOP ; #ld_al
T1 = _h ; NOP ; #ld_addr, #wr
NOP ; NOP ; #end
 
 
// T1 = (PC++), DO = T1
// T2 must be 0 on entry
:read_imm
 
T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy
T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy
T1 = DI ; DO = T1 ; #ret
 
 
// T1 = (WZ)
 
:read_wz
 
T1 = _z ; NOP ; #ld_al
T1 = _w ; NOP ; #ld_addr, #rd
T1 = DI ; NOP ; #ret
 
 
// (WZ) = DO, does not return
// TODO extra uinst is for wait state, which is not implemented
 
:write_wz
 
T1 = _z ; NOP ; #ld_al
T1 = _w ; NOP ; #ld_addr, #wr
NOP ; NOP ; #end
 
// T1 = (RP)
 
:read_p
 
T1 = {p}1 ; NOP ; #ld_al
T1 = {p}0 ; NOP ; #ld_addr, #rd
T1 = DI ; NOP ; #ret
 
 
// (RP) = DO, does not return
// TODO extra uinst is for wait state, which is not implemented
 
:write_p
 
T1 = {p}1 ; NOP ; #ld_al
T1 = {p}0 ; NOP ; #ld_addr, #wr
NOP ; NOP ; #end
 
// WZ = imm16
 
:read_imm_wz
 
T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy
T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy
T1 = DI ; _z = T1
T1 = _pl ; _pl = ADC ; #ld_al, #auxcy, #setacy
T1 = _ph ; _ph = ADC ; #ld_addr, #rd, #auxcy
T1 = DI ; _w = T1 ; #ret
 
// push DO
// no wait cycle!
 
:push
T2 = _sl ; _sl = SBB ; #auxcy, #setacy
T2 = _sh ; _sh = SBB ; #auxcy
T1 = _sl ; NOP ; #ld_al
T1 = _sh ; NOP ; #ld_addr, #wr,
NOP ; NOP ; #ret // extra line, flag clash
 
 
// POP T1
 
:pop
T1 = _sl ; _sl = ADC ; #ld_al, #auxcy, #setacy
T1 = _sh ; _sh = ADC ; #ld_addr, #rd, #auxcy
T1 = DI ; NOP ; #ret // extra line, flag clash
 
 
// End of file
/trunk/asm/TB0.PRN
0,0 → 1,824
 
 
;***********************************************************************
; MICROCOSM ASSOCIATES 8080/8085 CPU DIAGNOSTIC VERSION 1.0 (C) 1980
;***********************************************************************
;
;DONATED TO THE "SIG/M" CP/M USER'S GROUP BY:
;KELLY SMITH, MICROCOSM ASSOCIATES
;3055 WACO AVENUE
;SIMI VALLEY, CALIFORNIA, 93065
;(805) 527-9321 (MODEM, CP/M-NET (TM))
;(805) 527-0518 (VERBAL)
;
;***********************************************************************
; Modified 2001/02/28 by Richard Cini for use in the Altair32 Emulator
; Project
;
; Need to somehow connect this code to Windows so that failure messages
; can be posted to Windows. Maybe just store error code in
; Mem[0xffff]. Maybe trap NOP in the emulator code?
;
;***********************************************************************
; Modified 2006/11/16 by Scott Moore to work on CPU8080 FPGA core
;
;***********************************************************************
; Modified 2007/09/24 by Jose Ruiz for use in free8080 FPGA core
;
; 1.- Changed formatting for compatibility to CP/M's ASM
; 2.- Commented out all Altair / MITS hardware related stuff
; 3.- Set origin at 0H
;
;***********************************************************************
;
; Select controller defines
;
;selmain: equ 00H ; offset of main control register
;sel1msk: equ 02H ; offset of select 1 mask
;sel1cmp: equ 03H ; offset of select 1 compare
;sel2msk: equ 04H ; offset of select 1 mask
;sel2cmp: equ 05H ; offset of select 1 compare
;sel3msk: equ 06H ; offset of select 1 mask
;sel3cmp: equ 07H ; offset of select 1 compare
;sel4msk: equ 08H ; offset of select 1 mask
;sel4cmp: equ 09H ; offset of select 1 compare
;
; bits
;
;selenb: equ 01H ; enable select
;selio: equ 02H ; I/O address or memory
;
; Note: select 1 is ROM, 2, is RAM, 3 is interrupt controller, 4 is serial I/O.
;
;
; Where to place ROM and RAM for this test
;
;rombas: equ 0000H
;rambas: equ rombas+4*1024
;
; Interrupt controller defines
;
;intbas: equ 10H
;intmsk: equ intbas+00H ; mask
;intsts: equ intbas+01H ; status
;intact: equ intbas+02H ; active interrupt
;intpol: equ intbas+03H ; polarity select
;intedg: equ intbas+04H ; edge/level select
;intvec: equ intbas+05H ; vector base page
;
; Mits Serial I/O card
;
;siobas: equ 20H
;sioctl: equ siobas+00H ; control register
;siodat: equ siobas+01H ; data
;
; Set up selectors
;
;
; ROM
;
; mvi a,rombas shr 8 ; enable select 1 to 4kb at base
; out sel1cmp
; mvi a,(0f000H shr 8) or selenb
; out sel1msk
;
; RAM
;
; mvi a,rambas shr 8 ; enable select 2 to 1kb at base
; out sel2cmp
; mvi a,(0fc00H shr 8) or selenb
; out sel2msk
;
; ROM and RAM set up, exit bootstrap mode
;
; mvi a,00H ; exit bootstrap mode
; out selmain
;
; Serial I/O
;
; mvi a,siobas ; enable serial controller for 4 addresses
; out sel4cmp
; mvi a,0fcH or selio or selenb
; out sel4msk
;************************************************************
; 8080/8085 CPU TEST/DIAGNOSTIC
;************************************************************
;
;note: (1) program assumes "call",and "lxi sp" instructions work;
;
; (2) instructions not tested are "hlt","di","ei",
; and "rst 0" thru "rst 7"
;
;
;
;test jump instructions and flags
;
0000 org 0H
0000 31EF05 cpu: lxi sp,stack ;set the stack pointer
0003 3E77 mvi a,077H ;@ initialize A to remove X values from simulation
0005 E600 ani 0 ;initialize a reg. and clear all flags
0007 CA0D00 jz j010 ;test "jz"
000A CDE004 call cpuer
000D D21300 j010: jnc j020 ;test "jnc"
0010 CDE004 call cpuer
0013 EA1900 j020: jpe j030 ;test "jpe"
0016 CDE004 call cpuer
0019 F21F00 j030: jp j040 ;test "jp"
001C CDE004 call cpuer
001F C22E00 j040: jnz j050 ;test "jnz"
0022 DA2E00 jc j050 ;test "jc"
0025 E22E00 jpo j050 ;test "jpo"
0028 FA2E00 jm j050 ;test "jm"
002B C33100 jmp j060 ;test "jmp" (it's a little late,but what the hell;
002E CDE004 j050: call cpuer
0031 C606 j060: adi 6 ;a=6,c=0,p=1,s=0,z=0
0033 C23900 jnz j070 ;test "jnz"
0036 CDE004 call cpuer
0039 DA4200 j070: jc j080 ;test "jc"
003C E24200 jpo j080 ;test "jpo"
003F F24500 jp j090 ;test "jp"
0042 CDE004 j080: call cpuer
0045 C670 j090: adi 70H ;a=76h,c=0,p=0,s=0,z=0
0047 E24D00 jpo j100 ;test "jpo"
004A CDE004 call cpuer
004D FA5600 j100: jm j110 ;test "jm"
0050 CA5600 jz j110 ;test "jz"
0053 D25900 jnc j120 ;test "jnc"
0056 CDE004 j110: call cpuer
0059 C681 j120: adi 81H ;a=f7h,c=0,p=0,s=1,z=0
005B FA6100 jm j130 ;test "jm"
005E CDE004 call cpuer
0061 CA6A00 j130: jz j140 ;test "jz"
0064 DA6A00 jc j140 ;test "jc"
0067 E26D00 jpo j150 ;test "jpo"
006A CDE004 j140: call cpuer
006D C6FE j150: adi 0feH ;a=f5h,c=1,p=1,s=1,z=0
006F DA7500 jc j160 ;test "jc"
0072 CDE004 call cpuer
0075 CA7E00 j160: jz j170 ;test "jz"
0078 E27E00 jpo j170 ;test "jpo"
007B FA8100 jm aimm ;test "jm"
007E CDE004 j170: call cpuer
;
;
;
;test accumulator immediate instructions
;
0081 FE00 aimm: cpi 0 ;a=f5h,c=0,z=0
0083 DA9900 jc cpie ;test "cpi" for re-set carry
0086 CA9900 jz cpie ;test "cpi" for re-set zero
0089 FEF5 cpi 0f5H ;a=f5h,c=0,z=1
008B DA9900 jc cpie ;test "cpi" for re-set carry ("adi")
008E C29900 jnz cpie ;test "cpi" for re-set zero
0091 FEFF cpi 0ffH ;a=f5h,c=1,z=0
0093 CA9900 jz cpie ;test "cpi" for re-set zero
0096 DA9C00 jc acii ;test "cpi" for set carry
0099 CDE004 cpie: call cpuer
009C CE0A acii: aci 00aH ;a=f5h+0ah+carry(1)=0,c=1
009E CE0A aci 00aH ;a=0+0ah+carry(0)=0bh,c=0
00A0 FE0B cpi 00bH
00A2 CAA800 jz suii ;test "aci"
00A5 CDE004 call cpuer
00A8 D60C suii: sui 00cH ;a=ffh,c=0
00AA D60F sui 00fH ;a=f0h,c=1
00AC FEF0 cpi 0f0H
00AE CAB400 jz sbii ;test "sui"
00B1 CDE004 call cpuer
00B4 DEF1 sbii: sbi 0f1H ;a=f0h-0f1h-carry(0)=ffh,c=1
00B6 DE0E sbi 0eH ;a=ffh-oeh-carry(1)=f0h,c=0
00B8 FEF0 cpi 0f0H
00BA CAC000 jz anii ;test "sbi"
00BD CDE004 call cpuer
00C0 E655 anii: ani 055H ;a=f0h<and>55h=50h,c=0,p=1,s=0,z=0
00C2 FE50 cpi 050H
00C4 CACA00 jz orii ;test "ani"
00C7 CDE004 call cpuer
00CA F63A orii: ori 03aH ;a=50h<or>3ah=7ah,c=0,p=0,s=0,z=0
00CC FE7A cpi 07aH
00CE CAD400 jz xrii ;test "ori"
00D1 CDE004 call cpuer
00D4 EE0F xrii: xri 00fH ;a=7ah<xor>0fh=75h,c=0,p=0,s=0,z=0
00D6 FE75 cpi 075H
00D8 CADE00 jz c010 ;test "xri"
00DB CDE004 call cpuer
;
;
;
;test calls and returns
;
00DE E600 c010: ani 0H ;a=0,c=0,p=1,s=0,z=1
00E0 DCE004 cc cpuer ;test "cc"
00E3 E4E004 cpo cpuer ;test "cpo"
00E6 FCE004 cm cpuer ;test "cm"
00E9 C4E004 cnz cpuer ;test "cnz"
00EC FE00 cpi 0H
00EE CAF400 jz c020 ;a=0,c=0,p=0,s=0,z=1
00F1 CDE004 call cpuer
00F4 D677 c020: sui 077H ;a=89h,c=1,p=0,s=1,z=0
00F6 D4E004 cnc cpuer ;test "cnc"
00F9 ECE004 cpe cpuer ;test "cpe"
00FC F4E004 cp cpuer ;test "cp"
00FF CCE004 cz cpuer ;test "cz"
0102 FE89 cpi 089H
0104 CA0A01 jz c030 ;test for "calls" taking branch
0107 CDE004 call cpuer
010A E6FF c030: ani 0ffH ;set flags back;
010C E41701 cpo cpoi ;test "cpo"
010F FED9 cpi 0d9H
0111 CA7401 jz movi ;test "call" sequence success
0114 CDE004 call cpuer
0117 E8 cpoi: rpe ;test "rpe"
0118 C610 adi 010H ;a=99h,c=0,p=0,s=1,z=0
011A EC2301 cpe cpei ;test "cpe"
011D C602 adi 002H ;a=d9h,c=0,p=0,s=1,z=0
011F E0 rpo ;test "rpo"
0120 CDE004 call cpuer
0123 E0 cpei: rpo ;test "rpo"
0124 C620 adi 020H ;a=b9h,c=0,p=0,s=1,z=0
0126 FC2F01 cm cmi ;test "cm"
0129 C604 adi 004H ;a=d7h,c=0,p=1,s=1,z=0
012B E8 rpe ;test "rpe"
012C CDE004 call cpuer
012F F0 cmi: rp ;test "rp"
0130 C680 adi 080H ;a=39h,c=1,p=1,s=0,z=0
0132 F43B01 cp tcpi ;test "cp"
0135 C680 adi 080H ;a=d3h,c=0,p=0,s=1,z=0
0137 F8 rm ;test "rm"
0138 CDE004 call cpuer
013B F8 tcpi: rm ;test "rm"
013C C640 adi 040H ;a=79h,c=0,p=0,s=0,z=0
013E D44701 cnc cnci ;test "cnc"
0141 C640 adi 040H ;a=53h,c=0,p=1,s=0,z=0
0143 F0 rp ;test "rp"
0144 CDE004 call cpuer
0147 D8 cnci: rc ;test "rc"
0148 C68F adi 08fH ;a=08h,c=1,p=0,s=0,z=0
014A DC5301 cc cci ;test "cc"
014D D602 sui 002H ;a=13h,c=0,p=0,s=0,z=0
014F D0 rnc ;test "rnc"
0150 CDE004 call cpuer
0153 D0 cci: rnc ;test "rnc"
0154 C6F7 adi 0f7H ;a=ffh,c=0,p=1,s=1,z=0
0156 C45F01 cnz cnzi ;test "cnz"
0159 C6FE adi 0feH ;a=15h,c=1,p=0,s=0,z=0
015B D8 rc ;test "rc"
015C CDE004 call cpuer
015F C8 cnzi: rz ;test "rz"
0160 C601 adi 001H ;a=00h,c=1,p=1,s=0,z=1
0162 CC6B01 cz czi ;test "cz"
0165 C6D0 adi 0d0H ;a=17h,c=1,p=1,s=0,z=0
0167 C0 rnz ;test "rnz"
0168 CDE004 call cpuer
016B C0 czi: rnz ;test "rnz"
016C C647 adi 047H ;a=47h,c=0,p=1,s=0,z=0
016E FE47 cpi 047H ;a=47h,c=0,p=1,s=0,z=1
0170 C8 rz ;test "rz"
0171 CDE004 call cpuer
;
;
;
;test "mov","inr",and "dcr" instructions
;
0174 3E77 movi: mvi a,077H
0176 3C inr a
0177 47 mov b,a
0178 04 inr b
0179 48 mov c,b
017A 0D dcr c
017B 51 mov d,c
017C 5A mov e,d
017D 63 mov h,e
017E 6C mov l,h
017F 7D mov a,l ;test "mov" a,l,h,e,d,c,b,a
0180 3D dcr a
0181 4F mov c,a
0182 59 mov e,c
0183 6B mov l,e
0184 45 mov b,l
0185 50 mov d,b
0186 62 mov h,d
0187 7C mov a,h ;test "mov" a,h,d,b,l,e,c,a
0188 57 mov d,a
0189 14 inr d
018A 6A mov l,d
018B 4D mov c,l
018C 0C inr c
018D 61 mov h,c
018E 44 mov b,h
018F 05 dcr b
0190 58 mov e,b
0191 7B mov a,e ;test "mov" a,e,b,h,c,l,d,a
0192 5F mov e,a
0193 1C inr e
0194 43 mov b,e
0195 60 mov h,b
0196 24 inr h
0197 4C mov c,h
0198 69 mov l,c
0199 55 mov d,l
019A 15 dcr d
019B 7A mov a,d ;test "mov" a,d,l,c,h,b,e,a
019C 67 mov h,a
019D 25 dcr h
019E 54 mov d,h
019F 42 mov b,d
01A0 68 mov l,b
01A1 2C inr l
01A2 5D mov e,l
01A3 1D dcr e
01A4 4B mov c,e
01A5 79 mov a,c ;test "mov" a,c,e,l,b,d,h,a
01A6 6F mov l,a
01A7 2D dcr l
01A8 65 mov h,l
01A9 5C mov e,h
01AA 53 mov d,e
01AB 4A mov c,d
01AC 41 mov b,c
01AD 78 mov a,b
01AE FE77 cpi 077H
01B0 C4E004 cnz cpuer ;test "mov" a,b,c,d,e,h,l,a
;
;
;
;test arithmetic and logic instructions
;
01B3 AF xra a
01B4 0601 mvi b,001H
01B6 0E03 mvi c,003H
01B8 1607 mvi d,007H
01BA 1E0F mvi e,00fH
01BC 261F mvi h,01fH
01BE 2E3F mvi l,03fH
01C0 80 add b
01C1 81 add c
01C2 82 add d
01C3 83 add e
01C4 84 add h
01C5 85 add l
01C6 87 add a
01C7 FEF0 cpi 0f0H
01C9 C4E004 cnz cpuer ;test "add" b,c,d,e,h,l,a
01CC 90 sub b
01CD 91 sub c
01CE 92 sub d
01CF 93 sub e
01D0 94 sub h
01D1 95 sub l
01D2 FE78 cpi 078H
01D4 C4E004 cnz cpuer ;test "sub" b,c,d,e,h,l
01D7 97 sub a
01D8 C4E004 cnz cpuer ;test "sub" a
01DB 3E80 mvi a,080H
01DD 87 add a
01DE 0601 mvi b,001H
01E0 0E02 mvi c,002H
01E2 1603 mvi d,003H
01E4 1E04 mvi e,004H
01E6 2605 mvi h,005H
01E8 2E06 mvi l,006H
01EA 88 adc b
01EB 0680 mvi b,080H
01ED 80 add b
01EE 80 add b
01EF 89 adc c
01F0 80 add b
01F1 80 add b
01F2 8A adc d
01F3 80 add b
01F4 80 add b
01F5 8B adc e
01F6 80 add b
01F7 80 add b
01F8 8C adc h
01F9 80 add b
01FA 80 add b
01FB 8D adc l
01FC 80 add b
01FD 80 add b
01FE 8F adc a
01FF FE37 cpi 037H
0201 C4E004 cnz cpuer ;test "adc" b,c,d,e,h,l,a
0204 3E80 mvi a,080H
0206 87 add a
0207 0601 mvi b,001H
0209 98 sbb b
020A 06FF mvi b,0ffH
020C 80 add b
020D 99 sbb c
020E 80 add b
020F 9A sbb d
0210 80 add b
0211 9B sbb e
0212 80 add b
0213 9C sbb h
0214 80 add b
0215 9D sbb l
0216 FEE0 cpi 0e0H
0218 C4E004 cnz cpuer ;test "sbb" b,c,d,e,h,l
021B 3E80 mvi a,080H
021D 87 add a
021E 9F sbb a
021F FEFF cpi 0ffH
0221 C4E004 cnz cpuer ;test "sbb" a
0224 3EFF mvi a,0ffH
0226 06FE mvi b,0feH
0228 0EFC mvi c,0fcH
022A 16EF mvi d,0efH
022C 1E7F mvi e,07fH
022E 26F4 mvi h,0f4H
0230 2EBF mvi l,0bfH
0232 A7 ana a
0233 A1 ana c
0234 A2 ana d
0235 A3 ana e
0236 A4 ana h
0237 A5 ana l
0238 A7 ana a
0239 FE24 cpi 024H
023B C4E004 cnz cpuer ;test "ana" b,c,d,e,h,l,a
023E AF xra a
023F 0601 mvi b,001H
0241 0E02 mvi c,002H
0243 1604 mvi d,004H
0245 1E08 mvi e,008H
0247 2610 mvi h,010H
0249 2E20 mvi l,020H
024B B0 ora b
024C B1 ora c
024D B2 ora d
024E B3 ora e
024F B4 ora h
0250 B5 ora l
0251 B7 ora a
0252 FE3F cpi 03fH
0254 C4E004 cnz cpuer ;test "ora" b,c,d,e,h,l,a
0257 3E00 mvi a,0H
0259 268F mvi h,08fH
025B 2E4F mvi l,04fH
025D A8 xra b
025E A9 xra c
025F AA xra d
0260 AB xra e
0261 AC xra h
0262 AD xra l
0263 FECF cpi 0cfH
0265 C4E004 cnz cpuer ;test "xra" b,c,d,e,h,l
0268 AF xra a
0269 C4E004 cnz cpuer ;test "xra" a
026C 0644 mvi b,044H
026E 0E45 mvi c,045H
0270 1646 mvi d,046H
0272 1E47 mvi e,047H
0274 2604 mvi h,(temp0 / 0ffH) ;high byte of test memory location
0276 2EE8 mvi l,(temp0 and 0ffH) ;low byte of test memory location
0278 70 mov m,b
0279 0600 mvi b,0H
027B 46 mov b,m
027C 3E44 mvi a,044H
027E B8 cmp b
027F C4E004 cnz cpuer ;test "mov" m,b and b,m
0282 72 mov m,d
0283 1600 mvi d,0H
0285 56 mov d,m
0286 3E46 mvi a,046H
0288 BA cmp d
0289 C4E004 cnz cpuer ;test "mov" m,d and d,m
028C 73 mov m,e
028D 1E00 mvi e,0H
028F 5E mov e,m
0290 3E47 mvi a,047H
0292 BB cmp e
0293 C4E004 cnz cpuer ;test "mov" m,e and e,m
0296 74 mov m,h
0297 2604 mvi h,(temp0 / 0ffH)
0299 2EE8 mvi l,(temp0 and 0ffH)
029B 66 mov h,m
029C 3E04 mvi a,(temp0 / 0ffH)
029E BC cmp h
029F C4E004 cnz cpuer ;test "mov" m,h and h,m
02A2 75 mov m,l
02A3 2604 mvi h,(temp0 / 0ffH)
02A5 2EE8 mvi l,(temp0 and 0ffH)
02A7 6E mov l,m
02A8 3EE8 mvi a,(temp0 and 0ffH)
02AA BD cmp l
02AB C4E004 cnz cpuer ;test "mov" m,l and l,m
02AE 2604 mvi h,(temp0 / 0ffH)
02B0 2EE8 mvi l,(temp0 and 0ffH)
02B2 3E32 mvi a,032H
02B4 77 mov m,a
02B5 BE cmp m
02B6 C4E004 cnz cpuer ;test "mov" m,a
02B9 86 add m
02BA FE64 cpi 064H
02BC C4E004 cnz cpuer ;test "add" m
02BF AF xra a
02C0 7E mov a,m
02C1 FE32 cpi 032H
02C3 C4E004 cnz cpuer ;test "mov" a,m
02C6 2604 mvi h,(temp0 / 0ffH)
02C8 2EE8 mvi l,(temp0 and 0ffH)
02CA 7E mov a,m
02CB 96 sub m
02CC C4E004 cnz cpuer ;test "sub" m
02CF 3E80 mvi a,080H
02D1 87 add a
02D2 8E adc m
02D3 FE33 cpi 033H
02D5 C4E004 cnz cpuer ;test "adc" m
02D8 3E80 mvi a,080H
02DA 87 add a
02DB 9E sbb m
02DC FECD cpi 0cdH
02DE C4E004 cnz cpuer ;test "sbb" m
02E1 A6 ana m
02E2 C4E004 cnz cpuer ;test "ana" m
02E5 3E25 mvi a,025H
02E7 B6 ora m
02E8 FE37 cpi 37H
02EA C4E004 cnz cpuer ;test "ora" m
02ED AE xra m
02EE FE05 cpi 005H
02F0 C4E004 cnz cpuer ;test "xra" m
02F3 3655 mvi m,055H
02F5 34 inr m
02F6 35 dcr m
02F7 86 add m
02F8 FE5A cpi 05aH
02FA C4E004 cnz cpuer ;test "inr","dcr",and "mvi" m
02FD 01FF12 lxi b,12ffH
0300 11FF12 lxi d,12ffH
0303 21FF12 lxi h,12ffH
0306 03 inx b
0307 13 inx d
0308 23 inx h
0309 3E13 mvi a,013H
030B B8 cmp b
030C C4E004 cnz cpuer ;test "lxi" and "inx" b
030F BA cmp d
0310 C4E004 cnz cpuer ;test "lxi" and "inx" d
0313 BC cmp h
0314 C4E004 cnz cpuer ;test "lxi" and "inx" h
0317 3E00 mvi a,0H
0319 B9 cmp c
031A C4E004 cnz cpuer ;test "lxi" and "inx" b
031D BB cmp e
031E C4E004 cnz cpuer ;test "lxi" and "inx" d
0321 BD cmp l
0322 C4E004 cnz cpuer ;test "lxi" and "inx" h
0325 0B dcx b
0326 1B dcx d
0327 2B dcx h
0328 3E12 mvi a,012H
032A B8 cmp b
032B C4E004 cnz cpuer ;test "dcx" b
032E BA cmp d
032F C4E004 cnz cpuer ;test "dcx" d
0332 BC cmp h
0333 C4E004 cnz cpuer ;test "dcx" h
0336 3EFF mvi a,0ffH
0338 B9 cmp c
0339 C4E004 cnz cpuer ;test "dcx" b
033C BB cmp e
033D C4E004 cnz cpuer ;test "dcx" d
0340 BD cmp l
0341 C4E004 cnz cpuer ;test "dcx" h
0344 32E804 sta temp0
0347 AF xra a
0348 3AE804 lda temp0
034B FEFF cpi 0ffH
034D C4E004 cnz cpuer ;test "lda" and "sta"
0350 2AE604 lhld tempp
0353 22E804 shld temp0
0356 3AE604 lda tempp
0359 47 mov b,a
035A 3AE804 lda temp0
035D B8 cmp b
035E C4E004 cnz cpuer ;test "lhld" and "shld"
0361 3AE704 lda tempp+1
0364 47 mov b,a
0365 3AE904 lda temp0+1
0368 B8 cmp b
0369 C4E004 cnz cpuer ;test "lhld" and "shld"
036C 3EAA mvi a,0aaH
036E 32E804 sta temp0
0371 44 mov b,h
0372 4D mov c,l
0373 AF xra a
0374 0A ldax b
0375 FEAA cpi 0aaH
0377 C4E004 cnz cpuer ;test "ldax" b
037A 3C inr a
037B 02 stax b
037C 3AE804 lda temp0
037F FEAB cpi 0abH
0381 C4E004 cnz cpuer ;test "stax" b
0384 3E77 mvi a,077H
0386 32E804 sta temp0
0389 2AE604 lhld tempp
038C 110000 lxi d,00000H
038F EB xchg
0390 AF xra a
0391 1A ldax d
0392 FE77 cpi 077H
0394 C4E004 cnz cpuer ;test "ldax" d and "xchg"
0397 AF xra a
0398 84 add h
0399 85 add l
039A C4E004 cnz cpuer ;test "xchg"
039D 3ECC mvi a,0ccH
039F 12 stax d
03A0 3AE804 lda temp0
03A3 FECC cpi 0ccH
03A5 12 stax d
03A6 3AE804 lda temp0
03A9 FECC cpi 0ccH
03AB C4E004 cnz cpuer ;test "stax" d
03AE 217777 lxi h,07777H
03B1 29 dad h
03B2 3EEE mvi a,0eeH
03B4 BC cmp h
03B5 C4E004 cnz cpuer ;test "dad" h
03B8 BD cmp l
03B9 C4E004 cnz cpuer ;test "dad" h
03BC 215555 lxi h,05555H
03BF 01FFFF lxi b,0ffffH
03C2 09 dad b
03C3 3E55 mvi a,055H
03C5 D4E004 cnc cpuer ;test "dad" b
03C8 BC cmp h
03C9 C4E004 cnz cpuer ;test "dad" b
03CC 3E54 mvi a,054H
03CE BD cmp l
03CF C4E004 cnz cpuer ;test "dad" b
03D2 21AAAA lxi h,0aaaaH
03D5 113333 lxi d,03333H
03D8 19 dad d
03D9 3EDD mvi a,0ddH
03DB BC cmp h
03DC C4E004 cnz cpuer ;test "dad" d
03DF BD cmp l
03E0 C4E004 cnz cpuer ;test "dad" b
03E3 37 stc
03E4 D4E004 cnc cpuer ;test "stc"
03E7 3F cmc
03E8 DCE004 cc cpuer ;test "cmc
03EB 3EAA mvi a,0aaH
03ED 2F cma
03EE FE55 cpi 055H
03F0 C4E004 cnz cpuer ;test "cma"
03F3 B7 ora a ;re-set auxiliary carry
03F4 27 daa
03F5 FE55 cpi 055H
03F7 C4E004 cnz cpuer ;test "daa"
03FA 3E88 mvi a,088H
03FC 87 add a
03FD 27 daa
03FE FE76 cpi 076H
0400 C4E004 cnz cpuer ;test "daa"
0403 AF xra a
0404 3EAA mvi a,0aaH
0406 27 daa
0407 D4E004 cnc cpuer ;test "daa"
040A FE10 cpi 010H
040C C4E004 cnz cpuer ;test "daa"
040F AF xra a
0410 3E9A mvi a,09aH
0412 27 daa
0413 D4E004 cnc cpuer ;test "daa"
0416 C4E004 cnz cpuer ;test "daa"
0419 37 stc
041A 3E42 mvi a,042H
041C 07 rlc
041D DCE004 cc cpuer ;test "rlc" for re-set carry
0420 07 rlc
0421 D4E004 cnc cpuer ;test "rlc" for set carry
0424 FE09 cpi 009H
0426 C4E004 cnz cpuer ;test "rlc" for rotation
0429 0F rrc
042A D4E004 cnc cpuer ;test "rrc" for set carry
042D 0F rrc
042E FE42 cpi 042H
0430 C4E004 cnz cpuer ;test "rrc" for rotation
0433 17 ral
0434 17 ral
0435 D4E004 cnc cpuer ;test "ral" for set carry
0438 FE08 cpi 008H
043A C4E004 cnz cpuer ;test "ral" for rotation
043D 1F rar
043E 1F rar
043F DCE004 cc cpuer ;test "rar" for re-set carry
0442 FE02 cpi 002H
0444 C4E004 cnz cpuer ;test "rar" for rotation
0447 013412 lxi b,01234H
044A 11AAAA lxi d,0aaaaH
044D 215555 lxi h,05555H
0450 AF xra a
0451 C5 push b
0452 D5 push d
0453 E5 push h
0454 F5 push psw
0455 010000 lxi b,00000H
0458 110000 lxi d,00000H
045B 210000 lxi h,00000H
045E 3EC0 mvi a,0c0H
0460 C6F0 adi 0f0H
0462 F1 pop psw
0463 E1 pop h
0464 D1 pop d
0465 C1 pop b
0466 DCE004 cc cpuer ;test "push psw" and "pop psw"
0469 C4E004 cnz cpuer ;test "push psw" and "pop psw"
046C E4E004 cpo cpuer ;test "push psw" and "pop psw"
046F FCE004 cm cpuer ;test "push psw" and "pop psw"
0472 3E12 mvi a,012H
0474 B8 cmp b
0475 C4E004 cnz cpuer ;test "push b" and "pop b"
0478 3E34 mvi a,034H
047A B9 cmp c
047B C4E004 cnz cpuer ;test "push b" and "pop b"
047E 3EAA mvi a,0aaH
0480 BA cmp d
0481 C4E004 cnz cpuer ;test "push d" and "pop d"
0484 BB cmp e
0485 C4E004 cnz cpuer ;test "push d" and "pop d"
0488 3E55 mvi a,055H
048A BC cmp h
048B C4E004 cnz cpuer ;test "push h" and "pop h"
048E BD cmp l
048F C4E004 cnz cpuer ;test "push h" and "pop h"
0492 210000 lxi h,00000H
0495 39 dad sp
0496 22ED04 shld savstk ;save the "old" stack-pointer;
0499 31EC04 lxi sp,temp4
049C 3B dcx sp
049D 3B dcx sp
049E 33 inx sp
049F 3B dcx sp
04A0 3E55 mvi a,055H
04A2 32EA04 sta temp2
04A5 2F cma
04A6 32EB04 sta temp3
04A9 C1 pop b
04AA B8 cmp b
04AB C4E004 cnz cpuer ;test "lxi","dad","inx",and "dcx" sp
04AE 2F cma
04AF B9 cmp c
04B0 C4E004 cnz cpuer ;test "lxi","dad","inx", and "dcx" sp
04B3 21EC04 lxi h,temp4
04B6 F9 sphl
04B7 213377 lxi h,07733H
04BA 3B dcx sp
04BB 3B dcx sp
04BC E3 xthl
04BD 3AEB04 lda temp3
04C0 FE77 cpi 077H
04C2 C4E004 cnz cpuer ;test "sphl" and "xthl"
04C5 3AEA04 lda temp2
04C8 FE33 cpi 033H
04CA C4E004 cnz cpuer ;test "sphl" and "xthl"
04CD 3E55 mvi a,055H
04CF BD cmp l
04D0 C4E004 cnz cpuer ;test "sphl" and "xthl"
04D3 2F cma
04D4 BC cmp h
04D5 C4E004 cnz cpuer ;test "sphl" and "xthl"
04D8 2AED04 lhld savstk ;restore the "old" stack-pointer
04DB F9 sphl
04DC 21E304 lxi h,cpuok
04DF E9 pchl ;test "pchl"
04E0 3EAA cpuer: mvi a, 0aaH ; set exit code (failure)
04E2 76 hlt ; stop here
04E3 3E55 cpuok: mvi a, 55H ;
04E5 76 hlt ; stop here - no trap
;
; Data area in program space
;
04E6 E804 tempp: dw temp0 ;pointer used to test "lhld","shld",
; and "ldax" instructions
;
; Data area in variable space
;
04E8 temp0: ds 1 ;temporary storage for cpu test memory locations
04E9 temp1: ds 1 ;temporary storage for cpu test memory locations
04EA temp2: ds 1 ;temporary storage for cpu test memory locations
04EB temp3: ds 1 ;temporary storage for cpu test memory locations
04EC temp4: ds 1 ;temporary storage for cpu test memory locations
04ED savstk: ds 2 ;temporary stack-pointer storage location
04EF ds 256 ;de-bug stack pointer storage area
05EF 0000 stack: dw 0
/trunk/asm/TB1.PRN
0,0 → 1,62
 
 
0000 org 0H
0000 C34000 jmp start
; this will be used as interrupt routine
0020 org 20H
0020 C607 adi 7H
0022 FB ei
0023 C9 ret
; used as rst test
0028 org 28H
0028 47 mov b,a
0029 C9 ret
0040 start: org 40H
0040 310602 lxi sp,stack
0043 FB ei
0044 3E00 mvi a,0H ; a=0, b=?
0046 EF rst 5 ; rst 28h -> a=00h, b=00h
0047 C601 adi 1H ; a = 08h (interrupt 1 hits here: a = a + 07h)
0049 C601 adi 1H ; a = 09h
004B C601 adi 1H ; a = 0ah
004D C601 adi 1H ; a = 0bh
004F C601 adi 1H ; a = 0ch (interrupt 2 hits here: c = 0ch)
0051 C601 adi 1H ; a = 0dh
0053 C601 adi 1H ; a = 0eh
0055 FB ei
0056 C601 adi 1H ; a = 0fh
0058 C601 adi 1H ; a = 10h
005A C601 adi 1H ; a = 11h
005C FB ei
005D 76 hlt
005E FE11 cpi 11h
0060 C27B00 jnz fail
0063 78 mov a,b
0064 FE00 cpi 0
0066 C27B00 jnz fail
0069 79 mov a,c
006A FE0C cpi 0ch
006C C27B00 jnz fail
006F 7A mov a,d
0070 FE12 cpi 12h
0072 7B mov a,e
0073 FE34 cpi 34h
0075 C27B00 jnz fail
0078 3E55 mvi a,55h
007A 76 hlt
007B 3EAA fail: mvi a,0aah
007D 76 hlt
0100 org 100H
0100 C609 adi 9h
0102 0677 mvi b,77h
0104 FB ei
0105 C9 ret
; data space
0106 ds 256
0206 0000 stack: dw 0
/trunk/asm/tb0.asm
0,0 → 1,822
;***********************************************************************
; MICROCOSM ASSOCIATES 8080/8085 CPU DIAGNOSTIC VERSION 1.0 (C) 1980
;***********************************************************************
;
;DONATED TO THE "SIG/M" CP/M USER'S GROUP BY:
;KELLY SMITH, MICROCOSM ASSOCIATES
;3055 WACO AVENUE
;SIMI VALLEY, CALIFORNIA, 93065
;(805) 527-9321 (MODEM, CP/M-NET (TM))
;(805) 527-0518 (VERBAL)
;
;***********************************************************************
; Modified 2001/02/28 by Richard Cini for use in the Altair32 Emulator
; Project
;
; Need to somehow connect this code to Windows so that failure messages
; can be posted to Windows. Maybe just store error code in
; Mem[0xffff]. Maybe trap NOP in the emulator code?
;
;***********************************************************************
; Modified 2006/11/16 by Scott Moore to work on CPU8080 FPGA core
;
;***********************************************************************
; Modified 2007/09/24 by Jose Ruiz for use in free8080 FPGA core
;
; 1.- Changed formatting for compatibility to CP/M's ASM
; 2.- Commented out all Altair / MITS hardware related stuff
; 3.- Set origin at 0H
;
;***********************************************************************
 
 
;
; Select controller defines
;
;selmain: equ 00H ; offset of main control register
;sel1msk: equ 02H ; offset of select 1 mask
;sel1cmp: equ 03H ; offset of select 1 compare
;sel2msk: equ 04H ; offset of select 1 mask
;sel2cmp: equ 05H ; offset of select 1 compare
;sel3msk: equ 06H ; offset of select 1 mask
;sel3cmp: equ 07H ; offset of select 1 compare
;sel4msk: equ 08H ; offset of select 1 mask
;sel4cmp: equ 09H ; offset of select 1 compare
;
; bits
;
;selenb: equ 01H ; enable select
;selio: equ 02H ; I/O address or memory
 
;
; Note: select 1 is ROM, 2, is RAM, 3 is interrupt controller, 4 is serial I/O.
;
 
;
; Where to place ROM and RAM for this test
;
;rombas: equ 0000H
;rambas: equ rombas+4*1024
;
; Interrupt controller defines
;
;intbas: equ 10H
;intmsk: equ intbas+00H ; mask
;intsts: equ intbas+01H ; status
;intact: equ intbas+02H ; active interrupt
;intpol: equ intbas+03H ; polarity select
;intedg: equ intbas+04H ; edge/level select
;intvec: equ intbas+05H ; vector base page
;
; Mits Serial I/O card
;
;siobas: equ 20H
;sioctl: equ siobas+00H ; control register
;siodat: equ siobas+01H ; data
 
;
; Set up selectors
;
 
;
; ROM
;
; mvi a,rombas shr 8 ; enable select 1 to 4kb at base
; out sel1cmp
; mvi a,(0f000H shr 8) or selenb
; out sel1msk
;
; RAM
;
; mvi a,rambas shr 8 ; enable select 2 to 1kb at base
; out sel2cmp
; mvi a,(0fc00H shr 8) or selenb
; out sel2msk
;
; ROM and RAM set up, exit bootstrap mode
;
; mvi a,00H ; exit bootstrap mode
; out selmain
;
; Serial I/O
;
; mvi a,siobas ; enable serial controller for 4 addresses
; out sel4cmp
; mvi a,0fcH or selio or selenb
; out sel4msk
 
;************************************************************
; 8080/8085 CPU TEST/DIAGNOSTIC
;************************************************************
;
;note: (1) program assumes "call",and "lxi sp" instructions work;
;
; (2) instructions not tested are "hlt","di","ei",
; and "rst 0" thru "rst 7"
;
;
;
;test jump instructions and flags
;
org 0H
 
cpu: lxi sp,stack ;set the stack pointer
mvi a,077H ;@ initialize A to remove X values from simulation
ani 0 ;initialize a reg. and clear all flags
jz j010 ;test "jz"
call cpuer
j010: jnc j020 ;test "jnc"
call cpuer
j020: jpe j030 ;test "jpe"
call cpuer
j030: jp j040 ;test "jp"
call cpuer
j040: jnz j050 ;test "jnz"
jc j050 ;test "jc"
jpo j050 ;test "jpo"
jm j050 ;test "jm"
jmp j060 ;test "jmp" (it's a little late,but what the hell;
j050: call cpuer
j060: adi 6 ;a=6,c=0,p=1,s=0,z=0
jnz j070 ;test "jnz"
call cpuer
j070: jc j080 ;test "jc"
jpo j080 ;test "jpo"
jp j090 ;test "jp"
j080: call cpuer
j090: adi 70H ;a=76h,c=0,p=0,s=0,z=0
jpo j100 ;test "jpo"
call cpuer
j100: jm j110 ;test "jm"
jz j110 ;test "jz"
jnc j120 ;test "jnc"
j110: call cpuer
j120: adi 81H ;a=f7h,c=0,p=0,s=1,z=0
jm j130 ;test "jm"
call cpuer
j130: jz j140 ;test "jz"
jc j140 ;test "jc"
jpo j150 ;test "jpo"
j140: call cpuer
j150: adi 0feH ;a=f5h,c=1,p=1,s=1,z=0
jc j160 ;test "jc"
call cpuer
j160: jz j170 ;test "jz"
jpo j170 ;test "jpo"
jm aimm ;test "jm"
j170: call cpuer
;
;
;
;test accumulator immediate instructions
;
aimm: cpi 0 ;a=f5h,c=0,z=0
jc cpie ;test "cpi" for re-set carry
jz cpie ;test "cpi" for re-set zero
cpi 0f5H ;a=f5h,c=0,z=1
jc cpie ;test "cpi" for re-set carry ("adi")
jnz cpie ;test "cpi" for re-set zero
cpi 0ffH ;a=f5h,c=1,z=0
jz cpie ;test "cpi" for re-set zero
jc acii ;test "cpi" for set carry
cpie: call cpuer
acii: aci 00aH ;a=f5h+0ah+carry(1)=0,c=1
aci 00aH ;a=0+0ah+carry(0)=0bh,c=0
cpi 00bH
jz suii ;test "aci"
call cpuer
suii: sui 00cH ;a=ffh,c=0
sui 00fH ;a=f0h,c=1
cpi 0f0H
jz sbii ;test "sui"
call cpuer
sbii: sbi 0f1H ;a=f0h-0f1h-carry(0)=ffh,c=1
sbi 0eH ;a=ffh-oeh-carry(1)=f0h,c=0
cpi 0f0H
jz anii ;test "sbi"
call cpuer
anii: ani 055H ;a=f0h<and>55h=50h,c=0,p=1,s=0,z=0
cpi 050H
jz orii ;test "ani"
call cpuer
orii: ori 03aH ;a=50h<or>3ah=7ah,c=0,p=0,s=0,z=0
cpi 07aH
jz xrii ;test "ori"
call cpuer
xrii: xri 00fH ;a=7ah<xor>0fh=75h,c=0,p=0,s=0,z=0
cpi 075H
jz c010 ;test "xri"
call cpuer
;
;
;
;test calls and returns
;
c010: ani 0H ;a=0,c=0,p=1,s=0,z=1
cc cpuer ;test "cc"
cpo cpuer ;test "cpo"
cm cpuer ;test "cm"
cnz cpuer ;test "cnz"
cpi 0H
jz c020 ;a=0,c=0,p=0,s=0,z=1
call cpuer
c020: sui 077H ;a=89h,c=1,p=0,s=1,z=0
cnc cpuer ;test "cnc"
cpe cpuer ;test "cpe"
cp cpuer ;test "cp"
cz cpuer ;test "cz"
cpi 089H
jz c030 ;test for "calls" taking branch
call cpuer
c030: ani 0ffH ;set flags back;
cpo cpoi ;test "cpo"
cpi 0d9H
jz movi ;test "call" sequence success
call cpuer
cpoi: rpe ;test "rpe"
adi 010H ;a=99h,c=0,p=0,s=1,z=0
cpe cpei ;test "cpe"
adi 002H ;a=d9h,c=0,p=0,s=1,z=0
rpo ;test "rpo"
call cpuer
cpei: rpo ;test "rpo"
adi 020H ;a=b9h,c=0,p=0,s=1,z=0
cm cmi ;test "cm"
adi 004H ;a=d7h,c=0,p=1,s=1,z=0
rpe ;test "rpe"
call cpuer
cmi: rp ;test "rp"
adi 080H ;a=39h,c=1,p=1,s=0,z=0
cp tcpi ;test "cp"
adi 080H ;a=d3h,c=0,p=0,s=1,z=0
rm ;test "rm"
call cpuer
tcpi: rm ;test "rm"
adi 040H ;a=79h,c=0,p=0,s=0,z=0
cnc cnci ;test "cnc"
adi 040H ;a=53h,c=0,p=1,s=0,z=0
rp ;test "rp"
call cpuer
cnci: rc ;test "rc"
adi 08fH ;a=08h,c=1,p=0,s=0,z=0
cc cci ;test "cc"
sui 002H ;a=13h,c=0,p=0,s=0,z=0
rnc ;test "rnc"
call cpuer
cci: rnc ;test "rnc"
adi 0f7H ;a=ffh,c=0,p=1,s=1,z=0
cnz cnzi ;test "cnz"
adi 0feH ;a=15h,c=1,p=0,s=0,z=0
rc ;test "rc"
call cpuer
cnzi: rz ;test "rz"
adi 001H ;a=00h,c=1,p=1,s=0,z=1
cz czi ;test "cz"
adi 0d0H ;a=17h,c=1,p=1,s=0,z=0
rnz ;test "rnz"
call cpuer
czi: rnz ;test "rnz"
adi 047H ;a=47h,c=0,p=1,s=0,z=0
cpi 047H ;a=47h,c=0,p=1,s=0,z=1
rz ;test "rz"
call cpuer
;
;
;
;test "mov","inr",and "dcr" instructions
;
movi: mvi a,077H
inr a
mov b,a
inr b
mov c,b
dcr c
mov d,c
mov e,d
mov h,e
mov l,h
mov a,l ;test "mov" a,l,h,e,d,c,b,a
dcr a
mov c,a
mov e,c
mov l,e
mov b,l
mov d,b
mov h,d
mov a,h ;test "mov" a,h,d,b,l,e,c,a
mov d,a
inr d
mov l,d
mov c,l
inr c
mov h,c
mov b,h
dcr b
mov e,b
mov a,e ;test "mov" a,e,b,h,c,l,d,a
mov e,a
inr e
mov b,e
mov h,b
inr h
mov c,h
mov l,c
mov d,l
dcr d
mov a,d ;test "mov" a,d,l,c,h,b,e,a
mov h,a
dcr h
mov d,h
mov b,d
mov l,b
inr l
mov e,l
dcr e
mov c,e
mov a,c ;test "mov" a,c,e,l,b,d,h,a
mov l,a
dcr l
mov h,l
mov e,h
mov d,e
mov c,d
mov b,c
mov a,b
cpi 077H
cnz cpuer ;test "mov" a,b,c,d,e,h,l,a
;
;
;
;test arithmetic and logic instructions
;
xra a
mvi b,001H
mvi c,003H
mvi d,007H
mvi e,00fH
mvi h,01fH
mvi l,03fH
add b
add c
add d
add e
add h
add l
add a
cpi 0f0H
cnz cpuer ;test "add" b,c,d,e,h,l,a
sub b
sub c
sub d
sub e
sub h
sub l
cpi 078H
cnz cpuer ;test "sub" b,c,d,e,h,l
sub a
cnz cpuer ;test "sub" a
mvi a,080H
add a
mvi b,001H
mvi c,002H
mvi d,003H
mvi e,004H
mvi h,005H
mvi l,006H
adc b
mvi b,080H
add b
add b
adc c
add b
add b
adc d
add b
add b
adc e
add b
add b
adc h
add b
add b
adc l
add b
add b
adc a
cpi 037H
cnz cpuer ;test "adc" b,c,d,e,h,l,a
mvi a,080H
add a
mvi b,001H
sbb b
mvi b,0ffH
add b
sbb c
add b
sbb d
add b
sbb e
add b
sbb h
add b
sbb l
cpi 0e0H
cnz cpuer ;test "sbb" b,c,d,e,h,l
mvi a,080H
add a
sbb a
cpi 0ffH
cnz cpuer ;test "sbb" a
mvi a,0ffH
mvi b,0feH
mvi c,0fcH
mvi d,0efH
mvi e,07fH
mvi h,0f4H
mvi l,0bfH
ana a
ana c
ana d
ana e
ana h
ana l
ana a
cpi 024H
cnz cpuer ;test "ana" b,c,d,e,h,l,a
xra a
mvi b,001H
mvi c,002H
mvi d,004H
mvi e,008H
mvi h,010H
mvi l,020H
ora b
ora c
ora d
ora e
ora h
ora l
ora a
cpi 03fH
cnz cpuer ;test "ora" b,c,d,e,h,l,a
mvi a,0H
mvi h,08fH
mvi l,04fH
xra b
xra c
xra d
xra e
xra h
xra l
cpi 0cfH
cnz cpuer ;test "xra" b,c,d,e,h,l
xra a
cnz cpuer ;test "xra" a
mvi b,044H
mvi c,045H
mvi d,046H
mvi e,047H
mvi h,(temp0 / 0ffH) ;high byte of test memory location
mvi l,(temp0 and 0ffH) ;low byte of test memory location
mov m,b
mvi b,0H
mov b,m
mvi a,044H
cmp b
cnz cpuer ;test "mov" m,b and b,m
mov m,d
mvi d,0H
mov d,m
mvi a,046H
cmp d
cnz cpuer ;test "mov" m,d and d,m
mov m,e
mvi e,0H
mov e,m
mvi a,047H
cmp e
cnz cpuer ;test "mov" m,e and e,m
mov m,h
mvi h,(temp0 / 0ffH)
mvi l,(temp0 and 0ffH)
mov h,m
mvi a,(temp0 / 0ffH)
cmp h
cnz cpuer ;test "mov" m,h and h,m
mov m,l
mvi h,(temp0 / 0ffH)
mvi l,(temp0 and 0ffH)
mov l,m
mvi a,(temp0 and 0ffH)
cmp l
cnz cpuer ;test "mov" m,l and l,m
mvi h,(temp0 / 0ffH)
mvi l,(temp0 and 0ffH)
mvi a,032H
mov m,a
cmp m
cnz cpuer ;test "mov" m,a
add m
cpi 064H
cnz cpuer ;test "add" m
xra a
mov a,m
cpi 032H
cnz cpuer ;test "mov" a,m
mvi h,(temp0 / 0ffH)
mvi l,(temp0 and 0ffH)
mov a,m
sub m
cnz cpuer ;test "sub" m
mvi a,080H
add a
adc m
cpi 033H
cnz cpuer ;test "adc" m
mvi a,080H
add a
sbb m
cpi 0cdH
cnz cpuer ;test "sbb" m
ana m
cnz cpuer ;test "ana" m
mvi a,025H
ora m
cpi 37H
cnz cpuer ;test "ora" m
xra m
cpi 005H
cnz cpuer ;test "xra" m
mvi m,055H
inr m
dcr m
add m
cpi 05aH
cnz cpuer ;test "inr","dcr",and "mvi" m
lxi b,12ffH
lxi d,12ffH
lxi h,12ffH
inx b
inx d
inx h
mvi a,013H
cmp b
cnz cpuer ;test "lxi" and "inx" b
cmp d
cnz cpuer ;test "lxi" and "inx" d
cmp h
cnz cpuer ;test "lxi" and "inx" h
mvi a,0H
cmp c
cnz cpuer ;test "lxi" and "inx" b
cmp e
cnz cpuer ;test "lxi" and "inx" d
cmp l
cnz cpuer ;test "lxi" and "inx" h
dcx b
dcx d
dcx h
mvi a,012H
cmp b
cnz cpuer ;test "dcx" b
cmp d
cnz cpuer ;test "dcx" d
cmp h
cnz cpuer ;test "dcx" h
mvi a,0ffH
cmp c
cnz cpuer ;test "dcx" b
cmp e
cnz cpuer ;test "dcx" d
cmp l
cnz cpuer ;test "dcx" h
sta temp0
xra a
lda temp0
cpi 0ffH
cnz cpuer ;test "lda" and "sta"
lhld tempp
shld temp0
lda tempp
mov b,a
lda temp0
cmp b
cnz cpuer ;test "lhld" and "shld"
lda tempp+1
mov b,a
lda temp0+1
cmp b
cnz cpuer ;test "lhld" and "shld"
mvi a,0aaH
sta temp0
mov b,h
mov c,l
xra a
ldax b
cpi 0aaH
cnz cpuer ;test "ldax" b
inr a
stax b
lda temp0
cpi 0abH
cnz cpuer ;test "stax" b
mvi a,077H
sta temp0
lhld tempp
lxi d,00000H
xchg
xra a
ldax d
cpi 077H
cnz cpuer ;test "ldax" d and "xchg"
xra a
add h
add l
cnz cpuer ;test "xchg"
mvi a,0ccH
stax d
lda temp0
cpi 0ccH
stax d
lda temp0
cpi 0ccH
cnz cpuer ;test "stax" d
lxi h,07777H
dad h
mvi a,0eeH
cmp h
cnz cpuer ;test "dad" h
cmp l
cnz cpuer ;test "dad" h
lxi h,05555H
lxi b,0ffffH
dad b
mvi a,055H
cnc cpuer ;test "dad" b
cmp h
cnz cpuer ;test "dad" b
mvi a,054H
cmp l
cnz cpuer ;test "dad" b
lxi h,0aaaaH
lxi d,03333H
dad d
mvi a,0ddH
cmp h
cnz cpuer ;test "dad" d
cmp l
cnz cpuer ;test "dad" b
stc
cnc cpuer ;test "stc"
cmc
cc cpuer ;test "cmc
mvi a,0aaH
cma
cpi 055H
cnz cpuer ;test "cma"
ora a ;re-set auxiliary carry
daa
cpi 055H
cnz cpuer ;test "daa"
mvi a,088H
add a
daa
cpi 076H
cnz cpuer ;test "daa"
xra a
mvi a,0aaH
daa
cnc cpuer ;test "daa"
cpi 010H
cnz cpuer ;test "daa"
xra a
mvi a,09aH
daa
cnc cpuer ;test "daa"
cnz cpuer ;test "daa"
stc
mvi a,042H
rlc
cc cpuer ;test "rlc" for re-set carry
rlc
cnc cpuer ;test "rlc" for set carry
cpi 009H
cnz cpuer ;test "rlc" for rotation
rrc
cnc cpuer ;test "rrc" for set carry
rrc
cpi 042H
cnz cpuer ;test "rrc" for rotation
ral
ral
cnc cpuer ;test "ral" for set carry
cpi 008H
cnz cpuer ;test "ral" for rotation
rar
rar
cc cpuer ;test "rar" for re-set carry
cpi 002H
cnz cpuer ;test "rar" for rotation
lxi b,01234H
lxi d,0aaaaH
lxi h,05555H
xra a
push b
push d
push h
push psw
lxi b,00000H
lxi d,00000H
lxi h,00000H
mvi a,0c0H
adi 0f0H
pop psw
pop h
pop d
pop b
cc cpuer ;test "push psw" and "pop psw"
cnz cpuer ;test "push psw" and "pop psw"
cpo cpuer ;test "push psw" and "pop psw"
cm cpuer ;test "push psw" and "pop psw"
mvi a,012H
cmp b
cnz cpuer ;test "push b" and "pop b"
mvi a,034H
cmp c
cnz cpuer ;test "push b" and "pop b"
mvi a,0aaH
cmp d
cnz cpuer ;test "push d" and "pop d"
cmp e
cnz cpuer ;test "push d" and "pop d"
mvi a,055H
cmp h
cnz cpuer ;test "push h" and "pop h"
cmp l
cnz cpuer ;test "push h" and "pop h"
lxi h,00000H
dad sp
shld savstk ;save the "old" stack-pointer;
lxi sp,temp4
dcx sp
dcx sp
inx sp
dcx sp
mvi a,055H
sta temp2
cma
sta temp3
pop b
cmp b
cnz cpuer ;test "lxi","dad","inx",and "dcx" sp
cma
cmp c
cnz cpuer ;test "lxi","dad","inx", and "dcx" sp
lxi h,temp4
sphl
lxi h,07733H
dcx sp
dcx sp
xthl
lda temp3
cpi 077H
cnz cpuer ;test "sphl" and "xthl"
lda temp2
cpi 033H
cnz cpuer ;test "sphl" and "xthl"
mvi a,055H
cmp l
cnz cpuer ;test "sphl" and "xthl"
cma
cmp h
cnz cpuer ;test "sphl" and "xthl"
lhld savstk ;restore the "old" stack-pointer
sphl
lxi h,cpuok
pchl ;test "pchl"
 
cpuer: mvi a, 0aaH ; set exit code (failure)
hlt ; stop here
 
cpuok: mvi a, 55H ;
hlt ; stop here - no trap
 
 
;
; Data area in program space
;
tempp: dw temp0 ;pointer used to test "lhld","shld",
; and "ldax" instructions
;
; Data area in variable space
;
temp0: ds 1 ;temporary storage for cpu test memory locations
temp1: ds 1 ;temporary storage for cpu test memory locations
temp2: ds 1 ;temporary storage for cpu test memory locations
temp3: ds 1 ;temporary storage for cpu test memory locations
temp4: ds 1 ;temporary storage for cpu test memory locations
savstk: ds 2 ;temporary stack-pointer storage location
 
ds 256 ;de-bug stack pointer storage area
stack: dw 0
 
/trunk/asm/tb1.asm
0,0 → 1,68
;*******************************************************************************
; light8080 core test bench 1
; interrupt & halt test
;*******************************************************************************
; When used in the test bench vhdl\test\light8080_tb1.vhdl, this program
; should take 410 clock cycles to compplete, ending in halt state.
; At that moment, a 055h value in ACC means success and a 0aah means failure.
;*******************************************************************************
 
org 0H
jmp start
; this will be used as interrupt routine
org 20H
adi 7H
ei
ret
; used as rst test
org 28H
mov b,a
ret
start: org 40H
lxi sp,stack
ei
mvi a,0H ; a=0, b=?
rst 5 ; rst 28h -> a=00h, b=00h
adi 1H ; a = 08h (interrupt 1 hits here: a = a + 07h)
adi 1H ; a = 09h
adi 1H ; a = 0ah
adi 1H ; a = 0bh
adi 1H ; a = 0ch (interrupt 2 hits here: c = 0ch)
adi 1H ; a = 0dh
adi 1H ; a = 0eh
ei
adi 1H ; a = 0fh
adi 1H ; a = 10h
adi 1H ; a = 11h
ei
hlt ; (interrupt 3 hits when in halt: nop )
cpi 11h
jnz fail
mov a,b
cpi 0
jnz fail
mov a,c
cpi 0ch
jnz fail
mov a,d
cpi 12h
mov a,e
cpi 34h
jnz fail
mvi a,55h
hlt
fail: mvi a,0aah
hlt
org 100H
adi 9h
mvi b,77h
ei
ret
; data space
ds 256
stack: dw 0
/trunk/asm/TB0.HEX
0,0 → 1,81
:1000000031EF053E77E600CA0D00CDE004D21300C3
:10001000CDE004EA1900CDE004F21F00CDE004C2F7
:100020002E00DA2E00E22E00FA2E00C33100CDE0C1
:1000300004C606C23900CDE004DA4200E24200F212
:100040004500CDE004C670E24D00CDE004FA560054
:10005000CA5600D25900CDE004C681FA6100CDE055
:1000600004CA6A00DA6A00E26D00CDE004C6FEDA76
:100070007500CDE004CA7E00E27E00FA8100CDE08A
:1000800004FE00DA9900CA9900FEF5DA9900C299D7
:1000900000FEFFCA9900DA9C00CDE004CE0ACE0A29
:1000A000FE0BCAA800CDE004D60CD60FFEF0CAB4F1
:1000B00000CDE004DEF1DE0EFEF0CAC000CDE004AB
:1000C000E655FE50CACA00CDE004F63AFE7ACAD41C
:1000D00000CDE004EE0FFE75CADE00CDE004E600C0
:1000E000DCE004E4E004FCE004C4E004FE00CAF444
:1000F00000CDE004D677D4E004ECE004F4E004CCD6
:10010000E004FE89CA0A01CDE004E6FFE41701FE1F
:10011000D9CA7401CDE004E8C610EC2301C602E0A0
:10012000CDE004E0C620FC2F01C604E8CDE004F0D9
:10013000C680F43B01C680F8CDE004F8C640D44741
:1001400001C640F0CDE004D8C68FDC5301D602D002
:10015000CDE004D0C6F7C45F01C6FED8CDE004C828
:10016000C601CC6B01C6D0C0CDE004C0C647FE4777
:10017000C8CDE0043E773C4704480D515A636C7D7E
:100180003D4F596B4550627C57146A4D0C614405D4
:10019000587B5F1C4360244C6955157A672554428F
:1001A000682C5D1D4B796F2D655C534A4178FE7755
:1001B000C4E004AF06010E0316071E0F261F2E3FD4
:1001C00080818283848587FEF0C4E00490919293BD
:1001D0009495FE78C4E00497C4E0043E808706014D
:1001E0000E0216031E0426052E06880680808089CE
:1001F00080808A80808B80808C80808D80808FFE44
:1002000037C4E0043E808706019806FF8099809AF3
:10021000809B809C809DFEE0C4E0043E80879FFE22
:10022000FFC4E0043EFF06FE0EFC16EF1E7F26F420
:100230002EBFA7A1A2A3A4A5A7FE24C4E004AF06D5
:10024000010E0216041E0826102E20B0B1B2B3B45F
:10025000B5B7FE3FC4E0043E00268F2E4FA8A9AAE2
:10026000ABACADFECFC4E004AFC4E00406440E4521
:1002700016461E4726042EE8700600463E44B8C4C3
:10028000E004721600563E46BAC4E004731E005ED7
:100290003E47BBC4E0047426042EE8663E04BCC49A
:1002A000E0047526042EE86E3EE8BDC4E004260492
:1002B0002EE83E3277BEC4E00486FE64C4E004AF9C
:1002C0007EFE32C4E00426042EE87E96C4E0043E9E
:1002D00080878EFE33C4E0043E80879EFECDC4E05E
:1002E00004A6C4E0043E25B6FE37C4E004AEFE0515
:1002F000C4E0043655343586FE5AC4E00401FF12CA
:1003000011FF1221FF120313233E13B8C4E004BAF5
:10031000C4E004BCC4E0043E00B9C4E004BBC4E0D3
:1003200004BDC4E0040B1B2B3E12B8C4E004BAC4E5
:10033000E004BCC4E0043EFFB9C4E004BBC4E00474
:10034000BDC4E00432E804AF3AE804FEFFC4E004B0
:100350002AE60422E8043AE604473AE804B8C4E08E
:10036000043AE704473AE904B8C4E0043EAA32E894
:1003700004444DAF0AFEAAC4E0043C023AE804FE7D
:10038000ABC4E0043E7732E8042AE604110000EB37
:10039000AF1AFE77C4E004AF8485C4E0043ECC12FB
:1003A0003AE804FECC123AE804FECCC4E00421771B
:1003B00077293EEEBCC4E004BDC4E00421555501DC
:1003C000FFFF093E55D4E004BCC4E0043E54BDC464
:1003D000E00421AAAA113333193EDDBCC4E004BDF8
:1003E000C4E00437D4E0043FDCE0043EAA2FFE550D
:1003F000C4E004B727FE55C4E0043E888727FE7694
:10040000C4E004AF3EAA27D4E004FE10C4E004AF69
:100410003E9A27D4E004C4E004373E4207DCE004FF
:1004200007D4E004FE09C4E0040FD4E0040FFE4248
:10043000C4E0041717D4E004FE08C4E0041F1FDC66
:10044000E004FE02C4E00401341211AAAA215555A9
:10045000AFC5D5E5F50100001100002100003EC048
:10046000C6F0F1E1D1C1DCE004C4E004E4E004FC46
:10047000E0043E12B8C4E0043E34B9C4E0043EAA2D
:10048000BAC4E004BBC4E0043E55BCC4E004BDC42F
:10049000E0042100003922ED0431EC043B3B333B06
:1004A0003E5532EA042F32EB04C1B8C4E0042FB940
:1004B000C4E00421EC04F92133773B3BE33AEB043D
:1004C000FE77C4E0043AEA04FE33C4E0043E55BDBE
:1004D000C4E0042FBCC4E0042AED04F921E304E9DC
:0804E0003EAA763E5576E804C1
:0205EF0000000A
:0000000000
/trunk/asm/TB1.HEX
0,0 → 1,10
:03000000C34000FA
:04002000C607FBC94B
:0200280047C9C6
:10004000310602FB3E00EFC601C601C601C601C66D
:1000500001C601C601FBC601C601C601FB76FE1141
:10006000C27B0078FE00C27B0079FE0CC27B007A66
:0E007000FE127BFE34C27B003E55763EAA7621
:06010000C6090677FBC9E9
:020206000000F6
:0000000000
/trunk/doc/IMSAI SCS-1 Manual.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/IMSAI SCS-1 Manual.pdf
trunk/doc/IMSAI SCS-1 Manual.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/designNotes.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/designNotes.odt =================================================================== --- trunk/doc/designNotes.odt (nonexistent) +++ trunk/doc/designNotes.odt (revision 2)
trunk/doc/designNotes.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/designNotes.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/designNotes.pdf =================================================================== --- trunk/doc/designNotes.pdf (nonexistent) +++ trunk/doc/designNotes.pdf (revision 2)
trunk/doc/designNotes.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/synthesis/tb0_modelsim_wave.do =================================================================== --- trunk/synthesis/tb0_modelsim_wave.do (nonexistent) +++ trunk/synthesis/tb0_modelsim_wave.do (revision 2) @@ -0,0 +1,63 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(14) &rbank(15) )} SP +quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(8) &rbank(9) )} PC004 +quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(0) &rbank(1) )} BC +quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(2) &rbank(3) )} DE +quietly virtual signal -install /light8080_tb0/uut { (context /light8080_tb0/uut )(rbank(4) &rbank(5) )} HL +add wave -noupdate -format Logic /light8080_tb0/clk +add wave -noupdate -format Logic /light8080_tb0/halt_o +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/data_i +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/data_o +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/addr_o +add wave -noupdate -format Logic /light8080_tb0/vma_o +add wave -noupdate -format Logic /light8080_tb0/rd_o +add wave -noupdate -format Logic /light8080_tb0/wr_o +add wave -noupdate -color {Medium Slate Blue} -format Literal -label SP -radix hexadecimal /light8080_tb0/uut/SP +add wave -noupdate -color {Indian Red} -format Literal -label PC -radix hexadecimal /light8080_tb0/uut/PC004 +add wave -noupdate -color Yellow -format Literal -itemcolor Yellow -label PSW -radix binary /light8080_tb0/uut/flag_reg +add wave -noupdate -color {Dark Green} -format Literal -label ACC -radix hexadecimal /light8080_tb0/uut/rbank(7) +add wave -noupdate -color Pink -format Literal -itemcolor Pink -label BC -radix hexadecimal /light8080_tb0/uut/BC +add wave -noupdate -color {Indian Red} -format Literal -itemcolor {Indian Red} -label DE -radix hexadecimal /light8080_tb0/uut/DE +add wave -noupdate -color {Yellow Green} -format Literal -itemcolor {Yellow Green} -label HL -radix hexadecimal /light8080_tb0/uut/HL +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/rbank_data +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/rbank_rd_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/rbank_wr_addr +add wave -noupdate -format Logic /light8080_tb0/uut/we_rb +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/uc_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/next_uc_addr +add wave -noupdate -format Literal /light8080_tb0/uut/uc_addr_sel +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/uc_jmp_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/uc_ret_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/t1 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/t2 +add wave -noupdate -format Literal /light8080_tb0/uut/uc_flags1 +add wave -noupdate -format Literal /light8080_tb0/uut/uc_flags2 +add wave -noupdate -format Literal /light8080_tb0/uut/rb_addr_sel +add wave -noupdate -format Logic /light8080_tb0/uut/cy_in +add wave -noupdate -format Logic /light8080_tb0/uut/cy_in_sgn +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/alu_output +add wave -noupdate -format Literal /light8080_tb0/uut/alu_fn +add wave -noupdate -format Literal /light8080_tb0/uut/mux_fn +add wave -noupdate -format Logic /light8080_tb0/uut/use_logic +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/arith_op1 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/arith_op2 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/arith_op2_sgn +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/arith_res8 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb0/uut/arith_res +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {351700000 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 70 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {369173243 ps} {370911916 ps} Index: trunk/synthesis/tb1_modelsim_wave.do =================================================================== --- trunk/synthesis/tb1_modelsim_wave.do (nonexistent) +++ trunk/synthesis/tb1_modelsim_wave.do (revision 2) @@ -0,0 +1,67 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(14) &rbank(15) )} SP +quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(8) &rbank(9) )} PC004 +quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(0) &rbank(1) )} BC +quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(2) &rbank(3) )} DE +quietly virtual signal -install /light8080_tb1/uut { (context /light8080_tb1/uut )(rbank(4) &rbank(5) )} HL +add wave -noupdate -format Logic /light8080_tb1/clk +add wave -noupdate -format Logic /light8080_tb1/reset +add wave -noupdate -format Logic /light8080_tb1/halt_o +add wave -noupdate -format Logic /light8080_tb1/inte_o +add wave -noupdate -format Logic /light8080_tb1/intr_i +add wave -noupdate -format Logic /light8080_tb1/inta_o +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/data_i +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/data_o +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/addr_o +add wave -noupdate -format Logic /light8080_tb1/vma_o +add wave -noupdate -format Logic /light8080_tb1/rd_o +add wave -noupdate -format Logic /light8080_tb1/wr_o +add wave -noupdate -color {Medium Slate Blue} -format Literal -label SP -radix hexadecimal /light8080_tb1/uut/SP +add wave -noupdate -color {Indian Red} -format Literal -label PC -radix hexadecimal /light8080_tb1/uut/PC004 +add wave -noupdate -color Yellow -format Literal -itemcolor Yellow -label PSW -radix binary /light8080_tb1/uut/flag_reg +add wave -noupdate -color {Dark Green} -format Literal -label ACC -radix hexadecimal /light8080_tb1/uut/rbank(7) +add wave -noupdate -color Pink -format Literal -itemcolor Pink -label BC -radix hexadecimal /light8080_tb1/uut/BC +add wave -noupdate -color {Indian Red} -format Literal -itemcolor {Indian Red} -label DE -radix hexadecimal /light8080_tb1/uut/DE +add wave -noupdate -color {Yellow Green} -format Literal -itemcolor {Yellow Green} -label HL -radix hexadecimal /light8080_tb1/uut/HL +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/rbank_data +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/rbank_rd_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/rbank_wr_addr +add wave -noupdate -format Logic /light8080_tb1/uut/we_rb +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/uc_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/next_uc_addr +add wave -noupdate -format Literal /light8080_tb1/uut/uc_addr_sel +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/uc_jmp_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/uc_ret_addr +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/t1 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/t2 +add wave -noupdate -format Literal /light8080_tb1/uut/uc_flags1 +add wave -noupdate -format Literal /light8080_tb1/uut/uc_flags2 +add wave -noupdate -format Literal /light8080_tb1/uut/rb_addr_sel +add wave -noupdate -format Logic /light8080_tb1/uut/cy_in +add wave -noupdate -format Logic /light8080_tb1/uut/cy_in_sgn +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/alu_output +add wave -noupdate -format Literal /light8080_tb1/uut/alu_fn +add wave -noupdate -format Literal /light8080_tb1/uut/mux_fn +add wave -noupdate -format Logic /light8080_tb1/uut/use_logic +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/arith_op1 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/arith_op2 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/arith_op2_sgn +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/arith_res8 +add wave -noupdate -format Literal -radix hexadecimal /light8080_tb1/uut/arith_res +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {4800000 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 70 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {9925222 ps} {11653546 ps} Index: trunk/readme.txt =================================================================== --- trunk/readme.txt (nonexistent) +++ trunk/readme.txt (revision 2) @@ -0,0 +1,42 @@ +I have included the original documentation for the SCS-1 monitor program used +in the core demo, because it is quite difficult to find in the internet. + +The test and demo programs have been assembled with CP/M's ASM, running on the +SIMH 8080/Z80 emulator available at http://simh.trailing-edge.com. +CP/M software and disk images are available in the above site and elsewhere +on the internet. + + +FILE LIST +========== + +vhdl\light8080.vhdl Core source (single file) + +vhdl\test\light8080_tb0.vhdl Test bench 0 (Kelly test) +vhdl\test\light8080_tb1.vhdl Test bench 1 (Interrupts) + +vhdl\demo\cs2b_light8080_demo.vhd Demo for Cyclone 2 starter board +vhdl\demo\rs232_tx.vhdl Serial tx code for demo +vhdl\demo\rs232_rx.vhdl Serial rx code for demo +vhdl\demo\cs2b_demo.csv Pin assignment file for Quartus II + +util\uasm.pl Microcode assembler +util\hexconv.pl Intel HEX to VHDL converter +util\microrom.bat Sample DOS bat file for assembler + +ucode\light8080.m80 Microcode source file + +synthesis\tb0_modelsim_wave.do Modelsim macro for test bench 0 +synthesis\tb1_modelsim_wave.do Modelsim macro for test bench 1 + +doc\designNotes.odt Core documentation in OpenOffice format +doc\designNotes.pdf Core documentation in PDF format +doc\IMSAI SCS-1 Manual.pdf IMSAI SCS-1 original documentation + +asm\tb0.asm Test bench 0 program assembler source +asm\TB0.PRN Listing generated by CP/M ASM +asm\TB0.HEX Object code generated by CP/M ASM +asm\tb1.asm Test bench 1 program assembler source +asm\TB1.PRN Listing generated by CP/M ASM +asm\TB1.HEX Object code generated by CP/M ASM + \ No newline at end of file Index: trunk/util/uasm.pl =================================================================== --- trunk/util/uasm.pl (nonexistent) +++ trunk/util/uasm.pl (revision 2) @@ -0,0 +1,892 @@ +################################################################################ +# uasm.pl : light8080 core microcode assembler +################################################################################ +# Usage: perl uasm.pl +# +# The command list is a space-separated sequence of the following: +# +# -lst : Shows a listing of the assembled microinstructions next to their +# assembler source lines. Not very useful because it does not show +# assembler pragma, label or comment lines. +# -labels : Shows a list of all defined labels with their address and the +# number of times they are used. +# -bitfields: Shows a list of all the different microinstructions generated, +# plus the number of times they are used. Might be useful to encode +# the microinstructions and save rom bits. +# -instructions: Shows a list of all defined instructions with the address their +# microcode starts at. +# -rom_bin : Shows a raw list of all the binary microinstructions. +# -rom_vhdl : Shows a vhdl block containing the microcode rom declaration. +# +# If none of the above commands is given, the program just exits silently. Any +# unrecognized command is silently ignored. +################################################################################ +# Assembler format (informal definition, source is the ultimate reference!): +# +# := +# [

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