Subversion Repositories md5

/trunk/hash_core.v

trunk/hash_core.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/md5_padding.v =================================================================== --- trunk/md5_padding.v (nonexistent) +++ trunk/md5_padding.v (revision 2) @@ -0,0 +1,270 @@ +/******************************************************************************** +* Module : md5_padding +* Description: md5 Padding block +* +******************************************************************************** +* Esencia Technology Proprietary and Confidential +* All rights reserved (c) 2005 by Esencia Technolgy +********************************************************************************/ + + +module md5_padding ( + + //Inputs + clk, + rst_n, + DataVld, + InitVec, + DataIn, + DataFirst, + DataLast, + DataNumb, + RoundNum, + + //Outputs + DataBusy, + Md5DataIn, + Md5DataVld, + Md5StateAIn, + Md5StateBIn, + Md5StateCIn, + Md5StateDIn, + Md5StateVld + ); + +`include "md5_params.vh" +`include "ah_params.vh" +`include "md5_func.vh" + +input clk; +input rst_n; +input DataVld; // Valid flag for Data or InitVec +input [DATA_WIDTH - 1:0] DataIn; // 32 bit DataIn or Initvect +input DataFirst; // First chunk +input DataLast; // Last chunk of data +input [5:0] DataNumb; // Number of valid bits in + // last chuck of data +input [5:0] RoundNum; +input InitVec; // Inidicate Init Vector + +output Md5DataVld; +output [DATA_WIDTH - 1:0] Md5DataIn; +output Md5StateVld; +output [STATE_DWIDTH - 1:0] Md5StateAIn; +output [STATE_DWIDTH - 1:0] Md5StateBIn; +output [STATE_DWIDTH - 1:0] Md5StateCIn; +output [STATE_DWIDTH - 1:0] Md5StateDIn; +output DataBusy; + +reg [3:0] DinCntReg; +reg [3:0] DinCnt; +reg [63:0] PktLength; +wire [63:0] PktLengthBigEnd; + +reg Md5DataVld; +reg Md5DataVldTemp; +reg [DATA_WIDTH - 1:0] Md5DataIn; +reg [DATA_WIDTH - 1:0] Md5DataInTemp; +reg Md5StateVld; +reg [STATE_DWIDTH - 1:0] Md5StateAIn; +reg [STATE_DWIDTH - 1:0] Md5StateBIn; +reg [STATE_DWIDTH - 1:0] Md5StateCIn; +reg [STATE_DWIDTH - 1:0] Md5StateDIn; + +reg [1:0] InitVecCnt; +reg PktEnded; +wire DataBusy; +wire [8:0] PktLengthMod; +reg [2:0] SendDataCur; +reg [2:0] SendDataNxt; +reg Pad1Nxt; // Indicate to pad 1 + // in Next data cycle +reg Pad1NxtReg; +reg Send4SecRnd; +reg Send4SecRndReg; + +assign PktLengthMod = PktLength[8:0]; //PktLength % 512 + +assign DataBusy = PktEnded || (RoundNum > 14) || (SendDataCur == 4) || + (SendDataCur == 5) || (SendDataCur == 6); + +assign PktLengthBigEnd = {PktLength[7:0], PktLength[15:8], PktLength[23:16], + PktLength[31:24], PktLength[39:32], PktLength[47:40], + PktLength[55:48], PktLength[63:56]}; + + +// Send State Value incase of InitVec + +always @(posedge clk or negedge rst_n) begin + if (~rst_n) begin + InitVecCnt <= 3'b0; + Md5StateVld <= 1'b0; + end + else begin + InitVecCnt <= InitVec ? (InitVecCnt == 3) ? 0 : + InitVecCnt + 1 : InitVecCnt; + Md5StateVld <= (InitVecCnt == 3) && InitVec; + end +end + +always @(posedge clk) begin + if (InitVec) begin + case (InitVecCnt) + 3'b000 : begin + Md5StateAIn <= DataIn; + end + 3'b001 : begin + Md5StateBIn <= DataIn; + end + 3'b010 : begin + Md5StateCIn <= DataIn; + end + 3'b011 : begin + Md5StateDIn <= DataIn; + end + endcase + end +end + +// Start Collecting 512 byte (32x16 cycle) +// +always @(posedge clk or negedge rst_n) begin + if (~rst_n) begin + DinCntReg <= 4'b0; + PktLength <= 64'b0; + PktEnded <= 1'b0; + SendDataCur <= 2'b0; + Pad1NxtReg <= 1'b0; + Send4SecRndReg <= 1'b0; + end + else begin + SendDataCur <= SendDataNxt; + Send4SecRndReg <= Send4SecRnd; + Pad1NxtReg <= Pad1Nxt; + PktEnded <= (DinCntReg == 15) ? 1'b0 : DataLast ? + 1'b1 : PktEnded; + DinCntReg <= DinCnt; + if (DataVld) begin + if (DataFirst) begin + PktLength <= DataLast ? DataNumb : 32; + end + else begin + PktLength <= DataLast ? PktLength + DataNumb : + PktLength + 32; + end + end + end +end + +// Data Send FSM to CORE +parameter IDLE = 0; +parameter SEND_DATA = 1; +parameter SECOND_ROUND_CHK0 = 2; +parameter SECOND_ROUND_CHK1 = 3; +parameter WAIT = 4; +parameter WAIT2 = 5; +parameter SECOND_ROUND = 6; + +always @(SendDataCur or PktEnded or DinCntReg + or DataVld or DataLast or DataNumb or + Pad1NxtReg or Send4SecRndReg or RoundNum or + DataIn or PktLengthBigEnd ) begin + Md5DataVldTemp = 1'b0; + Md5DataInTemp = 32'b0; + Pad1Nxt = 1'b0; + Send4SecRnd = 1'b0; + SendDataNxt = 3'b0; + DinCnt = 4'b0; + case (SendDataCur) + IDLE : begin + if (DataVld) begin + SendDataNxt = SEND_DATA; + Md5DataInTemp = DataLast ? PadData(DataNumb, DataIn) : DataIn; + Md5DataVldTemp = 1'b1; + Pad1Nxt = DataLast && (DataNumb == 32); + DinCnt = 0; + end + end + SEND_DATA : begin + DinCnt = DinCntReg + 1; + Md5DataVldTemp = 1'b1; + Pad1Nxt = DataLast && (DataNumb == 32); + SendDataNxt = (DinCntReg < 12) ? SEND_DATA : SECOND_ROUND_CHK0; + Md5DataInTemp = Pad1NxtReg ? 32'h80000000 : DataLast ? PadData(DataNumb, DataIn) : PktEnded ? + 32'b0 : DataIn; + end + SECOND_ROUND_CHK0 : begin + DinCnt = DinCntReg + 1; + Md5DataVldTemp = 1'b1; + SendDataNxt = SECOND_ROUND_CHK1; + Send4SecRnd = DataLast || Pad1NxtReg; + Pad1Nxt = DataLast && (DataNumb == 32); + if (DataLast) begin + Md5DataInTemp = PadData(DataNumb, DataIn); + end + else begin + Md5DataInTemp = Pad1NxtReg ? 32'h80000000 : + PktEnded ? PktLengthBigEnd[63:32] : DataIn; + end + end + SECOND_ROUND_CHK1 : begin + DinCnt = DinCntReg + 1; + Md5DataVldTemp = 1'b1; + SendDataNxt = (Send4SecRndReg || DataLast) ? WAIT : IDLE; + Pad1Nxt = DataLast && (DataNumb == 32); + if (DataLast) begin + Md5DataInTemp = PadData(DataNumb, DataIn); + end + else begin + Md5DataInTemp = Pad1NxtReg ? 32'h80000000 : + PktEnded ? Send4SecRndReg ? 32'b0 : + PktLengthBigEnd[31:0] : DataIn; + end + end + WAIT : begin + DinCnt = 0; + Md5DataVldTemp = 1'b0; + Pad1Nxt = Pad1NxtReg; + SendDataNxt = (RoundNum == 63) ? WAIT2 : WAIT; + end + WAIT2 : begin + DinCnt = 0; + SendDataNxt = SECOND_ROUND; + Pad1Nxt = Pad1NxtReg; + Md5DataVldTemp = 1'b0; + end + SECOND_ROUND : begin + DinCnt = DinCntReg + 1; + Pad1Nxt = (DinCntReg == 0) ? Pad1NxtReg : 1'b0; + Md5DataVldTemp = (DinCntReg <= 15); + SendDataNxt = (DinCntReg == 15) ? IDLE : SECOND_ROUND; + if (DinCntReg < 14) begin + Md5DataInTemp = Pad1Nxt ? 32'h80000000 : 32'b0; + end + else begin + Md5DataInTemp = (DinCntReg == 14) ? PktLengthBigEnd[63:32] : + PktLengthBigEnd[31:0]; + end + end + default : begin + Md5DataVldTemp = 1'b0; + Md5DataInTemp = 32'b0; + Pad1Nxt = 1'b0; + Send4SecRnd = 1'b0; + DinCnt = 4'b0; + end + endcase +end + +// Send Pkt Data 512 byte with padding +always @(posedge clk or negedge rst_n) begin + if (~rst_n) begin + Md5DataVld <= 1'b0; + Md5DataIn <= 32'b0; + end + else begin + Md5DataVld <= Md5DataVldTemp; + Md5DataIn <= Md5DataInTemp; + end +end +endmodule

trunk/md5_padding.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/add32.v =================================================================== --- trunk/add32.v (nonexistent) +++ trunk/add32.v (revision 2) @@ -0,0 +1,23 @@ +/******************************************************* +* 32 bit Adder +* +*******************************************************/ + + +module add32 ( + In0, + In1, + Out + ); + +input [31:0] In0; +input [31:0] In1; + +output [31:0] Out; + +wire [31:0] Out; + +assign Out[31:0] = In0 + In1; + +endmodule +

trunk/add32.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/es1005.v =================================================================== --- trunk/es1005.v (nonexistent) +++ trunk/es1005.v (revision 2) @@ -0,0 +1,95 @@ +/******************************************************************************** +* Module : es1005 +* Description: MD5 Top level +* +******************************************************************************** +* Esencia Technology Proprietary and Confidential +* All rights reserved (c) 2005 by Esencia Technolgy +********************************************************************************/ + + +module es1005 ( + + //Inputs + clk, + rst_n, + DataVld, + DataIn, + DataFirst, + DataLast, + DataNumb, + InitVec, + + //Outputs + MsgDgstVld, + MsgDigest, + DataBusy + ); + +`include "md5_params.vh" +`include "ah_params.vh" + +input clk; +input rst_n; +input DataVld; // Valid flag for Data or InitVec +input [DATA_WIDTH - 1:0] DataIn; // 32 bit DataIn or Initvect +input DataFirst; // First chunk +input DataLast; // Last chunk of data +input [5:0] DataNumb; // Number of valid bits in + // last chuck of data +input InitVec; // Inidicate Init Vector + +output MsgDgstVld; +output [DATA_WIDTH -1:0] MsgDigest; +output DataBusy; // Inidicate core is busy + +wire MsgDgstVld; +wire DataBusy; +wire [DATA_WIDTH -1:0] MsgDigest; +wire Md5DataVld; +wire [DATA_WIDTH - 1:0] Md5DataIn; +wire Md5StateVld; +wire [STATE_DWIDTH - 1:0] Md5StateAIn; +wire [STATE_DWIDTH - 1:0] Md5StateBIn; +wire [STATE_DWIDTH - 1:0] Md5StateCIn; +wire [STATE_DWIDTH - 1:0] Md5StateDIn; +wire [5:0] RoundNum; + +hash_core u_hash_core ( + + .clk(clk), + .rst_n(rst_n), + .dataIn(Md5DataIn), + .dataVld(Md5DataVld), + .stateVld(Md5StateVld), + .stateAIn(Md5StateAIn), + .stateBIn(Md5StateBIn), + .stateCIn(Md5StateCIn), + .stateDIn(Md5StateDIn), + .RoundNum(RoundNum), + .msgDgstVld(MsgDgstVld), + .msgDigest(MsgDigest) + ); + +md5_padding u_md5_padding ( + + .clk(clk), + .rst_n(rst_n), + .DataVld(DataVld), + .DataIn(DataIn), + .DataFirst(DataFirst), + .DataLast(DataLast), + .DataNumb(DataNumb), + .InitVec(InitVec), + .RoundNum(RoundNum), + .DataBusy(DataBusy), + .Md5DataIn(Md5DataIn), + .Md5DataVld(Md5DataVld), + .Md5StateAIn(Md5StateAIn), + .Md5StateBIn(Md5StateBIn), + .Md5StateCIn(Md5StateCIn), + .Md5StateDIn(Md5StateDIn), + .Md5StateVld(Md5StateVld) + ); + +endmodule

trunk/es1005.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/hash_misc.v =================================================================== --- trunk/hash_misc.v (nonexistent) +++ trunk/hash_misc.v (revision 2) @@ -0,0 +1,99 @@ +/******************************************************************************** +* Multiplex-demultiplex logic +********************************************************************************/ + + +module hash_misc ( + + //Inputs + Md5MsgDgstVld, + Md5DataVld, + Md5DataIn, + + Md5StateAComb, + Md5StateBComb, + Md5StateCComb, + Md5StateDComb, + + Md5Addend0A, + Md5Addend0B, + Md5Addend1A, + Md5Addend1B, + + //Output + + msgDgstVld, + MuxedDataVld, + MuxedDataIn, + + MuxedStateAComb, + MuxedStateBComb, + MuxedStateCComb, + MuxedStateDComb, + MuxedStateEComb, + MuxedAddend0A, + MuxedAddend0B, + MuxedAddend1A, + MuxedAddend1B + + ); + +`include "ah_params.vh" +`include "md5_params.vh" + +input Md5DataVld; +input [DATA_WIDTH - 1 :0] Md5DataIn; +input Md5MsgDgstVld; + +input [STATE_DWIDTH - 1:0] Md5StateAComb; +input [STATE_DWIDTH - 1:0] Md5StateBComb; +input [STATE_DWIDTH - 1:0] Md5StateCComb; +input [STATE_DWIDTH - 1:0] Md5StateDComb; + +input [STATE_DWIDTH - 1:0] Md5Addend0A; +input [STATE_DWIDTH - 1:0] Md5Addend0B; +input [STATE_DWIDTH - 1:0] Md5Addend1A; +input [STATE_DWIDTH - 1:0] Md5Addend1B; + +output msgDgstVld; +output [DATA_WIDTH - 1:0] MuxedDataIn; +output MuxedDataVld; +output [STATE_DWIDTH -1:0] MuxedStateAComb; +output [STATE_DWIDTH -1:0] MuxedStateBComb; +output [STATE_DWIDTH -1:0] MuxedStateCComb; +output [STATE_DWIDTH -1:0] MuxedStateDComb; +output [STATE_DWIDTH -1:0] MuxedStateEComb; +output [STATE_DWIDTH - 1:0] MuxedAddend0A; +output [STATE_DWIDTH - 1:0] MuxedAddend0B; +output [STATE_DWIDTH - 1:0] MuxedAddend1A; +output [STATE_DWIDTH - 1:0] MuxedAddend1B; + +wire msgDgstVld; +wire [DATA_WIDTH - 1:0] MuxedDataIn; +wire MuxedDataVld; +wire [STATE_DWIDTH -1:0] MuxedStateAComb; +wire [STATE_DWIDTH -1:0] MuxedStateBComb; +wire [STATE_DWIDTH -1:0] MuxedStateCComb; +wire [STATE_DWIDTH -1:0] MuxedStateDComb; +wire [STATE_DWIDTH -1:0] MuxedStateEComb; +wire [STATE_DWIDTH - 1:0] MuxedAddend0A; +wire [STATE_DWIDTH - 1:0] MuxedAddend0B; +wire [STATE_DWIDTH - 1:0] MuxedAddend1A; +wire [STATE_DWIDTH - 1:0] MuxedAddend1B; + +assign msgDgstVld = Md5MsgDgstVld; +assign MuxedDataIn = Md5DataIn; +assign MuxedDataVld = Md5DataVld; + +assign MuxedStateAComb = Md5StateAComb; +assign MuxedStateBComb = Md5StateBComb; +assign MuxedStateCComb = Md5StateCComb; +assign MuxedStateDComb = Md5StateDComb; +assign MuxedStateEComb = 32'b0; + +assign MuxedAddend0A = Md5Addend0A; +assign MuxedAddend0B = Md5Addend0B; +assign MuxedAddend1A = Md5Addend1A; +assign MuxedAddend1B = Md5Addend1B; + +endmodule

trunk/hash_misc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/adders.v =================================================================== --- trunk/adders.v (nonexistent) +++ trunk/adders.v (revision 2) @@ -0,0 +1,131 @@ +/**************************************************************************** + Adders +****************************************************************************/ + +module adders ( + + //Inputs + Addend0A, + Addend0B, + Addend1A, + Addend1B, + Addend2A, + Addend3A, + Addend3B, + StateAReg, + StateBReg, + StateCReg, + StateDReg, + A_Reg, + B_Reg, + C_Reg, + D_Reg, + + //Outputs + ResStateAReg, + ResStateBReg, + ResStateCReg, + ResStateDReg, + AddResFinal1, + AddResFinal2, + AddResFinal3 + ); + +`include "ah_params.vh" + +input [STATE_DWIDTH - 1:0] Addend0A; +input [STATE_DWIDTH - 1:0] Addend0B; +input [STATE_DWIDTH - 1:0] Addend1A; +input [STATE_DWIDTH - 1:0] Addend1B; +input [STATE_DWIDTH - 1:0] Addend2A; +input [STATE_DWIDTH - 1:0] Addend3A; +input [STATE_DWIDTH - 1:0] Addend3B; +input [STATE_DWIDTH - 1:0] StateAReg; +input [STATE_DWIDTH - 1:0] StateBReg; +input [STATE_DWIDTH - 1:0] StateCReg; +input [STATE_DWIDTH - 1:0] StateDReg; +input [STATE_DWIDTH - 1:0] A_Reg; +input [STATE_DWIDTH - 1:0] B_Reg; +input [STATE_DWIDTH - 1:0] C_Reg; +input [STATE_DWIDTH - 1:0] D_Reg; + +output [STATE_DWIDTH - 1:0] ResStateAReg; +output [STATE_DWIDTH - 1:0] ResStateBReg; +output [STATE_DWIDTH - 1:0] ResStateCReg; +output [STATE_DWIDTH - 1:0] ResStateDReg; +output [STATE_DWIDTH - 1:0] AddResFinal1; +output [STATE_DWIDTH - 1:0] AddResFinal2; +output [STATE_DWIDTH - 1:0] AddResFinal3; + +wire [STATE_DWIDTH - 1:0] AddResFinal1; +wire [STATE_DWIDTH - 1:0] AddResFinal2; +wire [STATE_DWIDTH - 1:0] AddResFinal3; +wire [STATE_DWIDTH - 1:0] AddRes0; +wire [STATE_DWIDTH - 1:0] AddRes1; +wire [STATE_DWIDTH - 1:0] AddRes2; +wire [STATE_DWIDTH - 1:0] AddRes3; +wire [STATE_DWIDTH - 1:0] AddRes4; +wire [STATE_DWIDTH - 1:0] ResStateAReg; +wire [STATE_DWIDTH - 1:0] ResStateBReg; +wire [STATE_DWIDTH - 1:0] ResStateCReg; +wire [STATE_DWIDTH - 1:0] ResStateDReg; + +assign AddResFinal1 = AddRes2; +assign AddResFinal2 = AddRes3; +assign AddResFinal3 = AddRes4; + +add32 u_adder_0 ( + .In0(Addend0A), + .In1(Addend0B), + .Out(AddRes0) + ); + +add32 u_adder_1 ( + .In0(Addend1A), + .In1(Addend1B), + .Out(AddRes1) + ); + +add32 u_adder_2 ( + .In0(AddRes1), + .In1(AddRes0), + .Out(AddRes2) + ); + +add32 u_adder_3 ( + .In0(Addend2A), + .In1(AddRes2), + .Out(AddRes3) + ); + +add32 u_adder_9 ( + .In0(Addend3A), + .In1(Addend3B), + .Out(AddRes4) + ); + +add32 u_adder_4 ( + .In0(StateAReg), + .In1(A_Reg), + .Out(ResStateAReg) + ); + +add32 u_adder_5 ( + .In0(StateBReg), + .In1(B_Reg), + .Out(ResStateBReg) + ); + +add32 u_adder_6 ( + .In0(StateCReg), + .In1(C_Reg), + .Out(ResStateCReg) + ); + +add32 u_adder_7 ( + .In0(StateDReg), + .In1(D_Reg), + .Out(ResStateDReg) + ); + +endmodule

trunk/adders.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/md5_comb.v =================================================================== --- trunk/md5_comb.v (nonexistent) +++ trunk/md5_comb.v (revision 2) @@ -0,0 +1,551 @@ +/******************************************************************************** +* Module Name : md5_comb +* Description : MD5 computation combologic +* +* +* *******************************************************************************/ + +module md5_comb ( + + //Inputs + RoundNum, + StateAReg, + StateBReg, + StateCReg, + StateDReg, + DataVld, + DataIn, + BlockIn, + AddRes1, + AddRes2, + + //Outputs + Md5FuncValue, + TValue, + XValue, + StateAComb, + StateBComb, + StateCComb, + StateDComb, + AddendState1, + AddendState2, + ShiftedAddend + + ); + +`include "ah_params.vh" +`include "md5_params.vh" +`include "md5_func.vh" +input [5:0] RoundNum; +input [STATE_DWIDTH - 1:0] StateAReg; +input [STATE_DWIDTH - 1:0] StateBReg; +input [STATE_DWIDTH - 1:0] StateCReg; +input [STATE_DWIDTH - 1:0] StateDReg; +input [BLOCK_SIZE - 1:0] BlockIn; +input [DATA_WIDTH - 1:0] DataIn; +input DataVld; +input [STATE_DWIDTH - 1:0] AddRes1; +input [STATE_DWIDTH - 1:0] AddRes2; + +output [STATE_DWIDTH - 1:0] Md5FuncValue; +output [STATE_DWIDTH - 1:0] TValue; +output [STATE_DWIDTH - 1:0] XValue; +output [STATE_DWIDTH - 1:0] StateAComb; +output [STATE_DWIDTH - 1:0] StateBComb; +output [STATE_DWIDTH - 1:0] StateCComb; +output [STATE_DWIDTH - 1:0] StateDComb; +output [STATE_DWIDTH - 1:0] AddendState1; +output [STATE_DWIDTH - 1:0] AddendState2; +output [STATE_DWIDTH - 1:0] ShiftedAddend; + +reg [STATE_DWIDTH - 1:0] Md5FuncValue; +reg [STATE_DWIDTH - 1:0] TValue; +reg [STATE_DWIDTH - 1:0] XValue; +reg [STATE_DWIDTH - 1:0] StateAComb; +reg [STATE_DWIDTH - 1:0] StateBComb; +reg [STATE_DWIDTH - 1:0] StateCComb; +reg [STATE_DWIDTH - 1:0] StateDComb; +reg [STATE_DWIDTH - 1:0] AddendState1; +reg [STATE_DWIDTH - 1:0] AddendState2; +reg [STATE_DWIDTH - 1:0] ShiftedAddend; + +always @(RoundNum or StateAReg or StateBReg or StateCReg or + StateDReg or BlockIn or DataVld) + begin + Md5FuncValue = 0; + XValue = 0; + TValue = 0; + if (DataVld) begin + case(RoundNum) + 0 : begin + Md5FuncValue = F(StateBReg, StateCReg, StateDReg); + XValue = byte_flip(DataIn); + TValue = T01; + end + 1 : begin + Md5FuncValue = F(StateAReg, StateBReg, StateCReg); + XValue = byte_flip(DataIn); + TValue = T02; + end + 2 : begin + Md5FuncValue = F(StateDReg, StateAReg, StateBReg); + XValue = byte_flip(DataIn); + TValue = T03; + end + 3 : begin + Md5FuncValue = F(StateCReg, StateDReg, StateAReg); + XValue = byte_flip(DataIn); + TValue = T04; + end + 4 : begin + Md5FuncValue = F(StateBReg, StateCReg, StateDReg); + XValue = byte_flip(DataIn); + TValue = T05; + end + 5 : begin + Md5FuncValue = F(StateAReg, StateBReg, StateCReg); + XValue = byte_flip(DataIn); + TValue = T06; + end + 6 : begin + Md5FuncValue = F(StateDReg, StateAReg, StateBReg); + XValue = byte_flip(DataIn); + TValue = T07; + end + 7 : begin + Md5FuncValue = F(StateCReg, StateDReg, StateAReg); + XValue = byte_flip(DataIn); + TValue = T08; + end + 8 : begin + Md5FuncValue = F(StateBReg, StateCReg, StateDReg); + XValue = byte_flip(DataIn); + TValue = T09; + end + 9 : begin + Md5FuncValue = F(StateAReg, StateBReg, StateCReg); + XValue = byte_flip(DataIn); + TValue = T10; + end + 10 : begin + Md5FuncValue = F(StateDReg, StateAReg, StateBReg); + XValue = byte_flip(DataIn); + TValue = T11; + end + 11 : begin + Md5FuncValue = F(StateCReg, StateDReg, StateAReg); + XValue = byte_flip(DataIn); + TValue = T12; + end + 12 : begin + Md5FuncValue = F(StateBReg, StateCReg, StateDReg); + XValue = byte_flip(DataIn); + TValue = T13; + end + 13 : begin + Md5FuncValue = F(StateAReg, StateBReg, StateCReg); + XValue = byte_flip(DataIn); + TValue = T14; + end + 14 : begin + Md5FuncValue = F(StateDReg, StateAReg, StateBReg); + XValue = byte_flip(DataIn); + TValue = T15; + end + 15 : begin + Md5FuncValue = F(StateCReg, StateDReg, StateAReg); + XValue = byte_flip(DataIn); + TValue = T16; + end + 16 : begin + Md5FuncValue = G(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 1); + TValue = T17; + end + 17 : begin + Md5FuncValue = G(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 6); + TValue = T18; + end + 18 : begin + Md5FuncValue = G(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 11); + TValue = T19; + end + 19 : begin + Md5FuncValue = G(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 0); + TValue = T20; + end + 20 : begin + Md5FuncValue = G(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 5); + TValue = T21; + end + 21 : begin + Md5FuncValue = G(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 10); + TValue = T22; + end + 22 : begin + Md5FuncValue = G(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 15); + TValue = T23; + end + 23 : begin + Md5FuncValue = G(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 4); + TValue = T24; + end + 24 : begin + Md5FuncValue = G(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 9); + TValue = T25; + end + 25 : begin + Md5FuncValue = G(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 14); + TValue = T26; + end + 26 : begin + Md5FuncValue = G(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 3); + TValue = T27; + end + 27 : begin + Md5FuncValue = G(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 8); + TValue = T28; + end + 28 : begin + Md5FuncValue = G(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 13); + TValue = T29; + end + 29 : begin + Md5FuncValue = G(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 2); + TValue = T30; + end + 30 : begin + Md5FuncValue = G(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 7); + TValue = T31; + end + 31 : begin + Md5FuncValue = G(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 12); + TValue = T32; + end + 32 : begin + Md5FuncValue = H(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 5); + TValue = T33; + end + 33 : begin + Md5FuncValue = H(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 8); + TValue = T34; + end + 34 : begin + Md5FuncValue = H(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 11); + TValue = T35; + end + 35 : begin + Md5FuncValue = H(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 14); + TValue = T36; + end + 36 : begin + Md5FuncValue = H(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 1); + TValue = T37; + end + 37 : begin + Md5FuncValue = H(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 4); + TValue = T38; + end + 38 : begin + Md5FuncValue = H(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 7); + TValue = T39; + end + 39 : begin + Md5FuncValue = H(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 10); + TValue = T40; + end + 40 : begin + Md5FuncValue = H(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 13); + TValue = T41; + end + 41 : begin + Md5FuncValue = H(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 0); + TValue = T42; + end + 42 : begin + Md5FuncValue = H(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 3); + TValue = T43; + end + 43 : begin + Md5FuncValue = H(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 6); + TValue = T44; + end + 44 : begin + Md5FuncValue = H(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 9); + TValue = T45; + end + 45 : begin + Md5FuncValue = H(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 12); + TValue = T46; + end + 46 : begin + Md5FuncValue = H(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 15); + TValue = T47; + end + 47 : begin + Md5FuncValue = H(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 2); + TValue = T48; + end + 48 : begin + Md5FuncValue = I(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 0); + TValue = T49; + end + 49 : begin + Md5FuncValue = I(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 7); + TValue = T50; + end + 50 : begin + Md5FuncValue = I(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 14); + TValue = T51; + end + 51 : begin + Md5FuncValue = I(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 5); + TValue = T52; + end + 52 : begin + Md5FuncValue = I(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 12); + TValue = T53; + end + 53 : begin + Md5FuncValue = I(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 3); + TValue = T54; + end + 54 : begin + Md5FuncValue = I(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 10); + TValue = T55; + end + 55 : begin + Md5FuncValue = I(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 1); + TValue = T56; + end + 56 : begin + Md5FuncValue = I(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 8); + TValue = T57; + end + 57 : begin + Md5FuncValue = I(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 15); + TValue = T58; + end + 58 : begin + Md5FuncValue = I(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 6); + TValue = T59; + end + 59 : begin + Md5FuncValue = I(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 13); + TValue = T60; + end + 60 : begin + Md5FuncValue = I(StateBReg, StateCReg, StateDReg); + XValue = FX(BlockIn, 4); + TValue = T61; + end + 61 : begin + Md5FuncValue = I(StateAReg, StateBReg, StateCReg); + XValue = FX(BlockIn, 11); + TValue = T62; + end + 62 : begin + Md5FuncValue = I(StateDReg, StateAReg, StateBReg); + XValue = FX(BlockIn, 2); + TValue = T63; + end + 63 : begin + Md5FuncValue = I(StateCReg, StateDReg, StateAReg); + XValue = FX(BlockIn, 9); + TValue = T64; + end + default: begin + Md5FuncValue = 0; + XValue = 0; + TValue = 0; + end + endcase + end + else begin + Md5FuncValue = 0; + XValue = 0; + TValue = 0; + end + end + +always @(AddRes1 or AddRes2 or StateAReg or + StateBReg or StateCReg or StateDReg or + RoundNum or DataVld) + begin + AddendState1 = 0; + AddendState2 = 0; + StateAComb = StateAReg; + StateBComb = StateBReg; + StateCComb = StateCReg; + StateDComb = StateDReg; + ShiftedAddend = 0; + if (DataVld) begin + casex(RoundNum) + 6'b00XX00 : begin + AddendState1 = StateAReg; + AddendState2 = StateBReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S11); + $display(); + StateAComb = AddRes2; + end + 6'b00XX01 : begin + AddendState1 = StateDReg; + AddendState2 = StateAReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S12); + $display(); + StateDComb = AddRes2; + end + 6'b00XX10 : begin + AddendState1 = StateCReg; + AddendState2 = StateDReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S13); + $display(); + StateCComb = AddRes2; + end + 6'b00XX11 : begin + AddendState1 = StateBReg; + AddendState2 = StateCReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S14); + $display(); + StateBComb = AddRes2; + end + 6'b01XX00 : begin + AddendState1 = StateAReg; + AddendState2 = StateBReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S21); + $display(); + StateAComb = AddRes2; + end + 6'b01XX01 : begin + AddendState1 = StateDReg; + AddendState2 = StateAReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S22); + $display(); + StateDComb = AddRes2; + end + 6'b01XX10 : begin + AddendState1 = StateCReg; + AddendState2 = StateDReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S23); + $display(); + StateCComb = AddRes2; + end + 6'b01XX11 : begin + AddendState1 = StateBReg; + AddendState2 = StateCReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S24); + $display(); + StateBComb = AddRes2; + end + 6'b10XX00 : begin + AddendState1 = StateAReg; + AddendState2 = StateBReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S31); + $display(); + StateAComb = AddRes2; + end + 6'b10XX01 : begin + AddendState1 = StateDReg; + AddendState2 = StateAReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S32); + $display(); + StateDComb = AddRes2; + end + 6'b10XX10 : begin + AddendState1 = StateCReg; + AddendState2 = StateDReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S33); + $display(); + StateCComb = AddRes2; + end + 6'b10XX11 : begin + AddendState1 = StateBReg; + AddendState2 = StateCReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S34); + $display(); + StateBComb = AddRes2; + end + 6'b11XX00 : begin + AddendState1 = StateAReg; + AddendState2 = StateBReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S41); + $display(); + StateAComb = AddRes2; + end + 6'b11XX01 : begin + AddendState1 = StateDReg; + AddendState2 = StateAReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S42); + $display(); + StateDComb = AddRes2; + end + 6'b11XX10 : begin + AddendState1 = StateCReg; + AddendState2 = StateDReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S43); + $display(); + StateCComb = AddRes2; + end + 6'b11XX11 : begin + AddendState1 = StateBReg; + AddendState2 = StateCReg; + ShiftedAddend = ROTATE_LEFT(AddRes1, S44); + $display(); + StateBComb = AddRes2; + end + default : begin + AddendState1 = 0; + AddendState2 = 0; + ShiftedAddend = 0; + StateAComb = StateAReg; + StateBComb = StateBReg; + StateCComb = StateCReg; + StateDComb = StateDReg; + end + endcase + end + end +endmodule

trunk/md5_comb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/md5_top.v =================================================================== --- trunk/md5_top.v (nonexistent) +++ trunk/md5_top.v (revision 2) @@ -0,0 +1,152 @@ +/******************************************************************************** +* Module Name : md5_top +* Description : MD5 computation top level +* +* +******************************************************************************** +* Esencia Technology Proprietary and Confidential +* All rights reserved (c) 2004 by Esencia Technolgy +********************************************************************************/ + +module md5_top ( + + //Inputs + clk, + rst_n, + dataVld, + dataIn, + + //from adders + ResStateAReg, + ResStateBReg, + ResStateCReg, + ResStateDReg, + AddRes1, + AddRes2, + + // from Register file + StateAReg, + StateBReg, + StateCReg, + StateDReg, + BlockData, + + //Outputs + // To Adders + Md5FuncValue, + TValue, + XValue, + AddendState1, + AddendState2, + ShiftedAddend, + RoundNum, + + // To Register file + Md5Data, + StateAComb, + StateBComb, + StateCComb, + StateDComb, + + //final output + msgDgstVld, + msgDigest + ); + +`include "ah_params.vh" +`include "md5_params.vh" + +input clk; +input rst_n; +input dataVld; +input [DATA_WIDTH - 1:0] dataIn; +input [STATE_DWIDTH - 1:0] ResStateAReg; +input [STATE_DWIDTH - 1:0] ResStateBReg; +input [STATE_DWIDTH - 1:0] ResStateCReg; +input [STATE_DWIDTH - 1:0] ResStateDReg; +input [STATE_DWIDTH - 1:0] AddRes1; +input [STATE_DWIDTH - 1:0] AddRes2; + +input [STATE_DWIDTH - 1:0] StateAReg; +input [STATE_DWIDTH - 1:0] StateBReg; +input [STATE_DWIDTH - 1:0] StateCReg; +input [STATE_DWIDTH - 1:0] StateDReg; +input [BLOCK_SIZE-1:0] BlockData; + +output [STATE_DWIDTH - 1:0] Md5FuncValue; +output [STATE_DWIDTH - 1:0] TValue; +output [DATA_WIDTH - 1 :0] XValue; +output [STATE_DWIDTH - 1:0] AddendState1; +output [STATE_DWIDTH - 1:0] AddendState2; +output [STATE_DWIDTH - 1:0] ShiftedAddend; +output [STATE_DWIDTH - 1:0] StateAComb; +output [STATE_DWIDTH - 1:0] StateBComb; +output [STATE_DWIDTH - 1:0] StateCComb; +output [STATE_DWIDTH - 1:0] StateDComb; +output [DATA_WIDTH - 1:0] Md5Data; +output [5:0] RoundNum; + +output msgDgstVld; +output [DATA_WIDTH -1:0] msgDigest; + +wire [5:0] RoundNum; +wire [DATA_WIDTH - 1:0] Md5Data; + +wire [STATE_DWIDTH - 1:0] Md5FuncValue; +wire [STATE_DWIDTH - 1:0] TValue; +wire [DATA_WIDTH - 1 :0] XValue; +wire [STATE_DWIDTH - 1:0] AddendState1; +wire [STATE_DWIDTH - 1:0] AddendState2; +wire [STATE_DWIDTH - 1:0] ShiftedAddend; +wire [STATE_DWIDTH - 1:0] StateAComb; +wire [STATE_DWIDTH - 1:0] StateBComb; +wire [STATE_DWIDTH - 1:0] StateCComb; +wire [STATE_DWIDTH - 1:0] StateDComb; +wire DataVldExt; + +md5_ctrl u_md5_ctrl_0 ( + //Inputs + .clk(clk), + .rst_n(rst_n), + .DataVld(dataVld), + .DataIn(dataIn), + .ResStateAReg(ResStateAReg), + .ResStateBReg(ResStateBReg), + .ResStateCReg(ResStateCReg), + .ResStateDReg(ResStateDReg), + + //Outputs + .MsgDgstVld(msgDgstVld), + .MsgDigest(msgDigest), + .DataVldExt(DataVldExt), + .Md5Data(Md5Data), + .RoundNum(RoundNum) + ); + +md5_comb u_md5_comb_0 ( + //Inputs + .RoundNum(RoundNum), + .StateAReg(StateAReg), + .StateBReg(StateBReg), + .StateCReg(StateCReg), + .StateDReg(StateDReg), + .BlockIn(BlockData), + .DataVld(DataVldExt), + .DataIn(dataIn), + .AddRes1(AddRes1), + .AddRes2(AddRes2), + + //Outputs + .Md5FuncValue(Md5FuncValue), + .TValue(TValue), + .XValue(XValue), + .StateAComb(StateAComb), + .StateBComb(StateBComb), + .StateCComb(StateCComb), + .StateDComb(StateDComb), + .AddendState1(AddendState1), + .AddendState2(AddendState2), + .ShiftedAddend(ShiftedAddend) + ); + +endmodule

trunk/md5_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/ah_regs.v =================================================================== --- trunk/ah_regs.v (nonexistent) +++ trunk/ah_regs.v (revision 2) @@ -0,0 +1,143 @@ +/**************************************************************************** +Register file +****************************************************************************/ + + +module ah_regs ( + + //Inputs + rst_n, + clk, + DataVld, + DataIn, + stateVld, + stateAIn, + stateBIn, + stateCIn, + stateDIn, + StateAComb, + StateBComb, + StateCComb, + StateDComb, + StateEComb, + + //Outputs + StateAReg, + StateBReg, + StateCReg, + StateDReg, + A_Reg, + B_Reg, + C_Reg, + D_Reg, + BlockOut + ); + +`include "ah_params.vh" + +input rst_n; +input clk; +input DataVld; +input [DATA_WIDTH - 1:0] DataIn; +input stateVld; +input [STATE_DWIDTH - 1:0] stateAIn; +input [STATE_DWIDTH - 1:0] stateBIn; +input [STATE_DWIDTH - 1:0] stateCIn; +input [STATE_DWIDTH - 1:0] stateDIn; +input [STATE_DWIDTH - 1:0] StateAComb; +input [STATE_DWIDTH - 1:0] StateBComb; +input [STATE_DWIDTH - 1:0] StateCComb; +input [STATE_DWIDTH - 1:0] StateDComb; +input [STATE_DWIDTH - 1:0] StateEComb; + + +output [STATE_DWIDTH - 1:0] StateAReg; +output [STATE_DWIDTH - 1:0] StateBReg; +output [STATE_DWIDTH - 1:0] StateCReg; +output [STATE_DWIDTH - 1:0] StateDReg; +output [STATE_DWIDTH - 1:0] A_Reg; +output [STATE_DWIDTH - 1:0] B_Reg; +output [STATE_DWIDTH - 1:0] C_Reg; +output [STATE_DWIDTH - 1:0] D_Reg; +output [BLOCK_SIZE-1:0] BlockOut; + +reg [STATE_DWIDTH - 1:0] StateAReg; +reg [STATE_DWIDTH - 1:0] StateBReg; +reg [STATE_DWIDTH - 1:0] StateCReg; +reg [STATE_DWIDTH - 1:0] StateDReg; +reg [STATE_DWIDTH - 1:0] A_Reg; +reg [STATE_DWIDTH - 1:0] B_Reg; +reg [STATE_DWIDTH - 1:0] C_Reg; +reg [STATE_DWIDTH - 1:0] D_Reg; +reg [DATA_WIDTH - 1:0] WtData [15:0]; + +assign BlockOut = {WtData[15], WtData[14], WtData[13], WtData[12], + WtData[11], WtData[10], WtData[9], WtData[8], + WtData[7], WtData[6], WtData[5], WtData[4], + WtData[3], WtData[2], WtData[1], WtData[0]}; + + +always @(posedge clk) + begin + if (DataVld) begin + WtData[0] <= DataIn; + WtData[1] <= WtData[0]; + WtData[2] <= WtData[1]; + WtData[3] <= WtData[2]; + WtData[4] <= WtData[3]; + WtData[5] <= WtData[4]; + WtData[6] <= WtData[5]; + WtData[7] <= WtData[6]; + WtData[8] <= WtData[7]; + WtData[9] <= WtData[8]; + WtData[10] <= WtData[9]; + WtData[11] <= WtData[10]; + WtData[12] <= WtData[11]; + WtData[13] <= WtData[12]; + WtData[14] <= WtData[13]; + WtData[15] <= WtData[14]; + end + end + +always @(posedge clk or negedge rst_n) + begin + if (!rst_n) begin + StateAReg <= 32'b0; + StateBReg <= 32'b0; + StateCReg <= 32'b0; + StateDReg <= 32'b0; + end + else begin + if (stateVld) begin + StateAReg <= stateAIn; + StateBReg <= stateBIn; + StateCReg <= stateCIn; + StateDReg <= stateDIn; + end + else begin + StateAReg <= StateAComb; + StateBReg <= StateBComb; + StateCReg <= StateCComb; + StateDReg <= StateDComb; + end + end + end + +always @(posedge clk or negedge rst_n) + begin + if (!rst_n) begin + A_Reg <= 32'b0; + B_Reg <= 32'b0; + C_Reg <= 32'b0; + D_Reg <= 32'b0; + end + else begin + if (stateVld) begin + A_Reg <= stateAIn; + B_Reg <= stateBIn; + C_Reg <= stateCIn; + D_Reg <= stateDIn; + end + end + end +endmodule

trunk/ah_regs.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/md5_ctrl.v =================================================================== --- trunk/md5_ctrl.v (nonexistent) +++ trunk/md5_ctrl.v (revision 2) @@ -0,0 +1,147 @@ +/******************************************************************************** +* Module Name : md5_ctrl +* Description : MD5 computation control logic +* +********************************************************************************/ + + +module md5_ctrl ( + + //Inputs + clk, + rst_n, + DataVld, + DataIn, + ResStateAReg, + ResStateBReg, + ResStateCReg, + ResStateDReg, + + //Outputs + RoundNum, + DataVldExt, + Md5Data, + MsgDgstVld, + MsgDigest + ); + + +`include "ah_params.vh" +`include "md5_params.vh" +`include "md5_func.vh" + +input clk; +input rst_n; +input DataVld; +input [DATA_WIDTH - 1:0] DataIn; +input [STATE_DWIDTH - 1:0] ResStateAReg; +input [STATE_DWIDTH - 1:0] ResStateBReg; +input [STATE_DWIDTH - 1:0] ResStateCReg; +input [STATE_DWIDTH - 1:0] ResStateDReg; + +output [5:0] RoundNum; +output DataVldExt; +output [DATA_WIDTH - 1:0] Md5Data; +output MsgDgstVld; +output [DATA_WIDTH -1:0] MsgDigest; + +reg [5:0] RoundNum; +reg DataVldTemp; +reg MsgDgstVld_send; + +wire DataVldExt; +wire [DATA_WIDTH - 1:0] Md5Data; +wire [MD5_MSG_DIGEST -1:0] MsgDigest_wire; +reg [DATA_WIDTH -1:0] MsgDigest; +wire [STATE_DWIDTH - 1:0] ResStateAFlip; +wire [STATE_DWIDTH - 1:0] ResStateBFlip; +wire [STATE_DWIDTH - 1:0] ResStateCFlip; +wire [STATE_DWIDTH - 1:0] ResStateDFlip; +reg [2:0] sending_cnt; +reg [2:0] sending_cnt_r; +reg MsgDgstVld; +wire MsgDgstVld_c; + +assign ResStateAFlip = byte_flip(ResStateAReg); +assign ResStateBFlip = byte_flip(ResStateBReg); +assign ResStateCFlip = byte_flip(ResStateCReg); +assign ResStateDFlip = byte_flip(ResStateDReg); +assign MsgDigest_wire = {ResStateAFlip, ResStateBFlip, ResStateCFlip, ResStateDFlip}; + +assign DataVldExt = DataVld | DataVldTemp; +assign Md5Data = DataIn; + +assign MsgDgstVld_c = (sending_cnt != 0); + +always @(posedge clk or negedge rst_n) + begin + if (!rst_n) begin + RoundNum <= 0; + DataVldTemp <= 0; + end + else begin + if (DataVldExt) begin + RoundNum <= (RoundNum == 63) ? 0 : RoundNum + 1; + DataVldTemp <= (RoundNum != 63); + end + else begin + RoundNum <= 0; + DataVldTemp <= 0; + end + end + end + +always @(posedge clk or negedge rst_n) + begin + if (!rst_n) begin + MsgDgstVld_send <= 1'b0; + MsgDgstVld <= 1'b0; + end + else begin + MsgDgstVld_send <= (RoundNum == 63); + MsgDgstVld <= MsgDgstVld_c; + end + end + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + sending_cnt_r <= 3'b0; + end + else begin + sending_cnt_r <= sending_cnt; + end +end + +always @(MsgDgstVld_send or sending_cnt_r) begin + if (MsgDgstVld_send & (sending_cnt_r ==0)) begin + sending_cnt = 3'b001; + end + else if (sending_cnt_r !=0) begin + sending_cnt = (sending_cnt_r == 3'b100) ? 0 : sending_cnt_r + 1; + end + else begin + sending_cnt = 3'b0; + end +end + +always @(posedge clk) begin + case (sending_cnt) + 3'b001 : begin + MsgDigest <= MsgDigest_wire[31:0]; + end + 3'b010 : begin + MsgDigest <= MsgDigest_wire[63:32]; + end + 3'b011 : begin + MsgDigest <= MsgDigest_wire[95:64]; + end + 3'b100 : begin + MsgDigest <= MsgDigest_wire[127:96]; + end + default : begin + MsgDigest <= 32'b0; + end + endcase +end + +endmodule

trunk/md5_ctrl.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property