URL
https://opencores.org/ocsvn/miniuart2/miniuart2/trunk
Subversion Repositories miniuart2
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/branches/avendor/rtl/vhdl/utils.vhd
0,0 → 1,132
------------------------------------------------------------------------------- |
-- Title : UART |
-- Project : UART |
------------------------------------------------------------------------------- |
-- File : utils.vhd |
-- Author : Philippe CARTON |
-- (pc@microsystemes.com / philippe.carton2@libertysurf.fr) |
-- Organization: Microsystemes |
-- Created : 15/12/2001 |
-- Last update : 28/12/2001 |
-- Platform : Foundation 3.1i |
-- Simulators : Foundation logic simulator |
-- Synthesizers: Foundation Synopsys |
-- Targets : Xilinx Spartan |
-- Dependency : IEEE std_logic_1164 |
------------------------------------------------------------------------------- |
-- Description: VHDL utility file |
------------------------------------------------------------------------------- |
-- Copyright (c) notice |
-- This core adheres to the GNU public license |
-- |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : |
-- Version : |
-- Date : |
-- Modifier : name <email> |
-- Description : |
-- |
------------------------------------------------------------------------------ |
|
|
------------------------------------------------------------------------------- |
-- Revision list |
-- Version Author Date Changes |
-- |
-- 1.0 Philippe CARTON 19 December 2001 New model |
-- pc@microsystemes.com |
------------------------------------------------------------------------------- |
|
-------------------------------------------------------------------------------- |
-- Synchroniser: |
-- Synchronize an input signal (C1) with an input clock (C). |
-- The result is the O signal which is synchronous of C, and persist for |
-- one C clock period. |
-------------------------------------------------------------------------------- |
library IEEE,STD; |
use IEEE.Std_Logic_1164.all; |
|
entity synchroniser is |
port ( |
C1 : in Std_Logic; -- Asynchronous signal |
C : in Std_Logic; -- Clock |
O : out Std_logic); -- Synchronised signal |
end entity; |
|
architecture Behaviour of synchroniser is |
signal C1A : Std_Logic; |
signal C1S : Std_Logic; |
signal R : Std_Logic; |
begin |
RiseC1A : process(C1,R) |
begin |
if Rising_Edge(C1) then |
C1A <= '1'; |
end if; |
if (R = '1') then |
C1A <= '0'; |
end if; |
end process; |
|
SyncP : process(C,R) |
begin |
if Rising_Edge(C) then |
if (C1A = '1') then |
C1S <= '1'; |
else C1S <= '0'; |
end if; |
if (C1S = '1') then |
R <= '1'; |
else R <= '0'; |
end if; |
end if; |
if (R = '1') then |
C1S <= '0'; |
end if; |
end process; |
O <= C1S; |
end Behaviour; |
|
------------------------------------------------------------------------------- |
-- Counter |
-- This counter is a parametrizable clock divider. |
-- The count value is the generic parameter Count. |
-- It is CE enabled. (it will count only if CE is high). |
-- When it overflow, it will emit a pulse on O. |
-- It can be reseted to 0. |
------------------------------------------------------------------------------- |
library IEEE,STD; |
use IEEE.Std_Logic_1164.all; |
|
entity Counter is |
generic(Count: INTEGER range 0 to 65535); -- Count revolution |
port ( |
Clk : in Std_Logic; -- Clock |
Reset : in Std_Logic; -- Reset input |
CE : in Std_Logic; -- Chip Enable |
O : out Std_Logic); -- Output |
end entity; |
|
architecture Behaviour of Counter is |
begin |
counter : process(Clk,Reset) |
variable Cnt : INTEGER range 0 to Count-1; |
begin |
if Reset = '1' then |
Cnt := Count - 1; |
O <= '0'; |
elsif Rising_Edge(Clk) then |
if CE = '1' then |
if Cnt = 0 then |
O <= '1'; |
Cnt := Count - 1; |
else |
O <= '0'; |
Cnt := Cnt - 1; |
end if; |
else O <= '0'; |
end if; |
end if; |
end process; |
end Behaviour; |
/branches/avendor/rtl/vhdl/S95.log
0,0 → 1,2
CM: 0 error(s) 0 warning(s) found |
CM: 0 error(s) 0 warning(s) found |
/branches/avendor/rtl/vhdl/miniuart.vhd
0,0 → 1,145
------------------------------------------------------------------------------- |
-- Title : UART |
-- Project : UART |
------------------------------------------------------------------------------- |
-- File : Uart.vhd |
-- Author : Philippe CARTON |
-- (pc@microsystemes.com / philippe.carton2@libertysurf.fr) |
-- Organization: Microsystemes |
-- Created : 15/12/2001 |
-- Last update : 28/12/2001 |
-- Platform : Foundation 3.1i |
-- Simulators : Foundation logic simulator |
-- Synthesizers: Foundation Synopsys |
-- Targets : Xilinx Spartan |
-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd |
------------------------------------------------------------------------------- |
-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC. |
-- Wishbone compatable. |
------------------------------------------------------------------------------- |
-- Copyright (c) notice |
-- This core adheres to the GNU public license |
-- |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : |
-- Version : |
-- Date : |
-- Modifier : name <email> |
-- Description : |
-- |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity UART is |
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- Baud rate divisor |
port ( |
-- Wishbone signals |
WB_CLK_I : in Std_Logic; -- clock |
WB_RST_I : in Std_Logic; -- Reset input |
WB_ADR_I : in Std_Logic_Vector(1 downto 0); -- Adress bus |
WB_DAT_I : in Std_Logic_Vector(7 downto 0); -- DataIn Bus |
WB_DAT_O : out Std_Logic_Vector(7 downto 0); -- DataOut Bus |
WB_WE_I : in Std_Logic; -- Write Enable |
WB_STB_I : in Std_Logic; -- Strobe |
WB_ACK_O : out Std_Logic; -- Acknowledge |
-- process signals |
IntTx_O : out Std_Logic; -- Transmit interrupt: indicate waiting for Byte |
IntRx_O : out Std_Logic; -- Receive interrupt: indicate Byte received |
BR_Clk_I : in Std_Logic; -- Clock used for Transmit/Receive |
TxD_PAD_O: out Std_Logic; -- Tx RS232 Line |
RxD_PAD_I: in Std_Logic); -- Rx RS232 Line |
end entity; |
|
-- Architecture for UART for synthesis |
architecture Behaviour of UART is |
|
component Counter is |
generic(COUNT: INTEGER range 0 to 65535); -- Count revolution |
port ( |
Clk : in Std_Logic; -- Clock |
Reset : in Std_Logic; -- Reset input |
CE : in Std_Logic; -- Chip Enable |
O : out Std_Logic); -- Output |
end component; |
|
component RxUnit is |
port ( |
Clk : in Std_Logic; -- system clock signal |
Reset : in Std_Logic; -- Reset input |
Enable : in Std_Logic; -- Enable input |
ReadA : in Std_logic; -- Async Read Received Byte |
RxD : in Std_Logic; -- RS-232 data input |
RxAv : out Std_Logic; -- Byte available |
DataO : out Std_Logic_Vector(7 downto 0)); -- Byte received |
end component; |
|
component TxUnit is |
port ( |
Clk : in Std_Logic; -- Clock signal |
Reset : in Std_Logic; -- Reset input |
Enable : in Std_Logic; -- Enable input |
LoadA : in Std_Logic; -- Asynchronous Load |
TxD : out Std_Logic; -- RS-232 data output |
Busy : out Std_Logic; -- Tx Busy |
DataI : in Std_Logic_Vector(7 downto 0)); -- Byte to transmit |
end component; |
|
signal RxData : Std_Logic_Vector(7 downto 0); -- Last Byte received |
signal TxData : Std_Logic_Vector(7 downto 0); -- Last bytes transmitted |
signal SReg : Std_Logic_Vector(7 downto 0); -- Status register |
signal EnabRx : Std_Logic; -- Enable RX unit |
signal EnabTx : Std_Logic; -- Enable TX unit |
signal RxAv : Std_Logic; -- Data Received |
signal TxBusy : Std_Logic; -- Transmiter Busy |
signal ReadA : Std_Logic; -- Async Read receive buffer |
signal LoadA : Std_Logic; -- Async Load transmit buffer |
signal Sig0 : Std_Logic; -- gnd signal |
signal Sig1 : Std_Logic; -- vcc signal |
|
begin |
sig0 <= '0'; |
sig1 <= '1'; |
Uart_Rxrate : Counter -- Baud Rate adjust |
generic map (COUNT => BRDIVISOR) |
port map (BR_CLK_I, sig0, sig1, EnabRx); |
Uart_Txrate : Counter -- 4 Divider for Tx |
generic map (COUNT => 4) |
port map (BR_CLK_I, Sig0, EnabRx, EnabTx); |
Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData); |
Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData); |
IntTx_O <= not TxBusy; |
IntRx_O <= RxAv; |
SReg(0) <= not TxBusy; |
SReg(1) <= RxAv; |
|
-- Implements WishBone data exchange. |
-- Clocked on rising edge. Synchronous Reset RST_I |
WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I) |
variable StatM : Std_Logic_Vector(4 downto 0); |
begin |
if Rising_Edge(WB_CLK_I) then |
if (WB_RST_I = '1') then |
ReadA <= '0'; |
LoadA <= '0'; |
else |
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx |
TxData <= WB_DAT_I; |
LoadA <= '1'; -- Load signal |
else LoadA <= '0'; |
end if; |
if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx |
ReadA <= '1'; -- Read signal |
else ReadA <= '0'; |
end if; |
end if; |
end if; |
end process; |
WB_ACK_O <= WB_STB_I; |
WB_DAT_O <= |
RxData when WB_ADR_I = "00" else -- Read Byte from Rx |
SReg when WB_ADR_I = "01" else -- Read Status Reg |
X"00"; |
end Behaviour; |
/branches/avendor/rtl/vhdl/Rxunit.vhd
0,0 → 1,92
------------------------------------------------------------------------------- |
-- Title : UART |
-- Project : UART |
------------------------------------------------------------------------------- |
-- File : Rxunit.vhd |
-- Author : Philippe CARTON |
-- (pc@microsystemes.com / philippe.carton2@libertysurf.fr) |
-- Organization: Microsystemes |
-- Created : 15/12/2001 |
-- Last update : 28/12/2001 |
-- Platform : Foundation 3.1i |
-- Simulators : Foundation logic simulator |
-- Synthesizers: Foundation Synopsys |
-- Targets : Xilinx Spartan |
-- Dependency : IEEE std_logic_1164 |
------------------------------------------------------------------------------- |
-- Description: RxUnit is a serial to parallel unit Receiver. |
------------------------------------------------------------------------------- |
-- Copyright (c) notice |
-- This core adheres to the GNU public license |
-- |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : |
-- Version : |
-- Date : |
-- Modifier : name <email> |
-- Description : |
-- |
------------------------------------------------------------------------------ |
library ieee; |
use ieee.std_logic_1164.all; |
|
entity RxUnit is |
port ( |
Clk : in Std_Logic; -- system clock signal |
Reset : in Std_Logic; -- Reset input |
Enable : in Std_Logic; -- Enable input |
ReadA : in Std_logic; -- Async Read Received Byte |
RxD : in Std_Logic; -- RS-232 data input |
RxAv : out Std_Logic; -- Byte available |
DataO : out Std_Logic_Vector(7 downto 0)); -- Byte received |
end entity; |
|
architecture Behaviour of RxUnit is |
signal RReg : Std_Logic_Vector(7 downto 0); -- receive register |
signal RRegL : Std_Logic; -- Byte received |
begin |
-- RxAv process |
RxAvProc : process(RRegL,Reset,ReadA) |
begin |
if ReadA = '1' or Reset = '1' then |
RxAv <= '0'; -- Negate RxAv when RReg read |
elsif Rising_Edge(RRegL) then |
RxAv <= '1'; -- Assert RxAv when RReg written |
end if; |
end process; |
|
-- Rx Process |
RxProc : process(Clk,Reset,Enable,RxD,RReg) |
variable BitPos : INTEGER range 0 to 10; -- Position of the bit in the frame |
variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit |
begin |
if Reset = '1' then -- Reset |
RRegL <= '0'; |
BitPos := 0; |
elsif Rising_Edge(Clk) then |
if Enable = '1' then |
case BitPos is |
when 0 => -- idle |
RRegL <= '0'; |
if RxD = '0' then -- Start Bit |
SampleCnt := 0; |
BitPos := 1; |
end if; |
when 10 => -- Stop Bit |
BitPos := 0; -- next is idle |
RRegL <= '1'; -- Indicate byte received |
DataO <= RReg; -- Store received byte |
when others => |
if SampleCnt = 1 then -- Sample RxD on 1 |
RReg(BitPos-2) <= RxD; -- Deserialisation |
end if; |
if SampleCnt = 3 then -- Increment BitPos on 3 |
BitPos := BitPos + 1; |
end if; |
end case; |
sampleCnt := SampleCnt + 1; |
end if; |
end if; |
end process; |
end Behaviour; |
/branches/avendor/rtl/vhdl/Txunit.vhd
0,0 → 1,110
------------------------------------------------------------------------------- |
-- Title : UART |
-- Project : UART |
------------------------------------------------------------------------------- |
-- File : Txunit.vhd |
-- Author : Philippe CARTON |
-- (pc@microsystemes.com / philippe.carton2@libertysurf.fr) |
-- Organization: Microsystemes |
-- Created : 15/12/2001 |
-- Last update : 28/12/2001 |
-- Platform : Foundation 3.1i |
-- Simulators : Foundation logic simulator |
-- Synthesizers: Foundation Synopsys |
-- Targets : Xilinx Spartan |
-- Dependency : IEEE std_logic_1164 |
------------------------------------------------------------------------------- |
-- Description: Txunit is a parallel to serial unit transmitter. |
------------------------------------------------------------------------------- |
-- Copyright (c) notice |
-- This core adheres to the GNU public license |
-- |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : |
-- Version : |
-- Date : |
-- Modifier : name <email> |
-- Description : |
-- |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity TxUnit is |
port ( |
Clk : in Std_Logic; -- Clock signal |
Reset : in Std_Logic; -- Reset input |
Enable : in Std_Logic; -- Enable input |
LoadA : in Std_Logic; -- Asynchronous Load |
TxD : out Std_Logic; -- RS-232 data output |
Busy : out Std_Logic; -- Tx Busy |
DataI : in Std_Logic_Vector(7 downto 0)); -- Byte to transmit |
end entity; |
|
architecture Behaviour of TxUnit is |
signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer |
signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register |
signal TBufL : Std_Logic; -- Buffer loaded |
signal Load : Std_Logic; -- Load signal, Clk synchronised |
signal LoadAS : Std_Logic; -- Load signal Async started, Sync stopped |
|
begin |
process(LoadA, Load) |
begin |
if load = '1' then |
loadAS <= '0'; -- Clear LoadAS |
elsif Rising_Edge(LoadA) then |
LoadAS <= '1'; |
end if; |
end process; |
-- Synchronize Load on Clk |
SyncLoad : process(Clk, LoadAS) |
begin |
if Rising_Edge(Clk) then |
if LoadAS = '1' then |
Load <= '1'; |
end if; |
if Load = '1' then |
Load <= '0'; |
end if; |
end if; |
end process; |
Busy <= LoadAS or TBufL; |
|
-- Tx process |
TxProc : process(Clk, Reset, Enable, Load, DataI, TBuff, TReg, TBufL) |
variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame |
begin |
if Reset = '1' then |
TBufL <= '0'; |
BitPos := 0; |
elsif Rising_Edge(Clk) then |
if LoadAS = '1' then |
TBuff <= DataI; |
TBufL <= '1'; |
end if; |
if Enable = '1' then |
case BitPos is |
when 0 => -- idle or stop bit |
TxD <= '1'; |
if TBufL = '1' then -- start transmit. next is start bit |
TReg <= TBuff; |
TBufL <= '0'; |
BitPos := 1; |
end if; |
when 1 => -- Start bit |
TxD <= '0'; |
BitPos := 2; |
when others => |
TxD <= TReg(BitPos-2); -- Serialisation of TReg |
BitPos := BitPos + 1; |
end case; |
if BitPos = 10 then -- bit8. next is stop bit |
BitPos := 0; |
end if; |
end if; |
end if; |
end process; |
end Behaviour; |
/branches/avendor/doc/MiniUart.pdf
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branches/avendor/doc/MiniUart.pdf
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/avendor/doc/src/MiniUART.doc
===================================================================
Cannot display: file marked as a binary type.
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Index: branches/avendor/doc/src/MiniUART.doc
===================================================================
--- branches/avendor/doc/src/MiniUART.doc (nonexistent)
+++ branches/avendor/doc/src/MiniUART.doc (revision 2)
branches/avendor/doc/src/MiniUART.doc
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/avendor/sim/rtl_sim/bin/TESTRx.CMD
===================================================================
--- branches/avendor/sim/rtl_sim/bin/TESTRx.CMD (nonexistent)
+++ branches/avendor/sim/rtl_sim/bin/TESTRx.CMD (revision 2)
@@ -0,0 +1,53 @@
+| Script file for testing the receiver
+| for multi frames
+
+| Initial settings
+delete_waveforms
+restart
+stepsize 50nS
+
+| Watched Signals and Vectors
+watch WB_CLK_I | Wishbone clock
+watch WB_RST_I
+watch WB_WE_I
+watch WB_STB_I
+watch WB_ACK_O
+vector WB_ADR ADR_I[1:0]
+vector WB_DI DAT_I[7:0]
+vector WB_DO DAT_O[7:0]
+watch RxD | RS232 Rx Line
+watch IntRx | Emit Buffer is empty
+watch BRClk
+watch EnabRx
+
+| Stimulators Assignment
+| 1/Read SReg
+| 2/Read Byte Rx
+| 3/Read SReg
+| 4/Read Byte Rx
+clock WB_CLK_I 1 0
+wfm WB_RST_I @1nS=L 100nS=H 100nS=L
+wfm WB_STB_I @1nS=L +
+ @190.001uS=H 100nS=L +
+ @200.001uS=H 100nS=L +
+ @210.001uS=H 100nS=L +
+ @355.501uS=H 100nS=L
+wfm WB_WE_I @1nS=L +
+ @190.001uS=L +
+ @200.001uS=L +
+ @210.001uS=L +
+ @355.501uS=L
+wfm WB_ADR @1nS=L +
+ @190.001uS=1\H 100nS=Z +
+ @200.001uS=0\H 100nS=Z +
+ @210.001uS=1\H 100nS=Z +
+ @355.501uS=0\H 100nS=Z
+
+wfm BRClk @0nS=L (1uS=H 1uS=L)*8000 | Baud rate
+| Below is a generation of 50 same frames, coding 40h.
+wfm RxD @0nS=H +
+ 102.7uS=H (8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=L 8uS=H 8uS=L 8uS=H)*50 8uS=H
+
+| Perform Simulation
+sim 4000uS
+
branches/avendor/sim/rtl_sim/bin/TESTRx.CMD
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: branches/avendor/sim/rtl_sim/bin/TESTUART.CMD
===================================================================
--- branches/avendor/sim/rtl_sim/bin/TESTUART.CMD (nonexistent)
+++ branches/avendor/sim/rtl_sim/bin/TESTUART.CMD (revision 2)
@@ -0,0 +1,56 @@
+| Script file for testing the UART in echo mode (Txd and must be RxD tied)
+| 2 writes followed by 2 read
+
+| Initial settings
+delete_waveforms
+restart
+stepsize 50nS
+
+| Watched Signals and Vectors
+|
+| Define your signal and vector watch list here
+watch WB_CLK_I
+watch WB_RST_I
+watch WB_WE_I
+watch WB_STB_I
+watch WB_ACK_O
+vector WB_ADR ADR_I[1:0]
+vector WB_DI DAT_I[7:0]
+vector WB_DO DAT_O[7:0]
+watch RxD TEcho| RS232 Rx Line
+watch TxD | RS232 Tx Line
+watch IntTx | Byte present in buffer
+watch IntRx | Emit Buffer is empty
+watch BRClk
+watch EnabTx EnabRx
+
+| Stimulators Assignment
+| 1/Write Byte
+| 2/Write another byte
+| 3/Read Byte
+| 4/Read Byte
+clock WB_CLK_I 1 0
+wfm WB_RST_I @1nS=L 100nS=H 100nS=L
+wfm WB_STB_I @1nS=L +
+ @100.001uS=H 100nS=L +
+ @200.001uS=H 100nS=L +
+ @250.001uS=H 100nS=L +
+ @355.501uS=H 100nS=L
+wfm WB_WE_I @1nS=L +
+ @100.001uS=H +
+ @200.001uS=L +
+ @250.001uS=H +
+ @355.501uS=L
+wfm WB_ADR @1nS=L +
+ @100.001uS=0\H 100nS=Z +
+ @200.001uS=0\H 100nS=Z +
+ @250.001uS=0\H 100nS=Z +
+ @355.501uS=0\H 100nS=Z
+wfm WB_DI @1nS=\0H +
+ @100.001uS=81\H 101nS=Z +
+ @250.001uS=55\H 101nS=Z
+wfm BRClk @0nS=L (500nS=H 500nS=L)*500
+
+| Perform Simulation
+sim 400uS
+
branches/avendor/sim/rtl_sim/bin/TESTUART.CMD
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: branches/avendor/sw/TestCom/TestCom.bpr
===================================================================
--- branches/avendor/sw/TestCom/TestCom.bpr (nonexistent)
+++ branches/avendor/sw/TestCom/TestCom.bpr (revision 2)
@@ -0,0 +1,93 @@
+
+
+
+
+
+
+
+
+
+
+[Version Info]
+IncludeVerInfo=0
+AutoIncBuild=0
+MajorVer=1
+MinorVer=0
+Release=0
+Build=0
+Debug=0
+PreRelease=0
+Special=0
+Private=0
+DLL=0
+Locale=1036
+CodePage=1252
+
+[Version Info Keys]
+CompanyName=
+FileDescription=
+FileVersion=1.0.0.0
+InternalName=
+LegalCopyright=
+LegalTrademarks=
+OriginalFilename=
+ProductName=
+ProductVersion=1.0.0.0
+Comments=
+
+[Debugging]
+DebugSourceDirs=$(BCB)\source\vcl
+
+[Parameters]
+RunParams=1 9600
+HostApplication=
+RemoteHost=
+RemotePath=
+RemoteDebug=0
+
+[Compiler]
+ShowInfoMsgs=0
+LinkDebugVcl=0
+LinkCGLIB=0
+
+[Language]
+ActiveLang=
+ProjectLang=
+RootDir=
+
+
\ No newline at end of file
Index: branches/avendor/sw/TestCom/Thread.obj
===================================================================
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svn:mime-type = application/octet-stream
Index: branches/avendor/sw/TestCom/Thread.obj
===================================================================
--- branches/avendor/sw/TestCom/Thread.obj (nonexistent)
+++ branches/avendor/sw/TestCom/Thread.obj (revision 2)
branches/avendor/sw/TestCom/Thread.obj
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+application/octet-stream
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Index: branches/avendor/sw/TestCom/TestCom.bpf
===================================================================
--- branches/avendor/sw/TestCom/TestCom.bpf (nonexistent)
+++ branches/avendor/sw/TestCom/TestCom.bpf (revision 2)
@@ -0,0 +1,7 @@
+USEUNIT("mainUs.cpp");
+USEUNIT("Thread.cpp");
+//---------------------------------------------------------------------------
+Ce fichier n'est utilisé que par le Gestionnaire de projet et doit être traité comme le fichier projet
+
+
+main
\ No newline at end of file
Index: branches/avendor/sw/TestCom/mainUs.obj
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: branches/avendor/sw/TestCom/mainUs.obj
===================================================================
--- branches/avendor/sw/TestCom/mainUs.obj (nonexistent)
+++ branches/avendor/sw/TestCom/mainUs.obj (revision 2)
branches/avendor/sw/TestCom/mainUs.obj
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/avendor/sw/TestCom/Thread.cpp
===================================================================
--- branches/avendor/sw/TestCom/Thread.cpp (nonexistent)
+++ branches/avendor/sw/TestCom/Thread.cpp (revision 2)
@@ -0,0 +1,202 @@
+//---------------------------------------------------------------------------
+#include
+#pragma hdrstop
+
+#include
+#include "Thread.h"
+
+#pragma package(smart_init)
+
+//static AnsiString asBuf = "";
+static char sBuf[205];
+static stErr stErr1;
+HANDLE hComm;
+
+//---------------------------------------------------------------------------
+// Important: Methods and properties of objects in VCL can only be
+// used in a method called using Synchronize, for example:
+//
+// Synchronize(UpdateCaption);
+//
+// where UpdateCaption could look like:
+//
+// void __fastcall Thread_Com::UpdateCaption()
+// {
+// Form1->Caption = "Updated in a thread";
+// }
+//---------------------------------------------------------------------------
+__fastcall Thread_Com::Thread_Com(bool CreateSuspended,
+ int NumPortD, int BaudRateD) : TThread(CreateSuspended)
+{
+ NumPort = NumPortD;
+ BaudRate = BaudRateD;
+ Priority = tpHigher;
+}
+
+//---------------------------------------------------------------------------
+void __fastcall Thread_Com::AfterConstruction()
+{
+ DCB dcb;
+ BOOL fSuccess;
+ char str[5] = "COM0\x0";
+
+ str[3] = NumPort + 0x30;
+ hComm = CreateFile(str, GENERIC_READ | GENERIC_WRITE, 0, 0,
+ OPEN_EXISTING, FILE_FLAG_OVERLAPPED, NULL);
+
+ if (hComm == INVALID_HANDLE_VALUE)
+ {
+ sLastErr = "Impossible d'ouvrir COM"+AnsiString(NumPort);
+ dwLastErr = CANT_OPEN_COM;
+ return;
+ }
+ fSuccess = GetCommState(hComm, &dcb);
+ dcb.BaudRate = BaudRate;
+ dcb.ByteSize = 8;
+ dcb.Parity = NOPARITY;
+ dcb.StopBits = ONESTOPBIT;
+ fSuccess |= SetCommState(hComm, &dcb);
+
+ if (!fSuccess)
+ {
+ sLastErr = "Impossible de configurer COM"+AnsiString(NumPort);
+ dwLastErr = CANT_CONFIG_COM;
+ CloseHandle(hComm);
+ return;
+ }
+
+ Resume();
+}
+
+
+//---------------------------------------------------------------------------
+void __fastcall Thread_Com::Execute()
+{
+ LPSTR lpBuf;
+ DWORD dwNumByteRead;
+ DWORD dwRes;
+ BOOL fWaitingOnRead = false;
+ OVERLAPPED osReader = {0};
+ lpBuf = (char *)malloc(2);
+
+// Interdire l'execution si le port serie n'a pu être ouvert
+ if (hComm == INVALID_HANDLE_VALUE)return;
+
+// Definition d'un évènement
+ osReader.hEvent = CreateEvent(NULL, true, false, NULL);
+ if (osReader.hEvent == NULL) // Error creating overlapped event; abort.
+ {
+ sLastErr = "Erreur lors de la creation d'evènement";
+ dwLastErr = CREATE_EV_ERROR;
+ }
+
+ while (Terminated == false)
+ {
+ // Procedure pour lire sur le port hComm
+ if (!fWaitingOnRead)
+ {
+ // Issue the operation
+ if (!ReadFile(hComm, lpBuf, 1, &dwNumByteRead, &osReader))
+ {
+ if (GetLastError() != ERROR_IO_PENDING) // Read not delayed ?
+ { // Error in communications ; report it
+ sLastErr = "Erreur de lecture sur COM"+AnsiString(NumPort);
+ dwLastErr = ERR_READ_COM;
+ }
+ else fWaitingOnRead = true;
+ }
+ else // read completed immediately
+ HandleASuccessfulRead(*lpBuf);
+ }
+
+ if (fWaitingOnRead)
+ {
+ dwRes = WaitForSingleObject(osReader.hEvent, READ_TIMEOUT);
+ switch(dwRes)
+ {
+ // Read completed
+ case WAIT_OBJECT_0:
+ if (!GetOverlappedResult(hComm, &osReader, &dwNumByteRead, FALSE))
+ { // Error in communications ; report it
+ sLastErr = "Erreur de fin de lecture sur COM"+AnsiString(NumPort);
+ dwLastErr = ERR_READOVER_COM;
+ }
+ else // Read completed successfully.
+ {
+ dwLastErr = 0;
+ HandleASuccessfulRead(*lpBuf);
+ // Reset flag so that another operation can be issued
+ fWaitingOnRead = false;
+ }
+ break;
+ case WAIT_TIMEOUT:
+ // possible background work
+ break;
+ default:
+ // Error in the WaitforSingleObject; abort.
+ sLastErr = "Erreur d'attente de lecture sur COM"+AnsiString(NumPort);
+ dwLastErr = ERR_READWAIT_COM;
+ break;
+ }
+ }
+ }
+ free(lpBuf);
+ CloseHandle(osReader.hEvent);
+ CloseHandle(hComm);
+}
+//---------------------------------------------------------------------------
+BOOL __fastcall Thread_Com::WriteToComPort(AnsiString ASbuf)
+{
+ OVERLAPPED osWrite = {0};
+ DWORD dwToWrite;
+ DWORD dwNumByteWritten;
+ BOOL fRes;
+
+// Si le port serie n'a pu être ouvert, Sortir
+ if (hComm == INVALID_HANDLE_VALUE)return false;
+
+ dwToWrite = ASbuf.Length();
+ char *lpBuf = ASbuf.c_str();
+
+ // Create this write operation's OVERLAPPED structure's hEvent.
+ osWrite.hEvent = CreateEvent(NULL, true, false, NULL);
+ if (osWrite.hEvent == NULL)
+ // Error creating overlapped event handle
+ return false;
+
+ // Issue write.
+ if (!WriteFile(hComm, lpBuf, dwToWrite, &dwNumByteWritten, &osWrite))
+ {
+ if (GetLastError() != ERROR_IO_PENDING)
+ {
+ // WriteFile failed, but isn't delayed. Report error and abort.
+ sLastErr = "Erreur d'écriture sur COM"+AnsiString(NumPort);
+ dwLastErr = ERR_WRITE_COM;
+ fRes = false;
+ }
+ else
+ {
+ // Write is pending.
+ if (!GetOverlappedResult(hComm, &osWrite, &dwNumByteWritten, true))
+ fRes = false;
+ else
+ // Write operation completed successfully.
+ fRes = true;
+ }
+ }
+ else //WriteFile completed immediately.
+ dwLastErr = 0;
+ fRes = true;
+
+ CloseHandle(osWrite.hEvent);
+ return fRes;
+}
+
+
+//---------------------------------------------------------------------------
+extern void ReceiveCallBack(char *c);
+
+void __fastcall Thread_Com::HandleASuccessfulRead(char c)
+{
+ ReceiveCallBack(&c);
+}
Index: branches/avendor/sw/TestCom/Main.h
===================================================================
--- branches/avendor/sw/TestCom/Main.h (nonexistent)
+++ branches/avendor/sw/TestCom/Main.h (revision 2)
@@ -0,0 +1,2 @@
+void ReceiveCallBack(char *c);
+BOOL WINAPI CtrlHandler(DWORD dwCtrlType);
Index: branches/avendor/sw/TestCom/Readme.txt
===================================================================
--- branches/avendor/sw/TestCom/Readme.txt (nonexistent)
+++ branches/avendor/sw/TestCom/Readme.txt (revision 2)
@@ -0,0 +1,6 @@
+TestCom is a test program built to test a serial line connected in closed-loop,
+or to test an equipement configured in closed-loop.
+Developed under Borland C++ Builder 5.
+Feel free to use/edit/modify.
+
+Note: CC3250.DLL and VCL50.BPL are available at
\ No newline at end of file
Index: branches/avendor/sw/TestCom/Thread.h
===================================================================
--- branches/avendor/sw/TestCom/Thread.h (nonexistent)
+++ branches/avendor/sw/TestCom/Thread.h (revision 2)
@@ -0,0 +1,42 @@
+//---------------------------------------------------------------------------
+#ifndef ThreadH
+#define ThreadH
+//---------------------------------------------------------------------------
+#include
+
+#define READ_TIMEOUT 500 // milliseconds
+
+#define TWMD_WITH_GLERR 1
+#define TWMD_AND_CLOSE 2
+
+struct stErr
+{
+ DWORD Err;
+ AnsiString asMsg;
+};
+
+
+//---------------------------------------------------------------------------
+class Thread_Com : public TThread
+{
+enum {CANT_OPEN_COM = 1, CANT_CONFIG_COM, CREATE_EV_ERROR, ERR_READ_COM,
+ ERR_READOVER_COM, ERR_READWAIT_COM, ERR_WRITE_COM};
+
+private:
+protected:
+
+ void __fastcall Execute();
+ void __fastcall HandleASuccessfulRead(char c);
+public:
+ int NumPort;
+ int BaudRate;
+ int dwLastErr;
+ AnsiString sLastErr;
+ BOOL __fastcall WriteToComPort(AnsiString ASbuf);
+ __fastcall Thread_Com(bool CreateSuspended, int NumPortD, int BaudRate);
+ virtual void __fastcall AfterConstruction();
+};
+//---------------------------------------------------------------------------
+BOOL WriteToComPort(AnsiString ASbuf);
+BOOL ChangePort(int PortNum);
+#endif
Index: branches/avendor/sw/TestCom/mainFr.cpp
===================================================================
--- branches/avendor/sw/TestCom/mainFr.cpp (nonexistent)
+++ branches/avendor/sw/TestCom/mainFr.cpp (revision 2)
@@ -0,0 +1,50 @@
+//---------------------------------------------------------------------------
+#include
+#include
+#pragma hdrstop
+
+//---------------------------------------------------------------------------
+
+
+#pragma argsused
+int main(int argc, char* argv[])
+{
+ FILE *fs,*fd;
+ char line[200];
+ int l = 0;
+
+ if (argc != 3)
+ {
+ printf("Filtre de fichiers texte\n");
+ printf("Syntaxe:\n");
+ printf("FILTER File1 File2\n");
+ printf("\tFile1 = Fichier source\n");
+ printf("\tFile2 = Fichier destination\n");
+ return 0;
+ }
+
+ fs = fopen(argv[1], "rt");
+ if (fs == NULL)
+ {
+ printf("Impossible d'ouvrir %s\n", argv[1]);
+ return 0;
+ }
+
+ fd = fopen(argv[2], "wt");
+ if (fd == NULL)
+ {
+ printf("Impossible d'ouvrir %s\n", argv[2]);
+ fclose(fs);
+ return 0;
+ }
+
+ while(fgets(line, 200, fs) != NULL)
+ {
+ l++;
+ if (l <= 1 || l > 6)fprintf(fd, "%s", line);
+ }
+
+ fclose(fs);
+ fclose(fd);
+}
+//---------------------------------------------------------------------------
Index: branches/avendor/sw/TestCom/mainUs.cpp
===================================================================
--- branches/avendor/sw/TestCom/mainUs.cpp (nonexistent)
+++ branches/avendor/sw/TestCom/mainUs.cpp (revision 2)
@@ -0,0 +1,164 @@
+//---------------------------------------------------------------------------
+#include
+#include
+#include
+#include
+
+#include "main.h"
+#include "Thread.h"
+
+#pragma hdrstop
+//---------------------------------------------------------------------------
+
+#pragma argsused
+
+#define BUFLENGTH 500 // Size of the cyclic buffer for emit/receive checking
+
+Thread_Com *Thread_Com1;
+char Buf[BUFLENGTH];
+int BufTop, BufBot;
+bool CompErr;
+
+int main(int argc, char* argv[])
+{
+ int n, i;
+ int ComN;
+ unsigned int BaudRate;
+ long unsigned ncEmit;
+ char str[80];
+ HANDLE hConsole;
+ COORD c1;
+ DWORD dw1;
+
+ hConsole = GetStdHandle (STD_OUTPUT_HANDLE);
+
+ if (argc > 3)
+ {
+ printf ("Too many arguments on the command line.\n");
+ return 0;
+ }
+ if (argc == 0)printf ("Err 0.\n");
+ if (argc == 1)
+ {
+ printf("RS232 serial line tester\n");
+ printf("By Philippe Carton the 8/01/2002 (pc@microsystemes.com)\n");
+ printf("This program give a way to test the reliability of a closed-loop serial line\n");
+ printf("It emit a continuous random byte stream, and check that it receive exacly what\n");
+ printf("has been sent. The serial line, or the connected equipment must work in CLOSED-\n");
+ printf("LOOP, that is to say TxD and RxD tied.\n");
+ printf("Syntax:\n");
+ printf("TESTCOM port baudrate\n");
+ printf("\tport = com port number\n");
+ printf("\tFile2 = baudrate (9600, 19200 ...)\n");
+ return 0;
+ }
+ // Parse for the com port
+ n = sscanf (argv[1], "%d", &ComN);
+ if (n == 0 || ComN < 1 || ComN > 4)
+ {
+ printf ("invalid com port (1 to 4).\n");
+ return 0;
+ }
+ // Parse for the baudrate
+ BaudRate = 9600; // default
+ if (argc == 3)
+ {
+ n = sscanf (argv[2], "%d", &BaudRate);
+ if (n == 0 || BaudRate < 110 || BaudRate > 921600)
+ {
+ printf ("Invalid baudrate. (110 to 921600)\n");
+ return 0;
+ }
+ }
+
+ // Launch process
+ printf ("Com=%d Baudrate=%d\n", ComN, BaudRate);
+ printf ("--Test running, Ctrl-C to stop--\n");
+
+ // Open the thread communication thread
+ Thread_Com1 = new Thread_Com(true, ComN, BaudRate);
+ if (Thread_Com1->dwLastErr)
+ {
+ printf ("%s\n", Thread_Com1->sLastErr);
+ exit (0);
+ }
+
+ // Ctrl-C Handler
+ SetConsoleCtrlHandler (CtrlHandler, true);
+
+ // Continuous random byte emit
+ BufTop = 0;
+ BufBot = 0;
+ CompErr = false;
+ ncEmit = 0;
+
+ while (1)
+ {
+ // Test that cycling buf don't overflow
+ if (BufTop + 1 == BufBot || (BufBot == 0 && BufTop == sizeof(Buf)-1))
+ {
+ // Buf is full
+ printf ("Test Buffer is full.\n");
+ if (ncEmit == BUFLENGTH-1)
+ printf ("No byte has been received. The closed-loop fail.\n");
+ else
+ printf ("This mean that the OS is too slow compared to the specified baudrate.\n");
+ break;
+ }
+ Buf[BufTop] = random(256);
+ Thread_Com1->WriteToComPort(Buf[BufTop]);
+ if (Thread_Com1->dwLastErr)
+ {
+ printf ("%s\n", Thread_Com1->sLastErr);
+ break;
+ }
+ BufTop++; if (BufTop >= sizeof(Buf))BufTop = 0;
+
+ // Display the char count every 100 loop
+ ncEmit ++;
+ if (BufTop == 0)
+ {
+ sprintf (str, "car emis = %lu", ncEmit);
+ c1.X = 4; c1.Y = wherey()-1;
+ WriteConsoleOutputCharacter(hConsole, str, strlen(str), c1, &dw1);
+ }
+ // In case of error detected between Transmit-Receive
+ if (CompErr == true)
+ {
+ printf ("Mismatch observed between emit/received char.\n");
+ printf ("Last emitted char = \n\t");
+ for (i = 0; i < 10; i++)
+ {
+ printf ("%x ", (unsigned char)Buf[BufTop]);
+ BufTop --; if (BufTop < 0)BufTop = sizeof(Buf);
+ }
+ printf ("\n");
+ break;
+ }
+ }
+
+ // Close the communication thread
+ Thread_Com1->Terminate();
+ Thread_Com1->WaitFor();
+ delete Thread_Com1;
+
+ return 0;
+}
+
+BOOL WINAPI CtrlHandler(DWORD dwCtrlType)
+{
+ printf ("Serial line succesfully tested.\n");
+
+ return 0;
+}
+
+void ReceiveCallBack(char *c)
+{
+ if (*c != Buf[BufBot])
+ {
+ CompErr = true;
+ }
+ BufBot++; if (BufBot >= sizeof(Buf))BufBot = 0;
+}
+
+
Index: branches/avendor/sw/TestCom/TestCom.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: branches/avendor/sw/TestCom/TestCom.exe
===================================================================
--- branches/avendor/sw/TestCom/TestCom.exe (nonexistent)
+++ branches/avendor/sw/TestCom/TestCom.exe (revision 2)
branches/avendor/sw/TestCom/TestCom.exe
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/avendor/sw/TestCom/TestCom.dsk
===================================================================
--- branches/avendor/sw/TestCom/TestCom.dsk (nonexistent)
+++ branches/avendor/sw/TestCom/TestCom.dsk (revision 2)
@@ -0,0 +1,367 @@
+[Closed Files]
+File_0=SourceModule,'D:\pcarton\CBuilder\TestCom\main.h',0,1,1,1,1,0,0
+File_1=SourceModule,'D:\pcarton\CBuilder\TestCom\Main.cpp',0,1,1,1,1,0,0
+File_2=SourceModule,'D:\pcarton\CBuilder\TestCom\analy.cpp',0,1,110,1,121,0,0
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+File_4=SourceModule,'D:\pcarton\CBuilder\TestCom\analy.h',0,1,1,1,1,0,0
+File_5=SourceModule,'C:\pcarton\Safo_Client\Main.cpp',0,1,262,19,289,0,0
+File_6=SourceModule,'C:\pcarton\Safo\Thread.cpp',0,1,833,14,845,0,0
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+File_8=SourceModule,'C:\pcarton\Safo\Main.cpp',0,1,32,3,125,0,0
+File_9=SourceModule,'C:\Program Files\DaqX\Programming Language Support\daq\c\32-bit Enhanced API\Include\daqx.h',0,1,1,1,1,0,0
+
+[Modules]
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+
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+
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+[View0]
+Module=D:\pcarton\CBuilder\TestCom\mainUs.cpp
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+TopLine=1
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+
+[View1]
+Module=D:\pcarton\CBuilder\TestCom\Thread.cpp
+CursorX=32
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+
+[Watches]
+Count=0
+
+[Breakpoints]
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+
+[AddressBreakpoints]
+Count=0
+
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+
+[LocalVarsWindow]
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+MaxLeft=-1
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+[ToDo List]
+Create=1
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+MaxLeft=-1
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+ClientWidth=462
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+[FPUWindow]
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