OpenCores
URL https://opencores.org/ocsvn/nlprg/nlprg/trunk

Subversion Repositories nlprg

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/nlprg/trunk/doc/nlprg8.svg
0,0 → 1,440
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<!-- Created with Digital by H.Neemann -->
<!-- created: Mon Apr 13 07:17:35 CEST 2020 -->
 
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<circle cx="880.0" cy="760.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
<circle cx="960.0" cy="740.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
</g>
<g>
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<circle cx="1080.0" cy="720.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
<circle cx="1160.0" cy="700.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
</g>
<g>
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<circle cx="820.0" cy="360.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
<circle cx="820.0" cy="400.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
<circle cx="900.0" cy="380.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
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<circle cx="440.0" cy="400.0" r="2.0" stroke="#3b3b3b" stroke-width="2.8" fill="#3b3b3b" />
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/nlprg/trunk/rtl/dff.v
0,0 → 1,22
module dff
(
input d,
input ck,
input rst,
output q
 
);
reg state;
 
assign q = state;
 
always @ (posedge ck or posedge rst )
begin
if (rst)
state <= 'h0;
else
state <= d;
end
 
endmodule
 
/nlprg/trunk/rtl/nlprg8.v
0,0 → 1,96
module nlprg8 (
input ck,
input rst,
output o0,
output o1,
output o2,
output o3,
output o4,
output o5,
output o6,
output o7
);
wire s0;
wire o0_temp;
wire s1;
wire o2_temp;
wire s2;
wire o1_temp;
wire s3;
wire o3_temp;
wire o4_temp;
wire o5_temp;
wire o6_temp;
wire o7_temp;
 
dff dff0 (
.d( s0 ),
.ck( ck ),
.rst( rst ),
.q( o0_temp )
);
 
dff dff1 (
.d( s1 ),
.ck( ck ),
.rst( rst ),
.q( o2_temp )
);
 
dff dff2 (
.d( s2 ),
.ck( ck ),
.rst( rst ),
.q( o1_temp )
);
 
dff dff3 (
.d( s3 ),
.ck( ck ),
.rst( rst ),
.q( o3_temp )
);
 
dff dff4 (
.d( o4_temp ),
.ck( ck ),
.rst( rst ),
.q( o5_temp )
);
 
dff dff5 (
.d( o3_temp ),
.ck( ck ),
.rst( rst ),
.q( o4_temp )
);
 
dff dff6 (
.d( o5_temp ),
.ck( ck ),
.rst( rst ),
.q( o6_temp )
);
 
dff dff7 (
.d( o6_temp ),
.ck( ck ),
.rst( rst ),
.q( o7_temp )
);
 
assign s0 = (~ (o6_temp ^ o7_temp) ^ o3_temp);
assign s1 = ~ (~ (o3_temp ^ o4_temp) ^ o1_temp);
assign s2 = ~ (~ (o5_temp ^ o6_temp) ^ o0_temp);
assign s3 = ((o5_temp ^ o2_temp) ^ (~ (o1_temp | o0_temp) & (((o7_temp & o6_temp) & (o5_temp & o4_temp)) & o3_temp)));
assign o0 = o0_temp;
assign o1 = o1_temp;
assign o2 = o2_temp;
assign o3 = o3_temp;
assign o4 = o4_temp;
assign o5 = o5_temp;
assign o6 = o6_temp;
assign o7 = o7_temp;
 
endmodule
 
/nlprg/trunk/tb/log/nlprg8_tb.log
0,0 → 1,257
0 00000000
1 10000000
2 11000000
3 11100000
4 11110000
5 01011000
6 00101100
7 11100110
8 01100011
9 11110001
10 11011000
11 01101100
12 11000110
13 01110011
14 01011001
15 10101100
16 10100110
17 01000011
18 11100001
19 01110000
20 00011000
21 00001100
22 11110110
23 11001011
24 10000101
25 00010010
26 11101001
27 01010100
28 01011010
29 11101101
30 00000110
31 00010011
32 01101001
33 00010100
34 01111010
35 11111101
36 10101110
37 01100111
38 10100011
39 10010001
40 11101000
41 11010100
42 00011010
43 11001101
44 00010110
45 10111011
46 00011101
47 11011110
48 11111111
49 01101111
50 10000111
51 11010011
52 00001001
53 00100100
54 11000010
55 00100001
56 00010000
57 00101000
58 10110100
59 00101010
60 01110101
61 11001010
62 00000101
63 01010010
64 11001001
65 01000100
66 11110010
67 10011001
68 11001100
69 10010110
70 11111011
71 00111101
72 11001110
73 01010111
74 00011011
75 01001101
76 01010110
77 10011011
78 00001101
79 01110110
80 10001011
81 10100101
82 00000010
83 01000001
84 00100000
85 10010000
86 01101000
87 10010100
88 00111010
89 11011101
90 10111110
91 11001111
92 11010111
93 01011011
94 01101101
95 01000110
96 00110011
97 01111001
98 10111100
99 00001110
100 00110111
101 00101011
102 11110101
103 10001010
104 00100101
105 01000010
106 01100001
107 00110000
108 00111000
109 00011100
110 01011110
111 10111111
112 01001111
113 10010111
114 01111011
115 01111101
116 11101110
117 01000111
118 10110011
119 00111001
120 10011100
121 00011110
122 10011111
123 01011111
124 00111111
125 00011111
126 00001111
127 10110111
128 01101011
129 11010101
130 10011010
131 10001101
132 00110110
133 10101011
134 10110101
135 10101010
136 00110101
137 11101010
138 00010101
139 11111010
140 10111101
141 10001110
142 01110111
143 00001011
144 11100101
145 00100010
146 01010001
147 10001000
148 11100100
149 10100010
150 00010001
151 10101000
152 11110100
153 00001010
154 01100101
155 01100010
156 01110001
157 10011000
158 01001100
159 11010110
160 11011011
161 00101101
162 01100110
163 00100011
164 11010001
165 11001000
166 11000100
167 10110010
168 10111001
169 11011100
170 00111110
171 10001111
172 11110111
173 01001011
174 11000101
175 00110010
176 11111001
177 11111100
178 00101110
179 00100111
180 10000011
181 10000001
182 01000000
183 10100000
184 11010000
185 01001000
186 10000100
187 10010010
188 10101001
189 01110100
190 01001010
191 01000101
192 01110010
193 11011001
194 11101100
195 10000110
196 01010011
197 01001001
198 00000100
199 11010010
200 10001001
201 01100100
202 11100010
203 00110001
204 10111000
205 01011100
206 01111110
207 10101111
208 11100111
209 11100011
210 10110001
211 11111000
212 01111100
213 01101110
214 00000111
215 10010011
216 00101001
217 00110100
218 01101010
219 01010101
220 11011010
221 10101101
222 00100110
223 00000011
224 11000001
225 01100000
226 10110000
227 01111000
228 00111100
229 01001110
230 00010111
231 00111011
232 01011101
233 11111110
234 11101111
235 11000111
236 11110011
237 00011001
238 10001100
239 10110110
240 11101011
241 10010101
242 10111010
243 10011101
244 10011110
245 11011111
246 01111111
247 00101111
248 10100111
249 11000011
250 10100001
251 01010000
252 00001000
253 10100100
254 10000010
255 00000001
0 00000000
/nlprg/trunk/tb/wave/prng8_tb.vcd
0,0 → 1,4482
$date
Sat Apr 18 17:08:32 2020
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module prng8_tb $end
$var wire 1 ! prng_start_state $end
$var wire 1 " o7 $end
$var wire 1 # o6 $end
$var wire 1 $ o5 $end
$var wire 1 % o4 $end
$var wire 1 & o3 $end
$var wire 1 ' o2 $end
$var wire 1 ( o1 $end
$var wire 1 ) o0 $end
$var wire 8 * o [7:0] $end
$var wire 1 + cnt_start_state $end
$var reg 1 , ck $end
$var reg 8 - cnt [7:0] $end
$var reg 1 . endsim $end
$var reg 1 / pass $end
$var reg 1 0 rst $end
$var reg 1 1 rst_d0 $end
$var reg 1 2 rst_d1 $end
$var integer 32 3 f [31:0] $end
$scope module nlprg8_u $end
$var wire 1 , ck $end
$var wire 1 ) o0 $end
$var wire 1 ( o1 $end
$var wire 1 ' o2 $end
$var wire 1 & o3 $end
$var wire 1 % o4 $end
$var wire 1 $ o5 $end
$var wire 1 # o6 $end
$var wire 1 " o7 $end
$var wire 1 0 rst $end
$var wire 1 4 s0 $end
$var wire 1 5 s1 $end
$var wire 1 6 s2 $end
$var wire 1 7 s3 $end
$var wire 1 8 o7_temp $end
$var wire 1 9 o6_temp $end
$var wire 1 : o5_temp $end
$var wire 1 ; o4_temp $end
$var wire 1 < o3_temp $end
$var wire 1 = o2_temp $end
$var wire 1 > o1_temp $end
$var wire 1 ? o0_temp $end
$scope module dff0 $end
$var wire 1 , ck $end
$var wire 1 4 d $end
$var wire 1 0 rst $end
$var wire 1 ? q $end
$var reg 1 ? state $end
$upscope $end
$scope module dff1 $end
$var wire 1 , ck $end
$var wire 1 5 d $end
$var wire 1 0 rst $end
$var wire 1 = q $end
$var reg 1 = state $end
$upscope $end
$scope module dff2 $end
$var wire 1 , ck $end
$var wire 1 6 d $end
$var wire 1 0 rst $end
$var wire 1 > q $end
$var reg 1 > state $end
$upscope $end
$scope module dff3 $end
$var wire 1 , ck $end
$var wire 1 7 d $end
$var wire 1 0 rst $end
$var wire 1 < q $end
$var reg 1 < state $end
$upscope $end
$scope module dff4 $end
$var wire 1 , ck $end
$var wire 1 0 rst $end
$var wire 1 : q $end
$var wire 1 ; d $end
$var reg 1 : state $end
$upscope $end
$scope module dff5 $end
$var wire 1 , ck $end
$var wire 1 < d $end
$var wire 1 0 rst $end
$var wire 1 ; q $end
$var reg 1 ; state $end
$upscope $end
$scope module dff6 $end
$var wire 1 , ck $end
$var wire 1 : d $end
$var wire 1 0 rst $end
$var wire 1 9 q $end
$var reg 1 9 state $end
$upscope $end
$scope module dff7 $end
$var wire 1 , ck $end
$var wire 1 9 d $end
$var wire 1 0 rst $end
$var wire 1 8 q $end
$var reg 1 8 state $end
$upscope $end
$upscope $end
$scope begin cnt_process $end
$upscope $end
$scope begin display_process $end
$upscope $end
$scope begin end_sim_process $end
$upscope $end
$scope begin reset_delay_process $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0?
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0=
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0:
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08
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$end
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/nlprg/trunk/tb/filelist.f
0,0 → 1,3
../rtl/dff.v
../rtl/nlprg8.v
./nlprg8_tb.v
/nlprg/trunk/tb/nlprg8_tb.v
0,0 → 1,135
module prng8_tb ();
 
reg ck;
reg rst;
wire o0;
wire o1;
wire o2;
wire o3;
wire o4;
wire o5;
wire o6;
wire o7;
 
nlprg8 nlprg8_u (
.ck(ck),
.rst(rst),
.o0(o0),
.o1(o1),
.o2(o2),
.o3(o3),
.o4(o4),
.o5(o5),
.o6(o6),
.o7(o7)
);
 
// dump variables
 
initial begin
 
$dumpfile( "./wave/prng8_tb.vcd");
$dumpvars( 0, prng8_tb );
 
end
 
parameter N = 8;
 
wire [N-1:0] o = {o0,o1,o2,o3,o4,o5,o6,o7};
 
integer f = -1 ; // file handler
 
// generate clocks and reset
 
initial begin
 
f = $fopen("./log/nlprg8_tb.log","w+");
 
rst = 1'b1 ;
#5 rst = ~ rst ;
#5 rst = ~ rst ;
#5 rst = ~ rst ;
ck = 1'b1 ;
forever #5 ck = ~ ck ;
 
end
 
// generate counter
 
reg [N-1:0] cnt;
 
always@ ( posedge ck or posedge rst ) begin : cnt_process
if ( rst ) cnt <= {N{1'b0}} ;
else cnt <= cnt + 1'b1 ;
end
 
// delay reset
 
reg rst_d0;
reg rst_d1;
 
always@ ( posedge ck or posedge rst ) begin : reset_delay_process
if ( rst ) begin
rst_d0 <= 1'b1 ;
rst_d1 <= 1'b1 ;
 
end else begin
 
rst_d0 <= 1'b0 ;
rst_d1 <= rst_d0 ;
 
end
end
 
// generate endsim
 
reg endsim;
reg pass;
 
wire prng_start_state = ( o == {N{1'b0}});
wire cnt_start_state = ( cnt == {N{1'b0}});
 
 
always@ ( posedge ck or posedge rst ) begin : end_sim_process
if ( rst ) begin
endsim <= 1'b0 ;
pass <= 1'b0 ;
 
end else if ( prng_start_state & ( ! rst_d1 ) ) begin
endsim <= 1'b1 ;
pass <= 1'b0 ;
 
end else if ( cnt_start_state & prng_start_state & ( ! rst_d1 ) ) begin
endsim <= 1'b1 ;
pass <= 1'b1 ;
 
end else if ( cnt_start_state & ( ! rst_d1 ) ) begin
endsim <= 1'b1 ;
pass <= 1'b0 ;
end
 
end
 
 
// display and finish
 
always@ ( posedge ck or posedge rst ) begin : display_process
if (( ! endsim ) && ( ! rst )) begin
$fdisplay(f,"%10d %10b", cnt , o) ;
end else if ( endsim ) begin
$fclose(f);
$finish ;
end
end
 
endmodule
 
/nlprg/trunk/LICENSE
0,0 → 1,22
MIT License
 
Copyright (c) 2020 Francesco Dell' Anna
 
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 
/nlprg/trunk/README.md
0,0 → 1,8
# NLPRG
 
This project provides an example of a non-linear pseudo random generator ( nlprg ). The nlprg can produce a pseudo-random sequence with a period of 2^n numbers, where n is the numbers of registers.
For more information an circuit examples visit my blog at https://fdblog.xyz/circuits/non-linear-pseudo-random-generator-introduction/
 
You can find the circuit schematic in the doc folder.
 
After running the simulation ( for example by running : iverilog nlprng8_tb.v ; ./a.out ), you should find the resulting sequence in the tb/log and all the waves in the tb/wave.

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