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URL https://opencores.org/ocsvn/parallel_scrambler/parallel_scrambler/trunk

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/parallel_scrambler/trunk/tb/tb_par_scram.vhd
0,0 → 1,143
----------------------------------------------------------------------
---- ----
---- Parallel Scrambler.
---- ----
---- This file is part of the Configurable Parallel Scrambler project
---- http://opencores.org/project,parallel_scrambler ----
---- ----
---- Description ----
---- Test bench for Parallel scrambler/descrambler module ----
---- ----
---- ----
---- License: LGPL ----
---- - ----
---- ----
---- Author(s): ----
---- - Howard Yin, sparkish@opencores.org ----
---- ----
----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY tb_par_scram IS
END tb_par_scram;
ARCHITECTURE behavior OF tb_par_scram IS
-- Component Declaration for the Unit Under Test (UUT)
component par_scrambler
generic (
Data_Width : integer;
Polynomial_Width : integer
);
port (
rst, clk, scram_rst : in std_logic;
Polynomial : in std_logic_vector (Polynomial_Width downto 0);
data_in : in std_logic_vector (Data_Width-1 downto 0);
scram_en : in std_logic;
data_out : out std_logic_vector (Data_Width-1 downto 0);
out_valid : out std_logic
);
end component;
 
--Inputs
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal scram_en : std_logic := '0';
signal scram_start : std_logic := '0';
signal rst : std_logic := '1';
signal clk : std_logic := '0';
 
--Outputs
signal scram_data_out : std_logic_vector(7 downto 0);
signal descram_data_out : std_logic_vector(7 downto 0);
signal scram_data_valid : std_logic;
signal descram_data_valid : std_logic;
 
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
scram_mod: par_scrambler
Generic Map (
Data_Width => 8,
Polynomial_Width => 7
)
PORT MAP (
Polynomial => "10010001",
data_in => data_in,
scram_en => scram_en,
scram_rst => scram_start,
rst => rst,
clk => clk,
data_out => scram_data_out,
out_valid => scram_data_valid
);
descram_mod: par_scrambler
Generic Map (
Data_Width => 8,
Polynomial_Width => 7
)
PORT MAP (
Polynomial => "10010001",
data_in => scram_data_out,
scram_en => scram_data_valid,
scram_rst => scram_start,
rst => rst,
clk => clk,
data_out => descram_data_out,
out_valid => descram_data_valid
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 90 ns;
rst <= '0';
wait for clk_period*10;
scram_start <= '1';
wait for clk_period;
scram_start <= '0';
wait for clk_period*10;
for i in 0 to 7 loop
wait until (rising_edge(clk));
scram_en <= '1';
data_in <= std_logic_vector(to_unsigned(i, 8));
end loop;
wait until (rising_edge(clk));
scram_en <= '0';
wait for clk_period*10;
for i in 0 to 7 loop
wait until (rising_edge(clk));
scram_en <= '1';
data_in <= std_logic_vector(to_unsigned(i, 8));
wait until (rising_edge(clk));
scram_en <= '0';
wait for clk_period*10;
end loop;
 
wait;
end process;
 
END;
/parallel_scrambler/trunk/src/par_scrambler.vhd
0,0 → 1,74
----------------------------------------------------------------------
---- ----
---- Parallel Scrambler.
---- ----
---- This file is part of the Configurable Parallel Scrambler project
---- http://opencores.org/project,parallel_scrambler ----
---- ----
---- Description ----
---- Parallel scrambler/descrambler module, user reconfigurable ----
---- ----
---- ----
---- License: LGPL ----
---- - ----
---- ----
---- Author(s): ----
---- - Howard Yin, sparkish@opencores.org ----
---- ----
----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity par_scrambler is
generic (
Data_Width : integer := 8; -- Input/output data width
Polynomial_Width : integer := 8 -- Polynomial width
);
port (
rst : in std_logic; -- Async reset
clk : in std_logic; -- System clock
scram_rst : in std_logic; -- Scrambler reset, use for initialization.
Polynomial : in std_logic_vector (Polynomial_Width downto 0); -- Polynomial. Example: 1+x^4+x^6+x^7 represent as "11010001"
data_in : in std_logic_vector (Data_Width-1 downto 0); -- Data input
scram_en : in std_logic; -- Input valid
data_out : out std_logic_vector (Data_Width-1 downto 0); -- Data output
out_valid : out std_logic -- Output valid
);
end par_scrambler;
 
architecture behavior of par_scrambler is
 
begin
scram_p : process (clk,rst)
variable c : std_logic := '0';
variable lfsr_q: std_logic_vector (Polynomial_Width-1 downto 0) := (others => '1');
variable lfsr_c: std_logic_vector (Data_Width-1 downto 0) := (others => '0');
begin
if (rst = '1') then
lfsr_q := (others => '1');
out_valid <= '0';
data_out <= (others => '0');
c := '0';
elsif (clk'EVENT and clk = '1') then
out_valid <= scram_en;
if (scram_rst = '1') then
lfsr_q := (others => '1');
elsif (scram_en = '1') then
for i in 0 to Data_Width-1 loop
c := lfsr_q (Polynomial_Width-1);
xor_loop : for j in 1 to Polynomial_Width-2 loop
if Polynomial(j) = '1' then
c := c xor lfsr_q(j-1);
end if;
end loop xor_loop;
lfsr_q := lfsr_q (Polynomial_Width-2 downto 0) & c;
lfsr_c := c & lfsr_c(Data_Width-1 downto 1);
end loop;
data_out <= lfsr_c xor data_in;
end if;
end if;
end process;
end architecture behavior;

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