Subversion Repositories plbv46_to_wb_bridge

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/trunk/doc/src/plbv46_2_wb.doc

trunk/doc/src/plbv46_2_wb.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/plbv46_2_wb.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/plbv46_2_wb.pdf =================================================================== --- trunk/doc/plbv46_2_wb.pdf (nonexistent) +++ trunk/doc/plbv46_2_wb.pdf (revision 2)

trunk/doc/plbv46_2_wb.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/pcore/plbv46_2_wb_v1_10_a/hdl/vhdl/plbv46_2_wb.vhd =================================================================== --- trunk/pcore/plbv46_2_wb_v1_10_a/hdl/vhdl/plbv46_2_wb.vhd (nonexistent) +++ trunk/pcore/plbv46_2_wb_v1_10_a/hdl/vhdl/plbv46_2_wb.vhd (revision 2) @@ -0,0 +1,367 @@ +------------------------------------------------------------------------------ +-- +-- *************************************************************************** +-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. ** +-- ** ** +-- ** Xilinx, Inc. ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** +-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** +-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** +-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** +-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** +-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** +-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** +-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** +-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** +-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** +-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** +-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** +-- ** FOR A PARTICULAR PURPOSE. ** +-- ** ** +-- *************************************************************************** +-- +------------------------------------------------------------------------------ +-- Filename: plbv46_2_wb.vhd +-- Version: 1.10.a +-- Creation Date: Tue Jul 15, 2008 +-- Description: PLB version 4.6 to Wishbone B3 Bridge +-- Simple non-bursting bridge interface from Xilinx-derivative +-- PLB Bus for Microblaze/PowerPC to OpenCores.org Wishbone +-- bridge standard. +-- +-- File Revisions: +-- 7/15/08 - mds : Initial version +-- 7/25/08 - mds : Added retry and bus error detection. +-- +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library proc_common_v2_00_a; +use proc_common_v2_00_a.proc_common_pkg.all; +use proc_common_v2_00_a.ipif_pkg.all; + +library plbv46_slave_single_v1_00_a; +use plbv46_slave_single_v1_00_a.plbv46_slave_single; + +library plbv46_2_wb_v1_10_a; +use plbv46_2_wb_v1_10_a.user_logic; + +------------------------------------------------------------------------------ +-- Entity section +------------------------------------------------------------------------------ +entity plbv46_2_wb is + generic + ( + -- ADD USER GENERICS BELOW THIS LINE --------------- + C_WB_DBUS_SIZE : integer := 32; -- Constant + C_WB_ACCESS_TIMEOUT : integer := 16; -- Ranges from 1 to 256 + C_WB_RETRY_TIMEOUT : integer := 64; -- Ranges from 1 to 256 + C_WB_ACCESS_RETRIES : integer := 4; -- Ranges from 1 to 4 + -- ADD USER GENERICS ABOVE THIS LINE --------------- + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol parameters, do not add to or delete + C_SPLB_AWIDTH : integer := 32; + C_SPLB_DWIDTH : integer := 128; + C_SPLB_NUM_MASTERS : integer := 8; + C_SPLB_MID_WIDTH : integer := 3; + C_SPLB_NATIVE_DWIDTH : integer := 32; + C_SPLB_P2P : integer := 0; + C_SPLB_SUPPORT_BURSTS : integer := 0; + C_SPLB_SMALLEST_MASTER : integer := 32; + C_SPLB_CLK_PERIOD_PS : integer := 10000; + C_INCLUDE_DPHASE_TIMER : integer := 0; + C_FAMILY : string := "virtex5"; + C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF"; + C_MEM0_HIGHADDR : std_logic_vector := X"00000000" + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + port + ( + -- ADD USER PORTS BELOW THIS LINE ------------------ + WB_CLK_O : out std_logic; + WB_RST_O : out std_logic; + WB_ADR_O : out std_logic_vector(31 downto 0); + WB_DAT_O : out std_logic_vector(C_WB_DBUS_SIZE-1 downto 0); + WB_SEL_O : out std_logic_vector((C_WB_DBUS_SIZE/8)-1 downto 0); + WB_CYC_O : out std_logic; + WB_LOCK_O : out std_logic; + WB_STB_O : out std_logic; + WB_WE_O : out std_logic; + WB_DAT_I : in std_logic_vector(C_WB_DBUS_SIZE-1 downto 0); + WB_ACK_I : in std_logic; + WB_ERR_I : in std_logic; + WB_RTY_I : in std_logic; + -- ADD USER PORTS ABOVE THIS LINE ------------------ + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol ports, do not add to or delete + SPLB_Clk : in std_logic; + SPLB_Rst : in std_logic; + PLB_ABus : in std_logic_vector(0 to 31); + PLB_UABus : in std_logic_vector(0 to 31); + PLB_PAValid : in std_logic; + PLB_SAValid : in std_logic; + PLB_rdPrim : in std_logic; + PLB_wrPrim : in std_logic; + PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); + PLB_abort : in std_logic; + PLB_busLock : in std_logic; + PLB_RNW : in std_logic; + PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); + PLB_MSize : in std_logic_vector(0 to 1); + PLB_size : in std_logic_vector(0 to 3); + PLB_type : in std_logic_vector(0 to 2); + PLB_lockErr : in std_logic; + PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); + PLB_wrBurst : in std_logic; + PLB_rdBurst : in std_logic; + PLB_wrPendReq : in std_logic; + PLB_rdPendReq : in std_logic; + PLB_wrPendPri : in std_logic_vector(0 to 1); + PLB_rdPendPri : in std_logic_vector(0 to 1); + PLB_reqPri : in std_logic_vector(0 to 1); + PLB_TAttribute : in std_logic_vector(0 to 15); + Sl_addrAck : out std_logic; + Sl_SSize : out std_logic_vector(0 to 1); + Sl_wait : out std_logic; + Sl_rearbitrate : out std_logic; + Sl_wrDAck : out std_logic; + Sl_wrComp : out std_logic; + Sl_wrBTerm : out std_logic; + Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); + Sl_rdWdAddr : out std_logic_vector(0 to 3); + Sl_rdDAck : out std_logic; + Sl_rdComp : out std_logic; + Sl_rdBTerm : out std_logic; + Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); + Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); + Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); + Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1) + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + + attribute SIGIS : string; + attribute SIGIS of SPLB_Clk : signal is "CLK"; + attribute SIGIS of SPLB_Rst : signal is "RST"; + +end entity plbv46_2_wb; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture IMP of plbv46_2_wb is + + ------------------------------------------ + -- Array of base/high address pairs for each address range + ------------------------------------------ + constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); + + constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := + ( + ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address + ZERO_ADDR_PAD & C_MEM0_HIGHADDR -- user logic memory space 0 high address + ); + + ------------------------------------------ + -- Array of desired number of chip enables for each address range + ------------------------------------------ + constant USER_NUM_MEM : integer := 1; + + constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := + ( + 0 => 1 -- number of ce for user logic memory space 0 (always 1 chip enable) + ); + + ------------------------------------------ + -- Ratio of bus clock to core clock (for use in dual clock systems) + -- 1 = ratio is 1:1 + -- 2 = ratio is 2:1 + ------------------------------------------ + constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; + + ------------------------------------------ + -- Width of the slave data bus (32 only) + ------------------------------------------ + constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; + + constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; + + ------------------------------------------ + -- Width of the slave address bus (32 only) + ------------------------------------------ + constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH; + + ------------------------------------------ + -- Index for CS/CE + ------------------------------------------ + constant USER_MEM0_CS_INDEX : integer := 0; + + constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX; + + ------------------------------------------ + -- IP Interconnect (IPIC) signal declarations + ------------------------------------------ + signal ipif_Bus2IP_Clk : std_logic; + signal ipif_Bus2IP_Reset : std_logic; + signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); + signal ipif_IP2Bus_WrAck : std_logic; + signal ipif_IP2Bus_RdAck : std_logic; + signal ipif_IP2Bus_Error : std_logic; + signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); + signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); + signal ipif_Bus2IP_RNW : std_logic; + signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); + signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); + signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); + signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); + signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); + signal user_IP2Bus_RdAck : std_logic; + signal user_IP2Bus_WrAck : std_logic; + signal user_IP2Bus_Error : std_logic; + +begin + + ------------------------------------------ + -- instantiate plbv46_slave_single + ------------------------------------------ + PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single + generic map + ( + C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, + C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, + C_SPLB_P2P => C_SPLB_P2P, + C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, + C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, + C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, + C_SPLB_AWIDTH => C_SPLB_AWIDTH, + C_SPLB_DWIDTH => C_SPLB_DWIDTH, + C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, + C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, + C_FAMILY => C_FAMILY + ) + port map + ( + SPLB_Clk => SPLB_Clk, + SPLB_Rst => SPLB_Rst, + PLB_ABus => PLB_ABus, + PLB_UABus => PLB_UABus, + PLB_PAValid => PLB_PAValid, + PLB_SAValid => PLB_SAValid, + PLB_rdPrim => PLB_rdPrim, + PLB_wrPrim => PLB_wrPrim, + PLB_masterID => PLB_masterID, + PLB_abort => PLB_abort, + PLB_busLock => PLB_busLock, + PLB_RNW => PLB_RNW, + PLB_BE => PLB_BE, + PLB_MSize => PLB_MSize, + PLB_size => PLB_size, + PLB_type => PLB_type, + PLB_lockErr => PLB_lockErr, + PLB_wrDBus => PLB_wrDBus, + PLB_wrBurst => PLB_wrBurst, + PLB_rdBurst => PLB_rdBurst, + PLB_wrPendReq => PLB_wrPendReq, + PLB_rdPendReq => PLB_rdPendReq, + PLB_wrPendPri => PLB_wrPendPri, + PLB_rdPendPri => PLB_rdPendPri, + PLB_reqPri => PLB_reqPri, + PLB_TAttribute => PLB_TAttribute, + Sl_addrAck => Sl_addrAck, + Sl_SSize => Sl_SSize, + Sl_wait => Sl_wait, + Sl_rearbitrate => Sl_rearbitrate, + Sl_wrDAck => Sl_wrDAck, + Sl_wrComp => Sl_wrComp, + Sl_wrBTerm => Sl_wrBTerm, + Sl_rdDBus => Sl_rdDBus, + Sl_rdWdAddr => Sl_rdWdAddr, + Sl_rdDAck => Sl_rdDAck, + Sl_rdComp => Sl_rdComp, + Sl_rdBTerm => Sl_rdBTerm, + Sl_MBusy => Sl_MBusy, + Sl_MWrErr => Sl_MWrErr, + Sl_MRdErr => Sl_MRdErr, + Sl_MIRQ => Sl_MIRQ, + Bus2IP_Clk => ipif_Bus2IP_Clk, + Bus2IP_Reset => ipif_Bus2IP_Reset, + IP2Bus_Data => ipif_IP2Bus_Data, + IP2Bus_WrAck => ipif_IP2Bus_WrAck, + IP2Bus_RdAck => ipif_IP2Bus_RdAck, + IP2Bus_Error => ipif_IP2Bus_Error, + Bus2IP_Addr => ipif_Bus2IP_Addr, + Bus2IP_Data => ipif_Bus2IP_Data, + Bus2IP_RNW => ipif_Bus2IP_RNW, + Bus2IP_BE => ipif_Bus2IP_BE, + Bus2IP_CS => ipif_Bus2IP_CS, + Bus2IP_RdCE => ipif_Bus2IP_RdCE, + Bus2IP_WrCE => ipif_Bus2IP_WrCE + ); + + ------------------------------------------ + -- instantiate User Logic + ------------------------------------------ + USER_LOGIC_I : entity plbv46_2_wb_v1_00_a.user_logic + generic map + ( + -- MAP USER GENERICS BELOW THIS LINE --------------- + C_WB_DBUS_SIZE => C_WB_DBUS_SIZE, + C_WB_ACCESS_TIMEOUT => C_WB_ACCESS_TIMEOUT, + C_WB_RETRY_TIMEOUT => C_WB_RETRY_TIMEOUT, + C_WB_ACCESS_RETRIES => C_WB_ACCESS_RETRIES, + -- MAP USER GENERICS ABOVE THIS LINE --------------- + + C_SLV_AWIDTH => USER_SLV_AWIDTH, + C_SLV_DWIDTH => USER_SLV_DWIDTH, + C_NUM_MEM => USER_NUM_MEM + ) + port map + ( + -- MAP USER PORTS BELOW THIS LINE ------------------ + + WB_CLK_O => WB_CLK_O , + WB_RST_O => WB_RST_O , + WB_ADR_O => WB_ADR_O , + WB_DAT_O => WB_DAT_O , + WB_SEL_O => WB_SEL_O , + WB_CYC_O => WB_CYC_O , + WB_STB_O => WB_STB_O , + WB_WE_O => WB_WE_O , + WB_DAT_I => WB_DAT_I , + WB_ACK_I => WB_ACK_I , + WB_ERR_I => WB_ERR_I , + WB_RTY_I => WB_RTY_I , + + + --USER ports mapped here + -- MAP USER PORTS ABOVE THIS LINE ------------------ + + Bus2IP_Clk => ipif_Bus2IP_Clk, + Bus2IP_Reset => ipif_Bus2IP_Reset, + Bus2IP_Addr => ipif_Bus2IP_Addr, + Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1), + Bus2IP_RNW => ipif_Bus2IP_RNW, + Bus2IP_Data => ipif_Bus2IP_Data, + Bus2IP_BE => ipif_Bus2IP_BE, + IP2Bus_Data => user_IP2Bus_Data, + IP2Bus_RdAck => user_IP2Bus_RdAck, + IP2Bus_WrAck => user_IP2Bus_WrAck, + IP2Bus_Error => user_IP2Bus_Error + ); + + ------------------------------------------ + -- connect internal signals + ------------------------------------------ + WB_LOCK_O <= '0'; + + ipif_IP2Bus_Data <= user_IP2Bus_Data; + ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; + ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; + ipif_IP2Bus_Error <= user_IP2Bus_Error; + +end IMP; Index: trunk/pcore/plbv46_2_wb_v1_10_a/hdl/vhdl/user_logic.vhd =================================================================== --- trunk/pcore/plbv46_2_wb_v1_10_a/hdl/vhdl/user_logic.vhd (nonexistent) +++ trunk/pcore/plbv46_2_wb_v1_10_a/hdl/vhdl/user_logic.vhd (revision 2) @@ -0,0 +1,278 @@ +------------------------------------------------------------------------------ +-- +-- *************************************************************************** +-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. ** +-- ** ** +-- ** Xilinx, Inc. ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** +-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** +-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** +-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** +-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** +-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** +-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** +-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** +-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** +-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** +-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** +-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** +-- ** FOR A PARTICULAR PURPOSE. ** +-- ** ** +-- *************************************************************************** +-- +------------------------------------------------------------------------------ +-- Filename: user_logic.vhd +-- Version: 1.10.a +-- Description: User logic. +------------------------------------------------------------------------------ + +-- DO NOT EDIT BELOW THIS LINE -------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library proc_common_v2_00_a; +use proc_common_v2_00_a.proc_common_pkg.all; + + +------------------------------------------------------------------------------ +-- Entity section +------------------------------------------------------------------------------ + +entity user_logic is + generic + ( + -- ADD USER GENERICS BELOW THIS LINE --------------- + C_WB_DBUS_SIZE : integer := 32; + C_WB_ACCESS_TIMEOUT : integer := 16; + C_WB_RETRY_TIMEOUT : integer := 256; + C_WB_ACCESS_RETRIES : integer := 4; + -- ADD USER GENERICS ABOVE THIS LINE --------------- + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol parameters, do not add to or delete + C_SLV_AWIDTH : integer := 32; + C_SLV_DWIDTH : integer := 32; + C_NUM_MEM : integer := 1 + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + port + ( + -- ADD USER PORTS BELOW THIS LINE ------------------ + WB_CLK_O : out std_logic; + WB_RST_O : out std_logic; + WB_ADR_O : out std_logic_vector(31 downto 0); + WB_DAT_O : out std_logic_vector(C_WB_DBUS_SIZE-1 downto 0); + WB_SEL_O : out std_logic_vector((C_WB_DBUS_SIZE/8)-1 downto 0); + WB_CYC_O : out std_logic; + WB_STB_O : out std_logic; + WB_WE_O : out std_logic; + WB_DAT_I : in std_logic_vector(C_WB_DBUS_SIZE-1 downto 0); + WB_ACK_I : in std_logic; + WB_ERR_I : in std_logic; + WB_RTY_I : in std_logic; + -- ADD USER PORTS ABOVE THIS LINE ------------------ + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol ports, do not add to or delete + Bus2IP_Clk : in std_logic; + Bus2IP_Reset : in std_logic; + Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1); + Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1); + Bus2IP_RNW : in std_logic; + Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1); + Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1); + IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1); + IP2Bus_RdAck : out std_logic; + IP2Bus_WrAck : out std_logic; + IP2Bus_Error : out std_logic + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + + attribute SIGIS : string; + attribute SIGIS of Bus2IP_Clk : signal is "CLK"; + attribute SIGIS of Bus2IP_Reset : signal is "RST"; + +end entity user_logic; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ +architecture IMP of user_logic is + + -- State Machine Declarations + type state_type is (ST_IDLE, ST_ACCESS, ST_RETRY_STROBE, ST_RETRY, ST_ERROR, ST_DONE); + signal curr_st : state_type; + signal next_st : state_type; + -- Bus Ack Decode + signal wb_rdack : std_logic; + signal wb_wrack : std_logic; + -- Timer used to track bus error condition and retry timouts. + signal timer_en : std_logic; + signal timer_cnt : std_logic_vector(0 to 7); + -- Counter used to track number of retry attempts + signal retry_iter : std_logic_vector(0 to 1); + signal retry_iter_rst : std_logic; + signal retry_iter_en : std_logic; + -- Status Signals + signal retry_expire : std_logic; -- Maximum Retries exceeded + signal access_to : std_logic; -- Bus Error Detected + signal retry_to : std_logic; -- Retry cycle completed + +begin + + -- + -- We are not buffering these signals to the WB Bus. + -- Nor are we running the clock at a slower rate than the PLB Bus. + WB_CLK_O <= Bus2IP_Clk; + WB_RST_O <= Bus2IP_Reset; + + -- These can probably be treated as multi-cycle paths + -- Possibly will add in a Pipeline stage (user selectable?) + WB_ADR_O <= Bus2IP_Addr; + WB_DAT_O <= Bus2IP_Data; + WB_SEL_O <= Bus2IP_BE; + WB_WE_O <= not Bus2IP_RNW; + + -- + -- Number of retry attempts + -- + process(Bus2IP_Clk) begin + if (rising_edge(Bus2IP_Clk)) then + if (retry_iter_rst = '1') then + retry_iter <= (others=>'0'); + elsif (retry_iter_en = '1') then + retry_iter <= retry_iter + 1; + end if; + + retry_expire <= '0'; + if (retry_iter = conv_std_logic_vector(C_WB_ACCESS_RETRIES-1,2)) then + retry_expire <= '1'; + end if; + end if; + end process; + + -- + -- Retry Wait Counter + -- + process(Bus2IP_Clk) begin + if (rising_edge(Bus2IP_Clk)) then + if (timer_en = '0') then + timer_cnt <= (others => '0'); + else + timer_cnt <= timer_cnt + 1; + end if; + + retry_to <= '0'; + if (timer_cnt = conv_std_logic_vector(C_WB_RETRY_TIMEOUT-1, 8)) then + retry_to <= '1'; + end if; + + if (timer_cnt = conv_std_logic_vector(C_WB_ACCESS_TIMEOUT-1, 8)) then + access_to <= '1'; + end if; + + end if; + end process; + + -- + -- + -- WB Bridge State Machine (Next State Logic) + -- + -- + process(curr_st, Bus2IP_CS ,WB_RTY_I ,WB_ACK_I, retry_to, access_to) begin + + next_st <= curr_st; + timer_en <= '0'; + retry_iter_rst <= '0'; + retry_iter_en <= '0'; + WB_STB_O <= '0'; + WB_CYC_O <= '0'; + IP2Bus_RdAck <= '0'; + IP2Bus_WrAck <= '0'; + IP2Bus_Error <= '0'; + + case (curr_st) is + + + when ST_IDLE => + retry_iter_rst <= '1'; + if (Bus2IP_CS(0) = '1') then + next_st <= ST_ACCESS; + end if; + + -- Access State + -- Completes when we receive either a RETRY, ACK or we timeout of the transaction. + -- Transaction timeout is setup by the user. + when ST_ACCESS => + WB_STB_O <= '1'; + WB_CYC_O <= '1'; + timer_en <= '1'; + if (WB_RTY_I = '1') then + next_st <= ST_RETRY_STROBE; + elsif (WB_ACK_I = '1') then + next_st <= ST_DONE; + elsif (access_to = '1') then + next_st <= ST_ERROR; + end if; + + -- Retry Strobe + -- Simply used to reset timer and increment our retries. + -- We will also check to see if we have reached out limit of retries. + when ST_RETRY_STROBE => + retry_iter_en <= '1'; + if (retry_expire = '1') then + next_st <= ST_ERROR; + else + next_st <= ST_RETRY; + end if; + + -- Retry + -- Sit here and wait until we issues a WB Retry + when ST_RETRY => + timer_en <= '1'; + if (retry_to = '1') then + next_st <= ST_ACCESS; + end if; + + -- Error + -- Issue PLB Error + when ST_ERROR => + IP2Bus_Error <= '1'; + IP2Bus_WrAck <= not Bus2IP_RNW; + IP2Bus_RdAck <= Bus2IP_RNW; + next_st <= ST_IDLE; + + when ST_DONE => + IP2Bus_RdAck <= Bus2IP_RNW; + IP2Bus_WrAck <= not Bus2IP_RNW; + next_st <= ST_IDLE; + + + end case; + + end process; + + -- + -- + -- WB Bridge State Machine (Current State Logic) + -- + -- + process(Bus2IP_Clk) begin + if (rising_edge(Bus2IP_Clk)) then + if (Bus2IP_Reset = '1') then + curr_st <= ST_IDLE; + else + curr_st <= next_st; + end if; + end if; + end process; + + ------------------------------------------ + -- Example code to drive IP to Bus signals + ------------------------------------------ + IP2Bus_Data <= WB_DAT_I when wb_rdack = '1' else + (others => '0'); + +end IMP; Index: trunk/pcore/plbv46_2_wb_v1_10_a/data/plbv46_2_wb_v2_1_0.pao =================================================================== --- trunk/pcore/plbv46_2_wb_v1_10_a/data/plbv46_2_wb_v2_1_0.pao (nonexistent) +++ trunk/pcore/plbv46_2_wb_v1_10_a/data/plbv46_2_wb_v2_1_0.pao (revision 2) @@ -0,0 +1,16 @@ +############################################################################## +## Description: Peripheral Analysis Order +############################################################################## + +lib proc_common_v2_00_a proc_common_pkg vhdl +lib proc_common_v2_00_a ipif_pkg vhdl +lib proc_common_v2_00_a or_muxcy vhdl +lib proc_common_v2_00_a or_gate128 vhdl +lib proc_common_v2_00_a family_support vhdl +lib proc_common_v2_00_a pselect_f vhdl +lib proc_common_v2_00_a counter_f vhdl +lib plbv46_slave_single_v1_00_a plb_address_decoder vhdl +lib plbv46_slave_single_v1_00_a plb_slave_attachment vhdl +lib plbv46_slave_single_v1_00_a plbv46_slave_single vhdl +lib plbv46_2_wb_v1_10_a user_logic vhdl +lib plbv46_2_wb_v1_10_a plbv46_2_wb vhdl Index: trunk/pcore/plbv46_2_wb_v1_10_a/data/plbv46_2_wb_v2_1_0.mpd =================================================================== --- trunk/pcore/plbv46_2_wb_v1_10_a/data/plbv46_2_wb_v2_1_0.mpd (nonexistent) +++ trunk/pcore/plbv46_2_wb_v1_10_a/data/plbv46_2_wb_v2_1_0.mpd (revision 2) @@ -0,0 +1,111 @@ +################################################################### +## +## Name : plbv46_2_wb +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN plbv46_2_wb + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = VHDL +OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT) +OPTION IP_GROUP = MICROBLAZE:PPC:Bus and Bridge +OPTION DESC = PLBv46 to Wishbone B3 Bridge + + +## Bus Interfaces +BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46 + +## Generics for VHDL or Parameters for Verilog +PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT +PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128) +PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16) +PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4) +PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT +PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1) +PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT +PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128) +PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB +PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1) +PARAMETER C_FAMILY = virtex5, DT = STRING +PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM0_HIGHADDR +PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM0_BASEADDR + +PARAMETER C_WB_ACCESS_TIMEOUT = 16, DT = INTEGER, RANGE = (1:256) +PARAMETER C_WB_RETRY_TIMEOUT = 256, DT = INTEGER, RANGE = (1:256) +PARAMETER C_WB_ACCESS_RETRIES = 4, DT = INTEGER, RANGE = (1:4) +PARAMETER C_WB_DBUS_SIZE = 32, DT = INTEGER, ASSIGNMENT = CONSTANT + +## Ports +PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB +PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB +PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB +PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB +PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB +PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB +PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB +PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB +PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB +PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB +PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB +PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB +PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB +PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB +PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB +PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB +PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB +PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB +PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB +PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB +PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB +PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB +PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB +PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB +PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB +PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB +PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB +PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB +PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB +PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB +PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB +PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB +PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB +PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB +PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB +PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB +PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB +PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB +PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB +PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB +PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB +PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB + + + + +PORT WB_CLK_O = "", DIR = O +PORT WB_RST_O = "", DIR = O +PORT WB_ADR_O = "", DIR = O, VEC = [31:0] +PORT WB_DAT_O = "", DIR = O, VEC = [C_WB_DBUS_SIZE-1:0] +PORT WB_SEL_O = "", DIR = O, VEC = [(C_WB_DBUS_SIZE/8)-1:0] +PORT WB_CYC_O = "", DIR = O +PORT WB_LOCK_O = "", DIR = O +PORT WB_STB_O = "", DIR = O +PORT WB_WE_O = "", DIR = O +PORT WB_DAT_I = "", DIR = I, VEC = [C_WB_DBUS_SIZE-1:0] +PORT WB_ACK_I = "", DIR = I +PORT WB_ERR_I = "", DIR = I +PORT WB_RTY_I = "", DIR = I + + + + + + + + +END Index: trunk/pcore/plbv46_2_wb_v1_10_a/readme.txt ===================================================================