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/robust_ahb_matrix/trunk/src/gen/prgen_arbiter.v
0,0 → 1,132
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE prgen_arbiter_MSTR_SLV_MSTRNUM_SLVNUM.v
 
ITER MX MSTRNUM
ITER SX SLVNUM
 
CHECK CONST(#FFD) ##flip-flop delay
CHECK CONST(PREFIX) ##flip-flop delay
CHECK CONST(MSTR_SLV) ##arbiter type: mstr or slv
CHECK CONST(MSTRNUM) ##master num
CHECK CONST(SLVNUM) ##slave num
module prgen_arbiter_MSTR_SLV_MSTRNUM_SLVNUM(PORTS);
 
input clk;
input reset;
 
input [MSTRNUM-1:0] M_last;
input [MSTRNUM-1:0] M_req;
input [MSTRNUM-1:0] M_grant;
input [LOG2(SLVNUM)-1:0] MMX_slave;
output [MSTRNUM-1:0] SSX_master;
 
 
reg [MSTRNUM:0] SSX_master_prio_reg;
wire [MSTRNUM-1:0] SSX_master_prio;
reg [MSTRNUM-1:0] SSX_master_d;
wire [MSTRNUM-1:0] M_SSX;
wire [MSTRNUM-1:0] M_SSX_valid;
wire [MSTRNUM-1:0] M_SSX_prio;
reg [MSTRNUM-1:0] M_SSX_burst;
 
 
parameter MASTER_NONE = BIN(0 MSTRNUM);
parameter MASTERMX = BIN(EXPR(2^MX) MSTRNUM);
 
IFDEF DEF_PRIO
always @(posedge clk or posedge reset)
if (reset)
begin
SSX_master_prio_reg[MSTRNUM:1] <= #FFD {MSTRNUM{1'b0}};
SSX_master_prio_reg[0] <= #FFD 1'b1;
end
else if (|(M_req & M_grant & M_last))
begin
SSX_master_prio_reg[MSTRNUM:1] <= #FFD SSX_master_prio_reg[MSTRNUM-1:0];
SSX_master_prio_reg[0] <= #FFD SSX_master_prio_reg[MSTRNUM-1];
end
 
assign SSX_master_prio = SSX_master_prio_reg[MSTRNUM-1:0];
assign M_SSX_prio = M_SSX_valid & SSX_master_prio;
ENDIF DEF_PRIO
 
 
always @(posedge clk or posedge reset)
if (reset)
begin
SSX_master_d <= #FFD {MSTRNUM{1'b0}};
end
else
begin
SSX_master_d <= #FFD SSX_master;
end
 
LOOP MX MSTRNUM
always @(posedge clk or posedge reset)
if (reset)
begin
M_SSX_burst[MX] <= #FFD 1'b0;
end
else if (M_req[MX])
begin
M_SSX_burst[MX] <= #FFD SSX_master[MX] & (M_grant[MX] ? (~M_last[MX]) : 1'b1);
end
ENDLOOP MX
assign M_SSX = {CONCAT(MMX_slave == 'dSX ,)};
assign M_SSX_valid = M_SSX & M_req;
LOOP SX SLVNUM
assign SSX_master =
|M_SSX_burst ? SSX_master_d :
IF DEF_PRIO M_SSX_prio[MX] ? MASTERMX :
M_SSX_valid[MX] ? MASTERMX :
MASTER_NONE;
ENDLOOP SX
endmodule
 
/robust_ahb_matrix/trunk/src/base/def_ahb_matrix_static.txt
0,0 → 1,32
SWAP MSTRS MASTER_NUM
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DECERR_SLV))
 
LOOP MX MSTRS
LOOP SX SLVS
 
SWAP MSTR_BITS LOG2(MSTRS)
SWAP SLV_BITS LOG2(SLVS)
 
SWAP SERR EXPR(SLVS-1)
 
 
 
GROUP AHB_CMD is {
HADDR ADDR_BITS input
HBURST 3 input
HSIZE 2 input
HTRANS 2 input
HWRITE 1 input
}
 
GROUP AHB_RESP is {
HWDATA DATA_BITS input
HRDATA DATA_BITS output
HRESP 1 output
}
 
GROUP AHB joins {
GROUP AHB_CMD
GROUP AHB_RESP
HREADY 1 output
}
/robust_ahb_matrix/trunk/src/base/ahb_matrix.v
0,0 → 1,127
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX.v
INCLUDE def_ahb_matrix.txt
 
ITER MX
ITER SX
module PREFIX(PORTS);
 
input clk;
input reset;
port MMX_GROUP_AHB;
revport SSX_GROUP_AHB;
 
 
wire [MSTRS-1:0] SSX_mstr;
wire [SLV_BITS-1:0] MMX_slv;
 
wire MMX_HLAST;
wire SSX_MMX;
wire SSX_MMX_resp;
 
 
CREATE ahb_matrix_dec.v
PREFIX_dec
PREFIX_dec (
.MMX_HADDR(MMX_HADDR),
.MMX_slv(MMX_slv),
STOMP ,
);
 
 
CREATE ahb_matrix_hlast.v
PREFIX_hlast
PREFIX_hlast(
.clk(clk),
.reset(reset),
.MMX_HTRANS(MMX_HTRANS),
.MMX_HREADY(MMX_HREADY),
.MMX_HBURST(MMX_HBURST),
.MMX_HLAST(MMX_HLAST),
STOMP ,
);
CREATE prgen_arbiter.v DEFCMD(SWAP CONST(PREFIX) PREFIX) DEFCMD(SWAP MSTR_SLV mstr) DEFCMD(SWAP MSTRNUM MSTRS) DEFCMD(SWAP SLVNUM SLVS) DEFCMD(DEFINE DEF_PRIO)
prgen_arbiter_mstr_MSTRS_SLVS
prgen_arbiter_mstr_MSTRS_SLVS(
.clk(clk),
.reset(reset),
.MMX_slave(MMX_slv),
.SSX_master(SSX_mstr),
.M_last({CONCAT(MMX_HLAST ,)}),
.M_req({CONCAT(MMX_HTRANS[1] ,)}),
.M_grant({CONCAT(MMX_HREADY ,)})
);
 
CREATE ahb_matrix_sel.v
PREFIX_sel
PREFIX_sel (
.clk(clk),
.reset(reset),
.SSX_mstr(SSX_mstr),
.SSX_HREADY(SSX_HREADY),
.SSX_MMX(SSX_MMX),
.SSX_MMX_resp(SSX_MMX_resp),
STOMP ,
);
 
CREATE ahb_matrix_bus.v
PREFIX_bus
PREFIX_bus (
.clk(clk),
.reset(reset),
.MMX_GROUP_AHB(MMX_GROUP_AHB),
.SSX_GROUP_AHB(SSX_GROUP_AHB),
.SSX_MMX(SSX_MMX),
.SSX_MMX_resp(SSX_MMX_resp),
STOMP ,
);
 
endmodule
 
 
 
 
/robust_ahb_matrix/trunk/src/base/ahb_matrix_sel.v
0,0 → 1,72
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_sel.v
INCLUDE def_ahb_matrix.txt
 
ITER MX
ITER SX
module PREFIX_sel(PORTS);
 
input clk;
input reset;
 
input [MSTRS-1:0] SSX_mstr;
input SSX_HREADY;
output SSX_MMX;
output SSX_MMX_resp;
 
 
reg [MSTRS-1:0] SSX_mstr_resp;
 
 
LOOP SX
always @(posedge clk or posedge reset)
if (reset)
SSX_mstr_resp <= #FFD {MSTRS{1'b0}};
else if (SSX_HREADY)
SSX_mstr_resp <= #FFD SSX_mstr;
 
ENDLOOP SX
 
assign SSX_MMX = SSX_mstr[MX];
assign SSX_MMX_resp = SSX_mstr_resp[MX];
endmodule
 
 
 
 
/robust_ahb_matrix/trunk/src/base/def_ahb_matrix.txt
0,0 → 1,15
 
INCLUDE def_ahb_matrix_static.txt
 
SWAP.GLOBAL #FFD #1 ##flip-flop delay
 
SWAP PREFIX ahb_matrix_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
 
SWAP MASTER_NUM 3 ##number of masters
SWAP SLAVE_NUM 6 ##number of slaves
 
DEFINE DEF_DECERR_SLV ##use interanl decode slave error
 
SWAP DATA_BITS 32 ##AHB data bits
SWAP ADDR_BITS 32 ##AHB address bits
 
/robust_ahb_matrix/trunk/src/base/ahb_matrix_bus.v
0,0 → 1,76
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_bus.v
INCLUDE def_ahb_matrix.txt
 
ITER MX
ITER SX
module PREFIX_bus(PORTS);
 
input clk;
input reset;
port MMX_GROUP_AHB;
revport SSX_GROUP_AHB;
 
input SSX_MMX;
input SSX_MMX_resp;
 
parameter BUS_WIDTH = GONCAT(GROUP_AHB.IN.WIDTH +);
 
wire [BUS_WIDTH-1:0] SSX_BUS;
wire [BUS_WIDTH-1:0] MMX_BUS;
 
assign MMX_BUS = {GONCAT(MMX_GROUP_AHB_CMD.IN ,)};
assign SSX_BUS = CONCAT((MMX_BUS & {BUS_WIDTH{SSX_MMX}}) |);
assign {GONCAT(SSX_GROUP_AHB_CMD.IN ,)} = SSX_BUS;
 
assign SSX_HWDATA = CONCAT((MMX_HWDATA & {DATA_BITS{SSX_MMX_resp}}) |);
LOOP MX
assign MMX_GROUP_AHB_RESP.OUT = CONCAT(({GROUP_AHB_RESP.OUT.WIDTH{SSX_MMX_resp}} & SSX_GROUP_AHB_RESP.OUT) |);
assign MMX_HREADY = CONCAT(((SSX_MMX|SSX_MMX_resp)&SSX_HREADY) |);
ENDLOOP MX
endmodule
 
 
 
 
/robust_ahb_matrix/trunk/src/base/ahb_matrix_dec.v
0,0 → 1,62
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_dec.v
INCLUDE def_ahb_matrix.txt
 
ITER MX
ITER SX
 
module PREFIX_dec (PORTS);
 
input [ADDR_BITS-1:0] MMX_HADDR;
output [SLV_BITS-1:0] MMX_slv;
parameter DEC_MSB = ADDR_BITS - 1;
parameter DEC_LSB = ADDR_BITS - SLV_BITS;
reg [SLV_BITS-1:0] MMX_slv;
LOOP MX
always @(*)
begin
case (MMX_HADDR[DEC_MSB:DEC_LSB])
BIN(SX SLV_BITS) : MMX_slv = 'dSX;
 
default : MMX_slv = 'dSERR;
endcase
end
 
ENDLOOP MX
endmodule
 
 
 
/robust_ahb_matrix/trunk/src/base/ahb_matrix_hlast.v
0,0 → 1,81
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_hlast.v
INCLUDE def_ahb_matrix.txt
 
ITER MX
 
module PREFIX_hlast (PORTS);
 
input clk;
input reset;
input [1:0] MMX_HTRANS;
input MMX_HREADY;
input [2:0] MMX_HBURST;
output MMX_HLAST;
 
parameter TRANS_IDLE = 2'b00;
parameter TRANS_BUSY = 2'b01;
parameter TRANS_NONSEQ = 2'b10;
parameter TRANS_SEQ = 2'b11;
 
parameter BURST_SINGLE = 3'b000;
parameter BURST_INCR4 = 3'b011;
parameter BURST_INCR8 = 3'b101;
parameter BURST_INCR16 = 3'b111;
 
 
reg [3:0] MMX_count;
 
 
assign MMX_HLAST = (MMX_count == 'd1) | ((MMX_HTRANS == TRANS_NONSEQ) & MMX_HREADY & (MMX_HBURST == BURST_SINGLE));
 
LOOP MX
always @(posedge clk or posedge reset)
if (reset)
MMX_count <= #FFD 4'd15;
else if ((MMX_HTRANS == TRANS_NONSEQ) & MMX_HREADY)
MMX_count <= #FFD
(MMX_HBURST == BURST_INCR4) ? 4'd3 :
(MMX_HBURST == BURST_INCR8) ? 4'd7 :
(MMX_HBURST == BURST_INCR16) ? 4'd15 :
4'd0;
else if ((MMX_HTRANS == TRANS_SEQ) & MMX_HREADY)
MMX_count <= #FFD MMX_count - 1'b1;
 
ENDLOOP MX
 
endmodule
 
 
 
/robust_ahb_matrix/trunk/README.txt
0,0 → 1,23
 
------------------------------ Remark ----------------------------------------
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
 
We will be very happy to receive any kind of feedback regarding our tools and cores.
We will also be willing to support any company intending to integrate our cores into their project.
For any questions / remarks / suggestions / bugs please contact info@provartec.com.
------------------------------------------------------------------------------
 
RobustVerilog generic AHB matrix
 
In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
 
The RobustVerilog top source file is ahb_matrix.v, it calls the top definition file named def_ahb_matrix.txt.
 
The default definition file def_ic.txt generates a fabric with 3 masters and 6 slaves.
 
Changing the interconnect parameters should be made only in def_ahb_matrix.txt in the src/base directory (changing master num, slave num etc.).
 
 
 
 

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