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/rs_encoder_decoder/rtl/GF8lfsr.v
0,0 → 1,38
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Generic
// Bit Serial Hardware Multiplier
 
module GF8lfsr(clk_i, rst_i,
en_i, // Valid Input Set it to High When giving the input
lfsr_o // Gallios Field Generic Bit Serial Multiplier output
);
// Inputs are declared here
input clk_i,rst_i; // Clock and Reset Declaration
input en_i;
output reg [7:0] lfsr_o;
// Declaration of Wires And Register are here
 
always @(posedge clk_i or posedge rst_i) begin
if(rst_i) begin
lfsr_o[7] <=1'b0;
lfsr_o[6] <=1'b0;
lfsr_o[5] <=1'b0;
lfsr_o[4] <=1'b0;
lfsr_o[3] <=1'b0;
lfsr_o[2] <=1'b0;
lfsr_o[1] <=1'b0;
lfsr_o[0] <=1'b1;
end
else if(en_i) begin
lfsr_o[1] <= lfsr_o[0];
lfsr_o[2] <= lfsr_o[1]^lfsr_o[7];
lfsr_o[3] <= lfsr_o[2]^lfsr_o[7];
lfsr_o[4] <= lfsr_o[3]^lfsr_o[7];
lfsr_o[5] <= lfsr_o[4];
lfsr_o[6] <= lfsr_o[5];
lfsr_o[7] <= lfsr_o[6];
lfsr_o[0] <= lfsr_o[7];
end
end
endmodule
/rs_encoder_decoder/rtl/RS8Encoder_testbench.v
0,0 → 1,74
`timescale 1ns / 10 ps
 
module RS8Encoder_testbench;
reg clk_i,rst_i;
reg valid_i;
reg [7:0] enc_data_i;
wire [7:0] enc_data_o;
wire parity_o;
wire busy_o;
reg [126*7:0] path,input_file,output_file;
integer fd_in, fd_out;
reg [8:0] wait_cntr;
RS8Encoder8t DUT(.clk_i(clk_i), .rst_i(rst_i),
.encoder_i(enc_data_i), // Input to the encoder
.valid_i(valid_i), // set this when input is set
.encoder_o(enc_data_o), // output of the encoder
.parity_o(parity_o), // Valid signal is set when the output is available on the output line
.busy_o(busy_o) // Busy Signal When busy signal is high during the encoding process Please dont
); // give input to the incoder
// This is an input counter the purpose of this is to set the input to zero in the start
// of the encoding process
 
always @(posedge clk_i) begin
if(rst_i)
wait_cntr <= 0;
else
wait_cntr <= wait_cntr + 1;
end
always
#5 clk_i = !clk_i;
initial begin
path = "./";
// These are the input files that can be used in the encoder
// you can select any information bit generation
input_file = "input_file_RSEncodeData.dat";
output_file = "output_file_RSVerilogEncodedData.dat";
fd_in = $fopen(input_file,"r");
fd_out = $fopen(output_file,"w");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
enc_data_i = 0;
 
while(1)
begin
@(posedge clk_i);
if(wait_cntr < 4) begin
valid_i = 0;
enc_data_i = 0;
end
else if((wait_cntr >=4)&&(wait_cntr<=243)) begin // give the input to the encoder when the encoder is not busy
valid_i = 1;
$fscanf(fd_in,"%d\n",enc_data_i); // The input to the encoder should be given at continous clocks and atease 239 packets at a time
end
else if ((wait_cntr>243)&&(wait_cntr <= 259)) begin
valid_i =1;
enc_data_i =0;
end
else if (wait_cntr > 259) begin
valid_i =0;
enc_data_i =0;
end
if(parity_o)
$fwrite(fd_out,"%d \n",enc_data_o); // Write the output of the encoded data
end
end // initial begin
 
endmodule
/rs_encoder_decoder/rtl/GF8Inverse_testbench.v
0,0 → 1,58
`timescale 1ns / 10 ps
 
module GF8GenInverse_testbench;
reg clk_i,rst_i;
wire [7:0] inv_o;
wire valid_o;
reg [7:0] inv_i;
reg valid_i;
reg [126*7:0] path,input_file,output_file;
reg [7:0] cntr;
integer fd_in,fd_out;
GF8Inverse DUT(.clk_i(clk_i),.rst_i(rst_i),
.valid_i(valid_i),
.inv_i(inv_i),
.valid_o(valid_o),
.inv_o(inv_o));
always @(posedge clk_i) begin
if (rst_i) begin
cntr <= 0;
end else if (valid_o) begin
cntr <= 0;
end else begin
cntr <= cntr+1;
end
end
always
#5 clk_i = !clk_i;
initial begin
path = "./";
input_file = "input_file_GF8Inverse.dat";
output_file = "output_file_GF8Inverse.dat";
fd_in = $fopen(input_file,"r");
fd_out = $fopen(output_file,"w");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
 
while(!$feof(fd_in))
begin
@(negedge clk_i);
if(cntr == 1) begin
valid_i = 1;
end else begin
valid_i = 0;
end
if(valid_i) begin
$fscanf(fd_in,"%d\n",inv_i);
$fwrite(fd_out,"%d\n",inv_o);
end
end
end // initial begin
 
endmodule
/rs_encoder_decoder/rtl/GF8GenMult_testbench.v
0,0 → 1,38
`timescale 1ns / 10 ps
 
module GF8GenMult_testbench;
reg clk_i,rst_i;
wire [7:0] mult_o;
reg [7:0] mult_i1,mult_i2;
reg [126*7:0] path,input_file,output_file;
integer fd_in,fd_out;
GF8GenMult DUT(
.mult_i1(mult_i1),
.mult_i2(mult_i2),
.mult_o(mult_o));
always
#5 clk_i = !clk_i;
initial begin
path = "./";
input_file = "input_file_GF8Mult.dat";
output_file = "output_file_GF8Mult.dat";
fd_in = $fopen(input_file,"r");
fd_out = $fopen(output_file,"w");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
 
while(!$feof(fd_in))
begin
@(negedge clk_i);
$fscanf(fd_in,"%d %d\n",mult_i1,mult_i2);
$fwrite(fd_out,"%d\n",mult_o);
end
end // initial begin
 
endmodule
/rs_encoder_decoder/rtl/GF8Inverse.v
0,0 → 1,104
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field
// Hardware Inversion Circuit takes m-1 clockcycles
 
module GF8Inverse(clk_i, rst_i,
valid_i, // Valid Input Set it to High When giving the input
inv_i, // Gallios Field Inverter input
valid_o, // Valid Out High When The output is ready
inv_o // Gallios Field Inversion output
);
// Inputs are declared here
input clk_i,rst_i; // Clock and Reset Declaration
input valid_i;
input [7:0] inv_i;
output reg valid_o;
output wire [7:0] inv_o;
// Declaration of Wires And Register are here
reg [7:0] regSquare, regMult;
reg [2:0] cnt;
reg [0:0] state;
wire [7:0] multSquare_o, multMult_o;
 
assign inv_o = regMult;
 
GF8GenMult SQUARE(
.mult_i1(regSquare), // Gallios Field Generic Multiplier input 1
.mult_i2(regSquare), // Gallios Field Generic Multiplier input 2
.mult_o(multSquare_o)); // Gallios Field Generic Multiplier output
GF8GenMult MULTIPLY(
.mult_i1(multSquare_o), // Gallios Field Generic Multiplier input 1
.mult_i2(regMult), // Gallios Field Generic Multiplier input 2
.mult_o(multMult_o)); // Gallios Field Generic Multiplier output
parameter WAIT = 1'b0;
parameter PROCESS = 1'b1;
// CONTROLLER TO VALIDATE THE OUTPUT
always @(posedge clk_i) begin
if(rst_i) begin
cnt = 0;
regSquare <= 0;
regMult <= 0;
valid_o <= 0;
state <= WAIT;
end
else begin
case(state)
WAIT: if(valid_i) begin
// State machine
state <= PROCESS;
 
// REGISTER
regSquare<= inv_i;
regMult[0]<= 1'b1;
regMult[1]<= 1'b0;
regMult[2]<= 1'b0;
regMult[3]<= 1'b0;
regMult[4]<= 1'b0;
regMult[5]<= 1'b0;
regMult[6]<= 1'b0;
regMult[7]<= 1'b0;
 
// VALIDATION
cnt = 0;
valid_o <= 0;
end else begin
// State machine
state <= WAIT;
 
// REGISTER
regSquare <= 0;
regMult <= 0;
 
// VALIDATION
valid_o <= 0;
cnt = 0;
end
PROCESS: if(cnt == 7) begin
// State machine
state <= WAIT;
 
// REGISTER
regSquare <= regSquare;
regMult <= regMult;
 
// VALIDATION
cnt = 0;
valid_o <= 1;
end else begin
// State machine
state <= PROCESS;
 
// REGISTER
regSquare <= multSquare_o;
regMult <= multMult_o;
 
// VALIDATION
cnt = cnt + 1;
valid_o <= 0;
end
default : state <= WAIT;
endcase
end
end
endmodule
/rs_encoder_decoder/rtl/GF8GenMult.v
0,0 → 1,134
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Generic
// Bit Parallel Hardware Multiplier
 
// THIS BLOCK IS THE IMPLEMENTATION OF MODULE A
module GF8GenMultModA(
modA_i1, // Generic Multiplier Mod A input 1
modA_i2, // Generic Multiplier Mod A input 2
modA_o // Generic Multiplier Mod A output
);
// Inputs are declared here
input [7:0] modA_i1, modA_i2;
output wire modA_o;
 
// Declaration of Wires And Register are here
wire xor0_w0, xor0_w1, xor0_w2, xor0_w3;
wire xor1_w0, xor1_w1;
wire and_w0, and_w1, and_w2, and_w3, and_w4, and_w5, and_w6, and_w7;
 
//LOGIC STARTS FROM HERE
 
assign and_w0 = modA_i1[0] & modA_i2[0];
assign and_w1 = modA_i1[1] & modA_i2[1];
assign and_w2 = modA_i1[2] & modA_i2[2];
assign and_w3 = modA_i1[3] & modA_i2[3];
assign and_w4 = modA_i1[4] & modA_i2[4];
assign and_w5 = modA_i1[5] & modA_i2[5];
assign and_w6 = modA_i1[6] & modA_i2[6];
assign and_w7 = modA_i1[7] & modA_i2[7];
 
assign xor0_w0 = and_w0^and_w1;
assign xor0_w1 = and_w2^and_w3;
assign xor0_w2 = and_w4^and_w5;
assign xor0_w3 = and_w6^and_w7;
 
assign xor1_w0 = xor0_w0^xor0_w1;
assign xor1_w1 = xor0_w2^xor0_w3;
 
assign modA_o = xor1_w0^xor1_w1;
 
endmodule
 
 
 
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Generic
// Bit Parallel Hardware Multiplier
 
// THIS BLOCK IS THE IMPLEMENTATION OF MODULE B
module GF8GenMultModB(
modB_i, // Generic Multiplier Mod B input 1
modB_o // Generic Multiplier Mod B output
);
// Inputs are declared here
input [7:0] modB_i;
output wire [6:0] modB_o;
 
assign modB_o[0] = modB_i[0]^modB_i[2]^modB_i[3]^modB_i[4];
assign modB_o[1] = modB_i[1]^modB_i[3]^modB_i[4]^modB_i[5];
assign modB_o[2] = modB_i[2]^modB_i[4]^modB_i[5]^modB_i[6];
assign modB_o[3] = modB_i[3]^modB_i[5]^modB_i[6]^modB_i[7];
assign modB_o[4] = modB_i[0]^modB_i[2]^modB_i[3]^modB_i[6]^modB_i[7];
assign modB_o[5] = modB_i[0]^modB_i[1]^modB_i[2]^modB_i[7];
assign modB_o[6] = modB_i[0]^modB_i[1]^modB_i[4];
 
endmodule
 
 
 
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Generic
// Bit Parallel Hardware Multiplier
 
module GF8GenMult(
mult_i1, // Gallios Field Generic Multiplier input 1
mult_i2, // Gallios Field Generic Multiplier input 2
mult_o // Gallios Field Generic Multiplier output
);
// Inputs are declared here
input [7:0] mult_i1, mult_i2;
output wire [7:0] mult_o;
// Declaration of Wires And Register are here
wire [6:0] modB_o;
wire [7:0] dual_o, dual_i;
wire [7:0] modA_w [0:6];
assign dual_i[0] = mult_i1[1];
assign dual_i[1] = mult_i1[0];
assign dual_i[2] = mult_i1[7];
assign dual_i[3] = mult_i1[6];
assign dual_i[4] = mult_i1[5];
assign dual_i[5] = mult_i1[4];
assign dual_i[6] = mult_i1[3]^mult_i1[7];
assign dual_i[7] = mult_i1[2]^mult_i1[7]^mult_i1[6];
GF8GenMultModB MODB(
.modB_i(dual_i),
.modB_o(modB_o));
assign modA_w[0] = {modB_o[0],dual_i[7:1]};
assign modA_w[1] = {modB_o[1],modB_o[0],dual_i[7:2]};
assign modA_w[2] = {modB_o[2],modB_o[1],modB_o[0],dual_i[7:3]};
assign modA_w[3] = {modB_o[3],modB_o[2],modB_o[1],modB_o[0],dual_i[7:4]};
assign modA_w[4] = {modB_o[4],modB_o[3],modB_o[2],modB_o[1],modB_o[0],dual_i[7:5]};
assign modA_w[5] = {modB_o[5],modB_o[4],modB_o[3],modB_o[2],modB_o[1],modB_o[0],dual_i[7:6]};
assign modA_w[6] = {modB_o[6],modB_o[5],modB_o[4],modB_o[3],modB_o[2],modB_o[1],modB_o[0],dual_i[7:7]};
 
GF8GenMultModA MODA0(
.modA_i1(dual_i), // Generic Multiplier Mod A input 1
.modA_i2(mult_i2), // Generic Multiplier Mod A input 2
.modA_o(dual_o[0])); // Generic Multiplier Mod A output
genvar j;
generate
for (j=1; j < 8; j = j+1) begin:MODABLOCKS
GF8GenMultModA MODA(
.modA_i1(modA_w[j-1]), // Generic Multiplier Mod A input 1
.modA_i2(mult_i2), // Generic Multiplier Mod A input 2
.modA_o(dual_o[j])); // Generic Multiplier Mod A output
end
endgenerate
assign mult_o[0] = dual_o[1];
assign mult_o[1] = dual_o[0];
assign mult_o[2] = dual_o[7]^dual_o[2]^dual_o[3];
assign mult_o[3] = dual_o[6]^dual_o[2];
assign mult_o[4] = dual_o[5];
assign mult_o[5] = dual_o[4];
assign mult_o[6] = dual_o[3];
assign mult_o[7] = dual_o[2];
endmodule
/rs_encoder_decoder/rtl/RS8Controller.v
0,0 → 1,697
// This is a verilog File Generated
// By The C++ program That Generates
// Reed Solomon Controller
// Barlekamp Messay Controller
 
module RS8Controller(clk_i, rst_i,
valid_i, // Controller input valid
calc_S_0_o, // Control Signal to Calculate S_0
dft_sel_o, // select FFT or IFFT
dft_calc_o, // calculate fourier transform
mem_in_o, // memory control signal to input what in the memory
en_fir_o, // calculate new delta
fir_sel_o, // calculate new delta
calc_bm_step_o, // Calculate BM Step
step_o, // current_step
done_bm_step_i, // update from BM circuit
elp_busy_i, // Controller input busy signal from error loc poly
r_calc_o, // To enable R0 to calculate
r_calc_sel_o, // To enable R0 to select memmory address
r_calc_done_i, // When R0 has completed the operation
push_o, // push data in syndrom
mem_addr_o, // Memmory Address
load_last_o, // This is the first DFT calculation control signal
wren_o, // Write Data IN memmory
done_dec_o, // done BM decoding
last_in_sel_o, // ouput data 0
valid_o_o, // Asserted when data is being outputed from the RS decoder
busy_o // States the Status of the RS decoder
);
// Declaration of the inputs
input clk_i, rst_i;
input valid_i;
output reg dft_calc_o;
output reg [1:0] dft_sel_o;
output reg busy_o;
output reg en_fir_o;
output reg fir_sel_o;
output reg valid_o_o;
// Control Signals associated
output reg calc_S_0_o;
// with Error Loc Poly calculator
output reg calc_bm_step_o;
output wire [7:0] step_o;
input done_bm_step_i;
input elp_busy_i;
// R 0 calculator control signals
input r_calc_done_i; // When R0 has completed the operation
output reg r_calc_sel_o; // R0 memory address select
output reg r_calc_o; // to enable R0 to calculate
 
output reg push_o;
output reg done_dec_o;
// MEMORY ADDRESS AND MEMORY CONTROL SIGNALS
output wire [7:0] mem_addr_o;
output reg mem_in_o;
output reg wren_o;
output reg load_last_o;
output reg last_in_sel_o;
 
// Declaration of Wires And Register are here
// Control Registers
// INPUT COUNTER HANDLER
reg [8:0] input_cntr;
reg clr_input_cntr;
always @ (posedge clk_i) begin
if ((rst_i)||(clr_input_cntr)) begin
input_cntr = 0;
end
else if ((valid_i)&& (~(busy_o))) begin
input_cntr = input_cntr + 1;
end
end
// ErrorPolyCalcStep
reg [7:0] step;
always @ (posedge clk_i) begin
if ((rst_i)||(done_dec_o)) begin
step = 0;
end
else if (done_bm_step_i) begin
step = step + 1;
end
end
reg clr_mem_addr;
reg inc_mem_addr;
reg [7:0] mem_addr;
always @(posedge clk_i) begin
if((rst_i)||(clr_mem_addr)) begin
mem_addr = 0;
end
else if(inc_mem_addr) begin
mem_addr = mem_addr +1;
end
end
reg inc_idft_cntr;
reg clr_idft_cntr;
reg [7:0] idft_cntr;
always @(posedge clk_i) begin
if((rst_i)||(clr_idft_cntr)) begin
idft_cntr = 0;
end
else if(inc_idft_cntr) begin
idft_cntr = idft_cntr +1;
end
end
assign step_o = step;
assign mem_addr_o = mem_addr;
// Controller State Machine
parameter INIT = 5'b00000;
parameter INPUT = 5'b00001;
parameter CALCSYND = 5'b00010;
parameter CALCDELTA1 = 5'b00011;
parameter CALCDELTA2 = 5'b00100;
parameter CALCBMSTEP1 = 5'b00101;
parameter CALCBMSTEP2 = 5'b00110;
parameter DONEBM = 5'b00111;
parameter CALCR0 = 5'b01000;
parameter PUTZEROIDFT = 5'b01001;
parameter MEMORY = 5'b01010;
parameter CALCRE = 5'b01011;
parameter LOADIDFT = 5'b01100;
parameter DATA0OUT = 5'b01101;
parameter CALCIDFT = 5'b01110;
parameter DONE = 5'b01111;
reg [4:0] cs,ns;
// STATE TRANSITION BODY
always @ (posedge clk_i) begin
if (rst_i) begin
cs <= INIT;
end
else begin
cs <= ns;
end
end
 
// Combination Body
always @(*) begin
case (cs)
INIT: begin
ns = INPUT;
 
// output
calc_S_0_o = 0;
dft_sel_o = 2'b00;
dft_calc_o = 0;
inc_mem_addr = 0;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
done_dec_o = 0;
valid_o_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
clr_input_cntr = 1;
clr_mem_addr = 0;
push_o = 0;
wren_o = 0;
mem_in_o = 0;
r_calc_sel_o = 0;
r_calc_o = 0;
busy_o = 0;
load_last_o = 0;
last_in_sel_o = 0;
end
INPUT: begin
// At this state All the data is inputed
if(input_cntr < 255) begin
ns = INPUT;
end
else begin
ns = CALCDELTA1;
end
// output
if (valid_i) begin
dft_calc_o = 1;
calc_S_0_o = 1;
dft_sel_o = 2'b01;
end
else begin
dft_calc_o = 0;
calc_S_0_o = 0;
dft_sel_o = 2'b00;
end
inc_mem_addr = 0;
//used Not used
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
done_dec_o = 0;
clr_input_cntr = 0;
clr_mem_addr = 1;
push_o = 0;
wren_o = 0;
mem_in_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
busy_o = 0;
load_last_o = 0;
//un used
valid_o_o = 0;
last_in_sel_o = 0;
 
end
CALCSYND: begin
ns = CALCDELTA1;
// output
dft_sel_o = 2'b00;
dft_calc_o = 1;
inc_mem_addr = 1;
wren_o = 0;
mem_in_o = 1;
 
// need to be trimmed
push_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
done_dec_o = 0;
calc_S_0_o = 0;
valid_o_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
clr_mem_addr = 0;
load_last_o = 0;
last_in_sel_o = 0;
 
clr_input_cntr = 1;
// important signal
busy_o = 1;
 
end
CALCDELTA1: begin
ns = CALCDELTA2;
// output
dft_sel_o = 2'b00;
dft_calc_o = 0;
inc_mem_addr = 0;
en_fir_o = 1;
// The memory is written with first 16 syndroms
wren_o = 1;
mem_in_o = 1;
push_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
calc_S_0_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
done_dec_o = 0;
valid_o_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
clr_mem_addr = 0;
load_last_o = 0;
last_in_sel_o = 0;
clr_input_cntr = 0;
busy_o = 1;
end
CALCDELTA2: begin
ns = CALCBMSTEP1;
// output
dft_sel_o = 2'b00;
dft_calc_o = 0;
inc_mem_addr = 0;
en_fir_o = 0;
// why memmory is being written here
wren_o = 0;
mem_in_o = 0;
push_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
calc_S_0_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
done_dec_o = 0;
valid_o_o = 0;
clr_mem_addr = 0;
load_last_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
last_in_sel_o = 0;
clr_input_cntr = 0;
busy_o = 1;
end
 
CALCBMSTEP1: begin
ns = CALCBMSTEP2;
// output
calc_bm_step_o = 1;
 
dft_sel_o = 2'b00;
dft_calc_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
en_fir_o = 0;
inc_mem_addr = 0;
fir_sel_o = 0;
calc_S_0_o = 0;
done_dec_o = 0;
valid_o_o = 0;
clr_mem_addr = 0;
push_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
mem_in_o = 0;
wren_o = 0;
load_last_o = 0;
last_in_sel_o = 0;
clr_input_cntr = 0;
busy_o = 1;
 
end
CALCBMSTEP2: begin
if (done_bm_step_i) begin
if(step_o < 15) // 2*t-1
ns = CALCSYND;
else
ns = DONEBM;
end
else begin
ns = CALCBMSTEP2;
end
// output
dft_sel_o = 2'b00;
dft_calc_o = 0;
inc_mem_addr = 0;
calc_S_0_o = 0;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
done_dec_o = 0;
valid_o_o = 0;
clr_mem_addr = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
push_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
mem_in_o = 0;
wren_o = 0;
load_last_o = 0;
last_in_sel_o = 0;
 
clr_input_cntr = 1;
busy_o = 1;
end
DONEBM: begin
// important wait for the elp to complete inversion aswell
if(elp_busy_i) begin
ns = DONEBM;
r_calc_o = 0;
r_calc_sel_o= 0;
end
else begin
ns = CALCR0;
r_calc_o = 1;
r_calc_sel_o= 1;
end
 
// output
clr_mem_addr = 0;
dft_sel_o = 2'b00;
dft_calc_o = 0;
en_fir_o = 0;
calc_S_0_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
done_dec_o = 0;
valid_o_o = 0;
push_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
inc_mem_addr = 0;
mem_in_o = 0;
wren_o = 0;
load_last_o = 0;
last_in_sel_o = 0;
 
clr_input_cntr = 1;
busy_o = 1;
end
CALCR0: begin
if(r_calc_done_i) begin
ns = MEMORY;
end
else begin
ns = CALCR0;
end
// output
r_calc_sel_o = 1;
r_calc_o = 0;
 
dft_sel_o = 2'b00;
dft_calc_o = 0;
en_fir_o = 0;
calc_S_0_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
done_dec_o = 0;
valid_o_o = 0;
push_o = 0;
inc_idft_cntr = 0;
clr_mem_addr = 0;
clr_idft_cntr = 0;
inc_mem_addr = 0;
mem_in_o = 0;
wren_o = 0;
load_last_o = 0;
last_in_sel_o = 0;
 
clr_input_cntr = 1;
busy_o = 1;
end
MEMORY: begin
ns = CALCRE;
// output
dft_sel_o = 2'b00;
dft_calc_o = 1; // calc_first DFT0
fir_sel_o = 1; // calc_first RE
en_fir_o = 1; // dont calc first RE
inc_idft_cntr = 0;
clr_idft_cntr = 0;
calc_bm_step_o = 0;
// Put data in Memmory
clr_mem_addr = 0;
inc_mem_addr = 0;
wren_o = 0;
mem_in_o = 0;
done_dec_o = 0;
valid_o_o = 0;
push_o = 0;
load_last_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
calc_S_0_o = 0;
last_in_sel_o = 0;
 
busy_o = 1;
clr_input_cntr = 1;
 
end
CALCRE: begin
if(mem_addr<255) begin
ns = CALCRE;
clr_mem_addr = 0;
end
else begin
ns = PUTZEROIDFT;
clr_mem_addr = 1;
end
// output
// calculate remaining syndrome
dft_sel_o = 2'b00;
dft_calc_o = 1;
// calculate r0
en_fir_o = 1;
fir_sel_o = 1;
inc_mem_addr = 1;
calc_S_0_o = 0;
load_last_o = 1;
wren_o = 1;
r_calc_o = 0;
r_calc_sel_o = 0;
mem_in_o = 0;
// add syndrome and ro and put it in memmory
//////////////////////
inc_idft_cntr = 0;
push_o = 0;
clr_idft_cntr = 0;
calc_bm_step_o = 0;
done_dec_o = 0;
valid_o_o = 0;
clr_input_cntr = 0;
last_in_sel_o = 0;
busy_o = 1;
end
PUTZEROIDFT:begin
if(mem_addr<15) begin
ns = PUTZEROIDFT;
end
else begin
ns = LOADIDFT;
end
// output
dft_sel_o = 2'b11;
dft_calc_o = 1;
inc_mem_addr = 1;
// This signal is used to push zero in IDFT
push_o = 1;
en_fir_o = 0;
inc_idft_cntr = 0;
clr_idft_cntr = 0;
calc_bm_step_o = 0;
wren_o = 0;
mem_in_o = 0;
clr_mem_addr = 0;
fir_sel_o = 0;
done_dec_o = 0;
valid_o_o = 0;
load_last_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
calc_S_0_o = 0;
last_in_sel_o = 0;
 
busy_o = 1;
clr_input_cntr = 1;
end
LOADIDFT: begin
if(mem_addr<254) begin
ns = LOADIDFT;
end
else begin
ns = DATA0OUT;
end
// output
dft_sel_o = 2'b11;
dft_calc_o = 1;
inc_mem_addr = 1;
clr_mem_addr = 0;
load_last_o = 0;
clr_idft_cntr = 1;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
inc_idft_cntr = 0;
done_dec_o = 0;
valid_o_o = 0;
clr_input_cntr = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
push_o = 0;
wren_o = 0;
mem_in_o = 0;
calc_S_0_o = 0;
last_in_sel_o = 0;
 
busy_o = 1;
end
DATA0OUT: begin
ns = CALCIDFT;
// output
dft_sel_o = 2'b00;
dft_calc_o = 0;
inc_mem_addr = 0;
clr_mem_addr = 0;
load_last_o = 0;
clr_idft_cntr = 1;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
inc_idft_cntr = 0;
done_dec_o = 0;
valid_o_o = 1;
clr_input_cntr = 0;
push_o = 0;
wren_o = 0;
mem_in_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
calc_S_0_o = 0;
last_in_sel_o = 1;
 
busy_o = 1;
end
CALCIDFT: begin
if(idft_cntr<253) begin
ns = CALCIDFT;
end
else begin
ns = DONE;
end
// output
dft_sel_o = 2'b00;
dft_calc_o = 1;
inc_mem_addr = 0;
clr_mem_addr = 1;
inc_idft_cntr = 1;
clr_idft_cntr = 0;
valid_o_o = 1;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
done_dec_o = 0;
clr_input_cntr = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
push_o = 0;
wren_o = 0;
mem_in_o = 0;
load_last_o = 0;
calc_S_0_o = 0;
last_in_sel_o = 0;
 
busy_o = 1;
end
DONE: begin
ns = INIT;
// output
done_dec_o = 1;
clr_input_cntr = 1;
clr_mem_addr = 1;
clr_idft_cntr = 1;
busy_o = 1;
 
dft_sel_o = 2'b00;
dft_calc_o = 0;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
inc_idft_cntr = 0;
valid_o_o = 0;
mem_in_o = 0;
r_calc_o = 0;
r_calc_sel_o = 0;
push_o = 0;
wren_o = 0;
inc_mem_addr = 0;
load_last_o = 0;
calc_S_0_o = 0;
last_in_sel_o = 0;
end
default: begin
ns = INIT;
// output
dft_sel_o = 2'b00;
dft_calc_o = 0;
en_fir_o = 0;
fir_sel_o = 0;
calc_bm_step_o = 0;
inc_idft_cntr = 0;
done_dec_o = 0;
valid_o_o = 0;
clr_input_cntr = 1;
clr_mem_addr = 1;
clr_idft_cntr = 1;
r_calc_o = 0;
r_calc_sel_o = 0;
mem_in_o = 0;
push_o = 0;
wren_o = 0;
inc_mem_addr = 0;
load_last_o = 0;
last_in_sel_o = 0;
calc_S_0_o = 0;
busy_o = 1;
 
end
endcase
end
endmodule
/rs_encoder_decoder/rtl/GF8SigmaAdder8t.v
0,0 → 1,21
// This is a verilog File Generated
// By The C++ program That Generates
// ARG1 and ARG2 Adder
// And uses GF Adder and Multiplier
 
module GF8SigmaAdder8t(
arg_i1,
arg_i2,
NewSigma
);
// Declaration of the inputs
input [71:0] arg_i1;
input [71:0] arg_i2;
output wire [71:0] NewSigma;
// Declaration of registers and Wire is Here
 
assign NewSigma = arg_i1^arg_i2;
 
endmodule
 
/rs_encoder_decoder/rtl/GF8Reg.v
0,0 → 1,24
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Register
 
module GF8Reg(clk_i, rst_i,
en_i, // Enable Signal
reg_i, // Gallios Field Register input 1
reg_o // Gallios Field Register output
);
// Inputs are declared here
input clk_i,rst_i,en_i; // Clock and Reset Declaration
input [7:0] reg_i;
output reg [7:0] reg_o;
 
// Declaration of Wires And Register are here
// Sequential Body
always @(posedge clk_i or posedge rst_i) begin
if (rst_i)
reg_o = 0;
else if(en_i)
reg_o = reg_i;
end
endmodule
/rs_encoder_decoder/rtl/GF8Fir_testbench.v
0,0 → 1,67
`timescale 1ns / 10 ps
 
module GF8Fir8t_testbench;
reg clk_i,rst_i;
reg en_i;
reg [7:0] fir_i;
reg sel_i;
wire [7:0] fir_o;
reg [71:0] coeff_i,shift_reg_i;
reg [126*7:0] path,input_file,output_file;
integer fd_in, fd_out;
GF8Fir8t DUT(
.clk_i(clk_i),.rst_i(rst_i),
.en_i(en_i), // Gallios Field FIR Filter enable 1
.fir_i(fir_i), // Gallios Field FIR Filter input 1
.sel_i(sel_i), // Gallios Field FIR Filter input 1
.shift_reg_i(shift_reg_i), // Gallios Field FIR Coefficient input 1
.coeff_i(coeff_i), // Gallios Field FIR Coefficient input 1
.fir_o(fir_o) // Gallios Field FIR out
);
always
#5 clk_i = !clk_i;
initial begin
path = "./";
input_file = "input_file_GF8Fir.dat";
output_file = "output_file_GF8Fir.dat";
fd_in = $fopen(input_file,"r");
fd_out = $fopen(output_file,"w");
coeff_i[7:0] = 8'h0;
shift_reg_i[7:0] = 8'h8;
coeff_i[15:8] = 8'h1;
shift_reg_i[15:8] = 8'h7;
coeff_i[23:16] = 8'h2;
shift_reg_i[23:16] = 8'h6;
coeff_i[31:24] = 8'h3;
shift_reg_i[31:24] = 8'h5;
coeff_i[39:32] = 8'h4;
shift_reg_i[39:32] = 8'h4;
coeff_i[47:40] = 8'h5;
shift_reg_i[47:40] = 8'h3;
coeff_i[55:48] = 8'h6;
shift_reg_i[55:48] = 8'h2;
coeff_i[63:56] = 8'h7;
shift_reg_i[63:56] = 8'h1;
coeff_i[71:64] = 8'h8;
shift_reg_i[71:64] = 8'h0;
 
clk_i = 0;
rst_i = 1;
en_i = 0;
sel_i = 0;
#10 rst_i = 0;
 
while(!$feof(fd_in))
begin
@(negedge clk_i);
$fscanf(fd_in,"%d\n",fir_i);
$fwrite(fd_out,"%d\n",fir_o);
en_i = 1;
end
end // initial begin
 
endmodule
/rs_encoder_decoder/rtl/GF8Mult_testbench.v
0,0 → 1,36
`timescale 1ns / 10 ps
 
module GF8Mult5_testbench;
reg clk_i,rst_i;
wire [7:0] mult_o;
reg [7:0] mult_i;
reg [126*7:0] path,input_file,output_file;
integer fd_in,fd_out;
GF8Mult5 DUT(.clk_i(clk_i),.rst_i(rst_i),
.mult_i(mult_i),
.mult_o(mult_o));
always
#5 clk_i = !clk_i;
initial begin
path = "./";
input_file = "input_file_GF8Mult.dat";
output_file = "output_file_GF8Mult.dat";
fd_in = $fopen(input_file,"r");
fd_out = $fopen(output_file,"w");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
 
while(!$feof(fd_in))
begin
@(negedge clk_i);
$fscanf(fd_in,"%d\n",mult_i);
$fwrite(fd_out,"%d\n",mult_o);
end
end // initial begin
 
endmodule
/rs_encoder_decoder/rtl/Memmory.v
0,0 → 1,34
module Memmory
(
input [7:0] data,
input [7:0] addr,
input we, clk,
output reg [7:0] q
);
 
// Declare the RAM variable
parameter WIDTH = 256;
reg [7:0] ram[WIDTH-1:0];
//if remove clear function, the dpram can be synthesized to ram block
//always @(posedge clk ) begin:clear
// if (clear_i) begin
// for(i=0; i<WIDTH; i = i+1)
// ram[i] <= 0;
// end
//end
 
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] = data;
 
// Read (if read_addr == write_addr, return OLD data). To return
// NEW data, use = (blocking write) rather than <= (non-blocking write)
// in the write assignment. NOTE: NEW data may require extra bypass
// logic around the RAM.
q = ram[addr];
end
 
endmodule
/rs_encoder_decoder/rtl/Mux8to1.v
0,0 → 1,18
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Mux
 
module Mux8To1(sel_i, // Select Line
mux_i0, //Input 0
mux_i1, //Input 1
mux_o //Output from the MUX
);
// Inputs are declared here
// Ports are declared here
input sel_i;
input [7:0] mux_i0, mux_i1;
output wire [7:0] mux_o;
assign mux_o = sel_i?mux_i1:mux_i0;
 
endmodule
/rs_encoder_decoder/rtl/GF8Mult.v
0,0 → 1,6120
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult0(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[0];
assign mult_o[1] = mult_i[1];
assign mult_o[2] = mult_i[2];
assign mult_o[3] = mult_i[3];
assign mult_o[4] = mult_i[4];
assign mult_o[5] = mult_i[5];
assign mult_o[6] = mult_i[6];
assign mult_o[7] = mult_i[7];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult1(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7];
assign mult_o[1] = mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[3];
assign mult_o[5] = mult_i[4];
assign mult_o[6] = mult_i[5];
assign mult_o[7] = mult_i[6];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult2(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6];
assign mult_o[1] = mult_i[7];
assign mult_o[2] = mult_i[6]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[3];
assign mult_o[6] = mult_i[4];
assign mult_o[7] = mult_i[5];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult3(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5];
assign mult_o[1] = mult_i[6];
assign mult_o[2] = mult_i[7]^mult_i[5];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[3];
assign mult_o[7] = mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult4(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4];
assign mult_o[1] = mult_i[5];
assign mult_o[2] = mult_i[6]^mult_i[4];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult5(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3];
assign mult_o[1] = mult_i[4];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult6(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult7(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult8(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult9(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult10(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult11(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult12(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult13(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult14(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult15(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult16(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[3];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult17(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult18(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult19(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult20(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult21(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[0];
assign mult_o[5] = mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult22(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6];
assign mult_o[5] = mult_i[7]^mult_i[0];
assign mult_o[6] = mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult23(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5];
assign mult_o[5] = mult_i[7]^mult_i[6];
assign mult_o[6] = mult_i[7]^mult_i[0];
assign mult_o[7] = mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult24(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4];
assign mult_o[5] = mult_i[6]^mult_i[5];
assign mult_o[6] = mult_i[7]^mult_i[6];
assign mult_o[7] = mult_i[7]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult25(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[0];
assign mult_o[1] = mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[5]^mult_i[4];
assign mult_o[6] = mult_i[6]^mult_i[5];
assign mult_o[7] = mult_i[7]^mult_i[6];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult26(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6];
assign mult_o[1] = mult_i[7]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[5]^mult_i[4];
assign mult_o[7] = mult_i[6]^mult_i[5];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult27(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5];
assign mult_o[1] = mult_i[7]^mult_i[6];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[5]^mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult28(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4];
assign mult_o[1] = mult_i[6]^mult_i[5];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult29(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[5]^mult_i[4];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult30(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[5]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult31(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult32(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult33(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult34(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult35(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult36(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult37(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult38(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[2];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult39(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult40(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult41(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3];
assign mult_o[4] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult42(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult43(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult44(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[2];
assign mult_o[5] = mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult45(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[1];
assign mult_o[5] = mult_i[2];
assign mult_o[6] = mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult46(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[1];
assign mult_o[6] = mult_i[2];
assign mult_o[7] = mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult47(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[5];
assign mult_o[5] = mult_i[6]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[1];
assign mult_o[7] = mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult48(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[2];
assign mult_o[1] = mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[4];
assign mult_o[5] = mult_i[7]^mult_i[5];
assign mult_o[6] = mult_i[6]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult49(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[1];
assign mult_o[1] = mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3];
assign mult_o[5] = mult_i[6]^mult_i[4];
assign mult_o[6] = mult_i[7]^mult_i[5];
assign mult_o[7] = mult_i[6]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult50(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3];
assign mult_o[6] = mult_i[6]^mult_i[4];
assign mult_o[7] = mult_i[7]^mult_i[5];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult51(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5];
assign mult_o[1] = mult_i[6]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3];
assign mult_o[7] = mult_i[6]^mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult52(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4];
assign mult_o[1] = mult_i[7]^mult_i[5];
assign mult_o[2] = mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult53(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3];
assign mult_o[1] = mult_i[6]^mult_i[4];
assign mult_o[2] = mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult54(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult55(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult56(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult57(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult58(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult59(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult60(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult61(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult62(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult63(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult64(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult65(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult66(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult67(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult68(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult69(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult70(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult71(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult72(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult73(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult74(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult75(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult76(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult77(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult78(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult79(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult80(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult81(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult82(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult83(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult84(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult85(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult86(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult87(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult88(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult89(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult90(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult91(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult92(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult93(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult94(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[5]^mult_i[3];
assign mult_o[3] = mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult95(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult96(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult97(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[0];
assign mult_o[4] = mult_i[3];
assign mult_o[5] = mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult98(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5];
assign mult_o[4] = mult_i[7]^mult_i[2];
assign mult_o[5] = mult_i[3];
assign mult_o[6] = mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult99(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[2];
assign mult_o[6] = mult_i[3];
assign mult_o[7] = mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult100(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[2];
assign mult_o[7] = mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult101(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3];
assign mult_o[1] = mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult102(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[2];
assign mult_o[1] = mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult103(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult104(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult105(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult106(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult107(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult108(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult109(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult110(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult111(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult112(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult113(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult114(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult115(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult116(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult117(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult118(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult119(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult120(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult121(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[1];
assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult122(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult123(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4];
assign mult_o[4] = mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult124(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult125(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult126(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult127(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult128(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult129(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult130(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult131(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult132(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult133(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult134(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult135(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult136(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult137(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult138(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4];
assign mult_o[4] = mult_i[5]^mult_i[3];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult139(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[5]^mult_i[3];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult140(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[2];
assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[5]^mult_i[3];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult141(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[1];
assign mult_o[2] = mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[5]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult142(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult143(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[5]^mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult144(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult145(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult146(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult147(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult148(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult149(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult150(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult151(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5];
assign mult_o[3] = mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult152(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[3] = mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult153(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult154(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult155(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult156(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult157(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult158(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult159(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult160(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult161(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult162(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult163(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult164(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult165(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult166(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult167(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult168(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult169(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult170(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult171(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult172(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult173(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult174(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult175(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult176(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4];
assign mult_o[3] = mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult177(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3];
assign mult_o[3] = mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult178(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[3] = mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult179(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult180(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult181(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult182(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult183(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult184(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult185(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult186(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult187(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult188(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult189(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult190(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult191(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[4] = mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult192(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[4] = mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult193(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult194(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult195(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult196(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult197(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult198(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult199(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult200(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult201(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[2] = mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult202(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult203(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult204(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult205(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult206(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult207(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult208(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult209(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult210(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[5];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult211(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[4];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult212(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[3];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult213(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult214(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult215(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult216(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult217(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult218(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult219(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult220(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[4];
assign mult_o[5] = mult_i[5]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult221(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[4];
assign mult_o[6] = mult_i[5]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult222(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[4];
assign mult_o[7] = mult_i[5]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult223(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[2];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult224(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[4];
assign mult_o[1] = mult_i[5]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult225(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[4];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult226(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[3];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[3] = mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult227(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult228(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[2] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult229(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[2] = mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult230(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4];
assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult231(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3];
assign mult_o[4] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult232(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2];
assign mult_o[4] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult233(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult234(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult235(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[4];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult236(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[4];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult237(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[4];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult238(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[4];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult239(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[4];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult240(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[4];
assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult241(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3];
assign mult_o[2] = mult_i[5]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult242(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult243(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult244(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[5] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult245(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[5] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[6] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult246(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[3]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[4]^mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[5] = mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[6] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[7] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult247(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[7]^mult_i[6]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[7]^mult_i[6]^mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[3] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1];
assign mult_o[4] = mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[5] = mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[6] = mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[7] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult248(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[1] = mult_i[6]^mult_i[5]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[6]^mult_i[5]^mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[6]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[5] = mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[6] = mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[7] = mult_i[6]^mult_i[4]^mult_i[3];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult249(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[1] = mult_i[7]^mult_i[5]^mult_i[4]^mult_i[0];
assign mult_o[2] = mult_i[5]^mult_i[4]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[4] = mult_i[2]^mult_i[0];
assign mult_o[5] = mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[6] = mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[7] = mult_i[5]^mult_i[3]^mult_i[2];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult250(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[1] = mult_i[6]^mult_i[4]^mult_i[3];
assign mult_o[2] = mult_i[7]^mult_i[4]^mult_i[3]^mult_i[2]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[1];
assign mult_o[5] = mult_i[2]^mult_i[0];
assign mult_o[6] = mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[7] = mult_i[4]^mult_i[2]^mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult251(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[1] = mult_i[5]^mult_i[3]^mult_i[2];
assign mult_o[2] = mult_i[6]^mult_i[3]^mult_i[2]^mult_i[1];
assign mult_o[3] = mult_i[7]^mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[4] = mult_i[0];
assign mult_o[5] = mult_i[1];
assign mult_o[6] = mult_i[2]^mult_i[0];
assign mult_o[7] = mult_i[3]^mult_i[1]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult252(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[1] = mult_i[4]^mult_i[2]^mult_i[1];
assign mult_o[2] = mult_i[5]^mult_i[2]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[6]^mult_i[2]^mult_i[0];
assign mult_o[4] = mult_i[7];
assign mult_o[5] = mult_i[0];
assign mult_o[6] = mult_i[1];
assign mult_o[7] = mult_i[2]^mult_i[0];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult253(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[2]^mult_i[0];
assign mult_o[1] = mult_i[3]^mult_i[1]^mult_i[0];
assign mult_o[2] = mult_i[4]^mult_i[1]^mult_i[0];
assign mult_o[3] = mult_i[5]^mult_i[1];
assign mult_o[4] = mult_i[6];
assign mult_o[5] = mult_i[7];
assign mult_o[6] = mult_i[0];
assign mult_o[7] = mult_i[1];
endmodule
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Multiplier
 
module GF8Mult254(mult_i, mult_o);
// Inputs are declared here
input [7:0] mult_i;
output [7:0] mult_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign mult_o[0] = mult_i[1];
assign mult_o[1] = mult_i[2]^mult_i[0];
assign mult_o[2] = mult_i[3]^mult_i[0];
assign mult_o[3] = mult_i[4]^mult_i[0];
assign mult_o[4] = mult_i[5];
assign mult_o[5] = mult_i[6];
assign mult_o[6] = mult_i[7];
assign mult_o[7] = mult_i[0];
endmodule
/rs_encoder_decoder/rtl/RS8CalcErrLocPoly8t.v
0,0 → 1,321
// This is a verilog File Generated
// By The C++ program That Generates
// Gallios Field Error Loc Poly finder using
// Barlekamp Messay Algorithm only contins
// This Contains Only the Circuit
 
module RS8ErrLocPoly8t(clk_i,rst_i,
valid_i, // input 1
delta_i, // input 1
step_i, // input 1
done_dec_i, // input 1
valid_o, // output
sigma_0_o, // output
sigma_last_o, // output
sigma_o, // output
busy_o
);
// Declaration of the inputs
input clk_i,rst_i;
input valid_i;
input done_dec_i;
input [7:0] delta_i;
input [7:0] step_i;
output reg valid_o;
output reg busy_o;
output wire [71:0] sigma_0_o, sigma_o, sigma_last_o;
// Declaration of Wires are here
wire [71:0] arg1;
wire [71:0] arg2;
wire [71:0] newSigma;
wire [7:0] sigma_0_inv;
wire [7:0] sigma_last_inv;
wire signed [7:0] inL;
wire signed [7:0] add_res;
wire inv_done1, inv_done2;
// Declaration of Register are here
reg [71:0] prevSigma, sigma_2L, sigma;
reg [7:0] prevDelta;
reg [7:0] L;
reg [3:0] state;
reg inv_en;
 
assign sigma_o = sigma;
assign sigma_0_o = sigma_2L;
assign sigma_last_o = prevSigma;
GF8Inverse INVERS1(.clk_i(clk_i),.rst_i(rst_i),
.valid_i(inv_en), //
.inv_i(sigma[7:0]), //
.valid_o(inv_done1), //
.inv_o(sigma_last_inv)); //
GF8Inverse INVERS2(.clk_i(clk_i),.rst_i(rst_i),
.valid_i(inv_en), //
.inv_i(sigma[71:64]), //
.valid_o(inv_done), //
.inv_o(sigma_0_inv)); //
parameter INIT = 4'b0000;
parameter WAIT = 4'b0001;
parameter CALCSIGMA1 = 4'b0010;
parameter CALCSIGMA2 = 4'b0011;
parameter SHIFT = 4'b0100;
parameter UPDATE = 4'b0101;
parameter DONESTEP = 4'b0110;
parameter INVERSE = 4'b0111;
parameter DONEBM = 4'b1000;
 
assign add_res = step_i - L;
assign inL = add_res +1;
 
// Barlekamp Messey Algorithm State Machine
always @(posedge clk_i) begin
if((rst_i)||(done_dec_i))begin
state <= INIT;
prevDelta <= 0;
prevSigma <= 0;
sigma_2L <= 0;
sigma <= 0;
L <= 0;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
else begin
case(state)
INIT: begin
//state transition
state <= WAIT;
prevSigma <= 72'b000000010000000000000000000000000000000000000000000000000000000000000000;
sigma <= 72'b000000010000000000000000000000000000000000000000000000000000000000000000;
prevDelta <= 8'b00000001;
sigma_2L <= 72'b000000010000000000000000000000000000000000000000000000000000000000000000;
L <= 0;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
WAIT: begin
//state transition
if((valid_i) && (|delta_i)) begin
state <= CALCSIGMA1;
end
else if((valid_i) && (~(|delta_i)))begin
state <= SHIFT;
end
else begin
state <= WAIT;
end
prevSigma <= prevSigma;
prevDelta <= prevDelta;
sigma_2L <= sigma_2L;
sigma <= sigma;
L <= L;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
CALCSIGMA1: begin
//state transition
state <= CALCSIGMA2;
//output transition
prevSigma <= sigma;
sigma <= sigma;
prevDelta <= prevDelta;
sigma_2L <= sigma_2L;
L <= L;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
CALCSIGMA2: begin
//state transition
if (step_i<(L<<1))
state <= SHIFT;
else
state <= UPDATE;
//output transition
prevSigma <= prevSigma;
sigma <= newSigma;
prevDelta <= prevDelta;
sigma_2L <= sigma_2L;
L <= L;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
SHIFT: begin
state <= DONESTEP;
//output transition
prevSigma <= prevSigma;
sigma <= sigma;
prevDelta <= prevDelta;
sigma_2L <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0, sigma_2L[71:8]};
L <= L;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
UPDATE: begin
state <= DONESTEP;
valid_o <= 0;
prevSigma <= prevSigma;
sigma <= sigma;
prevDelta <= delta_i;
sigma_2L <= {1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0, prevSigma[71:8]};
L <= inL;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
DONESTEP: begin
if (step_i < 15) begin
state <= WAIT;
inv_en <= 0;
end
else begin
state <= INVERSE;
inv_en <= 1;
end
prevSigma <= prevSigma;
prevDelta <= prevDelta;
sigma_2L <= sigma_2L;
sigma <= sigma;
L <= L;
valid_o <= 1;
busy_o <= 0;
end
INVERSE: begin
if (inv_done) begin
state <= DONEBM;
end
else begin
state <= INVERSE;
end
prevDelta <= prevDelta;
sigma <= sigma;
sigma_2L <= {sigma[63:0],sigma_0_inv};
prevSigma <={sigma[71:8],sigma_last_inv};
L <= L;
valid_o <= 0;
inv_en <= 0;
busy_o <= 1;
end
DONEBM: begin
if(done_dec_i)
state <= INIT;
else
state <= DONEBM;
prevSigma <= prevSigma;
prevDelta <= prevDelta;
sigma_2L <= sigma_2L;
sigma <= sigma;
L <= L;
valid_o <= 0;
inv_en <= 0;
busy_o <= 0;
end
default: begin
state <= INIT;
prevSigma <= prevSigma;
prevDelta <= prevDelta;
sigma_2L <= sigma_2L;
sigma <= sigma;
L <= 0;
inv_en <= 0;
busy_o <= 0;
valid_o <= 0;
end
endcase
end
end
////////// ARG1 Multiplication //////////
GF8GenMult ARG1MULT0(
.mult_i1(prevSigma[7:0]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[7:0])); // Generic Multiplier output
GF8GenMult ARG1MULT1(
.mult_i1(prevSigma[15:8]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[15:8])); // Generic Multiplier output
GF8GenMult ARG1MULT2(
.mult_i1(prevSigma[23:16]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[23:16])); // Generic Multiplier output
GF8GenMult ARG1MULT3(
.mult_i1(prevSigma[31:24]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[31:24])); // Generic Multiplier output
GF8GenMult ARG1MULT4(
.mult_i1(prevSigma[39:32]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[39:32])); // Generic Multiplier output
GF8GenMult ARG1MULT5(
.mult_i1(prevSigma[47:40]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[47:40])); // Generic Multiplier output
GF8GenMult ARG1MULT6(
.mult_i1(prevSigma[55:48]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[55:48])); // Generic Multiplier output
GF8GenMult ARG1MULT7(
.mult_i1(prevSigma[63:56]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[63:56])); // Generic Multiplier output
GF8GenMult ARG1MULT8(
.mult_i1(prevSigma[71:64]), // Generic Multiplier input 1
.mult_i2(prevDelta), // Generic Multiplier input 2
.mult_o(arg1[71:64])); // Generic Multiplier output
////////// ARG2 Multiplication //////////
GF8GenMult ARG2MULT0(
.mult_i1(sigma_2L[7:0]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[7:0])); // Generic Multiplier output
GF8GenMult ARG2MULT1(
.mult_i1(sigma_2L[15:8]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[15:8])); // Generic Multiplier output
GF8GenMult ARG2MULT2(
.mult_i1(sigma_2L[23:16]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[23:16])); // Generic Multiplier output
GF8GenMult ARG2MULT3(
.mult_i1(sigma_2L[31:24]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[31:24])); // Generic Multiplier output
GF8GenMult ARG2MULT4(
.mult_i1(sigma_2L[39:32]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[39:32])); // Generic Multiplier output
GF8GenMult ARG2MULT5(
.mult_i1(sigma_2L[47:40]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[47:40])); // Generic Multiplier output
GF8GenMult ARG2MULT6(
.mult_i1(sigma_2L[55:48]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[55:48])); // Generic Multiplier output
GF8GenMult ARG2MULT7(
.mult_i1(sigma_2L[63:56]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[63:56])); // Generic Multiplier output
GF8GenMult ARG2MULT8(
.mult_i1(sigma_2L[71:64]), // Generic Multiplier input 1
.mult_i2(delta_i), // Generic Multiplier input 2
.mult_o(arg2[71:64])); // Generic Multiplier output
////////// SIGMA ADDER//////////
GF8SigmaAdder8t ARG1CT(
.arg_i1(arg1),
.arg_i2(arg2),
.NewSigma(newSigma)
);
endmodule
/rs_encoder_decoder/rtl/GF8tmmult.v
0,0 → 1,29
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Generic
// Bit Serial Hardware Multiplier
 
module GF8tmmult(clk_i, rst_i,
en_i, // Valid Input Set it to High When giving the input
tmmult_i, // Gallios Field Generic Bit Serial Multiplier output
tmmult_o // Gallios Field Generic Bit Serial Multiplier output
);
// Inputs are declared here
input clk_i,rst_i; // Clock and Reset Declaration
input en_i;
input [7:0] tmmult_i;
output wire [7:0] tmmult_o;
// Declaration of Wires
wire [7:0] lfsr;
GF8lfsr LFSR(.clk_i(clk_i), .rst_i(rst_i),
.en_i(en_i), // Valid Input Set it to High When giving the input
.lfsr_o(lfsr) // Gallios Field Generic Bit Serial Multiplier output
);
GF8GenMult MULT(
.mult_i1(lfsr),
.mult_i2(tmmult_reg),
.mult_o(tmmult_o));
endmodule
/rs_encoder_decoder/rtl/GF8GenMultBitSer_testbench.v
0,0 → 1,59
`timescale 1ns / 10 ps
 
module GF8GenMultBitSer_testbench;
reg clk_i,rst_i;
wire [7:0] mult_o;
wire valid_o;
reg [7:0] mult_i1,mult_i2;
reg valid_i;
reg [126*7:0] path,input_file,output_file;
reg [4:0] cntr;
integer fd_in,fd_out;
GF8GenMultBitSer DUT(.clk_i(clk_i),.rst_i(rst_i),
.valid_i(valid_i),
.mult_i1(mult_i1),
.mult_i2(mult_i2),
.valid_o(valid_o),
.mult_o(mult_o));
always @(posedge clk_i) begin
if (rst_i) begin
cntr <= 0;
end else if (valid_o) begin
cntr <= 0;
end else begin
cntr <= cntr+1;
end
end
always
#5 clk_i = !clk_i;
initial begin
path = "./";
input_file = "input_file_GF8Mult.dat";
output_file = "output_file_GF8Mult.dat";
fd_in = $fopen(input_file,"r");
fd_out = $fopen(output_file,"w");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
 
while(!$feof(fd_in))
begin
@(negedge clk_i);
if(cntr == 1) begin
valid_i = 1;
end else begin
valid_i = 0;
end
if(valid_i) begin
$fscanf(fd_in,"%d %d\n",mult_i1,mult_i2);
$fwrite(fd_out,"%d\n",mult_o);
end
end
end // initial begin
 
endmodule
/rs_encoder_decoder/rtl/GF8Dft_Idft.v
0,0 → 1,332
module GF8Dft_Idft(clk_i, rst_i,
dft_sel_i, // Control Signal calculates dft if dft_idft = 0 else idft if dft_idft = 1
en_i, // Control Signal
dft_i, // Gallios Field Register input 1
dft_o // Gallios Field Register output
);
// Inputs are declared here
input clk_i,rst_i,en_i; // Clock and Reset Declaration
input dft_sel_i; // Controll Signal That does All the Required Operations
input [7:0] dft_i;
output wire [7:0] dft_o;
 
// Declaration of Wires And Register are here
wire [7:0] reg_o [0:254];
wire [7:0] mult_o[0:254];
wire [7:0] mux_o [0:254];
wire [7:0] add_o [0:253];
assign dft_o = add_o[253];
 
///////////////// Structural Model ////////////////
GF8Mult0 MULT_0(.mult_i(reg_o[0]), .mult_o(mult_o[0]) );
GF8Mult1 MULT_1(.mult_i(reg_o[1]), .mult_o(mult_o[1]) );
GF8Mult2 MULT_2(.mult_i(reg_o[2]), .mult_o(mult_o[2]) );
GF8Mult3 MULT_3(.mult_i(reg_o[3]), .mult_o(mult_o[3]) );
GF8Mult4 MULT_4(.mult_i(reg_o[4]), .mult_o(mult_o[4]) );
GF8Mult5 MULT_5(.mult_i(reg_o[5]), .mult_o(mult_o[5]) );
GF8Mult6 MULT_6(.mult_i(reg_o[6]), .mult_o(mult_o[6]) );
GF8Mult7 MULT_7(.mult_i(reg_o[7]), .mult_o(mult_o[7]) );
GF8Mult8 MULT_8(.mult_i(reg_o[8]), .mult_o(mult_o[8]) );
GF8Mult9 MULT_9(.mult_i(reg_o[9]), .mult_o(mult_o[9]) );
GF8Mult10 MULT_10(.mult_i(reg_o[10]), .mult_o(mult_o[10]) );
GF8Mult11 MULT_11(.mult_i(reg_o[11]), .mult_o(mult_o[11]) );
GF8Mult12 MULT_12(.mult_i(reg_o[12]), .mult_o(mult_o[12]) );
GF8Mult13 MULT_13(.mult_i(reg_o[13]), .mult_o(mult_o[13]) );
GF8Mult14 MULT_14(.mult_i(reg_o[14]), .mult_o(mult_o[14]) );
GF8Mult15 MULT_15(.mult_i(reg_o[15]), .mult_o(mult_o[15]) );
GF8Mult16 MULT_16(.mult_i(reg_o[16]), .mult_o(mult_o[16]) );
GF8Mult17 MULT_17(.mult_i(reg_o[17]), .mult_o(mult_o[17]) );
GF8Mult18 MULT_18(.mult_i(reg_o[18]), .mult_o(mult_o[18]) );
GF8Mult19 MULT_19(.mult_i(reg_o[19]), .mult_o(mult_o[19]) );
GF8Mult20 MULT_20(.mult_i(reg_o[20]), .mult_o(mult_o[20]) );
GF8Mult21 MULT_21(.mult_i(reg_o[21]), .mult_o(mult_o[21]) );
GF8Mult22 MULT_22(.mult_i(reg_o[22]), .mult_o(mult_o[22]) );
GF8Mult23 MULT_23(.mult_i(reg_o[23]), .mult_o(mult_o[23]) );
GF8Mult24 MULT_24(.mult_i(reg_o[24]), .mult_o(mult_o[24]) );
GF8Mult25 MULT_25(.mult_i(reg_o[25]), .mult_o(mult_o[25]) );
GF8Mult26 MULT_26(.mult_i(reg_o[26]), .mult_o(mult_o[26]) );
GF8Mult27 MULT_27(.mult_i(reg_o[27]), .mult_o(mult_o[27]) );
GF8Mult28 MULT_28(.mult_i(reg_o[28]), .mult_o(mult_o[28]) );
GF8Mult29 MULT_29(.mult_i(reg_o[29]), .mult_o(mult_o[29]) );
GF8Mult30 MULT_30(.mult_i(reg_o[30]), .mult_o(mult_o[30]) );
GF8Mult31 MULT_31(.mult_i(reg_o[31]), .mult_o(mult_o[31]) );
GF8Mult32 MULT_32(.mult_i(reg_o[32]), .mult_o(mult_o[32]) );
GF8Mult33 MULT_33(.mult_i(reg_o[33]), .mult_o(mult_o[33]) );
GF8Mult34 MULT_34(.mult_i(reg_o[34]), .mult_o(mult_o[34]) );
GF8Mult35 MULT_35(.mult_i(reg_o[35]), .mult_o(mult_o[35]) );
GF8Mult36 MULT_36(.mult_i(reg_o[36]), .mult_o(mult_o[36]) );
GF8Mult37 MULT_37(.mult_i(reg_o[37]), .mult_o(mult_o[37]) );
GF8Mult38 MULT_38(.mult_i(reg_o[38]), .mult_o(mult_o[38]) );
GF8Mult39 MULT_39(.mult_i(reg_o[39]), .mult_o(mult_o[39]) );
GF8Mult40 MULT_40(.mult_i(reg_o[40]), .mult_o(mult_o[40]) );
GF8Mult41 MULT_41(.mult_i(reg_o[41]), .mult_o(mult_o[41]) );
GF8Mult42 MULT_42(.mult_i(reg_o[42]), .mult_o(mult_o[42]) );
GF8Mult43 MULT_43(.mult_i(reg_o[43]), .mult_o(mult_o[43]) );
GF8Mult44 MULT_44(.mult_i(reg_o[44]), .mult_o(mult_o[44]) );
GF8Mult45 MULT_45(.mult_i(reg_o[45]), .mult_o(mult_o[45]) );
GF8Mult46 MULT_46(.mult_i(reg_o[46]), .mult_o(mult_o[46]) );
GF8Mult47 MULT_47(.mult_i(reg_o[47]), .mult_o(mult_o[47]) );
GF8Mult48 MULT_48(.mult_i(reg_o[48]), .mult_o(mult_o[48]) );
GF8Mult49 MULT_49(.mult_i(reg_o[49]), .mult_o(mult_o[49]) );
GF8Mult50 MULT_50(.mult_i(reg_o[50]), .mult_o(mult_o[50]) );
GF8Mult51 MULT_51(.mult_i(reg_o[51]), .mult_o(mult_o[51]) );
GF8Mult52 MULT_52(.mult_i(reg_o[52]), .mult_o(mult_o[52]) );
GF8Mult53 MULT_53(.mult_i(reg_o[53]), .mult_o(mult_o[53]) );
GF8Mult54 MULT_54(.mult_i(reg_o[54]), .mult_o(mult_o[54]) );
GF8Mult55 MULT_55(.mult_i(reg_o[55]), .mult_o(mult_o[55]) );
GF8Mult56 MULT_56(.mult_i(reg_o[56]), .mult_o(mult_o[56]) );
GF8Mult57 MULT_57(.mult_i(reg_o[57]), .mult_o(mult_o[57]) );
GF8Mult58 MULT_58(.mult_i(reg_o[58]), .mult_o(mult_o[58]) );
GF8Mult59 MULT_59(.mult_i(reg_o[59]), .mult_o(mult_o[59]) );
GF8Mult60 MULT_60(.mult_i(reg_o[60]), .mult_o(mult_o[60]) );
GF8Mult61 MULT_61(.mult_i(reg_o[61]), .mult_o(mult_o[61]) );
GF8Mult62 MULT_62(.mult_i(reg_o[62]), .mult_o(mult_o[62]) );
GF8Mult63 MULT_63(.mult_i(reg_o[63]), .mult_o(mult_o[63]) );
GF8Mult64 MULT_64(.mult_i(reg_o[64]), .mult_o(mult_o[64]) );
GF8Mult65 MULT_65(.mult_i(reg_o[65]), .mult_o(mult_o[65]) );
GF8Mult66 MULT_66(.mult_i(reg_o[66]), .mult_o(mult_o[66]) );
GF8Mult67 MULT_67(.mult_i(reg_o[67]), .mult_o(mult_o[67]) );
GF8Mult68 MULT_68(.mult_i(reg_o[68]), .mult_o(mult_o[68]) );
GF8Mult69 MULT_69(.mult_i(reg_o[69]), .mult_o(mult_o[69]) );
GF8Mult70 MULT_70(.mult_i(reg_o[70]), .mult_o(mult_o[70]) );
GF8Mult71 MULT_71(.mult_i(reg_o[71]), .mult_o(mult_o[71]) );
GF8Mult72 MULT_72(.mult_i(reg_o[72]), .mult_o(mult_o[72]) );
GF8Mult73 MULT_73(.mult_i(reg_o[73]), .mult_o(mult_o[73]) );
GF8Mult74 MULT_74(.mult_i(reg_o[74]), .mult_o(mult_o[74]) );
GF8Mult75 MULT_75(.mult_i(reg_o[75]), .mult_o(mult_o[75]) );
GF8Mult76 MULT_76(.mult_i(reg_o[76]), .mult_o(mult_o[76]) );
GF8Mult77 MULT_77(.mult_i(reg_o[77]), .mult_o(mult_o[77]) );
GF8Mult78 MULT_78(.mult_i(reg_o[78]), .mult_o(mult_o[78]) );
GF8Mult79 MULT_79(.mult_i(reg_o[79]), .mult_o(mult_o[79]) );
GF8Mult80 MULT_80(.mult_i(reg_o[80]), .mult_o(mult_o[80]) );
GF8Mult81 MULT_81(.mult_i(reg_o[81]), .mult_o(mult_o[81]) );
GF8Mult82 MULT_82(.mult_i(reg_o[82]), .mult_o(mult_o[82]) );
GF8Mult83 MULT_83(.mult_i(reg_o[83]), .mult_o(mult_o[83]) );
GF8Mult84 MULT_84(.mult_i(reg_o[84]), .mult_o(mult_o[84]) );
GF8Mult85 MULT_85(.mult_i(reg_o[85]), .mult_o(mult_o[85]) );
GF8Mult86 MULT_86(.mult_i(reg_o[86]), .mult_o(mult_o[86]) );
GF8Mult87 MULT_87(.mult_i(reg_o[87]), .mult_o(mult_o[87]) );
GF8Mult88 MULT_88(.mult_i(reg_o[88]), .mult_o(mult_o[88]) );
GF8Mult89 MULT_89(.mult_i(reg_o[89]), .mult_o(mult_o[89]) );
GF8Mult90 MULT_90(.mult_i(reg_o[90]), .mult_o(mult_o[90]) );
GF8Mult91 MULT_91(.mult_i(reg_o[91]), .mult_o(mult_o[91]) );
GF8Mult92 MULT_92(.mult_i(reg_o[92]), .mult_o(mult_o[92]) );
GF8Mult93 MULT_93(.mult_i(reg_o[93]), .mult_o(mult_o[93]) );
GF8Mult94 MULT_94(.mult_i(reg_o[94]), .mult_o(mult_o[94]) );
GF8Mult95 MULT_95(.mult_i(reg_o[95]), .mult_o(mult_o[95]) );
GF8Mult96 MULT_96(.mult_i(reg_o[96]), .mult_o(mult_o[96]) );
GF8Mult97 MULT_97(.mult_i(reg_o[97]), .mult_o(mult_o[97]) );
GF8Mult98 MULT_98(.mult_i(reg_o[98]), .mult_o(mult_o[98]) );
GF8Mult99 MULT_99(.mult_i(reg_o[99]), .mult_o(mult_o[99]) );
GF8Mult100 MULT_100(.mult_i(reg_o[100]), .mult_o(mult_o[100]) );
GF8Mult101 MULT_101(.mult_i(reg_o[101]), .mult_o(mult_o[101]) );
GF8Mult102 MULT_102(.mult_i(reg_o[102]), .mult_o(mult_o[102]) );
GF8Mult103 MULT_103(.mult_i(reg_o[103]), .mult_o(mult_o[103]) );
GF8Mult104 MULT_104(.mult_i(reg_o[104]), .mult_o(mult_o[104]) );
GF8Mult105 MULT_105(.mult_i(reg_o[105]), .mult_o(mult_o[105]) );
GF8Mult106 MULT_106(.mult_i(reg_o[106]), .mult_o(mult_o[106]) );
GF8Mult107 MULT_107(.mult_i(reg_o[107]), .mult_o(mult_o[107]) );
GF8Mult108 MULT_108(.mult_i(reg_o[108]), .mult_o(mult_o[108]) );
GF8Mult109 MULT_109(.mult_i(reg_o[109]), .mult_o(mult_o[109]) );
GF8Mult110 MULT_110(.mult_i(reg_o[110]), .mult_o(mult_o[110]) );
GF8Mult111 MULT_111(.mult_i(reg_o[111]), .mult_o(mult_o[111]) );
GF8Mult112 MULT_112(.mult_i(reg_o[112]), .mult_o(mult_o[112]) );
GF8Mult113 MULT_113(.mult_i(reg_o[113]), .mult_o(mult_o[113]) );
GF8Mult114 MULT_114(.mult_i(reg_o[114]), .mult_o(mult_o[114]) );
GF8Mult115 MULT_115(.mult_i(reg_o[115]), .mult_o(mult_o[115]) );
GF8Mult116 MULT_116(.mult_i(reg_o[116]), .mult_o(mult_o[116]) );
GF8Mult117 MULT_117(.mult_i(reg_o[117]), .mult_o(mult_o[117]) );
GF8Mult118 MULT_118(.mult_i(reg_o[118]), .mult_o(mult_o[118]) );
GF8Mult119 MULT_119(.mult_i(reg_o[119]), .mult_o(mult_o[119]) );
GF8Mult120 MULT_120(.mult_i(reg_o[120]), .mult_o(mult_o[120]) );
GF8Mult121 MULT_121(.mult_i(reg_o[121]), .mult_o(mult_o[121]) );
GF8Mult122 MULT_122(.mult_i(reg_o[122]), .mult_o(mult_o[122]) );
GF8Mult123 MULT_123(.mult_i(reg_o[123]), .mult_o(mult_o[123]) );
GF8Mult124 MULT_124(.mult_i(reg_o[124]), .mult_o(mult_o[124]) );
GF8Mult125 MULT_125(.mult_i(reg_o[125]), .mult_o(mult_o[125]) );
GF8Mult126 MULT_126(.mult_i(reg_o[126]), .mult_o(mult_o[126]) );
GF8Mult127 MULT_127(.mult_i(reg_o[127]), .mult_o(mult_o[127]) );
GF8Mult128 MULT_128(.mult_i(reg_o[128]), .mult_o(mult_o[128]) );
GF8Mult129 MULT_129(.mult_i(reg_o[129]), .mult_o(mult_o[129]) );
GF8Mult130 MULT_130(.mult_i(reg_o[130]), .mult_o(mult_o[130]) );
GF8Mult131 MULT_131(.mult_i(reg_o[131]), .mult_o(mult_o[131]) );
GF8Mult132 MULT_132(.mult_i(reg_o[132]), .mult_o(mult_o[132]) );
GF8Mult133 MULT_133(.mult_i(reg_o[133]), .mult_o(mult_o[133]) );
GF8Mult134 MULT_134(.mult_i(reg_o[134]), .mult_o(mult_o[134]) );
GF8Mult135 MULT_135(.mult_i(reg_o[135]), .mult_o(mult_o[135]) );
GF8Mult136 MULT_136(.mult_i(reg_o[136]), .mult_o(mult_o[136]) );
GF8Mult137 MULT_137(.mult_i(reg_o[137]), .mult_o(mult_o[137]) );
GF8Mult138 MULT_138(.mult_i(reg_o[138]), .mult_o(mult_o[138]) );
GF8Mult139 MULT_139(.mult_i(reg_o[139]), .mult_o(mult_o[139]) );
GF8Mult140 MULT_140(.mult_i(reg_o[140]), .mult_o(mult_o[140]) );
GF8Mult141 MULT_141(.mult_i(reg_o[141]), .mult_o(mult_o[141]) );
GF8Mult142 MULT_142(.mult_i(reg_o[142]), .mult_o(mult_o[142]) );
GF8Mult143 MULT_143(.mult_i(reg_o[143]), .mult_o(mult_o[143]) );
GF8Mult144 MULT_144(.mult_i(reg_o[144]), .mult_o(mult_o[144]) );
GF8Mult145 MULT_145(.mult_i(reg_o[145]), .mult_o(mult_o[145]) );
GF8Mult146 MULT_146(.mult_i(reg_o[146]), .mult_o(mult_o[146]) );
GF8Mult147 MULT_147(.mult_i(reg_o[147]), .mult_o(mult_o[147]) );
GF8Mult148 MULT_148(.mult_i(reg_o[148]), .mult_o(mult_o[148]) );
GF8Mult149 MULT_149(.mult_i(reg_o[149]), .mult_o(mult_o[149]) );
GF8Mult150 MULT_150(.mult_i(reg_o[150]), .mult_o(mult_o[150]) );
GF8Mult151 MULT_151(.mult_i(reg_o[151]), .mult_o(mult_o[151]) );
GF8Mult152 MULT_152(.mult_i(reg_o[152]), .mult_o(mult_o[152]) );
GF8Mult153 MULT_153(.mult_i(reg_o[153]), .mult_o(mult_o[153]) );
GF8Mult154 MULT_154(.mult_i(reg_o[154]), .mult_o(mult_o[154]) );
GF8Mult155 MULT_155(.mult_i(reg_o[155]), .mult_o(mult_o[155]) );
GF8Mult156 MULT_156(.mult_i(reg_o[156]), .mult_o(mult_o[156]) );
GF8Mult157 MULT_157(.mult_i(reg_o[157]), .mult_o(mult_o[157]) );
GF8Mult158 MULT_158(.mult_i(reg_o[158]), .mult_o(mult_o[158]) );
GF8Mult159 MULT_159(.mult_i(reg_o[159]), .mult_o(mult_o[159]) );
GF8Mult160 MULT_160(.mult_i(reg_o[160]), .mult_o(mult_o[160]) );
GF8Mult161 MULT_161(.mult_i(reg_o[161]), .mult_o(mult_o[161]) );
GF8Mult162 MULT_162(.mult_i(reg_o[162]), .mult_o(mult_o[162]) );
GF8Mult163 MULT_163(.mult_i(reg_o[163]), .mult_o(mult_o[163]) );
GF8Mult164 MULT_164(.mult_i(reg_o[164]), .mult_o(mult_o[164]) );
GF8Mult165 MULT_165(.mult_i(reg_o[165]), .mult_o(mult_o[165]) );
GF8Mult166 MULT_166(.mult_i(reg_o[166]), .mult_o(mult_o[166]) );
GF8Mult167 MULT_167(.mult_i(reg_o[167]), .mult_o(mult_o[167]) );
GF8Mult168 MULT_168(.mult_i(reg_o[168]), .mult_o(mult_o[168]) );
GF8Mult169 MULT_169(.mult_i(reg_o[169]), .mult_o(mult_o[169]) );
GF8Mult170 MULT_170(.mult_i(reg_o[170]), .mult_o(mult_o[170]) );
GF8Mult171 MULT_171(.mult_i(reg_o[171]), .mult_o(mult_o[171]) );
GF8Mult172 MULT_172(.mult_i(reg_o[172]), .mult_o(mult_o[172]) );
GF8Mult173 MULT_173(.mult_i(reg_o[173]), .mult_o(mult_o[173]) );
GF8Mult174 MULT_174(.mult_i(reg_o[174]), .mult_o(mult_o[174]) );
GF8Mult175 MULT_175(.mult_i(reg_o[175]), .mult_o(mult_o[175]) );
GF8Mult176 MULT_176(.mult_i(reg_o[176]), .mult_o(mult_o[176]) );
GF8Mult177 MULT_177(.mult_i(reg_o[177]), .mult_o(mult_o[177]) );
GF8Mult178 MULT_178(.mult_i(reg_o[178]), .mult_o(mult_o[178]) );
GF8Mult179 MULT_179(.mult_i(reg_o[179]), .mult_o(mult_o[179]) );
GF8Mult180 MULT_180(.mult_i(reg_o[180]), .mult_o(mult_o[180]) );
GF8Mult181 MULT_181(.mult_i(reg_o[181]), .mult_o(mult_o[181]) );
GF8Mult182 MULT_182(.mult_i(reg_o[182]), .mult_o(mult_o[182]) );
GF8Mult183 MULT_183(.mult_i(reg_o[183]), .mult_o(mult_o[183]) );
GF8Mult184 MULT_184(.mult_i(reg_o[184]), .mult_o(mult_o[184]) );
GF8Mult185 MULT_185(.mult_i(reg_o[185]), .mult_o(mult_o[185]) );
GF8Mult186 MULT_186(.mult_i(reg_o[186]), .mult_o(mult_o[186]) );
GF8Mult187 MULT_187(.mult_i(reg_o[187]), .mult_o(mult_o[187]) );
GF8Mult188 MULT_188(.mult_i(reg_o[188]), .mult_o(mult_o[188]) );
GF8Mult189 MULT_189(.mult_i(reg_o[189]), .mult_o(mult_o[189]) );
GF8Mult190 MULT_190(.mult_i(reg_o[190]), .mult_o(mult_o[190]) );
GF8Mult191 MULT_191(.mult_i(reg_o[191]), .mult_o(mult_o[191]) );
GF8Mult192 MULT_192(.mult_i(reg_o[192]), .mult_o(mult_o[192]) );
GF8Mult193 MULT_193(.mult_i(reg_o[193]), .mult_o(mult_o[193]) );
GF8Mult194 MULT_194(.mult_i(reg_o[194]), .mult_o(mult_o[194]) );
GF8Mult195 MULT_195(.mult_i(reg_o[195]), .mult_o(mult_o[195]) );
GF8Mult196 MULT_196(.mult_i(reg_o[196]), .mult_o(mult_o[196]) );
GF8Mult197 MULT_197(.mult_i(reg_o[197]), .mult_o(mult_o[197]) );
GF8Mult198 MULT_198(.mult_i(reg_o[198]), .mult_o(mult_o[198]) );
GF8Mult199 MULT_199(.mult_i(reg_o[199]), .mult_o(mult_o[199]) );
GF8Mult200 MULT_200(.mult_i(reg_o[200]), .mult_o(mult_o[200]) );
GF8Mult201 MULT_201(.mult_i(reg_o[201]), .mult_o(mult_o[201]) );
GF8Mult202 MULT_202(.mult_i(reg_o[202]), .mult_o(mult_o[202]) );
GF8Mult203 MULT_203(.mult_i(reg_o[203]), .mult_o(mult_o[203]) );
GF8Mult204 MULT_204(.mult_i(reg_o[204]), .mult_o(mult_o[204]) );
GF8Mult205 MULT_205(.mult_i(reg_o[205]), .mult_o(mult_o[205]) );
GF8Mult206 MULT_206(.mult_i(reg_o[206]), .mult_o(mult_o[206]) );
GF8Mult207 MULT_207(.mult_i(reg_o[207]), .mult_o(mult_o[207]) );
GF8Mult208 MULT_208(.mult_i(reg_o[208]), .mult_o(mult_o[208]) );
GF8Mult209 MULT_209(.mult_i(reg_o[209]), .mult_o(mult_o[209]) );
GF8Mult210 MULT_210(.mult_i(reg_o[210]), .mult_o(mult_o[210]) );
GF8Mult211 MULT_211(.mult_i(reg_o[211]), .mult_o(mult_o[211]) );
GF8Mult212 MULT_212(.mult_i(reg_o[212]), .mult_o(mult_o[212]) );
GF8Mult213 MULT_213(.mult_i(reg_o[213]), .mult_o(mult_o[213]) );
GF8Mult214 MULT_214(.mult_i(reg_o[214]), .mult_o(mult_o[214]) );
GF8Mult215 MULT_215(.mult_i(reg_o[215]), .mult_o(mult_o[215]) );
GF8Mult216 MULT_216(.mult_i(reg_o[216]), .mult_o(mult_o[216]) );
GF8Mult217 MULT_217(.mult_i(reg_o[217]), .mult_o(mult_o[217]) );
GF8Mult218 MULT_218(.mult_i(reg_o[218]), .mult_o(mult_o[218]) );
GF8Mult219 MULT_219(.mult_i(reg_o[219]), .mult_o(mult_o[219]) );
GF8Mult220 MULT_220(.mult_i(reg_o[220]), .mult_o(mult_o[220]) );
GF8Mult221 MULT_221(.mult_i(reg_o[221]), .mult_o(mult_o[221]) );
GF8Mult222 MULT_222(.mult_i(reg_o[222]), .mult_o(mult_o[222]) );
GF8Mult223 MULT_223(.mult_i(reg_o[223]), .mult_o(mult_o[223]) );
GF8Mult224 MULT_224(.mult_i(reg_o[224]), .mult_o(mult_o[224]) );
GF8Mult225 MULT_225(.mult_i(reg_o[225]), .mult_o(mult_o[225]) );
GF8Mult226 MULT_226(.mult_i(reg_o[226]), .mult_o(mult_o[226]) );
GF8Mult227 MULT_227(.mult_i(reg_o[227]), .mult_o(mult_o[227]) );
GF8Mult228 MULT_228(.mult_i(reg_o[228]), .mult_o(mult_o[228]) );
GF8Mult229 MULT_229(.mult_i(reg_o[229]), .mult_o(mult_o[229]) );
GF8Mult230 MULT_230(.mult_i(reg_o[230]), .mult_o(mult_o[230]) );
GF8Mult231 MULT_231(.mult_i(reg_o[231]), .mult_o(mult_o[231]) );
GF8Mult232 MULT_232(.mult_i(reg_o[232]), .mult_o(mult_o[232]) );
GF8Mult233 MULT_233(.mult_i(reg_o[233]), .mult_o(mult_o[233]) );
GF8Mult234 MULT_234(.mult_i(reg_o[234]), .mult_o(mult_o[234]) );
GF8Mult235 MULT_235(.mult_i(reg_o[235]), .mult_o(mult_o[235]) );
GF8Mult236 MULT_236(.mult_i(reg_o[236]), .mult_o(mult_o[236]) );
GF8Mult237 MULT_237(.mult_i(reg_o[237]), .mult_o(mult_o[237]) );
GF8Mult238 MULT_238(.mult_i(reg_o[238]), .mult_o(mult_o[238]) );
GF8Mult239 MULT_239(.mult_i(reg_o[239]), .mult_o(mult_o[239]) );
GF8Mult240 MULT_240(.mult_i(reg_o[240]), .mult_o(mult_o[240]) );
GF8Mult241 MULT_241(.mult_i(reg_o[241]), .mult_o(mult_o[241]) );
GF8Mult242 MULT_242(.mult_i(reg_o[242]), .mult_o(mult_o[242]) );
GF8Mult243 MULT_243(.mult_i(reg_o[243]), .mult_o(mult_o[243]) );
GF8Mult244 MULT_244(.mult_i(reg_o[244]), .mult_o(mult_o[244]) );
GF8Mult245 MULT_245(.mult_i(reg_o[245]), .mult_o(mult_o[245]) );
GF8Mult246 MULT_246(.mult_i(reg_o[246]), .mult_o(mult_o[246]) );
GF8Mult247 MULT_247(.mult_i(reg_o[247]), .mult_o(mult_o[247]) );
GF8Mult248 MULT_248(.mult_i(reg_o[248]), .mult_o(mult_o[248]) );
GF8Mult249 MULT_249(.mult_i(reg_o[249]), .mult_o(mult_o[249]) );
GF8Mult250 MULT_250(.mult_i(reg_o[250]), .mult_o(mult_o[250]) );
GF8Mult251 MULT_251(.mult_i(reg_o[251]), .mult_o(mult_o[251]) );
GF8Mult252 MULT_252(.mult_i(reg_o[252]), .mult_o(mult_o[252]) );
GF8Mult253 MULT_253(.mult_i(reg_o[253]), .mult_o(mult_o[253]) );
GF8Mult254 MULT_254(.mult_i(reg_o[254]), .mult_o(mult_o[254]) );
// INPUT MUX TO THE REGISTER
// INPUTS FROM THE LEFT To REGISTER FOR CALCULATING DFT
// AND RIGHT TO CALCULATE IDFT
// AND SAME TO CALCULATE RES
// FIRST MUX
Mux8To1 MUX0(
.sel_i(dft_sel_i),
.mux_i0(mult_o[0]),
.mux_i1(dft_i),
.mux_o(mux_o[0]) );
genvar l;
generate
for (l=1; l < 255; l = l+1) begin:INPUTMUXES
Mux8To1 MUX(
.sel_i(dft_sel_i),
.mux_i0(mult_o[l]),
.mux_i1(reg_o[l-1]),
.mux_o(mux_o[l]));
end
endgenerate
genvar j;
generate
for (j=0; j < 255; j = j+1) begin:DFT_IDFTBLOCKS
GF8Reg REG(.clk_i(clk_i),
.rst_i(rst_i),
.en_i(en_i),
.reg_i(mux_o[j]),
.reg_o(reg_o[j]));
end
endgenerate
////////// ADDER TREE //////////
GF8Add Add_0(
.add_i1(mult_o[0]),
.add_i2(mult_o[1]),
.add_o(add_o[0]));
genvar k;
generate
for (k=1; k < 254; k = k+1) begin:ADD_TREE
GF8Add Add(
.add_i1(add_o[k-1]),
.add_i2(mult_o[k+1]),
.add_o(add_o[k]));
end
endgenerate
////////////////////
endmodule
/rs_encoder_decoder/rtl/RS8Encoder8t.v
0,0 → 1,209
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware DFT and IDFT
 
module RS8Encoder8t(clk_i, rst_i,
encoder_i, // Control Signal calculates dft if dft_idft = 0 else idft if dft_idft = 1
valid_i, // Control Signal
encoder_o, // Gallios Field Register input 1
parity_o,
busy_o
);
// Inputs are declared here
input clk_i,rst_i; // Clock and Reset Declaration
input valid_i; // Controll Signal That does All the Required Operations
input [7:0] encoder_i;
output reg [7:0] encoder_o;
output reg parity_o;
output reg busy_o;
// Declaration of Wires And Register are here
reg [7:0] enc_reg; // register inputs
reg [7:0] reg_o [0:15];
reg reg_o_o;
reg [7:0] add_i;
reg [8:0] input_counter;
wire [7:0] mult_o[0:15];
 
// Combinational Body
always @(input_counter or reg_o[0] or encoder_i) begin
if (input_counter < 241) begin
encoder_o = enc_reg;
end
else begin
encoder_o = reg_o[0];
end
end
always @(input_counter) begin
if(|input_counter)
parity_o = 1;
else
parity_o = 0;
end
always @(input_counter)begin
if(input_counter>=239)
busy_o = 1;
else
busy_o = 0;
end
always @(input_counter or encoder_i or reg_o[0]) begin
if(input_counter == 1)
add_i = enc_reg;
else if(input_counter <240)
add_i = reg_o[0]^enc_reg;
else
add_i = 8'b0;
end
 
// Sequential Circuit Starts from Here
// input counter that counts no of inputs set
always @(posedge clk_i) begin
if(rst_i)
enc_reg <= 0;
else
enc_reg <= encoder_i;
end
always @(posedge clk_i) begin
if((rst_i) || (input_counter[8])) begin
input_counter <= 0;
end
else if (valid_i) begin
input_counter <= input_counter + 1;
end
end
always @(posedge clk_i) begin
if (rst_i) begin
reg_o[0] <= 0;
reg_o[1] <= 0;
reg_o[2] <= 0;
reg_o[3] <= 0;
reg_o[4] <= 0;
reg_o[5] <= 0;
reg_o[6] <= 0;
reg_o[7] <= 0;
reg_o[8] <= 0;
reg_o[9] <= 0;
reg_o[10] <= 0;
reg_o[11] <= 0;
reg_o[12] <= 0;
reg_o[13] <= 0;
reg_o[14] <= 0;
reg_o[15] <= 0;
end
else if(input_counter == 1) begin
reg_o[0] <= mult_o[0];
reg_o[1] <= mult_o[1];
reg_o[2] <= mult_o[2];
reg_o[3] <= mult_o[3];
reg_o[4] <= mult_o[4];
reg_o[5] <= mult_o[5];
reg_o[6] <= mult_o[6];
reg_o[7] <= mult_o[7];
reg_o[8] <= mult_o[8];
reg_o[9] <= mult_o[9];
reg_o[10] <= mult_o[10];
reg_o[11] <= mult_o[11];
reg_o[12] <= mult_o[12];
reg_o[13] <= mult_o[13];
reg_o[14] <= mult_o[14];
reg_o[15] <= mult_o[15];
end
else begin
reg_o[0] <= reg_o[1]^mult_o[0];
reg_o[1] <= reg_o[2]^mult_o[1];
reg_o[2] <= reg_o[3]^mult_o[2];
reg_o[3] <= reg_o[4]^mult_o[3];
reg_o[4] <= reg_o[5]^mult_o[4];
reg_o[5] <= reg_o[6]^mult_o[5];
reg_o[6] <= reg_o[7]^mult_o[6];
reg_o[7] <= reg_o[8]^mult_o[7];
reg_o[8] <= reg_o[9]^mult_o[8];
reg_o[9] <= reg_o[10]^mult_o[9];
reg_o[10] <= reg_o[11]^mult_o[10];
reg_o[11] <= reg_o[12]^mult_o[11];
reg_o[12] <= reg_o[13]^mult_o[12];
reg_o[13] <= reg_o[14]^mult_o[13];
reg_o[14] <= reg_o[15]^mult_o[14];
reg_o[15] <= mult_o[15];
end
end
 
///////////////// Structural Model ////////////////
// Multipliers Depending on the Generator Polynomial
GF8Mult121 MULT_0(
.mult_i(add_i),
.mult_o(mult_o[0]) );
GF8Mult106 MULT_1(
.mult_i(add_i),
.mult_o(mult_o[1]) );
GF8Mult110 MULT_2(
.mult_i(add_i),
.mult_o(mult_o[2]) );
GF8Mult113 MULT_3(
.mult_i(add_i),
.mult_o(mult_o[3]) );
GF8Mult107 MULT_4(
.mult_i(add_i),
.mult_o(mult_o[4]) );
GF8Mult167 MULT_5(
.mult_i(add_i),
.mult_o(mult_o[5]) );
GF8Mult83 MULT_6(
.mult_i(add_i),
.mult_o(mult_o[6]) );
GF8Mult11 MULT_7(
.mult_i(add_i),
.mult_o(mult_o[7]) );
GF8Mult100 MULT_8(
.mult_i(add_i),
.mult_o(mult_o[8]) );
GF8Mult201 MULT_9(
.mult_i(add_i),
.mult_o(mult_o[9]) );
GF8Mult158 MULT_10(
.mult_i(add_i),
.mult_o(mult_o[10]) );
GF8Mult181 MULT_11(
.mult_i(add_i),
.mult_o(mult_o[11]) );
GF8Mult195 MULT_12(
.mult_i(add_i),
.mult_o(mult_o[12]) );
GF8Mult208 MULT_13(
.mult_i(add_i),
.mult_o(mult_o[13]) );
GF8Mult240 MULT_14(
.mult_i(add_i),
.mult_o(mult_o[14]) );
GF8Mult136 MULT_15(
.mult_i(add_i),
.mult_o(mult_o[15]) );
 
///////////INPUT ADDER/////////
endmodule
/rs_encoder_decoder/rtl/GF8GenMultBitSer.v
0,0 → 1,111
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Generic
// Bit Serial Hardware Multiplier
 
module GF8GenMultBitSer(clk_i, rst_i,
valid_i, // Valid Input Set it to High When giving the input
mult_i1, // Gallios Field Generic Bit Serial Multiplier input 1
mult_i2, // Gallios Field Generic Bit Serial Multiplier input 2
valid_o, // Valid Out High When The output is ready
mult_o // Gallios Field Generic Bit Serial Multiplier output
);
// Inputs are declared here
input clk_i,rst_i; // Clock and Reset Declaration
input valid_i;
input [7:0] mult_i1, mult_i2;
output reg valid_o;
output wire [7:0] mult_o;
// Declaration of Wires And Register are here
reg [7:0] regA, regB, regC;
reg [3:0] cnt;
reg [0:0] state;
 
assign mult_o = regA;
 
parameter WAIT = 1'b0;
parameter PROCESS = 1'b1;
// Counter To Calculate The Clock cycles for the Output
always @(posedge clk_i) begin
if(rst_i) begin
cnt = 0;
regA <= 0;
regB <= 0;
regC <= 0;
valid_o <= 0;
state <= WAIT;
end
else begin
case(state)
WAIT: if(valid_i) begin
state <= PROCESS;
regA <= 0;
regC[0]<= mult_i1[7];
regC[1]<= mult_i1[6];
regC[2]<= mult_i1[5];
regC[3]<= mult_i1[4];
regC[4]<= mult_i1[3];
regC[5]<= mult_i1[2];
regC[6]<= mult_i1[1];
regC[7]<= mult_i1[0];
regB[0]<= mult_i2[0];
regB[1]<= mult_i2[1];
regB[2]<= mult_i2[2];
regB[3]<= mult_i2[3];
regB[4]<= mult_i2[4];
regB[5]<= mult_i2[5];
regB[6]<= mult_i2[6];
regB[7]<= mult_i2[7];
cnt = 0;
valid_o <= 0;
end else begin
state <= WAIT;
cnt = 0;
regA <= 0;
regB <= 0;
regC <= 0;
valid_o <= 0;
end
PROCESS: if(cnt == 8) begin
state <= WAIT;
valid_o <= 1;
regA <= regA;
regB <= regB;
regC <= regC;
end else begin
state <= PROCESS;
regA[0] <= regA[0]^(regC[7]&regB[0]);
regA[1] <= regA[1]^(regC[7]&regB[1]);
regA[2] <= regA[2]^(regC[7]&regB[2]);
regA[3] <= regA[3]^(regC[7]&regB[3]);
regA[4] <= regA[4]^(regC[7]&regB[4]);
regA[5] <= regA[5]^(regC[7]&regB[5]);
regA[6] <= regA[6]^(regC[7]&regB[6]);
regA[7] <= regA[7]^(regC[7]&regB[7]);
 
regB[1] <= regB[0];
regB[2] <= regB[1]^regB[7];
regB[3] <= regB[2]^regB[7];
regB[4] <= regB[3]^regB[7];
regB[5] <= regB[4];
regB[6] <= regB[5];
regB[7] <= regB[6];
regB[0] <= regB[7];
 
regC[1] <= regC[0];
regC[2] <= regC[1];
regC[3] <= regC[2];
regC[4] <= regC[3];
regC[5] <= regC[4];
regC[6] <= regC[5];
regC[7] <= regC[6];
regC[0] <= regC[7];
 
cnt = cnt + 1;
valid_o <= 0;
end
default : state <= WAIT;
endcase
end
end
endmodule
/rs_encoder_decoder/rtl/RS8CALCR08.v
0,0 → 1,153
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Register
 
module RS8CALCR08(clk_i, rst_i,
en_i, // Enable Signal
sigma_i, // sigma value in to calculate R0
syndrom_i, // Syndrom value from the memory
loc_o, // mem_address
R_0_o, // Valid R_o when valid_o == 1
valid_o, // When processing done
done_dec_i // input to clear all the registers
);
// Inputs are declared here
input clk_i,rst_i,en_i; // Clock and Reset Declaration
input [71:0] sigma_i;
input [7:0] syndrom_i;
input done_dec_i;
output reg valid_o;
output reg [7:0] R_0_o;
output reg [7:0] loc_o;
 
// Declaration of Wires And Register are here
wire [7:0] add_i1;
wire [7:0] add_o;
reg acc;
reg [7:0] add_acc;
reg [7:0] mult_i2;
reg [7:0] mult_i1;
reg [71:0] sigma_t;
always@(posedge clk_i) begin
if(rst_i) begin
add_acc = 0;
end
else if(acc) begin
add_acc = add_o;
end
end
GF8GenMult MULT(
.mult_i1(mult_i1), // Generic Multiplier input 1
.mult_i2(mult_i2), // Generic Multiplier input 2
.mult_o(add_i1)); // Generic Multiplier output
GF8Add Add_ACC(
.add_i1(add_i1),
.add_i2(add_acc),
.add_o(add_o));
// Declaration of Register are here
reg [2:0] state;
 
parameter INIT = 3'b000;
parameter WAIT = 3'b001;
parameter CALC_ACC = 3'b010;
parameter INVERS = 3'b011;
parameter MULT_LAST = 3'b100;
parameter DONE = 3'b101;
 
always @(posedge clk_i) begin
if(rst_i) begin
state <= INIT;
loc_o <= 0;
mult_i2 <= 0;
mult_i1 <= 0;
sigma_t <= 0;
acc <= 0;
valid_o <= 0;
R_0_o <= 0;
end
else begin
case(state)
INIT: begin
state <= WAIT;
loc_o <= 8;
mult_i2 <= 0;
mult_i1 <= 0;
sigma_t <= 0;
acc <= 0;
valid_o <= 0;
R_0_o <= 0;
end
WAIT: begin
if (en_i) begin
state <= CALC_ACC;
end
else begin
state <= WAIT;
end
loc_o <= 8;
mult_i2 <= 0;
mult_i1 <= 0;
sigma_t <= sigma_i;
acc <= 0;
valid_o <= 0;
R_0_o <= R_0_o;
end
CALC_ACC: begin
if (loc_o < 15) begin
state <= CALC_ACC;
end
else begin
state <= MULT_LAST;
end
loc_o <= loc_o + 1;
mult_i1 <= syndrom_i;
mult_i2 <= sigma_t[71:64];
sigma_t <= sigma_t<<8;
acc <= 1;
valid_o <= 0;
R_0_o <= R_0_o;
end
MULT_LAST: begin
state <= DONE;
loc_o <= 0;
mult_i1 <= add_acc;
mult_i2 <= sigma_t[71:64];
sigma_t <= sigma_t;
acc <= 0;
valid_o <= 1;
R_0_o <= add_i1;
end
DONE: begin
if (done_dec_i)
state <= INIT;
else
state <= DONE;
loc_o <= 0;
mult_i2 <= add_acc;
mult_i1 <= sigma_t[71:64];
sigma_t <= sigma_t;
acc <= 0;
valid_o <= 1;
R_0_o <= add_i1;
end
default: begin
state <= INIT;
loc_o <= 0;
mult_i2 <= add_acc;
mult_i1 <= sigma_t[71:64];
sigma_t <= sigma_t;
acc <= 0;
valid_o <= 0;
R_0_o <= R_0_o;
end
endcase
end
end
endmodule
/rs_encoder_decoder/rtl/GF8SyndromBuffer.v
0,0 → 1,64
// THIS IS A SYNDROME BUFFER THAT PUTS DATA IN FIFO
// AND DATA CAN BE PICKED FROM THE LAST OF THE FIFO
// OR FROM LOCATION SPECIFIED BY loc_i
module GF8SyndromBuffer(clk_i, rst_i,
push_i, // push data
sel_i, // Enable Signal
loc_i, // Enable Signal
syndrom_i, // input syndrom
syndrom_o // data from loc
);
// Inputs are declared here
input clk_i,rst_i,push_i; // Clock and Reset Declaration
input sel_i;
input [4:0] loc_i;
input [7:0] syndrom_i;
output wire [7:0] syndrom_o;
// This is first 2*t syndrome buffer
reg [7:0] shift_reg[0:16];
 
assign syndrom_o = sel_i?shift_reg[loc_i]:shift_reg[16];
 
// Sequential Body
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
shift_reg[0] <= 0;
shift_reg[1] <= 0;
shift_reg[2] <= 0;
shift_reg[3] <= 0;
shift_reg[4] <= 0;
shift_reg[5] <= 0;
shift_reg[6] <= 0;
shift_reg[7] <= 0;
shift_reg[8] <= 0;
shift_reg[9] <= 0;
shift_reg[10] <= 0;
shift_reg[11] <= 0;
shift_reg[12] <= 0;
shift_reg[13] <= 0;
shift_reg[14] <= 0;
shift_reg[15] <= 0;
shift_reg[16] <= 0;
end
else if(push_i) begin
shift_reg[0] <= syndrom_i;
shift_reg[1] <= shift_reg[0];
shift_reg[2] <= shift_reg[1];
shift_reg[3] <= shift_reg[2];
shift_reg[4] <= shift_reg[3];
shift_reg[5] <= shift_reg[4];
shift_reg[6] <= shift_reg[5];
shift_reg[7] <= shift_reg[6];
shift_reg[8] <= shift_reg[7];
shift_reg[9] <= shift_reg[8];
shift_reg[10] <= shift_reg[9];
shift_reg[11] <= shift_reg[10];
shift_reg[12] <= shift_reg[11];
shift_reg[13] <= shift_reg[12];
shift_reg[14] <= shift_reg[13];
shift_reg[15] <= shift_reg[14];
shift_reg[16] <= shift_reg[15];
end
end
endmodule
/rs_encoder_decoder/rtl/GF8Add_testbench.v
0,0 → 1,37
`timescale 1ns / 10 ps
 
module GF8Add_testbench;
reg clk_i,rst_i;
wire [7:0] add_o;
reg [7:0] add_i1,add_i2;
reg [126*7:0] path,input_file,output_file;
integer fd_in,fd_out;
GF8Add DUT(.clk_i(clk_i),.rst_i(rst_i),
.add_i1(add_i1),
.add_i2(add_i2),
.add_o(add_o));
always
#5 clk_i = !clk_i;
initial begin
path = "./";
input_file = "input_file_GF8Add.dat";
output_file = "output_file_GF8Add.dat";
fd_in = $fopen(input_file,"r");
fd_out = $fopen(output_file,"w");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
 
while(!$feof(fd_in))
begin
@(negedge clk_i);
$fscanf(fd_in,"%d %d\n ",add_i1,add_i2);
$fwrite(fd_out,"%d\n ",add_o);
end
end // initial begin
 
endmodule
/rs_encoder_decoder/rtl/GF8Add.v
0,0 → 1,25
// This is a verilog File Generated
// By The C++ program That Generates
// An Gallios Field Hardware Adder
 
module GF8Add(
add_i1, // Gallios Field Adder input 1
add_i2, // Gallios Field Adder input 2
add_o // Gallios Field Adder output
);
// Inputs are declared here
input [7:0] add_i1,add_i2;
output wire [7:0] add_o;
 
// Declaration of Wires And Register are here
// Combinational Logic Body
assign add_o[0] = add_i1[0]^add_i2[0];
assign add_o[1] = add_i1[1]^add_i2[1];
assign add_o[2] = add_i1[2]^add_i2[2];
assign add_o[3] = add_i1[3]^add_i2[3];
assign add_o[4] = add_i1[4]^add_i2[4];
assign add_o[5] = add_i1[5]^add_i2[5];
assign add_o[6] = add_i1[6]^add_i2[6];
assign add_o[7] = add_i1[7]^add_i2[7];
endmodule
/rs_encoder_decoder/rtl/RS8FreqDecode_TestFile.v
0,0 → 1,67
`timescale 1ns / 10 ps
 
module RS8FreqDocode8t_testbench;
reg clk_i,rst_i;
reg valid_i;
reg [7:0] enc_data_i;
wire [7:0] dec_data_o;
wire valid_o;
reg [126*7:0] path,input_file,output_file;
reg [1:0] cntr;
integer fd_in, fd_out;
wire busy;
RS8FreqDecode DUT(.clk_i(clk_i), .rst_i(rst_i),
.valid_i(valid_i), // input valid signal
.enc_data_i(enc_data_i), // encoded data
.dec_data_o(dec_data_o), // decoded output
.valid_o(valid_o), // decoded output
.busy_o(busy)
);
always @(posedge clk_i) begin
if (rst_i) begin
cntr <= 0;
end else if (valid_o) begin
cntr <= 0;
end else begin
cntr <= cntr+1;
end
end
always
#5 clk_i = !clk_i;
initial begin
path = "./";
input_file = "output_file_C_RSEncodedData.dat";// To Take Data From the Encoder Implemented in C
//input_file = "output_file_RSVerilogEncodedData.dat";// To Take Data From the Encoder Implemented in Verilog
output_file = $fopen("output_file_GF8Decoded.dat","w");
fd_in = $fopen(input_file,"r");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
 
while(1)
begin
@(posedge clk_i);
if((cntr == 1)&&(~busy)) begin
valid_i = 1;
end else begin
valid_i = 0;
end
if(valid_i)
$fscanf(fd_in,"%d\n",enc_data_i);
if(valid_o)
$fwrite(output_file,"%d\n",dec_data_o);
end
end // initial begin
 
endmodule
 
 
 
/rs_encoder_decoder/rtl/RS8FreqDecode.v
0,0 → 1,202
// This is a verilog File Generated
// By The C++ program That Generates
// Reed Solomon Controller
// Barlekamp Messay Controller
 
module RS8FreqDecode(clk_i, rst_i,
valid_i, // input valid signal
enc_data_i, // encoded data
dec_data_o, // decoded output
valid_o, // decoded output
busy_o
);
// Declaration of the inputs
input clk_i, rst_i;
input valid_i;
input [7:0] enc_data_i;
output wire [7:0] dec_data_o;
output wire valid_o;
output wire busy_o;
 
// Declaration of Wires And Register are here
// Control Signal To Calculate S_0
wire calc_S_0;
// Control signals To Calculate fourier transforms
wire [1:0] dft_sel; // select signal tells to calculate DFT or IDFT
wire dft_calc; // enable signal
 
// Control Signal to Calculate DELTA;
wire en_fir;
wire fir_sel;
 
// Control Signal for errolocpoly;
wire calc_bm_step;
wire [7:0] step;
wire done_bm_step;
wire push_zero;
// MEMORY CONTROL SIGNAL
wire wren;
wire [7:0] mem_address;
wire busy;
// MEMORY DATA SIGNAL
wire [7:0] mem_data;
// IDFT Zero Value CONTROL SIGNALS
wire load_last;
wire load_sel_out;
wire done_dec;
// Data Signal
wire [71:0] sigma; // original error loc poly
wire [71:0] sigma_0; // error loc poly with shifted right 8 bit and inv(sigma(0)) in the end
wire [71:0] sigma_last; // error loc poly with sigma(0) inversed
wire [71:0] fir_i_sigma;
wire [7:0] synd;
wire [7:0] fir_o;
wire [7:0] add_res;
wire [7:0] dft_all_in;
wire [7:0] dft_in;
wire [7:0] mem_data_o;
// R 0 Calculator Signals
wire [7:0] mem_loc; // mem address from the R_0 module is enabled when r_calc_sel is set to high
wire r_calc_sel; // R_0_calculate Control signal from the controller to select R0 memmory address
wire r_calc_done; // R_0_calculate control signal to the controller
wire r_calc; // enable signal to calculate R0
// R 0 Data signals
wire [7:0] R_0;
// Registers
reg [7:0] delta;
reg [7:0] last_in;
reg [7:0] S_0;
// mem address and control signal from the controler
wire [7:0] mem_addr;
wire mem_in;
assign busy_o = busy;
assign add_res = delta^synd;
// Decoder output
assign dec_data_o = load_sel_out?last_in:synd;
// MUX TO INPUT SIGMA OR SIGMA_O DEPENDING ON OPERATION
assign fir_i_sigma = fir_sel ? sigma_0: sigma;
// MUX FOR THE INPUT OF DFT_IDFT BLOCK
assign dft_in = dft_sel[1] ? mem_data_o:enc_data_i;
assign dft_all_in = push_zero ? 8'b00000000:dft_in;
// MEMORY MUXES
assign mem_address = r_calc_sel ? mem_loc:mem_addr;
assign mem_data = mem_in ? synd:add_res; //input first 16 syndrom of add_res
 
 
// SEQUENTIAL BODY
always @(posedge clk_i) begin
if((rst_i)||(done_dec))begin
S_0 <= 0;
end
else if (calc_S_0) begin
S_0 <= S_0^enc_data_i;
end
end
always @(posedge clk_i) begin
if((rst_i)||(done_dec))begin
last_in <= 0;
end
else if (load_last) begin
last_in <= last_in^add_res;
end
end
 
always @(posedge clk_i) begin
if ((rst_i)||(done_dec))
delta <= 0;
else
delta <= fir_o;
end
 
// STRUCTURAL MODEL OF RS DECODER
// MEMORY EVALUALTOR
Memmory EVALMEM(
.clk (clk_i),
.addr (mem_address),
.data (mem_data),
.we (wren),
.q ( mem_data_o )
);
 
GF8Dft_Idft DFTIDFT(.clk_i(clk_i), .rst_i(rst_i),
.dft_sel_i(dft_sel[0]), // Control Signal calculates dft if dft_idft = 0 else idft if dft_idft = 1
.en_i(dft_calc), // Control Signal
.dft_i(dft_all_in), // Gallios Field Register input 1
.dft_o(synd) // Gallios Field Register output
);
 
RS8Controller CNTRLER(.clk_i(clk_i),.rst_i(rst_i),
.valid_i(valid_i), // Controller input valid
.calc_S_0_o(calc_S_0), // Control Signal to Calculate S_0
.dft_sel_o(dft_sel), // select FFT or IFFT
.dft_calc_o(dft_calc), // calculate fourier transform
.mem_in_o(mem_in), // memory data selection control signal
.en_fir_o(en_fir), // calculate new delta
.fir_sel_o(fir_sel), // calculate new delta
.calc_bm_step_o(calc_bm_step), // Calculate BM Step
.step_o(step), // current_step
.done_bm_step_i(done_bm_step), // update from BM circuit
.elp_busy_i(elp_busy), // Controller input busy signal from error loc poly
.r_calc_o(r_calc), // TO Enable R0 calculator
.r_calc_sel_o(r_calc_sel), // To selsect R0 MEMORY ADDRESS
.r_calc_done_i(r_calc_done), // When R0 has completed the operation
.push_o(push_zero), // push data in syndrom
.mem_addr_o(mem_addr), // Memmory Address
.wren_o(wren), // Write Data IN memmory
.load_last_o(load_last), // Load Last
.last_in_sel_o(load_sel_out), // ouput data 0
.valid_o_o(valid_o), // Output from the Decode
.busy_o(busy), // Output from the Decoder
.done_dec_o(done_dec) // When The Complete Decoding is done
);
RS8ErrLocPoly8t CALCERRLOCPOLY(.clk_i(clk_i),.rst_i(rst_i),
.valid_i(calc_bm_step), // input 1
.delta_i(delta), // input 1
.step_i(step), // input 1
.done_dec_i(done_dec), // input 1
.valid_o(done_bm_step), // output
.sigma_0_o(sigma_0), // output
.sigma_o(sigma), // output
.sigma_last_o(sigma_last), // output
.busy_o(elp_busy) // Busy signal indication for processing
);
GF8Fir8t CALCDELTARE(
.clk_i(clk_i),.rst_i(rst_i),
.en_i(en_fir), // Gallios Field FIR Filter enable 1
.fir_i(synd), // Gallios Field FIR Filter input 1
.sel_i(fir_sel), // Gallios Field FIR Filter input 1
.coeff_i(fir_i_sigma), // Gallios Field FIR Coefficient input 1
.fir_o(fir_o), // Gallios Field FIR out
.done_dec_i(done_dec) // This is to clear every thing in this module
);
RS8CALCR08 R0CALC(.clk_i(clk_i), .rst_i(rst_i),
.en_i(r_calc), // Enable Signal
.sigma_i(sigma_last), // sigma value in to calculate R0
.syndrom_i(mem_data_o), // Syndrom value from the memory
.loc_o(mem_loc), // mem_address
.R_0_o(R_0), // Valid R_o when valid_o == 1
.valid_o(r_calc_done), // When processing done
.done_dec_i(done_dec) // input to clear all the registers
);
 
 
endmodule
/rs_encoder_decoder/rtl/GF8Fir8t.v
0,0 → 1,148
// This is a verilog File Generated
// By The C++ program That Generates
// Gallios Field Based FIR Filter
// And uses GF Adder and Multiplier
 
module GF8Fir8t(clk_i, rst_i,
en_i, // Gallios Field FIR Filter enable 1
fir_i, // Gallios Field FIR Filter input 1
sel_i, // Gallios Field FIR Filter input 1
coeff_i, // Concatinated Coefficient Input
fir_o, // Gallios Field FIR out
done_dec_i // Done Decoding
);
// Inputs are declared here
input clk_i,rst_i; // Clock and Reset Declaration
input en_i; // Enable The input
input sel_i; // Enable The input
input done_dec_i;
input [7:0] fir_i;
input [71:0] coeff_i;
output wire [7:0] fir_o;
// Declaration of Wires And Register are here
wire [7:0] mult_o[0:8];
wire [7:0] add_o [0:7];
wire [7:0] output_mux;
wire [7:0] input_mux;
reg [7:0] shift_reg[0:8];
assign input_mux = sel_i ? mult_o[8] : fir_i;
assign output_mux = sel_i ? add_o[6] : shift_reg[8];
assign fir_o = sel_i ? mult_o[8] : add_o[7];
// Sequential Body
always @(posedge clk_i) begin
if ((rst_i)||(done_dec_i)) begin
shift_reg[0] <= 0;
shift_reg[1] <= 0;
shift_reg[2] <= 0;
shift_reg[3] <= 0;
shift_reg[4] <= 0;
shift_reg[5] <= 0;
shift_reg[6] <= 0;
shift_reg[7] <= 0;
shift_reg[8] <= 0;
end
else if(en_i) begin
shift_reg[0] <= input_mux;
shift_reg[1] <= shift_reg[0];
shift_reg[2] <= shift_reg[1];
shift_reg[3] <= shift_reg[2];
shift_reg[4] <= shift_reg[3];
shift_reg[5] <= shift_reg[4];
shift_reg[6] <= shift_reg[5];
shift_reg[7] <= shift_reg[6];
shift_reg[8] <= shift_reg[7];
end
end
GF8GenMult MULT0(
.mult_i1(coeff_i[71:64]), // Generic Multiplier input 1
.mult_i2(shift_reg[0]), // Generic Multiplier input 2
.mult_o(mult_o[0])); // Generic Multiplier output
GF8GenMult MULT1(
.mult_i1(coeff_i[63:56]), // Generic Multiplier input 1
.mult_i2(shift_reg[1]), // Generic Multiplier input 2
.mult_o(mult_o[1])); // Generic Multiplier output
GF8GenMult MULT2(
.mult_i1(coeff_i[55:48]), // Generic Multiplier input 1
.mult_i2(shift_reg[2]), // Generic Multiplier input 2
.mult_o(mult_o[2])); // Generic Multiplier output
GF8GenMult MULT3(
.mult_i1(coeff_i[47:40]), // Generic Multiplier input 1
.mult_i2(shift_reg[3]), // Generic Multiplier input 2
.mult_o(mult_o[3])); // Generic Multiplier output
GF8GenMult MULT4(
.mult_i1(coeff_i[39:32]), // Generic Multiplier input 1
.mult_i2(shift_reg[4]), // Generic Multiplier input 2
.mult_o(mult_o[4])); // Generic Multiplier output
GF8GenMult MULT5(
.mult_i1(coeff_i[31:24]), // Generic Multiplier input 1
.mult_i2(shift_reg[5]), // Generic Multiplier input 2
.mult_o(mult_o[5])); // Generic Multiplier output
GF8GenMult MULT6(
.mult_i1(coeff_i[23:16]), // Generic Multiplier input 1
.mult_i2(shift_reg[6]), // Generic Multiplier input 2
.mult_o(mult_o[6])); // Generic Multiplier output
GF8GenMult MULT7(
.mult_i1(coeff_i[15:8]), // Generic Multiplier input 1
.mult_i2(shift_reg[7]), // Generic Multiplier input 2
.mult_o(mult_o[7])); // Generic Multiplier output
GF8GenMult MULTLAST(
.mult_i1(coeff_i[7:0]), // Generic Multiplier input 1
.mult_i2(output_mux), // Generic Multiplier input 2
.mult_o(mult_o[8])); // Generic Multiplier output
////////// ADDER TREE //////////
GF8Add Add_0(
.add_i1(mult_o[0]),
.add_i2(mult_o[1]),
.add_o(add_o[0]));
GF8Add Add1(
.add_i1(add_o[0]),
.add_i2(mult_o[2]),
.add_o(add_o[1]));
GF8Add Add2(
.add_i1(add_o[1]),
.add_i2(mult_o[3]),
.add_o(add_o[2]));
GF8Add Add3(
.add_i1(add_o[2]),
.add_i2(mult_o[4]),
.add_o(add_o[3]));
GF8Add Add4(
.add_i1(add_o[3]),
.add_i2(mult_o[5]),
.add_o(add_o[4]));
GF8Add Add5(
.add_i1(add_o[4]),
.add_i2(mult_o[6]),
.add_o(add_o[5]));
GF8Add Add6(
.add_i1(add_o[5]),
.add_i2(mult_o[7]),
.add_o(add_o[6]));
GF8Add Add7(
.add_i1(add_o[6]),
.add_i2(mult_o[8]),
.add_o(add_o[7]));
////////////////////
endmodule
/rs_encoder_decoder/rtl/CompleteChain_testbench.v
0,0 → 1,99
`timescale 1ns / 10 ps
 
module CompleteChain_testBench;
reg clk_i,rst_i;
reg valid_i;
reg gen_i;
wire [7:0] enc_data_i;
wire [7:0] enc_data_o;
wire [7:0] dec_data_o;
wire parity_o;
wire busy_o;
reg [126*7:0] path,output_file,output_fileDec,output_fileRND;
integer fd_in, fd_out,fd_out1,fd_out2;
 
GF8lfsr RNDMIZER(.clk_i(clk_i), .rst_i(rst_i),
.en_i(gen_i), // Valid Input Set it to High When giving the input
.lfsr_o(enc_data_i) // Gallios Field Generic Bit Serial Multiplier output
);
RS8Encoder8t ENC(.clk_i(clk_i), .rst_i(rst_i),
.encoder_i(enc_data_i), // Input to the encoder
.valid_i(valid_i), // set this when input is set
.encoder_o(enc_data_o), // output of the encoder
.parity_o(parity_o), // Valid signal is set when the output is available on the output line
.busy_o(enc_busy_o) // Busy Signal When busy signal is high during the encoding process Please dont
); // give input to the incoder
RS8FreqDecode DEC(.clk_i(clk_i), .rst_i(rst_i),
.valid_i(parity_o), // input valid signal
.enc_data_i(enc_data_o), // encoded data
.dec_data_o(dec_data_o), // decoded output
.valid_o(valid_o), // decoded output
.busy_o(dec_busy_o)
);
// This is an input counter the purpose of this is to set the input to zero in the start
// of the encoding process
reg [10:0] wait_cntr;
always @(posedge clk_i) begin
if(rst_i)
wait_cntr <= 0;
else
wait_cntr <= wait_cntr + 1;
end
always
#5 clk_i = !clk_i;
initial begin
path = "./";
// These are the input files that can be used in the encoder
// you can select any information bit generation
output_file = "output_file_RSVerilogEncodedData.dat";
output_fileDec = "output_file_RSVerilogDecodedData.dat";
output_fileRND = "output_file_RSVerilogRNDData.data";
fd_out = $fopen(output_file,"w");
fd_out1 = $fopen(output_fileDec,"w");
fd_out2 = $fopen(output_fileRND,"w");
 
clk_i = 0;
rst_i = 1;
#10 rst_i = 0;
 
while(1)
begin
@(posedge clk_i);
if(wait_cntr < 4) begin
valid_i = 0;
gen_i = 1;
end
else if((wait_cntr >=4)&&(wait_cntr<=243)) begin // give the input to the encoder when the encoder is not busy
valid_i = 1;
gen_i = 1;
end
else if ((wait_cntr>243)&&(wait_cntr <= 259)) begin
valid_i =1;
gen_i = 0;
end
else if (wait_cntr > 259) begin
valid_i =0;
gen_i = 0;
end
if(parity_o)
$fwrite(fd_out,"%d \n",enc_data_o); // Write the output of the encoded data
if(valid_o)
$fwrite(fd_out1,"%d \n",dec_data_o); // Write the output of the encoded data
if(gen_i)
$fwrite(fd_out2,"%d \n",enc_data_i); // RandomLy Generated Data
end
end // initial begin
 
endmodule

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