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/rtcclock/trunk/rtl/hexmap.v
0,0 → 1,82
///////////////////////////////////////////////////////////////////////////
//
// Filename: hexmap.v
//
// Project: A Real--time Clock Core
//
// Purpose: Converts a 4'bit hexadecimal value to the seven bits needed
// by a seven segment display, specifying which bits are on and
// which are off.
//
// The display I am working with, however, requires a separate
// controller. This file only provides part of the input for that
// controller. That controller deals with turning on each part
// of the display in a rotating fashion, since the hardware I have
// cannot display more than one character at a time. So,
// buyer beware--this is not a complete seven segment display
// solution.
//
//
// The outputs of this routine are numbered as follows:
// o_map[7] turns on the bar at the top of the display
// o_map[6] turns on the top of the '1'
// o_map[5] turns on the bottom of a '1'
// o_map[4] turns on the bar at the bottom of the display
// o_map[3] turns on the vertical bar at the bottom left
// o_map[2] turns on the vertical bar at the top left, and
// o_map[1] turns on the bar in the middle of the display.
// The dash if you will.
// Bit zero, from elsewhere, would be the decimal point.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
module hexmap(i_clk, i_hex, o_map);
input i_clk;
input [3:0] i_hex;
output reg [7:1] o_map;
 
always @(posedge i_clk)
case(i_hex)
4'h0: o_map <= { 7'b1111110 };
4'h1: o_map <= { 7'b0110000 };
4'h2: o_map <= { 7'b1101101 };
4'h3: o_map <= { 7'b1111001 };
4'h4: o_map <= { 7'b0110011 };
4'h5: o_map <= { 7'b1011011 };
4'h6: o_map <= { 7'b1011111 };
4'h7: o_map <= { 7'b1110000 };
4'h8: o_map <= { 7'b1111111 };
4'h9: o_map <= { 7'b1111011 };
4'ha: o_map <= { 7'b1110111 };
4'hb: o_map <= { 7'b0011111 }; // b
4'hc: o_map <= { 7'b1001110 };
4'hd: o_map <= { 7'b0111101 }; // d
4'he: o_map <= { 7'b1001111 };
4'hf: o_map <= { 7'b1000111 };
endcase
endmodule
/rtcclock/trunk/rtl/rtcclock.v
0,0 → 1,468
///////////////////////////////////////////////////////////////////////////
//
// Filename: rtcclock.v
//
// Project: A Wishbone Controlled Real--time Clock Core
//
// Purpose: Implement a real time clock, including alarm, count--down
// timer, stopwatch, variable time frequency, and more.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
module rtcclock(i_clk,
// Wishbone interface
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
// o_wb_ack, o_wb_stb, o_wb_data, // no reads here
// // Button inputs
// i_btn,
// Output registers
o_data, // multiplexed based upon i_wb_addr
// Output controls
o_sseg, o_led, o_interrupt,
// Time setting hack(s)
i_hack);
input i_clk;
input i_wb_cyc, i_wb_stb, i_wb_we;
input [2:0] i_wb_addr;
input [31:0] i_wb_data;
// input i_btn;
output reg [31:0] o_data;
output reg [31:0] o_sseg;
output wire [15:0] o_led;
output wire o_interrupt;
input i_hack;
 
reg [31:0] clock, stopwatch, ckspeed;
reg [17:0] timer;
wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
 
reg [39:0] ck_counter;
reg ck_carry;
always @(posedge i_clk)
{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
 
wire ck_pps;
reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
reg [7:0] ck_sub;
initial clock = 32'h00000000;
assign ck_pps = (ck_carry)&&(ck_prepps);
always @(posedge i_clk)
begin
if (ck_carry)
ck_sub <= ck_sub + 1;
ck_prepps <= (ck_sub == 8'hff);
 
if (ck_pps)
begin // advance the seconds
if (clock[3:0] >= 4'h9)
clock[3:0] <= 4'h0;
else
clock[3:0] <= clock[3:0] + 4'h1;
if (clock[7:0] >= 8'h59)
clock[7:4] <= 4'h0;
else if (clock[3:0] >= 4'h9)
clock[7:4] <= clock[7:4] + 4'h1;
end
ck_ppm <= (clock[7:0] == 8'h59);
 
if ((ck_pps)&&(ck_ppm))
begin // advance the minutes
if (clock[11:8] >= 4'h9)
clock[11:8] <= 4'h0;
else
clock[11:8] <= clock[11:8] + 4'h1;
if (clock[15:8] >= 8'h59)
clock[15:12] <= 4'h0;
else if (clock[11:8] >= 4'h9)
clock[15:12] <= clock[15:12] + 4'h1;
end
ck_pph <= (clock[15:0] == 16'h5959);
 
if ((ck_pps)&&(ck_pph))
begin // advance the hours
if (clock[21:16] >= 6'h23)
begin
clock[19:16] <= 4'h0;
clock[21:20] <= 2'h0;
end else if (clock[19:16] >= 4'h9)
begin
clock[19:16] <= 4'h0;
clock[21:20] <= clock[21:20] + 2'h1;
end else begin
clock[19:16] <= clock[19:16] + 4'h1;
end
end
// ppd <= (clock{15:8] == 8'h59);
 
if ((ck_sel)&&(i_wb_we))
begin
if (8'hff != i_wb_data[7:0])
begin
clock[7:0] <= i_wb_data[7:0];
ck_ppm <= (i_wb_data[7:0] == 8'h59);
end
if (8'hff != i_wb_data[15:8])
begin
clock[15:8] <= i_wb_data[15:8];
ck_pph <= (i_wb_data[15:8] == 8'h59);
end
if (6'h3f != i_wb_data[21:16])
clock[21:16] <= i_wb_data[21:16];
clock[31:22] <= i_wb_data[31:22];
if (8'h00 == i_wb_data[7:0])
ck_sub <= 8'h00;
end
end
 
// Clock updates take several clocks, so let's make sure we
// are only looking at a valid clock value before testing it.
reg [21:0] ck_last_clock;
always @(posedge i_clk)
ck_last_clock <= clock[21:0];
 
reg tm_pps, tm_ppm, tm_int;
wire tm_stopped, tm_running, tm_alarm;
assign tm_stopped = ~timer[24];
assign tm_running = timer[24];
assign tm_alarm = timer[25];
reg [23:0] tm_start;
reg [7:0] tm_sub;
initial tm_start = 16'h00;
initial timer = 18'h00;
initial tm_int = 1'b0;
initial tm_pps = 1'b0;
always @(posedge i_clk)
begin
if (ck_carry)
begin
tm_sub <= tm_sub + 1;
tm_pps <= (tm_sub == 8'hff);
end else
tm_pps <= 1'b0;
if ((~tm_alarm)&&(tm_running)&&(tm_pps))
begin // If we are running ...
timer[25] <= 1'b0;
if (timer[23:0] == 24'h00)
timer[25] <= 1'b1;
else if (timer[3:0] != 4'h0)
timer[3:0] <= timer[3:0]-4'h1;
else begin // last digit is a zero
timer[3:0] <= 4'h9;
if (timer[7:4] != 4'h0)
timer[7:4] <= timer[7:4]-4'h1;
else begin // last two digits are zero
timer[7:4] <= 4'h5;
if (timer[11:8] != 4'h0)
timer[11:8] <= timer[11:8]-4'h1;
else begin // last three digits are zero
timer[11:8] <= 4'h9;
if (timer[15:12] != 4'h0)
timer[15:12] <= timer[15:12]-4'h1;
else begin
timer[15:12] <= 4'h5;
if (timer[19:16] != 4'h0)
timer[19:16] <= timer[19:16]-4'h1;
else begin
//
timer[19:16] <= 4'h9;
timer[23:20] <= timer[23:20]-4'h1;
end
end
end
end
end
end
 
if((~tm_alarm)&&(tm_running))
begin
timer[25] <= (timer[23:0] == 24'h00);
tm_int <= (timer[23:0] == 24'h00);
end else tm_int <= 1'b0;
if (tm_alarm)
timer[24] <= 1'b0;
 
if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
// Only allowed to stop the timer, nothing more
timer[24] <= i_wb_data[24];
else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
begin
timer[24] <= i_wb_data[24];
if ((timer[24])||(i_wb_data[24]))
timer[25] <= 1'b0;
if (i_wb_data[23:0] != 24'h0000)
begin
timer[23:0] <= i_wb_data[23:0];
tm_start <= i_wb_data[23:0];
tm_sub <= 8'h00;
end else if (timer[23:0] == 24'h00)
begin // Resetting timer to last valid timer start val
timer[23:0] <= tm_start;
tm_sub <= 8'h00;
end
// Any write clears the alarm
timer[25] <= 1'b0;
end
end
 
//
// Stopwatch functionality
//
// Setting bit '0' starts the stop watch, clearing it stops it.
// Writing to the register with bit '1' high will clear the stopwatch,
// and return it to zero provided that the stopwatch is stopped either
// before or after the write. Hence, writing a '2' to the device
// will always stop and clear it, whereas writing a '3' to the device
// will only clear it if it was already stopped.
reg sw_pps, sw_ppm, sw_pph;
reg [7:0] sw_sub;
wire sw_running;
assign sw_running = stopwatch[0];
initial stopwatch = 32'h00001;
always @(posedge i_clk)
begin
sw_pps <= 1'b0;
if (sw_running)
begin
if (ck_carry)
begin
sw_sub <= sw_sub + 1;
sw_pps <= (sw_sub == 8'hff);
end
end
 
stopwatch[7:1] <= sw_sub[7:1];
 
if (sw_pps)
begin // Second hand
if (stopwatch[11:8] >= 4'h9)
stopwatch[11:8] <= 4'h0;
else
stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
 
if (stopwatch[15:8] >= 8'h59)
stopwatch[15:12] <= 4'h0;
else if (stopwatch[11:8] >= 4'h9)
stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
sw_ppm <= (stopwatch[15:8] == 8'h59);
end else sw_ppm <= 1'b0;
 
if (sw_ppm)
begin // Minutes
if (stopwatch[19:16] >= 4'h9)
stopwatch[19:16] <= 4'h0;
else
stopwatch[19:16] <= stopwatch[19:16]+4'h1;
 
if (stopwatch[23:16] >= 8'h59)
stopwatch[23:20] <= 4'h0;
else if (stopwatch[19:16] >= 4'h9)
stopwatch[23:20] <= stopwatch[23:20]+4'h1;
sw_pph <= (stopwatch[23:16] == 8'h59);
end else sw_pph <= 1'b0;
 
if (sw_pph)
begin // And hours
if (stopwatch[27:24] >= 4'h9)
stopwatch[27:24] <= 4'h0;
else
stopwatch[27:24] <= stopwatch[27:24]+4'h1;
 
if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
stopwatch[31:28] <= stopwatch[27:24]+4'h1;
end
 
if ((sw_sel)&&(i_wb_we))
begin
stopwatch[0] <= i_wb_data[0];
if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
begin
stopwatch[31:1] <= 31'h00;
sw_sub <= 8'h00;
sw_pps <= 1'b0;
sw_ppm <= 1'b0;
sw_pph <= 1'b0;
end
end
end
 
//
// The alarm code
//
// Set the alarm register to the time you wish the board to "alarm".
// The "alarm" will take place once per day at that time. At that
// time, the RTC code will generate a clock interrupt, and the CPU/host
// can come and see that the alarm tripped.
//
//
reg [21:0] alarm_time;
reg al_int, // The alarm interrupt line
al_enabled, // Whether the alarm is enabled
al_tripped; // Whether the alarm has tripped
initial al_enabled= 1'b0;
initial al_tripped= 1'b0;
always @(posedge i_clk)
begin
if ((al_sel)&&(i_wb_we))
begin
// Only adjust the alarm hours if the requested hours
// are valid. This allows writes to the register,
// without a prior read, to leave these configuration
// bits alone.
if (i_wb_data[21:16] != 6'h3f)
alarm_time[21:16] <= i_wb_data[21:16];
// Here's the same thing for the minutes: only adjust
// the alarm minutes if the new bits are not all 1's.
if (i_wb_data[15:8] != 8'hff)
alarm_time[15:8] <= i_wb_data[15:8];
// Here's the same thing for the seconds: only adjust
// the alarm minutes if the new bits are not all 1's.
if (i_wb_data[7:0] != 8'hff)
alarm_time[7:0] <= i_wb_data[7:0];
al_enabled <= i_wb_data[24];
// Reset the alarm if a '1' is written to the tripped
// register, or if the alarm is disabled.
if ((i_wb_data[25])||(~i_wb_data[24]))
al_tripped <= 1'b0;
end
 
al_int <= 1'b0;
if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)
&&(al_enabled))
begin
al_tripped <= 1'b1;
al_int <= 1'b1;
end
end
 
//
// The ckspeed register is equal to 2^48 divded by the number of
// clock ticks you expect per second. Adjust high for a slower
// clock, lower for a faster clock. In this fashion, a single
// real time clock RTL file can handle tracking the clock in any
// device. Further, because this is only the lower 32 bits of a
// 48 bit counter per seconds, the clock jitter is kept below
// 1 part in 65 thousand.
//
initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz
// In the case of verilator, comment the above and uncomment the line
// below. The clock constant below is "close" to simulation time,
// meaning that my verilator simulation is running about 300x slower
// than board time.
// initial ckspeed = 32'd786432000;
always @(posedge i_clk)
if ((sp_sel)&&(i_wb_we))
ckspeed <= i_wb_data;
 
//
// If you want very fine precision control over your clock, you need
// to be able to transfer time from one location to another. This
// is the beginning of that means: by setting a wire, i_hack, high
// on a particular input, you can then read (later) what the clock
// time was on that input.
//
// What's missing from this high precision adjustment mechanism is a
// means of actually adjusting this time based upon the time
// difference you measure here between the hack time and some time
// on another clock, but we'll get there.
//
reg r_hack_carry;
reg [29:0] hack_time;
reg [39:0] hack_counter;
always @(posedge i_clk)
if (i_hack)
begin
hack_time <= { clock[21:0], ck_sub };
hack_counter <= ck_counter;
r_hack_carry <= ck_carry;
// if ck_carry is set, the clock register is in the
// middle of a two clock update. In that case ....
end else if (r_hack_carry)
begin // update again on the next clock to get the correct
// hack time.
hack_time <= { clock[21:0], ck_sub };
r_hack_carry <= 1'b0;
end
 
reg [15:0] h_sseg;
always @(posedge i_clk)
case(clock[27:24])
4'h0: h_sseg <= { 2'b00, ck_last_clock[21:8] };
4'h1: h_sseg <= timer[15:0];
4'h2: h_sseg <= stopwatch[19:4];
4'h3: h_sseg <= ck_last_clock[15:0];
default: h_sseg <= { 2'b00, ck_last_clock[21:8] };
endcase
 
wire [31:0] w_sseg;
assign w_sseg[ 0] = (~ck_sub[7]);
assign w_sseg[ 8] = 1'b0;
assign w_sseg[16] = 1'b0;
assign w_sseg[24] = 1'b0;
hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
 
always @(posedge i_clk)
if ((tm_alarm || al_tripped)&&(ck_sub[7]))
o_sseg <= 32'h0000;
else
o_sseg <= w_sseg;
 
reg [17:0] ledreg;
always @(posedge i_clk)
if ((ck_pps)&&(ck_ppm))
ledreg <= 18'h00;
else if (ck_carry)
ledreg <= ledreg + 18'h11;
assign o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:ledreg[17:2];
 
assign o_interrupt = tm_int || al_int;
 
always @(posedge i_clk)
case(i_wb_addr[2:0])
3'b000: o_data <= { clock[31:22], ck_last_clock };
3'b001: o_data <= { 14'h00, timer };
3'b010: o_data <= stopwatch;
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
3'b100: o_data <= ckspeed;
3'b101: o_data <= { 2'b00, hack_time };
3'b110: o_data <= hack_counter[39:8];
3'b111: o_data <= { hack_counter[7:0], 24'h00 };
endcase
 
endmodule
/rtcclock/trunk/doc/spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/rtcclock/trunk/doc/spec.pdf
rtcclock/trunk/doc/spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rtcclock/trunk/doc/src/gpl-3.0.tex =================================================================== --- rtcclock/trunk/doc/src/gpl-3.0.tex (nonexistent) +++ rtcclock/trunk/doc/src/gpl-3.0.tex (revision 2) @@ -0,0 +1,719 @@ +\documentclass[11pt]{article} + +\title{GNU GENERAL PUBLIC LICENSE} +\date{Version 3, 29 June 2007} + +\begin{document} +\maketitle + +\begin{center} +{\parindent 0in + +Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/} + +\bigskip +Everyone is permitted to copy and distribute verbatim copies of this + +license document, but changing it is not allowed.} + +\end{center} + +\renewcommand{\abstractname}{Preamble} +\begin{abstract} +The GNU General Public License is a free, copyleft license for +software and other kinds of works. + +The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + +When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + +To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. 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EXCEPT WHEN OTHERWISE STATED IN WRITING THE + COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS'' + WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 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It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the ``copyright'' line and a pointer to where the full notice is found. + +{\footnotesize +\begin{verbatim} + + +Copyright (C) + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +\end{verbatim} +} + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + +{\footnotesize +\begin{verbatim} + Copyright (C) + +This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. +This is free software, and you are welcome to redistribute it +under certain conditions; type `show c' for details. +\end{verbatim} +} + +The hypothetical commands {\tt show w} and {\tt show c} should show +the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an ``about box''. + +You should also get your employer (if you work as a programmer) or +school, if any, to sign a ``copyright disclaimer'' for the program, if +necessary. For more information on this, and how to apply and follow +the GNU GPL, see \texttt{http://www.gnu.org/licenses/}. + +The GNU General Public License does not permit incorporating your +program into proprietary programs. If your program is a subroutine +library, you may consider it more useful to permit linking proprietary +applications with the library. If this is what you want to do, use +the GNU Lesser General Public License instead of this License. But +first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}. + +\end{enumerate} + +\end{document} Index: rtcclock/trunk/doc/src/GT.eps =================================================================== --- rtcclock/trunk/doc/src/GT.eps (nonexistent) +++ rtcclock/trunk/doc/src/GT.eps (revision 2) @@ -0,0 +1,94 @@ +%!PS-Adobe-3.0 EPSF-3.0 +%%BoundingBox: 0 0 504 288 +%%Creator: Gisselquist Technology LLC +%%Title: Gisselquist Technology Logo +%%CreationDate: 11 Mar 2014 +%%EndComments +%%BeginProlog +/black { 0 setgray } def +/white { 1 setgray } def +/height { 288 } def +/lw { height 8 div } def +%%EndProlog +% %%Page: 1 + +false { % A bounding box + 0 setlinewidth + newpath + 0 0 moveto + 0 height lineto + 1.625 height mul lw add 0 rlineto + 0 height neg rlineto + closepath stroke +} if + +true { % The "G" + newpath + height 2 div 1.25 mul height moveto + height 2 div height 4 div sub height lineto + 0 height 3 4 div mul lineto + 0 height 4 div lineto + height 4 div 0 lineto + height 3 4 div mul 0 lineto + height height 4 div lineto + height height 2 div lineto + % + height lw sub height 2 div lineto + height lw sub height 4 div lw 2 div add lineto + height 3 4 div mul lw 2 div sub lw lineto + height 4 div lw 2 div add lw lineto + lw height 4 div lw 2 div add lineto + lw height 3 4 div mul lw 2 div sub lineto + height 4 div lw 2 div add height lw sub lineto + height 2 div 1.25 mul height lw sub lineto + closepath fill + newpath + height 2 div height 2 div moveto + height 2 div 0 rlineto + 0 height 2 div neg rlineto + lw neg 0 rlineto + 0 height 2 div lw sub rlineto + height 2 div height 2 div lw sub lineto + closepath fill +} if + +height 2 div 1.25 mul lw add 0 translate +false { + newpath + 0 height moveto + height 0 rlineto + 0 lw neg rlineto + height lw sub 2 div neg 0 rlineto + 0 height lw sub neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + 0 lw rlineto + closepath fill +} if + +true { % The "T" of "GT". + newpath + 0 height moveto + height lw add 2 div 0 rlineto + 0 height neg rlineto + lw neg 0 rlineto + 0 height lw sub rlineto + height lw sub 2 div neg 0 rlineto + closepath fill + + % The right half of the top of the "T" + newpath + % (height + lw)/2 + lw + height lw add 2 div lw add height moveto + % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw + height 3 lw mul sub 2 div 0 rlineto + 0 lw neg rlineto + height 3 lw mul sub 2 div neg 0 rlineto + closepath fill +} if + + +grestore +showpage +%%EOF Index: rtcclock/trunk/doc/src/gqtekspec.cls =================================================================== --- rtcclock/trunk/doc/src/gqtekspec.cls (nonexistent) +++ rtcclock/trunk/doc/src/gqtekspec.cls (revision 2) @@ -0,0 +1,296 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/ +% +% Copyright (C) 2015, Gisselquist Technology, LLC +% +% This template is free software: you can redistribute it and/or modify it +% under the terms of the GNU General Public License as published by the +% Free Software Foundation, either version 3 of the License, or (at your +% option) any later version. +% +% This template is distributed in the hope that it will be useful, but WITHOUT +% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +% for more details. +% +% You should have received a copy of the GNU General Public License along +% with this program. If not, see for a copy. +% +% License: GPL, v3, as defined and found on www.gnu.org, +% http://www.gnu.org/licenses/gpl.html +% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% \NeedsTeXFormat{LaTeX2e}[1995/12/01] +\ProvidesClass{gqtekspec}[2015/03/03 v0.1 -- Gisselquist Technology Specification] +\typeout{by Dan Gisselquist} +\LoadClassWithOptions{report} +\usepackage{datetime} +\usepackage{graphicx} +\usepackage[dvips]{pstricks} +\usepackage{hhline} +\usepackage{colortbl} +\newdateformat{headerdate}{\THEYEAR/\twodigit{\THEMONTH}/\twodigit{\THEDAY}} +\setlength{\hoffset}{0.25in} +\setlength{\voffset}{-0.5in} +\setlength{\marginparwidth}{0in} +\setlength{\marginparsep}{0in} +\setlength{\textwidth}{6in} +\setlength{\oddsidemargin}{0in} + +% ************************************** +% * APPENDIX * +% ************************************** +% +\newcommand\appfl@g{\appendixname} %used to test \@chapapp +% +% \renewcommand\appendix{\par\clearpage + % \setcounter{chapter}{0}% + % \setcounter{section}{0}% + % \renewcommand\@chapapp{\appendixname}% + % \renewcommand\thechapter{\Alph{chapter}} + % \if@nosectnum\else + % \renewcommand\thesection{\Alph{chapter}.\arabic{section}} + % \fi +% } + + +% FIGURE +% redefine the @caption command to put a period after the figure or +% table number in the lof and lot tables +\long\def\@caption#1[#2]#3{\par\addcontentsline{\csname + ext@#1\endcsname}{#1}{\protect\numberline{\csname + the#1\endcsname.}{\ignorespaces #2}}\begingroup + \@parboxrestore + \normalsize + \@makecaption{\csname fnum@#1\endcsname}{\ignorespaces #3}\par + \endgroup} + +% **************************************** +% * TABLE OF CONTENTS, ETC. * +% **************************************** + +\renewcommand\contentsname{Contents} +\renewcommand\listfigurename{Figures} +\renewcommand\listtablename{Tables} + +\newif\if@toc \@tocfalse +\renewcommand\tableofcontents{% + \begingroup% temporarily set if@toc so that \@schapter will not + % put Table of Contents in the table of contents. + \@toctrue + \chapter*{\contentsname} + \endgroup + \thispagestyle{gqtekspecplain} + + \baselineskip=10pt plus .5pt minus .5pt + + {\raggedleft Page \par\vskip-\parskip} + \@starttoc{toc}% + \baselineskip=\normalbaselineskip + } + +\def\l@appendix{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{8em}} + +\def\l@chapter{\pagebreak[3] + \vskip 1.0em plus 1pt % space above appendix line + \@dottedtocline{0}{0em}{4em}} + +% \if@nosectnum\else + % \renewcommand\l@section{\@dottedtocline{1}{5.5em}{2.4em}} + % \renewcommand\l@subsection{\@dottedtocline{2}{8.5em}{3.2em}} + % \renewcommand\l@subsubsection{\@dottedtocline{3}{11em}{4.1em}} + % \renewcommand\l@paragraph{\@dottedtocline{4}{13.5em}{5em}} + % \renewcommand\l@subparagraph{\@dottedtocline{5}{16em}{6em}} +% \fi + +% LIST OF FIGURES +% +\def\listoffigures{% + \begingroup + \chapter*{\listfigurename}% + \endgroup + \thispagestyle{gqtekspecplain}% + + \baselineskip=10pt plus .5pt minus .5pt% + + {\hbox to \hsize{Figure\hfil Page} \par\vskip-\parskip}% + + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lof}% + \baselineskip=\normalbaselineskip}% + +\def\l@figure{\@dottedtocline{1}{1em}{4.0em}} + +% LIST OF TABLES +% +\def\listoftables{% + \begingroup + \chapter*{\listtablename}% + \endgroup + \thispagestyle{gqtekspecplain}% + \baselineskip=10pt plus .5pt minus .5pt% + {\hbox to \hsize{Table\hfil Page} \par\vskip-\parskip}% + + % Added line underneath headings, 20 Jun 01, Capt Todd Hale. + \rule[2mm]{\textwidth}{0.5mm}\par + + \@starttoc{lot}% + \baselineskip=\normalbaselineskip}% + +\let\l@table\l@figure + +% **************************************** +% * PAGE STYLES * +% **************************************** +% +\def\ps@gqtekspectoc{% + \let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspectocn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm \hfil\raisebox{10pt}{Page}} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclof{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclofn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Figure}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspeclot{\let\@mkboth\@gobbletwo + \def \@oddhead{} + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} +\def\ps@gqtekspeclotn{\let\@mkboth\@gobbletwo + \def \@oddhead{\rm + \parbox{\textwidth}{\raisebox{0pt}{Table}\hfil\raisebox{0pt}{Page} % + \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }} + + \def \@oddfoot{\rm + \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +\def\ps@gqtekspecplain{\let\@mkboth\@gobbletwo + \def \@oddhead{\rput(0,-2pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{\includegraphics[height=0.8\headheight]{GT.eps} Gisselquist Technology, LLC}\hfil\hbox{\@title}\hfil\hbox to 1in{\hfil\headerdate\@date}} + \def \@oddfoot{\rput(0,9pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{www.opencores.com\hfil}\hfil\hbox{\r@vision}\hfil\hbox to 1in{\hfil{\thepage}}} + \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot} + +% \def\author#1{\def\auth@r{#1}} +% \def\title#1{\def\ti@tle{#1}} + +\def\logo{\begin{pspicture}(0,0)(5.67in,0.75in) + \rput[lb](0.05in,0.10in){\includegraphics[height=0.75in]{GT.eps}} + \rput[lb](1.15in,0.05in){\scalebox{1.8}{\parbox{2.0in}{Gisselquist\\Technology, LLC}}} + \end{pspicture}} +% TITLEPAGE +% +\def\titlepage{\setcounter{page}{1} + \typeout{^^JTitle Page.} + \thispagestyle{empty} + \leftline{\rput(0,0){\psline(0,0)(\textwidth,0)}\hfill} + \vskip 2\baselineskip + \logo\hfil % Original is 3.91 in x 1.26 in, let's match V thus + \vskip 2\baselineskip + \vspace*{10pt}\vfil + \begin{minipage}{\textwidth}\raggedleft + \ifproject{\Huge\bfseries\MakeUppercase\@project} \\\fi + \vspace*{15pt} + {\Huge\bfseries\MakeUppercase\@title} \\ + \vskip 10\baselineskip + \Large \@author \\ + \ifemail{\Large \@email}\\\fi + \vskip 6\baselineskip + \Large \usdate\@date \\ + \end{minipage} + % \baselineskip 22.5pt\large\rm\MakeUppercase\ti@tle + \vspace*{30pt} + \vfil + \newpage\baselineskip=\normalbaselineskip} + +\newenvironment{license}{\clearpage\typeout{^^JLicense Page.}\ \vfill\noindent}% + {\vfill\newpage} +% **************************************** +% * CHAPTER DEFINITIONS * +% **************************************** +% +\renewcommand\chapter{\if@openright\cleardoublepage\else\clearpage\fi + \thispagestyle{gqtekspecplain}% + \global\@topnum\z@ + \@afterindentfalse + \secdef\@chapter\@schapter} +\renewcommand\@makechapterhead[1]{% + \hbox to \textwidth{\hfil\scalebox{1.8}{\Huge\bfseries \thechapter.}}\vskip 10\p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@ + \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@ + \hbox to \textwidth{\hfill\scalebox{1.8}{\huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +\renewcommand\@makeschapterhead[1]{% + \hbox to \textwidth{\hfill\scalebox{1.8}{\huge\bfseries #1}}% + \par\nobreak\vskip 40\p@} +% **************************************** +% * INITIALIZATION * +% **************************************** +% +% Default initializations + +\ps@gqtekspecplain % 'gqtekspecplain' page style with lowered page nos. +\onecolumn % Single-column. +\pagenumbering{roman} % the first chapter will change pagenumbering + % to arabic +\setcounter{page}{1} % in case a titlepage is not requested + % otherwise titlepage sets page to 1 since the + % flyleaf is not counted as a page +\widowpenalty 10000 % completely discourage widow lines +\clubpenalty 10000 % completely discourage club (orphan) lines +\raggedbottom % don't force alignment of bottom of pages + +\date{\today} +\newif\ifproject\projectfalse +\def\project#1{\projecttrue\gdef\@project{#1}} +\def\@project{} +\newif\ifemail\emailfalse +\def\email#1{\emailtrue\gdef\@email{#1}} +\def\@email{} +\def\revision#1{\gdef\r@vision{#1}} +\def\r@vision{} +\def\at{\makeatletter @\makeatother} +\newdateformat{theyear}{\THEYEAR} +\newenvironment{revisionhistory}{\clearpage\typeout{^^JRevision History.}% + \hbox to \textwidth{\hfil\scalebox{1.8}{\large\bfseries Revision History}}\vskip 10\p@\noindent% + \begin{tabular}{|p{0.5in}|p{1in}|p{1in}|p{2.875in}|}\hline + \rowcolor[gray]{0.8} Rev. & Date & Author & Description\\\hline\hline} + {\end{tabular}\clearpage} +\newenvironment{clocklist}{\begin{tabular}{|p{0.75in}|p{0.5in}|l|l|p{2.875in}|}\hline + \rowcolor[gray]{0.85} Name & Source & \multicolumn{2}{l|}{Rates (MHz)} & Description \\\hhline{~|~|-|-|~}% + \rowcolor[gray]{0.85} & & Max & Min & \\\hline\hline}% + {\end{tabular}} +\newenvironment{reglist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.5in}|p{0.5in}|p{2.875in}|}\hline + \rowcolor[gray]{0.85} Name & Address & Width & Access & Description \\\hline\hline}% + {\end{tabular}} +\newenvironment{bitlist}{\begin{tabular}{|p{0.5in}|p{0.5in}|p{3.875in}|}\hline + \rowcolor[gray]{0.85} Bit \# & Access & Description \\\hline\hline}% + {\end{tabular}} +\newenvironment{portlist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.75in}|p{3.375in}|}\hline + \rowcolor[gray]{0.85} Port & Width & Direction & Description \\\hline\hline}% + {\end{tabular}} +\newenvironment{wishboneds}{\begin{tabular}{|p{2.5in}|p{2.5in}|}\hline + \rowcolor[gray]{0.85} Description & Specification \\\hline\hline}% + {\end{tabular}} +\newenvironment{preface}{\chapter*{Preface}}{\par\bigskip\bigskip\leftline{\hfill\@author}} +\endinput Index: rtcclock/trunk/doc/src/spec.tex =================================================================== --- rtcclock/trunk/doc/src/spec.tex (nonexistent) +++ rtcclock/trunk/doc/src/spec.tex (revision 2) @@ -0,0 +1,562 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Filename: spec.tex +%% +%% Project: A Wishbone Controlled Real-Time clock Core +%% +%% Purpose: This LaTeX file contains all of the documentation/description +%% currently provided with this FPGA Real-time Clock Core. +%% It's not nearly as interesting as the PDF file it creates, +%% so I'd recommend reading that before diving into this file. +%% You should be able to find the PDF file in the SVN distribution +%% together with this PDF file and a copy of the GPL-3.0 license +%% this file is distributed under. If not, just type 'make' +%% in the doc directory and it (should) build without a problem. +%% +%% +%% Creator: Dan Gisselquist +%% Gisselquist Technology, LLC +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% +%% Copyright (C) 2015, Gisselquist Technology, LLC +%% +%% This program is free software (firmware): you can redistribute it and/or +%% modify it under the terms of the GNU General Public License as published +%% by the Free Software Foundation, either version 3 of the License, or (at +%% your option) any later version. +%% +%% This program is distributed in the hope that it will be useful, but WITHOUT +%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +%% for more details. +%% +%% You should have received a copy of the GNU General Public License along +%% with this program. (It's in the $(ROOT)/doc directory, run make with no +%% target there if the PDF file isn't present.) If not, see +%% for a copy. +%% +%% License: GPL, v3, as defined and found on www.gnu.org, +%% http://www.gnu.org/licenses/gpl.html +%% +%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\documentclass{gqtekspec} +\project{Real-Time Clock} +\title{Specification} +\author{Dan Gisselquist, Ph.D.} +\email{dgisselq\at opencores.org} +\revision{Rev.~0.1} +\begin{document} +\pagestyle{gqtekspecplain} +\titlepage +\begin{license} +Copyright (C) \theyear\today, Gisselquist Technology, LLC + +This project is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. If not, see \hbox{} for a +copy. +\end{license} +\begin{revisionhistory} +0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline +\end{revisionhistory} +% Revision History +% Table of Contents, named Contents +\tableofcontents +% \listoffigures +\listoftables +\begin{preface} +Every FPGA project needs to start with a very simple core. Then, working +from simplicity, more and more complex cores can be built until an eventual +application comes from all the tiny details. + +This real time clock is one such simple core. All of the pieces to this +clock are simple. Nothing is inherently complex. However, placing this +clock into a larger FPGA structure requires a Wishbone bus, and being able +to command and control an FPGA over a wishbone bus is an achievement in +itself. Further, the clock produces seven segment display output values +and LED output values. These are also simple outputs, but still take a lot +of work to complete. Finally, this clock will strobe an interrupt line. +Reading and processing that interrupt line requires a whole 'nuther bit of +logic and the ability to capture, recognize, and respond to interrupts. +Hence, once you get a simple clock working, you have a lot working. +\end{preface} + +\chapter{Introduction} +\pagenumbering{arabic} +\setcounter{page}{1} + +This Real--Time Clock implements a twenty four hour clock, count-down timer, +stopwatch +and alarm. It is designed to be configurable to adjust to whatever clock +speed the underlying architecture is running on, so with only minor changes +should run on any fundamental clock rate from about 66~kHz on up to +250~TeraHertz with varying levels of accuracy along the way. + +This clock offers a fairly full feature set of capability: time, alarms, +a countdown timer and a stopwatch, all features which are available from the +wishbone bus. + +Other interfaces exist as well. + +Should you wish to investigate your clock's +stability or try to guarantee it's fine precision accuracy, it is possible to +provide a time hack pulse to the clock and subsequently read what all of the +internal registers were set to at that time. + +When either the count--down timer reaches zero or the clock reaches the alarm +time (if set), the clock module will produce an impulse which can be used +as an interrupt trigger. + +This clock will also provide outputs sufficient to drive an external seven +segment display driver and 16 LED's. + +Future enhancements may allow for button control and fine precision clock +adjustment. + +The layout of this specification follows the format set by OpenCores. +This introduction is the first chapter. Following this introduction is +a short chapter describing how this clock is implemented, +Chapt.~\ref{chap:arch}. Following this description, the Chapt.~\ref{chap:ops} +gives a brief overview of how to operate the clock. Most of the details, +however, are in the registers and their definitions. These you can find in +Chapt.~\ref{chap:regs}. As for the wishbone, the wishbone spec requires a +wishbone datasheet which you can find in Chapt.~\ref{chap:wishbone}. +That leaves the final pertinent information necessary for implementing this +core in Chapt.~\ref{chap:ioports}, the definitions and meanings of the +various I/O ports. + +As always, write me if you have any questions or problems. + +\chapter{Architecture}\label{chap:arch} + +Central to this real time clock architecture is a 48~bit sub--second register. +This register is incremented every clock by a user defined 32~bit value, +{\tt CKSPEED}. +When the register turns over at the end of each second, a second has taken +place and all of the various clock registers are adjusted. + +Well, not quite but almost. The 48~bit register is actually split into a +lower 40~bit register that is common to all clock components, as well as +separate eight bit upper registers for the clock, timer, and stopwatch. In +this fashion, these separate components can have different definitions for +when seconds begin and end, and with sufficient precision to satisfy most +applications. + +The next thing to note about this architecture is the format of the various +clock registers: Binary Coded Decimal, or BCD. Hence an {\tt 8'h59} refers +to a value of 59, rather than 89. In this fashion, setting the time to +{\tt 24'h231520} will set it to 23~hours, 15~minutes, and 20~seconds. The +only exception to this BCD format are the subseconds fields found in the +stopwatch and time hack registers. Seconds and above are all encoded as BCD. + +\chapter{Operation}\label{chap:ops} + +\section{Time} +To set the time, simply write to the clock register the current value of the +time. If the seconds hand is written as zero, subsecond time will be cleared +as well. The new clock value takes place one clock period after the value +is written to the bus. + +To set only some parts of the time and not others, such as the minutes but +not seconds or hours, write all '1's to the seconds and hours. In this way, +writing a {\tt 24'h3f17ff} will set the minutes to 17, but not affect the +rest of the clock. + +This is also the way to adjust the display without adjusting time. Suppose +you wish to switch to display option '1', just write a {\tt 32'h013fffff} to +the register and the display will switch without adjusting time. + +\section{Count-down Timer} +To use the count down timer, set it to the amount of time you wish to count +down for. When ready, or even in the same cycle, enable the count--down +timer by setting the RUN bit high. At this point in time, the count--down +timer is running. When it gets to zero, it will stop and trigger an interrupt. +You can tell if the alarm has been triggered by the TRIGGER bit being set. +Any write to the timer register will clear the alarm condition. + +While the timer is running, writing a '0' to the timer register will stop it +without clearing the time remaining. In this state, writing to the register +the RUN bit by itself will restart the timer, while anything else will set the +timer to a new value. Further, if the timer is stopped at zero, then writing +zero to the timer will reset the timer to the last start time it had. + +\section{Stopwatch} +The stop watch supports three operations: start, stop, and clear. Writing a +'1' to the stop watch register will start the stopwatch, while writing a '0' +will stop it. When it starts next, it will start where it left off unless the +register is cleared. To clear the register and set it back to zero, write a +'2' to the register. This will effectively stop the register and clear it in +one step. If the register is already stopped, writing a '3' will clear and +start it in one step. However, the register can only be cleared while stopped. +If the register is running, writing a '3' will have no effect. + +\section{Alarm} +To set the alarm, just write the alarm time to the alarm register together +with alarm enable bit. As with the time register, setting any field, +whether hours, minutes, or seconds, to {\tt 8'hff} has no effect on that +field. Hence, the alarm may be activated by writing {\tt 25'h13fffff} to +the register and deactivated by writing {\tt 25'h03fffff}. + +Once the alarm is tripped, the RTC core will generate an interrupt. Further, +the tripped bit in the alarm register will be set. To clear this bit and the +alarm tripped condition, either disable the alarm or write a '1' to this bit. + +\section{Time Hacks} + +For finer precision timing, the RTC module allows for setting a time +hack and reading the value from the device. On the clock following the +time hack being high, the internal state, to include the time and the 48~bit +counter, will be recorded and may then be read out. In this fashion, +it is possible to capture, with as much precision as the device offers, +the current time within the device. + +It is the users responsibility to read the time hack registers before a +subsequent time hack pulse sets them to new values. + +\chapter{Registers}\label{chap:regs} +This RTC clock module supports eight registers, as listed in +Tbl.~\ref{tbl:reglist}. Of these eight, the first four have been so placed +as to be the more routine or user used registers, while the latter four are +more lower level. +\begin{table}[htbp] +\begin{center} +\begin{reglist} +CLOCK & 0 & 32 & R/W & Wall clock time register\\\hline +TIMER & 1 & 32 & R/W & Count--down timer\\\hline +STPWTCH & 2 & 32 & R/W & Stopwatch control and value\\\hline +ALARM & 3 & 32 & R/W & Alarm time, and setting\\\hline\hline +CKSPEED & 4 & 32 & R/W & Clock speed control.\\\hline +HACKTIME &5 & 32 & R & Wall clock time at last hack.\\\hline +HACKCNTHI&6 & 32 & R & Wall clock time.\\\hline +HACKCNTLO&7 & 32 & R & Wall clock time.\\\hline +\end{reglist}\caption{List of Registers}\label{tbl:reglist} +\end{center}\end{table} +Each register will be discussed in detail in this chapter. + +\section{Clock Time Register} +The various bit fields associated with the current time may be found in +the {\tt CLOCK} register, shown in Tbl.~\ref{tbl:clockreg}. +\begin{table}[htbp]\begin{center} +\begin{bitlist} +28--31 & R & Always return zero.\\\hline +24--27 & R/W & Seven Segment Display Mode.\\\hline +22--23 & R & Always return zero.\\\hline +16--21 & R/W & Current time, BCD hours\\\hline +8--15 & R/W & Current time, BCD minutes\\\hline +0--7 & R/W & Current time, BCD seconds\\\hline +\end{bitlist} +\caption{Clock Time Register Bit Definitions}\label{tbl:clockreg} +\end{center}\end{table} +This register contains six clock digits: two each for hours, minutes, and +seconds. Each of these digits is encoded in Binary Coded Decimal (BCD). +Therefore, 23~hours would be encoded as 6'h23 and not 6'h17. Writes to each +of the various subcomponent registers will set that register, unless the +write value is a 8'hff. The behaviour of the clock when non--decimal +values are written, other than all F's, is undefined. + +Separate from the time, however, is the seven segment display mode. Four +values are currently supported: 4'h0 to display the hours and minutes, +4'h1 to display the timer in minutes and seconds, 4'h2 to display the +stopwatch in lower order minutes, seconds, and sixteenths of a second, and +4'h3 to display the minutes and seconds of the current time. In all cases, +the decimal point will appear to the right of the lowest order digit +and will blink with the second hand. That is, the decimal will be high for +the second half of any second, and low at the top of the second. + +\section{Countdown Timer Register} +The countdown timer register, whose bit--wise values are shown in +Tbl.~\ref{tbl:timer}, +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +26--31 & R & Unused, always read as '0'.\\\hline +25 & R/W & Alarm condition. Write a '1' to clear.\\\hline +24 & R/W & Running, stopped on '0'\\\hline +16--23 & R/W & BCD Hours\\\hline +8--15 & R/W & BCD Minutes\\\hline +0--7 & R/W & BCD Seconds\\\hline +\end{bitlist} +\caption{Count--down Timer register}\label{tbl:timer} +\end{center}\end{table} +controls the operation of the count--down timer. To use this timer, write +some amount of time to the register, then write zeros with bit 24 set. The +register will then reach an alarm condition after counting down that amount +of time. (Alternatively, you could set bit 24 while writing the register, +to set and start it in one operation.) To stop the register while it is +running, just write all zeros. To restart the register, provided more than a +second remains, write a {\tt 26'h1000000} to set it running again. Once +the timer alarms, the timer will stop and the alarm condition will be set. +Any write to the timer register after the alarm condition has been set will +clear the alarm condition. + +\section{Stopwatch Register} +The various bits of the stopwatch register are shown in +Tbl.~\ref{tbl:stopwatch}. +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +24--31 & R & Hours\\\hline +16--23 & R & Minutes\\\hline +8--15 & R & Sub Seconds\\\hline +1--7 & R & Sub Seconds\\\hline +1 & W & Clear\\\hline +0 & R/W & Running\\\hline +\end{bitlist} +\caption{Stopwatch Register}\label{tbl:stopwatch} +\end{center}\end{table} +Of note is the bottom bit that, when set, means the stop watch is running. +Set this bit to '1' to start the stopwatch, or to '0' to stop the stopwatch. +Further, while the stopwatch is stopped, a '1' can be written to the clear +bit. This will zero out the stopwatch and set it back to zero. + +\section{Alarm Register} +The various bits of the alarm register are shown in Tbl.~\ref{tbl:alarm}. +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +26--31 & R & Always reads zeros. \\\hline +25 & R/W & Alarm tripped. Write a '1' to this register to clear any alarm + condition. (A tripped alarm will not trip again.)\\\hline +24 & R/W & Alarm enabled\\\hline +16--23 & R & Alarm time, BCD hours\\\hline +8--15 & R & Alarm time, BCD minutes\\\hline +0--7 & R/W & Alarm time, BCD Seconds\\\hline +\end{bitlist} +\caption{Alarm Register}\label{tbl:alarm} +\end{center}\end{table} +Basically, the alarm register consists a time and two more bits. The extra +two bits encode whether or not the alarm is enabled, and whether or not it has +been tripped. The alarm will be {\em tripped} whenever it is enabled, and the +time changes to equal the alarm time. Once tripped, the alarm will stay +in the alarmed or tripped condition until either a '1' is written to the +tripped bit, or the alarm is disabled. + +As with the clock and timer registers, writing eight ones to any of the +BCD fields when writing to this register will leave those fields untouched. + +\section{Clock Speed Register} +The actual speed of the clock is controlled by the {\tt CKSPEED} register, +shown in Tbl.~\ref{tbl:ckspeed}. +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +0--31 & R/W & 48~bit counter time increment\\\hline +\end{bitlist} +\caption{Clock Speed Register}\label{tbl:ckspeed} +\end{center}\end{table} +This register contains a simple 32~bit unsigned value. To step the clock, +this value is extended to 48~bits and added to the fractional seconds value. + +This value should be set to $2^{48}$ divided by the clock frequency of the +controlling clock. Hence, for a 100~MHz clock, this value would be set to +{\tt 32'd2814750}. For clocks near 100~MHz, this allows adjusting speed +within about 40~clocks per second. For clocks near 500~MHz, this allows +time adjustment to an accuracy of about about 800~clocks per second. In +both cases, this is good enough to maintain a clock with less than a +microsecond loss over the course of a year. Hence, this RTC module provides +more logical stability than most hardware clocks on the market today. + +\section{Time--hack time} +To support finer precision clock control, the time--hack capability exists. +This capability consists of three registers, the time--hack time register +shown in Tbl.~\ref{tbl:hacktime}, +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +24--31 & R & BCD Hours.\\\hline +16--23 & R & BCD Minutes.\\\hline +8--15 & R & BCD seconds.\\\hline +0--7 & R & Subseconds, encoded in 256ths of a second\\\hline +\end{bitlist} +\caption{Time Hack Time Register}\label{tbl:hacktime} +\end{center}\end{table} +and two registers (Tbls.~\ref{tbl:hackcnthi} +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +0--31 & R & Upper 32 bits of the internal 40~bit counter.\\\hline +\end{bitlist} +\caption{Time Hack Counter, High}\label{tbl:hackcnthi} +\end{center}\end{table} +and~\ref{tbl:hackcntlo}) +\begin{table}[htbp] +\begin{center} +\begin{bitlist} +24--31 & R & Bottom 8~bits of the internal 40~bit counter.\\\hline +0--23 & R & Always read as '0'.\\\hline +\end{bitlist} +\caption{Time Hack Counter, Low}\label{tbl:hackcntlo} +\end{center}\end{table} +capturing the contents of the 40~bit internal counter at the time of the hack. + +The time--hack time register is perhaps the simplest to understand. This +captures the time of the time--hack in hours, minutes, seconds, and 8~fractional +subsecond bits. The top 24~bits of this register will match the bottom 24~bits +of the clock~time register at the time of the time hack. The bottom eight +bits are the top eight bits of the 48~bit subsecond time counter. The +rest of those 48~bits may then be returned in the other two time hack counter +registers. + +At present, this functionality isn't yet truly fully featured. Once fully +featured, there will (should) be a mechanism for adjusting this counter based +upon information gleaned from the hack time. Implementation details have +to date prevented this portion of the design from being implemented. + +\chapter{Wishbone Datasheet}\label{chap:wishbone} +Tbl.~\ref{tbl:wishbone} +\begin{table}[htbp] +\begin{center} +\begin{wishboneds} +Revision level of wishbone & WB B4 spec \\\hline +Type of interface & Slave, Read/Write \\\hline +Port size & 32--bit \\\hline +Port granularity & 32--bit \\\hline +Maximum Operand Size & 32--bit \\\hline +Data transfer ordering & (Irrelevant) \\\hline +Clock constraints & Faster than 66~kHz \\\hline +Signal Names & \begin{tabular}{ll} + Signal Name & Wishbone Equivalent \\\hline + {\tt i\_clk} & {\tt CLK\_I} \\ + {\tt i\_wb\_cyc} & {\tt CYC\_I} \\ + {\tt i\_wb\_stb} & {\tt STB\_I} \\ + {\tt i\_wb\_we} & {\tt WE\_I} \\ + {\tt i\_wb\_addr} & {\tt ADR\_I} \\ + {\tt i\_wb\_data} & {\tt DAT\_I} \\ + {\tt o\_wb\_ack} & {\tt ACK\_O} \\ + {\tt o\_wb\_stall} & {\tt STALL\_O} \\ + {\tt o\_wb\_data} & {\tt DAT\_O} + \end{tabular}\\\hline +\end{wishboneds} +\caption{Wishbone Datasheet}\label{tbl:wishbone} +\end{center}\end{table} +is required by the wishbone specification, and so +it is included here. The big thing to notice is that this real time clock +acts as a wishbone slave, and that all accesses to the +clock registers are 32--bit reads and writes. The address bus does not offer +byte level, but rather 32--bit word level resolution. Select lines are not +implemented. Bit ordering is the normal ordering where bit~31 is the most +significant bit and so forth. Although the stall line is implemented, it is +always zero. Access delays are a single clock, so the clock after a read or +write is placed on the bus the {\tt i\_wb\_ack} line will be high. + +\iffalse +\chapter{Clocks}\label{chap:clocks} + +This core is based upon the Basys--3 design. The Basys--3 development board +contains one external 100~MHz clock, which is sufficient to run this +core. The logic within the core can also be run faster, or slower, as is +necessary to meet the timing constraints associated with the internal +operations of the core and it's surrounding environment. See +Table.~\ref{tbl:clocks}. +\begin{table}[htbp] +\begin{center} +\begin{clocklist} +i\_clk & External & 250~THz & 66~kHz & System clock.\\\hline +\end{clocklist} +\caption{List of Clocks}\label{tbl:clocks} +\end{center}\end{table} + +\fi + +\chapter{I/O Ports}\label{chap:ioports} +The I/O ports for this core are shown in Tbls.~\ref{tbl:iowishbone} +\begin{table}[htbp] +\begin{center} +\begin{portlist} +i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline +i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline +i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline +i\_wb\_addr & 5 & Input & Wishbone address.\\\hline +i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing + (configuring) the core from the bus.\\\hline +o\_wb\_ack & 1 & Output & Return value acknowledging a wishbone write, or + signifying valid data in the case of a wishbone read request. + \\\hline +o\_wb\_stall & 1 & Output & Indicates the device is not yet ready for another + wishbone access, effectively stalling the bus.\\\hline +o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read + from the interface.\\\hline +\end{portlist} +\caption{Wishbone I/O Ports}\label{tbl:iowishbone} +\end{center}\end{table} +and~Tbl.~\ref{tbl:ioother}. +\begin{table}[htbp] +\begin{center} +\begin{portlist} +o\_sseg & 32 & Output & Lines to control a seven segment display, to be + sent to that display's driver. Each eight bit byte controls + one digit in the display, with the bottom bit in the byte + controlling the decimal point.\\\hline +o\_led & 16 & Output & Output LED's, consisting of a 16--bit counter counting + from zero to all ones each minute, and synchronized with each + minute so as to create an indicator of when the next minute + will take place when only the hours and minutes can be + displayed.\\\hline +o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the + clock needs to generate an interrupt, it will set this line + high for one clock cycle. \\\hline +i\_hack & 1 & Input & When this line is raised, copies are made of the + internal state registers on the next clock. These registers can then + be used for an accurate time hack regarding the state of the clock + at the time this line was strobed.\\\hline +\end{portlist} +\caption{Other I/O Ports}\label{tbl:ioother} +\end{center}\end{table} +Tbl.~\ref{tbl:iowishbone} reiterates the wishbone I/O values just discussed in +Chapt.~\ref{chap:wishbone}, and so need no further discussion here. + +This clock is designed for command and control via the wishbone. No other +registers, beyond the wishbone bus, are required. However, several other +may be valuable. These other registers are listed in Tbl.~\ref{tbl:ioother}. +We'll discuss each of these in turn. + +First of the other I/O registers is the {\tt o\_sseg} register. This register +encodes which outputs of a seven segment display need to be turned on to +represent the value of the clock requested. This register consists of four +eight bit bytes, with the highest order byte referencing the highest order +display segment value. In each byte, the low order bit references a decimal +point. The other bits are ordered around the zero, with the top bit being +the top bar of a '0', the next highest order bit and so on following the +zero clockwise. The final bit of each byte, the bit in the two's place, +encodes whether or not the middle line is to be displayed. When either timer +or alarm is triggered, this display will blink until the triggering conditions +are cleared. + +This output is expected to be the input to a seven segment display driver, +rather than being the output to the display itself. + +The next output lines are the 16~lines of the {\tt o\_led} bus. When connected +with 16~LED's, these lines will create a counting display that will count up +to each minute, synchronized to the minute. When either timer or alarm has +triggered, all of the LED's will flash together until the triggered condition +is reset. + +The third other line is the {\tt o\_interrupt} line. This line will be +strobed by the RTC module any time the alarm is triggered or the timer runs +out. The line will not remain high, but neither will it trigger a second +time until the underlying interrupt is cleared. That is, the timer will only +trigger once until cleared as will the alarm, but the alarm may trigger after +the timer has triggered and before the timer clears. + +The final other I/O line is a simple input line. This line is expected to be +strobed for one clock cycle any time a time hack is required. For example, +should you wish to read and synchronize to a GPS PPS signal, strobe the device +with the PPS (after dealing with any metastability issues), and read the time +hacks that are produced. + +% Appendices +% Index +\end{document} + + Index: rtcclock/trunk/doc/gpl-3.0.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: rtcclock/trunk/doc/gpl-3.0.pdf =================================================================== --- rtcclock/trunk/doc/gpl-3.0.pdf (nonexistent) +++ rtcclock/trunk/doc/gpl-3.0.pdf (revision 2)
rtcclock/trunk/doc/gpl-3.0.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rtcclock/trunk/doc/Makefile =================================================================== --- rtcclock/trunk/doc/Makefile (nonexistent) +++ rtcclock/trunk/doc/Makefile (revision 2) @@ -0,0 +1,20 @@ +all: gpl-3.0.pdf spec.pdf +DSRC := src + +gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + latex $(DSRC)/gpl-3.0.tex + dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi + ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf + rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps + +spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps + cd $(DSRC)/; latex spec.tex + cd $(DSRC)/; latex spec.tex + dvips -q -z -t letter -P pdf -o spec.ps $(DSRC)/spec.dvi + ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf + rm $(DSRC)/spec.dvi $(DSRC)/spec.log + rm $(DSRC)/spec.aux $(DSRC)/spec.toc + rm $(DSRC)/spec.lot # $(DSRC)/spec.lof + rm spec.ps +

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