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/trunk/code/ISDN_cont/tb/ISDN_cont_tb.vhd
0,0 → 1,359
-------------------------------------------------------------------------------
-- Title : ISDN tdm controller
-- Project : TDM controller
-------------------------------------------------------------------------------
-- File : ISDN_cont_tb.vhd
-- Author : Jamil Khatib <khatib@ieee.org>
-- Organization: OpenCores.org
-- Created : 2001/04/30
-- Last update:2001/04/30
-- Platform :
-- Simulators : NC-sim/linux, Modelsim XE/windows98
-- Synthesizers: Leonardo
-- Target :
-- Dependency : ieee.std_logic_1164, ieee.std_logic_unsigned.
-- HDLC.hdlc_components_pkg
-------------------------------------------------------------------------------
-- Description: ISDN tdm controller that extracts 2B+D channels from 3 time
-- slots of the incoming streem
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 2001/04/30
-- Modifier : Jamil Khatib <khatib@ieee.org>
-- Desccription : Created
-- ToOptimize :
-- Known Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2001/05/06 17:55:23 jamil
-- Initial Release
--
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library HDLC;
use HDLC.hdlc_components_pkg.all;
 
-------------------------------------------------------------------------------
 
entity isdn_cont_tb is
 
end isdn_cont_tb;
 
-------------------------------------------------------------------------------
 
architecture isdn_cont_tb of isdn_cont_tb is
 
component isdn_cont_ent
port (
rst_n : in std_logic;
C2 : in std_logic;
DSTi : in std_logic;
DSTo : out std_logic;
F0_n : in std_logic;
F0od_n : out std_logic;
HDLCen1 : out std_logic;
HDLCen2 : out std_logic;
HDLCen3 : out std_logic;
HDLCTxen1 : out std_logic;
HDLCTxen2 : out std_logic;
HDLCTxen3 : out std_logic;
Dout : out std_logic;
Din1 : in std_logic;
Din2 : in std_logic;
Din3 : in std_logic);
end component;
 
signal rst_n : std_logic := '0';
signal C2 : std_logic := '0';
signal DSTi : std_logic;
signal DSTo : std_logic;
signal F0_n : std_logic;
signal F0od_n : std_logic;
signal HDLCen1 : std_logic;
signal HDLCen2 : std_logic;
signal HDLCen3 : std_logic;
signal HDLCTxen1 : std_logic;
signal HDLCTxen2 : std_logic;
signal HDLCTxen3 : std_logic;
signal Dout : std_logic;
signal Din1 : std_logic;
signal Din2 : std_logic;
signal Din3 : std_logic;
 
--Rx HDLC
signal RxData_o : std_logic_vector(7 downto 0);
signal ValidFrame : std_logic;
signal FrameError_i : std_logic;
signal AbortSignal_i : std_logic;
signal Rx_Readbyte : std_logic;
signal Rx_rdy : std_logic;
 
--Tx HDLC
signal Tx_ValidFrame : std_logic;
signal Tx_AbortFrame : std_logic;
signal Tx_AbortedTrans : std_logic;
signal Tx_WriteByte : std_logic;
signal Tx_rdy : std_logic;
signal TxData : std_logic_vector(7 downto 0);
 
type SERIAL_typ is array (0 to 511) of std_logic; -- Serial Data array
 
signal RxData : SERIAL_typ; -- Rx Serial Data
 
begin -- isdn_cont_tb
 
C2 <= not C2 after 244 ns;
rst_n <= '0',
'1' after 730 ns;
 
 
-------------------------------------------------------------------------------
-- purpose: Initialization
-- type : combinational
-- inputs : rst_n
-- outputs:
INIT : process (rst_n)
variable counter : std_logic_vector(7 downto 0) := "00000000"; -- Internal Counter
begin -- PROCESS INIT
 
if (rst_n = '0') then
 
RxData(0) <= '1';
RxData(1) <= '1';
RxData(2) <= '1';
RxData(3) <= '1';
RxData(4) <= '1';
RxData(5) <= '1';
RxData(6) <= '1';
RxData(7) <= '1';
 
RxData(8) <= '1';
RxData(9) <= '1';
RxData(10) <= '1';
RxData(11) <= '1';
RxData(12) <= '1';
RxData(13) <= '1';
RxData(14) <= '1';
RxData(15) <= '1';
 
RxData(16) <= '1';
RxData(17) <= '1';
RxData(18) <= '1';
RxData(19) <= '1';
RxData(20) <= '1';
RxData(21) <= '1';
RxData(22) <= '1';
RxData(23) <= '1';
 
-- Idle
RxData(24) <= '0';
RxData(25) <= '1';
RxData(26) <= '1';
RxData(27) <= '1';
RxData(28) <= '1';
RxData(29) <= '1';
RxData(30) <= '1';
RxData(31) <= '0';
-- Opening Flag
 
-- Data pattern
for i in 0 to 5 loop
RxData(32+8*i+0) <= Counter(0);
RxData(32+8*i+1) <= Counter(1);
RxData(32+8*i+2) <= Counter(2);
RxData(32+8*i+3) <= Counter(3);
RxData(32+8*i+4) <= Counter(4);
RxData(32+8*i+5) <= Counter(5);
RxData(32+8*i+6) <= Counter(6);
RxData(32+8*i+7) <= Counter(7);
 
Counter := Counter +1;
end loop; -- i
 
 
 
 
 
 
-- Data pattern
-- FOR i IN 0 TO 31 LOOP
-- RxData(8*i+0) <= Counter(0);
-- RxData(8*i+1) <= Counter(1);
-- RxData(8*i+2) <= Counter(2);
-- RxData(8*i+3) <= Counter(3);
-- RxData(8*i+4) <= Counter(4);
-- RxData(8*i+5) <= Counter(5);
-- RxData(8*i+6) <= Counter(6);
-- RxData(8*i+7) <= Counter(7);
 
-- Counter := Counter +1;
-- END LOOP; -- i
 
end if;
end process INIT;
-- purpose: Framing pulse genertor
-- type : combinational
-- inputs :
-- outputs:
-- F0_gen : process
-- begin -- process F0_gen
 
F0_n <= '1',
-- wait until rst_n = '1';
 
'0' after 970 ns,
'1' after 1464 ns,
'0' after 12200 ns,
'1' after 12688 ns,
'0' after 25367 ns,
'1' after 25864 ns;
 
-- wait until C2 = '0';
-- F0_n <= '0' after 15130 ns,
-- '1' after 15500 ns;
-- end process F0_gen;
-------------------------------------------------------------------------------
-- purpose: Rx Data generator
-- type : combinational
-- inputs : C2, rst_n
-- outputs:
Rx_gen : process
variable i : integer := 0;
begin -- PROCESS Rx_gen
DSTi <= '1';
 
wait until rst_n = '1';
while (true) loop
 
wait until F0_n = '0';
 
for counter in 0 to 31 loop
 
DSTi <= RxData(i); --(counter+i*8);
 
wait until C2 = '1';
 
i := i +1;
 
end loop; -- counter
 
end loop; -- while
 
end process Rx_gen;
 
-------------------------------------------------------------------------------
-- purpose: Tx generator for serial backend data
-- type : combinational
-- inputs :
-- outputs:
-- Tx_gen : PROCESS
-- VARIABLE count_index : INTEGER := 0; --
 
-- BEGIN -- PROCESS Tx_gen
-- Din1 <= '0';
-- Din2 <= '0';
-- Din3 <= '0';
 
-- WAIT UNTIL rst_n = '1';
 
---- wait until C2 = '0';
-- WAIT UNTIL HDLCTxen1 = '1' AND C2 = '0';
 
-- WHILE HDLCTxen1 = '1' LOOP
-- Din1 <= RxData(count_index);
-- count_index := count_index + 1;
-- WAIT UNTIL C2 = '1';
-- END LOOP;
 
-- WHILE HDLCTxen2 = '1' LOOP
-- Din2 <= RxData(count_index);
-- count_index := count_index + 1;
-- WAIT UNTIL C2 = '1';
-- END LOOP;
 
-- WHILE HDLCTxen3 = '1' LOOP
-- Din3 <= RxData(count_index);
-- count_index := count_index + 1;
-- WAIT UNTIL C2 = '1';
-- END LOOP;
 
-- END PROCESS Tx_gen;
-------------------------------------------------------------------------------
HDLC_read : process
 
begin -- PROCESS HDLC_read
Rx_Readbyte <= '0';
 
while (true) loop
wait until Rx_rdy = '1';
Rx_Readbyte <= '1';
wait until Rx_rdy = '0';
Rx_Readbyte <= '0';
 
end loop;
 
end process HDLC_read;
DUT : isdn_cont_ent
port map (
rst_n => rst_n,
C2 => C2,
DSTi => DSTi,
DSTo => DSTo,
F0_n => F0_n,
F0od_n => F0od_n,
HDLCen1 => HDLCen1,
HDLCen2 => HDLCen2,
HDLCen3 => HDLCen3,
HDLCTxen1 => HDLCTxen1,
HDLCTxen2 => HDLCTxen2,
HDLCTxen3 => HDLCTxen3,
Dout => Dout,
Din1 => Din1,
Din2 => Din2,
Din3 => Din3);
 
 
RxChannel : RxChannel_ent
port map (
Rxclk => C2,
rst => rst_n,
Rx => Dout,
RxData => RxData_o,
ValidFrame => ValidFrame,
FrameError => FrameError_i,
AbortSignal => AbortSignal_i,
Readbyte => Rx_Readbyte,
rdy => Rx_rdy,
RxEn => HDLCen1);
 
 
TxChannel : TxChannel_ent
port map (
TxClk => C2,
rst_n => rst_n,
TXEN => HDLCTxen1,
Tx => Din1,
ValidFrame => Tx_ValidFrame,
AbortFrame => Tx_AbortFrame,
AbortedTrans => Tx_AbortedTrans,
WriteByte => Tx_WriteByte,
rdy => Tx_rdy,
TxData => TxData);
 
end isdn_cont_tb;
 
-------------------------------------------------------------------------------
/trunk/code/ISDN_cont/scripts/nc-sim/build_ISDN_cont.csh
0,0 → 1,51
#! /bin/tcsh -f
# By Jamil Khatib
# This file for compiling the tdm project files using Cadence nc-sim tool
# You need to create sim directory in the same level of the code directory
# From OpenCores CVS
# You have to start the simulation in this directory
#$Log: not supported by cvs2svn $
mkdir -p work
mkdir -p utility
mkdir -p hdlc
mkdir -p memLib
mkdir -p tdm
 
# Utility files
 
#memLib
 
 
#HDLC files
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/libs/hdlc_components_pkg.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/Rxcont.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/Zero_detect.vhd
 
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/flag_detect.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/RX/core/RxChannel.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/TXcont.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/flag_ins.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/zero_ins.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../../hdlc/code/TX/core/TxChannel.vhd
 
#ISDN files
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/ISDN_cont/core/ISDN_cont.vhd
 
ncvhdl -work tdm -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/libs/components_pkg.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/ISDN_cont/core/ISDN_cont_top.vhd
 
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/ISDN_cont/tb/ISDN_cont_tb.vhd
 
 
#elaborating design
ncelab -work work -cdslib ./cds.lib -logfile ncelab.log -errormax 15 -messages -status -v93 work.isdn_cont_tb:isdn_cont_tb
/trunk/code/ISDN_cont/scripts/modelsim/build_ISDN_cont.do
0,0 → 1,50
# By Jamil Khatib
# This file for compiling the tdm project files using Cadence nc-sim tool
# You need to create sim directory in the same level of the code directory
# From OpenCores CVS
# You have to start the simulation in this directory
#$Log: not supported by cvs2svn $
vlib work
vlib utility
vlib hdlc
vlib memLib
vlib tdm
 
# Utility files
 
#memLib
 
 
#HDLC files
vcom -work hdlc ../../hdlc/code/libs/hdlc_components_pkg.vhd
 
vcom -work hdlc ../../hdlc/code/RX/core/Rxcont.vhd
 
vcom -work hdlc ../../hdlc/code/RX/core/Zero_detect.vhd
 
 
vcom -work hdlc ../../hdlc/code/RX/core/flag_detect.vhd
 
vcom -work hdlc ../../hdlc/code/RX/core/RxChannel.vhd
 
vcom -work hdlc ../../hdlc/code/TX/core/TXcont.vhd
 
vcom -work hdlc ../../hdlc/code/TX/core/flag_ins.vhd
 
vcom -work hdlc ../../hdlc/code/TX/core/zero_ins.vhd
 
vcom -work hdlc ../../hdlc/code/TX/core/TxChannel.vhd
 
#ISDN files
vcom -work work ../code/ISDN_cont/core/ISDN_cont.vhd
 
vcom -work tdm ../code/libs/components_pkg.vhd
 
vcom -work work ../code/ISDN_cont/core/ISDN_cont_top.vhd
 
 
vcom -work work ../code/ISDN_cont/tb/ISDN_cont_tb.vhd
 
 
#elaborating design
#ncelab -work work -cdslib ./cds.lib -logfile ncelab.log -errormax 15 -messages -status -v93 work.isdn_cont_tb:isdn_cont_tb
/trunk/code/ISDN_cont/core/ISDN_cont.vhd
0,0 → 1,291
-------------------------------------------------------------------------------
-- Title : ISDN tdm controller
-- Project : TDM controller
-------------------------------------------------------------------------------
-- File : ISDN_cont.vhd
-- Author : Jamil Khatib <khatib@ieee.org>
-- Organization: OpenCores.org
-- Created : 2001/04/30
-- Last update:2001/05/04
-- Platform :
-- Simulators : NC-sim/linux, Modelsim XE/windows98
-- Synthesizers: Leonardo
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: ISDN tdm controller that extracts 2B+D channels from 3 time
-- slots of the incoming streem
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 2001/04/30
-- Modifier : Jamil Khatib <khatib@ieee.org>
-- Desccription : Created
-- ToOptimize :
-- Known Bugs : The serial interface is not compatible with the ST-Bus
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2001/05/06 17:55:23 jamil
-- Initial Release
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity isdn_cont_ent is
 
port (
rst_n : in std_logic; -- System asynchronous reset
C2 : in std_logic; -- ST-Bus clock
DSTi : in std_logic; -- ST-Bus input Data
DSTo : out std_logic; -- ST-Bus output Data
F0_n : in std_logic; -- St-Bus Framing pulse
F0od_n : out std_logic; -- ST-Bus Delayed Framing pulse
HDLCen1 : out std_logic; -- HDLC controller 1 enable
HDLCen2 : out std_logic; -- HDLC controller 2 enable
HDLCen3 : out std_logic; -- HDLC controller 3 enable
HDLCTxen1 : out std_logic; -- HDLC controller 1 enable Tx
HDLCTxen2 : out std_logic; -- HDLC controller 2 enable Tx
HDLCTxen3 : out std_logic; -- HDLC controller 3 enable Tx
Dout : out std_logic; -- Serial Data output
Din1 : in std_logic; -- Serial Data input1
Din2 : in std_logic; -- Serial Data input2
Din3 : in std_logic); -- Serial Data input3
 
end isdn_cont_ent;
 
-------------------------------------------------------------------------------
 
architecture isdn_cont_rtl of isdn_cont_ent is
type STATES_TYPE is (IDLE_st, PASSB1_st, PASSB2_st, PASSD_st); -- FSM states
 
signal p_state : STATES_TYPE; -- Present state
signal n_state : STATES_TYPE; -- Next State
signal counter_Rx_i : std_logic_vector( 2 downto 0); -- Internal counter
signal counter_Rx_reg : std_logic_vector( 2 downto 0); -- Internal counter
 
signal p_state_Tx : STATES_TYPE; -- Present state
signal n_state_Tx : STATES_TYPE; -- Next State
 
signal counter_Tx_i : std_logic_vector( 2 downto 0); -- Internal counter
signal counter_Tx_reg : std_logic_vector( 2 downto 0); -- Internal counter
 
signal DSTi_reg : std_logic; -- DSTi register
signal F0_n_reg : std_logic; -- F0_n register
 
signal F0od_n_i : std_logic; -- Delayed F0output internal
signal outputData_reg : std_logic_vector(17 downto 0);
-- Output Data register
signal outputData : std_logic_vector(17 downto 0);
-- Output Data
 
begin -- isdn_cont_rtl
 
Dout <= DSTi_reg;
 
-- purpose: Rising edge F0_n sampling
-- type : sequential
-- inputs : C2, rst_n
-- outputs:
rising_edge_regs : process (C2, rst_n)
begin -- process rising_edge
if rst_n = '0' then -- asynchronous reset (active low)
F0_n_reg <= '1';
-- F0od_n <= '1';
outputData_reg <= (others => '1');
p_state_tx <= IDLE_st;
counter_Tx_reg <= "000";
elsif C2'event and C2 = '1' then -- rising clock edge
F0_n_reg <= F0_n;
-- F0od_n <= F0od_n_i;
outputData_reg <= outputData;
p_state_tx <= n_state_tx;
counter_Tx_reg <= counter_Tx_i;
end if;
end process rising_edge_regs;
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- purpose: FSM Combinational logic
-- type : combinational
-- inputs : F0_n, p_state_tx, counter_tx_reg, outputData_reg, Din1, Din2, Din3
-- outputs:
comb_tx : process (F0_n, p_state_tx, counter_tx_reg, outputData_reg, Din1, Din2, Din3)
 
begin -- PROCESS comb
 
case p_state_tx is
 
when IDLE_st =>
HDLCTxen1 <= '0';
HDLCTxen2 <= '0';
HDLCTxen3 <= '0';
 
counter_Tx_i <= "000";
 
DSTo <= 'Z';
outputData <= outputData_reg;
 
if (F0_n = '0') then
n_state_tx <= PASSB1_st;
else
n_state_tx <= IDLE_st;
end if;
 
when PASSB1_st =>
 
HDLCTxen1 <= '1';
HDLCTxen2 <= '0';
HDLCTxen3 <= '0';
 
counter_Tx_i <= counter_Tx_reg + 1;
 
if (counter_tx_reg = "110" ) then
n_state_tx <= PASSB2_st;
else
n_state_tx <= PASSB1_st;
end if;
DSTo <= outputData_reg(0);
outputData <= Din1 & outputData_reg(17 downto 1);
 
when PASSB2_st =>
counter_Tx_i <= counter_Tx_reg +1;
 
HDLCTxen1 <= '0';
HDLCTxen2 <= '1';
HDLCTxen3 <= '0';
 
if (counter_tx_reg = "110" ) then
n_state_tx <= PASSD_st;
else
n_state_tx <= PASSB2_st;
end if;
DSTo <= outputData_reg(0);
outputData <= Din2 & outputData_reg(17 downto 1);
 
when PASSD_st =>
counter_Tx_i <= counter_Tx_reg + 1;
 
HDLCTxen1 <= '0';
HDLCTxen2 <= '0';
HDLCTxen3 <= '1';
 
if (counter_tx_reg = "001" ) then
n_state_tx <= IDLE_st;
else
n_state_tx <= PASSD_st;
end if;
DSTo <= outputData_reg(0);
outputData <= Din3 & outputData_reg(17 downto 1);
 
end case;
 
end process comb_tx;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- purpose: FSM registers
-- type : sequential
-- inputs : C2, rst_n
-- outputs:
fsm : process (C2, rst_n)
begin -- PROCESS fsm
 
if rst_n = '0' then -- asynchronous reset (active low)
p_state <= IDLE_st;
DSTi_reg <= '0';
F0od_n <= '1';
counter_Rx_reg <= "000";
elsif C2'event and C2 = '0' then -- falling clock edge
p_state <= n_state;
DSTi_reg <= DSTi;
F0od_n <= F0od_n_i;
counter_Rx_reg <= counter_Rx_i;
end if;
 
end process fsm;
 
-------------------------------------------------------------------------------
-- purpose: FSM Combinational logic
-- type : combinational
-- inputs : F0_n,Din,p_state
-- outputs:
comb : process (F0_n_reg, p_state, counter_Rx_reg, outputData_reg, Din1, Din2, Din3)
 
begin -- PROCESS comb
 
case p_state is
 
when IDLE_st =>
HDLCen1 <= '0';
HDLCen2 <= '0';
HDLCen3 <= '0';
 
counter_Rx_i <= "000";
 
F0od_n_i <= '1';
 
if (F0_n_reg = '0') then
n_state <= PASSB1_st;
else
n_state <= IDLE_st;
end if;
 
when PASSB1_st =>
 
HDLCen1 <= '1';
HDLCen2 <= '0';
HDLCen3 <= '0';
 
counter_Rx_i <= counter_Rx_reg + 1;
 
F0od_n_i <= '1';
 
if (counter_Rx_reg = "111" ) then
n_state <= PASSB2_st;
else
n_state <= PASSB1_st;
end if;
 
when PASSB2_st =>
HDLCen1 <= '0';
HDLCen2 <= '1';
HDLCen3 <= '0';
counter_Rx_i <= counter_Rx_reg + 1;
F0od_n_i <= '1';
 
if (counter_Rx_reg = "111" ) then
n_state <= PASSD_st;
else
n_state <= PASSB2_st;
end if;
 
when PASSD_st =>
HDLCen1 <= '0';
HDLCen2 <= '0';
HDLCen3 <= '1';
counter_Rx_i <= counter_Rx_reg + 1;
 
if (counter_Rx_reg = "001" ) then
n_state <= IDLE_st;
F0od_n_i <= '0';
else
n_state <= PASSD_st;
F0od_n_i <= '1';
end if;
 
end case;
end process comb;
 
-------------------------------------------------------------------------------
end isdn_cont_rtl;
/trunk/code/libs/components_pkg.vhd
0,0 → 1,64
-------------------------------------------------------------------------------
-- Title : ISDN tdm controller
-- Project : TDM controller
-------------------------------------------------------------------------------
-- File : components_pkg.vhd
-- Author : Jamil Khatib <khatib@ieee.org>
-- Organization: OpenCores.org
-- Created : 2001/05/06
-- Last update:2001/05/06
-- Platform :
-- Simulators : NC-sim/linux, Modelsim XE/windows98
-- Synthesizers: Leonardo
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: tdm components
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 2001/05/06
-- Modifier : Jamil Khatib <khatib@ieee.org>
-- Desccription : Created
-- ToOptimize :
-- Known Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
--
-------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
PACKAGE components_pkg IS
 
COMPONENT isdn_cont_ent
PORT (
rst_n : in std_logic;
C2 : in std_logic;
DSTi : in std_logic;
DSTo : out std_logic;
F0_n : in std_logic;
F0od_n : out std_logic;
HDLCen1 : out std_logic;
HDLCen2 : out std_logic;
HDLCen3 : out std_logic;
HDLCTxen1 : out std_logic;
HDLCTxen2 : out std_logic;
HDLCTxen3 : out std_logic;
Dout : out std_logic;
Din1 : in std_logic;
Din2 : in std_logic;
Din3 : in std_logic);
END COMPONENT;
 
END components_pkg;

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