URL
https://opencores.org/ocsvn/uart8systemc/uart8systemc/trunk
Subversion Repositories uart8systemc
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- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/uart8systemc/trunk/testbench/module_tb.v
0,0 → 1,63
|
`timescale 1ns/1ns |
module module_tb; |
|
reg CLK; |
wire RESET; |
wire RX; |
wire START; |
wire [7:0] DATA_TX; |
wire [11:0] WORK_FR; |
wire TX; |
wire [7:0] DATA_RX; |
wire PARITY_RX; |
wire READY_TX; |
wire READY; |
|
assign DATA_TX = DATA_RX; |
|
initial CLK = 1'b0; |
always #(10) CLK = ~CLK; |
|
integer i; |
|
initial |
begin |
$dumpfile("module_tb.vcd"); |
$dumpvars(0,module_tb); |
$global_init; |
i=0; |
end |
|
UART DUT( |
.CLK(CLK), |
.RESET(RESET), |
.RX(RX), |
.START(START), |
.DATA_TX(DATA_TX), |
.WORK_FR(WORK_FR), |
.TX(TX), |
.DATA_RX(DATA_RX), |
.PARITY_RX(PARITY_RX), |
.READY_TX(READY_TX), |
.READY(READY) |
); |
|
|
always@(posedge CLK) |
$reset_uart; |
|
always@(posedge CLK) |
$execute_uart; |
|
always@(posedge CLK) |
$global_counter; |
|
//FLAG USED TO FINISH SIMULATION PROGRAM |
always@(posedge CLK) |
begin |
wait(i == 1); |
$finish(); |
end |
|
endmodule |
/uart8systemc/trunk/rtl/UART.v
0,0 → 1,50
/* |
Name: Felipe Fernandes da Costa |
|
*/ |
|
`timescale 1ns/1ns |
|
module UART( |
|
input CLK, |
input RESET, |
input RX, |
|
input START, |
input [7:0] DATA_TX, |
|
input [11:0] WORK_FR, |
|
output TX, |
output [7:0] DATA_RX, |
output PARITY_RX, |
|
output READY_TX, |
output READY |
|
); |
|
|
uart_rx RX0 ( |
.PCLK(CLK), |
.RESET(RESET), |
.RX_I(RX), |
.DATA_RX_O(DATA_RX), |
.WORK_FR(WORK_FR), |
.READY(READY), |
.PARITY_RX(PARITY_RX) |
); |
|
|
uart_tx TX0 ( |
.PCLK(CLK), |
.RESET(RESET), |
.START(START), |
.WORK_FR(WORK_FR), |
.DATA_TX_I(DATA_TX), |
.READY_TX(READY_TX), |
.TX_O(TX) |
); |
|
endmodule |
uart8systemc/trunk/rtl/UART.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: uart8systemc/trunk/rtl/uart_rx.v
===================================================================
--- uart8systemc/trunk/rtl/uart_rx.v (nonexistent)
+++ uart8systemc/trunk/rtl/uart_rx.v (revision 2)
@@ -0,0 +1,235 @@
+
+`timescale 1ns/1ns
+
+module uart_rx#(
+ parameter integer WIDTH = 12
+ )
+ (
+ //external input
+ input PCLK,
+ input RESET,
+ input RX_I,
+ input [11:0] WORK_FR,
+ output reg [7:0] DATA_RX_O,
+ output reg PARITY_RX,
+ output READY
+ );
+
+localparam [3:0] RX_IDLE = 4'b0000,
+ RX_DETECT_START = 4'b0001,
+ RX_TAKE_DATA = 4'b0010,
+ RX_TAKE_PARITY = 4'b0100,
+ RX_HIGH_DETECT = 4'b1000;
+
+ reg [3:0] state_rx;
+ reg [3:0] next_state_rx;
+
+ reg [WIDTH-1:0] COUNTER;
+ reg [3:0] DATA_COUNTER;
+
+ reg AUX;
+
+
+assign READY = (state_rx == RX_HIGH_DETECT & COUNTER == 12'd2)?1'b1:1'b0;
+
+
+always@(*)
+begin
+
+ next_state_rx = state_rx;
+
+ case(state_rx)
+ RX_IDLE:
+ begin
+ if(RX_I)
+ begin
+ next_state_rx = RX_IDLE;
+ end
+ else
+ begin
+ next_state_rx = RX_DETECT_START;
+ end
+
+ end
+ RX_DETECT_START:
+ begin
+
+ if(COUNTER == WORK_FR && AUX == 1'b0)
+ begin
+ next_state_rx = RX_TAKE_DATA;
+ end
+ else if(COUNTER != WORK_FR)
+ begin
+ next_state_rx = RX_DETECT_START;
+ end
+ else
+ begin
+ next_state_rx = RX_IDLE;
+ end
+
+ end
+ RX_TAKE_DATA:
+ begin
+
+ if(COUNTER != WORK_FR && DATA_COUNTER != 4'b1000)
+ begin
+ next_state_rx = RX_TAKE_DATA;
+ end
+ else if(COUNTER == WORK_FR && DATA_COUNTER != 4'b1000)
+ begin
+ next_state_rx = RX_TAKE_DATA;
+ end
+ else if(COUNTER == WORK_FR && DATA_COUNTER == 4'b1000)
+ begin
+ next_state_rx = RX_TAKE_PARITY;
+ end
+ end
+ RX_TAKE_PARITY:
+ begin
+
+ if(COUNTER != WORK_FR)
+ begin
+ next_state_rx = RX_TAKE_PARITY;
+ end
+ else
+ begin
+ next_state_rx = RX_HIGH_DETECT;
+ end
+ end
+ RX_HIGH_DETECT:
+ begin
+
+ if(COUNTER != WORK_FR)
+ begin
+ next_state_rx = RX_HIGH_DETECT;
+ end
+ else if(COUNTER == WORK_FR && AUX == 1'b0)
+ begin
+ next_state_rx = RX_HIGH_DETECT;
+ end
+ else
+ begin
+ next_state_rx = RX_IDLE;
+ end
+ end
+ default:
+ begin
+ next_state_rx = RX_IDLE;
+ end
+ endcase
+
+end
+
+
+always@(posedge PCLK)
+begin
+
+ if(RESET)
+ begin
+ state_rx <= RX_IDLE;
+ COUNTER<= {WIDTH{1'b0}};
+ DATA_COUNTER<= 4'd0;
+ DATA_RX_O<=8'd0;
+ AUX<= 1'b1;
+ end
+ else
+ begin
+ state_rx <= next_state_rx;
+
+ case(state_rx)
+ RX_IDLE:
+ begin
+ if(RX_I)
+ begin
+ COUNTER<= {WIDTH{1'b0}};
+ DATA_COUNTER<= 4'd0;
+ end
+ else
+ begin
+ COUNTER<= COUNTER + 1'b1;
+ end
+ end
+ RX_DETECT_START:
+ begin
+
+ if(COUNTER == WORK_FR/2'd2)
+ begin
+ AUX <= RX_I;
+ COUNTER<= COUNTER + 1'b1;
+ end
+ else if(COUNTER < WORK_FR)
+ begin
+ COUNTER<= COUNTER + 1'b1;
+ end
+ else
+ begin
+ COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ RX_TAKE_DATA:
+ begin
+
+ if(DATA_COUNTER != 4'b1000 && COUNTER == WORK_FR/2'd2)
+ begin
+ DATA_COUNTER<= DATA_COUNTER+1'b1;
+ DATA_RX_O[DATA_COUNTER[2:0]]<=RX_I;
+ COUNTER<= COUNTER + 1'b1;
+ end
+ else if(COUNTER < WORK_FR)
+ begin
+ COUNTER<= COUNTER + 1'b1;
+ end
+ else
+ begin
+ COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ RX_TAKE_PARITY:
+ begin
+
+ if(COUNTER == WORK_FR/2'd2)
+ begin
+ PARITY_RX <= RX_I;
+ COUNTER <= COUNTER + 1'b1;
+ end
+ else if(COUNTER < WORK_FR)
+ begin
+ COUNTER <= COUNTER + 1'b1;
+ end
+ else
+ begin
+ COUNTER<= {WIDTH{1'b0}};
+ AUX <= 1'b0;
+ end
+
+ end
+ RX_HIGH_DETECT:
+ begin
+
+ if(COUNTER == WORK_FR/2'd2)
+ begin
+ AUX <= RX_I;
+ COUNTER<= COUNTER + 1'b1;
+ end
+ else if(COUNTER < WORK_FR)
+ begin
+ COUNTER<= COUNTER + 1'b1;
+ end
+ else
+ begin
+ COUNTER<= {WIDTH{1'b0}};
+ end
+ DATA_COUNTER<= 4'd0;
+ end
+ default:
+ begin
+ DATA_COUNTER<= 4'd0;
+ COUNTER<= {WIDTH{1'b0}};
+ end
+
+ endcase
+ end
+end
+
+
+endmodule
uart8systemc/trunk/rtl/uart_rx.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: uart8systemc/trunk/rtl/uart_tx.v
===================================================================
--- uart8systemc/trunk/rtl/uart_tx.v (nonexistent)
+++ uart8systemc/trunk/rtl/uart_tx.v (revision 2)
@@ -0,0 +1,367 @@
+
+`timescale 1ns/1ns
+
+module uart_tx#(
+ parameter integer WIDTH = 12
+ )
+ (
+ input PCLK,
+ input RESET,
+ input [7:0] DATA_TX_I,
+ input [11:0] WORK_FR,
+ input START,
+ output TX_O,
+ output reg READY_TX
+ );
+
+localparam [11:0] TX_IDLE = 12'b0000_0000_0000,
+ TX_START = 12'b0000_0000_0001,
+ TX_BIT_1 = 12'b0000_0000_0010,
+ TX_BIT_2 = 12'b0000_0000_0100,
+ TX_BIT_3 = 12'b0000_0000_1000,
+ TX_BIT_4 = 12'b0000_0001_0000,
+ TX_BIT_5 = 12'b0000_0010_0000,
+ TX_BIT_6 = 12'b0000_0100_0000,
+ TX_BIT_7 = 12'b0000_1000_0000,
+ TX_BIT_8 = 12'b0001_0000_0000,
+ TX_PARITY = 12'b0010_0000_0000,
+ TX_STOP = 12'b0100_0000_0000;
+
+ reg [11:0] state_tx;
+ reg [11:0] next_state_tx;
+
+ reg [WIDTH-1:0] DELAY_COUNTER;
+
+
+
+
+
+assign TX_O = (state_tx == TX_START)?1'b0:
+ (state_tx == TX_BIT_1)?DATA_TX_I[0:0]:
+ (state_tx == TX_BIT_2)?DATA_TX_I[1:1]:
+ (state_tx == TX_BIT_3)?DATA_TX_I[2:2]:
+ (state_tx == TX_BIT_4)?DATA_TX_I[3:3]:
+ (state_tx == TX_BIT_5)?DATA_TX_I[4:4]:
+ (state_tx == TX_BIT_6)?DATA_TX_I[5:5]:
+ (state_tx == TX_BIT_7)?DATA_TX_I[6:6]:
+ (state_tx == TX_BIT_8)?DATA_TX_I[7:7]:
+ (state_tx == TX_PARITY)?DATA_TX_I[0:0]^DATA_TX_I[1:1]^DATA_TX_I[2:2]^DATA_TX_I[3:3]^DATA_TX_I[4:4]^DATA_TX_I[5:5]^DATA_TX_I[6:6]^DATA_TX_I[7:7]:
+ (state_tx == TX_STOP)?1'b1:1'b1;
+
+always@(*)
+begin
+
+ next_state_tx = state_tx;
+
+ case(state_tx)
+ TX_IDLE:
+ begin
+ if(START == 1'b0)
+ begin
+ next_state_tx = TX_IDLE;
+ end
+ else
+ begin
+ next_state_tx = TX_START;
+ end
+ end
+ TX_START:
+ begin
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_START;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_1;
+ end
+
+ end
+ TX_BIT_1:
+ begin
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_1;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_2;
+ end
+
+ end
+ TX_BIT_2:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_2;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_3;
+ end
+
+ end
+ TX_BIT_3:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_3;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_4;
+ end
+ end
+ TX_BIT_4:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_4;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_5;
+ end
+ end
+ TX_BIT_5:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_5;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_6;
+ end
+ end
+ TX_BIT_6:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_6;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_7;
+ end
+ end
+ TX_BIT_7:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_7;
+ end
+ else
+ begin
+ next_state_tx = TX_BIT_8;
+ end
+ end
+ TX_BIT_8:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_BIT_8;
+ end
+ else
+ begin
+ next_state_tx = TX_PARITY;
+ end
+ end
+ TX_PARITY:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_PARITY;
+ end
+ else
+ begin
+ next_state_tx = TX_STOP;
+ end
+ end
+ TX_STOP:
+ begin
+
+ if(DELAY_COUNTER != WORK_FR)
+ begin
+ next_state_tx = TX_STOP;
+ end
+ else
+ begin
+ next_state_tx = TX_IDLE;
+ end
+
+ end
+ default:
+ begin
+ next_state_tx = TX_IDLE;
+ end
+ endcase
+end
+
+
+
+always@(posedge PCLK)
+begin
+ if(RESET)
+ begin
+ READY_TX <= 1'b1;
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ state_tx <= TX_IDLE;
+ end
+ else
+ begin
+ state_tx <= next_state_tx;
+
+ case(state_tx)
+ TX_IDLE:
+ begin
+ if(START == 1'b0)
+ begin
+ READY_TX<= 1'b1;
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ else
+ begin
+ READY_TX<= 1'b0;
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ end
+ TX_START:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_1:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_2:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_3:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_4:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_5:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_6:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_7:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ TX_BIT_8:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER <= {WIDTH{1'b0}};
+ end
+ end
+ TX_PARITY:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER <= {WIDTH{1'b0}};
+ end
+ end
+ TX_STOP:
+ begin
+ if(DELAY_COUNTER < WORK_FR)
+ begin
+ DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
+ end
+ else
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b0}};
+ end
+ end
+ default:
+ begin
+ DELAY_COUNTER<= {WIDTH{1'b1}};
+ end
+ endcase
+ end
+end
+
+
+endmodule
uart8systemc/trunk/rtl/uart_tx.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: uart8systemc/trunk/work/run.sh
===================================================================
--- uart8systemc/trunk/work/run.sh (nonexistent)
+++ uart8systemc/trunk/work/run.sh (revision 2)
@@ -0,0 +1,8 @@
+
+g++ -c -ldl -fpic ../vpi/env_uart.cpp -std=c++11 -Wwrite-strings -fpermissive
+
+g++ -shared -oenv_uart.vpi env_uart.o -lvpi -std=c++11 -Wwrite-strings -fpermissive
+
+iverilog -oenv_uart ../rtl/*.v ../testbench/module_tb.v
+
+vvp -M. -menv_uart env_uart
Index: uart8systemc/trunk/LICENSE
===================================================================
--- uart8systemc/trunk/LICENSE (nonexistent)
+++ uart8systemc/trunk/LICENSE (revision 2)
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. .
Index: uart8systemc/trunk/systemC/link_sc.h
===================================================================
--- uart8systemc/trunk/systemC/link_sc.h (nonexistent)
+++ uart8systemc/trunk/systemC/link_sc.h (revision 2)
@@ -0,0 +1,36 @@
+#ifndef CONTROL_SC_H
+#define CONTROL_SC_H
+
+class Control_SC
+{
+ public:
+ /*Constructor*/
+ Control_SC();
+
+ /*initialize systemC model*/
+ virtual void init();
+
+ /*Reset the model*/
+ virtual void reset_set_high();
+ virtual void reset_set_low();
+
+ /*This is used to configure clock on systemC model note here you must put period T = 1/F*/
+ virtual void set_period_clock_sc(unsigned value_freq);
+
+ /*This must be used to set baud value on Env. Ex: 9600 / 50MHz"Only 50"*/
+ virtual void set_baud_rate(unsigned int value_baud,unsigned frequency);
+ /*Get the baud rate and set it to your DUT*/
+ virtual int get_baud_rate();
+
+ /*We use functions to retreive values from RX / TX SytemC to Verilog*/
+ virtual void write_rx(unsigned int a);
+ virtual int read_tx();
+
+ /*Run the Env for a mmount off time*/
+ virtual void run_sim();
+
+ /*Tell to SystemC to finish*/
+ virtual void stop_sim();
+
+};
+#endif
Index: uart8systemc/trunk/README.md
===================================================================
--- uart8systemc/trunk/README.md (nonexistent)
+++ uart8systemc/trunk/README.md (revision 2)
@@ -0,0 +1,2 @@
+# UART
+This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
Index: uart8systemc/trunk/vpi/execute_uart.h
===================================================================
--- uart8systemc/trunk/vpi/execute_uart.h (nonexistent)
+++ uart8systemc/trunk/vpi/execute_uart.h (revision 2)
@@ -0,0 +1,67 @@
+static int execute_uart_calltf(char*user_data)
+{
+
+ vpiHandle RESET = vpi_handle_by_name("module_tb.RESET", NULL);
+ vpiHandle RX = vpi_handle_by_name("module_tb.RX", NULL);
+ vpiHandle START = vpi_handle_by_name("module_tb.START", NULL);
+ vpiHandle DATA_TX = vpi_handle_by_name("module_tb.DATA_TX", NULL);
+ vpiHandle WORK_FR = vpi_handle_by_name("module_tb.WORK_FR", NULL);
+ vpiHandle TX = vpi_handle_by_name("module_tb.TX", NULL);
+ vpiHandle DATA_RX = vpi_handle_by_name("module_tb.DATA_RX", NULL);
+ vpiHandle PARITY_RX = vpi_handle_by_name("module_tb.PARITY_RX", NULL);
+ vpiHandle READY_TX = vpi_handle_by_name("module_tb.READY_TX", NULL);
+ vpiHandle READY = vpi_handle_by_name("module_tb.READY", NULL);
+
+
+ reset.format = vpiIntVal;
+ rx_value.format = vpiIntVal;
+ tx_value.format = vpiIntVal;
+ ready_rx.format = vpiIntVal;
+ start_tx.format = vpiIntVal;
+ ready_tx.format = vpiIntVal;
+
+
+ vpi_get_value(RESET, &reset);
+
+ if(reset.value.integer == 0)
+ {
+ tx_value.value.integer = SC_UART->read_tx();
+ vpi_put_value(RX, &tx_value, NULL, vpiNoDelay);
+
+ vpi_get_value(TX, &rx_value);
+ SC_UART->write_rx(rx_value.value.integer);
+
+ SC_UART->run_sim();
+
+ vpi_get_value(READY, &ready_rx);
+
+ if(ready_rx.value.integer == 1)
+ {
+ vpi_get_value(READY_TX, &ready_tx);
+
+ if(ready_tx.value.integer == 1)
+ {
+ start_tx.value.integer = 1;
+ vpi_put_value(START, &start_tx, NULL, vpiNoDelay);
+ }
+ }
+ else
+ {
+ vpi_get_value(READY_TX, &ready_tx);
+
+ if(ready_tx.value.integer == 0)
+ {
+ start_tx.value.integer = 0;
+ vpi_put_value(START, &start_tx, NULL, vpiNoDelay);
+ }
+ }
+
+ }else
+ {
+
+ }
+
+
+
+ return 0;
+}
Index: uart8systemc/trunk/vpi/reset_uart.h
===================================================================
--- uart8systemc/trunk/vpi/reset_uart.h (nonexistent)
+++ uart8systemc/trunk/vpi/reset_uart.h (revision 2)
@@ -0,0 +1,22 @@
+static int reset_uart_calltf(char*user_data)
+{
+
+ vpiHandle RESET = vpi_handle_by_name("module_tb.RESET", NULL);
+
+ reset.format=vpiIntVal;
+
+ if(counter_reset < 5)
+ {
+ reset.value.integer = 1;
+ vpi_put_value(RESET, &reset, NULL, vpiNoDelay);
+ counter_reset = counter_reset + 1;
+ }
+ else
+ {
+ reset.value.integer = 0;
+ vpi_put_value(RESET, &reset, NULL, vpiNoDelay);
+ SC_UART->reset_set_low();
+ }
+
+ return 0;
+}
Index: uart8systemc/trunk/vpi/env_uart.cpp
===================================================================
--- uart8systemc/trunk/vpi/env_uart.cpp (nonexistent)
+++ uart8systemc/trunk/vpi/env_uart.cpp (revision 2)
@@ -0,0 +1,83 @@
+#include "../iverilog/vpi_user.h"
+
+#include "../systemC/link_sc.h"
+
+int counter;
+int counter_reset;
+
+#include
+#include
+#include
+#include
+#include
+
+using namespace std;
+
+void* lib_handle;
+
+Control_SC* (*create)();
+void (*destroy)(Control_SC*);
+
+Control_SC* SC_UART;
+
+s_vpi_value v_generate;
+
+s_vpi_value reset;
+s_vpi_value rx_value;
+s_vpi_value tx_value;
+
+s_vpi_value ready_rx;
+s_vpi_value start_tx;
+s_vpi_value ready_tx;
+
+#include "execute_uart.h"
+#include "reset_uart.h"
+#include "global_init.h"
+#include "counter_global.h"
+
+void Leitura_register()
+{
+ s_vpi_systf_data tf_data;
+
+ tf_data.type = vpiSysTask;
+ tf_data.sysfunctype = 0;
+ tf_data.tfname = "$execute_uart";
+ tf_data.calltf = execute_uart_calltf;
+ tf_data.compiletf = 0;
+ tf_data.sizetf = 0;
+ tf_data.user_data = 0;
+ vpi_register_systf(&tf_data);
+
+ tf_data.type = vpiSysTask;
+ tf_data.sysfunctype = 0;
+ tf_data.tfname = "$reset_uart";
+ tf_data.calltf = reset_uart_calltf;
+ tf_data.compiletf = 0;
+ tf_data.sizetf = 0;
+ tf_data.user_data = 0;
+ vpi_register_systf(&tf_data);
+
+ tf_data.type = vpiSysTask;
+ tf_data.sysfunctype = 0;
+ tf_data.tfname = "$global_counter";
+ tf_data.calltf = global_counter_calltf;
+ tf_data.compiletf = 0;
+ tf_data.sizetf = 0;
+ tf_data.user_data = 0;
+ vpi_register_systf(&tf_data);
+
+ tf_data.type = vpiSysTask;
+ tf_data.sysfunctype = 0;
+ tf_data.tfname = "$global_init";
+ tf_data.calltf = global_init_calltf;
+ tf_data.compiletf = 0;
+ tf_data.sizetf = 0;
+ tf_data.user_data = 0;
+ vpi_register_systf(&tf_data);
+}
+
+void (*vlog_startup_routines[])() = {
+ Leitura_register,
+ 0
+};
+
Index: uart8systemc/trunk/vpi/counter_global.h
===================================================================
--- uart8systemc/trunk/vpi/counter_global.h (nonexistent)
+++ uart8systemc/trunk/vpi/counter_global.h (revision 2)
@@ -0,0 +1,31 @@
+static int global_counter_calltf(char*user_data)
+{
+ vpiHandle i = vpi_handle_by_name("module_tb.i", NULL);
+ vpiHandle READY = vpi_handle_by_name("module_tb.READY", NULL);
+ vpiHandle RESET = vpi_handle_by_name("module_tb.RESET", NULL);
+
+ v_generate.format=vpiIntVal;
+ ready_rx.format =vpiIntVal;
+ reset.format = vpiIntVal;
+
+
+ if(counter > 100)
+ {
+ v_generate.value.integer = 1;
+ vpi_put_value(i, &v_generate, NULL, vpiNoDelay);
+ SC_UART->stop_sim();
+ destroy(SC_UART);
+ }
+
+ vpi_get_value(READY, &ready_rx);
+ vpi_get_value(RESET, &reset);
+
+ if(ready_rx.value.integer == 1 && reset.value.integer == 0)
+ {
+ counter = counter + 1;
+ }
+
+
+ return 0;
+
+}
Index: uart8systemc/trunk/vpi/global_init.h
===================================================================
--- uart8systemc/trunk/vpi/global_init.h (nonexistent)
+++ uart8systemc/trunk/vpi/global_init.h (revision 2)
@@ -0,0 +1,50 @@
+static int global_init_calltf(char*user_data)
+{
+
+ vpiHandle RESET = vpi_handle_by_name("module_tb.RESET", NULL);
+ vpiHandle START = vpi_handle_by_name("module_tb.START", NULL);
+ vpiHandle WORK_FR = vpi_handle_by_name("module_tb.WORK_FR", NULL);
+ vpiHandle RX = vpi_handle_by_name("module_tb.RX", NULL);
+ vpiHandle TX = vpi_handle_by_name("module_tb.TX", NULL);
+
+ reset.format=vpiIntVal;
+ rx_value.format = vpiIntVal;
+ tx_value.format = vpiIntVal;
+
+ reset.value.integer = 1;
+ vpi_put_value(RESET, &reset, NULL, vpiNoDelay);
+ reset.value.integer = 0;
+ vpi_put_value(START, &reset, NULL, vpiNoDelay);
+
+ counter = 0;
+ counter_reset = 0;
+
+ lib_handle = dlopen("./sc_uart.so", RTLD_LAZY);
+
+ if(!lib_handle)
+ {
+ fprintf(stderr, "%s\n", dlerror());
+ }
+
+ create = (Control_SC* (*)())dlsym(lib_handle, "create_object");
+ destroy = (void (*)(Control_SC*))dlsym(lib_handle, "destroy_object");
+
+ SC_UART = (Control_SC*)create();
+ SC_UART->set_baud_rate(115200,50);
+ SC_UART->init();
+
+ reset.value.integer = SC_UART->get_baud_rate();
+ vpi_put_value(WORK_FR, &reset, NULL, vpiNoDelay);
+
+ SC_UART->reset_set_high();
+
+ tx_value.value.integer = SC_UART->read_tx();
+ vpi_put_value(RX, &tx_value, NULL, vpiNoDelay);
+
+ vpi_get_value(TX, &rx_value);
+ SC_UART->write_rx(rx_value.value.integer);
+
+ SC_UART->run_sim();
+
+ return 0;
+}