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https://opencores.org/ocsvn/uart_block/uart_block/trunk
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/uart_block/trunk/hdl/iseProject/serial_receiver.syr
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Release 13.4 - xst O.87xd (nt64) |
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
--> Parameter TMPDIR set to xst/projnav.tmp |
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Total REAL time to Xst completion: 0.00 secs |
Total CPU time to Xst completion: 0.05 secs |
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--> Parameter xsthdpdir set to xst |
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Total REAL time to Xst completion: 0.00 secs |
Total CPU time to Xst completion: 0.05 secs |
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--> Reading design: serial_receiver.prj |
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TABLE OF CONTENTS |
1) Synthesis Options Summary |
2) HDL Compilation |
3) Design Hierarchy Analysis |
4) HDL Analysis |
5) HDL Synthesis |
5.1) HDL Synthesis Report |
6) Advanced HDL Synthesis |
6.1) Advanced HDL Synthesis Report |
7) Low Level Synthesis |
8) Partition Report |
9) Final Report |
9.1) Device utilization summary |
9.2) Partition Resource Summary |
9.3) TIMING REPORT |
|
|
========================================================================= |
* Synthesis Options Summary * |
========================================================================= |
---- Source Parameters |
Input File Name : "serial_receiver.prj" |
Input Format : mixed |
Ignore Synthesis Constraint File : NO |
|
---- Target Parameters |
Output File Name : "serial_receiver" |
Output Format : NGC |
Target Device : xc3s500e-4-fg320 |
|
---- Source Options |
Top Module Name : serial_receiver |
Automatic FSM Extraction : YES |
FSM Encoding Algorithm : Auto |
Safe Implementation : No |
FSM Style : LUT |
RAM Extraction : Yes |
RAM Style : Auto |
ROM Extraction : Yes |
Mux Style : Auto |
Decoder Extraction : YES |
Priority Encoder Extraction : Yes |
Shift Register Extraction : YES |
Logical Shifter Extraction : YES |
XOR Collapsing : YES |
ROM Style : Auto |
Mux Extraction : Yes |
Resource Sharing : YES |
Asynchronous To Synchronous : NO |
Multiplier Style : Auto |
Automatic Register Balancing : No |
|
---- Target Options |
Add IO Buffers : YES |
Global Maximum Fanout : 100000 |
Add Generic Clock Buffer(BUFG) : 24 |
Register Duplication : YES |
Slice Packing : YES |
Optimize Instantiated Primitives : NO |
Use Clock Enable : Yes |
Use Synchronous Set : Yes |
Use Synchronous Reset : Yes |
Pack IO Registers into IOBs : Auto |
Equivalent register Removal : YES |
|
---- General Options |
Optimization Goal : Speed |
Optimization Effort : 1 |
Keep Hierarchy : No |
Netlist Hierarchy : As_Optimized |
RTL Output : Yes |
Global Optimization : AllClockNets |
Read Cores : YES |
Write Timing Constraints : NO |
Cross Clock Analysis : NO |
Hierarchy Separator : / |
Bus Delimiter : <> |
Case Specifier : Maintain |
Slice Utilization Ratio : 100 |
BRAM Utilization Ratio : 100 |
Verilog 2001 : YES |
Auto BRAM Packing : NO |
Slice Utilization Ratio Delta : 5 |
|
========================================================================= |
|
|
========================================================================= |
* HDL Compilation * |
========================================================================= |
Compiling vhdl file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work. |
Architecture pkgdefinitions of Entity pkgdefinitions is up to date. |
Compiling vhdl file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work. |
Entity <serial_receiver> compiled. |
Entity <serial_receiver> (Architecture <behavioral>) compiled. |
|
========================================================================= |
* Design Hierarchy Analysis * |
========================================================================= |
Analyzing hierarchy for entity <serial_receiver> in library <work> (architecture <behavioral>). |
|
|
========================================================================= |
* HDL Analysis * |
========================================================================= |
Analyzing Entity <serial_receiver> in library <work> (Architecture <behavioral>). |
WARNING:Xst:819 - "E:/uart_block/hdl/iseProject/serial_receiver.vhd" line 76: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: |
<serial_in> |
Entity <serial_receiver> analyzed. Unit <serial_receiver> generated. |
|
|
========================================================================= |
* HDL Synthesis * |
========================================================================= |
|
Performing bidirectional port resolution... |
|
Synthesizing Unit <serial_receiver>. |
Related source file is "E:/uart_block/hdl/iseProject/serial_receiver.vhd". |
Found finite state machine <FSM_0> for signal <current_s>. |
----------------------------------------------------------------------- |
| States | 10 | |
| Transitions | 10 | |
| Inputs | 0 | |
| Outputs | 9 | |
| Clock | baudClk (rising_edge) | |
| Reset | syncDetected (negative) | |
| Reset type | asynchronous | |
| Reset State | rx_idle | |
| Power Up State | rx_idle | |
| Encoding | automatic | |
| Implementation | LUT | |
----------------------------------------------------------------------- |
Found finite state machine <FSM_1> for signal <filterRx>. |
----------------------------------------------------------------------- |
| States | 3 | |
| Transitions | 5 | |
| Inputs | 1 | |
| Outputs | 3 | |
| Clock | baudOverSampleClk (rising_edge) | |
| Reset | rst (positive) | |
| Reset type | asynchronous | |
| Reset State | s0 | |
| Power Up State | s0 | |
| Encoding | automatic | |
| Implementation | LUT | |
----------------------------------------------------------------------- |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. |
Found 1-bit register for signal <syncDetected>. |
Summary: |
inferred 2 Finite State Machine(s). |
inferred 1 D-type flip-flop(s). |
Unit <serial_receiver> synthesized. |
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|
========================================================================= |
HDL Synthesis Report |
|
Macro Statistics |
# Registers : 1 |
1-bit register : 1 |
# Latches : 8 |
1-bit latch : 8 |
|
========================================================================= |
|
========================================================================= |
* Advanced HDL Synthesis * |
========================================================================= |
|
Analyzing FSM <FSM_1> for best encoding. |
Optimizing FSM <filterRx/FSM> on signal <filterRx[1:2]> with gray encoding. |
------------------- |
State | Encoding |
------------------- |
s0 | 00 |
s1 | 01 |
s2 | 11 |
------------------- |
Analyzing FSM <FSM_0> for best encoding. |
Optimizing FSM <current_s/FSM> on signal <current_s[1:10]> with one-hot encoding. |
----------------------- |
State | Encoding |
----------------------- |
rx_idle | 0000000001 |
bit0 | 0000000010 |
bit1 | 0000000100 |
bit2 | 0000001000 |
bit3 | 0000010000 |
bit4 | 0000100000 |
bit5 | 0001000000 |
bit6 | 0010000000 |
bit7 | 0100000000 |
rx_stop | 1000000000 |
----------------------- |
|
========================================================================= |
Advanced HDL Synthesis Report |
|
Macro Statistics |
# FSMs : 2 |
# Registers : 1 |
Flip-Flops : 1 |
# Latches : 8 |
1-bit latch : 8 |
|
========================================================================= |
|
========================================================================= |
* Low Level Synthesis * |
========================================================================= |
|
Optimizing unit <serial_receiver> ... |
|
Mapping all equations... |
Building and optimizing final netlist ... |
Found area constraint ratio of 100 (+ 5) on block serial_receiver, actual ratio is 0. |
|
Final Macro Processing ... |
|
========================================================================= |
Final Register Report |
|
Macro Statistics |
# Registers : 13 |
Flip-Flops : 13 |
|
========================================================================= |
|
========================================================================= |
* Partition Report * |
========================================================================= |
|
Partition Implementation Status |
------------------------------- |
|
No Partitions were found in this design. |
|
------------------------------- |
|
========================================================================= |
* Final Report * |
========================================================================= |
Final Results |
RTL Top Level Output File Name : serial_receiver.ngr |
Top Level Output File Name : serial_receiver |
Output Format : NGC |
Optimization Goal : Speed |
Keep Hierarchy : No |
|
Design Statistics |
# IOs : 13 |
|
Cell Usage : |
# BELS : 4 |
# INV : 1 |
# LUT2 : 2 |
# LUT3 : 1 |
# FlipFlops/Latches : 21 |
# FDC : 12 |
# FDP : 1 |
# LD : 8 |
# Clock Buffers : 2 |
# BUFGP : 2 |
# IO Buffers : 11 |
# IBUF : 2 |
# OBUF : 9 |
========================================================================= |
|
Device utilization summary: |
--------------------------- |
|
Selected Device : 3s500efg320-4 |
|
Number of Slices: 7 out of 4656 0% |
Number of Slice Flip Flops: 13 out of 9312 0% |
Number of 4 input LUTs: 4 out of 9312 0% |
Number of IOs: 13 |
Number of bonded IOBs: 13 out of 232 5% |
IOB Flip Flops: 8 |
Number of GCLKs: 2 out of 24 8% |
|
--------------------------- |
Partition Resource Summary: |
--------------------------- |
|
No Partitions were found in this design. |
|
--------------------------- |
|
|
========================================================================= |
TIMING REPORT |
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. |
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT |
GENERATED AFTER PLACE-and-ROUTE. |
|
Clock Information: |
------------------ |
-----------------------------------+------------------------+-------+ |
Clock Signal | Clock buffer(FF name) | Load | |
-----------------------------------+------------------------+-------+ |
baudOverSampleClk | BUFGP | 3 | |
current_s_FSM_FFd2 | NONE(data_byte_7) | 1 | |
current_s_FSM_FFd3 | NONE(data_byte_6) | 1 | |
current_s_FSM_FFd4 | NONE(data_byte_5) | 1 | |
current_s_FSM_FFd5 | NONE(data_byte_4) | 1 | |
current_s_FSM_FFd6 | NONE(data_byte_3) | 1 | |
current_s_FSM_FFd7 | NONE(data_byte_2) | 1 | |
current_s_FSM_FFd8 | NONE(data_byte_1) | 1 | |
current_s_FSM_FFd9 | NONE(data_byte_0) | 1 | |
baudClk | BUFGP | 10 | |
-----------------------------------+------------------------+-------+ |
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. |
|
Asynchronous Control Signals Information: |
---------------------------------------- |
---------------------------------------------------------------+-------------------------+-------+ |
Control Signal | Buffer(FF name) | Load | |
---------------------------------------------------------------+-------------------------+-------+ |
current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)| NONE(current_s_FSM_FFd1)| 10 | |
rst | IBUF | 3 | |
---------------------------------------------------------------+-------------------------+-------+ |
|
Timing Summary: |
--------------- |
Speed Grade: -4 |
|
Minimum period: 2.213ns (Maximum Frequency: 451.875MHz) |
Minimum input arrival time before clock: 3.338ns |
Maximum output required time after clock: 4.368ns |
Maximum combinational path delay: No path found |
|
Timing Detail: |
-------------- |
All values displayed in nanoseconds (ns) |
|
========================================================================= |
Timing constraint: Default period analysis for Clock 'baudOverSampleClk' |
Clock period: 2.213ns (frequency: 451.875MHz) |
Total number of paths / destination ports: 4 / 3 |
------------------------------------------------------------------------- |
Delay: 2.213ns (Levels of Logic = 1) |
Source: filterRx_FSM_FFd1 (FF) |
Destination: syncDetected (FF) |
Source Clock: baudOverSampleClk rising |
Destination Clock: baudOverSampleClk rising |
|
Data Path: filterRx_FSM_FFd1 to syncDetected |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDC:C->Q 3 0.591 0.610 filterRx_FSM_FFd1 (filterRx_FSM_FFd1) |
LUT2:I1->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In) |
FDC:D 0.308 filterRx_FSM_FFd2 |
---------------------------------------- |
Total 2.213ns (1.603ns logic, 0.610ns route) |
(72.4% logic, 27.6% route) |
|
========================================================================= |
Timing constraint: Default period analysis for Clock 'baudClk' |
Clock period: 1.346ns (frequency: 742.942MHz) |
Total number of paths / destination ports: 10 / 10 |
------------------------------------------------------------------------- |
Delay: 1.346ns (Levels of Logic = 0) |
Source: current_s_FSM_FFd1 (FF) |
Destination: current_s_FSM_FFd10 (FF) |
Source Clock: baudClk rising |
Destination Clock: baudClk rising |
|
Data Path: current_s_FSM_FFd1 to current_s_FSM_FFd10 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDC:C->Q 2 0.591 0.447 current_s_FSM_FFd1 (current_s_FSM_FFd1) |
FDP:D 0.308 current_s_FSM_FFd10 |
---------------------------------------- |
Total 1.346ns (0.899ns logic, 0.447ns route) |
(66.8% logic, 33.2% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk' |
Total number of paths / destination ports: 3 / 3 |
------------------------------------------------------------------------- |
Offset: 3.338ns (Levels of Logic = 2) |
Source: serial_in (PAD) |
Destination: syncDetected (FF) |
Destination Clock: baudOverSampleClk rising |
|
Data Path: serial_in to syncDetected |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 1.108 serial_in_IBUF (serial_in_IBUF) |
LUT2:I0->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In) |
FDC:D 0.308 filterRx_FSM_FFd2 |
---------------------------------------- |
Total 3.338ns (2.230ns logic, 1.108ns route) |
(66.8% logic, 33.2% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd2' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_7 (LATCH) |
Destination Clock: current_s_FSM_FFd2 falling |
|
Data Path: serial_in to data_byte_7 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_7 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd3' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_6 (LATCH) |
Destination Clock: current_s_FSM_FFd3 falling |
|
Data Path: serial_in to data_byte_6 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_6 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd4' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_5 (LATCH) |
Destination Clock: current_s_FSM_FFd4 falling |
|
Data Path: serial_in to data_byte_5 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_5 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd5' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_4 (LATCH) |
Destination Clock: current_s_FSM_FFd5 falling |
|
Data Path: serial_in to data_byte_4 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_4 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd6' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_3 (LATCH) |
Destination Clock: current_s_FSM_FFd6 falling |
|
Data Path: serial_in to data_byte_3 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_3 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd7' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_2 (LATCH) |
Destination Clock: current_s_FSM_FFd7 falling |
|
Data Path: serial_in to data_byte_2 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_2 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd8' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_1 (LATCH) |
Destination Clock: current_s_FSM_FFd8 falling |
|
Data Path: serial_in to data_byte_1 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_1 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd9' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 2.459ns (Levels of Logic = 1) |
Source: serial_in (PAD) |
Destination: data_byte_0 (LATCH) |
Destination Clock: current_s_FSM_FFd9 falling |
|
Data Path: serial_in to data_byte_0 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF) |
LD:D 0.308 data_byte_0 |
---------------------------------------- |
Total 2.459ns (1.526ns logic, 0.933ns route) |
(62.1% logic, 37.9% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.310ns (Levels of Logic = 1) |
Source: current_s_FSM_FFd1 (FF) |
Destination: data_ready (PAD) |
Source Clock: baudClk rising |
|
Data Path: current_s_FSM_FFd1 to data_ready |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDC:C->Q 2 0.591 0.447 current_s_FSM_FFd1 (current_s_FSM_FFd1) |
OBUF:I->O 3.272 data_ready_OBUF (data_ready) |
---------------------------------------- |
Total 4.310ns (3.863ns logic, 0.447ns route) |
(89.6% logic, 10.4% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd2' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_7 (LATCH) |
Destination: data_byte<7> (PAD) |
Source Clock: current_s_FSM_FFd2 falling |
|
Data Path: data_byte_7 to data_byte<7> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_7 (data_byte_7) |
OBUF:I->O 3.272 data_byte_7_OBUF (data_byte<7>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd3' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_6 (LATCH) |
Destination: data_byte<6> (PAD) |
Source Clock: current_s_FSM_FFd3 falling |
|
Data Path: data_byte_6 to data_byte<6> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_6 (data_byte_6) |
OBUF:I->O 3.272 data_byte_6_OBUF (data_byte<6>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd4' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_5 (LATCH) |
Destination: data_byte<5> (PAD) |
Source Clock: current_s_FSM_FFd4 falling |
|
Data Path: data_byte_5 to data_byte<5> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_5 (data_byte_5) |
OBUF:I->O 3.272 data_byte_5_OBUF (data_byte<5>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd5' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_4 (LATCH) |
Destination: data_byte<4> (PAD) |
Source Clock: current_s_FSM_FFd5 falling |
|
Data Path: data_byte_4 to data_byte<4> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_4 (data_byte_4) |
OBUF:I->O 3.272 data_byte_4_OBUF (data_byte<4>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd6' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_3 (LATCH) |
Destination: data_byte<3> (PAD) |
Source Clock: current_s_FSM_FFd6 falling |
|
Data Path: data_byte_3 to data_byte<3> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_3 (data_byte_3) |
OBUF:I->O 3.272 data_byte_3_OBUF (data_byte<3>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd7' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_2 (LATCH) |
Destination: data_byte<2> (PAD) |
Source Clock: current_s_FSM_FFd7 falling |
|
Data Path: data_byte_2 to data_byte<2> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_2 (data_byte_2) |
OBUF:I->O 3.272 data_byte_2_OBUF (data_byte<2>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd8' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_1 (LATCH) |
Destination: data_byte<1> (PAD) |
Source Clock: current_s_FSM_FFd8 falling |
|
Data Path: data_byte_1 to data_byte<1> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_1 (data_byte_1) |
OBUF:I->O 3.272 data_byte_1_OBUF (data_byte<1>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd9' |
Total number of paths / destination ports: 1 / 1 |
------------------------------------------------------------------------- |
Offset: 4.368ns (Levels of Logic = 1) |
Source: data_byte_0 (LATCH) |
Destination: data_byte<0> (PAD) |
Source Clock: current_s_FSM_FFd9 falling |
|
Data Path: data_byte_0 to data_byte<0> |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
LD:G->Q 1 0.676 0.420 data_byte_0 (data_byte_0) |
OBUF:I->O 3.272 data_byte_0_OBUF (data_byte<0>) |
---------------------------------------- |
Total 4.368ns (3.948ns logic, 0.420ns route) |
(90.4% logic, 9.6% route) |
|
========================================================================= |
|
|
Total REAL time to Xst completion: 3.00 secs |
Total CPU time to Xst completion: 3.17 secs |
|
--> |
|
Total memory usage is 257012 kilobytes |
|
Number of errors : 0 ( 0 filtered) |
Number of warnings : 9 ( 0 filtered) |
Number of infos : 1 ( 0 filtered) |
|
/uart_block/trunk/hdl/iseProject/serial_receiver.xst
0,0 → 1,56
set -tmpdir "xst/projnav.tmp" |
set -xsthdpdir "xst" |
run |
-ifn serial_receiver.prj |
-ifmt mixed |
-ofn serial_receiver |
-ofmt NGC |
-p xc3s500e-4-fg320 |
-top serial_receiver |
-opt_mode Speed |
-opt_level 1 |
-iuc NO |
-keep_hierarchy No |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-verilog2001 YES |
-fsm_extract YES -fsm_encoding Auto |
-safe_implementation No |
-fsm_style LUT |
-ram_extract Yes |
-ram_style Auto |
-rom_extract Yes |
-mux_style Auto |
-decoder_extract YES |
-priority_extract Yes |
-shreg_extract YES |
-shift_extract YES |
-xor_collapse YES |
-rom_style Auto |
-auto_bram_packing NO |
-mux_extract Yes |
-resource_sharing YES |
-async_to_sync NO |
-mult_style Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 24 |
-register_duplication YES |
-register_balancing No |
-slice_packing YES |
-optimize_primitives NO |
-use_clock_enable Yes |
-use_sync_set Yes |
-use_sync_reset Yes |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
/uart_block/trunk/hdl/iseProject/serial_transmitter.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6e |
$74x5>6638;=754FNQWW>agsiVhrxh28:1<6?GSAOY20NX]PIODL5>E53JO87NB]9:ALIHOS\LN<7N\JAUGG5>B63L>0J5673:DGG1=ALJO87KJ_4:DEAD2<NOLN=6I<;FLG5>O53@:97D?=;H01?L533@H^J45FNHVPPDRB?2FDKDMNL59OQQ433E__8?5A029M444<F8=0BHZXOSI2?J><G'2<tiQC4:MAQC7<X=1[M_Zn;QKM[GSTAMRi7]GA_CWPJDKB;2ZYI<5^6:QLQWEB<2^R\Hm4URGQ[SOTAKFN?6XLC89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6V\TMKA3>^T\VMEH:5WSU]UGF0<PmhTEi??;Yfn[Hgmg{\n~~g`n028\akXE`dd~[k}shmm7>^t|>1imxjLljf8fdscKeaTNXHHP008gptumg~TRH\M^DE`4743jy~h`{_r]EWHYANm;;=>5luspfjqYtWOYFSKHk1030?fsuzldS~QISL]EBa759;1hy|jnu]p[CUJWOLo><<4ctpqakrX{VLXARHId231?fsuzldS~QISL]EBa26:2i~~kat^q\BVKXNOn>=?5luspfjqYtWOYFSKHk6008gptumg~TRH\M^DE`2753jy~h`{_r]EWHYANm2:>6mzrsgmpZuXNZGTJKj6159`qwtbf}UxSK]B_Nww577d3mkmRlvtd>3:f=ci}kTntzj<0<`?agsiVhrxh2=>b9geqgXjp~n0>0l;ecweZd~|l6?2n5kauc\f|rb4<4h7io{a^`zp`:16l1omyoPbxvf82<76j1omyoPbxvf828682njxlQmyug\4ZOE]O;;7io{a^`zp`Y6W@H^J<>4d`vb[gsmV8TEO[I119geqgXjp~nS>QFBTD24>bf|hUiuykP4^KAQC773mkmRlvtd]6[LDRN8:0hlzn_c{waZ0XAK_M==5kauc\f|rbW>UBNXH6;ecweZubf}o0hlzn_rgmpZIE]O90~~z7;sqw[LDRNh1xignl^mvpf=tm{cj`Razt00`?vcuahfTcxz<3b9pawofdVe~x>6m;rgqmdjXg|~?o6}jrhco[jss<1;;7~k}i`n\kpr30VY\<k5|eskbhZir|VEIYK?=;rgqmdjX|{ke`g{tdp24>~d;z?;<h#;-ge065{GHyl<7MNw658E>7<6sZ31?:4=3;307551=3;=jn=tn2795>h4>3<0(>:5319~W=<4?3886<=<0246>40ak<1o:94?:082V?=;>09?7?<31151?71nj90zY<m:182>4<5jrY26>9522827664><0::km<;%0e>4d<,;<1:85m6583>f<5938iwE<k;%0`>32<R=0:w?4ri2:94?=n=h0;66a:c;29?j3?2900e9h50;&1<?2b3g8<6=54i5f94?"503>n7c<8:098m1e=83.947:j;o04>7=<a=h1<7*=8;6f?k402:10e9o50;&1<?2b3g8<6954i5;94?"503>n7c<8:498m1>=83.947:j;o04>3=<a==1<7*=8;6f?k402>10n><50;394?6|,;i1=>5G309K6a=h9;0;66sm3283>4<729q/>n4=e:J05>N5l2e997>5;|`0`?6=<3:1<v*=c;d8L67<@;n0(<o51:k6>5<<ah0;66g=9;29?j4f2900qo=l:187>5<7s-8h6i5G309K6a=#9h0;7d;50;9j3?6=3`k1<75`2`83>>{e;k0;694?:1y'6f<c3A9:7E<k;%3b>5=n=3:17d950;9je?6=3f8j6=44}c66>5<3290;w)<l:e9K74=O:m1/=l4?;h794?=n?3:17do50;9l6d<722wi894?:583>5}#:j0o7E=>;I0g?!7f291b97>5;h594?=ni3:17b<n:188yg24290?6=4?{%0`>a=O;81C>i5+1`83?l3=831b;7>5;hc94?=h:h0;66sm4383>1<729q/>n4k;I12?M4c3-;j6=5f5;29?l1=831bm7>5;n0b>5<<uk>:6=4;:183!4d2m1C?<5G2e9'5d<73`?1<75f7;29?lg=831d>l4?::a05<72=0;6=u+2b8g?M563A8o7)?n:19j1?6=3`=1<75fa;29?j4f2900qo=i:187>5<7s-8h6i5G309K6a=#9h0;7d;50;9j3?6=3`k1<75`2`83>>{e;l0;694?:1y'6f<c3A9:7E<k;%3b>5=n=3:17d950;9je?6=3f8j6=44}c65>5<4290;w)<l:0a8L67<@;n0(<o5b:k21?6=3`;=6=44o3094?=zj?:1<7;50;2x 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|
/uart_block/trunk/hdl/iseProject/isim.log
0,0 → 1,19
ISim log file |
Running: E:\uart_block\hdl\iseProject\testSerial_receiver_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 us |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testSerial_receiver.vhd:stim_proc |
|
INFO: Simulator is stopped. |
/uart_block/trunk/hdl/iseProject/serial_transmitter_vhdl.prj
0,0 → 1,2
vhdl work "E:\uart_block\hdl\iseProject\pkgDefinitions.vhd" |
vhdl work "E:\uart_block\hdl\iseProject\serial_transmitter.vhd" |
/uart_block/trunk/hdl/iseProject/testSerial_receiver.vhd
0,0 → 1,112
--! Test serial_receiver module |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
--! Use CPU Definitions package |
use work.pkgDefinitions.all; |
|
ENTITY testSerial_receiver IS |
END testSerial_receiver; |
|
ARCHITECTURE behavior OF testSerial_receiver IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT serial_receiver |
PORT( |
rst : IN std_logic; |
baudClk : IN std_logic; |
baudOverSampleClk : IN std_logic; |
serial_in : IN std_logic; |
data_ready : OUT std_logic; |
data_byte : OUT std_logic_vector((nBits-1) downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal rst : std_logic := '0'; |
signal baudClk : std_logic := '0'; |
signal baudOverSampleClk : std_logic := '0'; |
signal serial_in : std_logic := '0'; |
|
--Outputs |
signal data_ready : std_logic; |
signal data_byte : std_logic_vector((nBits-1) downto 0); |
|
-- Clock period definitions |
constant baudClk_period : time := 8.6805 us; |
constant baudOverSampleClk_period : time := 1 us; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: serial_receiver PORT MAP ( |
rst => rst, |
baudClk => baudClk, |
baudOverSampleClk => baudOverSampleClk, |
serial_in => serial_in, |
data_ready => data_ready, |
data_byte => data_byte |
); |
|
-- Clock process definitions |
baudClk_process :process |
begin |
baudClk <= '0'; |
wait for baudClk_period/2; |
baudClk <= '1'; |
wait for baudClk_period/2; |
end process; |
|
baudOverSampleClk_process :process |
begin |
baudOverSampleClk <= '0'; |
wait for baudOverSampleClk_period/2; |
baudOverSampleClk <= '1'; |
wait for baudOverSampleClk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
rst <= '1'; |
serial_in <= '1'; -- Idle |
wait for 3 us; |
rst <= '0'; |
wait for baudClk_period * 3; |
|
-- Receive 0xC4 value (11000100) |
-- Start bit here |
serial_in <= '0'; |
wait for baudClk_period; |
|
serial_in <= '0'; |
wait for baudClk_period; |
serial_in <= '0'; |
wait for baudClk_period; |
serial_in <= '1'; |
wait for baudClk_period; |
serial_in <= '0'; |
wait for baudClk_period; |
serial_in <= '0'; |
wait for baudClk_period; |
serial_in <= '0'; |
wait for baudClk_period; |
serial_in <= '1'; |
wait for baudClk_period; |
serial_in <= '1'; |
wait for baudClk_period; |
|
-- Stop bit here |
serial_in <= '1'; |
wait for baudClk_period * 3; |
|
-- Stop Simulation |
assert false report "NONE. End of simulation." severity failure; |
|
wait; |
end process; |
|
END; |
/uart_block/trunk/hdl/iseProject/serial_receiver_summary.html
0,0 → 1,113
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>serial_receiver Project Status (04/21/2012 - 12:13:10)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>iseProject.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>serial_receiver</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc3s500e-4fg320</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='E:/uart_block/hdl/iseProject\_xmsgs/*.xmsgs?&DataKey=Warning'>9 Warnings (8 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='E:/uart_block/hdl/iseProject\serial_receiver_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slices</TD> |
<TD ALIGN=RIGHT>7</TD> |
<TD ALIGN=RIGHT>4656</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD> |
<TD ALIGN=RIGHT>13</TD> |
<TD ALIGN=RIGHT>9312</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>9312</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>13</TD> |
<TD ALIGN=RIGHT>232</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>5%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GCLKs</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>24</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>8%</TD> |
</TR> |
</TABLE> |
|
|
|
|
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
|
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
|
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 04/21/2012 - 12:13:10</center> |
</BODY></HTML> |
/uart_block/trunk/hdl/iseProject/serial_receiver.vhd
0,0 → 1,132
--! Data receiver |
--! http://www.fpga4fun.com/SerialInterface.html |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
--! Use CPU Definitions package |
use work.pkgDefinitions.all; |
|
entity serial_receiver is |
Port ( |
rst : in STD_LOGIC; |
baudClk : in STD_LOGIC; |
baudOverSampleClk : in STD_LOGIC; |
serial_in : in STD_LOGIC; |
data_ready : out STD_LOGIC; |
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); |
end serial_receiver; |
|
architecture Behavioral of serial_receiver is |
signal current_s,next_s: rxStates; |
signal filterRx : rxFilterStates; |
signal syncDetected : std_logic; |
|
begin |
-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC |
process (rst, baudOverSampleClk, serial_in) |
begin |
if rst = '1' then |
filterRx <= s0; |
syncDetected <= '0'; |
elsif rising_edge(baudOverSampleClk) then |
case filterRx is |
when s0 => |
syncDetected <= '0'; |
-- Spike down detected, verify if it's valid for at least 3 cycles |
if serial_in = '0' then |
filterRx <= s1; |
else |
filterRx <= s0; |
end if; |
|
when s1 => |
syncDetected <= '0'; |
if serial_in = '0' then |
filterRx <= s2; |
syncDetected <= '0'; |
else |
filterRx <= s0; |
end if; |
|
when s2 => |
-- Real Beginning of start bit detected |
if serial_in = '0' then |
filterRx <= s2; |
syncDetected <= '0'; |
else |
-- Start bit end detected |
filterRx <= s2; |
syncDetected <= '1'; |
end if; |
end case; |
end if; |
end process; |
|
-- Next state logic for rx Receiver (On this case our reset is the syncDetected signal |
process (syncDetected, baudClk, serial_in) |
begin |
if syncDetected = '0' then |
current_s <= rx_idle; |
elsif rising_edge(baudClk) then |
current_s <= next_s; |
end if; |
end process; |
|
-- Process to handle the serial receive |
process (current_s) |
begin |
case current_s is |
when rx_idle => |
data_ready <= '0'; |
--data_byte <= (others => 'Z'); |
next_s <= bit0; |
|
when bit0 => |
data_ready <= '0'; |
data_byte(0) <= serial_in; |
next_s <= bit1; |
|
when bit1 => |
data_ready <= '0'; |
data_byte(1) <= serial_in; |
next_s <= bit2; |
|
when bit2 => |
data_ready <= '0'; |
data_byte(2) <= serial_in; |
next_s <= bit3; |
|
when bit3 => |
data_ready <= '0'; |
data_byte(3) <= serial_in; |
next_s <= bit4; |
|
when bit4 => |
data_ready <= '0'; |
data_byte(4) <= serial_in; |
next_s <= bit5; |
|
when bit5 => |
data_ready <= '0'; |
data_byte(5) <= serial_in; |
next_s <= bit6; |
|
when bit6 => |
data_ready <= '0'; |
data_byte(6) <= serial_in; |
next_s <= bit7; |
|
when bit7 => |
data_ready <= '0'; |
data_byte(7) <= serial_in; |
next_s <= rx_stop; |
|
when rx_stop => |
data_ready <= '1'; |
next_s <= rx_idle; |
|
end case; |
end process; |
|
end Behavioral; |
|
/uart_block/trunk/hdl/iseProject/fuseRelaunch.cmd
0,0 → 1,132
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "work.testSerial_receiver" |
/uart_block/trunk/hdl/iseProject/serial_transmitter.stx
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
uart_block/trunk/hdl/iseProject/testSerial_transmitter_isim_beh.exe
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/serial_receiver.prj
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_receiver.prj (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_receiver.prj (revision 2)
@@ -0,0 +1,2 @@
+vhdl work "pkgDefinitions.vhd"
+vhdl work "serial_receiver.vhd"
Index: uart_block/trunk/hdl/iseProject/serial_receiver_xst.xrpt
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_receiver_xst.xrpt (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_receiver_xst.xrpt (revision 2)
@@ -0,0 +1,182 @@
+
+
+
+
+
+
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+
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+ -
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Index: uart_block/trunk/hdl/iseProject/pkgDefinitions.vhd
===================================================================
--- uart_block/trunk/hdl/iseProject/pkgDefinitions.vhd (nonexistent)
+++ uart_block/trunk/hdl/iseProject/pkgDefinitions.vhd (revision 2)
@@ -0,0 +1,30 @@
+--! @file
+--! @brief Global definitions
+
+--! @mainpage
+--!
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
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Index: uart_block/trunk/hdl/iseProject/serial_receiver_envsettings.html
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_receiver_envsettings.html (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_receiver_envsettings.html (revision 2)
@@ -0,0 +1,389 @@
+Xilinx System Settings Report
+
+System Settings
+ +
+
+
+
+
+
+
+
+
\ No newline at end of file
Index: uart_block/trunk/hdl/iseProject/serial_transmitter.ngr
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_transmitter.ngr (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_transmitter.ngr (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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+
+
+
+
+
+
+
+ 2
+ /serial_transmitter - Behavioral E:|uart_block|hdl|iseProject|serial_transmitter.vhd
+
+
+ 2
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000e6000000020000000100000000000000000200000064ffffffff000000810000000300000002000000e60000000100000003000000000000000100000003
+ true
+
+
+
+
+ 1
+ Configure Target Device
+ Design Utilities
+ Implement Design
+ User Constraints
+
+
+
+
+ 0
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
+ false
+
+
+
+
+ 1
+
+
+ 0
+ 0
+ 000000ff00000000000000010000000000000000010000000000000000000000000000000000000157000000040101000100000000000000000000000064ffffffff000000810000000000000004000000690000000100000000000000240000000100000000000000660000000100000000000000640000000100000000
+ false
+
+
+
+
+ 1
+
+
+ 0
+ 0
+ 000000ff000000000000000100000000000000000100000000000000000000000000000000000000f6000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
+ false
+ work
+
+
+
+ 1
+ Configure Target Device
+ Design Utilities
+ Implement Design
+ User Constraints
+
+
+ View RTL Schematic
+
+ 0
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
+ false
+ View RTL Schematic
+
+
+
+ 2
+
+
+ serial_transmitter - Behavioral (E:/uart_block/hdl/iseProject/serial_transmitter.vhd)
+
+ 0
+ 0
+ 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000147000000020000000000000000000000000200000064ffffffff000000810000000300000002000001470000000100000003000000000000000100000003
+ false
+ serial_transmitter - Behavioral (E:/uart_block/hdl/iseProject/serial_transmitter.vhd)
+
+
+
+ 1
+ Design Utilities
+
+
+
+
+ 0
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
+ false
+
+
+
+
+ 1
+
+
+ ISim Simulator
+
+ 0
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
+ false
+ ISim Simulator
+
+ 000000ff00000000000000020000011b0000011b01000000040100000002
+ Implementation
+
+
+ 1
+
+
+
+
+ 0
+ 0
+ 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
+ false
+
+
+
Index: uart_block/trunk/hdl/iseProject/iseconfig/serial_receiver.xreport
===================================================================
--- uart_block/trunk/hdl/iseProject/iseconfig/serial_receiver.xreport (nonexistent)
+++ uart_block/trunk/hdl/iseProject/iseconfig/serial_receiver.xreport (revision 2)
@@ -0,0 +1,215 @@
+
+
+
+ 2012-04-21T11:42:00
+ serial_receiver
+ 2012-04-21T11:41:51
+ E:/uart_block/hdl/iseProject/iseconfig/serial_receiver.xreport
+ E:/uart_block/hdl/iseProject
+ 2012-04-21T11:41:59
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
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+
+
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+
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+
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+
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+
+
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+
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+
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+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: uart_block/trunk/hdl/iseProject/iseconfig/serial_transmitter.xreport
===================================================================
--- uart_block/trunk/hdl/iseProject/iseconfig/serial_transmitter.xreport (nonexistent)
+++ uart_block/trunk/hdl/iseProject/iseconfig/serial_transmitter.xreport (revision 2)
@@ -0,0 +1,215 @@
+
+
+
+ 2012-04-21T00:50:59
+ serial_transmitter
+ Unknown
+ E:/uart_block/hdl/iseProject/iseconfig/serial_transmitter.xreport
+ E:/uart_block/hdl/iseProject
+ 2012-04-20T23:52:34
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
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+
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+
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+
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+
+
+
+
+
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+
+
+
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+
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+
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+
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+
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+
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+
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+
+
+
+
Index: uart_block/trunk/hdl/iseProject/serial_transmitter.lso
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_transmitter.lso (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_transmitter.lso (revision 2)
@@ -0,0 +1 @@
+work
Index: uart_block/trunk/hdl/iseProject/serial_receiver.ngc
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_receiver.ngc (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_receiver.ngc (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$7;x5>6638;04<948;MVPUSS2mkmRlvtd>4>5823K_MK]64BTQ\MK@H92I87NB]9:ALIHOS\LN<7N\JAUGG5>B53O>87KJL3:DGT4=@92C97D>=;H31?L433@H^J45FNHVPPDRB;2CEZ>5FOC08HA1I?3F$3;ujPL59LFP@33YKYXl5_IO]AQVOCPk1[ECQMURLBI@5erz{oexR}PFRO\EfusWOYFSd`y1^KMRZ66:2i~~kat^q\BVKXNOn:=>5luspfjqYtWOYFSKHk1131?fsuzldS~QISL]EBa46:2i~~kat^q\BVKXNOn8=?5luspfjqYtWOYFSKHk4008gptumg~TRH\M^DE`0753jy~h`{_r]EWHYANm<:>6mzrsgmpZuXNZGTJKj8139`qwtbf}UxSK]B_GDg<44bf|hUiuyk33?a8`drfWksi1:1c:fbpdYeq}o793m4d`vb[gsm5<5i6jnt`]a}qc;?3:5o6jnt`]a}qc;?7h0hlzn_c{waZ6682njxlQmyug\4ZIE]Oh0hlzn_c{waZ7682njxlQmyug\5ZIE]Oh0hlzn_c{waZ4682njxlQmyug\6ZIE]Oh0hlzn_c{waZ5682njxlQmyug\7ZIE]Oh0hlzn_c{waZ2682njxlQmyug\0ZIE]Oh0hlzn_c{waZ3682njxlQmyug\1ZIE]Oh0hlzn_c{waZ0682njxlQmyug\2ZIE]Oh0hlzn_c{waZ1682njxlQmyug\3ZIE]Ok0hlzn_sgb`|`5}su:8vvrXAK_M56}jrhco[lhb3zoyelbPio]JFP@a3zoyelbPrdafmscuk2yrbnJjtdawaa733zseoIk{ebvf`Zkrp9:;=<;4sxl`@`rbk}ooS`{w012251=sz|o:<6vl3r734`+3%om8>=sO@q335>FGp?91J7<51zQ:>7b=9m0:?>><64828c`b?sR5<3:1=7?52`yP=?4c28n1=>=?37795=dei2.9;7?7;%3e>3>2.9978<;[795~5=u`8n6=44i4d94?=h=>0;66g91;29?l572900c9850;&15?223g8;6=54o5694?"593>>7c7=>7c3=10n;:50;694?6|,;?1o6F=9:J12>o12900e:4?::kb>5<5<50z&11?703A827E<9;%35>315;|`7b?6=;3:13A8=7)?9:758md<722cn6=44o3194?=zj=n1<7=50;2x 73=9>1C>45G279'53<1?2cj6=44id83>>i5;3:17pl;b;297?6=8r.997?8;I0:?M413-;=6;94i`83>>ob2900c?=50;9~f1?=8391<7>t$37952=O:01C>;5+17853>of2900eh4?::m17?6=3th?;7>53;294~"5=3;<7E<6;I05?!712?=0el4?::kf>5<N5>2.:87>4i783>>o02900el4?::m17?6=3th>o7>54;294~"5=3i0D?74H348 42=82c=6=44i683>>of2900c?=50;9~f63=83>1<7>t$379`>N512B9:6*>4;38m3<722cj6=44i3094?=h::0;66sm3e83>1<729q/>84l;I0:?M413-;?6=5f6;29?l1=831bm7>5;n00>5<45G279'51<73`<1<75f7;29?lg=831d>>4?::a7g<72=0;6=u+248`?M4>3A8=7)?;:19j2?6=3`=1<75fa;29?j442900qo=n:187>5<7s-8>6n5G289K63=#9=0;7d850;9j3?6=3`k1<75`2283>>{e;00;694?:1y'605=n>3:17d950;9je?6=3f886=44}c1;>5<3290;w)<::b9K6<=O:?1/=94?;h494?=n?3:17do50;9l66<722wi?:4?:583>5}#:<0h7E<6;I05?!73291b:7>5;h594?=ni3:17b<<:188yg51290?6=4?{%06>f=O:01C>;5+1583?l0=831b;7>5;hc94?=h::0;66sm3583>1<729q/>84l;I0:?M413-;?6=5f6;29?l1=831bm7>5;n00>5<5;h32>5<5<>{e=k0;694?:1y'60<6i2B956F=6:&20?d>o6:3:17b?l:188yg0729096=4?{%06>45<@;30D?84ig83>>i6k3:17pl92;296?6=8r.997?<;I0:?M413`l1<75`1b83>>{e=10;6?4?:1y'60<6m2B956F=6:ke>5<5;n3`>5<5;|`66?6=:3:13A8=7dh50;9l5f<722wi9=4?:383>5}#:<0:i6F=9:J12>oa2900ct$3795`=O:01C>;5ff;29?j7d2900qo:l:181>5<7s-8>6c;29?xd3i3:1>7>50z&11?7b3A827E<9;hd94?=h9j0;66sm4983>7<729q/>84>e:J1=>N5>2cm6=44o0a94?=zj;l1<7<50;2x 73=<2B956F=6:ke>5<N5>2cm6=44o0a94?=zj:91<7<50;2x 73=9<1C>45G279jb?6=3f;h6=44}r0f>5<5sW8n70;56:?0`?0<5:i1:632785784=2:92>;4?3<01>856:?00?0<5;l1=n5rs2294?4|V::01>?5f:p74<72=q6:949;<7:>3=:=j0=70=>:0a8yv55290iw0=::308962=?278:794=2593>;403=01>757:?0e?1<5:h1;63650;1x907=m27847<<;<14>d=z{:31<7=t=5d9a>;4138870=7:`9~w6g=839p19j5e:?0e?4434926l5rs2`94?5|5=h1i63m50;1x91?=m278o7<<;<1a>d=z{:n1<7=t=559a>;4l38870=l:`9~w6c=838pR>k4=5:95f=z{:l1<750;0xZ16<5=i1=n5rs5394?4|V=;019k51b9~w14=838pR9<4=4295f=z{=91<71=n5rs5494?4|V=<018851b9~w11=838p1995229>0=52z?7=?4434>j6k5rs5`94?4|5=h1>>524b8e?xu3l3:1>v3;d;00?82b2o1v9h50;0x91`=::169=4i;|q65?6=:r7>=7<<;<71>c=z{<91<72h169o4>c:p1f<72;q69n4=3:?6f?763ty>h7>52z?6g?g<55f:p25<72=q6:948;<7:>2=:=j0<708?:0a8yv062909wS8>;<41>c=z{?81<7mt=479e>;2;3k018?5a:?7b?g<5=n1m63;b;c891?=i27?;7o4=4g955=:=k0:<6392;3`?80128:0q~8;:1818032;901>=5f:p20<72;q6:94n;<45>4e51zJ12>{iil0;65<6sA8=7p`m1;295~N5>2wen?4?:0yK63=zfk91<7?tH348ykd3290:wE<9;|la1?6=9rB9:6sab783>4}O:?1vbo950;3xL70{I05?xhe13:1=vF=6:mfd<728qC>;5rnc`94?7|@;<0qcll:182M413tdih7>51zJ12>{ijl0;65<6sA8=7p`l1;295~N5>2weo?4?:0yK63=zfj91<7?tH348yke3290:wE<9;|l`1?6=9rB9:6sac783>4}O:?1vbn950;3xL70{I05?xhd13:1=vF=6:mgd<728qC>;5rnb`94?7|@;<0qcml:182M413tdhh7>51zJ12>{ikl0;65<6sA8=7p`k1;295~N5>2weh?4?:0yK63=zfm91<7?tH348ykb3290:wE<9;|lg1?6=9rB9:6sad783>4}O:?1vqpsO@By244<0kmk>9=6r@A@x4xFGXrwKL
\ No newline at end of file
Index: uart_block/trunk/hdl/iseProject/serial_receiver_vhdl.prj
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_receiver_vhdl.prj (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_receiver_vhdl.prj (revision 2)
@@ -0,0 +1,2 @@
+vhdl work "E:\uart_block\hdl\iseProject\pkgDefinitions.vhd"
+vhdl work "E:\uart_block\hdl\iseProject\serial_receiver.vhd"
Index: uart_block/trunk/hdl/iseProject/testSerial_receiver_beh.prj
===================================================================
--- uart_block/trunk/hdl/iseProject/testSerial_receiver_beh.prj (nonexistent)
+++ uart_block/trunk/hdl/iseProject/testSerial_receiver_beh.prj (revision 2)
@@ -0,0 +1,3 @@
+vhdl work "pkgDefinitions.vhd"
+vhdl work "serial_receiver.vhd"
+vhdl work "testSerial_receiver.vhd"
Index: uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.wdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.wdb
===================================================================
--- uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.wdb (nonexistent)
+++ uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.wdb (revision 2)
Main document of the uart_block project
\n +--!Features
+--! Wishbone slave \n +--! Calculate baudrate based on clock speed \n\n +--! Interesting links \n +--! http://opencores.org/ \n + +--! Use standard library + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package pkgDefinitions is + +--! Declare constants, enums, functions used by the design +constant nBits : integer := 8; + +type txStates is (tx_idle, tx_start, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, tx_stop1, tx_stop2); +type rxStates is (rx_idle, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, rx_stop); +type rxFilterStates is (s0, s1, s2); + +end pkgDefinitions; + +package body pkgDefinitions is + +end pkgDefinitions; Index: uart_block/trunk/hdl/iseProject/iseProject.gise =================================================================== --- uart_block/trunk/hdl/iseProject/iseProject.gise (nonexistent) +++ uart_block/trunk/hdl/iseProject/iseProject.gise (revision 2) @@ -0,0 +1,162 @@ + ++ +
Environment Settings | +||||
Environment Variable | +xst | +ngdbuild | +map | +par | +
PATHEXT | +.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
+< data not available > | +< data not available > | +< data not available > | +
Path | +e:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64; e:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64; E:\Xilinx\13.4\ISE_DS\PlanAhead\bin; E:\Xilinx\13.4\ISE_DS\ISE\bin\nt64; E:\Xilinx\13.4\ISE_DS\ISE\lib\nt64; E:\Xilinx\13.4\ISE_DS\EDK\bin\nt64; E:\Xilinx\13.4\ISE_DS\EDK\lib\nt64; E:\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin; E:\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; E:\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin; E:\Xilinx\13.4\ISE_DS\common\bin\nt64; E:\Xilinx\13.4\ISE_DS\common\lib\nt64; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\DMIX; C:\Program Files (x86)\Windows Live\Shared; C:\Program Files (x86)\Autodesk\Backburner\; C:\Program Files (x86)\QuickTime\QTSystem\; E:\Matlab12a\runtime\win64; E:\Matlab12a\bin; E:\Matlab\runtime\win64; E:\Matlab\bin; C:\Program Files\TortoiseSVN\bin; C:\Program Files\doxygen\bin |
+< data not available > | +< data not available > | +< data not available > | +
XILINX | +e:\Xilinx\13.4\ISE_DS\ISE\ | +< data not available > | +< data not available > | +< data not available > | +
XILINX_DSP | +E:\Xilinx\13.4\ISE_DS\ISE | +< data not available > | +< data not available > | +< data not available > | +
XILINX_EDK | +E:\Xilinx\13.4\ISE_DS\EDK | +< data not available > | +< data not available > | +< data not available > | +
XILINX_FOR_ALTIUM_OVERRIDE | ++ | < data not available > | +< data not available > | +< data not available > | +
XILINX_PLANAHEAD | +E:\Xilinx\13.4\ISE_DS\PlanAhead | +< data not available > | +< data not available > | +< data not available > | +
Synthesis Property Settings | +|||
Switch Name | +Property Name | +Value | +Default Value | +
-ifn | ++ | serial_receiver.prj | ++ |
-ifmt | ++ | mixed | +MIXED | +
-ofn | ++ | serial_receiver | ++ |
-ofmt | ++ | NGC | +NGC | +
-p | ++ | xc3s500e-4-fg320 | ++ |
-top | ++ | serial_receiver | ++ |
-opt_mode | +Optimization Goal | +Speed | +SPEED | +
-opt_level | +Optimization Effort | +1 | +1 | +
-iuc | +Use synthesis Constraints File | +NO | +NO | +
-keep_hierarchy | +Keep Hierarchy | +No | +NO | +
-netlist_hierarchy | +Netlist Hierarchy | +As_Optimized | +as_optimized | +
-rtlview | +Generate RTL Schematic | +Yes | +NO | +
-glob_opt | +Global Optimization Goal | +AllClockNets | +ALLCLOCKNETS | +
-read_cores | +Read Cores | +YES | +YES | +
-write_timing_constraints | +Write Timing Constraints | +NO | +NO | +
-cross_clock_analysis | +Cross Clock Analysis | +NO | +NO | +
-bus_delimiter | +Bus Delimiter | +<> | +<> | +
-slice_utilization_ratio | +Slice Utilization Ratio | +100 | +100% | +
-bram_utilization_ratio | +BRAM Utilization Ratio | +100 | +100% | +
-verilog2001 | +Verilog 2001 | +YES | +YES | +
-fsm_extract | ++ | YES | +YES | +
-fsm_encoding | ++ | Auto | +AUTO | +
-safe_implementation | ++ | No | +NO | +
-fsm_style | ++ | LUT | +LUT | +
-ram_extract | ++ | Yes | +YES | +
-ram_style | ++ | Auto | +AUTO | +
-rom_extract | ++ | Yes | +YES | +
-shreg_extract | ++ | YES | +YES | +
-rom_style | ++ | Auto | +AUTO | +
-auto_bram_packing | ++ | NO | +NO | +
-resource_sharing | ++ | YES | +YES | +
-async_to_sync | ++ | NO | +NO | +
-mult_style | ++ | Auto | +AUTO | +
-iobuf | ++ | YES | +YES | +
-max_fanout | ++ | 100000 | +500 | +
-bufg | ++ | 24 | +24 | +
-register_duplication | ++ | YES | +YES | +
-register_balancing | ++ | No | +NO | +
-optimize_primitives | ++ | NO | +NO | +
-use_clock_enable | ++ | Yes | +YES | +
-use_sync_set | ++ | Yes | +YES | +
-use_sync_reset | ++ | Yes | +YES | +
-iob | ++ | Auto | +AUTO | +
-equivalent_register_removal | ++ | YES | +YES | +
-slice_utilization_ratio_maxmargin | ++ | 5 | +0% | +
Operating System Information | +||||
Operating System Information | +xst | +ngdbuild | +map | +par | +
CPU Architecture/Speed | +Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz/3502 MHz | +< data not available > | +< data not available > | +< data not available > | +
Host | +Leonardo-PC | +< data not available > | +< data not available > | +< data not available > | +
OS Name | +Microsoft Windows 7 , 64-bit | +< data not available > | +< data not available > | +< data not available > | +
OS Release | +Service Pack 1 (build 7601) | +< data not available > | +< data not available > | +< data not available > | +
uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.wdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/serial_transmitter.cmd_log
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_transmitter.cmd_log (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_transmitter.cmd_log (revision 2)
@@ -0,0 +1,5 @@
+xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_transmitter.xst" -ofn "E:/uart_block/hdl/iseProject/serial_transmitter.syr"
+xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_transmitter.xst" -ofn "E:/uart_block/hdl/iseProject/serial_transmitter.syr"
+xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_transmitter.xst" -ofn "E:/uart_block/hdl/iseProject/serial_transmitter.syr"
+xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_transmitter.xst" -ofn "E:/uart_block/hdl/iseProject/serial_transmitter.syr"
+xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_transmitter.xst" -ofn "E:/uart_block/hdl/iseProject/serial_transmitter.syr"
Index: uart_block/trunk/hdl/iseProject/serial_receiver.stx
===================================================================
Index: uart_block/trunk/hdl/iseProject/fuse.log
===================================================================
--- uart_block/trunk/hdl/iseProject/fuse.log (nonexistent)
+++ uart_block/trunk/hdl/iseProject/fuse.log (revision 2)
@@ -0,0 +1,21 @@
+Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver
+ISim O.87xd (signature 0xc3576ebc)
+Number of CPUs detected in this system: 8
+Turning on mult-threading, number of parallel sub-compilation jobs: 16
+Determining compilation order of HDL files
+Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
+Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
+Parsing VHDL file "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
+Starting static elaboration
+Completed static elaboration
+Compiling package standard
+Compiling package std_logic_1164
+Compiling package pkgdefinitions
+Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
+Compiling architecture behavior of entity testserial_receiver
+Time Resolution for simulation is 1ps.
+Waiting for 2 sub-compilation(s) to finish...
+Compiled 6 VHDL Units
+Built simulation executable E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
+Fuse Memory Usage: 29424 KB
+Fuse CPU Usage: 265 ms
Index: uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.exe
===================================================================
--- uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.exe (nonexistent)
+++ uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.exe (revision 2)
uart_block/trunk/hdl/iseProject/testSerial_receiver_isim_beh.exe
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/webtalk_pn.xml
===================================================================
--- uart_block/trunk/hdl/iseProject/webtalk_pn.xml (nonexistent)
+++ uart_block/trunk/hdl/iseProject/webtalk_pn.xml (revision 2)
@@ -0,0 +1,45 @@
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
Index: uart_block/trunk/hdl/iseProject/serial_transmitter.syr
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_transmitter.syr (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_transmitter.syr (revision 2)
@@ -0,0 +1,386 @@
+Release 13.4 - xst O.87xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+--> Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.22 secs
+
+--> Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.22 secs
+
+--> Reading design: serial_transmitter.prj
+
+TABLE OF CONTENTS
+ 1) Synthesis Options Summary
+ 2) HDL Compilation
+ 3) Design Hierarchy Analysis
+ 4) HDL Analysis
+ 5) HDL Synthesis
+ 5.1) HDL Synthesis Report
+ 6) Advanced HDL Synthesis
+ 6.1) Advanced HDL Synthesis Report
+ 7) Low Level Synthesis
+ 8) Partition Report
+ 9) Final Report
+ 9.1) Device utilization summary
+ 9.2) Partition Resource Summary
+ 9.3) TIMING REPORT
+
+
+=========================================================================
+* Synthesis Options Summary *
+=========================================================================
+---- Source Parameters
+Input File Name : "serial_transmitter.prj"
+Input Format : mixed
+Ignore Synthesis Constraint File : NO
+
+---- Target Parameters
+Output File Name : "serial_transmitter"
+Output Format : NGC
+Target Device : xc3s500e-4-fg320
+
+---- Source Options
+Top Module Name : serial_transmitter
+Automatic FSM Extraction : YES
+FSM Encoding Algorithm : Auto
+Safe Implementation : No
+FSM Style : LUT
+RAM Extraction : Yes
+RAM Style : Auto
+ROM Extraction : Yes
+Mux Style : Auto
+Decoder Extraction : YES
+Priority Encoder Extraction : Yes
+Shift Register Extraction : YES
+Logical Shifter Extraction : YES
+XOR Collapsing : YES
+ROM Style : Auto
+Mux Extraction : Yes
+Resource Sharing : YES
+Asynchronous To Synchronous : NO
+Multiplier Style : Auto
+Automatic Register Balancing : No
+
+---- Target Options
+Add IO Buffers : YES
+Global Maximum Fanout : 100000
+Add Generic Clock Buffer(BUFG) : 24
+Register Duplication : YES
+Slice Packing : YES
+Optimize Instantiated Primitives : NO
+Use Clock Enable : Yes
+Use Synchronous Set : Yes
+Use Synchronous Reset : Yes
+Pack IO Registers into IOBs : Auto
+Equivalent register Removal : YES
+
+---- General Options
+Optimization Goal : Speed
+Optimization Effort : 1
+Keep Hierarchy : No
+Netlist Hierarchy : As_Optimized
+RTL Output : Yes
+Global Optimization : AllClockNets
+Read Cores : YES
+Write Timing Constraints : NO
+Cross Clock Analysis : NO
+Hierarchy Separator : /
+Bus Delimiter : <>
+Case Specifier : Maintain
+Slice Utilization Ratio : 100
+BRAM Utilization Ratio : 100
+Verilog 2001 : YES
+Auto BRAM Packing : NO
+Slice Utilization Ratio Delta : 5
+
+=========================================================================
+
+
+=========================================================================
+* HDL Compilation *
+=========================================================================
+Compiling vhdl file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
+Package compiled.
+Package body compiled.
+Compiling vhdl file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.
+Architecture behavioral of Entity serial_transmitter is up to date.
+
+=========================================================================
+* Design Hierarchy Analysis *
+=========================================================================
+Analyzing hierarchy for entity in library (architecture ).
+
+
+=========================================================================
+* HDL Analysis *
+=========================================================================
+Analyzing Entity in library (Architecture ).
+Entity analyzed. Unit generated.
+
+
+=========================================================================
+* HDL Synthesis *
+=========================================================================
+
+Performing bidirectional port resolution...
+
+Synthesizing Unit .
+ Related source file is "E:/uart_block/hdl/iseProject/serial_transmitter.vhd".
+ Found finite state machine for signal .
+ -----------------------------------------------------------------------
+ | States | 12 |
+ | Transitions | 12 |
+ | Inputs | 0 |
+ | Outputs | 13 |
+ | Clock | baudClk (rising_edge) |
+ | Reset | rst (positive) |
+ | Reset type | asynchronous |
+ | Reset State | tx_idle |
+ | Power Up State | tx_idle |
+ | Encoding | automatic |
+ | Implementation | LUT |
+ -----------------------------------------------------------------------
+ Summary:
+ inferred 1 Finite State Machine(s).
+Unit synthesized.
+
+
+=========================================================================
+HDL Synthesis Report
+
+Found no macro
+=========================================================================
+
+=========================================================================
+* Advanced HDL Synthesis *
+=========================================================================
+
+Analyzing FSM for best encoding.
+Optimizing FSM on signal with one-hot encoding.
+--------------------------
+ State | Encoding
+--------------------------
+ tx_idle | 000000000001
+ tx_start | 000000000010
+ bit0 | 000000000100
+ bit1 | 000000001000
+ bit2 | 000000010000
+ bit3 | 000000100000
+ bit4 | 000001000000
+ bit5 | 000010000000
+ bit6 | 000100000000
+ bit7 | 001000000000
+ tx_stop1 | 010000000000
+ tx_stop2 | 100000000000
+--------------------------
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# FSMs : 1
+
+=========================================================================
+
+=========================================================================
+* Low Level Synthesis *
+=========================================================================
+
+Optimizing unit ...
+
+Mapping all equations...
+Building and optimizing final netlist ...
+Found area constraint ratio of 100 (+ 5) on block serial_transmitter, actual ratio is 0.
+
+Final Macro Processing ...
+
+=========================================================================
+Final Register Report
+
+Macro Statistics
+# Registers : 12
+ Flip-Flops : 12
+
+=========================================================================
+
+=========================================================================
+* Partition Report *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+* Final Report *
+=========================================================================
+Final Results
+RTL Top Level Output File Name : serial_transmitter.ngr
+Top Level Output File Name : serial_transmitter
+Output Format : NGC
+Optimization Goal : Speed
+Keep Hierarchy : No
+
+Design Statistics
+# IOs : 12
+
+Cell Usage :
+# BELS : 9
+# GND : 1
+# LUT2 : 1
+# LUT4 : 6
+# VCC : 1
+# FlipFlops/Latches : 12
+# FDC : 10
+# FDCE : 1
+# FDP : 1
+# Clock Buffers : 1
+# BUFGP : 1
+# IO Buffers : 11
+# IBUF : 9
+# OBUF : 2
+=========================================================================
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 3s500efg320-4
+
+ Number of Slices: 7 out of 4656 0%
+ Number of Slice Flip Flops: 12 out of 9312 0%
+ Number of 4 input LUTs: 7 out of 9312 0%
+ Number of IOs: 12
+ Number of bonded IOBs: 12 out of 232 5%
+ Number of GCLKs: 1 out of 24 4%
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+ No Partitions were found in this design.
+
+---------------------------
+
+
+=========================================================================
+TIMING REPORT
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+ FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+ GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+-----------------------------------+------------------------+-------+
+Clock Signal | Clock buffer(FF name) | Load |
+-----------------------------------+------------------------+-------+
+baudClk | BUFGP | 12 |
+-----------------------------------+------------------------+-------+
+
+Asynchronous Control Signals Information:
+----------------------------------------
+-----------------------------------+------------------------+-------+
+Control Signal | Buffer(FF name) | Load |
+-----------------------------------+------------------------+-------+
+rst | IBUF | 12 |
+-----------------------------------+------------------------+-------+
+
+Timing Summary:
+---------------
+Speed Grade: -4
+
+ Minimum period: 1.677ns (Maximum Frequency: 596.303MHz)
+ Minimum input arrival time before clock: No path found
+ Maximum output required time after clock: 8.036ns
+ Maximum combinational path delay: 8.540ns
+
+Timing Detail:
+--------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'baudClk'
+ Clock period: 1.677ns (frequency: 596.303MHz)
+ Total number of paths / destination ports: 11 / 11
+-------------------------------------------------------------------------
+Delay: 1.677ns (Levels of Logic = 0)
+ Source: current_s_FSM_FFd2 (FF)
+ Destination: current_s_FSM_FFd1 (FF)
+ Source Clock: baudClk rising
+ Destination Clock: baudClk rising
+
+ Data Path: current_s_FSM_FFd2 to current_s_FSM_FFd1
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ FDC:C->Q 3 0.591 0.531 current_s_FSM_FFd2 (current_s_FSM_FFd2)
+ FDCE:CE 0.555 current_s_FSM_FFd1
+ ----------------------------------------
+ Total 1.677ns (1.146ns logic, 0.531ns route)
+ (68.3% logic, 31.7% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
+ Total number of paths / destination ports: 13 / 2
+-------------------------------------------------------------------------
+Offset: 8.036ns (Levels of Logic = 4)
+ Source: current_s_FSM_FFd7 (FF)
+ Destination: serial_out (PAD)
+ Source Clock: baudClk rising
+
+ Data Path: current_s_FSM_FFd7 to serial_out
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ FDC:C->Q 2 0.591 0.622 current_s_FSM_FFd7 (current_s_FSM_FFd7)
+ LUT4:I0->O 1 0.704 0.595 serial_out12 (serial_out12)
+ LUT4:I0->O 1 0.704 0.424 serial_out48_SW0 (N01)
+ LUT4:I3->O 1 0.704 0.420 serial_out48 (serial_out_OBUF)
+ OBUF:I->O 3.272 serial_out_OBUF (serial_out)
+ ----------------------------------------
+ Total 8.036ns (5.975ns logic, 2.061ns route)
+ (74.4% logic, 25.6% route)
+
+=========================================================================
+Timing constraint: Default path analysis
+ Total number of paths / destination ports: 8 / 1
+-------------------------------------------------------------------------
+Delay: 8.540ns (Levels of Logic = 5)
+ Source: data_byte<3> (PAD)
+ Destination: serial_out (PAD)
+
+ Data Path: data_byte<3> to serial_out
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ IBUF:I->O 1 1.218 0.499 data_byte_3_IBUF (data_byte_3_IBUF)
+ LUT4:I1->O 1 0.704 0.595 serial_out12 (serial_out12)
+ LUT4:I0->O 1 0.704 0.424 serial_out48_SW0 (N01)
+ LUT4:I3->O 1 0.704 0.420 serial_out48 (serial_out_OBUF)
+ OBUF:I->O 3.272 serial_out_OBUF (serial_out)
+ ----------------------------------------
+ Total 8.540ns (6.602ns logic, 1.938ns route)
+ (77.3% logic, 22.7% route)
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 5.00 secs
+Total CPU time to Xst completion: 5.00 secs
+
+-->
+
+Total memory usage is 255476 kilobytes
+
+Number of errors : 0 ( 0 filtered)
+Number of warnings : 0 ( 0 filtered)
+Number of infos : 0 ( 0 filtered)
+
Index: uart_block/trunk/hdl/iseProject/serial_transmitter.xst
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_transmitter.xst (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_transmitter.xst (revision 2)
@@ -0,0 +1,56 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn serial_transmitter.prj
+-ifmt mixed
+-ofn serial_transmitter
+-ofmt NGC
+-p xc3s500e-4-fg320
+-top serial_transmitter
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: uart_block/trunk/hdl/iseProject/serial_receiver.ngr
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_receiver.ngr (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_receiver.ngr (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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7c=82wbn7>5;ha94?=n980;66a;6;29?xd6i3:187<55z&7g?7f3`9;6=44i0a94?=n;k0;66a>6;29?g7>29086=4?{%6`>3=On4?::k1`?6=3f9>6=44}c3;>5<4290;w):l:258L1`>i4=3:17p}<0;296~X4827:579;0g?xu4j3:1>vP52z\22>;6039>7p}>7;296~;6139>70?7:3f8yxd6m3:1?7>50z&7g?5?3A>m7d53z\04>;6i39;70?j:3a8yv772908wS??;<36>g=:9j0i7p}8:180[1<58?1o63>c;a8yv5e290?wS=m;<36>10<58k1?o521d81`>{t9?0;6?u214825>;6i3;=7p}>d;296~;6k3;:70?j:278yxua2909wSh4=34955=z{=21<77}Y;h16>;4{t;90;6?uQ319>63<482wvn;l50;195?5|D<:1=vF<1:O14<0sg2;6884$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<72;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<74$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<72;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<72;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<750;195?5|D<:1=vF<1:O14<0sg2;6;h4$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<72;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<72;k0b:951:&4b?753t.?o7=;;h32>5<>d729086=4?{%6`>64<@=l0e50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<75G4g9O14<5s-=m6<<4n9295`=zak0;66gl:188m47=831d8;4?::a<6<72:0;6=u+4b86?M2a3`8h6=44i3f94?=h;<0;66s|5683>7}Y=>16944i;|q4f?6=;rT62j1v:=50;0xZ25<5<318<5rs6f94?d|V>n01::5319>2g<6927=o7?>;<4g>47<5?o1=<526g825>;083;:709>:038924=98164>4=d:p1=<72:qU9552758e?8>62k1v8o50;0x90?=;016:o4=a:p1g<72;q6944o7>52z?6=?5e345<5s4?26>m4=7g96d=z{o09m6s|5g83>7}:=008i6380;0b?xu183:1>v3:9;1e?8162;k0q~8>:18183>2=:01:<52`9~w=4=838p15?5109><6<4=2wx;84?:3y>31<4j273?757:7;<:2>1052z\5<>;093>=7):m:7;8j1g=92wx::4?:3y]22=:?90?:6*;b;4:?k2f2;1v;850;0xZ30<5?l18;5+4c85=>h3i390q~8::181[02343?7}Y>:16:n4;6:&7f?0>3g>j6;5rs7094?4|V?801;l5479'0g<112d?m794}|~yEFDs8?869;6530;4xFGJr:vLM^t}AB
\ No newline at end of file
Index: uart_block/trunk/hdl/iseProject/serial_transmitter.vhd
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_transmitter.vhd (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_transmitter.vhd (revision 2)
@@ -0,0 +1,100 @@
+--! Data transmitter
+--! http://www.fpga4fun.com/SerialInterface.html
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+--! Use CPU Definitions package
+use work.pkgDefinitions.all;
+
+entity serial_transmitter is
+ Port ( rst : in STD_LOGIC;
+ baudClk : in STD_LOGIC;
+ data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
+ data_sent : out STD_LOGIC;
+ serial_out : out STD_LOGIC);
+end serial_transmitter;
+
+architecture Behavioral of serial_transmitter is
+signal current_s,next_s: txStates;
+begin
+
+ -- Next state process
+ process (rst, baudClk)
+ begin
+ if rst = '1' then
+ current_s <= tx_idle;
+ elsif rising_edge(baudClk) then
+ current_s <= next_s;
+ end if;
+ end process;
+
+ process (current_s, data_byte)
+ begin
+ case current_s is
+ when tx_idle =>
+ serial_out <= '1';
+ data_sent <= '0';
+ next_s <= tx_start;
+
+ -- Start bit
+ when tx_start =>
+ serial_out <= '0';
+ data_sent <= '0';
+ next_s <= bit0;
+
+ when bit0 => -- Send the least significat bit
+ serial_out <= data_byte(0);
+ data_sent <= '0';
+ next_s <= bit1;
+
+ when bit1 =>
+ serial_out <= data_byte(1);
+ data_sent <= '0';
+ next_s <= bit2;
+
+ when bit2 =>
+ serial_out <= data_byte(2);
+ data_sent <= '0';
+ next_s <= bit3;
+
+ when bit3 =>
+ serial_out <= data_byte(3);
+ data_sent <= '0';
+ next_s <= bit4;
+
+ when bit4 =>
+ serial_out <= data_byte(4);
+ data_sent <= '0';
+ next_s <= bit5;
+
+ when bit5 =>
+ serial_out <= data_byte(5);
+ data_sent <= '0';
+ next_s <= bit6;
+
+ when bit6 =>
+ serial_out <= data_byte(6);
+ data_sent <= '0';
+ next_s <= bit7;
+
+ when bit7 => -- Send the most significat bit
+ serial_out <= data_byte(7);
+ data_sent <= '0';
+ next_s <= tx_stop1;
+
+
+ when tx_stop1 =>
+ serial_out <= '1';
+ data_sent <= '1';
+ next_s <= tx_stop2;
+
+ when tx_stop2 => -- Stop here and wait for other reset
+ serial_out <= '1';
+ data_sent <= '1';
+ next_s <= tx_stop2;
+
+ end case;
+ end process;
+
+end Behavioral;
+
Index: uart_block/trunk/hdl/iseProject/serial_transmitter_summary.html
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_transmitter_summary.html (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_transmitter_summary.html (revision 2)
@@ -0,0 +1,113 @@
+Xilinx Design Summary
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Date Generated: 04/21/2012 - 12:13:10
+
\ No newline at end of file
Index: uart_block/trunk/hdl/iseProject/testSerial_transmitter.vhd
===================================================================
--- uart_block/trunk/hdl/iseProject/testSerial_transmitter.vhd (nonexistent)
+++ uart_block/trunk/hdl/iseProject/testSerial_transmitter.vhd (revision 2)
@@ -0,0 +1,85 @@
+--! Test serial_transmitter module
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+--! Use CPU Definitions package
+use work.pkgDefinitions.all;
+
+ENTITY testSerial_transmitter IS
+END testSerial_transmitter;
+
+ARCHITECTURE behavior OF testSerial_transmitter IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT serial_transmitter
+ PORT(
+ rst : IN std_logic;
+ baudClk : IN std_logic;
+ data_byte : IN std_logic_vector(7 downto 0);
+ data_sent : OUT std_logic;
+ serial_out : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal rst : std_logic := '0';
+ signal baudClk : std_logic := '0';
+ signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
+
+ --Outputs
+ signal data_sent : std_logic;
+ signal serial_out : std_logic;
+
+ -- Clock period definitions
+ constant baudClk_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: serial_transmitter PORT MAP (
+ rst => rst,
+ baudClk => baudClk,
+ data_byte => data_byte,
+ data_sent => data_sent,
+ serial_out => serial_out
+ );
+
+ -- Clock process definitions
+ baudClk_process :process
+ begin
+ baudClk <= '0';
+ wait for baudClk_period/2;
+ baudClk <= '1';
+ wait for baudClk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- Prepare the data to be sent 0x55
+ rst <= '1';
+ data_byte <= "01010101";
+ wait for 50 ns;
+ rst <= '0';
+
+ wait until data_sent = '1';
+ wait for baudClk_period*3;
+
+ -- Prepare the data to be sent
+ rst <= '1';
+ data_byte <= "11000100";
+ wait for 50 ns;
+ rst <= '0';
+
+ wait until data_sent = '1';
+ wait for baudClk_period*3;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
Index: uart_block/trunk/hdl/iseProject/serial_receiver.lso
===================================================================
--- uart_block/trunk/hdl/iseProject/serial_receiver.lso (nonexistent)
+++ uart_block/trunk/hdl/iseProject/serial_receiver.lso (revision 2)
@@ -0,0 +1 @@
+work
Index: uart_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
===================================================================
--- uart_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs (nonexistent)
+++ uart_block/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs (revision 2)
@@ -0,0 +1,15 @@
+
+
+
+
+
+
+
+
+
+
+Parsing VHDL file "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
+
+
+
+
Index: uart_block/trunk/hdl/iseProject/_xmsgs/xst.xmsgs
===================================================================
--- uart_block/trunk/hdl/iseProject/_xmsgs/xst.xmsgs (nonexistent)
+++ uart_block/trunk/hdl/iseProject/_xmsgs/xst.xmsgs (revision 2)
@@ -0,0 +1,40 @@
+
+
+
+"E:/uart_block/hdl/iseProject/serial_receiver.vhd " line 76 : One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
+<serial_in>
+
+
+Found 1 -bit latch for signal <data_byte_0 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+Found 1 -bit latch for signal <data_byte_1 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+Found 1 -bit latch for signal <data_byte_2 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+Found 1 -bit latch for signal <data_byte_3 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+Found 1 -bit latch for signal <data_byte_4 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+Found 1 -bit latch for signal <data_byte_5 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+Found 1 -bit latch for signal <data_byte_6 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+Found 1 -bit latch for signal <data_byte_7 >. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
+
+
+HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+
+
+
+
Index: uart_block/trunk/hdl/iseProject/isim/work/pkgdefinitions.vdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/isim/work/pkgdefinitions.vdb
===================================================================
--- uart_block/trunk/hdl/iseProject/isim/work/pkgdefinitions.vdb (nonexistent)
+++ uart_block/trunk/hdl/iseProject/isim/work/pkgdefinitions.vdb (revision 2)
serial_receiver Project Status (04/21/2012 - 12:13:10) | |||
Project File: | +iseProject.xise | +Parser Errors: | +No Errors | +
Module Name: | +serial_transmitter | +Implementation State: | +Synthesized | +
Target Device: | +xc3s500e-4fg320 | +
|
++ |
Product Version: | ISE 13.4 | +
|
++ |
Design Goal: | +Balanced | +
|
++ | +
Design Strategy: | +Xilinx Default (unlocked) | +
|
++ |
Environment: | ++ +System Settings + | +
|
++ |
Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | +7 | +4656 | +0% | +|
Number of Slice Flip Flops | +12 | +9312 | +0% | +|
Number of 4 input LUTs | +7 | +9312 | +0% | +|
Number of bonded IOBs | +12 | +232 | +5% | +|
Number of GCLKs | +1 | +24 | +4% | +
Detailed Reports | [-] | |||||
Report Name | Status | Generated | +Errors | Warnings | Infos | |
Synthesis Report | Current | sáb 21. abr 11:41:49 2012 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | sáb 21. abr 09:34:09 2012 |
uart_block/trunk/hdl/iseProject/isim/work/pkgdefinitions.vdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/isim/work/testserial_receiver.vdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/isim/work/testserial_receiver.vdb
===================================================================
--- uart_block/trunk/hdl/iseProject/isim/work/testserial_receiver.vdb (nonexistent)
+++ uart_block/trunk/hdl/iseProject/isim/work/testserial_receiver.vdb (revision 2)
uart_block/trunk/hdl/iseProject/isim/work/testserial_receiver.vdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/isim/work/serial_receiver.vdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/isim/work/serial_receiver.vdb
===================================================================
--- uart_block/trunk/hdl/iseProject/isim/work/serial_receiver.vdb (nonexistent)
+++ uart_block/trunk/hdl/iseProject/isim/work/serial_receiver.vdb (revision 2)
uart_block/trunk/hdl/iseProject/isim/work/serial_receiver.vdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/isim/isim_usage_statistics.html
===================================================================
--- uart_block/trunk/hdl/iseProject/isim/isim_usage_statistics.html (nonexistent)
+++ uart_block/trunk/hdl/iseProject/isim/isim_usage_statistics.html (revision 2)
@@ -0,0 +1,5 @@
+
+
ISim Statistics | ||||
+ +
Environment Settings | +||||
Environment Variable | +xst | +ngdbuild | +map | +par | +
PATHEXT | +.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
+< data not available > | +< data not available > | +< data not available > | +
Path | +e:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64; e:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64; E:\Xilinx\13.4\ISE_DS\PlanAhead\bin; E:\Xilinx\13.4\ISE_DS\ISE\bin\nt64; E:\Xilinx\13.4\ISE_DS\ISE\lib\nt64; E:\Xilinx\13.4\ISE_DS\EDK\bin\nt64; E:\Xilinx\13.4\ISE_DS\EDK\lib\nt64; E:\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin; E:\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; E:\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin; E:\Xilinx\13.4\ISE_DS\common\bin\nt64; E:\Xilinx\13.4\ISE_DS\common\lib\nt64; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files\Intel\DMIX; C:\Program Files (x86)\Windows Live\Shared; C:\Program Files (x86)\Autodesk\Backburner\; C:\Program Files (x86)\QuickTime\QTSystem\; E:\Matlab12a\runtime\win64; E:\Matlab12a\bin; E:\Matlab\runtime\win64; E:\Matlab\bin; C:\Program Files\TortoiseSVN\bin; C:\Program Files\doxygen\bin |
+< data not available > | +< data not available > | +< data not available > | +
XILINX | +e:\Xilinx\13.4\ISE_DS\ISE\ | +< data not available > | +< data not available > | +< data not available > | +
XILINX_DSP | +E:\Xilinx\13.4\ISE_DS\ISE | +< data not available > | +< data not available > | +< data not available > | +
XILINX_EDK | +E:\Xilinx\13.4\ISE_DS\EDK | +< data not available > | +< data not available > | +< data not available > | +
XILINX_FOR_ALTIUM_OVERRIDE | ++ | < data not available > | +< data not available > | +< data not available > | +
XILINX_PLANAHEAD | +E:\Xilinx\13.4\ISE_DS\PlanAhead | +< data not available > | +< data not available > | +< data not available > | +
Synthesis Property Settings | +|||
Switch Name | +Property Name | +Value | +Default Value | +
-ifn | ++ | serial_transmitter.prj | ++ |
-ifmt | ++ | mixed | +MIXED | +
-ofn | ++ | serial_transmitter | ++ |
-ofmt | ++ | NGC | +NGC | +
-p | ++ | xc3s500e-4-fg320 | ++ |
-top | ++ | serial_transmitter | ++ |
-opt_mode | +Optimization Goal | +Speed | +SPEED | +
-opt_level | +Optimization Effort | +1 | +1 | +
-iuc | +Use synthesis Constraints File | +NO | +NO | +
-keep_hierarchy | +Keep Hierarchy | +No | +NO | +
-netlist_hierarchy | +Netlist Hierarchy | +As_Optimized | +as_optimized | +
-rtlview | +Generate RTL Schematic | +Yes | +NO | +
-glob_opt | +Global Optimization Goal | +AllClockNets | +ALLCLOCKNETS | +
-read_cores | +Read Cores | +YES | +YES | +
-write_timing_constraints | +Write Timing Constraints | +NO | +NO | +
-cross_clock_analysis | +Cross Clock Analysis | +NO | +NO | +
-bus_delimiter | +Bus Delimiter | +<> | +<> | +
-slice_utilization_ratio | +Slice Utilization Ratio | +100 | +100% | +
-bram_utilization_ratio | +BRAM Utilization Ratio | +100 | +100% | +
-verilog2001 | +Verilog 2001 | +YES | +YES | +
-fsm_extract | ++ | YES | +YES | +
-fsm_encoding | ++ | Auto | +AUTO | +
-safe_implementation | ++ | No | +NO | +
-fsm_style | ++ | LUT | +LUT | +
-ram_extract | ++ | Yes | +YES | +
-ram_style | ++ | Auto | +AUTO | +
-rom_extract | ++ | Yes | +YES | +
-shreg_extract | ++ | YES | +YES | +
-rom_style | ++ | Auto | +AUTO | +
-auto_bram_packing | ++ | NO | +NO | +
-resource_sharing | ++ | YES | +YES | +
-async_to_sync | ++ | NO | +NO | +
-mult_style | ++ | Auto | +AUTO | +
-iobuf | ++ | YES | +YES | +
-max_fanout | ++ | 100000 | +500 | +
-bufg | ++ | 24 | +24 | +
-register_duplication | ++ | YES | +YES | +
-register_balancing | ++ | No | +NO | +
-optimize_primitives | ++ | NO | +NO | +
-use_clock_enable | ++ | Yes | +YES | +
-use_sync_set | ++ | Yes | +YES | +
-use_sync_reset | ++ | Yes | +YES | +
-iob | ++ | Auto | +AUTO | +
-equivalent_register_removal | ++ | YES | +YES | +
-slice_utilization_ratio_maxmargin | ++ | 5 | +0% | +
Operating System Information | +||||
Operating System Information | +xst | +ngdbuild | +map | +par | +
CPU Architecture/Speed | +Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz/3502 MHz | +< data not available > | +< data not available > | +< data not available > | +
Host | +Leonardo-PC | +< data not available > | +< data not available > | +< data not available > | +
OS Name | +Microsoft Windows 7 , 64-bit | +< data not available > | +< data not available > | +< data not available > | +
OS Release | +Service Pack 1 (build 7601) | +< data not available > | +< data not available > | +< data not available > | +
uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl00.vho
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl01.vho
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl01.vho
===================================================================
--- uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl01.vho (nonexistent)
+++ uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl01.vho (revision 2)
uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl01.vho
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl02.vho
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl02.vho
===================================================================
--- uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl02.vho (nonexistent)
+++ uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl02.vho (revision 2)
uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl02.vho
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl03.vho
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl03.vho
===================================================================
--- uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl03.vho (nonexistent)
+++ uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl03.vho (revision 2)
uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl03.vho
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho
===================================================================
--- uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho (nonexistent)
+++ uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho (revision 2)
uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl04.vho
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho
===================================================================
--- uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho (nonexistent)
+++ uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho (revision 2)
uart_block/trunk/hdl/iseProject/xst/work/sub00/vhpl05.vho
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref
===================================================================
--- uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref (nonexistent)
+++ uart_block/trunk/hdl/iseProject/xst/work/hdllib.ref (revision 2)
@@ -0,0 +1,6 @@
+PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335003187
+EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335003188
+AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335001308
+EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335001307
+PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335003186
+AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335003189
Index: uart_block/trunk/hdl/iseProject/iseProject.xise
===================================================================
--- uart_block/trunk/hdl/iseProject/iseProject.xise (nonexistent)
+++ uart_block/trunk/hdl/iseProject/iseProject.xise (revision 2)
@@ -0,0 +1,360 @@
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