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URL https://opencores.org/ocsvn/uart_serial/uart_serial/trunk

Subversion Repositories uart_serial

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/trunk/testbench/tb_uart.vhd
0,0 → 1,137
-------------------------------------------------------------------------------
-- Use of this source code through a simulator and/or a compiler tool
-- is illegal if not authorised through Author License agreement.
-------------------------------------------------------------------------------
-- top level : tb_uart.vhd
-- File : tb_uart.vhd
-- Author : Xavier Martin
-- Email :
-- Organization:
-- Created : 2008, june 30th
-- Last update :
-- Simulators : ModelSim Altera 6.0c
-- Synthesizers: Quartus II 5.0
-- Targets :
-- Dependency :
-------------------------------------------------------------------------------
-- Description : This entity is a testbench for generic UART block
-- baud : 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
-- 230400, 460800, 921600
-------------------------------------------------------------------------------
-- Version : 1.0
-- Date :
-- Modifier :
-- Modif. :
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity tb_uart is
end entity;
 
 
architecture behavior of tb_uart is
 
signal reset : std_logic; -- reset control signal
signal clk : std_logic:='1'; -- 14.7456 Mhz Clock frequency
signal rx_data_serial : std_logic; -- Received Serial data from RS232
signal rx_data_out : std_logic_vector(7 downto 0); -- Received Data
signal rx_data_en : std_logic; -- Received data enable control signal
signal tx_data_serial : std_logic; -- Transmited serial data to RS232
signal tx_data_in : std_logic_vector(7 downto 0); -- Transmited data
signal tx_data_en : std_logic; -- Transmited data latch enable
signal tx_ch_rdy : std_logic; -- Transmition channel ready status signal
signal tx_ch_rdy_i : std_logic;
signal baud_sel : std_logic_vector(3 downto 0); -- Baud value see Note
signal parity_en : std_logic; -- Enable parity control signal active HIGH
signal parity_type : std_logic; -- 1:ODD parity / 0:EVEN parity
signal fifo_usedw : std_logic_vector(1 downto 0);
signal rx_ovf_err : std_logic; -- Received over frame error status signal
signal rx_parity_err : std_logic; -- Received parity error
 
 
begin
-------------------------------------------------------------------------------
uart_serial_inst:
entity work.uart_serial
-------------------------------------------------------------------------------
port map(
-- Global signal
reset => reset, -- [in] reset control signal
clk => clk, -- [in] 14.7456 Mhz Clock frequency
-- Reception channel
rx_data_serial => rx_data_serial, -- [in] Received Serial data from RS232
rx_data_out => rx_data_out, -- [out] Received Data
rx_data_en => rx_data_en, -- [out] Received data enable control signal
rx_ovf_err => rx_ovf_err, -- [out] Received over frame error status signal
rx_parity_err => rx_parity_err, -- [out] Received parity error
-- Transmition channel
tx_data_serial => tx_data_serial, -- [out] Transmited Serial data to RS232
tx_data_in => tx_data_in, -- [in] Transmited data
tx_data_en => tx_data_en, -- [in] Transmited data latch enable
tx_ch_rdy => tx_ch_rdy, -- [out] Transmition channel ready status signal
-- Control command
baud_sel => baud_sel, -- [in] Baud value see Note
parity_en => parity_en, -- [in] Enable parity control signal active HIGH
parity_type => parity_type); -- [in] 1:ODD parity / 0:EVEN parity
process(reset,clk)
begin
if reset = '1' then
rx_data_serial <= '1';
elsif rising_edge(clk) then
rx_data_serial <= tx_data_serial;
end if;
end process;
-------------------------------------------------------------------------------
-- CONTROL COMMAND VALUE
-------------------------------------------------------------------------------
baud_sel <= x"8";
parity_en <= '0';
parity_type <= '0';
-------------------------------------------------------------------------------
-- GLOBAL SIGNALS PROCESS
-------------------------------------------------------------------------------
reset_proc:
process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
wait;
end process;
clk_proc:
process
begin
clk <= not(clk);
wait for 33.9 ns;
end process;
-------------------------------------------------------------------------------
-- Data To transmit
-------------------------------------------------------------------------------
process(reset,clk)
begin
if reset = '1' then
tx_data_in <= (others => '0');
tx_data_en <= '0';
tx_ch_rdy_i <= '0';
elsif rising_edge(clk) then
tx_ch_rdy_i <= tx_ch_rdy;
if tx_ch_rdy = '1' and tx_ch_rdy_i = '0' then
tx_data_en <= '1';
tx_data_in <= tx_data_in + 1;
else
tx_data_en <= '0';
end if;
end if;
end process;
end behavior;
/trunk/sources/uart_serial.vhd
0,0 → 1,374
-------------------------------------------------------------------------------
-- Use of this source code through a simulator and/or a compiler tool
-- is illegal if not authorised through Author License agreement.
-------------------------------------------------------------------------------
-- top level : uart_serial.vhd
-- File : uart_serial.vhd
-- Author : Xavier Martin
-- Email :
-- Organization:
-- Created : 2008, june 30th
-- Last update :
-- Simulators : ModelSim Altera 6.0c
-- Synthesizers: Quartus II 5.0
-- Targets :
-- Dependency :
-------------------------------------------------------------------------------
-- Description : This entity is a generic UART block
-- UART allows to work with one or two bits stop
-- baud : 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
-- 230400, 460800, 921600
-- Note:
-- Br*br_divisor=921.600
-- Fclk/921.600=clk_divisor
-- => Br=Fclk/(clk_divisor*br_divisor)=1/((clk_divisor*Tclk)*br_divisor)
-------------------------------------------------------------------------------
-- Version : 1.0
-- Date :
-- Modifier :
-- Modif. :
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity uart_serial is
port(
-- Global signal
reset : in std_logic; -- reset control signal
clk : in std_logic; -- 14.7456 Mhz Clock frequency
-- Reception channel
rx_data_serial : in std_logic; -- Received Serial data from RS232
rx_data_out : out std_logic_vector(7 downto 0); -- Received Data
rx_data_en : out std_logic; -- Received data enable control signal
rx_ovf_err : out std_logic; -- Received data over frame error detected
rx_parity_err : out std_logic; -- Received data parity error
-- Transmition channel
tx_data_serial : out std_logic; -- Transmited Serial data to RS232
tx_data_in : in std_logic_vector(7 downto 0); -- Transmited data
tx_data_en : in std_logic; -- Transmited data latch enable
tx_ch_rdy : out std_logic; -- Transmition channel ready status signal
-- Control command
baud_sel : in std_logic_vector(3 downto 0); -- Baud value see Note
parity_en : in std_logic; -- Enable parity control signal active HIGH
parity_type : in std_logic); -- 1:ODD parity / 0:EVEN parity
end entity;
 
 
architecture rtl of uart_serial is
 
-------------------------------------------------------------------------------
-- CONSTANT DECLARATION
-------------------------------------------------------------------------------
constant ODD_PARITY : std_logic := '1';
constant EVEN_PARITY : std_logic := '0';
constant CLK_DIVISOR : integer := 16; -- clock divisor to obtain 921600 bauds - CLK_DIVISOR = Fclk/921600
constant BR_DIVISOR_300 : integer := 3072; -- 300 bauds bit rate divisor value
constant BR_DIVISOR_1200 : integer := 768; -- 1200 bauds bit rate divisor value
constant BR_DIVISOR_2400 : integer := 384; -- 2400 bauds bit rate divisor value
constant BR_DIVISOR_4800 : integer := 192; -- 4800 bauds bit rate divisor value
constant BR_DIVISOR_9600 : integer := 96; -- 9600 bauds bit rate divisor value
constant BR_DIVISOR_19200 : integer := 48; -- 19200 bauds bit rate divisor value
constant BR_DIVISOR_38400 : integer := 24; -- 38400 bauds bit rate divisor value
constant BR_DIVISOR_57600 : integer := 16; -- 57600 bauds bit rate divisor value
constant BR_DIVISOR_115200 : integer := 8; -- 115200 bauds bit rate divisor value
constant BR_DIVISOR_230400 : integer := 4; -- 230400 bauds bit rate divisor value
constant BR_DIVISOR_460800 : integer := 2; -- 460800 bauds bit rate divisor value
constant BR_DIVISOR_921600 : integer := 1; -- 921600 bauds bit rate divisor value
-------------------------------------------------------------------------------
-- SIGNAL DECLARATION
-------------------------------------------------------------------------------
type tx_state_m is (IDLE,LOAD_TX_DATA,TX_DATA,TX_STOP);
type rx_state_m is (IDLE,START_RX,EDGE_RX,SHIFT_RX,STOP_RX,RX_OVF);
signal tx_state : tx_state_m;
signal rx_state : rx_state_m;
signal br_divisor : std_logic_vector(9 downto 0); -- Bit rate divisor
signal top_ref_baud : std_logic; -- Top reference baud 921600
signal tx_top_baud : std_logic; -- Transmit Top selected baud
signal rx_top_baud : std_logic; -- Transmit Top selected baud
signal tx_data_s : std_logic_vector(7 downto 0); -- Sample Transmited data input
signal tx_data_reg : std_logic_vector(10 downto 0); -- Transmited data register
signal rx_data_i : std_logic_vector(7 downto 0); -- Intermediary Received data
signal rx_parity_err_i : std_logic; -- Intermediary parity error status signal
signal clr_rx_baud : std_logic; -- clear Receive baud counter divisor counter
-------------------------------------------------------------------------------
-- FUNCTION DECLARATION
------------------------------------------------------------------------------
function parity (data: std_logic_vector; parity_type : std_logic) return std_logic is
variable tmp : std_logic;
begin
if parity_type = EVEN_PARITY then -- making the number of data even
tmp := '0';
for i in data'range loop
tmp := tmp xor data(i);
end loop;
elsif parity_type = ODD_PARITY then -- making the number of data odd
tmp := '1';
for i in data'range loop
tmp := tmp xnor data(i);
end loop;
end if;
 
return tmp;
end function;
begin
-------------------------------------------------------------------------------
-- This process is used to select bit rate divisor associated to baud_sel
-- vector value. The bit rate divisor is necessary to obtain the correct baud
-- once the 921600 baud is obtain by clock division
-------------------------------------------------------------------------------
baud_sel_proc:
process(reset, clk)
begin
if reset = '1' then
br_divisor <= (others => '0');
elsif rising_edge(clk) then
case baud_sel is
when x"0" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_300,br_divisor'length)); -- 300 bauds
when x"1" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_1200,br_divisor'length)); -- 1200 bauds
when x"2" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_2400,br_divisor'length)); -- 2400 bauds
when x"3" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_4800,br_divisor'length)); -- 4800 bauds
when x"4" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_9600,br_divisor'length)); -- 9600 bauds
when x"5" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_19200,br_divisor'length)); -- 19200 bauds
when x"6" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_38400,br_divisor'length)); -- 38400 bauds
when x"7" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_57600,br_divisor'length)); -- 57600 bauds
when x"8" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_115200,br_divisor'length)); -- 115200 bauds
when x"9" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_230400,br_divisor'length)); -- 230400 bauds
when x"A" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_460800,br_divisor'length)); -- 460800 bauds
when x"B" => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_921600,br_divisor'length)); -- 921600 bauds
when others => br_divisor <= std_logic_vector(to_unsigned(BR_DIVISOR_115200,br_divisor'length));
end case;
end if;
end process;
 
-------------------------------------------------------------------------------
-- This process is neccessary to obtain the 921600 baud. This baud is obtained by
-- dividing clock frequency with the followed equation CLK_DIVISOR = Fclk/921600
-- This baud will be the reference one to obtain others ones.
-------------------------------------------------------------------------------
baud_ref_proc:
process(reset, clk)
variable clk_divisor_cnt : integer range 0 to CLK_DIVISOR; -- Clock divisier counter
begin
if reset = '1' then
top_ref_baud <= '0';
clk_divisor_cnt := 0;
elsif rising_edge(clk) then
top_ref_baud <= '0';
clk_divisor_cnt := clk_divisor_cnt + 1;
if clk_divisor_cnt = CLK_DIVISOR then
top_ref_baud <= '1';
clk_divisor_cnt := 0;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process is necessary to obtain the selected bit rate by divising the
-- 921600 reference baud with baud selected value.
-------------------------------------------------------------------------------
tx_baud_proc:
process(reset, clk)
variable tx_br_divisor_cnt : integer range 0 to BR_DIVISOR_300;
begin
if reset = '1' then
tx_top_baud <= '0';
tx_br_divisor_cnt := 0;
elsif rising_edge(clk) then
tx_top_baud <= '0';
if top_ref_baud = '1' then
tx_br_divisor_cnt := tx_br_divisor_cnt + 1;
if tx_br_divisor_cnt = br_divisor then
tx_top_baud <= '1';
tx_br_divisor_cnt := 0;
end if;
end if;
end if;
end process;
rx_baud_proc:
process(reset, clk)
variable rx_br_divisor_cnt : std_logic_vector(9 downto 0);
begin
if reset = '1' then
rx_top_baud <= '0';
rx_br_divisor_cnt := (others => '0');
elsif rising_edge(clk) then
rx_top_baud <= '0';
if clr_rx_baud = '1' then
rx_br_divisor_cnt := (others => '0');
elsif top_ref_baud = '1' and rx_state /= IDLE then
rx_br_divisor_cnt := rx_br_divisor_cnt + 1;
if rx_br_divisor_cnt(8 downto 0) = br_divisor(9 downto 1) then
rx_top_baud <= '1';
rx_br_divisor_cnt := (others => '0');
end if;
end if;
end if;
end process;
 
 
-------------------------------------------------------------------------------
-- Transmition process
-------------------------------------------------------------------------------
tx_proc:
process(reset, clk)
variable tx_bit_cnt : integer;
begin
if reset = '1' then
tx_data_s <= (others => '0');
tx_data_reg <= (others => '1');
tx_ch_rdy <= '0';
elsif rising_edge(clk) then
case tx_state is
when IDLE =>
if tx_data_en = '1' then
tx_data_s <= tx_data_in;
tx_ch_rdy <= '0';
tx_state <= LOAD_TX_DATA;
else
tx_ch_rdy <= '1';
end if;
 
when LOAD_TX_DATA =>
if tx_top_baud = '1' then
if parity_en = '1' then
-- start + data + parity + stop
tx_bit_cnt := 8 + 3;
tx_data_reg(10 downto 0) <= '1' & parity(tx_data_s,parity_type) & tx_data_s(7 downto 0) & '0';
else
-- start + data + stop
tx_bit_cnt := 8 + 2;
tx_data_reg(10 downto 0) <= "11" & tx_data_s(7 downto 0) & '0';
end if;
tx_state <= TX_DATA;
end if;
when TX_DATA =>
if tx_top_baud = '1' then
tx_data_reg(10 downto 0) <= '1' & tx_data_reg(10 downto 1);
tx_bit_cnt := tx_bit_cnt-1;
if tx_bit_cnt = 1 then
tx_state <= TX_STOP;
end if;
end if;
when TX_STOP => -- stop bit
if tx_top_baud = '1' then
tx_state <= IDLE;
end if;
when others =>
null;
end case;
end if;
end process;
tx_data_serial <= tx_data_reg(0);
-------------------------------------------------------------------------------
-- Reception process
-------------------------------------------------------------------------------
process(reset, clk)
variable rx_bit_cnt : integer;
begin
if reset = '1' then
rx_data_out <= (others => '0');
rx_data_en <= '0';
rx_ovf_err <= '0';
rx_data_i <= (others => '0');
rx_parity_err <= '0';
rx_parity_err_i<= '0';
elsif rising_edge(clk) then
 
clr_rx_baud <= '0';
rx_ovf_err <= '0';
rx_parity_err <= '0';
rx_parity_err_i<= '0';
rx_data_en <= '0';
case rx_state is
when IDLE => -- Wait start bit
if top_ref_baud = '1' then
if rx_data_serial = '0' then
clr_rx_baud <= '1';
rx_state <= START_RX;
rx_bit_cnt := 1;
end if;
end if;
 
 
when START_RX =>
if rx_top_baud = '1' then
if rx_data_serial = '1' then
rx_state <= RX_OVF;
else
rx_state <= EDGE_RX;
end if;
end if;
when EDGE_RX =>
if rx_top_baud = '1' then
if (parity_en = '1' and rx_bit_cnt = 10) or -- start + data + parity + stop
(parity_en = '0' and rx_bit_cnt = 9) then -- start + data + stop
rx_state <= STOP_RX;
else -- data
rx_state <= SHIFT_RX;
end if;
end if;
when SHIFT_RX =>
if rx_top_baud = '1' then
rx_bit_cnt := rx_bit_cnt + 1;
if not((parity_en = '1' and rx_bit_cnt = 10)) then -- start + data + parity + stop
rx_data_i(7 downto 0) <= rx_data_serial & rx_data_i(7 downto 1);
else
if parity(rx_data_i,parity_type) /= rx_data_serial then
rx_parity_err_i <= '1';
end if;
end if;
rx_state <= EDGE_RX;
end if;
when STOP_RX =>
-- if rx_top_baud = '1' then
rx_data_out <= rx_data_i;
rx_parity_err <= rx_parity_err_i;
rx_ovf_err <= '0';
rx_data_en <= '1';
rx_state <= IDLE;
-- end if;
when RX_OVF => -- Overframe error
rx_ovf_err <= '1';
if rx_data_serial = '1' then
rx_state <= IDLE;
end if;
when others => null;
end case;
end if;
end process;
end rtl;
/trunk/modelsim/wave.do
0,0 → 1,46
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider uart_serial
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/reset
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/clk
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/rx_data_serial
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/rx_data_i
add wave -noupdate -format Literal -radix hexadecimal /tb_uart/uart_serial_inst/rx_data_out
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/line__294/rx_bit_cnt
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/rx_state
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/rx_data_en
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/rx_ovf_err
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/rx_parity_err
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/tx_data_serial
add wave -noupdate -format Literal -radix hexadecimal /tb_uart/uart_serial_inst/tx_data_in
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/tx_data_en
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/tx_ch_rdy
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/baud_sel
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/parity_en
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/parity_type
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/tx_state
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/br_divisor
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/top_ref_baud
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/tx_top_baud
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/rx_top_baud
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/tx_data_s
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/tx_data_reg
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/rx_parity_err_i
add wave -noupdate -format Logic /tb_uart/uart_serial_inst/clr_rx_baud
add wave -noupdate -format Literal /tb_uart/uart_serial_inst/rx_baud_proc/rx_br_divisor_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {7654653900 ps} 0} {{Cursor 2} {484386792 ps} 0} {{Cursor 3} {225740100 ps} 0} {{Cursor 4} {17533019 ps} 0} {{Cursor 5} {0 ps} 0}
configure wave -namecolwidth 132
configure wave -valuecolwidth 40
configure wave -justifyvalue right
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {105 us}
/trunk/modelsim/run.tcl
0,0 → 1,3
 
vsim work.tb_uart
do wave.do
/trunk/modelsim/compile.tcl
0,0 → 1,22
# if simulation was running then quit
quit -sim
 
set origin [pwd]
 
if {![file isdirectory work]} {
exec vlib work
}
 
#cd $origin
 
# map lpm library, for ModelSim to find lpm objects
exec vmap lpm {$MODEL_TECH/../altera/vhdl/220model}
 
# map the work library
exec vmap work work
 
 
# compile all files
 
vcom -work work -2002 -explicit -check_synthesis ../sources/uart_serial.vhd
vcom -work work -2002 -explicit -check_synthesis ../testbench/tb_uart.vhd
/trunk/modelsim/uart.mpf
0,0 → 1,292
[Library]
 
; Altera specific primitive library mappings
 
vital2000 = $MODEL_TECH/../vital2000
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
std = $MODEL_TECH/../std
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
apex20k = $MODEL_TECH/../altera/vhdl/apex20k
apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
apexii = $MODEL_TECH/../altera/vhdl/apexii
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
mercury = $MODEL_TECH/../altera/vhdl/mercury
max = $MODEL_TECH/../altera/vhdl/max
maxii = $MODEL_TECH/../altera/vhdl/maxii
stratix = $MODEL_TECH/../altera/vhdl/stratix
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
hcstratix = $MODEL_TECH/../altera/vhdl/hcstratix
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
sgate = $MODEL_TECH/../altera/vhdl/sgate
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
apexii_ver = $MODEL_TECH/../altera/verilog/apexii
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
mercury_ver = $MODEL_TECH/../altera/verilog/mercury
max_ver = $MODEL_TECH/../altera/verilog/max
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
hcstratix_ver = $MODEL_TECH/../altera/verilog/hcstratix
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
work = work
[vcom]
; Turn on VHDL-1993 as the default. Normally is off.
; VHDL93 = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; .ini file has Explict enable so that std_logic_signed/unsigned
; will match synthesis tools behavior.
Explicit = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = false
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
 
; RequireConfigForAllDefaultBinding = 1
 
[vlog]
 
; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Turns on incremental compilation of modules
; Incremental = 1
 
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 1ps
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
UserTimeUnit = default
 
; Default run length
RunLength = 100 ps
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 1000
 
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; License = plus
 
; Stop the simulator after an assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
 
; Assertion File - alternate file for storing assertion messages
; AssertFile = assert.log
 
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
;CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format. For VHDL, PathSeparator = /
; for Verilog, PathSeparator = .
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Disable assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Default force kind. May be freeze, drive, or deposit
; or in other terms, fixed, wired or charged.
; DefaultForceKind = freeze
 
; If zero, open files when elaborated
; else open files on first read or write
; DelayFileOpen = 0
 
; Control VHDL files opened for write
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control number of VHDL files open concurrently
; This number should always be less then the
; current ulimit setting for max file descriptors
; 0 = unlimited
ConcurrentFileLimit = 40
 
; This controls the number of hierarchical regions displayed as
; part of a signal name shown in the waveform window. The default
; value or a value of zero tells VSIM to display the full name.
; WaveSignalNameWidth = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit
; packages.
; NumericStdNoWarnings = 1
 
; Control the format of a generate statement label. Don't quote it.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is to be compressed.
; CheckpointCompressMode = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {//saturne/martinx/vhdl/mustang/evalmustang/evalmusin/dp2_uart_serial/sources/uart_serial.vhd 0 1} {//saturne/martinx/vhdl/mustang/evalmustang/evalmusin/dp2_uart_serial/testbench/tb_uart.vhd 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1

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