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/utosnet/trunk/gateware/uTosNet_spi/dataRegister.xco
0,0 → 1,89
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Mon Nov 02 14:50:24 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=dataRegister
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=true
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=32
CSET read_width_b=32
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=64
CSET write_width_a=32
CSET write_width_b=32
# END Parameters
GENERATE
# CRC: af90b416
/utosnet/trunk/gateware/uTosNet_spi/uTosNet_spi.vhd
0,0 → 1,174
----------------------------------------------------------------------------------
-- Company: University of Southern Denmark
-- Engineer: Simon Falsig
--
-- Create Date: 19/3/2010
-- Design Name: uTosNet
-- Module Name: uTosNet_spi - Behavioral
-- Project Name: uTosNet
-- Target Devices: SDU XC3S50AN Board
-- Tool versions: Xilinx ISE 11.4
-- Description: PseudoTosNet is designed to provide an interface similar to
-- the full-blown TosNet core, but usable on the SDU XC3S50AN
-- Board. It features a SPI module which is made for use in
-- conjunction with a Digi Connect ME 9210 with the Generic
-- TosNet Masternode application. By using this combination, it
-- is possible to access the blockram from any Ethernet-enabled
-- device.
--
-- Revision:
-- Revision 0.10 - Initial release
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uTosNet_spi is
Port ( clk_50M : in STD_LOGIC;
spi_miso : out STD_LOGIC;
spi_mosi : in STD_LOGIC;
spi_clk : in STD_LOGIC;
spi_en : in STD_LOGIC;
dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0);
dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0);
dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0);
dataReg_clk : in STD_LOGIC;
dataReg_writeEnable : in STD_LOGIC);
end uTosNet_spi;
 
architecture Behavioral of uTosNet_spi is
component dataRegister
Port ( clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR(0 downto 0);
addra : in STD_LOGIC_VECTOR(5 downto 0);
dina : in STD_LOGIC_VECTOR(31 downto 0);
douta : out STD_LOGIC_VECTOR(31 downto 0);
clkb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR(0 downto 0);
addrb : in STD_LOGIC_VECTOR(5 downto 0);
dinb : in STD_LOGIC_VECTOR(31 downto 0);
doutb : out STD_LOGIC_VECTOR(31 downto 0));
end component;
signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0);
signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0);
signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0);
signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0);
signal int_dataReg_clk : STD_LOGIC;
signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0);
signal readData : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal writeAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
signal readAddress : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
signal doWrite : STD_LOGIC := '0';
signal doRead : STD_LOGIC := '0';
signal int_spi_mosi : STD_LOGIC;
signal int_spi_clk : STD_LOGIC;
signal int_spi_en : STD_LOGIC;
signal last_spi_clk : STD_LOGIC;
signal dataInBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal dataOutBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
signal bitCounter : STD_LOGIC_VECTOR(6 downto 0) := (others => '0');
begin
 
dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:)
 
dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister
Port map ( clka => dataReg_clk, --PortA is used for the user application
wea => dataReg_writeEnable_V, --
addra => dataReg_addr, --
dina => dataReg_dataIn, --
douta => dataReg_dataOut, --
clkb => int_dataReg_clk, --PortB is used for the SPI interface
web => int_dataReg_we, --
addrb => int_dataReg_addr, --
dinb => int_dataReg_dataIn, --
doutb => int_dataReg_dataOut); --
 
--Synchronize inputs
process(clk_50M)
begin
if(clk_50M = '0' and clk_50M'event) then
int_spi_mosi <= spi_mosi;
int_spi_clk <= spi_clk;
int_spi_en <= spi_en;
end if;
end process;
--SPI Process
process(clk_50M)
begin
if(clk_50M = '1' and clk_50M'event) then
last_spi_clk <= int_spi_clk; --Save current value to use for manual edge triggering
 
if(int_spi_en = '1') then --SPI is not enabled (spi_en is active low)
bitCounter <= (others => '0'); --Reset the bitcounter
if((doWrite = '1') and (int_dataReg_we = "0")) then --If a write was requested in the previously received command,
int_dataReg_addr <= writeAddress; -- then prepare it,
int_dataReg_dataIn <= dataInBuffer; -- the data to write are those left in the input buffer,
int_dataReg_we <= "1"; --
int_dataReg_clk <= '0'; --
elsif((doWrite = '1') and (int_dataReg_clk = '0')) then --
int_dataReg_clk <= '1'; -- and perform it by pulling the dataReg clock high
doWrite <= '0'; --Write is done
else --If there aren't any writes to perform,
int_dataReg_clk <= '0'; -- just clear the various signals
int_dataReg_we <= "0"; --
doRead <= '0'; --
doWrite <= '0'; --
end if;
else --SPI is enabled
if(int_spi_clk = '0' and last_spi_clk = '1') then --Falling edge on spi_clk
dataInBuffer <= dataInBuffer(30 downto 0) & int_spi_mosi; --Read next received bit into the input buffer,
bitCounter <= bitCounter + 1; -- and increment the bitcounter
elsif(int_spi_clk = '1' and last_spi_clk = '0') then --Rising edge on spi_clk
spi_miso <= dataOutBuffer(31); --Write out the next bit from the output buffer,
dataOutBuffer <= dataOutBuffer(30 downto 0) & '0'; -- and left-shift the buffer
end if;
case bitCounter is --Parse the command
when "0000101" => --Bit 27 (the 5th read bit),
doRead <= dataInBuffer(0); -- contains the 'doRead' flag
when "0010000" => --Bits 16-25 (available when 16 bits have been read),
readAddress <= dataInBuffer(5 downto 0); -- contain the address to read from
when "0010001" => --Bit 15 (the 17th read bit),
int_dataReg_addr <= readAddress; -- doesn't contain anything useful, but we can easily use the timeslot for reading from the dataregister
int_dataReg_we <= "0"; --
int_dataReg_clk <= '0'; --
when "0010010" => --Bit 14 (the 18th read bit),
int_dataReg_clk <= '1'; -- still nothing, now performing the read by pulling the dataregister clock high
when "0010011" => --Bit 13 (the 19th read bit),
int_dataReg_clk <= '0'; -- the read is finished,
readData <= int_dataReg_dataOut; -- and the read value is stored
when "0010101" => --Bit 11 (the 21st read bit),
doWrite <= dataInBuffer(0); -- contains the 'doWrite' flag
when "0011111" => --Bit 1 (the 31st read bit),
if(doRead = '1') then -- we're not using this bit for anything right now, but we need to put the previously read data value into the output buffer now
dataOutBuffer <= readData; --
else --If a read was not requested,
dataOutBuffer <= (others => '0'); -- the output buffer is just filled with zeros instead
end if;
when "0100000" => --Bits 9-0 (available when 32 bits have been read),
writeAddress <= dataInBuffer(5 downto 0); -- contain the address to write to
when others => --Other bit positions are ignored
end case;
end if;
end if;
end process;
end Behavioral;
/utosnet/trunk/gateware/uTosNet_uart/dataRegister.xco
0,0 → 1,89
##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Mon Nov 02 14:50:24 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s50an
SET devicefamily = spartan3a
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=dataRegister
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=true
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=32
CSET read_width_b=32
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=64
CSET write_width_a=32
CSET write_width_b=32
# END Parameters
GENERATE
# CRC: af90b416
/utosnet/trunk/gateware/uTosNet_uart/uTosNet_uart.vhd
0,0 → 1,497
----------------------------------------------------------------------------------
-- Company: University of Southern Denmark
-- Engineer: Simon Falsig
--
-- Create Date: 19/03/2010
-- Design Name: uTosNet
-- Module Name: uTosNet_usb - Behavioral
-- Project Name: uTosNet
-- Target Devices: SDU XC3S50AN Board
-- Tool versions: Xilinx ISE 11.4
-- Description: This module implements a very simple ASCII based protocol over
-- a uart. Data can be read and written from and to one port of a
-- dual-port blockRAM, where the other blockRAM port is available
-- to the user application. Communication takes place at the fol-
-- lowing settings:
-- Baudrate: 115200 kbps
-- Parity: none
-- Bits: 8 data bits, 1 stop bit
-- Flowcontrol: none
-- The protocol format can be seen in the documentation files.
--
-- Focus has mostly been on a simple implementation, as the
-- module is to be used during courses at the university.
--
-- Dependencies: The module uses the uart implementation from Ken Chapmans
-- PicoBlaze. More specifically the following files:
-- uart_rx.vhd
-- kcuart_rx.vhd
-- bbfifo_16x8.vhd
-- uart_tx.vhd
-- kcuart_tx.vhd
-- These files can be downloaded from Xilinx:
-- https://secure.xilinx.com/webreg/register.do?group=picoblaze
--
-- It should not be hard to implement the module using another
-- uart implementation though.
--
-- Revision:
-- Revision 0.10 - Initial release
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uTosNet_uart is
Port ( clk_50M : in STD_LOGIC;
serial_out : out STD_LOGIC;
serial_in : in STD_LOGIC;
dataReg_addr : in STD_LOGIC_VECTOR(5 downto 0);
dataReg_dataIn : in STD_LOGIC_VECTOR(31 downto 0);
dataReg_dataOut : out STD_LOGIC_VECTOR(31 downto 0);
dataReg_clk : in STD_LOGIC;
dataReg_writeEnable : in STD_LOGIC);
end uTosNet_uart;
 
architecture Behavioral of uTosNet_uart is
 
component dataRegister
Port ( clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR(0 downto 0);
addra : in STD_LOGIC_VECTOR(5 downto 0);
dina : in STD_LOGIC_VECTOR(31 downto 0);
douta : out STD_LOGIC_VECTOR(31 downto 0);
clkb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR(0 downto 0);
addrb : in STD_LOGIC_VECTOR(5 downto 0);
dinb : in STD_LOGIC_VECTOR(31 downto 0);
doutb : out STD_LOGIC_VECTOR(31 downto 0));
end component;
 
component uart_rx
Port ( serial_in : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
read_buffer : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
buffer_data_present : out STD_LOGIC;
buffer_full : out STD_LOGIC;
buffer_half_full : out STD_LOGIC;
clk : in STD_LOGIC);
end component;
 
component uart_tx
Port ( serial_out : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
write_buffer : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
buffer_full : out STD_LOGIC;
buffer_half_full : out STD_LOGIC;
clk : in STD_LOGIC);
end component;
signal baudCount : integer range 0 to 36 :=0;
signal en_16_x_baud : STD_LOGIC;
signal readFromUart : STD_LOGIC;
signal rxData : STD_LOGIC_VECTOR(7 downto 0);
signal rxDataPresent : STD_LOGIC;
signal rxFull : STD_LOGIC;
signal rxHalfFull : STD_LOGIC;
 
signal txData : STD_LOGIC_VECTOR(7 downto 0);
signal writeToUart : STD_LOGIC;
signal txFull : STD_LOGIC;
signal txHalfFull : STD_LOGIC;
 
constant UARTDIV : STD_LOGIC_VECTOR(5 downto 0) := "011010";
 
type STATES is (IDLE, COMMAND_IN, WAIT1, REG_IN, WAIT2, INDEX_IN, WAIT3, SPACE_IN, WAIT4, DATA_IN, WAIT_DATA_IN, DATA_OUT, PERFORM_READ_SETUP, PERFORM_READ_CLK, PERFORM_READ_DONE, PERFORM_WRITE_SETUP, PERFORM_WRITE_CLK, PERFORM_WRITE_DONE);
signal state : STATES := IDLE;
signal nextState : STATES := IDLE;
 
type COMMANDS is (CMD_NONE, CMD_READ, CMD_WRITE, CMD_COMMIT_READ, CMD_COMMIT_WRITE);
 
signal currentCommand : COMMANDS := CMD_NONE;
 
signal int_dataReg_dataIn : STD_LOGIC_VECTOR(31 downto 0);
signal int_dataReg_addr : STD_LOGIC_VECTOR(5 downto 0);
signal int_dataReg_dataOut : STD_LOGIC_VECTOR(31 downto 0);
signal int_dataReg_we : STD_LOGIC_VECTOR(0 downto 0);
signal int_dataReg_clk : STD_LOGIC;
signal dataReg_writeEnable_V : STD_LOGIC_VECTOR(0 downto 0);
signal inputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal outputBuffer : STD_LOGIC_VECTOR(31 downto 0) := (others => '1');
signal readCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal writeCounter : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal currentReg : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal currentIndex : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal commitRead : STD_LOGIC := '0';
signal commitWrite : STD_LOGIC := '0';
 
begin
 
dataReg_writeEnable_V(0) <= dataReg_writeEnable; --Conversion from std_logic to std_logic_vector(0 downto 0) - to allow for dataReg_writeEnable to be a std_logic, which is nicer...:)
 
dataRegisterInst : dataRegister --Instantation of the dual-port blockram used for the dataregister
Port map ( clka => dataReg_clk, --PortA is used for the user application
wea => dataReg_writeEnable_V, --
addra => dataReg_addr, --
dina => dataReg_dataIn, --
douta => dataReg_dataOut, --
clkb => int_dataReg_clk, --PortB is used for the SPI interface
web => int_dataReg_we, --
addrb => int_dataReg_addr, --
dinb => int_dataReg_dataIn, --
doutb => int_dataReg_dataOut); --
 
rx_inst: uart_rx
Port map ( serial_in => serial_in,
data_out => rxData,
read_buffer => readFromUart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rxDataPresent,
buffer_full => rxFull,
buffer_half_full => rxHalfFull,
clk => clk_50M );
 
tx_inst : uart_tx
Port map ( serial_out => serial_out,
data_in => txData,
write_buffer => writeToUart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_full => txFull,
buffer_half_full => txHalfFull,
clk => clk_50M);
 
baudTimer_inst: process(clk_50M)
begin
if(clk_50M'event and clk_50M='1')then
if(baudCount = UARTDIV)then
baudCount <= 0;
en_16_x_baud <= '1';
else
baudCount <= baudCount + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baudTimer_inst;
 
process(clk_50M)
begin
if(clk_50M = '1' and clk_50M'event) then
state <= nextState;
readFromUart <= '0';
writeToUart <= '0';
case state is
when IDLE =>
currentCommand <= CMD_NONE;
readCounter <= (others => '0');
writeCounter <= (others => '0');
commitRead <= '0';
commitWrite <= '0';
when COMMAND_IN =>
commitRead <= '0';
commitWrite <= '0';
if(rxDataPresent = '1') then
case rxData is
when "01110010" => --'r'
currentCommand <= CMD_READ;
when "01110111" => --'w'
currentCommand <= CMD_WRITE;
when "01110100" => --'t'
commitRead <= '1';
currentCommand <= CMD_NONE;
when "01100011" => --'c'
commitWrite <= '1';
currentCommand <= CMD_NONE;
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
end if;
when WAIT1 =>
when REG_IN =>
if(rxDataPresent = '1') then
case rxData is
when "00110000" =>
currentReg <= "000";
when "00110001" =>
currentReg <= "001";
when "00110010" =>
currentReg <= "010";
when "00110011" =>
currentReg <= "011";
when "00110100" =>
currentReg <= "100";
when "00110101" =>
currentReg <= "101";
when "00110110" =>
currentReg <= "110";
when "00110111" =>
currentReg <= "111";
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
end if;
when WAIT2 =>
when INDEX_IN =>
if(rxDataPresent = '1') then
case rxData is
when "00110000" =>
currentIndex <= "000";
when "00110001" =>
currentIndex <= "001";
when "00110010" =>
currentIndex <= "010";
when "00110011" =>
currentIndex <= "011";
when "00110100" =>
currentIndex <= "100";
when "00110101" =>
currentIndex <= "101";
when "00110110" =>
currentIndex <= "110";
when "00110111" =>
currentIndex <= "111";
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
end if;
when WAIT3 =>
when SPACE_IN =>
if(rxDataPresent = '1') then
if(not(rxData = "00100000")) then
currentCommand <= CMD_NONE;
end if;
readFromUart <= '1';
end if;
when WAIT4 =>
when DATA_IN =>
if(rxDataPresent = '1') then
case rxData is
when "00110000" => --'0'
inputBuffer <= inputBuffer(27 downto 0) & "0000";
when "00110001" => --'1'
inputBuffer <= inputBuffer(27 downto 0) & "0001";
when "00110010" => --'2'
inputBuffer <= inputBuffer(27 downto 0) & "0010";
when "00110011" => --'3'
inputBuffer <= inputBuffer(27 downto 0) & "0011";
when "00110100" => --'4'
inputBuffer <= inputBuffer(27 downto 0) & "0100";
when "00110101" => --'5'
inputBuffer <= inputBuffer(27 downto 0) & "0101";
when "00110110" => --'6'
inputBuffer <= inputBuffer(27 downto 0) & "0110";
when "00110111" => --'7'
inputBuffer <= inputBuffer(27 downto 0) & "0111";
when "00111000" => --'8'
inputBuffer <= inputBuffer(27 downto 0) & "1000";
when "00111001" => --'9'
inputBuffer <= inputBuffer(27 downto 0) & "1001";
when "01100001" => --'a'
inputBuffer <= inputBuffer(27 downto 0) & "1010";
when "01100010" => --'b'
inputBuffer <= inputBuffer(27 downto 0) & "1011";
when "01100011" => --'c'
inputBuffer <= inputBuffer(27 downto 0) & "1100";
when "01100100" => --'d'
inputBuffer <= inputBuffer(27 downto 0) & "1101";
when "01100101" => --'e'
inputBuffer <= inputBuffer(27 downto 0) & "1110";
when "01100110" => --'f'
inputBuffer <= inputBuffer(27 downto 0) & "1111";
when others =>
currentCommand <= CMD_NONE;
end case;
readFromUart <= '1';
readCounter <= readCounter + 1;
end if;
when WAIT_DATA_IN =>
when DATA_OUT =>
writeToUart <= '1';
if(writeCounter = 8) then
txData <= "00100000"; --Transmit a space to make thinks look nicer...:)
else
case outputBuffer(31 downto 28) is
when "0000" => --'0'
txData <= "00110000";
when "0001" => --'1'
txData <= "00110001";
when "0010" => --'2'
txData <= "00110010";
when "0011" => --'3'
txData <= "00110011";
when "0100" => --'4'
txData <= "00110100";
when "0101" => --'5'
txData <= "00110101";
when "0110" => --'6'
txData <= "00110110";
when "0111" => --'7'
txData <= "00110111";
when "1000" => --'8'
txData <= "00111000";
when "1001" => --'9'
txData <= "00111001";
when "1010" => --'a'
txData <= "01100001";
when "1011" => --'b'
txData <= "01100010";
when "1100" => --'c'
txData <= "01100011";
when "1101" => --'d'
txData <= "01100100";
when "1110" => --'e'
txData <= "01100101";
when "1111" => --'f'
txData <= "01100110";
when others =>
end case;
end if;
outputBuffer <= outputBuffer(27 downto 0) & "0000";
writeCounter <= writeCounter + 1;
when PERFORM_READ_SETUP =>
int_dataReg_addr <= currentReg & currentIndex;
int_dataReg_we <= "0";
int_dataReg_clk <= '0';
when PERFORM_READ_CLK =>
int_dataReg_clk <= '1';
when PERFORM_READ_DONE =>
outputBuffer <= int_dataReg_dataOut;
int_dataReg_clk <= '0';
when PERFORM_WRITE_SETUP =>
int_dataReg_addr <= currentReg & currentIndex;
int_dataReg_dataIn <= inputBuffer;
int_dataReg_we <= "1";
int_dataReg_clk <= '0';
when PERFORM_WRITE_CLK =>
int_dataReg_clk <= '1';
when PERFORM_WRITE_DONE =>
int_dataReg_we <= "0";
int_dataReg_clk <= '0';
end case;
end if;
end process;
process(state, rxDataPresent, currentCommand, readCounter, writeCounter)
begin
if((currentCommand = CMD_NONE) and not ((state = COMMAND_IN) or (state = IDLE))) then
nextState <= IDLE;
else
case state is
when IDLE =>
nextState <= COMMAND_IN;
when COMMAND_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT1;
else
nextState <= COMMAND_IN;
end if;
when WAIT1 =>
if(rxDataPresent = '0') then
nextState <= REG_IN;
else
nextState <= WAIT1;
end if;
when REG_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT2;
else
nextState <= REG_IN;
end if;
when WAIT2 =>
if(rxDataPresent = '0') then
nextState <= INDEX_IN;
else
nextState <= WAIT2;
end if;
when INDEX_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT3;
else
nextState <= INDEX_IN;
end if;
when WAIT3 =>
if(rxDataPresent = '0') then
if(currentCommand = CMD_READ) then
nextState <= PERFORM_READ_SETUP;
else
nextState <= SPACE_IN;
end if;
else
nextState <= WAIT3;
end if;
when SPACE_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT4;
else
nextState <= SPACE_IN;
end if;
when WAIT4 =>
if(rxDataPresent = '0') then
nextState <= DATA_IN;
else
nextState <= WAIT4;
end if;
when DATA_IN =>
if(rxDataPresent = '1') then
nextState <= WAIT_DATA_IN;
else
nextState <= DATA_IN;
end if;
when WAIT_DATA_IN =>
if(rxDataPresent = '0') then
if(readCounter = 8) then
nextState <= PERFORM_WRITE_SETUP;
else
nextState <= DATA_IN;
end if;
else
nextState <= WAIT_DATA_IN;
end if;
when DATA_OUT =>
if(writeCounter = 8) then
nextState <= IDLE;
else
nextState <= DATA_OUT;
end if;
when PERFORM_READ_SETUP =>
nextState <= PERFORM_READ_CLK;
when PERFORM_READ_CLK =>
nextState <= PERFORM_READ_DONE;
when PERFORM_READ_DONE =>
nextState <= DATA_OUT;
when PERFORM_WRITE_SETUP =>
nextState <= PERFORM_WRITE_CLK;
when PERFORM_WRITE_CLK =>
nextState <= PERFORM_WRITE_DONE;
when PERFORM_WRITE_DONE =>
nextState <= IDLE;
end case;
end if;
end process;
end Behavioral;
 

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