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URL https://opencores.org/ocsvn/wb_async_mem_bridge/wb_async_mem_bridge/trunk

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/wb_async_mem_bridge/trunk/src/sync.v
0,0 → 1,26
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module sync (
input async_sig,
output sync_out,
input clk
);
 
reg [1:2] resync;
 
always @(posedge clk)
begin
// update history shifter.
resync <= {async_sig , resync[1]};
end
assign sync_out = resync[2];
 
endmodule
 
/wb_async_mem_bridge/trunk/src/wb_async_mem_bridge.v
0,0 → 1,168
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
wb_async_mem_bridge
#(
parameter DW = 32,
parameter AW = 32
)
(
input [(DW-1):0] wb_data_i,
output [(DW-1):0] wb_data_o,
output [(AW-1):0] wb_addr_o,
output [3:0] wb_sel_o,
output wb_we_o,
output wb_cyc_o,
output wb_stb_o,
input wb_ack_i,
input wb_err_i,
input wb_rty_i,
inout [(DW-1):0] mem_d,
input [(AW-1):0] mem_a,
input mem_oe_n,
input [3:0] mem_bls_n,
input mem_we_n,
input mem_cs_n,
input wb_clk_i,
input wb_rst_i
);
 
// --------------------------------------------------------------------
// sync data & bls
wire [(DW-1):0] sync_mem_d;
wire [(AW-1):0] sync_mem_a;
wire [3:0] sync_mem_bls_n;
 
genvar i;
generate
for( i = 0; i < DW; i = i + 1 )
begin: sync_data_loop
sync i_sync( .async_sig(mem_d[i]), .sync_out(sync_mem_d[i]), .clk(wb_clk_i) );
end
endgenerate
 
generate
for( i = 0; i < AW; i = i + 1 )
begin: sync_addr_loop
sync i_sync( .async_sig(mem_a[i]), .sync_out(sync_mem_a[i]), .clk(wb_clk_i) );
end
endgenerate
 
generate
for( i = 0; i < 4; i = i + 1 )
begin: sync_bls_loop
sync i_sync( .async_sig(mem_bls_n[i]), .sync_out(sync_mem_bls_n[i]), .clk(wb_clk_i) );
end
endgenerate
// --------------------------------------------------------------------
// sync mem_cs_n & mem_oe_n & mem_we_n
wire sync_mem_oe_n, sync_mem_oe_n_rise, sync_mem_oe_n_fall;
wire sync_mem_cs_n;
wire sync_mem_we_n, sync_mem_we_n_rise, sync_mem_we_n_fall;
sync
(
.async_sig(),
.sync_out(),
.clk(wb_clk_i)
);
 
sync_edge_detect
i_sync_mem_oe_n(
.async_sig(mem_oe_n),
.sync_out(sync_mem_oe_n),
.clk(wb_clk_i),
.rise(sync_mem_oe_n_rise),
.fall(sync_mem_oe_n_fall)
);
 
sync
i_sync_mem_cs_n(
.async_sig(mem_cs_n),
.sync_out(sync_mem_cs_n),
.clk(wb_clk_i)
);
 
sync_edge_detect
i_sync_mem_we_n(
.async_sig(mem_we_n),
.sync_out(sync_mem_we_n),
.clk(wb_clk_i),
.rise(sync_mem_we_n_rise),
.fall(sync_mem_we_n_fall)
);
 
// --------------------------------------------------------------------
// state machine
wb_async_mem_sm #( .DW(DW), .AW(AW) )
i_wb_async_mem_sm
(
.wb_data_i(wb_data_i),
// .wb_data_o(wb_data_o),
.wb_addr_i(wb_addr_o),
// .wb_sel_o(wb_sel_o),
.wb_we_o(wb_we_o),
.wb_cyc_o(wb_cyc_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
.mem_d(sync_mem_d),
.mem_a(sync_mem_a),
.mem_oe_n(sync_mem_oe_n),
.mem_bls_n(sync_mem_bls_n),
.mem_we_n(sync_mem_we_n),
.mem_cs_n(sync_mem_cs_n),
.mem_we_n_fall(sync_mem_we_n_fall),
.mem_oe_n_fall(sync_mem_oe_n_fall),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i)
);
 
// --------------------------------------------------------------------
// wb_data_i flop
reg [(DW-1):0] wb_data_i_r;
always @(posedge wb_clk_i)
if(wb_ack_i)
wb_data_i_r <= wb_data_i;
// --------------------------------------------------------------------
// wb_data_o flop
reg [(DW-1):0] wb_data_o_r;
always @(posedge wb_clk_i)
if(~sync_mem_we_n)
wb_data_o_r <= sync_mem_d;
// --------------------------------------------------------------------
// outputs
assign mem_d = (~sync_mem_oe_n & ~sync_mem_cs_n ) ? wb_data_i_r : 'bz;
assign wb_addr_o = sync_mem_a;
assign wb_data_o = wb_data_o_r;
assign wb_sel_o = ~sync_mem_bls_n;
endmodule
 
/wb_async_mem_bridge/trunk/src/test_harness.v
0,0 → 1,96
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
test_harness(
inout [35:0] gpio_0,
inout [35:0] gpio_1,
input sys_clk_i,
input sys_rst_i
);
// --------------------------------------------------------------------
// wb_async_mem_bridge
wire [31:0] wb_data_i;
wire [31:0] wb_data_o;
wire [31:0] wb_addr_o;
wire [3:0] wb_sel_o;
wire wb_we_o;
wire wb_cyc_o;
wire wb_stb_o;
wire wb_ack_i;
wire wb_err_i;
wire wb_rty_i;
wb_async_mem_bridge i_wb_async_mem_bridge(
.wb_data_i(wb_data_i),
.wb_data_o(wb_data_o),
.wb_addr_o(wb_addr_o),
.wb_sel_o(wb_sel_o),
.wb_we_o(wb_we_o),
.wb_cyc_o(wb_cyc_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
.mem_d( gpio_1[31:0] ),
.mem_a( {8'h00, gpio_0[23:0]} ),
.mem_oe_n( gpio_0[30] ),
.mem_bls_n( { gpio_0[26], gpio_0[27], gpio_0[28], gpio_0[29] } ),
.mem_we_n( gpio_0[25] ),
.mem_cs_n( gpio_0[24] ),
.wb_clk_i(sys_clk_i),
.wb_rst_i(sys_rst_i)
);
// --------------------------------------------------------------------
// soc_ram
soc_ram
i_soc_ram_0(
.data(wb_data_o[7:0]),
.addr(wb_addr_o[7:2]),
.we(wb_we_o & wb_stb_o & wb_sel_o[0]),
.clk(sys_clk_i),
.q(wb_data_i[7:0])
);
soc_ram
i_soc_ram_1(
.data(wb_data_o[15:8]),
.addr(wb_addr_o[7:2]),
.we(wb_we_o & wb_stb_o & wb_sel_o[1]),
.clk(sys_clk_i),
.q(wb_data_i[15:8])
);
soc_ram
i_soc_ram_2(
.data(wb_data_o[23:16]),
.addr(wb_addr_o[7:2]),
.we(wb_we_o & wb_stb_o & wb_sel_o[2]),
.clk(sys_clk_i),
.q(wb_data_i[23:16])
);
soc_ram
i_soc_ram_3(
.data(wb_data_o[31:24]),
.addr(wb_addr_o[7:2]),
.we(wb_we_o & wb_stb_o & wb_sel_o[3]),
.clk(sys_clk_i),
.q(wb_data_i[31:24])
);
 
endmodule
 
/wb_async_mem_bridge/trunk/src/top.v
0,0 → 1,166
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module top(
//////////////////////// Clock Input ////////////////////////
input [1:0] clock_24, // 24 MHz
input [1:0] clock_27, // 27 MHz
input clock_50, // 50 MHz
input ext_clock, // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] key, // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [9:0] sw, // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] hex0, // Seven Segment Digit 0
output [6:0] hex1, // Seven Segment Digit 1
output [6:0] hex2, // Seven Segment Digit 2
output [6:0] hex3, // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
output [7:0] ledg, // LED Green[7:0]
output [9:0] ledr, // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
output uart_txd, // UART Transmitter
input uart_rxd, // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] dram_dq, // SDRAM Data bus 16 Bits
output [11:0] dram_addr, // SDRAM Address bus 12 Bits
output dram_ldqm, // SDRAM Low-byte Data Mask
output dram_udqm, // SDRAM High-byte Data Mask
output dram_we_n, // SDRAM Write Enable
output dram_cas_n, // SDRAM Column Address Strobe
output dram_ras_n, // SDRAM Row Address Strobe
output dram_cs_n, // SDRAM Chip Select
output dram_ba_0, // SDRAM Bank Address 0
output dram_ba_1, // SDRAM Bank Address 0
output dram_clk, // SDRAM Clock
output dram_cke, // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] fl_dq, // FLASH Data bus 8 Bits
output [21:0] fl_addr, // FLASH Address bus 22 Bits
output fl_we_n, // FLASH Write Enable
output fl_rst_n, // FLASH Reset
output fl_oe_n, // FLASH Output Enable
output fl_ce_n, // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] sram_dq, // SRAM Data bus 16 Bits
output [17:0] sram_addr, // SRAM Address bus 18 Bits
output sram_ub_n, // SRAM High-byte Data Mask
output sram_lb_n, // SRAM Low-byte Data Mask
output sram_we_n, // SRAM Write Enable
output sram_ce_n, // SRAM Chip Enable
output sram_oe_n, // SRAM Output Enable
//////////////////// SD Card Interface ////////////////////////
inout sd_dat, // SD Card Data
inout sd_dat3, // SD Card Data 3
inout sd_cmd, // SD Card Command Signal
output sd_clk, // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout i2c_sdat, // I2C Data
output i2c_sclk, // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input ps2_dat, // PS2 Data
input ps2_clk, // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input tdi, // CPLD -> FPGA (data in)
input tck, // CPLD -> FPGA (clk)
input tcs, // CPLD -> FPGA (CS)
output tdo, // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output vga_hs, // VGA H_SYNC
output vga_vs, // VGA V_SYNC
output [3:0] vga_r, // VGA Red[3:0]
output [3:0] vga_g, // VGA Green[3:0]
output [3:0] vga_b, // VGA Blue[3:0]
//////////////////// Audio CODEC ////////////////////////////
inout aud_adclrck, // Audio CODEC ADC LR Clock
input aud_adcdat, // Audio CODEC ADC Data
inout aud_daclrck, // Audio CODEC DAC LR Clock
output aud_dacdat, // Audio CODEC DAC Data
inout aud_bclk, // Audio CODEC Bit-Stream Clock
output aud_xck, // Audio CODEC Chip Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] gpio_0, // GPIO Connection 0
inout [35:0] gpio_1 // GPIO Connection 1
);
 
 
//---------------------------------------------------
// system wires
wire reset_switch;
wire sysclk = clock_24[0];
//---------------------------------------------------
// sync reset
sync
i_sync_reset(
.async_sig(~key[0]),
.sync_out(reset_switch),
.clk(sysclk)
);
 
//---------------------------------------------------
// FLED
reg [24:0] counter;
wire [7:0] fled;
 
always @(posedge sysclk or posedge reset_switch)
if(reset_switch)
counter <= 25'b0;
else
counter <= counter + 1;
assign fled[0] = sw[0];
assign fled[1] = sw[1];
assign fled[2] = sw[2];
assign fled[3] = sw[3];
assign fled[4] = sw[4];
assign fled[5] = sw[5];
assign fled[6] = sw[6];
assign fled[7] = counter[24];
 
//---------------------------------------------------
// test_harness
test_harness i_test_harness(
.gpio_0(gpio_0),
.gpio_1(gpio_1),
.sys_clk_i(sysclk),
.sys_rst_i(reset_switch)
);
//---------------------------------------------------
// outputs
// Turn off all display
assign hex0 = 7'h7f;
assign hex1 = 7'h7f;
assign hex2 = 7'h7f;
assign hex3 = 7'h7f;
// assign ledg = 8'hff;
assign ledg = fled;
assign ledr = 10'h000;
// All inout port turn to tri-state
assign dram_dq = 16'hzzzz;
assign fl_dq = 8'hzz;
assign sram_dq = 16'hzzzz;
assign sd_dat = 1'bz;
assign i2c_sdat = 1'bz;
assign aud_adclrck = 1'bz;
assign aud_daclrck = 1'bz;
assign aud_bclk = 1'bz;
assign gpio_0 = 36'hzzzzzzzzz;
assign gpio_1 = 36'hzzzzzzzzz;
endmodule
 
/wb_async_mem_bridge/trunk/src/wb_async_mem_sm.v
0,0 → 1,133
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
wb_async_mem_sm
#(
parameter DW = 32,
parameter AW = 32
)
(
input [(DW-1):0] wb_data_i,
output [(DW-1):0] wb_data_o,
input [(AW-1):0] wb_addr_i,
output [3:0] wb_sel_o,
output wb_we_o,
output wb_cyc_o,
output wb_stb_o,
input wb_ack_i,
input wb_err_i,
input wb_rty_i,
input [(DW-1):0] mem_d,
input [(AW-1):0] mem_a,
input mem_oe_n,
input [3:0] mem_bls_n,
input mem_we_n,
input mem_cs_n,
input mem_we_n_fall,
input mem_oe_n_fall,
output [5:0] dbg_state,
input wb_clk_i,
input wb_rst_i
);
// --------------------------------------------------------------------
// wires
wire address_change;
// --------------------------------------------------------------------
// state machine
 
localparam STATE_IDLE = 6'b000001;
localparam STATE_WE = 6'b000010;
localparam STATE_OE = 6'b000100;
localparam STATE_DONE = 6'b001000;
localparam STATE_ERROR = 6'b010000;
localparam STATE_GLITCH = 6'b100000;
 
reg [5:0] state;
reg [5:0] next_state;
always @(posedge wb_clk_i or posedge wb_rst_i)
if(wb_rst_i)
state <= STATE_IDLE;
else
state <= next_state;
 
always @(*)
case( state )
STATE_IDLE: if( (mem_oe_n & mem_we_n) | mem_cs_n )
next_state = STATE_IDLE;
else
if( ~mem_oe_n & ~mem_we_n )
next_state = STATE_ERROR;
else
if( ~mem_we_n )
next_state = STATE_WE;
else
next_state = STATE_OE;
STATE_WE: if( mem_we_n | mem_cs_n )
next_state = STATE_ERROR;
else
if( wb_ack_i )
next_state = STATE_DONE;
else
next_state = STATE_WE;
STATE_OE: if( mem_oe_n | mem_cs_n | address_change )
next_state = STATE_ERROR;
else
if( wb_ack_i )
next_state = STATE_DONE;
else
next_state = STATE_OE;
STATE_DONE: if( mem_cs_n )
next_state = STATE_IDLE;
else
if( mem_we_n_fall )
next_state = STATE_WE;
else if( mem_oe_n_fall )
next_state = STATE_OE;
else
next_state = STATE_DONE;
STATE_ERROR: next_state = STATE_IDLE;
STATE_GLITCH: next_state = STATE_IDLE;
default: next_state = STATE_GLITCH;
endcase
// --------------------------------------------------------------------
// wb_addr_i flop
reg [(AW-1):0] wb_addr_i_r;
assign address_change = (wb_addr_i != wb_addr_i_r);
always @(posedge wb_clk_i)
if( (state != STATE_DONE) | (state != STATE_OE) )
wb_addr_i_r <= wb_addr_i;
// --------------------------------------------------------------------
// outputs
assign wb_cyc_o = (state == STATE_WE) | (state == STATE_OE);
assign wb_stb_o = (state == STATE_WE) | (state == STATE_OE);
assign wb_we_o = (state == STATE_WE);
assign dbg_state = state;
endmodule
 
/wb_async_mem_bridge/trunk/src/soc_ram.v
0,0 → 1,41
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
module soc_ram( data, addr, we, clk, q );
 
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 6;
parameter MEM_INIT = 0;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] addr;
input we;
input clk;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
always @ (posedge clk)
begin
// Write
if (we) ram[addr] <= data;
addr_reg <= addr;
end
// Read returns NEW data at addr if we == 1'b1. This is the
// natural behavior of TriMatrix memory blocks in Single Port
// mode
assign q = ram[addr_reg];
 
// generate
// if( MEM_INIT != 0 )
// initial
// $readmemh( MEM_INIT, ram );
// endgenerate
 
endmodule
/wb_async_mem_bridge/trunk/src/timescale.v
0,0 → 1,41
`timescale 1ns/10ps
/wb_async_mem_bridge/trunk/src/sync_edge_detect.v
0,0 → 1,32
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module sync_edge_detect (
input async_sig,
output sync_out,
input clk,
output reg rise,
output reg fall
);
 
reg [1:3] resync;
 
always @(posedge clk)
begin
// detect rising and falling edges.
rise <= ~resync[3] & resync[2];
fall <= ~resync[2] & resync[3];
// update history shifter.
resync <= {async_sig , resync[1:2]};
end
assign sync_out = resync[2];
 
endmodule
 
/wb_async_mem_bridge/trunk/sim/tests/debug/tb_dut.v
0,0 → 1,99
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
 
 
// --------------------------------------------------------------------
// async_mem_master
wire [31:0] mem_d;
wire [31:0] mem_a;
wire mem_oe_n;
wire [3:0] mem_bls_n;
wire mem_we_n;
wire mem_cs_n;
async_mem_master
async_mem(
.mem_d(mem_d),
.mem_a(mem_a),
.mem_oe_n(mem_oe_n),
.mem_bls_n(mem_bls_n),
.mem_we_n(mem_we_n),
.mem_cs_n(mem_cs_n),
.tb_clk(tb_clk),
.tb_rst(tb_rst)
);
 
// --------------------------------------------------------------------
// wb_async_mem_bridge
wire [31:0] wb_data_i;
wire [31:0] wb_data_o;
wire [31:0] wb_addr_o;
wire [3:0] wb_sel_o;
wire wb_we_o;
wire wb_cyc_o;
wire wb_stb_o;
wire wb_ack_i;
wire wb_err_i;
wire wb_rty_i;
wb_async_mem_bridge
i_wb_async_mem_bridge(
.wb_data_i(wb_data_i),
.wb_data_o(wb_data_o),
.wb_addr_o(wb_addr_o),
.wb_sel_o(wb_sel_o),
.wb_we_o(wb_we_o),
.wb_cyc_o(wb_cyc_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
.mem_d(mem_d),
.mem_a(mem_a),
.mem_oe_n(mem_oe_n),
.mem_bls_n(mem_bls_n),
.mem_we_n(mem_we_n),
.mem_cs_n(mem_cs_n),
.wb_clk_i(tb_clk),
.wb_rst_i(tb_rst)
);
 
// --------------------------------------------------------------------
// wb_slave_model
wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )
i_wb_slave_model(
.clk_i(tb_clk),
.rst_i(tb_rst),
.dat_o(wb_data_i),
.dat_i(wb_data_o),
.adr_i(wb_addr_o),
.cyc_i(wb_cyc_o),
.stb_i(wb_stb_o),
.we_i(wb_we_o),
.sel_i(wb_sel_o),
.ack_o(wb_ack_i),
.err_o(wb_err_i),
.rty_o(wb_rty_i)
);
endmodule
 
 
/wb_async_mem_bridge/trunk/sim/tests/debug/debug.mpf
0,0 → 1,1263
; Copyright 1991-2008 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
mtiAvm = $MODEL_TECH/../avm
mtiOvm = $MODEL_TECH/../ovm
mtiUPF = $MODEL_TECH/../upf_lib
floatfixlib = $MODEL_TECH/../floatfixlib
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
; Run the 0-in compiler on the VHDL source files
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
 
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
 
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageSub = 0
 
; Automatically exclude VHDL case statement default branches.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverageFEC = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverageShortCircuit = 0
 
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
 
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
 
; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0
 
; Turn on fsm debug flow.
; FsmDebug = 1
 
; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
 
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1
 
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with depth equal
; to or greater than 1M are marked as sparse)
; SparseMemThreshold = 1048576
 
; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000
 
; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200
 
; Run the 0-in compiler on the Verilog source files
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
 
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
 
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
 
; Automatically exclude Verilog case statement default branches.
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a Verilog condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverageFEC = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverageShortCircuit = 0
 
 
; Turn on code coverage in VLOG `celldefine modules and modules included
; using vlog -v and -y. Default is off.
; CoverCells = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 1 to 4, with the following
; meanings (the default is 3):
; 1 -- Turn off all optimizations that affect coverage reports.
; 2 -- Allow optimizations that allow large performance improvements
; by invoking sequential processes only when the data changes.
; This may make major reductions in coverage counts.
; 3 -- In addition, allow optimizations that may change expressions or
; remove some statements. Allow constant propagation. Allow VHDL
; subprogram inlining.
; 4 -- In addition, allow optimizations that may remove major regions of
; code by changing assignments to built-ins or removing unused
; signals. Change Verilog gates to continuous assignments.
; Allow VHDL FF recognition.
; CoverOpt = 3
 
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
 
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
 
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; in the [vsim] section can override this value.
; SVCovergroupGoalDefault = 100
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; in the [vsim] section can override this value.
; SVCovergroupTypeGoalDefault = 100
 
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
; SVCovergroupStrobeDefault = 0
 
; Specify the override for the default value of "merge_instances" option for
; the Covergroup Type. This is a compile time option which forces
; "merge_instances" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupMergeInstancesDefault = 0
 
; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero).
; SVCovergroupPerInstanceDefault = 0
 
; Specify the override for the default value of "get_inst_coverage" option for the
; Covergroup variables. This is a compile time option which forces
; "get_inst_coverage" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupGetInstCoverageDefault = 0
 
;
; A space separated list of resource libraries that contain precompiled
; packages. The behavior is identical to using the "-L" switch.
;
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm mtiOvm mtiUPF
 
; The behavior is identical to the "-mixedansiports" switch. Default is off.
; MixedAnsiPorts = 1
 
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1
 
; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1
 
; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5
 
; Turn on fsm debug flow.
; FsmDebug = 1
 
; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
; Turn off detections of FSMs having x-assignment.
; FsmXAssign = 0
 
; List of file suffixes which will be read as SystemVerilog. White space
; in extensions can be specified with a back-slash: "\ ". Back-slashes
; can be specified with two consecutive back-slashes: "\\";
; SVFileExtensions = sv svp
 
; This setting is the same as the vlog -sv command line switch.
; Enables SystemVerilog features and keywords when true (1).
; When false (0), the rules of IEEE Std 1364-2001 are followed and
; SystemVerilog keywords are ignored.
; Svlog = 0
 
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
 
; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g
 
; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++
 
; Enable verbose messages from sccom. Default is off.
; SccomVerbose = 1
 
; sccom logfile. Default is no logfile.
; SccomLogfile = sccom.log
 
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft
 
; Control compiler optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a vopt condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
[vsim]
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1
 
; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0
 
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
 
; Disable certain code coverage exclusions automatically.
; Assertions and FSM are exluded from the code coverage by default
; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
; Or specify comma or space separated list
;AutoExclusionsDisable = fsm,assertions
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 100 ps
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1
 
; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
; -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1
 
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; noviewer Disable checkout of msimviewer and vsim-viewer license
; features (PE ONLY)
; noslvhdl Disable checkout of qhsimvh and vsim license features
; noslvlog Disable checkout of qhsimvl and vsimvlog license features
; nomix Disable checkout of msimhdlmix and hdlmix license features
; nolnl Disable checkout of msimhdlsim and hdlsim license features
; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
; features
; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
; hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus
 
; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; VHDL assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
; from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use MessageFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
; level), use MessageFormatBreak;
; - otherwise, use MessageFormat.
; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
 
; Error File - alternate file for storing error messages
; ErrorFile = error.log
 
 
; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name: # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1
 
; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; VSIM Shutdown file
; Filename to save u/i formats and configurations.
; ShutdownFile = restart.do
; To explicitly disable auto save:
; ShutdownFile = --disable-auto-save
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Specify a unique path separator for the Signal Spy set of functions.
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /
 
; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.
; If set to 0, the syntax of the source language must be used.
; Each identifier in a hierarchical name may need different syntax,
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
; GenerousIdentifierParsing = 1
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Disable System Verilog assertion messages
; IgnoreSVAInfo = 1
; IgnoreSVAWarning = 1
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
; The term "out-of-the-blue" refers to SystemVerilog export function calls
; made from C functions that don't have the proper context setup
; (as is the case when running under "DPI-C" import functions).
; When this is enabled, one can call a DPI export function
; (but not task) from any C code.
; The default is 0 (disabled).
; DpiOutOfTheBlue = 1
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Which default VPI object model should the tool conform to?
; The 1364 modes are Verilog-only, for backwards compatibility with older
; libraries, and SystemVerilog objects are not available in these modes.
;
; In the absence of a user-specified default, the tool default is the
; latest available LRM behavior.
; Options for PliCompatDefault are:
; VPI_COMPATIBILITY_VERSION_1364v1995
; VPI_COMPATIBILITY_VERSION_1364v2001
; VPI_COMPATIBILITY_VERSION_1364v2005
; VPI_COMPATIBILITY_VERSION_1800v2005
; VPI_COMPATIBILITY_VERSION_1800v2008
;
; Synonyms for each string are also recognized:
; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
 
 
; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; DefaultRestartOptions = -force
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Specify whether or not a WLF file should be optimized during
; simulation. If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0
 
; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf
 
; Specify the WLF reader cache size limit for each open WLF file.
; The size is giving in megabytes. A value of 0 turns off the
; WLF cache.
; WLFSimCacheSize allows a different cache size to be set for
; simulation WLF file independent of post-simulation WLF file
; viewing. If WLFSimCacheSize is not set it defaults to the
; WLFCacheSize setting.
; The default WLFCacheSize setting is enabled to 256M per open WLF file.
; WLFCacheSize = 2000
; WLFSimCacheSize = 500
 
; Specify the WLF file event collapse mode.
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
; 1 = Only record values of logged objects at the end of a simulator iteration.
; (same as -wlfcollapsedelta)
; 2 = Only record values of logged objects at the end of a simulator time step.
; (same as -wlfcollapsetime)
; The default is 1.
; WLFCollapseMode = 0
 
; Specify whether WLF file logging can use threads on multi-processor machines
; if 0, no threads will be used, if 1, threads will be used if the system has
; more than one processor
; WLFUseThreads = 1
 
; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0
 
; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1
 
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
; ScShowIeeeDeprecationWarnings = 1
 
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
; ScEnableScSignalWriteCheck = 1
 
; Set SystemC default time unit.
; Set to fs, ps, ns, us, ms, or sec with optional
; prefix of 1, 10, or 100. The default is 1 ns.
; The ScTimeUnit value is honored if it is coarser than Resolution.
; If ScTimeUnit is finer than Resolution, it is set to the value
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
; then the default time unit will be 1 ns. However if Resolution
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
ScTimeUnit = ns
 
; Set SystemC sc_main stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
; on the amount of data on the sc_main() stack and the memory required
; to succesfully execute the longest function call chain of sc_main().
ScMainStackSize = 10 Mb
 
; Turn on/off execution of remainder of sc_main upon quitting the current
; simulation session. If the cumulative length of sc_main() in terms of
; simulation time units is less than the length of the current simulation
; run upon quit or restart, sc_main() will be in the middle of execution.
; This switch gives the option to execute the remainder of sc_main upon
; quitting simulation. The drawback of not running sc_main till the end
; is memory leaks for objects created by sc_main. If on, the remainder of
; sc_main will be executed ignoring all delays. This may cause the simulator
; to crash if the code in sc_main is dependent on some simulation state.
; Default is on.
ScMainFinishOnQuit = 1
 
; Set the SCV relationship name that will be used to identify phase
; relations. If the name given to a transactor relation matches this
; name, the transactions involved will be treated as phase transactions
ScvPhaseRelationName = mti_phase
 
; Customize the vsim kernel shutdown behavior at the end of the simulation.
; Some common causes of the end of simulation are $finish (implicit or explicit),
; sc_stop(), tf_dofinish(), and assertion failures.
; This should be set to "ask", "exit", or "stop". The default is "ask".
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
; In GUI mode, a dialog box will pop up and ask for user confirmation
; whether or not to quit the simulation.
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
; post-simulation tasks easier.
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
; Note: these ini variables can be overriden by the vsim command
; line switch "-onfinish <ask|stop|exit>".
OnFinish = ask
 
; Print "simstats" result at the end of simulation before shutdown.
; If this is enabled, the simstats result will be printed out before shutdown.
; The default is off.
; PrintSimStats = 1
 
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log
 
; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1
 
; Turn on/off PSL/SVA concurrent assertion pass enable.
; For SVA, Default is on when the assertion has a pass action block, or
; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
; For PSL, Default is on only when vsim switch "-assertdebug" is used
; and the vopt "+acc=a" flag is active.
; AssertionPassEnable = 0
 
; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
; AssertionFailEnable = 0
 
; Set PSL/SVA concurrent assertion pass limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionPassLimit = 1
 
; Set PSL/SVA concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionFailLimit = 1
 
; Turn on/off PSL concurrent assertion pass log. Default is off.
; The flag does not affect SVA
; AssertionPassLog = 1
 
; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0
 
; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
; AssertionFailLocalVarLog = 0
 
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue 1 = Break 2 = Exit
; AssertionFailAction = 1
 
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1
 
; Control how many waveform rows will be used for displaying the active threads. Default is 5.
; AssertionActiveThreadMonitorLimit = 5
 
; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance. Default is -1 (ALL).
; ATVStartTimeKeepCount = -1
 
; Turn on/off code coverage
; CodeCoverage = 0
 
; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1
 
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1
 
; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100
 
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to not include them.
; ToggleVlogIntegers = 1
 
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128
 
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1
 
; Turn on/off all PSL/SVA cover directive enables. Default is on.
; CoverEnable = 0
 
; Turn on/off PSL/SVA cover log. Default is off.
; CoverLog = 1
 
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
; CoverAtLeast = 2
 
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1
 
; Specify the coverage database filename.
; Default is "" (i.e. database is NOT automatically saved on close).
; UCDBFilename = vsim.ucdb
 
; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed.
; MaxReportRhsSVCrossProducts = 1000
 
; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64
 
; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0
 
; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then
; cross_num_print_missing is ignored for creating reports and displaying
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0
 
; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0
 
; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100
 
; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100
 
; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
; builtin functions, and report. This setting changes the default values of
; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
; behavior if explicit assignments are not made on option.get_inst_coverage and
; type_option.merge_instances by the user. There are two vsim command line
; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
; The default value of this variable is 1
; SVCovergroup63Compatibility = 1
 
; Enable or disable generation of more detailed information about the sampling
; of covergroup, cross, and coverpoints. It provides the details of the number
; of times the covergroup instance and type were sampled, as well as details
; about why covergroup, cross and coverpoint were not covered. A non-zero value
; is to enable this feature. 0 is to disable this feature. Default is 0
; SVCovergroupSampleInfo = 0
 
; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648
 
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
; MaxSVCoverpointBinsInst = 2147483648
 
; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648
 
; Specify maximum number of Cross bins in any instance of a Covergroup
; MaxSVCrossBinsInst = 2147483648
 
; Set weight for all PSL/SVA cover directives. Default is 1.
; CoverWeight = 2
 
; Check vsim plusargs. Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
 
; Run the 0in tools from within the simulator.
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0in runtime tool.
; Default value set to "".
; ZeroInOptions = ""
 
; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
; Sv_Seed = 0
 
; Maximum size of dynamic arrays that are resized during randomize().
; The default is 1000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 1000
 
; Error message severity when randomize() failure is detected (SystemVerilog).
; The default is 0 (no error).
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; SolveFailSeverity = 0
 
; Enable/disable debug information for randomize() failures (SystemVerilog).
; The default is 0 (disabled). Set to 1 to enable.
; SolveFailDebug = 0
 
; When SolveFailDebug is enabled, this value specifies the algorithm used to
; discover conflicts between constraints for randomize() failures.
; The default is "many".
;
; Valid schemes are:
; "many" = best for determining conflicts due to many related constraints
; "few" = best for determining conflicts due to few related constraints
;
; SolveFailDebugScheme = many
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum number of constraint subsets that will be tested for
; conflicts.
; The default is 0 (no limit).
; SolveFailDebugLimit = 0
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum size of constraint subsets that will be tested for
; conflicts.
; The default value is 0 (no limit).
; SolveFailDebugMaxSet = 0
 
; Maximum size of the solution graph that may be generated during randomize().
; This value can be used to force randomize() to abort if the complexity of
; the constraint scenario (both in memory and time spent during evaluation)
; exceeds the specified limit. This value is specified in 1000s of nodes.
; The default is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000
 
; Use SolveFlags to specify options that will guide the behavior of the
; constraint solver. These options may improve the performance of the
; constraint solver for some testcases, and decrease the performance of
; the constraint solver for others.
; The default value is "" (no options).
;
; Valid flags are:
; c = interleave bits of concatenation operands
; i = disable bit interleaving for >, >=, <, <= constraints
; n = disable bit interleaving for all constraints
; r = reverse bit interleaving
;
; SolveFlags =
 
; Specify random sequence compatiblity with a prior letter release. This
; option is used to get the same random sequences during simulation as
; as a prior letter release. Only prior letter releases (of the current
; number release) are allowed.
; Note: To achieve the same random sequences, solver optimizations and/or
; bug fixes introduced since the specified release may be disabled -
; yielding the performance / behavior of the prior release.
; Default value set to "" (random compatibility not required).
; SolveRev =
 
; Environment variable expansion of command line arguments has been depricated
; in favor shell level expansion. Universal environment variable expansion
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this
; deprecated behavior. The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0
 
; Turn on/off collapsing of bus ports in VCD dumpports output
DumpportsCollapse = 1
 
; Location of Multi-Level Verification Component (MVC) installation.
; The default location is the product installation directory.
; MvcHome = $MODEL_TECH/...
 
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
 
; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of Verilog display system task messages and
; PLI/FLI print function call messages. The system tasks include
; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
; also include the analogous file I/O tasks that write to STDOUT
; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
; is to have messages appear only in the transcript. The other
; settings are to send messages to the wlf file only (messages that
; are recorded in the wlf file can be viewed in the MsgViewer) or
; to both the transcript and the wlf file. The valid values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; displaymsgmode = tran
 
; Control transcripting of elaboration/runtime messages not
; addressed by the displaymsgmode setting. The default is to
; have messages appear in the transcript and recorded in the wlf
; file (messages that are recorded in the wlf file can be viewed
; in the MsgViewer). The other settings are to send messages
; only to the transcript or only to the wlf file. The valid
; values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 8
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/tests/debug/tb_top.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1255736155 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/sync_edge_detect.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1254874408 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/sync.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1251997300 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/wb_async_mem_sm.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1255737461 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/models/async_mem_master.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1255737931 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/tests/debug/tb_dut.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1255481763 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/models/wb_slave_model.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1255480557 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/wb_async_mem_bridge.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1255737852 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/tests/debug/tb_top.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 4
/wb_async_mem_bridge/trunk/sim/tests/debug/tb_top.v
0,0 → 1,67
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_top();
 
parameter CLK_PERIOD = 10;
 
reg tb_clk, tb_rst;
 
initial
begin
tb_clk <= 1'b1;
tb_rst <= 1'b1;
#(CLK_PERIOD); #(CLK_PERIOD/3);
tb_rst = 1'b0;
end
 
always
#(CLK_PERIOD/2) tb_clk = ~tb_clk;
// --------------------------------------------------------------------
// tb_dut
tb_dut dut( tb_clk, tb_rst );
 
// --------------------------------------------------------------------
// insert test below
 
initial
begin
wait( ~tb_rst );
repeat(2) @(posedge tb_clk);
//
$display("\n^^^- \n");
dut.async_mem.async_mem_write( 32'h83000000, 32'habbabeef, 4'b0000 );
repeat(10) @(posedge tb_clk);
dut.async_mem.async_mem_cmp( 32'h83000000, 32'habbabeef, 4'b0000 );
repeat(10) @(posedge tb_clk);
dut.async_mem.async_mem_3x_write( 32'h83000000, 32'habbabeef, 32'h55555555, 32'haaaaaaaa, 4'b0000 );
repeat(10) @(posedge tb_clk);
dut.async_mem.async_mem_3x_cmp( 32'h83000000, 32'habbabeef, 32'h55555555, 32'haaaaaaaa, 4'b0000 );
repeat(10) @(posedge tb_clk);
$display("\n^^^---------------------------------\n");
$display("^^^- Testbench done. %t.\n", $time);
$stop();
end
endmodule
 
/wb_async_mem_bridge/trunk/sim/tests/de1_system/wb_slave_32_bit.txt
0,0 → 1,48
00
00
00
11
11
11
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/wb_async_mem_bridge/trunk/sim/tests/de1_system/tb_dut.v
0,0 → 1,260
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
`include "timescale.v"
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
wire [3:0] boot_strap = 4'b0010;
// --------------------------------------------------------------------
// de1 wires
wire [1:0] clock_24;
wire [1:0] clock_27;
wire clock_50;
wire ext_clock;
wire [3:0] key;
wire [9:0] sw;
wire [6:0] hex0;
wire [6:0] hex1;
wire [6:0] hex2;
wire [6:0] hex3;
wire [7:0] ledg;
wire [9:0] ledr;
wire uart_txd;
wire uart_rxd;
wire [15:0] dram_dq;
wire [11:0] dram_addr;
wire dram_ldqm;
wire dram_udqm;
wire dram_we_n;
wire dram_cas_n;
wire dram_ras_n;
wire dram_cs_n;
wire dram_ba_0;
wire dram_ba_1;
wire dram_clk;
wire dram_cke;
wire [7:0] fl_dq;
wire [21:0] fl_addr;
wire fl_we_n;
wire fl_rst_n;
wire fl_oe_n;
wire fl_ce_n;
wire [15:0] sram_dq;
wire [17:0] sram_addr;
wire sram_ub_n;
wire sram_lb_n;
wire sram_we_n;
wire sram_ce_n;
wire sram_oe_n;
wire sd_dat;
wire sd_dat3;
wire sd_cmd;
wire sd_clk;
wire i2c_sdat;
wire i2c_sclk;
wire ps2_dat;
wire ps2_clk;
wire tdi;
wire tck;
wire tcs;
wire tdo;
wire vga_hs;
wire vga_vs;
wire [3:0] vga_r;
wire [3:0] vga_g;
wire [3:0] vga_b;
wire aud_adclrck;
wire aud_adcdat;
wire aud_daclrck;
wire aud_dacdat;
wire aud_bclk;
wire aud_xck;
wire [35:0] gpio_0;
wire [35:0] gpio_1;
// --------------------------------------------------------------------
// fpga top
assign clock_24 = {1'b0, tb_clk};
assign sw = {6'b000000, boot_strap};
assign key = {3'b000, ~tb_rst};
top
i_top(
//////////////////////// Clock Input ////////////////////////
.clock_24( clock_24 ), // 24 MHz
.clock_27(clock_27), // 27 MHz
.clock_50(clock_50), // 50 MHz
.ext_clock(ext_clock), // External Clock
//////////////////////// Push Button ////////////////////////
.key( key ), // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
.sw( sw ), // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
.hex0(hex0), // Seven Segment Digit 0
.hex1(hex1), // Seven Segment Digit 1
.hex2(hex2), // Seven Segment Digit 2
.hex3(hex3), // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
.ledg(ledg), // LED Green[7:0]
.ledr(ledr), // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
.uart_txd(uart_txd), // UART Transmitter
.uart_rxd(uart_rxd), // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
.dram_dq(dram_dq), // SDRAM Data bus 16 Bits
.dram_addr(dram_addr), // SDRAM Address bus 12 Bits
.dram_ldqm(dram_ldqm), // SDRAM Low-byte Data Mask
.dram_udqm(dram_udqm), // SDRAM High-byte Data Mask
.dram_we_n(dram_we_n), // SDRAM Write Enable
.dram_cas_n(dram_cas_n), // SDRAM Column Address Strobe
.dram_ras_n(dram_ras_n), // SDRAM Row Address Strobe
.dram_cs_n(dram_cs_n), // SDRAM Chip Select
.dram_ba_0(dram_ba_0), // SDRAM Bank Address 0
.dram_ba_1(dram_ba_1), // SDRAM Bank Address 0
.dram_clk(dram_clk), // SDRAM Clock
.dram_cke(dram_cke), // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
.fl_dq(fl_dq), // FLASH Data bus 8 Bits
.fl_addr(fl_addr), // FLASH Address bus 22 Bits
.fl_we_n(fl_we_n), // FLASH Write Enable
.fl_rst_n(fl_rst_n), // FLASH Reset
.fl_oe_n(fl_oe_n), // FLASH Output Enable
.fl_ce_n(fl_ce_n), // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
.sram_dq(sram_dq), // SRAM Data bus 16 Bits
.sram_addr(sram_addr), // SRAM Address bus 18 Bits
.sram_ub_n(sram_ub_n), // SRAM High-byte Data Mask
.sram_lb_n(sram_lb_n), // SRAM Low-byte Data Mask
.sram_we_n(sram_we_n), // SRAM Write Enable
.sram_ce_n(sram_ce_n), // SRAM Chip Enable
.sram_oe_n(sram_oe_n), // SRAM Output Enable
//////////////////// SD Card Interface ////////////////////////
.sd_dat(sd_dat), // SD Card Data
.sd_dat3(sd_dat3), // SD Card Data 3
.sd_cmd(sd_cmd), // SD Card Command Signal
.sd_clk(sd_clk), // SD Card Clock
//////////////////////// I2C ////////////////////////////////
.i2c_sdat(i2c_sdat), // I2C Data
.i2c_sclk(i2c_sclk), // I2C Clock
//////////////////////// PS2 ////////////////////////////////
.ps2_dat(ps2_dat), // PS2 Data
.ps2_clk(ps2_clk), // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
.tdi(tdi), // CPLD -> FPGA (data in)
.tck(tck), // CPLD -> FPGA (clk)
.tcs(tcs), // CPLD -> FPGA (CS)
.tdo(tdo), // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
.vga_hs(vga_hs), // VGA H_SYNC
.vga_vs(vga_vs), // VGA V_SYNC
.vga_r(vga_r), // VGA Red[3:0]
.vga_g(vga_g), // VGA Green[3:0]
.vga_b(vga_b), // VGA Blue[3:0]
//////////////////// Audio CODEC ////////////////////////////
.aud_adclrck(aud_adclrck), // Audio CODEC ADC LR Clock
.aud_adcdat(aud_adcdat), // Audio CODEC ADC Data
.aud_daclrck(aud_daclrck), // Audio CODEC DAC LR Clock
.aud_dacdat(aud_dacdat), // Audio CODEC DAC Data
.aud_bclk(aud_bclk), // Audio CODEC Bit-Stream Clock
.aud_xck(aud_xck), // Audio CODEC Chip Clock
//////////////////////// GPIO ////////////////////////////////
.gpio_0(gpio_0), // GPIO Connection 0
.gpio_1(gpio_1) // GPIO Connection 1
);
 
// --------------------------------------------------------------------
// IS61LV25616
IS61LV25616 i_IS61LV25616 (
.A(sram_addr),
.IO(sram_dq),
.CE_(sram_ce_n),
.OE_(sram_oe_n),
.WE_(sram_we_n),
.LB_(sram_lb_n),
.UB_(sram_ub_n)
);
// --------------------------------------------------------------------
// s29al032d_00
s29al032d_00 #( .UserPreload(1'b1), .mem_file_name( "../../../sw/load_this_to_ram/boot_rom_2.txt" ) )
i_s29al032d_00(
.A21(fl_addr[21]),
.A20(fl_addr[20]),
.A19(fl_addr[19]),
.A18(fl_addr[18]),
.A17(fl_addr[17]),
.A16(fl_addr[16]),
.A15(fl_addr[15]),
.A14(fl_addr[14]),
.A13(fl_addr[13]),
.A12(fl_addr[12]),
.A11(fl_addr[11]),
.A10(fl_addr[10]),
.A9(fl_addr[9]),
.A8(fl_addr[8]),
.A7(fl_addr[7]),
.A6(fl_addr[6]),
.A5(fl_addr[5]),
.A4(fl_addr[4]),
.A3(fl_addr[3]),
.A2(fl_addr[2]),
.A1(fl_addr[1]),
.A0(fl_addr[0]),
 
.DQ7(fl_dq[7]),
.DQ6(fl_dq[6]),
.DQ5(fl_dq[5]),
.DQ4(fl_dq[4]),
.DQ3(fl_dq[3]),
.DQ2(fl_dq[2]),
.DQ1(fl_dq[1]),
.DQ0(fl_dq[0]),
 
.CENeg(fl_ce_n),
.OENeg(fl_oe_n),
.WENeg(fl_we_n),
.RESETNeg(fl_rst_n),
.ACC(),
.RY()
);
// --------------------------------------------------------------------
// async_mem_master
wire [31:0] mem_d;
wire [31:0] mem_a;
wire mem_oe_n;
wire [3:0] mem_bls_n;
wire mem_we_n;
wire mem_cs_n;
async_mem_master
async_mem(
.mem_d( gpio_1[31:0] ),
.mem_a( gpio_0[23:0] ),
.mem_oe_n( gpio_0[30] ),
.mem_bls_n( { gpio_0[26], gpio_0[27], gpio_0[28], gpio_0[29] } ),
.mem_we_n( gpio_0[25] ),
.mem_cs_n( gpio_0[24] ),
.tb_clk(tb_clk),
.tb_rst(tb_rst)
);
 
endmodule
 
 
 
/wb_async_mem_bridge/trunk/sim/tests/de1_system/timescale.v
0,0 → 1,260
`timescale 1ns/10ps
/wb_async_mem_bridge/trunk/sim/tests/de1_system/tb_top.v
0,0 → 1,61
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_top();
 
parameter CLK_PERIOD = 10;
 
reg tb_clk, tb_rst;
 
initial
begin
tb_clk <= 1'b1;
tb_rst <= 1'b1;
#(CLK_PERIOD); #(CLK_PERIOD/3);
tb_rst = 1'b0;
end
 
always
#(CLK_PERIOD/2) tb_clk = ~tb_clk;
// --------------------------------------------------------------------
// tb_dut
tb_dut dut( tb_clk, tb_rst );
 
// --------------------------------------------------------------------
// insert test below
 
initial
begin
wait( ~tb_rst );
repeat(2) @(posedge tb_clk);
//
$display("\n^^^- \n");
dut.async_mem.async_mem_write( 32'h83000000, 32'habbabeef, 4'b0000 );
repeat(2) @(posedge tb_clk);
dut.async_mem.async_mem_cmp( 32'h83000000, 32'habbabeef, 4'b0000 );
repeat(4) @(posedge tb_clk);
$display("\n^^^---------------------------------\n");
$display("^^^- Testbench done. %t.\n", $time);
$stop();
end
endmodule
 
/wb_async_mem_bridge/trunk/sim/tests/de1_system/de1_system.mpf
0,0 → 1,1271
; Copyright 1991-2008 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
mtiAvm = $MODEL_TECH/../avm
mtiOvm = $MODEL_TECH/../ovm
mtiUPF = $MODEL_TECH/../upf_lib
floatfixlib = $MODEL_TECH/../floatfixlib
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
; Run the 0-in compiler on the VHDL source files
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
 
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
 
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageSub = 0
 
; Automatically exclude VHDL case statement default branches.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverageFEC = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverageShortCircuit = 0
 
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
 
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
 
; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0
 
; Turn on fsm debug flow.
; FsmDebug = 1
 
; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
 
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1
 
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with depth equal
; to or greater than 1M are marked as sparse)
; SparseMemThreshold = 1048576
 
; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000
 
; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200
 
; Run the 0-in compiler on the Verilog source files
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
 
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
 
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
 
; Automatically exclude Verilog case statement default branches.
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a Verilog condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverageFEC = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverageShortCircuit = 0
 
 
; Turn on code coverage in VLOG `celldefine modules and modules included
; using vlog -v and -y. Default is off.
; CoverCells = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 1 to 4, with the following
; meanings (the default is 3):
; 1 -- Turn off all optimizations that affect coverage reports.
; 2 -- Allow optimizations that allow large performance improvements
; by invoking sequential processes only when the data changes.
; This may make major reductions in coverage counts.
; 3 -- In addition, allow optimizations that may change expressions or
; remove some statements. Allow constant propagation. Allow VHDL
; subprogram inlining.
; 4 -- In addition, allow optimizations that may remove major regions of
; code by changing assignments to built-ins or removing unused
; signals. Change Verilog gates to continuous assignments.
; Allow VHDL FF recognition.
; CoverOpt = 3
 
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
 
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
 
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; in the [vsim] section can override this value.
; SVCovergroupGoalDefault = 100
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; in the [vsim] section can override this value.
; SVCovergroupTypeGoalDefault = 100
 
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
; SVCovergroupStrobeDefault = 0
 
; Specify the override for the default value of "merge_instances" option for
; the Covergroup Type. This is a compile time option which forces
; "merge_instances" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupMergeInstancesDefault = 0
 
; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero).
; SVCovergroupPerInstanceDefault = 0
 
; Specify the override for the default value of "get_inst_coverage" option for the
; Covergroup variables. This is a compile time option which forces
; "get_inst_coverage" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupGetInstCoverageDefault = 0
 
;
; A space separated list of resource libraries that contain precompiled
; packages. The behavior is identical to using the "-L" switch.
;
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm mtiOvm mtiUPF
 
; The behavior is identical to the "-mixedansiports" switch. Default is off.
; MixedAnsiPorts = 1
 
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1
 
; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1
 
; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5
 
; Turn on fsm debug flow.
; FsmDebug = 1
 
; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
; Turn off detections of FSMs having x-assignment.
; FsmXAssign = 0
 
; List of file suffixes which will be read as SystemVerilog. White space
; in extensions can be specified with a back-slash: "\ ". Back-slashes
; can be specified with two consecutive back-slashes: "\\";
; SVFileExtensions = sv svp
 
; This setting is the same as the vlog -sv command line switch.
; Enables SystemVerilog features and keywords when true (1).
; When false (0), the rules of IEEE Std 1364-2001 are followed and
; SystemVerilog keywords are ignored.
; Svlog = 0
 
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
 
; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g
 
; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++
 
; Enable verbose messages from sccom. Default is off.
; SccomVerbose = 1
 
; sccom logfile. Default is no logfile.
; SccomLogfile = sccom.log
 
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft
 
; Control compiler optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a vopt condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
[vsim]
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1
 
; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0
 
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
 
; Disable certain code coverage exclusions automatically.
; Assertions and FSM are exluded from the code coverage by default
; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
; Or specify comma or space separated list
;AutoExclusionsDisable = fsm,assertions
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 100 ns
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1
 
; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
; -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1
 
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; noviewer Disable checkout of msimviewer and vsim-viewer license
; features (PE ONLY)
; noslvhdl Disable checkout of qhsimvh and vsim license features
; noslvlog Disable checkout of qhsimvl and vsimvlog license features
; nomix Disable checkout of msimhdlmix and hdlmix license features
; nolnl Disable checkout of msimhdlsim and hdlsim license features
; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
; features
; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
; hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus
 
; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; VHDL assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
; from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use MessageFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
; level), use MessageFormatBreak;
; - otherwise, use MessageFormat.
; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
 
; Error File - alternate file for storing error messages
; ErrorFile = error.log
 
 
; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name: # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1
 
; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; VSIM Shutdown file
; Filename to save u/i formats and configurations.
; ShutdownFile = restart.do
; To explicitly disable auto save:
; ShutdownFile = --disable-auto-save
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Specify a unique path separator for the Signal Spy set of functions.
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /
 
; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.
; If set to 0, the syntax of the source language must be used.
; Each identifier in a hierarchical name may need different syntax,
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
; GenerousIdentifierParsing = 1
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Disable System Verilog assertion messages
; IgnoreSVAInfo = 1
; IgnoreSVAWarning = 1
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
; The term "out-of-the-blue" refers to SystemVerilog export function calls
; made from C functions that don't have the proper context setup
; (as is the case when running under "DPI-C" import functions).
; When this is enabled, one can call a DPI export function
; (but not task) from any C code.
; The default is 0 (disabled).
; DpiOutOfTheBlue = 1
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Which default VPI object model should the tool conform to?
; The 1364 modes are Verilog-only, for backwards compatibility with older
; libraries, and SystemVerilog objects are not available in these modes.
;
; In the absence of a user-specified default, the tool default is the
; latest available LRM behavior.
; Options for PliCompatDefault are:
; VPI_COMPATIBILITY_VERSION_1364v1995
; VPI_COMPATIBILITY_VERSION_1364v2001
; VPI_COMPATIBILITY_VERSION_1364v2005
; VPI_COMPATIBILITY_VERSION_1800v2005
; VPI_COMPATIBILITY_VERSION_1800v2008
;
; Synonyms for each string are also recognized:
; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
 
 
; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; DefaultRestartOptions = -force
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Specify whether or not a WLF file should be optimized during
; simulation. If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0
 
; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf
 
; Specify the WLF reader cache size limit for each open WLF file.
; The size is giving in megabytes. A value of 0 turns off the
; WLF cache.
; WLFSimCacheSize allows a different cache size to be set for
; simulation WLF file independent of post-simulation WLF file
; viewing. If WLFSimCacheSize is not set it defaults to the
; WLFCacheSize setting.
; The default WLFCacheSize setting is enabled to 256M per open WLF file.
; WLFCacheSize = 2000
; WLFSimCacheSize = 500
 
; Specify the WLF file event collapse mode.
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
; 1 = Only record values of logged objects at the end of a simulator iteration.
; (same as -wlfcollapsedelta)
; 2 = Only record values of logged objects at the end of a simulator time step.
; (same as -wlfcollapsetime)
; The default is 1.
; WLFCollapseMode = 0
 
; Specify whether WLF file logging can use threads on multi-processor machines
; if 0, no threads will be used, if 1, threads will be used if the system has
; more than one processor
; WLFUseThreads = 1
 
; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0
 
; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1
 
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
; ScShowIeeeDeprecationWarnings = 1
 
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
; ScEnableScSignalWriteCheck = 1
 
; Set SystemC default time unit.
; Set to fs, ps, ns, us, ms, or sec with optional
; prefix of 1, 10, or 100. The default is 1 ns.
; The ScTimeUnit value is honored if it is coarser than Resolution.
; If ScTimeUnit is finer than Resolution, it is set to the value
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
; then the default time unit will be 1 ns. However if Resolution
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
ScTimeUnit = ns
 
; Set SystemC sc_main stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
; on the amount of data on the sc_main() stack and the memory required
; to succesfully execute the longest function call chain of sc_main().
ScMainStackSize = 10 Mb
 
; Turn on/off execution of remainder of sc_main upon quitting the current
; simulation session. If the cumulative length of sc_main() in terms of
; simulation time units is less than the length of the current simulation
; run upon quit or restart, sc_main() will be in the middle of execution.
; This switch gives the option to execute the remainder of sc_main upon
; quitting simulation. The drawback of not running sc_main till the end
; is memory leaks for objects created by sc_main. If on, the remainder of
; sc_main will be executed ignoring all delays. This may cause the simulator
; to crash if the code in sc_main is dependent on some simulation state.
; Default is on.
ScMainFinishOnQuit = 1
 
; Set the SCV relationship name that will be used to identify phase
; relations. If the name given to a transactor relation matches this
; name, the transactions involved will be treated as phase transactions
ScvPhaseRelationName = mti_phase
 
; Customize the vsim kernel shutdown behavior at the end of the simulation.
; Some common causes of the end of simulation are $finish (implicit or explicit),
; sc_stop(), tf_dofinish(), and assertion failures.
; This should be set to "ask", "exit", or "stop". The default is "ask".
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
; In GUI mode, a dialog box will pop up and ask for user confirmation
; whether or not to quit the simulation.
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
; post-simulation tasks easier.
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
; Note: these ini variables can be overriden by the vsim command
; line switch "-onfinish <ask|stop|exit>".
OnFinish = ask
 
; Print "simstats" result at the end of simulation before shutdown.
; If this is enabled, the simstats result will be printed out before shutdown.
; The default is off.
; PrintSimStats = 1
 
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log
 
; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1
 
; Turn on/off PSL/SVA concurrent assertion pass enable.
; For SVA, Default is on when the assertion has a pass action block, or
; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
; For PSL, Default is on only when vsim switch "-assertdebug" is used
; and the vopt "+acc=a" flag is active.
; AssertionPassEnable = 0
 
; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
; AssertionFailEnable = 0
 
; Set PSL/SVA concurrent assertion pass limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionPassLimit = 1
 
; Set PSL/SVA concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionFailLimit = 1
 
; Turn on/off PSL concurrent assertion pass log. Default is off.
; The flag does not affect SVA
; AssertionPassLog = 1
 
; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0
 
; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
; AssertionFailLocalVarLog = 0
 
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue 1 = Break 2 = Exit
; AssertionFailAction = 1
 
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1
 
; Control how many waveform rows will be used for displaying the active threads. Default is 5.
; AssertionActiveThreadMonitorLimit = 5
 
; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance. Default is -1 (ALL).
; ATVStartTimeKeepCount = -1
 
; Turn on/off code coverage
; CodeCoverage = 0
 
; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1
 
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1
 
; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100
 
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to not include them.
; ToggleVlogIntegers = 1
 
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128
 
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1
 
; Turn on/off all PSL/SVA cover directive enables. Default is on.
; CoverEnable = 0
 
; Turn on/off PSL/SVA cover log. Default is off.
; CoverLog = 1
 
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
; CoverAtLeast = 2
 
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1
 
; Specify the coverage database filename.
; Default is "" (i.e. database is NOT automatically saved on close).
; UCDBFilename = vsim.ucdb
 
; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed.
; MaxReportRhsSVCrossProducts = 1000
 
; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64
 
; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0
 
; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then
; cross_num_print_missing is ignored for creating reports and displaying
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0
 
; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0
 
; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100
 
; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100
 
; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
; builtin functions, and report. This setting changes the default values of
; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
; behavior if explicit assignments are not made on option.get_inst_coverage and
; type_option.merge_instances by the user. There are two vsim command line
; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
; The default value of this variable is 1
; SVCovergroup63Compatibility = 1
 
; Enable or disable generation of more detailed information about the sampling
; of covergroup, cross, and coverpoints. It provides the details of the number
; of times the covergroup instance and type were sampled, as well as details
; about why covergroup, cross and coverpoint were not covered. A non-zero value
; is to enable this feature. 0 is to disable this feature. Default is 0
; SVCovergroupSampleInfo = 0
 
; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648
 
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
; MaxSVCoverpointBinsInst = 2147483648
 
; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648
 
; Specify maximum number of Cross bins in any instance of a Covergroup
; MaxSVCrossBinsInst = 2147483648
 
; Set weight for all PSL/SVA cover directives. Default is 1.
; CoverWeight = 2
 
; Check vsim plusargs. Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
 
; Run the 0in tools from within the simulator.
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0in runtime tool.
; Default value set to "".
; ZeroInOptions = ""
 
; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
; Sv_Seed = 0
 
; Maximum size of dynamic arrays that are resized during randomize().
; The default is 1000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 1000
 
; Error message severity when randomize() failure is detected (SystemVerilog).
; The default is 0 (no error).
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; SolveFailSeverity = 0
 
; Enable/disable debug information for randomize() failures (SystemVerilog).
; The default is 0 (disabled). Set to 1 to enable.
; SolveFailDebug = 0
 
; When SolveFailDebug is enabled, this value specifies the algorithm used to
; discover conflicts between constraints for randomize() failures.
; The default is "many".
;
; Valid schemes are:
; "many" = best for determining conflicts due to many related constraints
; "few" = best for determining conflicts due to few related constraints
;
; SolveFailDebugScheme = many
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum number of constraint subsets that will be tested for
; conflicts.
; The default is 0 (no limit).
; SolveFailDebugLimit = 0
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum size of constraint subsets that will be tested for
; conflicts.
; The default value is 0 (no limit).
; SolveFailDebugMaxSet = 0
 
; Maximum size of the solution graph that may be generated during randomize().
; This value can be used to force randomize() to abort if the complexity of
; the constraint scenario (both in memory and time spent during evaluation)
; exceeds the specified limit. This value is specified in 1000s of nodes.
; The default is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000
 
; Use SolveFlags to specify options that will guide the behavior of the
; constraint solver. These options may improve the performance of the
; constraint solver for some testcases, and decrease the performance of
; the constraint solver for others.
; The default value is "" (no options).
;
; Valid flags are:
; c = interleave bits of concatenation operands
; i = disable bit interleaving for >, >=, <, <= constraints
; n = disable bit interleaving for all constraints
; r = reverse bit interleaving
;
; SolveFlags =
 
; Specify random sequence compatiblity with a prior letter release. This
; option is used to get the same random sequences during simulation as
; as a prior letter release. Only prior letter releases (of the current
; number release) are allowed.
; Note: To achieve the same random sequences, solver optimizations and/or
; bug fixes introduced since the specified release may be disabled -
; yielding the performance / behavior of the prior release.
; Default value set to "" (random compatibility not required).
; SolveRev =
 
; Environment variable expansion of command line arguments has been depricated
; in favor shell level expansion. Universal environment variable expansion
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this
; deprecated behavior. The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0
 
; Turn on/off collapsing of bus ports in VCD dumpports output
DumpportsCollapse = 1
 
; Location of Multi-Level Verification Component (MVC) installation.
; The default location is the product installation directory.
; MvcHome = $MODEL_TECH/...
 
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
 
; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of Verilog display system task messages and
; PLI/FLI print function call messages. The system tasks include
; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
; also include the analogous file I/O tasks that write to STDOUT
; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
; is to have messages appear only in the transcript. The other
; settings are to send messages to the wlf file only (messages that
; are recorded in the wlf file can be viewed in the MsgViewer) or
; to both the transcript and the wlf file. The valid values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; displaymsgmode = tran
 
; Control transcripting of elaboration/runtime messages not
; addressed by the displaymsgmode setting. The default is to
; have messages appear in the transcript and recorded in the wlf
; file (messages that are recorded in the wlf file can be viewed
; in the MsgViewer). The other settings are to send messages
; only to the transcript or only to the wlf file. The valid
; values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
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Project_DefaultLib = work
Project_SortMethod = unused
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Project_File_4 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/models/async_mem_master.v
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Project_File_5 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/test_harness.v
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Project_File_6 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/top.v
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Project_File_7 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/soc_ram.v
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Project_File_8 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/sync.v
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Project_File_10 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/models/wb_slave_model.v
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Project_Folder_Count = 0
Echo_Compile_Output = 0
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ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
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UCDB_CustomDoubleClick =
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Project_Minor_Version = 4
/wb_async_mem_bridge/trunk/sim/models/s29al032d_00.v
0,0 → 1,2816
//////////////////////////////////////////////////////////////////////////////
// File name : s29al032d_00.v
//////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2005 Spansion, LLC.
//
// MODIFICATION HISTORY :
//
//
// version: | author: | mod date: | changes made:
// V1.0 D.Lukovic 05 May 17 Initial release
//
//////////////////////////////////////////////////////////////////////////////
//
// PART DESCRIPTION:
//
// Library: FLASH
// Technology: Flash memory
// Part: s29al032d_00
//
// Description: 32Mbit (4M x 8-Bit) Flash Memory
//
//
//
///////////////////////////////////////////////////////////////////////////////
// Known Bugs:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ns
 
module s29al032d_00
(
A21 ,
A20 ,
A19 ,
A18 ,
A17 ,
A16 ,
A15 ,
A14 ,
A13 ,
A12 ,
A11 ,
A10 ,
A9 ,
A8 ,
A7 ,
A6 ,
A5 ,
A4 ,
A3 ,
A2 ,
A1 ,
A0 ,
 
DQ7 ,
DQ6 ,
DQ5 ,
DQ4 ,
DQ3 ,
DQ2 ,
DQ1 ,
DQ0 ,
 
CENeg ,
OENeg ,
WENeg ,
RESETNeg ,
ACC ,
RY
 
);
 
////////////////////////////////////////////////////////////////////////
// Port / Part Pin Declarations
////////////////////////////////////////////////////////////////////////
 
input A21 ;
input A20 ;
input A19 ;
input A18 ;
input A17 ;
input A16 ;
input A15 ;
input A14 ;
input A13 ;
input A12 ;
input A11 ;
input A10 ;
input A9 ;
input A8 ;
input A7 ;
input A6 ;
input A5 ;
input A4 ;
input A3 ;
input A2 ;
input A1 ;
input A0 ;
 
inout DQ7 ;
inout DQ6 ;
inout DQ5 ;
inout DQ4 ;
inout DQ3 ;
inout DQ2 ;
inout DQ1 ;
inout DQ0 ;
 
input CENeg ;
input OENeg ;
input WENeg ;
input RESETNeg ;
input ACC ;
output RY ;
 
// interconnect path delay signals
 
wire A21_ipd ;
wire A20_ipd ;
wire A19_ipd ;
wire A18_ipd ;
wire A17_ipd ;
wire A16_ipd ;
wire A15_ipd ;
wire A14_ipd ;
wire A13_ipd ;
wire A12_ipd ;
wire A11_ipd ;
wire A10_ipd ;
wire A9_ipd ;
wire A8_ipd ;
wire A7_ipd ;
wire A6_ipd ;
wire A5_ipd ;
wire A4_ipd ;
wire A3_ipd ;
wire A2_ipd ;
wire A1_ipd ;
wire A0_ipd ;
 
wire [21 : 0] A;
assign A = {
A21_ipd,
A20_ipd,
A19_ipd,
A18_ipd,
A17_ipd,
A16_ipd,
A15_ipd,
A14_ipd,
A13_ipd,
A12_ipd,
A11_ipd,
A10_ipd,
A9_ipd,
A8_ipd,
A7_ipd,
A6_ipd,
A5_ipd,
A4_ipd,
A3_ipd,
A2_ipd,
A1_ipd,
A0_ipd };
 
wire DQ7_ipd ;
wire DQ6_ipd ;
wire DQ5_ipd ;
wire DQ4_ipd ;
wire DQ3_ipd ;
wire DQ2_ipd ;
wire DQ1_ipd ;
wire DQ0_ipd ;
 
wire [7 : 0 ] DIn;
assign DIn = {DQ7_ipd,
DQ6_ipd,
DQ5_ipd,
DQ4_ipd,
DQ3_ipd,
DQ2_ipd,
DQ1_ipd,
DQ0_ipd };
 
wire [7 : 0 ] DOut;
assign DOut = {DQ7,
DQ6,
DQ5,
DQ4,
DQ3,
DQ2,
DQ1,
DQ0 };
 
wire CENeg_ipd ;
wire OENeg_ipd ;
wire WENeg_ipd ;
wire RESETNeg_ipd ;
wire ACC_ipd ;
wire VIO_ipd ;
 
// internal delays
 
reg HANG_out ; // Program/Erase Timing Limit
reg HANG_in ;
reg START_T1 ; // Start TimeOut
reg START_T1_in ;
reg CTMOUT ; // Sector Erase TimeOut
reg CTMOUT_in ;
reg READY_in ;
reg READY ; // Device ready after reset
 
reg [7 : 0] DOut_zd;
wire DQ7_Pass ;
wire DQ6_Pass ;
wire DQ5_Pass ;
wire DQ4_Pass ;
wire DQ3_Pass ;
wire DQ2_Pass ;
wire DQ1_Pass ;
wire DQ0_Pass ;
 
reg [7 : 0] DOut_Pass;
assign {DQ7_Pass,
DQ6_Pass,
DQ5_Pass,
DQ4_Pass,
DQ3_Pass,
DQ2_Pass,
DQ1_Pass,
DQ0_Pass } = DOut_Pass;
 
reg RY_zd;
 
parameter UserPreload = 1'b0;
parameter mem_file_name = "none";
parameter prot_file_name = "none";
parameter secsi_file_name = "none";
 
parameter TimingModel = "DefaultTimingModel";
 
parameter DelayValues = "FROM_PLI";
parameter PartID = "s29al032d";
parameter MaxData = 255;
parameter SecSize = 65535;
parameter SecNum = 63;
parameter HiAddrBit = 21;
parameter SecSiSize = 255;
 
// powerup
reg PoweredUp;
 
//FSM control signals
reg ULBYPASS ; ////Unlock Bypass Active
reg ESP_ACT ; ////Erase Suspend
reg OTP_ACT ; ////SecSi Access
 
reg PDONE ; ////Prog. Done
reg PSTART ; ////Start Programming
//Program location is in protected sector
reg PERR ;
 
reg EDONE ; ////Ers. Done
reg ESTART ; ////Start Erase
reg ESUSP ; ////Suspend Erase
reg ERES ; ////Resume Erase
//All sectors selected for erasure are protected
reg EERR ;
 
//Sectors selected for erasure
reg [SecNum:0] Ers_queue; // = SecNum'b0;
 
//Command Register
reg write ;
reg read ;
 
//Sector Address
integer SecAddr = 0;
 
integer SA = 0;
 
//Address within sector
integer Address = 0;
integer MemAddress = 0;
integer SecSiAddr = 0;
integer AS_ID = 0;
integer AS_SecSi_FP = 0;
integer AS_ID2 = 0;
//A19:A11 Don't Care
integer Addr ;
 
//glitch protection
wire gWE_n ;
wire gCE_n ;
wire gOE_n ;
 
reg RST ;
reg reseted ;
 
integer Mem[0:(SecNum+1)*(SecSize+1)-1];
//Sector Protection Status
reg [SecNum:0] Sec_Prot;
 
// timing check violation
reg Viol = 1'b0;
// CFI query address
integer SecSi[0:SecSiSize];
integer CFI_array[16:79];
 
reg FactoryProt = 0;
 
integer WBData;
integer WBAddr;
 
reg oe = 1'b0;
event oe_event;
 
event initOK;
event MergeE;
 
//Status reg.
reg[15:0] Status = 8'b0;
 
reg[7:0] old_bit, new_bit;
integer old_int, new_int;
integer wr_cnt;
reg[7:0] temp;
 
integer S_ind = 0;
integer ind = 0;
 
integer i,j,k;
 
integer Debug;
 
//TPD_XX_DATA
time OEDQ_t;
time CEDQ_t;
time ADDRDQ_t;
time OENeg_event;
time CENeg_event;
time OENeg_posEvent;
time CENeg_posEvent;
time ADDR_event;
reg FROMOE;
reg FROMCE;
reg FROMADDR;
integer OEDQ_01;
integer CEDQ_01;
integer ADDRDQ_01;
 
reg[7:0] TempData;
 
///////////////////////////////////////////////////////////////////////////////
//Interconnect Path Delay Section
///////////////////////////////////////////////////////////////////////////////
buf (A21_ipd, A21);
buf (A20_ipd, A20);
buf (A19_ipd, A19);
buf (A18_ipd, A18);
buf (A17_ipd, A17);
buf (A16_ipd, A16);
buf (A15_ipd, A15);
buf (A14_ipd, A14);
buf (A13_ipd, A13);
buf (A12_ipd, A12);
buf (A11_ipd, A11);
buf (A10_ipd, A10);
buf (A9_ipd , A9 );
buf (A8_ipd , A8 );
buf (A7_ipd , A7 );
buf (A6_ipd , A6 );
buf (A5_ipd , A5 );
buf (A4_ipd , A4 );
buf (A3_ipd , A3 );
buf (A2_ipd , A2 );
buf (A1_ipd , A1 );
buf (A0_ipd , A0 );
 
buf (DQ7_ipd , DQ7 );
buf (DQ6_ipd , DQ6 );
buf (DQ5_ipd , DQ5 );
buf (DQ4_ipd , DQ4 );
buf (DQ3_ipd , DQ3 );
buf (DQ2_ipd , DQ2 );
buf (DQ1_ipd , DQ1 );
buf (DQ0_ipd , DQ0 );
 
buf (CENeg_ipd , CENeg );
buf (OENeg_ipd , OENeg );
buf (WENeg_ipd , WENeg );
buf (RESETNeg_ipd , RESETNeg );
buf (ACC_ipd , ACC );
///////////////////////////////////////////////////////////////////////////////
// Propagation delay Section
///////////////////////////////////////////////////////////////////////////////
nmos (DQ7 , DQ7_Pass , 1);
nmos (DQ6 , DQ6_Pass , 1);
nmos (DQ5 , DQ5_Pass , 1);
nmos (DQ4 , DQ4_Pass , 1);
nmos (DQ3 , DQ3_Pass , 1);
nmos (DQ2 , DQ2_Pass , 1);
nmos (DQ1 , DQ1_Pass , 1);
nmos (DQ0 , DQ0_Pass , 1);
nmos (RY , 1'b0 , ~RY_zd);
 
wire deg;
 
//VHDL VITAL CheckEnable equivalents
// Address setup/hold near WE# falling edge
wire CheckEnable_A0_WE;
assign CheckEnable_A0_WE = ~CENeg && OENeg;
// Data setup/hold near WE# rising edge
wire CheckEnable_DQ0_WE;
assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg;
// Address setup/hold near CE# falling edge
wire CheckEnable_A0_CE;
assign CheckEnable_A0_CE = ~WENeg && OENeg;
// Data setup/hold near CE# rising edge
wire CheckEnable_DQ0_CE;
assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg;
 
specify
 
// tipd delays: interconnect path delays , mapped to input port delays.
// In Verilog is not necessary to declare any tipd_ delay variables,
// they can be taken from SDF file
// With all the other delays real delays would be taken from SDF file
 
// tpd delays
specparam tpd_RESETNeg_DQ0 =1;
specparam tpd_A0_DQ0 =1;//tacc ok
specparam tpd_CENeg_DQ0 =1;//ok
//(tCE,tCE,tDF,-,tDF,-)
specparam tpd_OENeg_DQ0 =1;//ok
//(tOE,tOE,tDF,-,tDF,-)
specparam tpd_WENeg_RY =1; //tBUSY
specparam tpd_CENeg_RY =1; //tBUSY
 
// tsetup values: setup time
specparam tsetup_A0_WENeg =1; //tAS edge \
specparam tsetup_DQ0_WENeg =1; //tDS edge /
 
// thold values: hold times
specparam thold_A0_WENeg =1; //tAH edge \
specparam thold_DQ0_CENeg =1; //tDH edge /
specparam thold_OENeg_WENeg =1; //tOEH edge /
specparam thold_CENeg_RESETNeg =1; //tRH edge /
specparam thold_WENeg_OENeg =1; //tGHVL edge /
 
// tpw values: pulse width
specparam tpw_RESETNeg_negedge =1; //tRP
specparam tpw_WENeg_negedge =1; //tWP
specparam tpw_WENeg_posedge =1; //tWPH
specparam tpw_CENeg_negedge =1; //tCP
specparam tpw_CENeg_posedge =1; //tCEPH
specparam tpw_A0_negedge =1; //tWC tRC ok
specparam tpw_A0_posedge =1; //tWC tRC ok
// tdevice values: values for internal delays
//Program Operation
specparam tdevice_POB = 9000; //9 us;
//Sector Erase Operation
specparam tdevice_SEO = 700000000; //700 ms;
//Timing Limit Exceeded
specparam tdevice_HANG = 400000000; //400 ms;
//Erase suspend time
specparam tdevice_START_T1 = 20000; //20 us;
//sector erase command sequence timeout
specparam tdevice_CTMOUT = 50000; //50 us;
//device ready after Hardware reset(during embeded algorithm)
specparam tdevice_READY = 20000; //20 us; //tReady
 
// If tpd values are fetched from specify block, these parameters
// must change along with SDF values, SDF values change will NOT
// imlicitly apply here !
// If you want tpd values to be fetched by the model itself, please
// use the PLI routine approach but be shure to set parameter
// DelayValues to "FROM_PLI" as default
 
///////////////////////////////////////////////////////////////////////////////
// Input Port Delays don't require Verilog description
///////////////////////////////////////////////////////////////////////////////
// Path delays //
///////////////////////////////////////////////////////////////////////////////
//for DQ signals
if (FROMCE)
( CENeg => DQ0 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ1 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ2 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ3 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ4 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ5 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ6 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ7 ) = tpd_CENeg_DQ0;
 
if (FROMOE)
( OENeg => DQ0 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ1 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ2 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ3 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ4 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ5 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ6 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ7 ) = tpd_OENeg_DQ0;
 
if (FROMADDR)
( A0 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ7 ) = tpd_A0_DQ0;
 
if (FROMADDR)
( A19 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ7 ) = tpd_A0_DQ0;
 
if (FROMADDR)
( A20 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ7 ) = tpd_A0_DQ0;
 
if (FROMADDR)
( A21 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ7 ) = tpd_A0_DQ0;
 
if (~RESETNeg)
( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0;
 
//for RY signal
(WENeg => RY) = tpd_WENeg_RY;
(CENeg => RY) = tpd_CENeg_RY;
 
////////////////////////////////////////////////////////////////////////////////
// Timing Violation //
////////////////////////////////////////////////////////////////////////////////
 
$setup ( A0 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A1 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A2 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A3 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A4 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A5 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A6 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A7 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A8 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A9 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A21, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
 
$setup ( A0 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A1 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A2 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A3 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A4 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A5 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A6 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A7 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A8 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A9 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A10, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A11, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A12, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A13, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A14, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A15, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A16, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A17, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A18, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A19, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A20, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A21, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
 
$setup ( DQ0, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ1, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ2, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ3, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ4, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ5, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ6, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ7, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
 
$setup ( DQ0, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ1, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ2, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ3, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ4, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ5, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ6, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ7, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
 
$hold ( posedge RESETNeg&&&(CENeg===1), CENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge RESETNeg&&&(OENeg===1), OENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge RESETNeg&&&(WENeg===1), WENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge OENeg, WENeg, thold_WENeg_OENeg, Viol);
$hold ( posedge WENeg, OENeg, thold_OENeg_WENeg, Viol);
 
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A0 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A1 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A2 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A3 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A4 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A5 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A6 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A7 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A9 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A21 , thold_A0_WENeg, Viol);
 
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A21 , thold_A0_WENeg, Viol);
 
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7, thold_DQ0_CENeg, Viol);
 
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7, thold_DQ0_CENeg, Viol);
 
$width (negedge RESETNeg, tpw_RESETNeg_negedge);
$width (posedge WENeg, tpw_WENeg_posedge);
$width (negedge WENeg, tpw_WENeg_negedge);
$width (posedge CENeg, tpw_CENeg_posedge);
$width (negedge CENeg, tpw_CENeg_negedge);
$width (negedge A0, tpw_A0_negedge);//ok
$width (negedge A1, tpw_A0_negedge);//ok
$width (negedge A2, tpw_A0_negedge);//ok
$width (negedge A3, tpw_A0_negedge);//ok
$width (negedge A4, tpw_A0_negedge);//ok
$width (negedge A5, tpw_A0_negedge);//ok
$width (negedge A6, tpw_A0_negedge);//ok
$width (negedge A7, tpw_A0_negedge);//ok
$width (negedge A8, tpw_A0_negedge);//ok
$width (negedge A9, tpw_A0_negedge);//ok
$width (negedge A10, tpw_A0_negedge);//ok
$width (negedge A11, tpw_A0_negedge);//ok
$width (negedge A12, tpw_A0_negedge);//ok
$width (negedge A13, tpw_A0_negedge);//ok
$width (negedge A14, tpw_A0_negedge);//ok
$width (negedge A15, tpw_A0_negedge);//ok
$width (negedge A16, tpw_A0_negedge);//ok
$width (negedge A17, tpw_A0_negedge);//ok
$width (negedge A18, tpw_A0_negedge);//ok
$width (negedge A19, tpw_A0_negedge);//ok
$width (negedge A20, tpw_A0_negedge);//ok
$width (negedge A21, tpw_A0_negedge);//ok
$width (posedge A0, tpw_A0_posedge);//ok
$width (posedge A1, tpw_A0_posedge);//ok
$width (posedge A2, tpw_A0_posedge);//ok
$width (posedge A3, tpw_A0_posedge);//ok
$width (posedge A4, tpw_A0_posedge);//ok
$width (posedge A5, tpw_A0_posedge);//ok
$width (posedge A6, tpw_A0_posedge);//ok
$width (posedge A7, tpw_A0_posedge);//ok
$width (posedge A8, tpw_A0_posedge);//ok
$width (posedge A9, tpw_A0_posedge);//ok
$width (posedge A10, tpw_A0_posedge);//ok
$width (posedge A11, tpw_A0_posedge);//ok
$width (posedge A12, tpw_A0_posedge);//ok
$width (posedge A13, tpw_A0_posedge);//ok
$width (posedge A14, tpw_A0_posedge);//ok
$width (posedge A15, tpw_A0_posedge);//ok
$width (posedge A16, tpw_A0_posedge);//ok
$width (posedge A17, tpw_A0_posedge);//ok
$width (posedge A18, tpw_A0_posedge);//ok
$width (posedge A19, tpw_A0_posedge);//ok
$width (posedge A20, tpw_A0_posedge);//ok
$width (posedge A21, tpw_A0_posedge);//ok
endspecify
 
////////////////////////////////////////////////////////////////////////////////
// Main Behavior Block //
////////////////////////////////////////////////////////////////////////////////
 
// FSM states
parameter RESET =6'd0;
parameter Z001 =6'd1;
parameter PREL_SETBWB =6'd2;
parameter PREL_ULBYPASS =6'd3;
parameter PREL_ULBYPASS_RESET =6'd4;
parameter AS =6'd5;
parameter A0SEEN =6'd6;
parameter OTP =6'd7;
parameter OTP_Z001 =6'd8;
parameter OTP_PREL =6'd9;
parameter OTP_AS =6'd10;
parameter OTP_AS_CFI =6'd11;
parameter OTP_A0SEEN =6'd12;
parameter C8 =6'd13;
parameter C8_Z001 =6'd14;
parameter C8_PREL =6'd15;
parameter ERS =6'd16;
parameter SERS =6'd17;
parameter ESPS =6'd18;
parameter SERS_EXEC =6'd19;
parameter ESP =6'd20;
parameter ESP_Z001 =6'd21;
parameter ESP_PREL =6'd22;
parameter ESP_A0SEEN =6'd23;
parameter ESP_AS =6'd24;
parameter PGMS =6'd25;
parameter CFI =6'd26;
parameter AS_CFI =6'd27;
parameter ESP_CFI =6'd28;
parameter ESP_AS_CFI =6'd29;
 
reg [5:0] current_state;
reg [5:0] next_state;
 
reg deq;
 
always @(DIn, DOut)
begin
if (DIn==DOut)
deq=1'b1;
else
deq=1'b0;
end
// check when data is generated from model to avoid setuphold check in
// those occasion
assign deg =deq;
 
// initialize memory and load preoload files if any
initial
begin : NBlck
integer i,j;
integer tmp1,tmp2,tmp3;
integer secure_silicon[0:SecSiSize];
reg sector_prot[0:SecNum];
 
for (i=0;i<=((SecNum+1)*(SecSize+1)-1);i=i+1)
begin
Mem[i]=MaxData;
end
for (i=0;i<=SecSiSize;i=i+1)
begin
secure_silicon[i]=MaxData;
end
for (i=0;i<=SecNum;i=i+1)
begin
sector_prot[i]=0;
end
if (UserPreload && !(prot_file_name == "none"))
begin
//s29al032d_00_prot sector protect file
// // - comment
// @aa - <aa> stands for sector address
// (aa is incremented at every load)
// b - <b> is 1 for protected sector <aa>, 0 for unprotect.
$readmemb(prot_file_name,sector_prot);
end
if (UserPreload && !(mem_file_name == "none"))
begin
//s29al032d_00_memory preload file
// @aaaaaa - <aaaaaa> stands for address within last defined sector
// dd - <dd> is byte to be written at Mem(nn)(aaaaaa++)
// (aaaaaa is incremented at every load)
$readmemh(mem_file_name,Mem);
end
if (UserPreload && !(secsi_file_name == "none"))
begin
//s29al032d_00_secsi memory preload file
// @aaaa - <aaaa> stands for address within last defined sector
// dd - <dd> is byte to be written at Mem(nn)(aaaa++)
// (aaaa is incremented at every load)
$readmemh(secsi_file_name,secure_silicon);
end
 
for (i=0;i<=SecSiSize;i=i+1)
begin
SecSi[i] = secure_silicon[i];
end
for (i=0;i<=SecNum;i=i+1)
Ers_queue[i] = 0;
// every 4-group sectors protect bit must equel
for (i=0;i<=SecNum;i=i+1)
Sec_Prot[i] = sector_prot[i];
 
if ((Sec_Prot[3:0] != 4'h0 && Sec_Prot[3:0] != 4'hF)
|| (Sec_Prot[7:4] != 4'h0 && Sec_Prot[7:4] != 4'hF)
|| (Sec_Prot[11:8] != 4'h0 && Sec_Prot[11:8] != 4'hF)
|| (Sec_Prot[15:12] != 4'h0 && Sec_Prot[15:12] != 4'hF)
|| (Sec_Prot[19:16] != 4'h0 && Sec_Prot[19:16] != 4'hF)
|| (Sec_Prot[23:20] != 4'h0 && Sec_Prot[23:20] != 4'hF)
|| (Sec_Prot[27:24] != 4'h0 && Sec_Prot[27:24] != 4'hF)
|| (Sec_Prot[31:28] != 4'h0 && Sec_Prot[31:28] != 4'hF)
|| (Sec_Prot[35:32] != 4'h0 && Sec_Prot[35:32] != 4'hF)
|| (Sec_Prot[39:36] != 4'h0 && Sec_Prot[39:36] != 4'hF)
|| (Sec_Prot[43:40] != 4'h0 && Sec_Prot[43:40] != 4'hF)
|| (Sec_Prot[47:44] != 4'h0 && Sec_Prot[47:44] != 4'hF)
|| (Sec_Prot[51:48] != 4'h0 && Sec_Prot[51:48] != 4'hF)
|| (Sec_Prot[55:52] != 4'h0 && Sec_Prot[55:52] != 4'hF)
|| (Sec_Prot[59:56] != 4'h0 && Sec_Prot[59:56] != 4'hF)
|| (Sec_Prot[63:60] != 4'h0 && Sec_Prot[63:60] != 4'hF))
 
$display("Bad sector protect group preload");
 
WBData = -1;
 
end
 
//Power Up time 100 ns;
initial
begin
PoweredUp = 1'b0;
#100 PoweredUp = 1'b1;
end
 
always @(RESETNeg)
begin
RST <= #499 RESETNeg;
end
 
initial
begin
write = 1'b0;
read = 1'b0;
Addr = 0;
 
ULBYPASS = 1'b0;
ESP_ACT = 1'b0;
OTP_ACT = 1'b0;
 
PDONE = 1'b1;
PSTART = 1'b0;
 
PERR = 1'b0;
 
EDONE = 1'b1;
ESTART = 1'b0;
ESUSP = 1'b0;
ERES = 1'b0;
 
EERR = 1'b0;
READY_in = 1'b0;
READY = 1'b0;
end
 
always @(posedge START_T1_in)
begin:TESTARTT1r
#tdevice_START_T1 START_T1 = START_T1_in;
end
always @(negedge START_T1_in)
begin:TESTARTT1f
#1 START_T1 = START_T1_in;
end
 
always @(posedge CTMOUT_in)
begin:TCTMOUTr
#tdevice_CTMOUT CTMOUT = CTMOUT_in;
end
always @(negedge CTMOUT_in)
begin:TCTMOUTf
#1 CTMOUT = CTMOUT_in;
end
 
always @(posedge READY_in)
begin:TREADYr
#tdevice_READY READY = READY_in;
end
always @(negedge READY_in)
begin:TREADYf
#1 READY = READY_in;
end
////////////////////////////////////////////////////////////////////////////
//// obtain 'LAST_EVENT information
////////////////////////////////////////////////////////////////////////////
always @(negedge OENeg)
begin
OENeg_event = $time;
end
always @(negedge CENeg)
begin
CENeg_event = $time;
end
 
always @(posedge OENeg)
begin
OENeg_posEvent = $time;
end
always @(posedge CENeg)
begin
CENeg_posEvent = $time;
end
 
always @(A)
begin
ADDR_event = $time;
end
 
////////////////////////////////////////////////////////////////////////////
//// sequential process for reset control and FSM state transition
////////////////////////////////////////////////////////////////////////////
always @(negedge RST)
begin
ESP_ACT = 1'b0;
ULBYPASS = 1'b0;
OTP_ACT = 1'b0;
end
 
reg R;
reg E;
always @(RESETNeg)
begin
if (PoweredUp)
begin
//Hardware reset timing control
if (~RESETNeg)
begin
E = 1'b0;
if (~PDONE || ~EDONE)
begin
//if program or erase in progress
READY_in = 1'b1;
R = 1'b1;
end
else
begin
READY_in = 1'b0;
R = 1'b0; //prog or erase not in progress
end
end
else if (RESETNeg && RST)
begin
//RESET# pulse < tRP
READY_in = 1'b0;
R = 1'b0;
E = 1'b1;
end
end
end
 
always @(next_state or RESETNeg or CENeg or RST or
READY or PoweredUp)
begin: StateTransition
 
if (PoweredUp)
begin
if (RESETNeg && (~R || (R && READY)))
begin
current_state = next_state;
READY_in = 1'b0;
E = 1'b0;
R = 1'b0;
reseted = 1'b1;
end
else if ((~R && ~RESETNeg && ~RST) ||
(R && ~RESETNeg && ~RST && ~READY) ||
(R && RESETNeg && ~RST && ~READY))
begin
//no state transition while RESET# low
current_state = RESET; //reset start
reseted = 1'b0;
end
end
else
begin
current_state = RESET; // reset
reseted = 1'b0;
E = 1'b0;
R = 1'b0;
end
end
 
// /////////////////////////////////////////////////////////////////////////
// //Glitch Protection: Inertial Delay does not propagate pulses <5ns
// /////////////////////////////////////////////////////////////////////////
assign #5 gWE_n = WENeg_ipd;
assign #5 gCE_n = CENeg_ipd;
assign #5 gOE_n = OENeg_ipd;
 
///////////////////////////////////////////////////////////////////////////
//Process that reports warning when changes on signals WE#, CE#, OE# are
//discarded
///////////////////////////////////////////////////////////////////////////
always @(WENeg)
begin: PulseWatch1
if (gWE_n == WENeg)
$display("Glitch on WE#");
end
always @(CENeg)
begin: PulseWatch2
if (gCE_n == CENeg)
$display("Glitch on CE#");
end
always @(OENeg)
begin: PulseWatch3
if (gOE_n == OENeg)
$display("Glitch on OE#");
end
 
//latch address on rising edge and data on falling edge of write
always @(gWE_n or gCE_n or gOE_n )
begin: write_dc
if (RESETNeg!=1'b0)
begin
if (~gWE_n && ~gCE_n && gOE_n)
write = 1'b1;
else
write = 1'b0;
end
 
if (gWE_n && ~gCE_n && ~gOE_n)
read = 1'b1;
else
read = 1'b0;
end
 
///////////////////////////////////////////////////////////////////////////
////Latch address on falling edge of WE# or CE# what ever comes later
////Latch data on rising edge of WE# or CE# what ever comes first
//// also Write cycle decode
////////////////////////////////////////////////////////////////////////////
integer A_tmp ;
integer SA_tmp ;
integer A_tmp1 ;
integer Mem_tmp;
integer AS_addr;
reg CE;
 
always @(WENeg_ipd)
begin
if (reseted)
begin
if (~WENeg_ipd && ~CENeg_ipd && OENeg_ipd )
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
end
end
end
 
always @(CENeg_ipd)
begin
if (reseted)
begin
if (~CENeg_ipd && (WENeg_ipd != OENeg_ipd) )
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
end
if (~CENeg_ipd && WENeg_ipd && ~OENeg_ipd)
begin
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
end
end
end
 
always @(negedge OENeg_ipd )
begin
if (reseted)
begin
if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd)
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
AS_addr = A[21];
end
 
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
CE = CENeg;
Addr = A_tmp;
end
end
 
always @(A)
begin
if (reseted)
if (WENeg_ipd && ~CENeg_ipd && ~OENeg_ipd)
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
CE = CENeg;
end
end
 
always @(posedge write)
begin
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
CE = CENeg;
end
 
///////////////////////////////////////////////////////////////////////////
// Timing control for the Program Operations
///////////////////////////////////////////////////////////////////////////
 
integer cnt_write = 0;
//time elapsed_write ;
time duration_write ;
//time start_write ;
event pdone_event;
 
always @(posedge reseted)
begin
PDONE = 1'b1;
end
 
always @(reseted or PSTART)
begin
if (reseted)
begin
if (PSTART && PDONE)
begin
if ((~FactoryProt && OTP_ACT)||
( ~Sec_Prot[SA] &&(~Ers_queue[SA] || ~ESP_ACT )&& ~OTP_ACT))
begin
duration_write = tdevice_POB + 5;
PDONE = 1'b0;
->pdone_event;
end
else
begin
PERR = 1'b1;
PERR <= #1005 1'b0;
end
end
end
end
 
always @(pdone_event)
begin:pdone_process
PDONE = 1'b0;
#duration_write PDONE = 1'b1;
end
 
/////////////////////////////////////////////////////////////////////////
// Timing control for the Erase Operations
/////////////////////////////////////////////////////////////////////////
integer cnt_erase = 0;
time elapsed_erase;
time duration_erase;
time start_erase;
 
always @(posedge reseted)
begin
disable edone_process;
EDONE = 1'b1;
end
event edone_event;
always @(reseted or ESTART)
begin: erase
integer i;
if (reseted)
begin
if (ESTART && EDONE)
begin
cnt_erase = 0;
for (i=0;i<=SecNum;i=i+1)
begin
if ((Ers_queue[i]==1'b1) && (Sec_Prot[i]!=1'b1))
cnt_erase = cnt_erase + 1;
end
 
if (cnt_erase>0)
begin
elapsed_erase = 0;
duration_erase = cnt_erase* tdevice_SEO + 4;
->edone_event;
start_erase = $time;
end
else
begin
EERR = 1'b1;
EERR <= #100005 1'b0;
end
end
end
end
 
always @(edone_event)
begin : edone_process
EDONE = 1'b0;
#duration_erase EDONE = 1'b1;
end
 
always @(reseted or ESUSP)
begin
if (reseted)
if (ESUSP && ~EDONE)
begin
disable edone_process;
elapsed_erase = $time - start_erase;
duration_erase = duration_erase - elapsed_erase;
EDONE = 1'b0;
end
end
always @(reseted or ERES)
begin
if (reseted)
if (ERES && ~EDONE)
begin
start_erase = $time;
EDONE = 1'b0;
->edone_event;
end
end
 
// /////////////////////////////////////////////////////////////////////////
// // Main Behavior Process
// // combinational process for next state generation
// /////////////////////////////////////////////////////////////////////////
reg PATTERN_1 = 1'b0;
reg PATTERN_2 = 1'b0;
reg A_PAT_1 = 1'b0;
reg A_PAT_2 = 1'b0;
reg A_PAT_3 = 1'b0;
integer DataByte ;
 
always @(negedge write)
begin
DataByte = DIn;
PATTERN_1 = DataByte==8'hAA ;
PATTERN_2 = DataByte==8'h55 ;
A_PAT_1 = 1'b1;
A_PAT_2 = Address==16'hAAA ;
A_PAT_3 = Address==16'h555 ;
end
 
always @(write or reseted)
begin: StateGen1
if (reseted!=1'b1)
next_state = current_state;
else
if (~write)
case (current_state)
RESET :
begin
if (PATTERN_1)
next_state = Z001;
else if ((Addr==8'h55) && (DataByte==8'h98))
next_state = CFI;
else
next_state = RESET;
end
 
CFI:
begin
if (DataByte==8'hF0)
next_state = RESET;
else
next_state = CFI;
end
 
Z001 :
begin
if (PATTERN_2)
next_state = PREL_SETBWB;
else
next_state = RESET;
end
 
PREL_SETBWB :
begin
if (A_PAT_1 && (DataByte==16'h20))
next_state = PREL_ULBYPASS;
else if (A_PAT_1 && (DataByte==16'h90))
next_state = AS;
else if (A_PAT_1 && (DataByte==16'hA0))
next_state = A0SEEN;
else if (A_PAT_1 && (DataByte==16'h80))
next_state = C8;
else if (A_PAT_1 && (DataByte==16'h88))
next_state = OTP;
else
next_state = RESET;
end
 
PREL_ULBYPASS :
begin
if (DataByte == 16'h90 )
next_state <= PREL_ULBYPASS_RESET;
if (A_PAT_1 && (DataByte == 16'hA0))
next_state = A0SEEN;
else
next_state = PREL_ULBYPASS;
end
 
PREL_ULBYPASS_RESET :
begin
if (DataByte == 16'h00 )
if (ESP_ACT)
next_state = ESP;
else
next_state = RESET;
else
next_state <= PREL_ULBYPASS;
end
 
AS :
begin
if (DataByte==16'hF0)
next_state = RESET;
else if ((Addr==8'h55) && (DataByte==8'h98))
next_state = AS_CFI;
else
next_state = AS;
end
 
AS_CFI:
begin
if (DataByte==8'hF0)
next_state = AS;
else
next_state = AS_CFI;
end
 
A0SEEN :
begin
next_state = PGMS;
end
 
OTP :
begin
if (PATTERN_1)
next_state = OTP_Z001;
else
next_state = OTP;
end
 
OTP_Z001 :
begin
if (PATTERN_2)
next_state = OTP_PREL;
else
next_state = OTP;
end
 
OTP_PREL :
begin
if (A_PAT_1 && (DataByte == 16'h90))
next_state = OTP_AS;
else if (A_PAT_1 && (DataByte == 16'hA0))
next_state = OTP_A0SEEN;
else
next_state = OTP;
end
 
OTP_AS:
begin
if (DataByte == 16'h00)
if (ESP_ACT)
next_state = ESP;
else
next_state = RESET;
else if (DataByte == 16'hF0)
next_state = OTP;
else if (DataByte == 16'h98)
next_state = OTP_AS_CFI;
else
next_state = OTP_AS;
end
 
OTP_AS_CFI:
begin
if (DataByte == 16'hF0)
next_state = OTP_AS;
else
next_state = OTP_AS_CFI;
end
 
OTP_A0SEEN :
begin
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
(Address >= 16'hFF00))
next_state = PGMS;
else
next_state = OTP;
end
 
C8 :
begin
if (PATTERN_1)
next_state = C8_Z001;
else
next_state = RESET;
end
 
C8_Z001 :
begin
if (PATTERN_2)
next_state = C8_PREL;
else
next_state = RESET;
end
 
C8_PREL :
begin
if (A_PAT_1 && (DataByte==16'h10))
next_state = ERS;
else if (DataByte==16'h30)
next_state = SERS;
else
next_state = RESET;
end
 
ERS :
begin
end
 
SERS :
begin
if (~CTMOUT && DataByte == 16'hB0)
next_state = ESP; // ESP according to datasheet
else if (DataByte==16'h30)
next_state = SERS;
else
next_state = RESET;
end
 
SERS_EXEC :
begin
end
 
ESP :
begin
if (DataByte == 16'h30)
next_state = SERS_EXEC;
else
begin
if (PATTERN_1)
next_state = ESP_Z001;
if (Addr == 8'h55 && DataByte == 8'h98)
next_state = ESP_CFI;
end
end
 
ESP_CFI:
begin
if (DataByte == 8'hF0)
next_state = ESP;
else
next_state = ESP_CFI;
end
 
ESP_Z001 :
begin
if (PATTERN_2)
next_state = ESP_PREL;
else
next_state = ESP;
end
 
ESP_PREL :
begin
if (A_PAT_1 && DataByte == 16'hA0)
next_state = ESP_A0SEEN;
else if (A_PAT_1 && DataByte == 16'h20)
next_state <= PREL_ULBYPASS;
else if (A_PAT_1 && DataByte == 16'h88)
next_state <= OTP;
else if (A_PAT_1 && DataByte == 16'h90)
next_state = ESP_AS;
else
next_state = ESP;
end
 
ESP_A0SEEN :
begin
next_state = PGMS; //set ESP
end
 
ESP_AS :
begin
if (DataByte == 16'hF0)
next_state = ESP;
else if ((Addr==8'h55) && (DataByte==8'h98))
next_state = ESP_AS_CFI;
end
 
ESP_AS_CFI:
begin
if (DataByte == 8'hF0)
next_state = ESP_AS;
else
next_state = ESP_AS_CFI;
end
 
endcase
end
 
always @(posedge PDONE or negedge PERR)
begin: StateGen6
if (reseted!=1'b1)
next_state = current_state;
else
begin
if (current_state==PGMS && ULBYPASS)
next_state = PREL_ULBYPASS;
else if (current_state==PGMS && OTP_ACT)
next_state = OTP;
else if (current_state==PGMS && ESP_ACT)
next_state = ESP;
else if (current_state==PGMS)
next_state = RESET;
end
end
 
always @(posedge EDONE or negedge EERR)
begin: StateGen2
if (reseted!=1'b1)
next_state = current_state;
else
begin
if ((current_state==ERS) || (current_state==SERS_EXEC))
next_state = RESET;
end
end
 
always @(negedge write or reseted)
begin: StateGen7 //ok
integer i,j;
if (reseted!=1'b1)
next_state = current_state;
else
begin
if (current_state==SERS_EXEC && (write==1'b0) && (EERR!=1'b1))
if (DataByte==16'hB0)
begin
next_state = ESPS;
ESUSP = 1'b1;
ESUSP <= #1 1'b0;
end
end
end
 
always @(CTMOUT or reseted)
begin: StateGen4
if (reseted!=1'b1)
next_state = current_state;
else
begin
if (current_state==SERS && CTMOUT) next_state = SERS_EXEC;
end
end
 
always @(posedge START_T1 or reseted)
begin: StateGen5
if (reseted!=1'b1)
next_state = current_state;
else
if (current_state==ESPS && START_T1) next_state = ESP;
end
 
///////////////////////////////////////////////////////////////////////////
//FSM Output generation and general funcionality
///////////////////////////////////////////////////////////////////////////
 
always @(posedge read)
begin
->oe_event;
end
always @(MemAddress)
begin
if (read)
->oe_event;
end
 
always @(oe_event)
begin
oe = 1'b1;
#1 oe = 1'b0;
end
 
always @(DOut_zd)
begin : OutputGen
if (DOut_zd[0] !== 1'bz)
begin
CEDQ_t = CENeg_event + CEDQ_01;
OEDQ_t = OENeg_event + OEDQ_01;
ADDRDQ_t = ADDR_event + ADDRDQ_01;
FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time));
FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time));
FROMADDR = 1'b1;
if ((ADDRDQ_t > $time )&&
(((ADDRDQ_t>OEDQ_t)&&FROMOE) ||
((ADDRDQ_t>CEDQ_t)&&FROMCE)))
begin
TempData = DOut_zd;
FROMADDR = 1'b0;
DOut_Pass = 8'bx;
#(ADDRDQ_t - $time) DOut_Pass = TempData;
end
else
begin
DOut_Pass = DOut_zd;
end
end
end
 
always @(DOut_zd)
begin
if (DOut_zd[0] === 1'bz)
begin
disable OutputGen;
FROMCE = 1'b1;
FROMOE = 1'b1;
if ((CENeg_posEvent <= OENeg_posEvent) &&
( CENeg_posEvent + 5 >= $time))
FROMOE = 1'b0;
if ((OENeg_posEvent < CENeg_posEvent) &&
( OENeg_posEvent + 5 >= $time))
FROMCE = 1'b0;
FROMADDR = 1'b0;
DOut_Pass = DOut_zd;
end
end
 
always @(oe or reseted or current_state)
begin
if (reseted)
begin
case (current_state)
 
RESET :
begin
if (oe)
MemRead(DOut_zd);
end
 
AS, ESP_AS, OTP_AS :
begin
if (oe)
begin
if (AS_addr == 1'b0)
begin
end
else
AS_ID = 1'b0;
if ((Address[7:0] == 0) && (AS_ID == 1'b1))
DOut_zd = 1;
else if ((Address[7:0] == 1) && (AS_ID == 1'b1))
DOut_zd = 8'hA3;
else if ((Address[7:0] == 2) &&
(((SecAddr < 32 ) && (AS_ID == 1'b1))
|| ((SecAddr > 31 ) && (AS_ID2 == 1'b1))))
begin
DOut_zd = 8'b00000000;
DOut_zd[0] = Sec_Prot[SecAddr];
end
else if ((Address[7:0] == 6) && (AS_SecSi_FP == 1'b1))
begin
DOut_zd = 8'b0;
if (FactoryProt)
DOut_zd = 16'h99;
else
DOut_zd = 16'h19;
end
else
DOut_zd = 8'bz;
end
end
 
OTP :
begin
if (oe)
begin
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
(Address >= 16'hFF00))
begin
SecSiAddr = Address%(SecSiSize +1);
if (SecSi[SecSiAddr]==-1)
DOut_zd = 8'bx;
else
DOut_zd = SecSi[SecSiAddr];
end
else
$display ("Invalid SecSi query address");
end
end
 
CFI, AS_CFI, ESP_CFI, ESP_AS_CFI, OTP_AS_CFI :
begin
if (oe)
begin
DOut_zd = 8'bZ;
if (((MemAddress>=16'h10) && (MemAddress <= 16'h3C)) ||
((MemAddress>=16'h40) && (MemAddress <= 16'h4F)))
begin
DOut_zd = CFI_array[MemAddress];
end
else
begin
$display ("Invalid CFI query address");
end
end
end
 
ERS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
// read status / embeded erase algorithm - Chip Erase
///////////////////////////////////////////////////////////
Status[7] = 1'b0;
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
Status[3] = 1'b1;
Status[2] = ~Status[2]; //toggle
 
DOut_zd = Status;
end
end
 
SERS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status - sector erase timeout
///////////////////////////////////////////////////////////
Status[3] = 1'b0;
Status[7] = 1'b1;
DOut_zd = Status;
end
end
 
ESPS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status / erase suspend timeout - stil erasing
///////////////////////////////////////////////////////////
if (Ers_queue[SecAddr]==1'b1)
begin
Status[7] = 1'b0;
Status[2] = ~Status[2]; //toggle
end
else
Status[7] = 1'b1;
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
Status[3] = 1'b1;
DOut_zd = Status;
end
end
 
SERS_EXEC:
begin
if (oe)
begin
///////////////////////////////////////////////////
//read status erase
///////////////////////////////////////////////////
if (Ers_queue[SecAddr]==1'b1)
begin
Status[7] = 1'b0;
Status[2] = ~Status[2]; //toggle
end
else
Status[7] = 1'b1;
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
Status[3] = 1'b1;
DOut_zd = Status;
end
end
 
ESP :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read
///////////////////////////////////////////////////////////
 
if (Ers_queue[SecAddr]!=1'b1)
begin
MemRead(DOut_zd);
end
else
begin
///////////////////////////////////////////////////////
//read status
///////////////////////////////////////////////////////
Status[7] = 1'b1;
// Status[6) No toggle
Status[5] = 1'b0;
Status[2] = ~Status[2]; //toggle
DOut_zd = Status;
end
end
end
 
PGMS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status
///////////////////////////////////////////////////////////
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
//Status[2) no toggle
Status[1] = 1'b0;
DOut_zd = Status;
if (SecAddr == SA)
DOut_zd[7] = Status[7];
else
DOut_zd[7] = ~Status[7];
end
 
end
endcase
end
end
 
always @(write or reseted)
begin : Output_generation
if (reseted)
begin
case (current_state)
RESET :
begin
ESP_ACT = 1'b0;
ULBYPASS = 1'b0;
OTP_ACT = 1'b0;
if (~write)
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1'b1;
else
AS_SecSi_FP = 1'b0;
end
 
Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1'b0;
end
 
PREL_SETBWB :
begin
if (~write)
begin
if (A_PAT_1 && (DataByte==16'h20))
ULBYPASS = 1'b1;
else if (A_PAT_1 && (DataByte==16'h90))
begin
ULBYPASS = 1'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1'b0;
if (AS_addr == 1'b0)
begin
AS_ID = 1'b1;
AS_ID2= 1'b0;
end
else
begin
AS_ID = 1'b0;
AS_ID2= 1'b1;
end
end
else if (A_PAT_1 && (DataByte==16'h88))
begin
OTP_ACT = 1;
ULBYPASS = 1'b0;
end
end
end
 
PREL_ULBYPASS :
begin
if (~write)
begin
ULBYPASS = 1'b1;
if (A_PAT_1 && (DataByte==16'h90))
ULBYPASS = 1'b0;
end
end
 
PREL_ULBYPASS_RESET :
if ((~write) && (DataByte != 16'h00 ))
ULBYPASS = 1'b1;
 
OTP_A0SEEN :
begin
if (~write)
begin
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
(Address >= 16'hFF00))
begin
SecSiAddr = Address%(SecSiSize +1);
OTP_ACT = 1;
PSTART = 1'b1;
PSTART <= #1 1'b0;
 
WBAddr = SecSiAddr;
SA = SecAddr;
temp = DataByte;
Status[7] = ~temp[7];
WBData = DataByte;
end
else
$display ("Invalid program address in SecSi region:"
,Address);
end
end
 
OTP_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16'h90))
begin
ULBYPASS = 1'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1'b0;
if (AS_addr == 1'b0)
begin
AS_ID = 1'b1;
AS_ID2= 1'b0;
end
else
begin
AS_ID = 1'b0;
AS_ID2= 1'b1;
end
end
end
 
OTP_Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1'b0;
end
OTP :
begin
if (~write)
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1'b1;
else
AS_SecSi_FP = 1'b0;
RY_zd = 1;
end
 
AS :
begin
if (~write)
if (DataByte==16'hF0)
begin
AS_SecSi_FP = 1'b0;
AS_ID = 1'b0;
AS_ID2 = 1'b0;
end
end
 
A0SEEN :
begin
if (~write)
begin
PSTART = 1'b1;
PSTART <= #1 1'b0;
WBData = DataByte;
WBAddr = Address;
SA = SecAddr;
Status[7] = ~DataByte[7];
end
end
 
C8 :
begin
end
 
C8_Z001 :
begin
end
 
C8_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16'h10))
begin
//Start Chip Erase
ESTART = 1'b1;
ESTART <= #1 1'b0;
ESUSP = 1'b0;
ERES = 1'b0;
Ers_queue = ~(0);
Status = 8'b00001000;
end
else if (DataByte==16'h30)
begin
//put selected sector to sec. ers. queue
//start timeout
Ers_queue = 0;
Ers_queue[SecAddr] = 1'b1;
disable TCTMOUTr;
CTMOUT_in = 1'b0;
#1 CTMOUT_in <= 1'b1;
end
end
 
ERS :
begin
end
 
SERS :
begin
if (~write && ~CTMOUT)
begin
if (DataByte == 16'hB0)
begin
//need to start erase process prior to suspend
ESTART = 1'b1;
ESTART = #1 1'b0;
ESUSP = #1 1'b0;
ESUSP = #1 1'b1;
ESUSP <= #2 1'b0;
ERES = 1'b0;
end
else if (DataByte==16'h30)
begin
disable TCTMOUTr;
CTMOUT_in = 1'b0;
#1 CTMOUT_in <= 1'b1;
Ers_queue[SecAddr] = 1'b1;
end
end
end
 
SERS_EXEC :
begin
if (~write)
if (~EDONE && (EERR!=1'b1) && DataByte==16'hB0)
START_T1_in = 1'b1;
end
 
ESP :
begin
if (~write)
begin
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1'b1;
else
AS_SecSi_FP = 1'b0;
if (DataByte == 16'h30)
begin
ERES = 1'b1;
ERES <= #1 1'b0;
end
end
end
 
ESP_Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1'b0;
end
 
ESP_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16'h90))
begin
ULBYPASS = 1'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1'b0;
if (AS_addr == 1'b0)
begin
AS_ID = 1'b1;
AS_ID2= 1'b0;
end
else
begin
AS_ID = 1'b0;
AS_ID2= 1'b1;
end
end
end
 
ESP_A0SEEN :
begin
if (~write)
begin
ESP_ACT = 1'b1;
PSTART = 1'b1;
PSTART <= #1 1'b0;
WBData = DataByte;
WBAddr = Address;
SA = SecAddr;
Status[7] = ~DataByte[7];
end
end
 
ESP_AS :
begin
end
 
endcase
end
end
 
initial
begin
///////////////////////////////////////////////////////////////////////
//CFI array data
///////////////////////////////////////////////////////////////////////
 
//CFI query identification string
for (i=16;i<92;i=i+1)
CFI_array[i] = -1;
 
CFI_array[16'h10] = 16'h51;
CFI_array[16'h11] = 16'h52;
CFI_array[16'h12] = 16'h59;
CFI_array[16'h13] = 16'h02;
CFI_array[16'h14] = 16'h00;
CFI_array[16'h15] = 16'h40;
CFI_array[16'h16] = 16'h00;
CFI_array[16'h17] = 16'h00;
CFI_array[16'h18] = 16'h00;
CFI_array[16'h19] = 16'h00;
CFI_array[16'h1A] = 16'h00;
 
//system interface string
CFI_array[16'h1B] = 16'h27;
CFI_array[16'h1C] = 16'h36;
CFI_array[16'h1D] = 16'h00;
CFI_array[16'h1E] = 16'h00;
CFI_array[16'h1F] = 16'h04;
CFI_array[16'h20] = 16'h00;
CFI_array[16'h21] = 16'h0A;
CFI_array[16'h22] = 16'h00;
CFI_array[16'h23] = 16'h05;
CFI_array[16'h24] = 16'h00;
CFI_array[16'h25] = 16'h04;
CFI_array[16'h26] = 16'h00;
//device geometry definition
CFI_array[16'h27] = 16'h16;
CFI_array[16'h28] = 16'h00;
CFI_array[16'h29] = 16'h00;
CFI_array[16'h2A] = 16'h00;
CFI_array[16'h2B] = 16'h00;
CFI_array[16'h2C] = 16'h01;
CFI_array[16'h2D] = 16'h3F;
CFI_array[16'h2E] = 16'h00;
CFI_array[16'h2F] = 16'h00;
CFI_array[16'h30] = 16'h01;
CFI_array[16'h31] = 16'h00;
CFI_array[16'h32] = 16'h00;
CFI_array[16'h33] = 16'h00;
CFI_array[16'h34] = 16'h00;
CFI_array[16'h35] = 16'h00;
CFI_array[16'h36] = 16'h00;
CFI_array[16'h37] = 16'h00;
CFI_array[16'h38] = 16'h00;
CFI_array[16'h39] = 16'h00;
CFI_array[16'h3A] = 16'h00;
CFI_array[16'h3B] = 16'h00;
CFI_array[16'h3C] = 16'h00;
 
//primary vendor-specific extended query
CFI_array[16'h40] = 16'h50;
CFI_array[16'h41] = 16'h52;
CFI_array[16'h42] = 16'h49;
CFI_array[16'h43] = 16'h31;
CFI_array[16'h44] = 16'h31;
CFI_array[16'h45] = 16'h01;
CFI_array[16'h46] = 16'h02;
CFI_array[16'h47] = 16'h01;
CFI_array[16'h48] = 16'h01;
CFI_array[16'h49] = 16'h04;
CFI_array[16'h4A] = 16'h00;
CFI_array[16'h4B] = 16'h00;
CFI_array[16'h4C] = 16'h00;
CFI_array[16'h4D] = 16'hB5;
CFI_array[16'h4E] = 16'hC5;
CFI_array[16'h4F] = 16'h00;
 
end
 
always @(current_state or reseted)
begin
if (reseted)
if (current_state==RESET) RY_zd = 1'b1;
if (current_state==PREL_ULBYPASS) RY_zd = 1'b1;
if (current_state==A0SEEN) RY_zd = 1'b1;
if (current_state==ERS) RY_zd = 1'b0;
if (current_state==SERS) RY_zd = 1'b0;
if (current_state==ESPS) RY_zd = 1'b0;
if (current_state==SERS_EXEC) RY_zd = 1'b0;
if (current_state==ESP) RY_zd = 1'b1;
if (current_state==OTP) RY_zd = 1'b1;
if (current_state==ESP_A0SEEN) RY_zd = 1'b1;
if (current_state==PGMS) RY_zd = 1'b0;
end
 
always @(EERR or EDONE or current_state)
begin : ERS2
integer i;
integer j;
if (current_state==ERS && EERR!=1'b1)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1)
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = -1;
end
if (current_state==ERS && EDONE)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1)
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = MaxData;
end
end
 
always @(CTMOUT or current_state)
begin : SERS2
if (current_state==SERS && CTMOUT)
begin
CTMOUT_in = 1'b0;
START_T1_in = 1'b0;
ESTART = 1'b1;
ESTART <= #1 1'b0;
ESUSP = 1'b0;
ERES = 1'b0;
end
end
 
always @(START_T1 or current_state)
begin : ESPS2
if (current_state==ESPS && START_T1)
begin
ESP_ACT = 1'b1;
START_T1_in = 1'b0;
end
end
 
always @(EERR or EDONE or current_state)
begin: SERS_EXEC2
integer i,j;
if (current_state==SERS_EXEC)
begin
if (EERR!=1'b1)
begin
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = -1;
 
if (EDONE)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = MaxData;
end
end
end
end
end
 
always @(current_state or posedge PDONE)
begin: PGMS2
integer i,j;
if (current_state==PGMS)
begin
if (PERR!=1'b1)
begin
new_int = WBData;
if (OTP_ACT!=1'b1) //mem write
old_int=Mem[sa(SA) + WBAddr];
else
old_int=SecSi[WBAddr];
new_bit = new_int;
if (old_int>-1)
begin
old_bit = old_int;
for(j=0;j<=7;j=j+1)
if (~old_bit[j])
new_bit[j]=1'b0;
new_int=new_bit;
end
WBData = new_int;
if (OTP_ACT!=1'b1) //mem write
Mem[sa(SA) + WBAddr] = -1;
else
SecSi[WBAddr] = -1;
if (PDONE && ~PSTART)
begin
if (OTP_ACT!=1'b1) //mem write
Mem[sa(SA) + WBAddr] = WBData;
else
SecSi[WBAddr] = WBData;
WBData= -1;
end
end
end
end
 
always @(gOE_n or gCE_n or RESETNeg or RST )
begin
//Output Disable Control
if (gOE_n || gCE_n || (~RESETNeg && ~RST))
DOut_zd = 8'bZ;
end
 
reg BuffInOE , BuffInCE , BuffInADDR;
wire BuffOutOE, BuffOutCE, BuffOutADDR;
 
BUFFER BUFOE (BuffOutOE, BuffInOE);
BUFFER BUFCE (BuffOutCE, BuffInCE);
BUFFER BUFADDR (BuffOutADDR, BuffInADDR);
initial
begin
BuffInOE = 1'b1;
BuffInCE = 1'b1;
BuffInADDR = 1'b1;
end
 
always @(posedge BuffOutOE)
begin
OEDQ_01 = $time;
end
always @(posedge BuffOutCE)
begin
CEDQ_01 = $time;
end
always @(posedge BuffOutADDR)
begin
ADDRDQ_01 = $time;
end
 
function integer sa;
input [7:0] sect;
begin
sa = sect * (SecSize + 1);
end
endfunction
 
task MemRead;
inout[7:0] DOut_zd;
begin
if (Mem[sa(SecAddr)+Address]==-1)
DOut_zd = 8'bx;
else
DOut_zd = Mem[sa(SecAddr)+Address];
end
endtask
endmodule
 
module BUFFER (OUT,IN);
input IN;
output OUT;
buf ( OUT, IN);
endmodule
/wb_async_mem_bridge/trunk/sim/models/wb_slave_model.v
0,0 → 1,138
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module wb_slave_model( clk_i, rst_i, dat_o, dat_i, adr_i,
cyc_i, stb_i, we_i, sel_i,
ack_o, err_o, rty_o );
 
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter ACK_DELAY = 2;
parameter SLAVE_RAM_INIT = "wb_slave_model.txt";
input clk_i;
input rst_i;
output [DWIDTH-1:0] dat_o;
input [DWIDTH-1:0] dat_i;
input [AWIDTH-1:0] adr_i;
input cyc_i;
input stb_i;
input we_i;
input [( (DWIDTH/8) - 1 ):0] sel_i;
output ack_o;
output err_o;
output rty_o;
// --------------------------------------------------------------------
// slave ram
reg [7:0] ram[2**AWIDTH-1:0];
initial
$readmemh( SLAVE_RAM_INIT, ram );
 
// --------------------------------------------------------------------
//
generate
case( DWIDTH )
8: begin
initial
$display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[adr_i] <= dat_i[7:0];
assign dat_o = ram[adr_i];
end
16: begin
initial
$display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[1])
ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];
assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };
end
32: begin
initial
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[{adr_i[AWIDTH-1:2], 2'b00}] <= dat_i[7:0];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[1])
ram[{adr_i[AWIDTH-1:2], 2'b01}] <= dat_i[15:8];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[2])
ram[{adr_i[AWIDTH-1:2], 2'b10}] <= dat_i[23:16];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[3])
ram[{adr_i[AWIDTH-1:2], 2'b11}] <= dat_i[31:24];
assign dat_o = { ram[{adr_i[AWIDTH-1:2], 2'b11}], ram[{adr_i[AWIDTH-1:2], 2'b10}], ram[{adr_i[AWIDTH-1:2], 2'b01}], ram[{adr_i[AWIDTH-1:2], 2'b00}] };
end
default: begin
localparam SLAVE_SIZE = -1;
initial
begin
$display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );
$stop();
end
end
endcase
endgenerate
 
// --------------------------------------------------------------------
// ack delay
reg ack_delayed;
initial
ack_delayed = 1'b0;
always @(posedge clk_i or cyc_i or stb_i)
begin
if(cyc_i & stb_i)
begin
ack_delayed = 1'b0;
repeat(ACK_DELAY) @(posedge clk_i);
if(cyc_i & stb_i)
ack_delayed = 1'b1;
else
ack_delayed = 1'b0;
end
else
ack_delayed = 1'b0;
end
// --------------------------------------------------------------------
// assign outputs
assign ack_o = ack_delayed;
assign err_o = 1'b0;
assign rty_o = 1'b0;
 
endmodule
/wb_async_mem_bridge/trunk/sim/models/IS61LV25616AL.v
0,0 → 1,107
// IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
// Note; 1) Please include "+define+ OEb" in running script if you want to check
// timing in the case of OE_ being set.
// 2) Please specify access time by defining tAC_10 or tAC_12.
 
// `define OEb
`define tAC_10
`timescale 1ns/10ps
 
module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
 
parameter dqbits = 16;
parameter memdepth = 262143;
parameter addbits = 18;
parameter Toha = 2;
 
parameter Tsa = 2;
 
`ifdef tAC_10
parameter Taa = 10,
Thzce = 3,
Thzwe = 5;
`endif
 
`ifdef tAC_12
parameter Taa = 12,
Thzce = 5,
Thzwe = 6;
`endif
 
input CE_, OE_, WE_, LB_, UB_;
input [(addbits - 1) : 0] A;
inout [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
 
wire r_en = WE_ & (~CE_) & (~OE_);
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_));
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
 
initial
$timeformat (-9, 0.1, " ns", 10);
 
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
 
always @(A or w_en)
begin
#Tsa
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
end
end
// Timing Check
`ifdef tAC_10
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 10,
tPWE1 = 8,
tPBW = 8;
`else
 
`ifdef tAC_10
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 12,
tPWE1 = 8,
tPBW = 8;
`endif
`endif
 
$setup (A, negedge CE_, tSA);
// $setup (A, posedge CE_, tAW);
// $setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
// $setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
 
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
 
endspecify
 
endmodule
 
/wb_async_mem_bridge/trunk/sim/models/async_mem_master.v
0,0 → 1,248
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module async_mem_master
#(
parameter log_level = 3,
parameter ce_setup = 10,
parameter op_hold = 15,
parameter dw = 32,
parameter aw = 32
)
(
inout [(dw-1):0] mem_d,
output [(aw-1):0] mem_a,
output mem_oe_n,
output [3:0] mem_bls_n,
output mem_we_n,
output mem_cs_n,
input tb_clk,
input tb_rst
);
 
 
// --------------------------------------------------------------------
// async_mem_default_state
reg [(dw-1):0] mem_d_r;
reg [(aw-1):0] mem_a_r;
reg mem_oe_n_r;
reg [3:0] mem_bls_n_r;
reg mem_we_n_r;
reg mem_cs_n_r;
reg tb_oe_r;
task async_mem_default_state;
begin
mem_d_r = 'bx;
mem_a_r = 'bx;
mem_oe_n_r = 1'b1;
mem_bls_n_r = 4'b1111;
mem_we_n_r = 1'b1;
tb_oe_r = 1'b0;
end
endtask
// --------------------------------------------------------------------
//
initial
begin
async_mem_default_state();
mem_cs_n_r = 1'b1;
end
 
// --------------------------------------------------------------------
// async_mem_3x_write
task async_mem_3x_write;
input [(dw-1):0] address;
input [(dw-1):0] data1;
input [(dw-1):0] data2;
input [(dw-1):0] data3;
input [3:0] byte_lane_select;
begin
if( log_level > 2 )
$display( "###- async_mem_3x_write: @ 0x%h at time %t. ", address, $time );
@(posedge tb_clk);
mem_cs_n_r = 1'b0;
repeat(ce_setup) @(posedge tb_clk);
mem_d_r = data1;
mem_a_r = address;
mem_oe_n_r = 1'b1;
mem_bls_n_r = byte_lane_select;
mem_we_n_r = 1'b0;
tb_oe_r = 1'b1;
repeat(op_hold) @(posedge tb_clk);
mem_we_n_r = 1'b1;
repeat(ce_setup) @(posedge tb_clk);
mem_d_r = data2;
mem_a_r = address + 4;
mem_we_n_r = 1'b0;
repeat(op_hold) @(posedge tb_clk);
mem_we_n_r = 1'b1;
repeat(ce_setup) @(posedge tb_clk);
mem_d_r = data3;
mem_a_r = address + 8;
mem_we_n_r = 1'b0;
repeat(op_hold) @(posedge tb_clk);
mem_we_n_r = 1'b1;
@(posedge tb_clk);
async_mem_default_state();
 
mem_cs_n_r = 1'b1;
end
endtask
// --------------------------------------------------------------------
// async_mem_write
task async_mem_write;
input [(dw-1):0] address;
input [(dw-1):0] data;
input [3:0] byte_lane_select;
begin
if( log_level > 2 )
$display( "###- async_mem_write: 0x%h @ 0x%h at time %t. ", data, address, $time );
@(posedge tb_clk);
mem_cs_n_r = 1'b0;
repeat(ce_setup) @(posedge tb_clk);
mem_d_r = data;
mem_a_r = address;
mem_oe_n_r = 1'b1;
mem_bls_n_r = byte_lane_select;
mem_we_n_r = 1'b0;
tb_oe_r = 1'b1;
repeat(op_hold) @(posedge tb_clk);
async_mem_default_state();
 
mem_cs_n_r = 1'b1;
end
endtask
// --------------------------------------------------------------------
// async_mem_cmp
task async_mem_cmp;
input [(dw-1):0] address;
input [(dw-1):0] data;
input [3:0] byte_lane_select;
begin
if( log_level > 2 )
$display( "###- async_mem_cmp: 0x%h @ 0x%h at time %t. ", data, address, $time );
@(posedge tb_clk);
mem_cs_n_r = 1'b0;
mem_we_n_r = 1'b1;
mem_oe_n_r = 1'b0;
tb_oe_r = 1'b0;
mem_a_r = address;
mem_bls_n_r = byte_lane_select;
repeat(ce_setup) @(posedge tb_clk);
if( ( mem_d !== data ) & (log_level > 0) )
$display( "!!!- Data compare error at time %t. Received %h, expected %h at address %h", $time, mem_d, data, address);
 
repeat(op_hold) @(posedge tb_clk);
async_mem_default_state();
 
mem_cs_n_r = 1'b1;
end
endtask
// --------------------------------------------------------------------
// async_mem_3x_cmp
task async_mem_3x_cmp;
input [(dw-1):0] address;
input [(dw-1):0] data1;
input [(dw-1):0] data2;
input [(dw-1):0] data3;
input [3:0] byte_lane_select;
begin
if( log_level > 2 )
$display( "###- async_mem_3x_cmp: @ 0x%h at time %t. ", address, $time );
@(posedge tb_clk);
mem_cs_n_r = 1'b0;
mem_we_n_r = 1'b1;
mem_oe_n_r = 1'b0;
tb_oe_r = 1'b0;
mem_a_r = address;
mem_bls_n_r = byte_lane_select;
repeat(ce_setup) @(posedge tb_clk);
if( ( mem_d !== data1 ) & (log_level > 0) )
$display( "!!!- Data compare error at time %t. Received %h, expected %h at address %h", $time, mem_d, data1, address);
 
repeat(op_hold) @(posedge tb_clk);
mem_a_r = address + 4;
repeat(ce_setup) @(posedge tb_clk);
if( ( mem_d !== data2 ) & (log_level > 0) )
$display( "!!!- Data compare error at time %t. Received %h, expected %h at address %h", $time, mem_d, data2, address + 4);
 
repeat(op_hold) @(posedge tb_clk);
mem_a_r = address + 8;
repeat(ce_setup) @(posedge tb_clk);
if( ( mem_d !== data3 ) & (log_level > 0) )
$display( "!!!- Data compare error at time %t. Received %h, expected %h at address %h", $time, mem_d, data3, address + 8);
 
repeat(op_hold) @(posedge tb_clk);
async_mem_default_state();
 
mem_cs_n_r = 1'b1;
end
endtask
// --------------------------------------------------------------------
// outputs
assign mem_d = tb_oe_r ? mem_d_r : 'bz;
assign mem_a = mem_a_r;
assign mem_oe_n = mem_oe_n_r;
assign mem_bls_n = mem_bls_n_r;
assign mem_we_n = mem_we_n_r;
assign mem_cs_n = mem_cs_n_r;
 
endmodule
 
 
/wb_async_mem_bridge/trunk/sw/scripts/lpc-l2294_test.txt
0,0 → 1,54
 
# enable cs3
iopoke -b 0xE002C014 -4 -v 0x0f814924
 
# configure BCFG3
iopoke -b 0xFFE0000C -4 -v 0x20007de7
iopeek -b 0xFFE0000C -4
 
 
# read & write to FPGA
 
iopoke -b 0x83000000 -4 -v 0xabbabeef
iopeek -b 0x83000000 -4
 
iopeek -b 0x83000000 -1
iopeek -b 0x83000001 -1
iopeek -b 0x83000002 -1
iopeek -b 0x83000003 -1
 
iopoke -b 0x83000000 -1 -v 0x01
iopoke -b 0x83000000 -1 -v 0x02
iopoke -b 0x83000000 -1 -v 0x04
iopoke -b 0x83000000 -1 -v 0x08
iopoke -b 0x83000000 -1 -v 0x10
iopoke -b 0x83000000 -1 -v 0x20
iopoke -b 0x83000000 -1 -v 0x40
iopoke -b 0x83000000 -1 -v 0x80
 
iopoke -b 0x83000001 -1 -v 0x01
 
iopoke -b 0x83000002 -1 -v 0x01
 
iopoke -b 0x83000003 -1 -v 0x01
 
iopoke -b 0x83000000 -1 -v 0x01
iopoke -b 0x83000001 -1 -v 0x02
iopoke -b 0x83000002 -1 -v 0x04
iopoke -b 0x83000003 -1 -v 0x08
iopoke -b 0x83000004 -1 -v 0x10
iopoke -b 0x83000005 -1 -v 0x20
iopoke -b 0x83000006 -1 -v 0x40
iopoke -b 0x83000007 -1 -v 0x80
 
iopoke -b 0x83000008 -4 -v 0xabbabeef
iopoke -b 0x8300000c -4 -v 0xffffffff
iopoke -b 0x83000010 -4 -v 0x00ffffff
iopoke -b 0x83000014 -4 -v 0xff00ffff
iopoke -b 0x83000018 -4 -v 0xffff00ff
iopoke -b 0x8300001c -4 -v 0xffffff00
 
dump -b 0x83000000 -4
 
iopeek -b 0x83000014 -4
 
/wb_async_mem_bridge/trunk/syn/debug/top.qpf
0,0 → 1,21
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
 
 
 
# Revisions
 
PROJECT_REVISION = "top"
/wb_async_mem_bridge/trunk/syn/debug/top.qsf
0,0 → 1,1174
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
# The default values for assignments are stored in the file
# DE1_TOP_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
 
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
 
 
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:25:28 APRIL 24, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_location_assignment PIN_A13 -to gpio_0[0]
set_location_assignment PIN_B13 -to gpio_0[1]
set_location_assignment PIN_A14 -to gpio_0[2]
set_location_assignment PIN_B14 -to gpio_0[3]
set_location_assignment PIN_A15 -to gpio_0[4]
set_location_assignment PIN_B15 -to gpio_0[5]
set_location_assignment PIN_A16 -to gpio_0[6]
set_location_assignment PIN_B16 -to gpio_0[7]
set_location_assignment PIN_A17 -to gpio_0[8]
set_location_assignment PIN_B17 -to gpio_0[9]
set_location_assignment PIN_A18 -to gpio_0[10]
set_location_assignment PIN_B18 -to gpio_0[11]
set_location_assignment PIN_A19 -to gpio_0[12]
set_location_assignment PIN_B19 -to gpio_0[13]
set_location_assignment PIN_A20 -to gpio_0[14]
set_location_assignment PIN_B20 -to gpio_0[15]
set_location_assignment PIN_C21 -to gpio_0[16]
set_location_assignment PIN_C22 -to gpio_0[17]
set_location_assignment PIN_D21 -to gpio_0[18]
set_location_assignment PIN_D22 -to gpio_0[19]
set_location_assignment PIN_E21 -to gpio_0[20]
set_location_assignment PIN_E22 -to gpio_0[21]
set_location_assignment PIN_F21 -to gpio_0[22]
set_location_assignment PIN_F22 -to gpio_0[23]
set_location_assignment PIN_G21 -to gpio_0[24]
set_location_assignment PIN_G22 -to gpio_0[25]
set_location_assignment PIN_J21 -to gpio_0[26]
set_location_assignment PIN_J22 -to gpio_0[27]
set_location_assignment PIN_K21 -to gpio_0[28]
set_location_assignment PIN_K22 -to gpio_0[29]
set_location_assignment PIN_J19 -to gpio_0[30]
set_location_assignment PIN_J20 -to gpio_0[31]
set_location_assignment PIN_J18 -to gpio_0[32]
set_location_assignment PIN_K20 -to gpio_0[33]
set_location_assignment PIN_L19 -to gpio_0[34]
set_location_assignment PIN_L18 -to gpio_0[35]
set_location_assignment PIN_H12 -to gpio_1[0]
set_location_assignment PIN_H13 -to gpio_1[1]
set_location_assignment PIN_H14 -to gpio_1[2]
set_location_assignment PIN_G15 -to gpio_1[3]
set_location_assignment PIN_E14 -to gpio_1[4]
set_location_assignment PIN_E15 -to gpio_1[5]
set_location_assignment PIN_F15 -to gpio_1[6]
set_location_assignment PIN_G16 -to gpio_1[7]
set_location_assignment PIN_F12 -to gpio_1[8]
set_location_assignment PIN_F13 -to gpio_1[9]
set_location_assignment PIN_C14 -to gpio_1[10]
set_location_assignment PIN_D14 -to gpio_1[11]
set_location_assignment PIN_D15 -to gpio_1[12]
set_location_assignment PIN_D16 -to gpio_1[13]
set_location_assignment PIN_C17 -to gpio_1[14]
set_location_assignment PIN_C18 -to gpio_1[15]
set_location_assignment PIN_C19 -to gpio_1[16]
set_location_assignment PIN_C20 -to gpio_1[17]
set_location_assignment PIN_D19 -to gpio_1[18]
set_location_assignment PIN_D20 -to gpio_1[19]
set_location_assignment PIN_E20 -to gpio_1[20]
set_location_assignment PIN_F20 -to gpio_1[21]
set_location_assignment PIN_E19 -to gpio_1[22]
set_location_assignment PIN_E18 -to gpio_1[23]
set_location_assignment PIN_G20 -to gpio_1[24]
set_location_assignment PIN_G18 -to gpio_1[25]
set_location_assignment PIN_G17 -to gpio_1[26]
set_location_assignment PIN_H17 -to gpio_1[27]
set_location_assignment PIN_J15 -to gpio_1[28]
set_location_assignment PIN_H18 -to gpio_1[29]
set_location_assignment PIN_N22 -to gpio_1[30]
set_location_assignment PIN_N21 -to gpio_1[31]
set_location_assignment PIN_P15 -to gpio_1[32]
set_location_assignment PIN_N15 -to gpio_1[33]
set_location_assignment PIN_P17 -to gpio_1[34]
set_location_assignment PIN_P18 -to gpio_1[35]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[0]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[1]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[2]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[3]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[4]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[5]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[6]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[7]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[8]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[9]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[10]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[11]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[12]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[13]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[14]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[15]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[16]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[17]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[18]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[19]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[20]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[21]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[22]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[23]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[24]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[25]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[26]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[27]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[28]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[29]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[30]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[31]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[32]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[33]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[34]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_0[35]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[0]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[1]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[2]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[3]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[4]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[5]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[6]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[7]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[8]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[9]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[10]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[11]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[12]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[13]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[14]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[15]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[16]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[17]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[18]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[19]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[20]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[21]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[22]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[23]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[24]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[25]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[26]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[27]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[28]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[29]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[30]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[31]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[32]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[33]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[34]
set_instance_assignment -name IO_STANDARD LVTTL -to gpio_1[35]
set_location_assignment PIN_L22 -to sw[0]
set_location_assignment PIN_L21 -to sw[1]
set_location_assignment PIN_M22 -to sw[2]
set_location_assignment PIN_V12 -to sw[3]
set_location_assignment PIN_W12 -to sw[4]
set_location_assignment PIN_U12 -to sw[5]
set_location_assignment PIN_U11 -to sw[6]
set_location_assignment PIN_M2 -to sw[7]
set_location_assignment PIN_M1 -to sw[8]
set_location_assignment PIN_L2 -to sw[9]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[0]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[1]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[2]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[3]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[4]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[5]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[6]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[7]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[8]
set_instance_assignment -name IO_STANDARD LVTTL -to sw[9]
set_location_assignment PIN_J2 -to hex0[0]
set_location_assignment PIN_J1 -to hex0[1]
set_location_assignment PIN_H2 -to hex0[2]
set_location_assignment PIN_H1 -to hex0[3]
set_location_assignment PIN_F2 -to hex0[4]
set_location_assignment PIN_F1 -to hex0[5]
set_location_assignment PIN_E2 -to hex0[6]
set_location_assignment PIN_E1 -to hex1[0]
set_location_assignment PIN_H6 -to hex1[1]
set_location_assignment PIN_H5 -to hex1[2]
set_location_assignment PIN_H4 -to hex1[3]
set_location_assignment PIN_G3 -to hex1[4]
set_location_assignment PIN_D2 -to hex1[5]
set_location_assignment PIN_D1 -to hex1[6]
set_location_assignment PIN_G5 -to hex2[0]
set_location_assignment PIN_G6 -to hex2[1]
set_location_assignment PIN_C2 -to hex2[2]
set_location_assignment PIN_C1 -to hex2[3]
set_location_assignment PIN_E3 -to hex2[4]
set_location_assignment PIN_E4 -to hex2[5]
set_location_assignment PIN_D3 -to hex2[6]
set_location_assignment PIN_F4 -to hex3[0]
set_location_assignment PIN_D5 -to hex3[1]
set_location_assignment PIN_D6 -to hex3[2]
set_location_assignment PIN_J4 -to hex3[3]
set_location_assignment PIN_L8 -to hex3[4]
set_location_assignment PIN_F3 -to hex3[5]
set_location_assignment PIN_D4 -to hex3[6]
set_instance_assignment -name IO_STANDARD LVTTL -to hex0[0]
set_instance_assignment -name IO_STANDARD LVTTL -to hex0[1]
set_instance_assignment -name IO_STANDARD LVTTL -to hex0[2]
set_instance_assignment -name IO_STANDARD LVTTL -to hex0[3]
set_instance_assignment -name IO_STANDARD LVTTL -to hex0[4]
set_instance_assignment -name IO_STANDARD LVTTL -to hex0[5]
set_instance_assignment -name IO_STANDARD LVTTL -to hex0[6]
set_instance_assignment -name IO_STANDARD LVTTL -to hex1[0]
set_instance_assignment -name IO_STANDARD LVTTL -to hex1[1]
set_instance_assignment -name IO_STANDARD LVTTL -to hex1[2]
set_instance_assignment -name IO_STANDARD LVTTL -to hex1[3]
set_instance_assignment -name IO_STANDARD LVTTL -to hex1[4]
set_instance_assignment -name IO_STANDARD LVTTL -to hex1[5]
set_instance_assignment -name IO_STANDARD LVTTL -to hex1[6]
set_instance_assignment -name IO_STANDARD LVTTL -to hex2[0]
set_instance_assignment -name IO_STANDARD LVTTL -to hex2[1]
set_instance_assignment -name IO_STANDARD LVTTL -to hex2[2]
set_instance_assignment -name IO_STANDARD LVTTL -to hex2[3]
set_instance_assignment -name IO_STANDARD LVTTL -to hex2[4]
set_instance_assignment -name IO_STANDARD LVTTL -to hex2[5]
set_instance_assignment -name IO_STANDARD LVTTL -to hex2[6]
set_instance_assignment -name IO_STANDARD LVTTL -to hex3[0]
set_instance_assignment -name IO_STANDARD LVTTL -to hex3[1]
set_instance_assignment -name IO_STANDARD LVTTL -to hex3[2]
set_instance_assignment -name IO_STANDARD LVTTL -to hex3[3]
set_instance_assignment -name IO_STANDARD LVTTL -to hex3[4]
set_instance_assignment -name IO_STANDARD LVTTL -to hex3[5]
set_instance_assignment -name IO_STANDARD LVTTL -to hex3[6]
set_location_assignment PIN_R22 -to key[0]
set_location_assignment PIN_R21 -to key[1]
set_location_assignment PIN_T22 -to key[2]
set_location_assignment PIN_T21 -to key[3]
set_location_assignment PIN_R20 -to ledr[0]
set_location_assignment PIN_R19 -to ledr[1]
set_location_assignment PIN_U19 -to ledr[2]
set_location_assignment PIN_Y19 -to ledr[3]
set_location_assignment PIN_T18 -to ledr[4]
set_location_assignment PIN_V19 -to ledr[5]
set_location_assignment PIN_Y18 -to ledr[6]
set_location_assignment PIN_U18 -to ledr[7]
set_location_assignment PIN_R18 -to ledr[8]
set_location_assignment PIN_R17 -to ledr[9]
set_location_assignment PIN_U22 -to ledg[0]
set_location_assignment PIN_U21 -to ledg[1]
set_location_assignment PIN_V22 -to ledg[2]
set_location_assignment PIN_V21 -to ledg[3]
set_location_assignment PIN_W22 -to ledg[4]
set_location_assignment PIN_W21 -to ledg[5]
set_location_assignment PIN_Y22 -to ledg[6]
set_location_assignment PIN_Y21 -to ledg[7]
set_instance_assignment -name IO_STANDARD LVTTL -to key[0]
set_instance_assignment -name IO_STANDARD LVTTL -to key[1]
set_instance_assignment -name IO_STANDARD LVTTL -to key[2]
set_instance_assignment -name IO_STANDARD LVTTL -to key[3]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[0]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[1]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[2]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[3]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[4]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[5]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[6]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[7]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[8]
set_instance_assignment -name IO_STANDARD LVTTL -to ledr[9]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[0]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[1]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[2]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[3]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[4]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[5]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[6]
set_instance_assignment -name IO_STANDARD LVTTL -to ledg[7]
set_location_assignment PIN_D12 -to clock_27[0]
set_location_assignment PIN_E12 -to clock_27[1]
set_location_assignment PIN_B12 -to clock_24[0]
set_location_assignment PIN_A12 -to clock_24[1]
set_location_assignment PIN_L1 -to clock_50
set_location_assignment PIN_M21 -to ext_clock
set_instance_assignment -name IO_STANDARD LVTTL -to clock_27[1]
set_instance_assignment -name IO_STANDARD LVTTL -to clock_24[0]
set_instance_assignment -name IO_STANDARD LVTTL -to clock_24[1]
set_instance_assignment -name IO_STANDARD LVTTL -to clock_50
set_instance_assignment -name IO_STANDARD LVTTL -to ext_clock
set_location_assignment PIN_H15 -to ps2_clk
set_location_assignment PIN_J14 -to ps2_dat
set_location_assignment PIN_F14 -to uart_rxd
set_location_assignment PIN_G12 -to uart_txd
set_instance_assignment -name IO_STANDARD LVTTL -to ps2_clk
set_instance_assignment -name IO_STANDARD LVTTL -to ps2_dat
set_instance_assignment -name IO_STANDARD LVTTL -to uart_rxd
set_instance_assignment -name IO_STANDARD LVTTL -to uart_txd
set_location_assignment PIN_E8 -to tdi
set_location_assignment PIN_D8 -to tcs
set_location_assignment PIN_C7 -to tck
set_location_assignment PIN_D7 -to tdo
set_instance_assignment -name IO_STANDARD LVTTL -to tdi
set_instance_assignment -name IO_STANDARD LVTTL -to tcs
set_instance_assignment -name IO_STANDARD LVTTL -to tck
set_instance_assignment -name IO_STANDARD LVTTL -to tdo
set_location_assignment PIN_D9 -to vga_r[0]
set_location_assignment PIN_C9 -to vga_r[1]
set_location_assignment PIN_A7 -to vga_r[2]
set_location_assignment PIN_B7 -to vga_r[3]
set_location_assignment PIN_B8 -to vga_g[0]
set_location_assignment PIN_C10 -to vga_g[1]
set_location_assignment PIN_B9 -to vga_g[2]
set_location_assignment PIN_A8 -to vga_g[3]
set_location_assignment PIN_A9 -to vga_b[0]
set_location_assignment PIN_D11 -to vga_b[1]
set_location_assignment PIN_A10 -to vga_b[2]
set_location_assignment PIN_B10 -to vga_b[3]
set_location_assignment PIN_A11 -to vga_hs
set_location_assignment PIN_B11 -to vga_vs
set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[0]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[1]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[2]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_r[3]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[0]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[1]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[2]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_g[3]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[0]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[1]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[2]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_b[3]
set_instance_assignment -name IO_STANDARD LVTTL -to vga_hs
set_instance_assignment -name IO_STANDARD LVTTL -to vga_vs
set_location_assignment PIN_A3 -to i2c_sclk
set_location_assignment PIN_B3 -to i2c_sdat
set_location_assignment PIN_A6 -to aud_adclrck
set_location_assignment PIN_B6 -to aud_adcdat
set_location_assignment PIN_A5 -to aud_daclrck
set_location_assignment PIN_B5 -to aud_dacdat
set_location_assignment PIN_B4 -to aud_xck
set_location_assignment PIN_A4 -to aud_bclk
set_instance_assignment -name IO_STANDARD LVTTL -to i2c_sclk
set_instance_assignment -name IO_STANDARD LVTTL -to i2c_sdat
set_instance_assignment -name IO_STANDARD LVTTL -to aud_adclrck
set_instance_assignment -name IO_STANDARD LVTTL -to aud_adcdat
set_instance_assignment -name IO_STANDARD LVTTL -to aud_daclrck
set_instance_assignment -name IO_STANDARD LVTTL -to aud_dacdat
set_instance_assignment -name IO_STANDARD LVTTL -to aud_xck
set_instance_assignment -name IO_STANDARD LVTTL -to aud_bclk
set_location_assignment PIN_W4 -to dram_addr[0]
set_location_assignment PIN_W5 -to dram_addr[1]
set_location_assignment PIN_Y3 -to dram_addr[2]
set_location_assignment PIN_Y4 -to dram_addr[3]
set_location_assignment PIN_R6 -to dram_addr[4]
set_location_assignment PIN_R5 -to dram_addr[5]
set_location_assignment PIN_P6 -to dram_addr[6]
set_location_assignment PIN_P5 -to dram_addr[7]
set_location_assignment PIN_P3 -to dram_addr[8]
set_location_assignment PIN_N4 -to dram_addr[9]
set_location_assignment PIN_W3 -to dram_addr[10]
set_location_assignment PIN_N6 -to dram_addr[11]
set_location_assignment PIN_U3 -to dram_ba_0
set_location_assignment PIN_V4 -to dram_ba_1
set_location_assignment PIN_T3 -to dram_cas_n
set_location_assignment PIN_N3 -to dram_cke
set_location_assignment PIN_U4 -to dram_clk
set_location_assignment PIN_T6 -to dram_cs_n
set_location_assignment PIN_U1 -to dram_dq[0]
set_location_assignment PIN_U2 -to dram_dq[1]
set_location_assignment PIN_V1 -to dram_dq[2]
set_location_assignment PIN_V2 -to dram_dq[3]
set_location_assignment PIN_W1 -to dram_dq[4]
set_location_assignment PIN_W2 -to dram_dq[5]
set_location_assignment PIN_Y1 -to dram_dq[6]
set_location_assignment PIN_Y2 -to dram_dq[7]
set_location_assignment PIN_N1 -to dram_dq[8]
set_location_assignment PIN_N2 -to dram_dq[9]
set_location_assignment PIN_P1 -to dram_dq[10]
set_location_assignment PIN_P2 -to dram_dq[11]
set_location_assignment PIN_R1 -to dram_dq[12]
set_location_assignment PIN_R2 -to dram_dq[13]
set_location_assignment PIN_T1 -to dram_dq[14]
set_location_assignment PIN_T2 -to dram_dq[15]
set_location_assignment PIN_R7 -to dram_ldqm
set_location_assignment PIN_T5 -to dram_ras_n
set_location_assignment PIN_M5 -to dram_udqm
set_location_assignment PIN_R8 -to dram_we_n
set_location_assignment PIN_AB20 -to fl_addr[0]
set_location_assignment PIN_AA14 -to fl_addr[1]
set_location_assignment PIN_Y16 -to fl_addr[2]
set_location_assignment PIN_R15 -to fl_addr[3]
set_location_assignment PIN_T15 -to fl_addr[4]
set_location_assignment PIN_U15 -to fl_addr[5]
set_location_assignment PIN_V15 -to fl_addr[6]
set_location_assignment PIN_W15 -to fl_addr[7]
set_location_assignment PIN_R14 -to fl_addr[8]
set_location_assignment PIN_Y13 -to fl_addr[9]
set_location_assignment PIN_R12 -to fl_addr[10]
set_location_assignment PIN_T12 -to fl_addr[11]
set_location_assignment PIN_AB14 -to fl_addr[12]
set_location_assignment PIN_AA13 -to fl_addr[13]
set_location_assignment PIN_AB13 -to fl_addr[14]
set_location_assignment PIN_AA12 -to fl_addr[15]
set_location_assignment PIN_AB12 -to fl_addr[16]
set_location_assignment PIN_AA20 -to fl_addr[17]
set_location_assignment PIN_U14 -to fl_addr[18]
set_location_assignment PIN_V14 -to fl_addr[19]
set_location_assignment PIN_U13 -to fl_addr[20]
set_location_assignment PIN_R13 -to fl_addr[21]
set_location_assignment PIN_AB16 -to fl_dq[0]
set_location_assignment PIN_AA16 -to fl_dq[1]
set_location_assignment PIN_AB17 -to fl_dq[2]
set_location_assignment PIN_AA17 -to fl_dq[3]
set_location_assignment PIN_AB18 -to fl_dq[4]
set_location_assignment PIN_AA18 -to fl_dq[5]
set_location_assignment PIN_AB19 -to fl_dq[6]
set_location_assignment PIN_AA19 -to fl_dq[7]
set_location_assignment PIN_AA15 -to fl_oe_n
set_location_assignment PIN_W14 -to fl_rst_n
set_location_assignment PIN_Y14 -to fl_we_n
set_location_assignment PIN_AA3 -to sram_addr[0]
set_location_assignment PIN_AB3 -to sram_addr[1]
set_location_assignment PIN_AA4 -to sram_addr[2]
set_location_assignment PIN_AB4 -to sram_addr[3]
set_location_assignment PIN_AA5 -to sram_addr[4]
set_location_assignment PIN_AB10 -to sram_addr[5]
set_location_assignment PIN_AA11 -to sram_addr[6]
set_location_assignment PIN_AB11 -to sram_addr[7]
set_location_assignment PIN_V11 -to sram_addr[8]
set_location_assignment PIN_W11 -to sram_addr[9]
set_location_assignment PIN_R11 -to sram_addr[10]
set_location_assignment PIN_T11 -to sram_addr[11]
set_location_assignment PIN_Y10 -to sram_addr[12]
set_location_assignment PIN_U10 -to sram_addr[13]
set_location_assignment PIN_R10 -to sram_addr[14]
set_location_assignment PIN_T7 -to sram_addr[15]
set_location_assignment PIN_Y6 -to sram_addr[16]
set_location_assignment PIN_Y5 -to sram_addr[17]
set_location_assignment PIN_AB5 -to sram_ce_n
set_location_assignment PIN_AA6 -to sram_dq[0]
set_location_assignment PIN_AB6 -to sram_dq[1]
set_location_assignment PIN_AA7 -to sram_dq[2]
set_location_assignment PIN_AB7 -to sram_dq[3]
set_location_assignment PIN_AA8 -to sram_dq[4]
set_location_assignment PIN_AB8 -to sram_dq[5]
set_location_assignment PIN_AA9 -to sram_dq[6]
set_location_assignment PIN_AB9 -to sram_dq[7]
set_location_assignment PIN_Y9 -to sram_dq[8]
set_location_assignment PIN_W9 -to sram_dq[9]
set_location_assignment PIN_V9 -to sram_dq[10]
set_location_assignment PIN_U9 -to sram_dq[11]
set_location_assignment PIN_R9 -to sram_dq[12]
set_location_assignment PIN_W8 -to sram_dq[13]
set_location_assignment PIN_V8 -to sram_dq[14]
set_location_assignment PIN_U8 -to sram_dq[15]
set_location_assignment PIN_Y7 -to sram_lb_n
set_location_assignment PIN_T8 -to sram_oe_n
set_location_assignment PIN_W7 -to sram_ub_n
set_location_assignment PIN_AA10 -to sram_we_n
set_location_assignment PIN_AB15 -to fl_ce_n
 
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
 
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
 
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VERILOG_FILE ../../src/test_harness.v
set_global_assignment -name VERILOG_FILE ../../src/soc_ram.v
set_global_assignment -name VERILOG_FILE ../../src/sync.v
set_global_assignment -name VERILOG_FILE ../../src/sync_edge_detect.v
set_global_assignment -name VERILOG_FILE ../../src/wb_async_mem_bridge.v
set_global_assignment -name VERILOG_FILE ../../src/top.v
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_clk_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[0] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[1] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[2] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[3] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[4] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[5] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[6] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[7] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[8] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[9] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[10] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[11] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[12] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[13] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[14] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[15] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[16] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[17] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[18] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[19] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[20] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[21] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[22] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[23] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[24] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[25] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[26] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[27] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[28] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[29] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[30] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[31] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[32] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[33] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[34] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[35] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[36] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[37] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[38] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[39] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[40] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[41] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[42] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[43] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[44] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[45] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[46] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[47] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[48] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[49] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[50] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[51] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[52] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[53] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[54] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[55] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[56] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[57] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[58] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[59] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[60] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[61] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[62] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[63] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[64] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[65] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[66] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[67] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[68] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[69] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[70] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_GAP_RECORD=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_MODE=TRANSITIONAL" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=2" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1,basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|rise" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|sync_out" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_we_n|sync_out" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|rise" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|sync_out" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_we_n|sync_out" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[71] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|rise" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[72] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|sync_out" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[73] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_we_n|sync_out" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[74] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[75] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[76] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[77] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[78] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[79] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[80] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[81] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[82] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[83] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[84] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[85] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[86] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[87] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[88] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[89] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[90] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[91] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[92] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[93] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[94] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[95] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[96] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[97] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[98] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[99] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[100] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[101] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[102] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[103] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[104] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[105] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[106] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[107] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[108] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[109] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[110] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[111] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[112] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[113] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[114] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[115] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[116] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[117] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[118] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[119] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[120] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[121] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[122] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[123] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[124] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[125] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[126] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[127] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[128] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[129] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[130] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[131] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[132] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[133] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[134] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[135] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[136] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[137] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[138] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[139] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[140] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[141] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[142] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[143] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[144] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[145] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[146] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[147] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[148] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[149] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[150] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[151] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[152] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[153] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[154] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[155] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[156] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[157] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[158] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[159] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[160] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[161] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[162] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[163] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[164] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[165] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[166] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[167] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[168] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[169] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[170] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[171] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[172] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[173] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[174] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[175] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[176] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[177] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[178] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[179] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[180] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[181] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[182] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[183] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[184] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[185] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[186] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[187] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[188] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[189] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[190] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[191] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[192] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[193] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[194] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[195] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[196] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[197] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[198] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[199] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[200] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[201] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[202] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[203] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[204] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[205] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[206] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[207] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[208] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[209] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[210] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[211] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[212] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[213] -to "test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=214" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=214" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=214" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=1520" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=215" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=47034" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=19066" -section_id auto_signaltap_0
/wb_async_mem_bridge/trunk/syn/debug/stp1.stp
0,0 → 1,2336
<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C15/20 (0x020B30DD)" sof_file="top.sof" top_level_entity="top">
<display_tree gui_logging_enabled="0">
<display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<global_info>
<single attribute="active instance" value="0"/>
<single attribute="lock mode" value="36110"/>
<multi attribute="window position" size="9" value="1144,766,398,124,0,50,124,0,0"/>
</global_info>
<instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="false" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
<position_info>
<single attribute="active tab" value="0"/>
<single attribute="data vertical scroll position" value="2"/>
<single attribute="data horizontal scroll position" value="0"/>
<single attribute="zoom level numerator" value="1"/>
<single attribute="zoom level denominator" value="1"/>
<single attribute="zoom offset numerator" value="130944"/>
<single attribute="zoom offset denominator" value="1"/>
<single attribute="data hierarchy root" value="3"/>
<single attribute="data hierarchy test_harness:i_test_harness" value="3"/>
<single attribute="data hierarchy wb_async_mem_bridge:i_wb_async_mem_bridge" value="1"/>
<single attribute="setup vertical scroll position" value="6"/>
<single attribute="setup horizontal scroll position" value="27"/>
</position_info>
<signal_set is_expanded="false" name="signal_set: 2009/10/14 13:53:16 #0">
<clock name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_clk_i" polarity="posedge" tap_mode="classic"/>
<config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" tap_mode="classic" type="register"/>
</trigger_input_vec>
<data_input_vec>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" tap_mode="classic" type="register"/>
</data_input_vec>
<storage_qualifier_input_vec>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" tap_mode="classic" type="register"/>
</storage_qualifier_input_vec>
</signal_vec>
<presentation>
<data_view>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o"/>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]"/>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]"/>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]"/>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]"/>
</bus>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]"/>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]"/>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]"/>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r" order="lsb_to_msb" radix="hex" state="collapse" type="register">
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r"/>
</data_view>
<setup_view>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r" order="lsb_to_msb" radix="hex" state="collapse" type="register">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r"/>
</setup_view>
</presentation>
<trigger CRC="9360E715" attribute_mem_mode="false" gap_record="true" is_expanded="false" name="trigger: 2009/10/14 13:53:16 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="transitional" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/>
<events use_custom_flow_control="no">
<level enabled="yes" name="condition1" type="basic">
<power_up enabled="yes">
</power_up>
<op_node/>
</level>
<level enabled="yes" name="condition2" type="basic">
<power_up enabled="yes">
</power_up>
<op_node/>
</level>
</events>
<storage_qualifier_events>
<transitional>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
<pwr_up_transitional>0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
</pwr_up_transitional>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
</storage_qualifier_events>
<log>
<data name="log: 2009/10/14 13:58:08 #0" power_up_mode="false" sample_depth="0" trigger_position="-1"></data>
<extradata></extradata>
</log>
</trigger>
</signal_set>
<signal_set global_temp="1" name="signal_set: 2009/10/14 15:50:23 #0">
<clock name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_clk_i" polarity="posedge" tap_mode="classic"/>
<config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|rise" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|sync_out" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_we_n|sync_out" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" tap_mode="classic" type="register"/>
</trigger_input_vec>
<data_input_vec>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|rise" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|sync_out" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_we_n|sync_out" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" tap_mode="classic" type="register"/>
</data_input_vec>
<storage_qualifier_input_vec>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|rise" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|sync_out" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_we_n|sync_out" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" tap_mode="classic" type="register"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" tap_mode="classic" type="combinatorial"/>
<wire name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r" tap_mode="classic" type="register"/>
</storage_qualifier_input_vec>
</signal_vec>
<presentation>
<data_view>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r" order="lsb_to_msb" radix="hex" state="collapse" type="register">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|sync_out"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_cs_n|rise"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|sync_edge_detect:i_sync_mem_we_n|sync_out"/>
</data_view>
<setup_view>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[31]"/>
</bus>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o"/>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o" order="lsb_to_msb" radix="hex" state="collapse" type="combinatorial">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r" order="lsb_to_msb" radix="hex" state="collapse" type="register">
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]"/>
<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]"/>
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</bus>
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<net is_signal_inverted="no" name="test_harness:i_test_harness|wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o_r"/>
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</setup_view>
</presentation>
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<log>
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<mnemonics/>
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