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https://opencores.org/ocsvn/wisbone_2_ahb/wisbone_2_ahb/trunk
Subversion Repositories wisbone_2_ahb
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/branches/toomuch/bench/ahbmas_wbslv_top_tb.v
0,0 → 1,318
//****************************************************************************************************** |
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd. |
|
|
//File name : ahbmas_wbslv_top_tb.v |
//Designer : Ravi S Gupta |
//Date : 23 May, 2007 |
//Description : Wishbone to AHB interface protocol converter Testbench |
//Revision : 1.0 |
|
|
//****************************************************************************************************** |
|
//DEFINES |
`define DEL 1 //Clock to output delay, zero time delays can cause problems |
//TOP MODULE |
module AHBMAS_WBSLV_TOP_tb ; |
//PARAMETERS |
parameter DWIDTH = 32 ; |
parameter AWIDTH = 32 ; |
parameter TON = 5 ; |
parameter TOFF = 5 ; |
|
integer address = 0; |
integer data = 0; |
//SIGNAL DECLARATIONS |
wire [1:0] htrans ; |
reg stb_i ; |
reg [DWIDTH-1:0] data_i ; |
wire hwrite ; |
reg [3:0] sel_i ; |
reg [DWIDTH-1:0] hrdata ; |
wire ack_o ; |
reg hready ; |
wire [DWIDTH-1:0] data_o ; |
wire [2:0] hburst ; |
wire [31:0] hwdata ; |
reg [1:0] hresp ; |
reg [AWIDTH-1:0] addr_i ; |
wire [AWIDTH-1:0] haddr ; |
wire [2:0] hsize ; |
reg we_i ; |
reg cyc_i ; |
reg clk_i ; |
reg rst_i ; |
reg hclk; |
reg hresetn; |
|
//MAIN CODE |
//Instantiate the DUT |
AHBMAS_WBSLV_TOP #( DWIDTH , AWIDTH ) |
DUT ( |
.htrans (htrans ) , |
.stb_i (stb_i ) , |
.data_i (data_i ) , |
.hwrite (hwrite ) , |
.sel_i (sel_i ) , |
.hrdata (hrdata ) , |
.ack_o (ack_o ) , |
.hready (hready ) , |
.data_o (data_o ) , |
.hburst (hburst ) , |
.hwdata (hwdata ) , |
.hresp (hresp ) , |
.addr_i (addr_i ) , |
.haddr (haddr ) , |
.hsize (hsize ) , |
.we_i (we_i ) , |
.cyc_i (cyc_i ) , |
.clk_i (clk_i), |
.rst_i (rst_i), |
.hclk (hclk), |
.hresetn(hresetn)); |
|
// Clock Generation |
always begin |
#TOFF //clk generation with OFF timeperiod = 5 |
clk_i = 'b0; |
#TON //clk generation with ON timeperiod = 5 |
clk_i = 'b1; |
end |
// local memory in AHB slave model |
reg [DWIDTH-1 : 0] ahb_mem [AWIDTH-1 : 0]; |
reg [AWIDTH-1:0] haddr_temp; |
reg [DWIDTH-1 :0] hrdata_temp; |
reg hwrite_temp; |
|
// always@(posedge clk_i) |
// hrdata <= hrdata_temp; |
//************************************************* |
// AHB slave model |
//************************************************* |
|
always @(posedge clk_i) begin |
if (hready) begin |
haddr_temp <= #2 haddr; |
hwrite_temp<=#2 hwrite; |
if (hwrite_temp) begin |
ahb_mem[haddr_temp] <= #2 hwdata; // data stored in ahb slave |
end |
else if (!hwrite) begin |
hrdata <= #2 ahb_mem[haddr]; |
end |
end |
end |
|
//***************************************** |
//Write operations with no wait states |
//***************************************** |
task write_data; |
|
input [AWIDTH-1:0] addr; |
input [DWIDTH-1:0] Data; |
begin |
#2 |
cyc_i=1'b1; |
stb_i=1'b1; |
we_i=1'b1; |
//if(ack_o) begin |
addr_i <= addr; |
data_i <= Data;//Send Data |
//end |
hready <= 'b1; |
end |
endtask |
//************************************************ |
//Write operations with wait states from AHB Slave |
//************************************************ |
task write_data_WSAHB; |
begin |
@(posedge clk_i) begin |
#2 cyc_i = 1'b1; |
stb_i = 1'b1; |
we_i = 1'b1; |
hready = 1'b0; //AHB Master is in Wait State |
end |
end |
|
endtask |
|
//*********************************************** |
//Write operations with wait states from WB Master |
//*********************************************** |
task write_data_WSWB; |
begin |
@(posedge clk_i) begin |
#2 cyc_i = 1'b1; |
stb_i = 1'b0;//WB Master is in Wait State |
we_i = 1'b1; |
hready = 1'b1; |
end |
end |
|
endtask |
|
//************************************* |
//Read operations without wait states |
//************************************* |
task read_data; |
input [31:0] addr; |
begin #2 |
cyc_i=1'b1; |
stb_i=1'b1; |
we_i=1'b0; |
if (ack_o) begin |
addr_i = addr; |
end |
// else begin |
// hrdata_temp = ahb_mem[haddr]; |
// end |
hready = 1'b1; |
end |
endtask |
//********************************************** |
//Read operations with wait states from AHB Slave |
//********************************************** |
task read_data_WSAHB; |
begin |
@(posedge clk_i) begin |
#2 cyc_i = 1'b1; |
stb_i = 1'b1; |
we_i = 1'b0; |
hready = 1'b0; //AHB Master is in Wait State |
end |
end |
endtask |
|
//********************************************** |
//Read operations with wait states from WB Master |
//********************************************** |
task read_data_WSWB; |
begin |
@(posedge clk_i) begin |
#2 cyc_i = 1'b1; |
stb_i = 1'b0; //WB Master in in Wait state |
we_i = 1'b0; |
hready = 1'b1; |
end |
end |
endtask |
|
|
|
// Initialize Inputs |
initial |
begin |
clk_i=1'b0; |
|
rst_i = 'b0; |
#2 |
rst_i = 'b1; |
#23 |
rst_i = 'b0; // reset for more than one clock cycle |
|
hready = 1'b1; |
hresp = 2'b00; |
# 20 cyc_i='b0; |
stb_i='b0; |
sel_i=4'b0000; |
|
|
//************************************* |
//Block Write cycle |
//************************************* |
repeat(7) begin |
address = address + 1; |
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n]) |
data = data +1; |
end |
//************************************* |
//Write cycle with wait states from AHB Slave |
//************************************* |
// #10; |
repeat(2) |
write_data_WSAHB; |
//************************************* |
//Block Write cycle |
//************************************* |
// #10; |
repeat(4) begin |
address = address + 1; |
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n]) |
data = data +1; |
end |
//************************************* |
//Write cycle with wait states from WB Master |
//************************************* |
// #10; |
repeat(2) |
write_data_WSWB; |
|
//************************************* |
//Block Write cycle |
//************************************* |
// #10; |
repeat(4) begin |
address = address + 1; |
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n]) |
data = data +1; |
end |
|
//************************************* |
//Block Read cycle |
//************************************* |
// #10; |
repeat(6) begin |
@(posedge clk_i) read_data(address); |
address = address -1; |
end |
|
//************************************* |
//Read cycle with Wait State from AHB Slave |
//************************************* |
// #10; |
repeat(2) |
read_data_WSAHB; |
|
//************************************* |
//Block Read cycle |
//************************************* |
// #10; |
repeat(4) begin |
@(posedge clk_i) read_data(address); |
address = address -1; |
end |
|
//************************************* |
//Read cycle with Wait State from WB Master |
//************************************* |
// #10; |
repeat(2) |
read_data_WSWB; |
//************************************* |
//Block Read cycle |
//************************************* |
// #10; |
repeat(5) begin |
address = address + 1; |
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n]) |
data = data +1; |
end |
|
//************************************* |
//Block Write cycle |
//************************************* |
repeat(4) begin |
address = address + 1; |
@(posedge clk_i) write_data(address, data); // format : write_data(A[n+1], d[n]) |
data = data +1; |
end |
|
#20 stb_i='b0; |
#5 cyc_i='b0; |
|
#200 $stop; |
end |
|
endmodule |
branches/toomuch/bench/ahbmas_wbslv_top_tb.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: branches/toomuch/script/modelsim.ini
===================================================================
--- branches/toomuch/script/modelsim.ini (nonexistent)
+++ branches/toomuch/script/modelsim.ini (revision 2)
@@ -0,0 +1,790 @@
+; Copyright 2006 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+ahb_wb = ../ahb_wb
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile=1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0in tools from within the simulator.
+; Default value set to 0. Please set it to 1 to invoke 0in.
+; VcomZeroIn = 1
+
+; Set the options to be passed to the 0in tools.
+; Default value set to "". Please set it to appropriate options needed.
+; VcomZeroInOptions = ""
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageNoSub = 0
+
+; Automatically exclude VHDL case statement default branches.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Turn on code coverage in VHDL generate blocks. Default is off.
+; CoverGenerate = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+vlog95compat = 0
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code.
+; The default is 0 (i.e. no memory is automatically given sparse status)
+; SparseMemThreshold = 1048576
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Run the 0in tools from within the simulator.
+; Default value set to 0. Please set it to 1 to invoke 0in.
+; VlogZeroIn = 1
+
+; Set the options to be passed to the 0in tools.
+; Default value set to "". Please set it to appropriate options needed.
+; VlogZeroInOptions = ""
+
+; Run the 0in tools from within the simulator.
+; Default value set to 0. Please set it to 1 to invoke 0in.
+; VoptZeroIn = 1
+
+; Set the options to be passed to the 0in tools.
+; Default value set to "". Please set it to appropriate options needed.
+; VoptZeroInOptions = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Turn on code coverage in VLOG generate blocks. Default is off.
+; CoverGenerate = 1
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => _
+; SVCoverpointExprVariablePrefix = expr
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vsim]
+
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 0
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL/Verilog immediate assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use AssertionFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use AssertionFormatBreak;
+; - otherwise, use AssertionFormat.
+; AssertionFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable System Verilog assertion messages
+; Info and Warning are disabled by default
+; IgnoreSVAInfo = 0
+; IgnoreSVAWarning = 0
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify whether to enable SystemVerilog DPI out-of-the-blue call.
+; Out-of-the-blue call refers to a SystemVerilog export function call
+; directly from a C function that don't have the proper context setup
+; as done in DPI-C import C functions. When this is enabled, one can
+; call a DPI export function (but not task) from any C code.
+; The default is 0 (disabled).
+; DpiOutOfTheBlue = 1
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
+; This is necessary when C++ files have been compiled with aCC's -AA option.
+; The default behavior is to use /usr/lib/libCsup.sl.
+; UseCsupV2 = 1
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; WLF reader cache size limit. Specifies the internal WLF file cache size,
+; in megabytes, for EACH open WLF file. A value of 0 turns off the
+; WLF cache.
+; The default setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 1000
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+
+; Do not exit when executing sc_stop().
+; If this is enabled, the control will be returned to the user before exiting
+; the simulation. This can make some cleanup tasks easier before kernel exits.
+; The default is off.
+; NoExitOnScStop = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA concurrent assertion pass enable. Default is on.
+; AssertionPassEnable = 0
+
+; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL/SVA concurrent assertion pass limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = 1
+
+; Set PSL/SVA concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off.
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default value set to 0. Please set it to 1 to invoke 0in.
+; VsimZeroIn = 1
+
+; Set the options to be passed to the 0in tools.
+; Default value set to "". Please set it to appropriate options needed.
+; VsimZeroInOptions = ""
+
+; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
+; Sv_Seed = 0
+
+; Maximum size of dynamic arrays that are resized during randomize().
+; The default is 1000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 1000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; The default is 0 (no error).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures (SystemVerilog).
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; When SolveFailDebug is enabled, this value specifies the maximum number of
+; constraint subsets that will be tested for conflicts.
+; The default is 0 (no limit).
+; SolveFailDebugLimit = 0
+
+; When SolveFailDebug is eanbled, this value specifies the maximum size of
+; constraint subsets that will be tested for conflicts.
+; The default value is 0 (no limit).
+; SolveFailDebugMaxSet = 0
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; Note: To achieve the same random sequences, solver optimizations and/or
+; bug fixes introduced since the specified release may be disabled -
+; yielding the performance / behavior of the prior release.
+; Default value set to "" (random compatibility not required).
+; SolveRev = ""
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Retroactive Recording uses a limited number of private data channels in the WLF
+; file. Too many channels degrade WLF performance. If the limit is reached,
+; simulation ends with a fatal error. You may change this limit as needed, but be
+; aware of the implications of too many channels. The value must be an integer
+; greater than or equal to zero, where zero disables all retroactive recording.
+; RetroChannelLimit = 20
+
+; Options to give vopt when code coverage is turned on.
+; Default is "+acc=lprnb -opt=-merge -opt=-suppressAlways"
+; VoptCoverageOptions = +acc=lprnb -opt=-merge -opt=-suppressAlways
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = /lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = /lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = /lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = /lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = /lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: = [,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; The command verror can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer). The other settings
+; are to send messages only to the transcript or only to the
+; wlf file. The valid values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
branches/toomuch/script/modelsim.ini
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+++ branches/toomuch/script/run.mti (revision 2)
@@ -0,0 +1,24 @@
+
+#!/bin/bash
+
+ahb_wb=../ #project directory
+src=$ahb_wb/src #source code directory
+bench=$ahb_wb/bench #test bench directory
+
+
+vlog \
+ -work ahb_wb \
+ +incldir+$src \
+ $src/ahbmas_wbslv_top.v
+
+vlog \
+ -work ahb_wb \
+ +incldir+$bench \
+ $bench/AHBMAS_WBSLV_TOP_tb.v
+
+
+vsim -c ahb_wb.AHBMAS_WBSLV_TOP_tb -do " log -r /* ; run -all; quit -f " 2>&1 | tee transcript.log
+echo "Converting to VCD format..........."
+wlf2vcd vsim.wlf > vsim.vcd
+gtkwave vsim.vcd &
+
branches/toomuch/script/run.mti
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branches/toomuch/doc/wb_ahb_doc.pdf
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+
+ $.' ",#(7),01444'9=82<.342 C
+
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