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/trunk/rtl/vhdl/reg_pc.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:48:44 17.04.2008
-- at - 22:53:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
17,13 → 17,12
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_pc_as_i : in std_logic;
sel_pc_in_i : in std_logic;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0);
cout_pc_o : out std_logic
adr_pc_o : out std_logic_vector (15 downto 0)
);
 
-- Declarations
44,16 → 43,17
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Program Counter Logic
-- Path: R6502_TC/Reg_PC/struct
-- Edited: by eda on 17 Apr 2008
-- Edited: by eda on 01 Jan 2009
--
-- VHDL Architecture R6502_TC.Reg_PC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:48:44 17.04.2008
-- at - 22:53:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
67,24 → 67,35
-- Architecture declarations
 
-- Internal signal declarations
signal d : std_logic_vector(7 downto 0);
signal d1 : std_logic_vector(7 downto 0);
signal dout : std_logic;
signal dout1 : std_logic_vector(7 downto 0);
signal dout3 : std_logic;
signal dout5 : std_logic_vector(7 downto 0);
signal dout6 : std_logic_vector(7 downto 0);
signal load : std_logic;
signal load3 : std_logic;
signal val_one : std_logic_vector(7 downto 0);
signal val_two : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
signal adr_pc_low_o_i : std_logic_vector(7 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal as_n_o_i : std_logic;
signal ci_o_i : std_logic;
signal cout_pc_o_i : std_logic;
signal load3_o_i : std_logic;
signal load_o_i : std_logic;
signal offset_high_o_i : std_logic_vector(7 downto 0);
signal offset_low_o_i : std_logic_vector(7 downto 0);
signal val_o_i : std_logic_vector(7 downto 0);
signal val_one : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
 
-- Implicit buffer signal declarations
signal adr_pc_o_internal : std_logic_vector (15 downto 0);
signal cout_pc_o_internal : std_logic;
signal adr_pc_o_internal : std_logic_vector (15 downto 0);
signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_12' of 'addsub'
signal mw_U_12temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_12temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_12sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
 
93,71 → 104,47
 
 
begin
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
adr_nxt_pc_o(7 DOWNTO 0) <= d;
 
-- HDL Embedded Text Block 2 eb2
-- eb1 1
val_zero (7 downto 0) <= X"00";
val_one (7 downto 0) <= X"01";
val_two (7 downto 0) <= X"02";
 
-- HDL Embedded Text Block 3 eb3
-- eb1 1
adr_nxt_pc_o(15 DOWNTO 8) <= d1;
 
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
u_11combo_proc: process (dout5, dout1, dout3, val_zero(0))
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
mw_U_11temp_din0 <= '0' & adr_pc_low_o_i;
mw_U_11temp_din1 <= '0' & val_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, as_n_o_i)
variable temp_carry : std_logic;
variable temp_cout : std_logic;
begin
temp_din0 := '0' & dout5;
temp_din1 := '0' & dout1;
temp_carry := val_zero(0);
if (dout3 = '1') then
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
temp_cout := temp_sum(8) ;
temp_carry := '0';
if (as_n_o_i = '1') then
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
else
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
temp_cout := temp_sum(8) ;
mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
end if;
d <= conv_std_logic_vector(temp_sum(7 downto 0),8);
cout_pc_o_internal <= temp_cout;
end process u_11combo_proc;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
cout_pc_o_i <= mw_U_11sum(8);
 
-- ModuleWare code(v1.9) for instance 'U_12' of 'addsub'
u_12combo_proc: process (dout6, offset_i(15 DOWNTO 8), dout3, dout)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
mw_U_12temp_din0 <= '0' & adr_pc_high_o_i;
mw_U_12temp_din1 <= '0' & offset_high_o_i;
u_12combo_proc: process (mw_U_12temp_din0, mw_U_12temp_din1, as_n_o_i, ci_o_i)
variable temp_carry : std_logic;
begin
temp_din0 := '0' & dout6;
temp_din1 := '0' & offset_i(15 DOWNTO 8);
temp_carry := dout;
if (dout3 = '1') then
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
temp_carry := ci_o_i;
if (as_n_o_i = '1') then
mw_U_12sum <= unsigned(mw_U_12temp_din0) + unsigned(mw_U_12temp_din1) + temp_carry;
else
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
mw_U_12sum <= unsigned(mw_U_12temp_din0) - unsigned(mw_U_12temp_din1) - temp_carry;
end if;
d1 <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_12combo_proc;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(mw_U_12sum(7 downto 0),8);
 
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_i)
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_i = '1') then
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load = '1') then
mw_U_0reg_cval <= d;
if (load_o_i = '1') then
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
end if;
end if;
end process u_0seq_proc;
164,68 → 151,70
 
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_i)
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_i = '1') then
if (rst_rst_n_i = '0') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load3 = '1') then
mw_U_4reg_cval <= d1;
if (load3_o_i = '1') then
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
end if;
end if;
end process u_4seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load <= ld_pc_i and ld_i(0);
load_o_i <= ld_pc_i and ld_i(0);
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load3 <= ld_pc_i and ld_i(1);
load3_o_i <= ld_pc_i and ld_i(1);
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
dout <= cout_pc_o_internal and ld_pc_i;
ci_o_i <= cout_pc_o_i and ld_pc_i;
 
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
val_zero <= "00000000";
 
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
val_one <= "00000001";
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
dout3 <= not(sel_pc_as_i);
as_n_o_i <= not(sel_pc_as_i);
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'mux'
u_5combo_proc: process(val_one, val_two, offset_i(7 DOWNTO 0),
val_zero, sel_pc_val_i)
begin
case sel_pc_val_i is
when "00" => dout1 <= val_one;
when "01" => dout1 <= val_two;
when "10" => dout1 <= offset_i(7 DOWNTO 0);
when "11" => dout1 <= val_zero;
when others => dout1 <= (others => 'X');
end case;
end process u_5combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: process(adr_pc_o_internal(7 DOWNTO 0),
adr_i(7 DOWNTO 0), sel_pc_in_i)
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
begin
case sel_pc_in_i is
when '0' => dout5 <= adr_pc_o_internal(7 DOWNTO 0);
when '1' => dout5 <= adr_i(7 DOWNTO 0);
when others => dout5 <= (others => 'X');
when '0' => adr_pc_o_i <= adr_pc_o_internal;
when '1' => adr_pc_o_i <= adr_i;
when others => adr_pc_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_9' of 'mux'
u_9combo_proc: process(adr_pc_o_internal(15 DOWNTO 8),
adr_i(15 DOWNTO 8), sel_pc_in_i)
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
sel_pc_val_i)
begin
case sel_pc_in_i is
when '0' => dout6 <= adr_pc_o_internal(15 DOWNTO 8);
when '1' => dout6 <= adr_i(15 DOWNTO 8);
when others => dout6 <= (others => 'X');
case sel_pc_val_i is
when "00" => val_o_i <= val_one;
when "01" => val_o_i <= val_zero;
when "10" => val_o_i <= offset_low_o_i;
when "11" => val_o_i <= val_zero;
when others => val_o_i <= (others => 'X');
end case;
end process u_9combo_proc;
end process u_13combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
adr_pc_low_o_i <= adr_pc_o_i(7 downto 0);
adr_pc_high_o_i <= adr_pc_o_i(15 downto 8);
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
offset_low_o_i <= offset_i(7 downto 0);
offset_high_o_i <= offset_i(15 downto 8);
 
-- Instance port mappings.
 
-- Implicit buffered output assignments
adr_pc_o <= adr_pc_o_internal;
cout_pc_o <= cout_pc_o_internal;
adr_pc_o <= adr_pc_o_internal;
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
 
end struct;
/trunk/rtl/vhdl/reg_sp.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:48:44 17.04.2008
-- at - 22:53:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
12,16 → 12,14
 
entity Reg_SP is
port(
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
ld_i : in std_logic_vector (1 downto 0);
ld_sp_i : in std_logic;
rst_rst_i : in std_logic;
sel_sp_as_i : in std_logic;
sel_sp_in_i : in std_logic;
sel_sp_val_i : in std_logic;
adr_nxt_sp_o : out std_logic_vector (15 downto 0);
adr_sp_o : out std_logic_vector (15 downto 0)
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic;
ld_low_i : in std_logic;
ld_sp_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_sp_as_i : in std_logic;
sel_sp_in_i : in std_logic;
adr_sp_o : out std_logic_vector (15 downto 0)
);
 
-- Declarations
42,16 → 40,17
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Stack Pointer Logic
-- Path: R6502_TC/Reg_SP/struct
-- Edited: by eda on 17 Apr 2008
-- Edited: by eda on 01 Jan 2009
--
-- VHDL Architecture R6502_TC.Reg_SP.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:48:45 17.04.2008
-- at - 22:53:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
65,114 → 64,81
-- Architecture declarations
 
-- Internal signal declarations
signal d : std_logic_vector(7 downto 0);
signal dout1 : std_logic_vector(7 downto 0);
signal dout2 : std_logic_vector(7 downto 0);
signal dout3 : std_logic;
signal load : std_logic;
signal load3 : std_logic;
signal val_one : std_logic_vector(7 downto 0);
signal val_two : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
signal adr_sp_low_o_i : std_logic_vector(7 downto 0);
signal load_o_i : std_logic;
signal result_low1_o_i : std_logic_vector(7 downto 0);
signal result_low_o_i : std_logic_vector(7 downto 0);
signal sp_as_n_o_i : std_logic;
signal val_one : std_logic_vector(7 downto 0);
 
-- Implicit buffer signal declarations
signal adr_sp_o_internal : std_logic_vector (15 downto 0);
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
 
 
begin
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
-- eb1 1
val_zero (7 downto 0) <= X"00";
val_one (7 downto 0) <= X"01";
val_two (7 downto 0) <= X"02";
adr_nxt_sp_o (15 downto 8) <= X"01";
 
-- HDL Embedded Text Block 3 eb3
-- eb1 1
adr_nxt_sp_o (7 DOWNTO 0) <= d;
 
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
u_11combo_proc: process (adr_sp_o_internal(7 DOWNTO 0), dout1, dout3, val_zero(0))
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
mw_U_11temp_din0 <= '0' & adr_sp_low_o_i;
mw_U_11temp_din1 <= '0' & val_one;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, sp_as_n_o_i)
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_sp_o_internal(7 DOWNTO 0);
temp_din1 := '0' & dout1;
temp_carry := val_zero(0);
if (dout3 = '1') then
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
temp_carry := '0';
if (sp_as_n_o_i = '1') then
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
else
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
end if;
dout2 <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_11combo_proc;
result_low_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
 
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_i)
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_i = '1') then
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load = '1') then
mw_U_0reg_cval <= d;
if (load_o_i = '1') then
mw_U_0reg_cval <= result_low1_o_i;
end if;
end if;
end process u_0seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
adr_sp_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_i)
begin
if (rst_rst_i = '1') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load3 = '1') then
mw_U_4reg_cval <= val_one;
end if;
end if;
end process u_4seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load <= ld_sp_i and ld_i(0);
load_o_i <= ld_sp_i and ld_low_i;
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load3 <= ld_sp_i and ld_i(1);
-- ModuleWare code(v1.9) for instance 'U_3' of 'buff'
adr_sp_o_internal(15 DOWNTO 8) <= val_one;
 
-- ModuleWare code(v1.9) for instance 'U_4' of 'constval'
val_one <= "00000001";
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
dout3 <= not(sel_sp_as_i);
sp_as_n_o_i <= not(sel_sp_as_i);
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'mux'
u_5combo_proc: process(val_one, val_two, sel_sp_val_i)
begin
case sel_sp_val_i is
when '0' => dout1 <= val_one;
when '1' => dout1 <= val_two;
when others => dout1 <= (others => 'X');
end case;
end process u_5combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: process(dout2, adr_i(7 DOWNTO 0), sel_sp_in_i)
u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
begin
case sel_sp_in_i is
when '0' => d <= dout2;
when '1' => d <= adr_i(7 DOWNTO 0);
when others => d <= (others => 'X');
when '0' => result_low1_o_i <= result_low_o_i;
when '1' => result_low1_o_i <= adr_low_i;
when others => result_low1_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'tap'
adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
 
-- Instance port mappings.
 
-- Implicit buffered output assignments
/trunk/rtl/vhdl/r6502_tc.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:49:04 17.04.2008
-- at - 22:53:22 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
45,16 → 45,17
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- Title: Top Level for the 6502 Core
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Top Level
-- Path: R6502_TC/R6502_TC/struct
-- Edited: by eda on 17 Apr 2008
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:49:04 17.04.2008
-- at - 22:53:22 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
/trunk/rtl/vhdl/fsm_execution_unit.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:53 04.01.2009
-- at - 22:53:07 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
103,7 → 103,7
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:55 04.01.2009
-- at - 22:53:08 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
/trunk/rtl/vhdl/core.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:49:03 17.04.2008
-- at - 22:53:21 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
45,16 → 45,17
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- Title: Core of 6502
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Core
-- Path: R6502_TC/Core/struct
-- Edited: by eda on 17 Apr 2008
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:49:03 17.04.2008
-- at - 22:53:22 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
69,72 → 70,108
-- Architecture declarations
 
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_nxt_sp_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal cout_pc_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal fetch_o_i : std_logic;
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_core_o_i : std_logic;
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_3flag_core_o_i : std_logic;
signal reg_6flag_o_i : std_logic;
signal reg_7flag_core_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal rst_rst_int_o_i : std_logic;
signal sel_alu_as_o_i : std_logic;
signal sel_alu_out_o_i : std_logic_vector(2 downto 0);
signal sel_pc_as_o_i : std_logic;
signal sel_pc_in_o_i : std_logic_vector(1 downto 0);
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(2 downto 0);
signal sel_rb_out_o_i : std_logic_vector(2 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic_vector(1 downto 0);
signal sel_sp_val_o_i : std_logic_vector(1 downto 0);
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal fetch_o_i : std_logic;
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal sel_pc_as_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- Component Declarations
component ALU
component FSM_Execution_Unit
port (
ch_a_i : in std_logic_vector (7 downto 0);
ch_b_i : in std_logic_vector (7 downto 0);
reg_0flag_core_i : in std_logic ;
reg_3flag_core_i : in std_logic ;
reg_7flag_core_i : in std_logic ;
sel_alu_as_i : in std_logic ;
sel_alu_out_i : in std_logic_vector (2 downto 0);
d_alu_o : out std_logic_vector (7 downto 0);
reg_0flag_o : out std_logic ;
reg_1flag_o : out std_logic ;
reg_6flag_o : out std_logic ;
reg_7flag_o : out std_logic
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
sel_pc_as_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
component FSM_NMI
port (
clk_clk_i : in std_logic ;
fetch_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
);
end component;
component RegBank_AXY
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (2 downto 0);
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
150,135 → 187,125
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_pc_as_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0);
cout_pc_o : out std_logic
adr_pc_o : out std_logic_vector (15 downto 0)
);
end component;
component Reg_SP
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_sp_i : in std_logic ;
rst_rst_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
sel_sp_val_i : in std_logic ;
adr_nxt_sp_o : out std_logic_vector (15 downto 0);
adr_sp_o : out std_logic_vector (15 downto 0)
);
end component;
component fsm_core_V2_0
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_nxt_sp_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
cout_pc_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_6flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
reg_0flag_o : out std_logic ;
reg_1flag_o : out std_logic ;
reg_3flag_o : out std_logic ;
reg_7flag_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic ;
sel_alu_as_o_i : inout std_logic ;
sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 );
sel_pc_as_o_i : inout std_logic ;
sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 );
sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 );
sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 );
sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 );
sel_reg_o_i : inout std_logic_vector ( 1 downto 0 );
sel_sp_as_o_i : inout std_logic ;
sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 );
sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 )
);
end component;
component fsm_nmi
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
fetch_i : in std_logic ;
nmi_n_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
);
end component;
 
-- Optional embedded configurations
-- pragma synthesis_off
for all : ALU use entity R6502_TC.ALU;
for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit;
for all : FSM_NMI use entity R6502_TC.FSM_NMI;
for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
for all : Reg_PC use entity R6502_TC.Reg_PC;
for all : Reg_SP use entity R6502_TC.Reg_SP;
for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0;
for all : fsm_nmi use entity R6502_TC.fsm_nmi;
-- pragma synthesis_on
 
 
begin
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'inv'
rst_rst_int_o_i <= not(rst_rst_n_i);
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
mw_U_11temp_din0 <= '0' & ch_a_o_i;
mw_U_11temp_din1 <= '0' & ch_b_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1)
variable temp_carry : std_logic;
begin
temp_carry := '0';
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
end process u_11combo_proc;
d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
reg_0flag_o_i <= mw_U_11sum(8) ;
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
 
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
 
-- Instance port mappings.
U_3 : ALU
U_4 : FSM_Execution_Unit
port map (
ch_a_i => ch_a_o_i,
ch_b_i => ch_b_o_i,
reg_0flag_core_i => reg_0flag_core_o_i,
reg_3flag_core_i => reg_3flag_core_o_i,
reg_7flag_core_i => reg_7flag_core_o_i,
sel_alu_as_i => sel_alu_as_o_i,
sel_alu_out_i => sel_alu_out_o_i,
d_alu_o => d_alu_o_i,
reg_0flag_o => reg_0flag_o_i,
reg_1flag_o => reg_1flag_o_i,
reg_6flag_o => reg_6flag_o_i,
reg_7flag_o => reg_7flag_o_i
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
fetch_o => fetch_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
sel_pc_as_o => sel_pc_as_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_6 : FSM_NMI
port map (
clk_clk_i => clk_clk_i,
fetch_i => fetch_o_i,
nmi_n_i => nmi_n_i,
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
);
U_2 : RegBank_AXY
port map (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_i => rst_rst_int_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i(1 DOWNTO 0),
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
292,89 → 319,23
ld_i => ld_o_i,
ld_pc_i => ld_pc_o_i,
offset_i => offset_o_i,
rst_rst_i => rst_rst_int_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_pc_as_i => sel_pc_as_o_i,
sel_pc_in_i => sel_pc_in_o_i(0),
sel_pc_in_i => sel_pc_in_o_i,
sel_pc_val_i => sel_pc_val_o_i,
adr_nxt_pc_o => adr_nxt_pc_o_i,
adr_pc_o => adr_pc_o_i,
cout_pc_o => cout_pc_o_i
adr_pc_o => adr_pc_o_i
);
U_1 : Reg_SP
port map (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
ld_sp_i => ld_sp_o_i,
rst_rst_i => rst_rst_int_o_i,
sel_sp_as_i => sel_sp_as_o_i,
sel_sp_in_i => sel_sp_in_o_i(0),
sel_sp_val_i => sel_sp_val_o_i(0),
adr_nxt_sp_o => adr_nxt_sp_o_i,
adr_sp_o => adr_sp_o_i
);
U_4 : fsm_core_V2_0
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_nxt_sp_i => adr_nxt_sp_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
cout_pc_i => cout_pc_o_i,
d_alu_i => d_alu_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_6flag_i => reg_6flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
fetch_o => fetch_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
reg_0flag_o => reg_0flag_core_o_i,
reg_1flag_o => open,
reg_3flag_o => reg_3flag_core_o_i,
reg_7flag_o => reg_7flag_core_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o,
sel_alu_as_o_i => sel_alu_as_o_i,
sel_alu_out_o_i => sel_alu_out_o_i,
sel_pc_as_o_i => sel_pc_as_o_i,
sel_pc_in_o_i => sel_pc_in_o_i,
sel_pc_val_o_i => sel_pc_val_o_i,
sel_rb_in_o_i => sel_rb_in_o_i,
sel_rb_out_o_i => sel_rb_out_o_i,
sel_reg_o_i => sel_reg_o_i,
sel_sp_as_o_i => sel_sp_as_o_i,
sel_sp_in_o_i => sel_sp_in_o_i,
sel_sp_val_o_i => sel_sp_val_o_i
);
U_6 : fsm_nmi
port map (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
fetch_i => fetch_o_i,
nmi_n_i => nmi_n_i,
ld_low_i => ld_o_i(0),
ld_sp_i => ld_sp_o_i,
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
sel_sp_as_i => sel_sp_as_o_i,
sel_sp_in_i => sel_sp_in_o_i,
adr_sp_o => adr_sp_o_i
);
 
end struct;
/trunk/rtl/vhdl/fsm_nmi.vhd
1,8 → 1,8
-- VHDL Entity R6502_TC.fsm_nmi.symbol
-- VHDL Entity R6502_TC.FSM_NMI.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:49:03 17.04.2008
-- at - 22:53:21 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
10,7 → 10,7
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity fsm_nmi is
entity FSM_NMI is
port(
clk_clk_i : in std_logic;
fetch_i : in std_logic;
21,7 → 21,7
 
-- Declarations
 
end fsm_nmi ;
end FSM_NMI ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
 
51,20 → 51,22
 
--
 
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
 
-- <<-- more -->>
 
-- Title: FSM for NMI
 
-- Path: R6502_TC/fsm_nmi/fsm
-- Path: R6502_TC/FSM_NMI/fsm
 
-- Edited: by eda on 17 Apr 2008
-- Edited: by eda on 03 Jan 2009
 
--
-- VHDL Architecture R6502_TC.fsm_nmi.fsm
-- VHDL Architecture R6502_TC.FSM_NMI.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:49:03 17.04.2008
-- at - 22:53:21 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
72,7 → 74,7
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_nmi is
architecture fsm of FSM_NMI is
 
type state_type is (
idle,
129,6 → 131,7
-----------------------------------------------------------------
begin
case current_state is
-- <<< REQ1
when idle =>
if (nmi_n_i = '1') then
next_state <= idle1;
150,6 → 153,8
when IMP =>
if (fetch_i = '1') then
next_state <= idle;
else
next_state <= IMP;
end if;
when others =>
next_state <= idle;
/trunk/rtl/vhdl/regbank_axy.vhd
2,7 → 2,7
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:48:45 17.04.2008
-- at - 22:53:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
15,8 → 15,8
clk_clk_i : in std_logic;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic;
rst_rst_i : in std_logic;
sel_rb_in_i : in std_logic_vector (2 downto 0);
rst_rst_n_i : in std_logic;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
43,16 → 43,17
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Register Bank for register A, X and Y
-- Path: R6502_TC/RegBank_AXY/struct
-- Edited: by eda on 17 Apr 2008
-- Edited: by eda on 02 Jan 2009
--
-- VHDL Architecture R6502_TC.RegBank_AXY.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:48:45 17.04.2008
-- at - 22:53:07 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
66,15 → 67,12
-- Architecture declarations
 
-- Internal signal declarations
signal dout : std_logic_vector(7 downto 0);
signal dout1 : std_logic_vector(7 downto 0);
signal ld : std_logic_vector(3 downto 0);
signal load : std_logic;
signal load1 : std_logic;
signal load2 : std_logic;
signal load3 : std_logic;
signal q_zw : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
signal ld : std_logic_vector(2 downto 0);
signal load1_o_i : std_logic;
signal load2_o_i : std_logic;
signal load_o_i : std_logic;
signal q_mux_o_i : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
 
-- Implicit buffer signal declarations
signal q_a_o_internal : std_logic_vector (7 downto 0);
91,26 → 89,18
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
signal mw_U_5reg_cval : std_logic_vector(7 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_10' of 'adff'
signal mw_U_10reg_cval : std_logic_vector(7 downto 0);
 
 
begin
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
val_zero (7 downto 0) <= X"00";
 
 
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
q_a_o_internal <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_i)
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_i = '1') then
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load = '1') then
mw_U_0reg_cval <= dout;
if (load_o_i = '1') then
mw_U_0reg_cval <= q_mux_o_i;
end if;
end if;
end process u_0seq_proc;
117,13 → 107,13
 
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
q_x_o_internal <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_i)
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_i = '1') then
if (rst_rst_n_i = '0') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load1 = '1') then
mw_U_4reg_cval <= dout;
if (load1_o_i = '1') then
mw_U_4reg_cval <= q_mux_o_i;
end if;
end if;
end process u_4seq_proc;
130,41 → 120,28
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
q_y_o_internal <= mw_U_5reg_cval;
u_5seq_proc: process (clk_clk_i, rst_rst_i)
u_5seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_i = '1') then
if (rst_rst_n_i = '0') then
mw_U_5reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load2 = '1') then
mw_U_5reg_cval <= dout;
if (load2_o_i = '1') then
mw_U_5reg_cval <= q_mux_o_i;
end if;
end if;
end process u_5seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'adff'
q_zw <= mw_U_10reg_cval;
u_10seq_proc: process (clk_clk_i, rst_rst_i)
begin
if (rst_rst_i = '1') then
mw_U_10reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load3 = '1') then
mw_U_10reg_cval <= dout;
end if;
end if;
end process u_10seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load <= load_regs_i and ld(0);
load_o_i <= load_regs_i and ld(0);
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load1 <= load_regs_i and ld(1);
load1_o_i <= load_regs_i and ld(1);
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'and'
load2 <= load_regs_i and ld(2);
load2_o_i <= load_regs_i and ld(2);
 
-- ModuleWare code(v1.9) for instance 'U_9' of 'and'
load3 <= load_regs_i and ld(3);
-- ModuleWare code(v1.9) for instance 'U_11' of 'constval'
val_zero <= "00000000";
 
-- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
u_1combo_proc: process (sel_reg_i)
174,7 → 151,6
when "00" => ld(0) <= '1';
when "01" => ld(1) <= '1';
when "10" => ld(2) <= '1';
when "11" => ld(3) <= '1';
when others => ld <= (others => '0');
end case;
end process u_1combo_proc;
181,13 → 157,13
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal,
q_zw, sel_rb_out_i)
val_zero, sel_rb_out_i)
begin
case sel_rb_out_i is
when "00" => d_regs_out_o <= q_a_o_internal;
when "01" => d_regs_out_o <= q_x_o_internal;
when "10" => d_regs_out_o <= q_y_o_internal;
when "11" => d_regs_out_o <= q_zw;
when "11" => d_regs_out_o <= val_zero;
when others => d_regs_out_o <= (others => 'X');
end case;
end process u_2combo_proc;
194,27 → 170,17
 
-- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal,
d_regs_in_i, sel_rb_in_i(1 DOWNTO 0))
d_regs_in_i, sel_rb_in_i)
begin
case sel_rb_in_i(1 DOWNTO 0) is
when "00" => dout1 <= q_a_o_internal;
when "01" => dout1 <= q_y_o_internal;
when "10" => dout1 <= q_x_o_internal;
when "11" => dout1 <= d_regs_in_i;
when others => dout1 <= (others => 'X');
case sel_rb_in_i is
when "00" => q_mux_o_i <= q_a_o_internal;
when "01" => q_mux_o_i <= q_y_o_internal;
when "10" => q_mux_o_i <= q_x_o_internal;
when "11" => q_mux_o_i <= d_regs_in_i;
when others => q_mux_o_i <= (others => 'X');
end case;
end process u_3combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'mux'
u_11combo_proc: process(dout1, q_zw, sel_rb_in_i(2))
begin
case sel_rb_in_i(2) is
when '0' => dout <= dout1;
when '1' => dout <= q_zw;
when others => dout <= (others => 'X');
end case;
end process u_11combo_proc;
 
-- Instance port mappings.
 
-- Implicit buffered output assignments
/trunk/doc/HTML/R6502_TCR6502_TCindex.htm
1118,62 → 1118,6
'BlockDiagram', 'R6502_TC/Reg_PC/struct',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'R6502_TC/Reg_PC/struct');
nodes[6] = theMenu.addChild(nodes[5],
'VHDL', '1: eb1',
'R6502_TC/@reg_@p@c/struct_bd@072eb1.htm',
'1: eb1');
nodes[6] = theMenu.addChild(nodes[5],
'VHDL', '2: eb2',
'R6502_TC/@reg_@p@c/struct_bd@072eb2.htm',
'2: eb2');
nodes[6] = theMenu.addChild(nodes[5],
'VHDL', '3: eb3',
'R6502_TC/@reg_@p@c/struct_bd@072eb3.htm',
'3: eb3');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_0 : moduleware.adff',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_0 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_10 : moduleware.and',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_10 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_11 : moduleware.addsub',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_11 : moduleware.addsub');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_12 : moduleware.addsub',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_12 : moduleware.addsub');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_2 : moduleware.inv',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_2 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_4 : moduleware.adff',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_4 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_5 : moduleware.mux',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_5 : moduleware.mux');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_6 : moduleware.and',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_6 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_7 : moduleware.and',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_7 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_8 : moduleware.mux',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_8 : moduleware.mux');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_9 : moduleware.mux',
'R6502_TC/@reg_@p@c/struct_bd.htm',
'U_9 : moduleware.mux');
nodes[4] = theMenu.addChild(nodes[3],
'Instance', 'U_1 : R6502_TC.Reg_SP',
'R6502_TC/@core/struct_bd.htm',
1182,46 → 1126,6
'BlockDiagram', 'R6502_TC/Reg_SP/struct',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'R6502_TC/Reg_SP/struct');
nodes[6] = theMenu.addChild(nodes[5],
'VHDL', '2: eb2',
'R6502_TC/@reg_@s@p/struct_bd@072eb2.htm',
'2: eb2');
nodes[6] = theMenu.addChild(nodes[5],
'VHDL', '3: eb3',
'R6502_TC/@reg_@s@p/struct_bd@072eb3.htm',
'3: eb3');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_0 : moduleware.adff',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_0 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_11 : moduleware.addsub',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_11 : moduleware.addsub');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_2 : moduleware.inv',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_2 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_4 : moduleware.adff',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_4 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_5 : moduleware.mux',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_5 : moduleware.mux');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_6 : moduleware.and',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_6 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_7 : moduleware.and',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_7 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_8 : moduleware.mux',
'R6502_TC/@reg_@s@p/struct_bd.htm',
'U_8 : moduleware.mux');
nodes[4] = theMenu.addChild(nodes[3],
'Instance', 'U_2 : R6502_TC.RegBank_AXY',
'R6502_TC/@core/struct_bd.htm',
1230,297 → 1134,165
'BlockDiagram', 'R6502_TC/RegBank_AXY/struct',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'R6502_TC/RegBank_AXY/struct');
nodes[6] = theMenu.addChild(nodes[5],
'VHDL', '1: eb1',
'R6502_TC/@reg@bank_@a@x@y/struct_bd@072eb1.htm',
'1: eb1');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_0 : moduleware.adff',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_0 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_1 : moduleware.decoder1',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_1 : moduleware.decoder1');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_10 : moduleware.adff',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_10 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_11 : moduleware.mux',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_11 : moduleware.mux');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_2 : moduleware.mux',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_2 : moduleware.mux');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_3 : moduleware.mux',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_3 : moduleware.mux');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_4 : moduleware.adff',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_4 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_5 : moduleware.adff',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_5 : moduleware.adff');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_6 : moduleware.and',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_6 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_7 : moduleware.and',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_7 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_8 : moduleware.and',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_8 : moduleware.and');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_9 : moduleware.and',
'R6502_TC/@reg@bank_@a@x@y/struct_bd.htm',
'U_9 : moduleware.and');
nodes[4] = theMenu.addChild(nodes[3],
'Instance', 'U_3 : R6502_TC.ALU',
'Instance', 'U_4 : R6502_TC.FSM_Execution_Unit',
'R6502_TC/@core/struct_bd.htm',
'U_3 : R6502_TC.ALU');
'U_4 : R6502_TC.FSM_Execution_Unit');
nodes[5] = theMenu.addChild(nodes[4],
'BlockDiagram', 'R6502_TC/ALU/struct',
'R6502_TC/@a@l@u/struct_bd.htm',
'R6502_TC/ALU/struct');
'StateDiagram', 'R6502_TC/FSM_Execution_Unit/fsm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm.htm',
'R6502_TC/FSM_Execution_Unit/fsm');
nodes[6] = theMenu.addChild(nodes[5],
'VHDL', '3: eb3',
'R6502_TC/@a@l@u/struct_bd@072eb3.htm',
'3: eb3');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_0 : moduleware.sand',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_0 : moduleware.sand');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_1 : moduleware.sor',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_1 : moduleware.sor');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_10 : moduleware.inv',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_10 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_11 : moduleware.sand',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_11 : moduleware.sand');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_12 : moduleware.sor',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_12 : moduleware.sor');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_13 : moduleware.sand',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_13 : moduleware.sand');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_14 : moduleware.inv',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_14 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_2 : moduleware.sxor',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_2 : moduleware.sxor');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_3 : moduleware.inv',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_3 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_4 : moduleware.inv',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_4 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_5 : moduleware.mux',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_5 : moduleware.mux');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_7 : moduleware.por',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_7 : moduleware.por');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_8 : moduleware.inv',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_8 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'InlineModulewareInstance', 'U_9 : moduleware.inv',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_9 : moduleware.inv');
nodes[6] = theMenu.addChild(nodes[5],
'Instance', 'U_6 : R6502_TC.ADD_SUB',
'R6502_TC/@a@l@u/struct_bd.htm',
'U_6 : R6502_TC.ADD_SUB');
nodes[7] = theMenu.addChild(nodes[6],
'FlowDiagram', 'R6502_TC/ADD_SUB/flow',
'R6502_TC/@a@d@d_@s@u@b/flow_fc.htm',
'R6502_TC/ADD_SUB/flow');
nodes[8] = theMenu.addChild(nodes[7],
'FcConcurrent', 'process0',
'R6502_TC/@a@d@d_@s@u@b/flow_fc_process0.htm',
'process0');
nodes[4] = theMenu.addChild(nodes[3],
'Instance', 'U_4 : R6502_TC.fsm_core_V2_0',
'R6502_TC/@core/struct_bd.htm',
'U_4 : R6502_TC.fsm_core_V2_0');
nodes[5] = theMenu.addChild(nodes[4],
'StateDiagram', 'R6502_TC/fsm_core_V2_0/fsm',
'R6502_TC/fsm_core_@v2_0/fsm_sm.htm',
'R6502_TC/fsm_core_V2_0/fsm');
nodes[6] = theMenu.addChild(nodes[5],
'SmConcurrent', 'csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm.htm',
'csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'ADC :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@a@d@c.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@a@d@c.htm',
'ADC :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'ASL :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@a@s@l.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@a@s@l.htm',
'ASL :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'ASL1 :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@a@s@l1.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@a@s@l1.htm',
'ASL1 :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'BEQ :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@b@e@q.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@b@e@q.htm',
'BEQ :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'BIT :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@b@i@t.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@b@i@t.htm',
'BIT :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'BRK :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@b@r@k.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@b@r@k.htm',
'BRK :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'CLC :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@c@l@c.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@c@l@c.htm',
'CLC :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'CLD :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@c@l@d.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@c@l@d.htm',
'CLD :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'CLI :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@c@l@i.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@c@l@i.htm',
'CLI :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'CLV :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@c@l@v.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@c@l@v.htm',
'CLV :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'DEC :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@d@e@c.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@d@e@c.htm',
'DEC :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'DEX :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@d@e@x.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@d@e@x.htm',
'DEX :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'IRQ :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@i@r@q.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@i@r@q.htm',
'IRQ :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'JMP :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@j@m@p.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@j@m@p.htm',
'JMP :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'JSR :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@j@s@r.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@j@s@r.htm',
'JSR :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'LDA :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@l@d@a.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@l@d@a.htm',
'LDA :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'LSR1 :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@l@s@r1.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@l@s@r1.htm',
'LSR1 :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'NMI :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@n@m@i.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@n@m@i.htm',
'NMI :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'NOP :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@n@o@p.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@n@o@p.htm',
'NOP :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'PHA :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@p@h@a.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@p@h@a.htm',
'PHA :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'PHP :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@p@h@p.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@p@h@p.htm',
'PHP :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'PLA :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@p@l@a.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@p@l@a.htm',
'PLA :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'PLP :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@p@l@p.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@p@l@p.htm',
'PLP :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'RES1 :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@r@e@s1.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@r@e@s1.htm',
'RES1 :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'RL1 :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@r@l1.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@r@l1.htm',
'RL1 :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'RR1 :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@r@r1.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@r@r1.htm',
'RR1 :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'RTI :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@r@t@i.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@r@t@i.htm',
'RTI :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'RTS :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@r@t@s.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@r@t@s.htm',
'RTS :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'SBC :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@s@b@c.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@s@b@c.htm',
'SBC :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'SEC :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@s@e@c.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@s@e@c.htm',
'SEC :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'SED :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@s@e@d.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@s@e@d.htm',
'SED :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'SEI :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@s@e@i.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@s@e@i.htm',
'SEI :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'STA :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@s@t@a.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@s@t@a.htm',
'STA :csm');
nodes[7] = theMenu.addChild(nodes[6],
'StateDiagram', 'TAX :csm',
'R6502_TC/fsm_core_@v2_0/fsm_sm_csm_@t@a@x.htm',
'R6502_TC/@f@s@m_@execution_@unit/fsm_sm_csm_@t@a@x.htm',
'TAX :csm');
nodes[4] = theMenu.addChild(nodes[3],
'Instance', 'U_6 : R6502_TC.fsm_nmi',
'Instance', 'U_6 : R6502_TC.FSM_NMI',
'R6502_TC/@core/struct_bd.htm',
'U_6 : R6502_TC.fsm_nmi');
'U_6 : R6502_TC.FSM_NMI');
nodes[5] = theMenu.addChild(nodes[4],
'StateDiagram', 'R6502_TC/fsm_nmi/fsm',
'R6502_TC/fsm_nmi/fsm_sm.htm',
'R6502_TC/fsm_nmi/fsm');
'StateDiagram', 'R6502_TC/FSM_NMI/fsm',
'R6502_TC/@f@s@m_@n@m@i/fsm_sm.htm',
'R6502_TC/FSM_NMI/fsm');
nodes[6] = theMenu.addChild(nodes[5],
'SmConcurrent', 'csm',
'R6502_TC/fsm_nmi/fsm_sm_csm.htm',
'R6502_TC/@f@s@m_@n@m@i/fsm_sm_csm.htm',
'csm');
 
}

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