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URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

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Rev 10 → Rev 11

/trunk/bench/verilog/dbg_tb.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/09/20 10:10:29 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3 2001/09/19 11:54:03 mohor
// Minor changes for simulation.
//
91,8 → 94,6
wire P_TDO;
wire [31:0] ADDR_RISC;
wire [31:0] DATAIN_RISC; // DATAIN_RISC is connect to DATAOUT
wire RISC_CS;
wire RISC_RW;
 
wire [31:0] DATAOUT_RISC; // DATAOUT_RISC is connect to DATAIN
 
100,11 → 101,11
 
// Connecting TAP module
dbg_top dbgTAP1(.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI),
.tdo_pad_o(P_TDO), .wb_rst_i(wb_rst_i), .mclk(Mclk),
.tdo_pad_o(P_TDO), .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk),
.risc_addr_o(ADDR_RISC), .risc_data_i(DATAOUT_RISC), .risc_data_o(DATAIN_RISC),
.risc_cs_o(RISC_CS), .risc_rw_o(RISC_RW), .wp_i(Wp), .bp_i(Bp),
.wp_i(Wp), .bp_i(Bp),
.opselect_o(OpSelect), .lsstatus_i(LsStatus), .istatus_i(IStatus),
. risc_stall_o(), . risc_reset_o()
.risc_stall_o(), .reset_o()
);
 
 
674,15 → 675,11
// print RISC registers read/write
always @ (posedge Mclk)
begin
if(dbg_tb.dbgTAP1.risc_cs_o)
if(dbg_tb.dbgTAP1.risc_rw_o)
begin
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
end
else
begin
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.risc_data_i[31:0]);
end
if(dbg_tb.dbgTAP1.RISCAccess & ~dbg_tb.dbgTAP1.RISCAccess_q & dbg_tb.dbgTAP1.RW)
$write("\n\t\tWrite to RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.DataOut[31:0]);
else
if(dbg_tb.dbgTAP1.RISCAccess_q & ~dbg_tb.dbgTAP1.RISCAccess_q2 & ~dbg_tb.dbgTAP1.RW)
$write("\n\t\tRead from RISC Register (addr=0x%h, data=0x%h)", dbg_tb.dbgTAP1.ADDR[31:0], dbg_tb.dbgTAP1.risc_data_i[31:0]);
end
 
 
/trunk/bench/verilog/file_communication.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/20 10:10:30 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
140,10 → 143,10
 
// Connecting dbgTAP module
dbg_top dbg1 (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), .tdo_pad_o(P_TDO),
.wb_rst_i(wb_rst_i), .mclk(Mclk), .risc_addr_o(), .risc_data_i(DataIn),
.risc_data_o(), .risc_cs_o(), .risc_rw_o(), .wp_i(11'h0), .bp_i(1'b0),
.wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), .risc_addr_o(), .risc_data_i(DataIn),
.risc_data_o(), .wp_i(11'h0), .bp_i(1'b0),
.opselect_o(), .lsstatus_i(4'h0), .istatus_i(2'h0),
. risc_stall_o(), . risc_reset_o()
.risc_stall_o(), .reset_o()
);
 
 
/trunk/rtl/verilog/dbg_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3 2001/09/19 11:55:13 mohor
// Asynchronous set/reset not used in trace any more.
//
74,8 → 77,8
tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
// RISC signals
mclk, risc_addr_o, risc_data_i, risc_data_o, risc_cs_o, risc_rw_o, wp_i,
bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, risc_reset_o,
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
// WISHBONE signals
wb_rst_i
92,7 → 95,7
 
 
// RISC signals
input mclk; // Master clock (RISC clock)
input risc_clk_i; // Master clock (RISC clock)
input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
input [10:0] wp_i; // Watchpoint inputs
input bp_i; // Breakpoint input
101,10 → 104,8
output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
output [31:0] risc_data_o; // RISC data output (data read from risc registers)
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
output risc_cs_o; // Chip select for accessing RISC registers
output risc_rw_o; // Read/write for accessing RISC registers
output risc_stall_o; // Stalls the RISC
output risc_reset_o; // Resets the RISC
output reset_o; // Resets the RISC
 
 
// WISHBONE signals
148,8 → 149,10
reg [31:0] risc_data_o;
reg [31:0] DataOut;
 
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
 
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
reg [31:0] RISC_DATAINLatch; // Data from DataIn is latched one mclk clock cycle after RISC register is
reg [31:0] RISC_DATAINLatch; // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is
// accessed for reading
reg [31:0] RegisterReadLatch; // Data when reading register is latched one TCK clock after the register is read.
reg RegAccessTck; // Indicates access to the registers (read or write)
181,7 → 184,11
wire RegisterScanChain; // Register Scan chain selected
wire RiscDebugScanChain; // Risc Debug Scan chain selected
 
wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
wire RiscStall_access; // Stalling RISC because of the read or write access
 
integer ii, jj, kk; // Counters for relocating bits bacuse of the RISC big endian mode of operation
243,6 → 250,9
wire TraceTestScanChain; // Trace Test Scan chain selected
wire [47:0] Trace_Data; // Trace data
 
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
// data is set to the risc_data_i)
 
`endif
 
 
715,19 → 725,19
end
 
 
// Synchronizing the RegAccess signal to mclk clock
dbg_sync_clk1_clk2 syn1 (.clk1(mclk), .clk2(TCK), .reset1(RESET), .reset2(RESET),
// Synchronizing the RegAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(TCK), .reset1(RESET), .reset2(RESET),
.set2(RegAccessTck), .sync_out(RegAccess)
);
 
// Synchronizing the RISCAccess signal to mclk clock
dbg_sync_clk1_clk2 syn2 (.clk1(mclk), .clk2(TCK), .reset1(RESET), .reset2(RESET),
// Synchronizing the RISCAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(TCK), .reset1(RESET), .reset2(RESET),
.set2(RISCAccessTck), .sync_out(RISCAccess)
);
 
 
// Delayed signals used for accessing registers and RISC
always @ (posedge mclk or posedge RESET)
always @ (posedge risc_clk_i or posedge RESET)
begin
if(RESET)
begin
747,7 → 757,7
 
 
// Latching data read from registers
always @ (posedge mclk or posedge RESET)
always @ (posedge risc_clk_i or posedge RESET)
begin
if(RESET)
RegisterReadLatch[31:0]<=#Tp 0;
758,23 → 768,37
 
 
// Chip select and read/write signals for accessing RISC
assign risc_cs_o = RISCAccess & ~RISCAccess_q;
assign risc_rw_o = RW;
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q & RW;
assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
//assign risc_rw_o = RW;
 
 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
`ifdef TRACE_ENABLED
assign risc_stall_o = risc_cs_o | RiscStall_reg | RiscStall_trace ;
assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
`else
assign risc_stall_o = risc_cs_o | RiscStall_reg;
assign risc_stall_o = RiscStall_access | RiscStall_read_access | RiscStall_reg;
`endif
 
assign risc_reset_o = RiscReset_reg;
assign reset_o = RiscReset_reg;
 
 
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
begin
if(RiscStall_write_access)
opselect_o = `DEBUG_WRITE_SPR; // Write spr
else
if(RiscStall_read_access)
opselect_o = `DEBUG_READ_SPR; // Read spr
else
opselect_o = opselect_trace;
end
 
 
 
// Latching data read from RISC
always @ (posedge mclk or posedge RESET)
always @ (posedge risc_clk_i or posedge RESET)
begin
if(RESET)
RISC_DATAINLatch[31:0]<=#Tp 0;
795,14 → 819,14
`ifdef TRACE_ENABLED
 
// Synchronizing the trace read buffer signal to mclk clock
dbg_sync_clk1_clk2 syn3 (.clk1(mclk), .clk2(TCK), .reset1(RESET), .reset2(RESET),
// Synchronizing the trace read buffer signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn3 (.clk1(risc_clk_i), .clk2(TCK), .reset1(RESET), .reset2(RESET),
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
);
 
 
 
always @(posedge mclk or posedge RESET)
always @(posedge risc_clk_i or posedge RESET)
begin
if(RESET)
ReadTraceBuffer_q <=#Tp 0;
988,7 → 1012,7
* *
**********************************************************************************/
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
.Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(mclk),
.Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
.Reset(wb_rst_i),
`ifdef TRACE_ENABLED
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
1093,9 → 1117,9
* *
**********************************************************************************/
`ifdef TRACE_ENABLED
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_o),
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
.Mclk(mclk), .Reset(RESET), .TraceChain(TraceChain),
.Mclk(risc_clk_i), .Reset(RESET), .TraceChain(TraceChain),
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
.WpTrigger(WpTrigger),
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
/trunk/rtl/verilog/dbg_defines.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2 2001/09/18 14:13:47 mohor
// Trace fixed. Some registers changed, trace simplified.
//
97,6 → 100,16
`define OPSELECTWIDTH 3
`define OPSELECTIONCOUNTER 8 //2^3
 
// OpSelect (dbg_op_i) signal meaning
`define DEBUG_READ_PC 0
`define DEBUG_READ_LSEA 1
`define DEBUG_READ_LDATA 2
`define DEBUG_READ_SDATA 3
`define DEBUG_READ_SPR 4
`define DEBUG_WRITE_SPR 5
`define DEBUG_READ_INSTR 6
//`define Reserved 7
 
// Supported Instructions
`define EXTEST 5'b00000
`define SAMPLE_PRELOAD 5'b00001

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