OpenCores
URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 10 to Rev 11
    ↔ Reverse comparison
  •

Rev 10 → Rev 11

/trunk/source/testbench/MDCT_TB.DO
21,11 → 21,21
#------------------------------------------------------------------------------
 
 
#set ROM_MODEL XILINX
set ROM_MODEL GENERIC
 
vlib work
vmap work work
vcom SOURCE/MDCT_PKG.vhd
vcom SOURCE/ROME.VHD
vcom SOURCE/ROMO.VHD
if {$ROM_MODEL=="XILINX"} {
vcom SOURCE/XILINX/ROME_XIL.VHD
vcom SOURCE/XILINX/ROME.VHD
vcom SOURCE/XILINX/ROMO_XIL.VHD
vcom SOURCE/XILINX/ROMO.VHD
} else {
vcom SOURCE/ROME.VHD
vcom SOURCE/ROMO.VHD
}
vcom SOURCE/RAM.VHD
vcom SOURCE/DCT1D.VHD
vcom SOURCE/DCT2D.VHD
/trunk/source/ROME.VHD
31,7 → 31,8
 
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
115,15 → 116,18
std_logic_vector( CP ),
(others => '0')
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
 
process( addr )
datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) );
process(clk)
begin
datao <= rom( TO_INTEGER(UNSIGNED(addr)) );
end process;
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
/trunk/source/MDCT.VHD
189,7 → 189,8
------------------------------
component ROME
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
200,7 → 201,8
------------------------------
component ROMO
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
508,7 → 510,8
------------------------------
U1_ROME0 : ROME
port map(
addr => romeaddro0_s,
addr => romeaddro0_s,
clk => clk,
datao => romedatao0_s
);
519,6 → 522,7
U1_ROME1 : ROME
port map(
addr => romeaddro1_s,
clk => clk,
datao => romedatao1_s
);
528,7 → 532,8
------------------------------
U1_ROME2 : ROME
port map(
addr => romeaddro2_s,
addr => romeaddro2_s,
clk => clk,
datao => romedatao2_s
);
538,7 → 543,8
------------------------------
U1_ROME3 : ROME
port map(
addr => romeaddro3_s,
addr => romeaddro3_s,
clk => clk,
datao => romedatao3_s
);
547,7 → 553,8
------------------------------
U1_ROME4 : ROME
port map(
addr => romeaddro4_s,
addr => romeaddro4_s,
clk => clk,
datao => romedatao4_s
);
556,7 → 563,8
------------------------------
U1_ROME5 : ROME
port map(
addr => romeaddro5_s,
addr => romeaddro5_s,
clk => clk,
datao => romedatao5_s
);
565,7 → 573,8
------------------------------
U1_ROME6 : ROME
port map(
addr => romeaddro6_s,
addr => romeaddro6_s,
clk => clk,
datao => romedatao6_s
);
574,7 → 583,8
------------------------------
U1_ROME7 : ROME
port map(
addr => romeaddro7_s,
addr => romeaddro7_s,
clk => clk,
datao => romedatao7_s
);
583,7 → 593,8
------------------------------
U1_ROME8 : ROME
port map(
addr => romeaddro8_s,
addr => romeaddro8_s,
clk => clk,
datao => romedatao8_s
);
593,7 → 604,8
------------------------------
U1_ROMO0 : ROMO
port map(
addr => romoaddro0_s,
addr => romoaddro0_s,
clk => clk,
datao => romodatao0_s
);
602,7 → 614,8
------------------------------
U1_ROMO1 : ROMO
port map(
addr => romoaddro1_s,
addr => romoaddro1_s,
clk => clk,
datao => romodatao1_s
);
611,7 → 624,8
------------------------------
U1_ROMO2 : ROMO
port map(
addr => romoaddro2_s,
addr => romoaddro2_s,
clk => clk,
datao => romodatao2_s
);
620,7 → 634,8
------------------------------
U1_ROMO3 : ROMO
port map(
addr => romoaddro3_s,
addr => romoaddro3_s,
clk => clk,
datao => romodatao3_s
);
630,6 → 645,7
U1_ROMO4 : ROMO
port map(
addr => romoaddro4_s,
clk => clk,
datao => romodatao4_s
);
638,7 → 654,8
------------------------------
U1_ROMO5 : ROMO
port map(
addr => romoaddro5_s,
addr => romoaddro5_s,
clk => clk,
datao => romodatao5_s
);
647,7 → 664,8
------------------------------
U1_ROMO6 : ROMO
port map(
addr => romoaddro6_s,
addr => romoaddro6_s,
clk => clk,
datao => romodatao6_s
);
656,7 → 674,8
------------------------------
U1_ROMO7 : ROMO
port map(
addr => romoaddro7_s,
addr => romoaddro7_s,
clk => clk,
datao => romodatao7_s
);
665,7 → 684,8
------------------------------
U1_ROMO8 : ROMO
port map(
addr => romoaddro8_s,
addr => romoaddro8_s,
clk => clk,
datao => romodatao8_s
);
678,7 → 698,8
------------------------------
U2_ROME0 : ROME
port map(
addr => rome2addro0_s,
addr => rome2addro0_s,
clk => clk,
datao => rome2datao0_s
);
688,7 → 709,8
------------------------------
U2_ROME1 : ROME
port map(
addr => rome2addro1_s,
addr => rome2addro1_s,
clk => clk,
datao => rome2datao1_s
);
698,7 → 720,8
------------------------------
U2_ROME2 : ROME
port map(
addr => rome2addro2_s,
addr => rome2addro2_s,
clk => clk,
datao => rome2datao2_s
);
708,7 → 731,8
------------------------------
U2_ROME3 : ROME
port map(
addr => rome2addro3_s,
addr => rome2addro3_s,
clk => clk,
datao => rome2datao3_s
);
717,7 → 741,8
------------------------------
U2_ROME4 : ROME
port map(
addr => rome2addro4_s,
addr => rome2addro4_s,
clk => clk,
datao => rome2datao4_s
);
726,7 → 751,8
------------------------------
U2_ROME5 : ROME
port map(
addr => rome2addro5_s,
addr => rome2addro5_s,
clk => clk,
datao => rome2datao5_s
);
735,7 → 761,8
------------------------------
U2_ROME6 : ROME
port map(
addr => rome2addro6_s,
addr => rome2addro6_s,
clk => clk,
datao => rome2datao6_s
);
744,7 → 771,8
------------------------------
U2_ROME7 : ROME
port map(
addr => rome2addro7_s,
addr => rome2addro7_s,
clk => clk,
datao => rome2datao7_s
);
753,7 → 781,8
------------------------------
U2_ROME8 : ROME
port map(
addr => rome2addro8_s,
addr => rome2addro8_s,
clk => clk,
datao => rome2datao8_s
);
762,7 → 791,8
------------------------------
U2_ROME9 : ROME
port map(
addr => rome2addro9_s,
addr => rome2addro9_s,
clk => clk,
datao => rome2datao9_s
);
771,7 → 801,8
------------------------------
U2_ROME10 : ROME
port map(
addr => rome2addro10_s,
addr => rome2addro10_s,
clk => clk,
datao => rome2datao10_s
);
781,7 → 812,8
------------------------------
U2_ROMO0 : ROMO
port map(
addr => romo2addro0_s,
addr => romo2addro0_s,
clk => clk,
datao => romo2datao0_s
);
790,7 → 822,8
------------------------------
U2_ROMO1 : ROMO
port map(
addr => romo2addro1_s,
addr => romo2addro1_s,
clk => clk,
datao => romo2datao1_s
);
799,7 → 832,8
------------------------------
U2_ROMO2 : ROMO
port map(
addr => romo2addro2_s,
addr => romo2addro2_s,
clk => clk,
datao => romo2datao2_s
);
808,7 → 842,8
------------------------------
U2_ROMO3 : ROMO
port map(
addr => romo2addro3_s,
addr => romo2addro3_s,
clk => clk,
datao => romo2datao3_s
);
817,7 → 852,8
------------------------------
U2_ROMO4 : ROMO
port map(
addr => romo2addro4_s,
addr => romo2addro4_s,
clk => clk,
datao => romo2datao4_s
);
826,7 → 862,8
------------------------------
U2_ROMO5 : ROMO
port map(
addr => romo2addro5_s,
addr => romo2addro5_s,
clk => clk,
datao => romo2datao5_s
);
835,7 → 872,8
------------------------------
U2_ROMO6 : ROMO
port map(
addr => romo2addro6_s,
addr => romo2addro6_s,
clk => clk,
datao => romo2datao6_s
);
844,7 → 882,8
------------------------------
U2_ROMO7 : ROMO
port map(
addr => romo2addro7_s,
addr => romo2addro7_s,
clk => clk,
datao => romo2datao7_s
);
853,7 → 892,8
------------------------------
U2_ROMO8 : ROMO
port map(
addr => romo2addro8_s,
addr => romo2addro8_s,
clk => clk,
datao => romo2datao8_s
);
862,7 → 902,8
------------------------------
U2_ROMO9 : ROMO
port map(
addr => romo2addro9_s,
addr => romo2addro9_s,
clk => clk,
datao => romo2datao9_s
);
871,7 → 912,8
------------------------------
U2_ROMO10 : ROMO
port map(
addr => romo2addro10_s,
addr => romo2addro10_s,
clk => clk,
datao => romo2datao10_s
);
/trunk/source/xilinx/Romo.coe
0,0 → 1,67
; Sample Initialization file for ROMO
memory_initialization_radix = 2;
memory_initialization_vector =
00000000000000,
00000110010000,
00010001110010,
00011000000010,
00011010100111,
00100000110111,
00101100011001,
00110010101001,
00011111011001,
00100101101001,
00110001001011,
00110111011011,
00111010000000,
01000000010000,
01001011110010,
01010010000010,
00000000000000,
11101110001110,
11100000100111,
11001110110101,
11111001110000,
11100111111110,
11011010010111,
11001000100101,
00011010100111,
00001000110101,
11111011001110,
11101001011100,
00010100010111,
00000010100101,
11110100111110,
11100011001100,
00000000000000,
00011010100111,
00000110010000,
00100000110111,
11100000100111,
11111011001110,
11100110110111,
00000001011110,
00010001110010,
00101100011001,
00011000000010,
00110010101001,
11110010011001,
00001101000000,
11111000101001,
00010011010000,
00000000000000,
11100000100111,
00011010100111,
11111011001110,
11101110001110,
11001110110101,
00001000110101,
11101001011100,
00000110010000,
11100110110111,
00100000110111,
00000001011110,
11110100011110,
11010101000101,
00001111000101,
11101111101100;
/trunk/source/xilinx/ROME.VHD
0,0 → 1,65
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
 
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use WORK.MDCT_PKG.all;
 
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
 
architecture XILINX of ROME is
component rome_xil
port
(
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0)
);
end component;
 
begin
 
U1 : rome_xil
port map
(
A => addr,
CLK => clk,
QSPO => datao
);
end XILINX;
--------------------------------------------------------------------------------
/trunk/source/xilinx/romo_xil.mif
0,0 → 1,64
00000000000000
00000110010000
00010001110010
00011000000010
00011010100111
00100000110111
00101100011001
00110010101001
00011111011001
00100101101001
00110001001011
00110111011011
00111010000000
01000000010000
01001011110010
01010010000010
00000000000000
11101110001110
11100000100111
11001110110101
11111001110000
11100111111110
11011010010111
11001000100101
00011010100111
00001000110101
11111011001110
11101001011100
00010100010111
00000010100101
11110100111110
11100011001100
00000000000000
00011010100111
00000110010000
00100000110111
11100000100111
11111011001110
11100110110111
00000001011110
00010001110010
00101100011001
00011000000010
00110010101001
11110010011001
00001101000000
11111000101001
00010011010000
00000000000000
11100000100111
00011010100111
11111011001110
11101110001110
11001110110101
00001000110101
11101001011100
00000110010000
11100110110111
00100000110111
00000001011110
11110100011110
11010101000101
00001111000101
11101111101100
/trunk/source/xilinx/rome_xil.edn
0,0 → 1,1655
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2006 4 20 20 18 13)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.3i"))))
(comment "
This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of
design files limited to Xilinx devices or technologies. Use
with non-Xilinx devices or technologies is expressly prohibited
and immediately terminates your license.
XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE.
Xilinx products are not intended for use in life support
appliances, devices, or systems. Use in such applications are
expressly prohibited.
(c) Copyright 1995-2004 Xilinx, Inc.
All rights reserved.
")
(comment "Core parameters: ")
(comment "c_qualify_we = false ")
(comment "c_mem_type = 0 ")
(comment "c_has_qdpo_rst = false ")
(comment "InstanceName = rome_xil ")
(comment "c_has_qspo = true ")
(comment "c_has_qspo_rst = false ")
(comment "c_family = spartan3 ")
(comment "c_has_dpo = false ")
(comment "c_has_qdpo_clk = false ")
(comment "c_has_d = false ")
(comment "c_qce_joined = false ")
(comment "c_width = 14 ")
(comment "c_reg_a_d_inputs = false ")
(comment "c_latency = 1 ")
(comment "c_has_spo = false ")
(comment "c_has_we = false ")
(comment "c_depth = 64 ")
(comment "c_has_i_ce = false ")
(comment "c_default_data_radix = 2 ")
(comment "c_default_data = 0 ")
(comment "c_has_dpra = false ")
(comment "c_has_clk = true ")
(comment "c_enable_rlocs = true ")
(comment "c_generate_mif = true ")
(comment "c_has_qspo_ce = false ")
(comment "c_addr_width = 6 ")
(comment "c_has_qdpo_srst = false ")
(comment "c_mux_type = 0 ")
(comment "c_has_spra = false ")
(comment "c_has_qdpo = false ")
(comment "c_mem_init_file = rome_xil.mif ")
(comment "c_reg_dpra_input = false ")
(comment "c_has_qspo_srst = false ")
(comment "c_has_rd_en = false ")
(comment "c_read_mif = true ")
(comment "c_sync_enable = 0 ")
(comment "c_has_qdpo_ce = false ")
(external xilinxun (edifLevel 0)
(technology (numberDefinition))
(cell VCC (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
(cell GND (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port G (direction OUTPUT))
)
)
)
(cell FDE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell LUT4 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXF5 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXF6 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
)
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell rome_xil
(cellType GENERIC) (view view_1 (viewType NETLIST)
(interface
(port ( array ( rename A "A(5:0)") 6 ) (direction INPUT))
(port ( rename CLK "CLK") (direction INPUT))
(port ( array ( rename QSPO "QSPO(13:0)") 14 ) (direction OUTPUT))
)
(contents
(instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun))))
(instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun))))
(instance BU11
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y1"))
(property INIT (string "0000"))
)
(instance BU12
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y1"))
(property INIT (string "0000"))
)
(instance BU13
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y1"))
)
(instance BU14
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
(property INIT (string "0000"))
)
(instance BU15
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
(property INIT (string "0000"))
)
(instance BU16
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
)
(instance BU17
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
)
(instance BU19
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
)
(instance BU24
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y3"))
(property INIT (string "0000"))
)
(instance BU25
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y3"))
(property INIT (string "0000"))
)
(instance BU26
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y3"))
)
(instance BU27
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
(property INIT (string "0000"))
)
(instance BU28
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
(property INIT (string "0000"))
)
(instance BU29
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
)
(instance BU30
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
)
(instance BU32
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
)
(instance BU37
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y5"))
(property INIT (string "0000"))
)
(instance BU38
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y5"))
(property INIT (string "55aa"))
)
(instance BU39
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y5"))
)
(instance BU40
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
(property INIT (string "0000"))
)
(instance BU41
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
(property INIT (string "3c3c"))
)
(instance BU42
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
)
(instance BU43
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
)
(instance BU45
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
)
(instance BU50
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y7"))
(property INIT (string "6996"))
)
(instance BU51
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y7"))
(property INIT (string "00aa"))
)
(instance BU52
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y7"))
)
(instance BU53
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
(property INIT (string "6996"))
)
(instance BU54
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
(property INIT (string "3030"))
)
(instance BU55
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
)
(instance BU56
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
)
(instance BU58
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
)
(instance BU63
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y9"))
(property INIT (string "7ee8"))
)
(instance BU64
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y9"))
(property INIT (string "3c96"))
)
(instance BU65
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y9"))
)
(instance BU66
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
(property INIT (string "42d4"))
)
(instance BU67
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
(property INIT (string "659a"))
)
(instance BU68
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
)
(instance BU69
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
)
(instance BU71
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
)
(instance BU76
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y11"))
(property INIT (string "e996"))
)
(instance BU77
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y11"))
(property INIT (string "5924"))
)
(instance BU78
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y11"))
)
(instance BU79
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
(property INIT (string "2942"))
)
(instance BU80
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
(property INIT (string "1c86"))
)
(instance BU81
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
)
(instance BU82
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
)
(instance BU84
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
)
(instance BU89
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y13"))
(property INIT (string "7ee8"))
)
(instance BU90
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y13"))
(property INIT (string "5d04"))
)
(instance BU91
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y13"))
)
(instance BU92
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
(property INIT (string "4294"))
)
(instance BU93
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
(property INIT (string "0c8e"))
)
(instance BU94
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
)
(instance BU95
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
)
(instance BU97
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
)
(instance BU102
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y15"))
(property INIT (string "e996"))
)
(instance BU103
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y15"))
(property INIT (string "08ae"))
)
(instance BU104
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y15"))
)
(instance BU105
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
(property INIT (string "2942"))
)
(instance BU106
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
(property INIT (string "30b2"))
)
(instance BU107
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
)
(instance BU108
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
)
(instance BU110
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
)
(instance BU115
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y17"))
(property INIT (string "177e"))
)
(instance BU116
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y17"))
(property INIT (string "6138"))
)
(instance BU117
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y17"))
)
(instance BU118
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
(property INIT (string "2b02"))
)
(instance BU119
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
(property INIT (string "5924"))
)
(instance BU120
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
)
(instance BU121
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
)
(instance BU123
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
)
(instance BU128
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y19"))
(property INIT (string "9668"))
)
(instance BU129
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y19"))
(property INIT (string "7130"))
)
(instance BU130
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y19"))
)
(instance BU131
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
(property INIT (string "4294"))
)
(instance BU132
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
(property INIT (string "5d04"))
)
(instance BU133
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
)
(instance BU134
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
)
(instance BU136
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
)
(instance BU141
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y21"))
(property INIT (string "8116"))
)
(instance BU142
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y21"))
(property INIT (string "4d0c"))
)
(instance BU143
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y21"))
)
(instance BU144
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
(property INIT (string "2942"))
)
(instance BU145
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
(property INIT (string "08ae"))
)
(instance BU146
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
)
(instance BU147
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
)
(instance BU149
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
)
(instance BU154
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y23"))
(property INIT (string "1668"))
)
(instance BU155
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y23"))
(property INIT (string "18a6"))
)
(instance BU156
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y23"))
)
(instance BU157
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
(property INIT (string "4294"))
)
(instance BU158
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
(property INIT (string "3492"))
)
(instance BU159
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
)
(instance BU160
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
)
(instance BU162
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
)
(instance BU167
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y25"))
(property INIT (string "e880"))
)
(instance BU168
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y25"))
(property INIT (string "08ae"))
)
(instance BU169
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y25"))
)
(instance BU170
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
(property INIT (string "40d4"))
)
(instance BU171
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
(property INIT (string "30b2"))
)
(instance BU172
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
)
(instance BU173
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
)
(instance BU175
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
)
(instance BU180
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y27"))
(property INIT (string "0000"))
)
(instance BU181
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y27"))
(property INIT (string "08ae"))
)
(instance BU182
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y27"))
)
(instance BU183
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
(property INIT (string "40d4"))
)
(instance BU184
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
(property INIT (string "30b2"))
)
(instance BU185
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
)
(instance BU186
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
)
(instance BU188
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
)
(net N1
(joined
(portRef P (instanceRef VCC))
(portRef CE (instanceRef BU19))
(portRef CE (instanceRef BU32))
(portRef CE (instanceRef BU45))
(portRef CE (instanceRef BU58))
(portRef CE (instanceRef BU71))
(portRef CE (instanceRef BU84))
(portRef CE (instanceRef BU97))
(portRef CE (instanceRef BU110))
(portRef CE (instanceRef BU123))
(portRef CE (instanceRef BU136))
(portRef CE (instanceRef BU149))
(portRef CE (instanceRef BU162))
(portRef CE (instanceRef BU175))
(portRef CE (instanceRef BU188))
)
)
(net (rename N2 "A(0)")
(joined
(portRef (member A 5))
(portRef I0 (instanceRef BU11))
(portRef I0 (instanceRef BU12))
(portRef I0 (instanceRef BU14))
(portRef I0 (instanceRef BU15))
(portRef I0 (instanceRef BU24))
(portRef I0 (instanceRef BU25))
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(portRef I0 (instanceRef BU40))
(portRef I0 (instanceRef BU41))
(portRef I0 (instanceRef BU50))
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(portRef I0 (instanceRef BU54))
(portRef I0 (instanceRef BU63))
(portRef I0 (instanceRef BU64))
(portRef I0 (instanceRef BU66))
(portRef I0 (instanceRef BU67))
(portRef I0 (instanceRef BU76))
(portRef I0 (instanceRef BU77))
(portRef I0 (instanceRef BU79))
(portRef I0 (instanceRef BU80))
(portRef I0 (instanceRef BU89))
(portRef I0 (instanceRef BU90))
(portRef I0 (instanceRef BU92))
(portRef I0 (instanceRef BU93))
(portRef I0 (instanceRef BU102))
(portRef I0 (instanceRef BU103))
(portRef I0 (instanceRef BU105))
(portRef I0 (instanceRef BU106))
(portRef I0 (instanceRef BU115))
(portRef I0 (instanceRef BU116))
(portRef I0 (instanceRef BU118))
(portRef I0 (instanceRef BU119))
(portRef I0 (instanceRef BU128))
(portRef I0 (instanceRef BU129))
(portRef I0 (instanceRef BU131))
(portRef I0 (instanceRef BU132))
(portRef I0 (instanceRef BU141))
(portRef I0 (instanceRef BU142))
(portRef I0 (instanceRef BU144))
(portRef I0 (instanceRef BU145))
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(portRef I0 (instanceRef BU157))
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(portRef I0 (instanceRef BU168))
(portRef I0 (instanceRef BU170))
(portRef I0 (instanceRef BU171))
(portRef I0 (instanceRef BU180))
(portRef I0 (instanceRef BU181))
(portRef I0 (instanceRef BU183))
(portRef I0 (instanceRef BU184))
)
)
(net (rename N3 "A(1)")
(joined
(portRef (member A 4))
(portRef I1 (instanceRef BU11))
(portRef I1 (instanceRef BU12))
(portRef I1 (instanceRef BU14))
(portRef I1 (instanceRef BU15))
(portRef I1 (instanceRef BU24))
(portRef I1 (instanceRef BU25))
(portRef I1 (instanceRef BU27))
(portRef I1 (instanceRef BU28))
(portRef I1 (instanceRef BU37))
(portRef I1 (instanceRef BU38))
(portRef I1 (instanceRef BU40))
(portRef I1 (instanceRef BU41))
(portRef I1 (instanceRef BU50))
(portRef I1 (instanceRef BU51))
(portRef I1 (instanceRef BU53))
(portRef I1 (instanceRef BU54))
(portRef I1 (instanceRef BU63))
(portRef I1 (instanceRef BU64))
(portRef I1 (instanceRef BU66))
(portRef I1 (instanceRef BU67))
(portRef I1 (instanceRef BU76))
(portRef I1 (instanceRef BU77))
(portRef I1 (instanceRef BU79))
(portRef I1 (instanceRef BU80))
(portRef I1 (instanceRef BU89))
(portRef I1 (instanceRef BU90))
(portRef I1 (instanceRef BU92))
(portRef I1 (instanceRef BU93))
(portRef I1 (instanceRef BU102))
(portRef I1 (instanceRef BU103))
(portRef I1 (instanceRef BU105))
(portRef I1 (instanceRef BU106))
(portRef I1 (instanceRef BU115))
(portRef I1 (instanceRef BU116))
(portRef I1 (instanceRef BU118))
(portRef I1 (instanceRef BU119))
(portRef I1 (instanceRef BU128))
(portRef I1 (instanceRef BU129))
(portRef I1 (instanceRef BU131))
(portRef I1 (instanceRef BU132))
(portRef I1 (instanceRef BU141))
(portRef I1 (instanceRef BU142))
(portRef I1 (instanceRef BU144))
(portRef I1 (instanceRef BU145))
(portRef I1 (instanceRef BU154))
(portRef I1 (instanceRef BU155))
(portRef I1 (instanceRef BU157))
(portRef I1 (instanceRef BU158))
(portRef I1 (instanceRef BU167))
(portRef I1 (instanceRef BU168))
(portRef I1 (instanceRef BU170))
(portRef I1 (instanceRef BU171))
(portRef I1 (instanceRef BU180))
(portRef I1 (instanceRef BU181))
(portRef I1 (instanceRef BU183))
(portRef I1 (instanceRef BU184))
)
)
(net (rename N4 "A(2)")
(joined
(portRef (member A 3))
(portRef I2 (instanceRef BU11))
(portRef I2 (instanceRef BU12))
(portRef I2 (instanceRef BU14))
(portRef I2 (instanceRef BU15))
(portRef I2 (instanceRef BU24))
(portRef I2 (instanceRef BU25))
(portRef I2 (instanceRef BU27))
(portRef I2 (instanceRef BU28))
(portRef I2 (instanceRef BU37))
(portRef I2 (instanceRef BU38))
(portRef I2 (instanceRef BU40))
(portRef I2 (instanceRef BU41))
(portRef I2 (instanceRef BU50))
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(portRef I2 (instanceRef BU79))
(portRef I2 (instanceRef BU80))
(portRef I2 (instanceRef BU89))
(portRef I2 (instanceRef BU90))
(portRef I2 (instanceRef BU92))
(portRef I2 (instanceRef BU93))
(portRef I2 (instanceRef BU102))
(portRef I2 (instanceRef BU103))
(portRef I2 (instanceRef BU105))
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(portRef I2 (instanceRef BU128))
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(portRef I2 (instanceRef BU180))
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(portRef I2 (instanceRef BU183))
(portRef I2 (instanceRef BU184))
)
)
(net (rename N5 "A(3)")
(joined
(portRef (member A 2))
(portRef I3 (instanceRef BU11))
(portRef I3 (instanceRef BU12))
(portRef I3 (instanceRef BU14))
(portRef I3 (instanceRef BU15))
(portRef I3 (instanceRef BU24))
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(portRef I3 (instanceRef BU93))
(portRef I3 (instanceRef BU102))
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(portRef I3 (instanceRef BU180))
(portRef I3 (instanceRef BU181))
(portRef I3 (instanceRef BU183))
(portRef I3 (instanceRef BU184))
)
)
(net (rename N6 "A(4)")
(joined
(portRef (member A 1))
(portRef S (instanceRef BU13))
(portRef S (instanceRef BU16))
(portRef S (instanceRef BU26))
(portRef S (instanceRef BU29))
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(portRef S (instanceRef BU78))
(portRef S (instanceRef BU81))
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(portRef S (instanceRef BU104))
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(portRef S (instanceRef BU120))
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(portRef S (instanceRef BU172))
(portRef S (instanceRef BU182))
(portRef S (instanceRef BU185))
)
)
(net (rename N7 "A(5)")
(joined
(portRef (member A 0))
(portRef S (instanceRef BU17))
(portRef S (instanceRef BU30))
(portRef S (instanceRef BU43))
(portRef S (instanceRef BU56))
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)
)
(net (rename N8 "CLK")
(joined
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(joined
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)
)
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(joined
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(portRef Q (instanceRef BU149))
)
)
(net (rename N20 "QSPO(11)")
(joined
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(portRef Q (instanceRef BU162))
)
)
(net (rename N21 "QSPO(12)")
(joined
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(portRef Q (instanceRef BU175))
)
)
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(joined
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)
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(net N70
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(net N194
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)
))))
(design rome_xil (cellRef rome_xil (libraryRef test_lib))
(property X_CORE_INFO (string "C_DIST_MEM_V7_1, Coregen 6.3i"))
(property PART (string "XC3S5000-4-fg900") (owner "Xilinx")))
)
/trunk/source/xilinx/Rome.coe
0,0 → 1,67
; Sample Initialization file for ROME
memory_initialization_radix = 2;
memory_initialization_vector =
00000000000000,
00010110101000,
00010110101000,
00101101010000,
00010110101000,
00101101010000,
00101101010000,
01000011111000,
00010110101000,
00101101010000,
00101101010000,
01000011111000,
00101101010000,
01000011111000,
01000011111000,
01011010100000,
00000000000000,
11100010011100,
11110011110000,
11010110001100,
00001100010000,
11101110101100,
00000000000000,
11100010011100,
00011101100100,
00000000000000,
00010001010100,
11110011110000,
00101001110100,
00001100010000,
00011101100100,
00000000000000,
00000000000000,
00010110101000,
11101001011000,
00000000000000,
11101001011000,
00000000000000,
11010010110000,
11101001011000,
00010110101000,
00101101010000,
00000000000000,
00010110101000,
00000000000000,
00010110101000,
11101001011000,
00000000000000,
00000000000000,
11110011110000,
00011101100100,
00010001010100,
11100010011100,
11010110001100,
00000000000000,
11110011110000,
00001100010000,
00000000000000,
00101001110100,
00011101100100,
11101110101100,
11100010011100,
00001100010000,
00000000000000;
/trunk/source/xilinx/rome_xil.mif
0,0 → 1,64
00000000000000
00010110101000
00010110101000
00101101010000
00010110101000
00101101010000
00101101010000
01000011111000
00010110101000
00101101010000
00101101010000
01000011111000
00101101010000
01000011111000
01000011111000
01011010100000
00000000000000
11100010011100
11110011110000
11010110001100
00001100010000
11101110101100
00000000000000
11100010011100
00011101100100
00000000000000
00010001010100
11110011110000
00101001110100
00001100010000
00011101100100
00000000000000
00000000000000
00010110101000
11101001011000
00000000000000
11101001011000
00000000000000
11010010110000
11101001011000
00010110101000
00101101010000
00000000000000
00010110101000
00000000000000
00010110101000
11101001011000
00000000000000
00000000000000
11110011110000
00011101100100
00010001010100
11100010011100
11010110001100
00000000000000
11110011110000
00001100010000
00000000000000
00101001110100
00011101100100
11101110101100
11100010011100
00001100010000
00000000000000
/trunk/source/xilinx/romo_xil.vhd
0,0 → 1,107
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2004 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file romo_xil.vhd when simulating
-- the core, romo_xil. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
Library XilinxCoreLib;
ENTITY romo_xil IS
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
END romo_xil;
 
ARCHITECTURE romo_xil_a OF romo_xil IS
 
component wrapped_romo_xil
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_romo_xil use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
generic map(
c_qualify_we => 0,
c_mem_type => 0,
c_has_qdpo_rst => 0,
c_has_qspo => 1,
c_has_qspo_rst => 0,
c_has_dpo => 0,
c_has_qdpo_clk => 0,
c_has_d => 0,
c_qce_joined => 0,
c_width => 14,
c_reg_a_d_inputs => 0,
c_latency => 1,
c_has_we => 0,
c_has_spo => 0,
c_depth => 64,
c_has_i_ce => 0,
c_default_data => "0",
c_default_data_radix => 2,
c_has_dpra => 0,
c_has_clk => 1,
c_enable_rlocs => 1,
c_generate_mif => 1,
c_addr_width => 6,
c_has_qspo_ce => 0,
c_has_qdpo_srst => 0,
c_mux_type => 0,
c_has_spra => 0,
c_has_qdpo => 0,
c_mem_init_file => "c:/elektronika/dct/mdct/source/xilinx/romo_xil.mif",
c_reg_dpra_input => 0,
c_has_rd_en => 0,
c_has_qspo_srst => 0,
c_read_mif => 1,
c_sync_enable => 0,
c_has_qdpo_ce => 0);
BEGIN
 
U0 : wrapped_romo_xil
port map (
A => A,
CLK => CLK,
QSPO => QSPO);
END romo_xil_a;
 
-- synopsys translate_on
 
/trunk/source/xilinx/ROMO.VHD
0,0 → 1,64
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMO.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (odd part)
--
--------------------------------------------------------------------------------
 
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use WORK.MDCT_PKG.all;
 
entity ROMO is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMO;
 
architecture XILINX of ROMO is
 
component romo_xil
port
(
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0)
);
end component;
 
begin
 
U1 : romo_xil
port map
(
A => addr,
CLK => clk,
QSPO => datao
);
end XILINX;
 
/trunk/source/xilinx/romo_xil.edn
0,0 → 1,1655
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2006 4 20 23 32 0)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.3i"))))
(comment "
This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of
design files limited to Xilinx devices or technologies. Use
with non-Xilinx devices or technologies is expressly prohibited
and immediately terminates your license.
XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE.
Xilinx products are not intended for use in life support
appliances, devices, or systems. Use in such applications are
expressly prohibited.
(c) Copyright 1995-2004 Xilinx, Inc.
All rights reserved.
")
(comment "Core parameters: ")
(comment "c_qualify_we = false ")
(comment "c_mem_type = 0 ")
(comment "c_has_qdpo_rst = false ")
(comment "InstanceName = romo_xil ")
(comment "c_has_qspo = true ")
(comment "c_has_qspo_rst = false ")
(comment "c_family = spartan3 ")
(comment "c_has_dpo = false ")
(comment "c_has_qdpo_clk = false ")
(comment "c_has_d = false ")
(comment "c_qce_joined = false ")
(comment "c_width = 14 ")
(comment "c_reg_a_d_inputs = false ")
(comment "c_latency = 1 ")
(comment "c_has_spo = false ")
(comment "c_has_we = false ")
(comment "c_depth = 64 ")
(comment "c_has_i_ce = false ")
(comment "c_default_data_radix = 2 ")
(comment "c_default_data = 0 ")
(comment "c_has_dpra = false ")
(comment "c_has_clk = true ")
(comment "c_enable_rlocs = true ")
(comment "c_generate_mif = true ")
(comment "c_has_qspo_ce = false ")
(comment "c_addr_width = 6 ")
(comment "c_has_qdpo_srst = false ")
(comment "c_mux_type = 0 ")
(comment "c_has_spra = false ")
(comment "c_has_qdpo = false ")
(comment "c_mem_init_file = romo_xil.mif ")
(comment "c_reg_dpra_input = false ")
(comment "c_has_qspo_srst = false ")
(comment "c_has_rd_en = false ")
(comment "c_read_mif = true ")
(comment "c_sync_enable = 0 ")
(comment "c_has_qdpo_ce = false ")
(external xilinxun (edifLevel 0)
(technology (numberDefinition))
(cell VCC (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
(cell GND (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port G (direction OUTPUT))
)
)
)
(cell FDE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell LUT4 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXF5 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXF6 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
)
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell romo_xil
(cellType GENERIC) (view view_1 (viewType NETLIST)
(interface
(port ( array ( rename A "A(5:0)") 6 ) (direction INPUT))
(port ( rename CLK "CLK") (direction INPUT))
(port ( array ( rename QSPO "QSPO(13:0)") 14 ) (direction OUTPUT))
)
(contents
(instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun))))
(instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun))))
(instance BU11
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y1"))
(property INIT (string "0ff0"))
)
(instance BU12
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y1"))
(property INIT (string "33cc"))
)
(instance BU13
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y1"))
)
(instance BU14
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
(property INIT (string "5a5a"))
)
(instance BU15
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
(property INIT (string "6666"))
)
(instance BU16
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
)
(instance BU17
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
)
(instance BU19
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y0"))
)
(instance BU24
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y3"))
(property INIT (string "cc3c"))
)
(instance BU25
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y3"))
(property INIT (string "5566"))
)
(instance BU26
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y3"))
)
(instance BU27
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
(property INIT (string "05fa"))
)
(instance BU28
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
(property INIT (string "1e1e"))
)
(instance BU29
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
)
(instance BU30
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
)
(instance BU32
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y2"))
)
(instance BU37
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y5"))
(property INIT (string "0030"))
)
(instance BU38
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y5"))
(property INIT (string "ffee"))
)
(instance BU39
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y5"))
)
(instance BU40
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
(property INIT (string "00fa"))
)
(instance BU41
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
(property INIT (string "fefe"))
)
(instance BU42
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
)
(instance BU43
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
)
(instance BU45
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y4"))
)
(instance BU50
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y7"))
(property INIT (string "0fc0"))
)
(instance BU51
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y7"))
(property INIT (string "cc22"))
)
(instance BU52
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y7"))
)
(instance BU53
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
(property INIT (string "5aa0"))
)
(instance BU54
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
(property INIT (string "9898"))
)
(instance BU55
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
)
(instance BU56
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
)
(instance BU58
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y6"))
)
(instance BU63
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y9"))
(property INIT (string "6966"))
)
(instance BU64
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y9"))
(property INIT (string "5a78"))
)
(instance BU65
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y9"))
)
(instance BU66
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
(property INIT (string "93cc"))
)
(instance BU67
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
(property INIT (string "1fe0"))
)
(instance BU68
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
)
(instance BU69
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
)
(instance BU71
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y8"))
)
(instance BU76
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y11"))
(property INIT (string "42b4"))
)
(instance BU77
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y11"))
(property INIT (string "63bc"))
)
(instance BU78
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y11"))
)
(instance BU79
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
(property INIT (string "495a"))
)
(instance BU80
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
(property INIT (string "8666"))
)
(instance BU81
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
)
(instance BU82
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
)
(instance BU84
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y10"))
)
(instance BU89
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y13"))
(property INIT (string "4f04"))
)
(instance BU90
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y13"))
(property INIT (string "8c30"))
)
(instance BU91
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y13"))
)
(instance BU92
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
(property INIT (string "a1a0"))
)
(instance BU93
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
(property INIT (string "e888"))
)
(instance BU94
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
)
(instance BU95
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
)
(instance BU97
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y12"))
)
(instance BU102
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y15"))
(property INIT (string "d992"))
)
(instance BU103
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y15"))
(property INIT (string "a56a"))
)
(instance BU104
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y15"))
)
(instance BU105
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
(property INIT (string "9866"))
)
(instance BU106
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
(property INIT (string "c33c"))
)
(instance BU107
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
)
(instance BU108
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
)
(instance BU110
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y14"))
)
(instance BU115
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y17"))
(property INIT (string "0b42"))
)
(instance BU116
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y17"))
(property INIT (string "502a"))
)
(instance BU117
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y17"))
)
(instance BU118
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
(property INIT (string "2244"))
)
(instance BU119
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
(property INIT (string "f330"))
)
(instance BU120
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
)
(instance BU121
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
)
(instance BU123
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y16"))
)
(instance BU128
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y19"))
(property INIT (string "5158"))
)
(instance BU129
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y19"))
(property INIT (string "0fda"))
)
(instance BU130
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y19"))
)
(instance BU131
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
(property INIT (string "6622"))
)
(instance BU132
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
(property INIT (string "c0fc"))
)
(instance BU133
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
)
(instance BU134
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
)
(instance BU136
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y18"))
)
(instance BU141
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y21"))
(property INIT (string "9d9c"))
)
(instance BU142
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y21"))
(property INIT (string "5550"))
)
(instance BU143
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y21"))
)
(instance BU144
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
(property INIT (string "dd22"))
)
(instance BU145
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
(property INIT (string "300c"))
)
(instance BU146
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
)
(instance BU147
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
)
(instance BU149
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y20"))
)
(instance BU154
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y23"))
(property INIT (string "1ee0"))
)
(instance BU155
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y23"))
(property INIT (string "cc36"))
)
(instance BU156
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y23"))
)
(instance BU157
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
(property INIT (string "5a78"))
)
(instance BU158
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
(property INIT (string "969a"))
)
(instance BU159
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
)
(instance BU160
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
)
(instance BU162
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y22"))
)
(instance BU167
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y25"))
(property INIT (string "e000"))
)
(instance BU168
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y25"))
(property INIT (string "ccfe"))
)
(instance BU169
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y25"))
)
(instance BU170
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
(property INIT (string "5070"))
)
(instance BU171
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
(property INIT (string "b2ba"))
)
(instance BU172
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
)
(instance BU173
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
)
(instance BU175
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y24"))
)
(instance BU180
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y27"))
(property INIT (string "0000"))
)
(instance BU181
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y27"))
(property INIT (string "ccfe"))
)
(instance BU182
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y27"))
)
(instance BU183
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
(property INIT (string "5070"))
)
(instance BU184
(viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
(property INIT (string "b2ba"))
)
(instance BU185
(viewRef view_1 (cellRef MUXF5 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
)
(instance BU186
(viewRef view_1 (cellRef MUXF6 (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
)
(instance BU188
(viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
(property RLOC (string "x0y26"))
)
(net N1
(joined
(portRef P (instanceRef VCC))
(portRef CE (instanceRef BU19))
(portRef CE (instanceRef BU32))
(portRef CE (instanceRef BU45))
(portRef CE (instanceRef BU58))
(portRef CE (instanceRef BU71))
(portRef CE (instanceRef BU84))
(portRef CE (instanceRef BU97))
(portRef CE (instanceRef BU110))
(portRef CE (instanceRef BU123))
(portRef CE (instanceRef BU136))
(portRef CE (instanceRef BU149))
(portRef CE (instanceRef BU162))
(portRef CE (instanceRef BU175))
(portRef CE (instanceRef BU188))
)
)
(net (rename N2 "A(0)")
(joined
(portRef (member A 5))
(portRef I0 (instanceRef BU11))
(portRef I0 (instanceRef BU12))
(portRef I0 (instanceRef BU14))
(portRef I0 (instanceRef BU15))
(portRef I0 (instanceRef BU24))
(portRef I0 (instanceRef BU25))
(portRef I0 (instanceRef BU27))
(portRef I0 (instanceRef BU28))
(portRef I0 (instanceRef BU37))
(portRef I0 (instanceRef BU38))
(portRef I0 (instanceRef BU40))
(portRef I0 (instanceRef BU41))
(portRef I0 (instanceRef BU50))
(portRef I0 (instanceRef BU51))
(portRef I0 (instanceRef BU53))
(portRef I0 (instanceRef BU54))
(portRef I0 (instanceRef BU63))
(portRef I0 (instanceRef BU64))
(portRef I0 (instanceRef BU66))
(portRef I0 (instanceRef BU67))
(portRef I0 (instanceRef BU76))
(portRef I0 (instanceRef BU77))
(portRef I0 (instanceRef BU79))
(portRef I0 (instanceRef BU80))
(portRef I0 (instanceRef BU89))
(portRef I0 (instanceRef BU90))
(portRef I0 (instanceRef BU92))
(portRef I0 (instanceRef BU93))
(portRef I0 (instanceRef BU102))
(portRef I0 (instanceRef BU103))
(portRef I0 (instanceRef BU105))
(portRef I0 (instanceRef BU106))
(portRef I0 (instanceRef BU115))
(portRef I0 (instanceRef BU116))
(portRef I0 (instanceRef BU118))
(portRef I0 (instanceRef BU119))
(portRef I0 (instanceRef BU128))
(portRef I0 (instanceRef BU129))
(portRef I0 (instanceRef BU131))
(portRef I0 (instanceRef BU132))
(portRef I0 (instanceRef BU141))
(portRef I0 (instanceRef BU142))
(portRef I0 (instanceRef BU144))
(portRef I0 (instanceRef BU145))
(portRef I0 (instanceRef BU154))
(portRef I0 (instanceRef BU155))
(portRef I0 (instanceRef BU157))
(portRef I0 (instanceRef BU158))
(portRef I0 (instanceRef BU167))
(portRef I0 (instanceRef BU168))
(portRef I0 (instanceRef BU170))
(portRef I0 (instanceRef BU171))
(portRef I0 (instanceRef BU180))
(portRef I0 (instanceRef BU181))
(portRef I0 (instanceRef BU183))
(portRef I0 (instanceRef BU184))
)
)
(net (rename N3 "A(1)")
(joined
(portRef (member A 4))
(portRef I1 (instanceRef BU11))
(portRef I1 (instanceRef BU12))
(portRef I1 (instanceRef BU14))
(portRef I1 (instanceRef BU15))
(portRef I1 (instanceRef BU24))
(portRef I1 (instanceRef BU25))
(portRef I1 (instanceRef BU27))
(portRef I1 (instanceRef BU28))
(portRef I1 (instanceRef BU37))
(portRef I1 (instanceRef BU38))
(portRef I1 (instanceRef BU40))
(portRef I1 (instanceRef BU41))
(portRef I1 (instanceRef BU50))
(portRef I1 (instanceRef BU51))
(portRef I1 (instanceRef BU53))
(portRef I1 (instanceRef BU54))
(portRef I1 (instanceRef BU63))
(portRef I1 (instanceRef BU64))
(portRef I1 (instanceRef BU66))
(portRef I1 (instanceRef BU67))
(portRef I1 (instanceRef BU76))
(portRef I1 (instanceRef BU77))
(portRef I1 (instanceRef BU79))
(portRef I1 (instanceRef BU80))
(portRef I1 (instanceRef BU89))
(portRef I1 (instanceRef BU90))
(portRef I1 (instanceRef BU92))
(portRef I1 (instanceRef BU93))
(portRef I1 (instanceRef BU102))
(portRef I1 (instanceRef BU103))
(portRef I1 (instanceRef BU105))
(portRef I1 (instanceRef BU106))
(portRef I1 (instanceRef BU115))
(portRef I1 (instanceRef BU116))
(portRef I1 (instanceRef BU118))
(portRef I1 (instanceRef BU119))
(portRef I1 (instanceRef BU128))
(portRef I1 (instanceRef BU129))
(portRef I1 (instanceRef BU131))
(portRef I1 (instanceRef BU132))
(portRef I1 (instanceRef BU141))
(portRef I1 (instanceRef BU142))
(portRef I1 (instanceRef BU144))
(portRef I1 (instanceRef BU145))
(portRef I1 (instanceRef BU154))
(portRef I1 (instanceRef BU155))
(portRef I1 (instanceRef BU157))
(portRef I1 (instanceRef BU158))
(portRef I1 (instanceRef BU167))
(portRef I1 (instanceRef BU168))
(portRef I1 (instanceRef BU170))
(portRef I1 (instanceRef BU171))
(portRef I1 (instanceRef BU180))
(portRef I1 (instanceRef BU181))
(portRef I1 (instanceRef BU183))
(portRef I1 (instanceRef BU184))
)
)
(net (rename N4 "A(2)")
(joined
(portRef (member A 3))
(portRef I2 (instanceRef BU11))
(portRef I2 (instanceRef BU12))
(portRef I2 (instanceRef BU14))
(portRef I2 (instanceRef BU15))
(portRef I2 (instanceRef BU24))
(portRef I2 (instanceRef BU25))
(portRef I2 (instanceRef BU27))
(portRef I2 (instanceRef BU28))
(portRef I2 (instanceRef BU37))
(portRef I2 (instanceRef BU38))
(portRef I2 (instanceRef BU40))
(portRef I2 (instanceRef BU41))
(portRef I2 (instanceRef BU50))
(portRef I2 (instanceRef BU51))
(portRef I2 (instanceRef BU53))
(portRef I2 (instanceRef BU54))
(portRef I2 (instanceRef BU63))
(portRef I2 (instanceRef BU64))
(portRef I2 (instanceRef BU66))
(portRef I2 (instanceRef BU67))
(portRef I2 (instanceRef BU76))
(portRef I2 (instanceRef BU77))
(portRef I2 (instanceRef BU79))
(portRef I2 (instanceRef BU80))
(portRef I2 (instanceRef BU89))
(portRef I2 (instanceRef BU90))
(portRef I2 (instanceRef BU92))
(portRef I2 (instanceRef BU93))
(portRef I2 (instanceRef BU102))
(portRef I2 (instanceRef BU103))
(portRef I2 (instanceRef BU105))
(portRef I2 (instanceRef BU106))
(portRef I2 (instanceRef BU115))
(portRef I2 (instanceRef BU116))
(portRef I2 (instanceRef BU118))
(portRef I2 (instanceRef BU119))
(portRef I2 (instanceRef BU128))
(portRef I2 (instanceRef BU129))
(portRef I2 (instanceRef BU131))
(portRef I2 (instanceRef BU132))
(portRef I2 (instanceRef BU141))
(portRef I2 (instanceRef BU142))
(portRef I2 (instanceRef BU144))
(portRef I2 (instanceRef BU145))
(portRef I2 (instanceRef BU154))
(portRef I2 (instanceRef BU155))
(portRef I2 (instanceRef BU157))
(portRef I2 (instanceRef BU158))
(portRef I2 (instanceRef BU167))
(portRef I2 (instanceRef BU168))
(portRef I2 (instanceRef BU170))
(portRef I2 (instanceRef BU171))
(portRef I2 (instanceRef BU180))
(portRef I2 (instanceRef BU181))
(portRef I2 (instanceRef BU183))
(portRef I2 (instanceRef BU184))
)
)
(net (rename N5 "A(3)")
(joined
(portRef (member A 2))
(portRef I3 (instanceRef BU11))
(portRef I3 (instanceRef BU12))
(portRef I3 (instanceRef BU14))
(portRef I3 (instanceRef BU15))
(portRef I3 (instanceRef BU24))
(portRef I3 (instanceRef BU25))
(portRef I3 (instanceRef BU27))
(portRef I3 (instanceRef BU28))
(portRef I3 (instanceRef BU37))
(portRef I3 (instanceRef BU38))
(portRef I3 (instanceRef BU40))
(portRef I3 (instanceRef BU41))
(portRef I3 (instanceRef BU50))
(portRef I3 (instanceRef BU51))
(portRef I3 (instanceRef BU53))
(portRef I3 (instanceRef BU54))
(portRef I3 (instanceRef BU63))
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(portRef I3 (instanceRef BU66))
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(portRef I3 (instanceRef BU106))
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(portRef I3 (instanceRef BU116))
(portRef I3 (instanceRef BU118))
(portRef I3 (instanceRef BU119))
(portRef I3 (instanceRef BU128))
(portRef I3 (instanceRef BU129))
(portRef I3 (instanceRef BU131))
(portRef I3 (instanceRef BU132))
(portRef I3 (instanceRef BU141))
(portRef I3 (instanceRef BU142))
(portRef I3 (instanceRef BU144))
(portRef I3 (instanceRef BU145))
(portRef I3 (instanceRef BU154))
(portRef I3 (instanceRef BU155))
(portRef I3 (instanceRef BU157))
(portRef I3 (instanceRef BU158))
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(portRef I3 (instanceRef BU168))
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(portRef I3 (instanceRef BU171))
(portRef I3 (instanceRef BU180))
(portRef I3 (instanceRef BU181))
(portRef I3 (instanceRef BU183))
(portRef I3 (instanceRef BU184))
)
)
(net (rename N6 "A(4)")
(joined
(portRef (member A 1))
(portRef S (instanceRef BU13))
(portRef S (instanceRef BU16))
(portRef S (instanceRef BU26))
(portRef S (instanceRef BU29))
(portRef S (instanceRef BU39))
(portRef S (instanceRef BU42))
(portRef S (instanceRef BU52))
(portRef S (instanceRef BU55))
(portRef S (instanceRef BU65))
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(portRef S (instanceRef BU94))
(portRef S (instanceRef BU104))
(portRef S (instanceRef BU107))
(portRef S (instanceRef BU117))
(portRef S (instanceRef BU120))
(portRef S (instanceRef BU130))
(portRef S (instanceRef BU133))
(portRef S (instanceRef BU143))
(portRef S (instanceRef BU146))
(portRef S (instanceRef BU156))
(portRef S (instanceRef BU159))
(portRef S (instanceRef BU169))
(portRef S (instanceRef BU172))
(portRef S (instanceRef BU182))
(portRef S (instanceRef BU185))
)
)
(net (rename N7 "A(5)")
(joined
(portRef (member A 0))
(portRef S (instanceRef BU17))
(portRef S (instanceRef BU30))
(portRef S (instanceRef BU43))
(portRef S (instanceRef BU56))
(portRef S (instanceRef BU69))
(portRef S (instanceRef BU82))
(portRef S (instanceRef BU95))
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(portRef S (instanceRef BU134))
(portRef S (instanceRef BU147))
(portRef S (instanceRef BU160))
(portRef S (instanceRef BU173))
(portRef S (instanceRef BU186))
)
)
(net (rename N8 "CLK")
(joined
(portRef CLK)
(portRef C (instanceRef BU19))
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)
)
(net (rename N9 "QSPO(0)")
(joined
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)
)
(net (rename N10 "QSPO(1)")
(joined
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)
)
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(joined
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)
)
(net (rename N12 "QSPO(3)")
(joined
(portRef (member QSPO 10))
(portRef Q (instanceRef BU58))
)
)
(net (rename N13 "QSPO(4)")
(joined
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)
)
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(joined
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)
)
(net (rename N15 "QSPO(6)")
(joined
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)
)
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)
)
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)
)
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(joined
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)
)
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(joined
(portRef (member QSPO 3))
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)
)
(net (rename N20 "QSPO(11)")
(joined
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)
)
(net (rename N21 "QSPO(12)")
(joined
(portRef (member QSPO 1))
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)
)
(net (rename N22 "QSPO(13)")
(joined
(portRef (member QSPO 0))
(portRef Q (instanceRef BU188))
)
)
(net N70
(joined
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)
)
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)
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)
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)
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)
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)
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)
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)
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)
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)
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)
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)
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)
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)
)
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)
)
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)
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)
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)
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)
)
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)
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)
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)
)
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)
)
(net N118
(joined
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)
)
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)
)
(net N120
(joined
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)
)
(net N121
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)
)
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)
)
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)
)
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)
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)
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)
)
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)
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)
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)
)
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)
)
(net N135
(joined
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)
)
(net N136
(joined
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)
)
(net N137
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)
)
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)
)
(net N141
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)
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)
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)
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)
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)
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)
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)
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)
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)
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)
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)
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)
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(net N170
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(net N173
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(joined
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)
)
(net N175
(joined
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(net N176
(joined
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(net N177
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(net N181
(joined
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(net N182
(joined
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(net N183
(joined
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)
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(net N184
(joined
(portRef O (instanceRef BU168))
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)
)
(net N185
(joined
(portRef O (instanceRef BU170))
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)
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(net N186
(joined
(portRef O (instanceRef BU171))
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)
)
(net N189
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)
)
(net N190
(joined
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)
)
(net N191
(joined
(portRef O (instanceRef BU180))
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)
)
(net N192
(joined
(portRef O (instanceRef BU181))
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)
)
(net N193
(joined
(portRef O (instanceRef BU183))
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)
)
(net N194
(joined
(portRef O (instanceRef BU184))
(portRef I1 (instanceRef BU185))
)
)
))))
(design romo_xil (cellRef romo_xil (libraryRef test_lib))
(property X_CORE_INFO (string "C_DIST_MEM_V7_1, Coregen 6.3i"))
(property PART (string "XC3S5000-4-fg900") (owner "Xilinx")))
)
/trunk/source/xilinx/rome_xil.vhd
0,0 → 1,107
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2004 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file rome_xil.vhd when simulating
-- the core, rome_xil. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".
 
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
Library XilinxCoreLib;
ENTITY rome_xil IS
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
END rome_xil;
 
ARCHITECTURE rome_xil_a OF rome_xil IS
 
component wrapped_rome_xil
port (
A: IN std_logic_VECTOR(5 downto 0);
CLK: IN std_logic;
QSPO: OUT std_logic_VECTOR(13 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_rome_xil use entity XilinxCoreLib.C_DIST_MEM_V7_1(behavioral)
generic map(
c_qualify_we => 0,
c_mem_type => 0,
c_has_qdpo_rst => 0,
c_has_qspo => 1,
c_has_qspo_rst => 0,
c_has_dpo => 0,
c_has_qdpo_clk => 0,
c_has_d => 0,
c_qce_joined => 0,
c_width => 14,
c_reg_a_d_inputs => 0,
c_latency => 1,
c_has_we => 0,
c_has_spo => 0,
c_depth => 64,
c_has_i_ce => 0,
c_default_data => "0",
c_default_data_radix => 2,
c_has_dpra => 0,
c_has_clk => 1,
c_enable_rlocs => 1,
c_generate_mif => 1,
c_addr_width => 6,
c_has_qspo_ce => 0,
c_has_qdpo_srst => 0,
c_mux_type => 0,
c_has_spra => 0,
c_has_qdpo => 0,
c_mem_init_file => "c:/elektronika/dct/mdct/source/xilinx/rome_xil.mif",
c_reg_dpra_input => 0,
c_has_rd_en => 0,
c_has_qspo_srst => 0,
c_read_mif => 1,
c_sync_enable => 0,
c_has_qdpo_ce => 0);
BEGIN
 
U0 : wrapped_rome_xil
port map (
A => A,
CLK => CLK,
QSPO => QSPO);
END rome_xil_a;
 
-- synopsys translate_on
 
/trunk/source/ROMO.VHD
31,7 → 31,8
 
entity ROMO is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
111,14 → 112,17
std_logic_vector( GP+FM+EP ),
std_logic_vector( GP+FM+EP+DM )
);
 
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
-------------------------------------------------------------------------------
rom_proc: -- ROM generator process
-------------------------------------------------------------------------------
process( addr )
datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) );
process(clk)
begin
datao <= rom( TO_INTEGER(UNSIGNED(addr)) );
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
/trunk/DOC/mdct_spec.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/mdct.mpf
531,51 → 531,61
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 17
Project_Files_Count = 21
Project_File_0 = C:/elektronika/dct/mdct/source/ROME.VHD
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144870599 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144870599 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_1 = C:/elektronika/dct/MDCT/source/DBUFCTL.VHD
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143785621 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143785621 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_2 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.DO
Project_File_P_2 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_3 = C:/elektronika/dct/mdct/source/testbench/RUNSIM.DO
Project_File_P_3 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_4 = C:/elektronika/dct/MDCT/source/testbench/COMPILE_TIMING.DO
Project_File_P_4 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_5 = C:/elektronika/dct/mdct/source/RAM.VHD
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143489389 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_6 = C:/elektronika/dct/MDCT/source/DCT2D.VHD
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143972066 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 87
Project_File_7 = C:/elektronika/dct/mdct/source/testbench/CLKGEN.VHD
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143489388 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_8 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.VHD
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1144881653 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_9 = C:/elektronika/dct/MDCT/synthesis/mdct_temp_2/MDCT_out.vhd
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_10 = C:/elektronika/dct/MDCT/source/testbench/RUNSIM_TIMING.DO
Project_File_P_10 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
Project_File_11 = C:/elektronika/dct/mdct/source/ROMO.VHD
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144946089 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_12 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_13 = C:/elektronika/dct/mdct/source/MDCT.VHD
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_14 = C:/elektronika/dct/mdct/source/DCT1D.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_15 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_16 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_P_2 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_3 = C:/elektronika/dct/MDCT/source/xilinx/ROME.VHD
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_4 = C:/elektronika/dct/mdct/source/testbench/RUNSIM.DO
Project_File_P_4 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_5 = C:/elektronika/dct/MDCT/source/testbench/COMPILE_TIMING.DO
Project_File_P_5 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_6 = C:/elektronika/dct/mdct/source/RAM.VHD
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143489389 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_7 = C:/elektronika/dct/MDCT/source/DCT2D.VHD
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143972066 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 87
Project_File_8 = C:/elektronika/dct/mdct/source/testbench/CLKGEN.VHD
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143489388 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_9 = C:/elektronika/dct/MDCT/source/xilinx/romo_xil.vhd
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_10 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.VHD
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1144881653 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_11 = C:/elektronika/dct/MDCT/synthesis/mdct_temp_2/MDCT_out.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_12 = C:/elektronika/dct/MDCT/source/testbench/RUNSIM_TIMING.DO
Project_File_P_12 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
Project_File_13 = C:/elektronika/dct/mdct/source/ROMO.VHD
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145568090 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_14 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_15 = C:/elektronika/dct/MDCT/source/xilinx/ROMO.VHD
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_16 = C:/elektronika/dct/mdct/source/MDCT.VHD
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_17 = C:/elektronika/dct/mdct/source/DCT1D.vhd
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_18 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_19 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 93
Project_File_20 = C:/elektronika/dct/MDCT/source/xilinx/rome_xil.vhd
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 4
Project_Folder_0 = TESTBENCH
Project_Folder_Count = 5
Project_Folder_0 = XILINX
Project_Folder_P_0 = folder SOURCE
Project_Folder_1 = SOURCE
Project_Folder_P_1 = folder {Top Level}
Project_Folder_2 = MODELSIM
Project_Folder_1 = TESTBENCH
Project_Folder_P_1 = folder SOURCE
Project_Folder_2 = SOURCE
Project_Folder_P_2 = folder {Top Level}
Project_Folder_3 = PAR
Project_Folder_3 = MODELSIM
Project_Folder_P_3 = folder {Top Level}
Project_Folder_4 = PAR
Project_Folder_P_4 = folder {Top Level}
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
603,6 → 613,6
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/MDCT_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT2D.VHD 0 1} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/ROMO.VHD 0 0} {C:/elektronika/dct/MDCT/source/ROME.VHD 0 0}
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/MDCT_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT2D.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/INPIMAGE.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCT_TB.DO 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1

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