URL
https://opencores.org/ocsvn/microriscii/microriscii/trunk
Subversion Repositories microriscii
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- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/trunk/verilog/rtl/au.v
27,14 → 27,12
`define ALU_PCNTC 4'b1110 |
`define ALU_RND 4'b1111 |
|
module au(a,b,clk,arith_op,carry,o,rndin); |
module au(a,b,arith_op,carry,o,rndin); |
// Inputs |
input [31:0] a; |
wire [31:0] a; |
input [31:0] b; |
wire [31:0] b; |
input clk; |
wire clk; |
input [3:0] arith_op; |
wire [3:0] arith_op; |
input [31:0] rndin; |
91,9 → 89,7
a_chg[0] = a[1] ^^ a[0]; |
end |
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// TODO |
// always @ (posedge clk) |
// rnd = rndin; |
// TODO: Random Number Generator |
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always @ (arith_op || a || b) // Main Operation |
case (arith_op) |
147,8 → 143,6
end |
`ALU_RND : // Random |
o = rnd; |
default : // BAD NEWS |
o = 8'h4655434B; // Random data for have fun ;) |
endcase |
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function [5:0] PopCntO4; // One Count |
/trunk/documentation/ISA.txt
1,5 → 1,23
The encoding info is scattered in the source I'm gonna organize it all soon. |
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Registers: |
0000: $SP - Stack Pointer |
0001: $GP - Global Pointer |
0010: $RA - Return Address |
0011: $SYS - System |
0100: $R0 - General Purpose Registers |
0101: $R1 |
0110: $R2 |
0111: $R3 |
1000: $R4 |
1001: $R5 |
1010: $R6 |
1011: $R7 |
1100: $T0 - Temporary Registers |
1101: $T1 |
1110: $T2 |
1111: $T3 |
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MicroRISC II Instruction Set |
|
Arithmetic: |
19,7 → 37,9
Arguments: reg,reg,reg |
Arguments: reg,reg,imm16 |
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0100: |
| OP(4) | ALUOP(4) | REGD(4) | REGA(4) | REGB(4) | VOID(12) | |
0101: |
| OP(4) | ALUOP(4) | REGD(4) | REGA(4) | IMM(16) | |
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Logic: |
29,7 → 49,10
NOT |
Arguments: reg,reg,reg |
|
0010: |
| OP(4) | LOGICOP(2) | VOID(2) | REGD(4) | REGA(4) | REGB(4) | VOID(12) | |
0011: |
| OP(4) | LOGICOP(2) | HIGH/LOW(1) | VOID(1) | REGD(4) | REGA(4) | VOID(16) | |
|
Memory: |
LB/LW/LD(S) |
36,17 → 59,18
SB/SW/SD |
Arguments: reg,[reg+imm16] |
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0001: |
| OP(4) | STORE/LOAD(1) | SIGNED(1) | SIZE(2) | REGD(4) | REGA(4) | IMM(16) | |
|
Branch: |
BEQ(L) |
BNE(L) |
BZ(L) |
BNZ(L) |
BC(L) |
BNC(L) |
J(L) |
JR(L) |
J(L) 1000 |
JR(L) 1001 |
BEQ(L) 1010 |
BNE(L) 1011 |
BZ(L) 1100 |
BNZ(L) 1101 |
BC(L) 1110 |
BNC(L) 1111 |
|
| OP(4) | REGD(4) | REGA(4) | REGB(4) | IMM(16) | |
|
59,6 → 83,7
BNG(L) |
BNGU(L) |
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0111: |
| OP(4) | BranchOP(4) | REGD(4) | REGA(4) | REGB(4) | VOID(4) | IMM(8) | |
|
Interupts/Special: |
73,5 → 98,7
IRET reg // Interupt Return |
GPRSR reg // Get Program Restore State Register(Carry,etc.) |
SPRSR reg // Set Program Restore State Register |
SWMC // Switch Microcode Size(16bit/32bit) |
|
0000: |
| OP(4) | SOP(4) | REGD(4) | REGA(4) | IMM(16) | |