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Rev 10 → Rev 11

/trunk/rtl/vhdl/P16C55.vhd
1,7 → 1,7
--
-- PIC16C55 compatible microcontroller core
--
-- Version : 0220
-- Version : 0222
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
73,30 → 73,39
component ROM55
port(
Clk : in std_logic;
A : in std_logic_vector(8 downto 0);
A : in std_logic_vector(ROMAddressWidth - 1 downto 0);
D : out std_logic_vector(11 downto 0)
);
end component;
 
signal Reset_s_n : std_logic;
signal ROM_Addr : std_logic_vector(8 downto 0);
signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);
signal ROM_Data : std_logic_vector(InstructionLength - 1 downto 0);
signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
signal File_CS : std_logic_vector(7 downto 5);
signal RAM_CS : std_logic;
signal TMR_CS : std_logic;
signal File_Rd : std_logic;
signal File_Wr : std_logic;
signal Tris_Rd : std_logic;
signal W_Wr : std_logic;
signal Tris_A_Wr : std_logic;
signal Tris_B_Wr : std_logic;
signal Tris_C_Wr : std_logic;
signal RAM_Data : std_logic_vector(7 downto 0);
signal Port_A_Wr : std_logic;
signal Port_B_Wr : std_logic;
signal Port_C_Wr : std_logic;
signal Op_Bus : std_logic_vector(7 downto 0);
signal Op_Mux : std_logic_vector(7 downto 0);
signal Res_Bus : std_logic_vector(7 downto 0);
signal RAM_Data : std_logic_vector(7 downto 0);
signal OPTION : std_logic_vector(5 downto 0);
signal PortA : std_logic_vector(7 downto 0);
signal PortB : std_logic_vector(7 downto 0);
signal PortC : std_logic_vector(7 downto 0);
signal TMR : std_logic_vector(7 downto 0);
signal W : std_logic_vector(7 downto 0);
signal STATUS : std_logic_vector(7 downto 0);
signal FSR : std_logic_vector(7 downto 0);
signal Int_Trig : std_logic;
signal GIE : std_logic;
 
127,18 → 136,47
end generate;
 
-- Address decoder
Tris_Rd <= '0';
RAM_CS <= '1' when File_Addr_r(4 downto 3) /= "00" else '0';
TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 1 else '0';
Tris_A_Wr <= '1' when Instruction(11 downto 0) = "000000000101" else '0';
Tris_B_Wr <= '1' when Instruction(11 downto 0) = "000000000110" else '0';
Tris_C_Wr <= '1' when Instruction(11 downto 0) = "000000000111" else '0';
File_CS(5) <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 5 else '0';
File_CS(6) <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 6 else '0';
File_CS(7) <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 7 else '0';
Port_A_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 5 and File_Wr = '1' else '0';
Port_B_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 6 and File_Wr = '1' else '0';
Port_C_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 7 and File_Wr = '1' else '0';
 
-- Register selector
process (Clk)
begin
if Clk'event and Clk = '1' then
case to_integer(unsigned(File_Addr(4 downto 0))) is
when 1 => Op_Bus <= TMR;
when 2 => Op_Bus <= ROM_Addr(7 downto 0);
when 3 => Op_Bus <= STATUS;
when 4 => Op_Bus <= FSR;
when 5 => Op_Bus <= PortA;
when 6 => Op_Bus <= PortB;
when 7 => Op_Bus <= PortC;
when others => Op_Bus <= "--------";
end case;
if File_Wr = '1' and File_Addr_r = File_Addr then
-- Write through
Op_Bus <= Res_Bus;
end if;
RAM_CS <= '0';
if ROM_Data(InstructionLength - 1) = '1' then
Op_Bus <= W;
-- Write through
if W_Wr = '1' then
Op_Bus <= Res_Bus;
end if;
elsif File_Addr(4 downto 3) /= "00" then
RAM_CS <= '1';
end if;
end if;
end process;
 
-- Register File
Op_Bus <= RAM_Data when RAM_CS = '1' and File_Rd = '1' ELSE "ZZZZZZZZ";
Op_Mux <= RAM_Data when RAM_CS = '1' else Op_Bus;
pr : PPX_RAM
generic map(Bottom => 8, Top => 31, AddrWidth => 5)
port map(
179,10 → 217,13
GIE => GIE,
File_Addr => File_Addr,
File_Addr_r => File_Addr_r,
File_Rd => File_Rd,
File_Wr => File_Wr,
W_Wr => W_Wr,
Instruction => Instruction,
Op_Bus => Op_Bus,
Op_Bus => Op_Mux,
W => W,
STATUS => STATUS,
FSR => FSR,
Res_Bus => Res_Bus);
 
tmr0 : PPX_TMR port map(
194,45 → 235,35
PS => OPTION(2 downto 0),
PSA => OPTION(3),
TMR_Sel => TMR_CS,
Rd => File_Rd,
Wr => File_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus);
Data_Out => TMR);
 
porta : PPX_Port port map(
aport : PPX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(5),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_Rd,
Port_Wr => Port_A_Wr,
Tris_Wr => Tris_A_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Port_In => PortA,
IOPort => Port_A);
 
portb : PPX_Port port map(
bport : PPX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(6),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_Rd,
Port_Wr => Port_B_Wr,
Tris_Wr => Tris_B_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Port_In => PortB,
IOPort => Port_B);
 
portc : PPX_Port port map(
cport : PPX_Port port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(7),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_Rd,
Port_Wr => Port_C_Wr,
Tris_Wr => Tris_C_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Port_In => PortC,
IOPort => Port_C);
 
end;
/trunk/rtl/vhdl/PPX_Pack.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0221
-- Version : 0222
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
59,7 → 59,7
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Q : inout std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
Skip : in std_logic;
Carry : in std_logic;
Z_Skip : out std_logic;
73,12 → 73,14
InstructionLength : integer
);
port(
Clk : in std_logic;
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
Inst : in std_logic_vector(InstructionLength - 1 downto 0);
File_Rd : out std_logic;
Skip : in std_logic;
File_Wr : out std_logic;
W_Wr : out std_logic;
W_Rd : out std_logic;
Imm_Op : out std_logic;
A2Res : out std_logic;
B2Res : out std_logic;
Push : out std_logic;
Pop : out std_logic;
99,10 → 101,8
Clk : in std_logic;
Reset_n : in std_logic;
CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
PCLATH : in std_logic_vector(4 downto 0);
STATUS : in std_logic_vector(6 downto 5);
133,11 → 133,15
Int_Ret : out std_logic;
File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
File_Rd : out std_logic;
File_Wr : out std_logic;
W_Wr : out std_logic;
Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
Op_Bus : inout std_logic_vector(7 downto 0);
Res_Bus : inout std_logic_vector(7 downto 0)
Op_Bus : in std_logic_vector(7 downto 0);
W : out std_logic_vector(7 downto 0);
STATUS : out std_logic_vector(7 downto 0);
FSR : out std_logic_vector(7 downto 0);
PCLATH : out std_logic_vector(4 downto 0);
Res_Bus : out std_logic_vector(7 downto 0)
);
end component;
 
161,13 → 165,11
port(
Clk : in std_logic;
Reset_n : in std_logic;
Port_CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Tris_Rd : in std_logic;
Port_Wr : in std_logic;
Tris_Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Port_In : out std_logic_vector(7 downto 0);
Tris : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end component;
182,7 → 184,6
PS : in std_logic_vector(2 downto 0);
PSA : in std_logic;
TMR_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
/trunk/rtl/vhdl/PPX_RAM.vhd
73,7 → 73,6
signal RAM : RAM_Image;
signal AddrRd : std_logic_vector(AddrWidth - 1 downto 0);
signal AddrWr : std_logic_vector(AddrWidth - 1 downto 0);
signal Tmp_Data : std_logic_vector(7 downto 0);
 
begin
 
90,7 → 89,7
 
Data_Out <= RAM(to_integer(unsigned(AddrRd)))
-- pragma translate_off
when to_integer(unsigned(Addr)) >= Bottom and to_integer(unsigned(Addr)) <= Top else "--------"
when to_integer(unsigned(AddrRd)) >= Bottom and to_integer(unsigned(AddrRd)) <= Top else "--------"
-- pragma translate_on
;
 
/trunk/rtl/vhdl/P16F84.vhd
1,7 → 1,7
--
-- PIC16F84 compatible microcontroller core
--
-- Version : 0220
-- Version : 0222
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
86,20 → 86,29
signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
signal File_CS : std_logic_vector(6 downto 5);
signal TMR_CS : std_logic;
signal RAM_CS : std_logic;
signal File_Rd : std_logic;
signal File_Wr : std_logic;
signal Tris_A_Rd : std_logic;
signal W_Wr : std_logic;
signal Port_A_Wr : std_logic;
signal Tris_A_Wr : std_logic;
signal Tris_B_Rd : std_logic;
signal Port_B_Wr : std_logic;
signal Tris_B_Wr : std_logic;
signal RAM_Data : std_logic_vector(7 downto 0);
signal Op_Bus : std_logic_vector(7 downto 0);
signal Op_Mux : std_logic_vector(7 downto 0);
signal Res_Bus : std_logic_vector(7 downto 0);
signal OPTION : std_logic_vector(7 downto 0);
signal INTCON : std_logic_vector(7 downto 0);
signal PortA : std_logic_vector(7 downto 0);
signal TrisA : std_logic_vector(7 downto 0);
signal PortB : std_logic_vector(7 downto 0);
signal TrisB : std_logic_vector(7 downto 0);
signal TMR : std_logic_vector(7 downto 0);
signal W : std_logic_vector(7 downto 0);
signal STATUS : std_logic_vector(7 downto 0);
signal FSR : std_logic_vector(7 downto 0);
signal PCLATH : std_logic_vector(4 downto 0);
signal Int_Trig : std_logic;
signal Int_Acc : std_logic;
signal Int_Ret : std_logic;
131,19 → 140,51
end generate;
 
-- Address decoder
File_CS(5) <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 5 else '0';
File_CS(6) <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 6 else '0';
Tris_A_Rd <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 133 and File_Rd = '1' else '0';
Tris_B_Rd <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 134 and File_Rd = '1' else '0';
Port_A_Wr <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 5 and File_Wr = '1' else '0';
Port_B_Wr <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 6 and File_Wr = '1' else '0';
Tris_A_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 133 and File_Wr = '1') or
Instruction(13 downto 0) = "00000001100101" else '0';
Tris_B_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 134 and File_Wr = '1') or
Instruction(13 downto 0) = "00000001100110" else '0';
RAM_CS <= '1' when File_Addr_r(6 downto 4) /= "000" or File_Addr_r(3 downto 2) = "11" else '0';
TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 1 else '0';
 
-- Register selector
process (Clk)
begin
if Clk'event and Clk = '1' then
case to_integer(unsigned(File_Addr(7 downto 0))) is
when 1 => Op_Bus <= TMR;
when 129 => Op_Bus <= OPTION;
when 2 | 130 => Op_Bus <= ROM_Addr(7 downto 0);
when 3 | 131 => Op_Bus <= STATUS;
when 4 | 132 => Op_Bus <= FSR;
when 5 => Op_Bus <= PortA;
when 133 => Op_Bus <= TrisA;
when 6 => Op_Bus <= PortB;
when 134 => Op_Bus <= TrisB;
when 10 | 138 => Op_Bus(4 downto 0) <= PCLATH;
when 11 | 139 => Op_Bus <= INTCON;
when others => Op_Bus <= "--------";
end case;
if File_Wr = '1' and File_Addr_r = File_Addr then
-- Write through
Op_Bus <= Res_Bus;
end if;
RAM_CS <= '0';
if ROM_Data(InstructionLength - 1) = '1' then
Op_Bus <= W;
-- Write through
if W_Wr = '1' then
Op_Bus <= Res_Bus;
end if;
elsif File_Addr(6 downto 4) /= "000" or File_Addr(3 downto 2) = "11" then
RAM_CS <= '1';
end if;
end if;
end process;
 
-- Register File
Op_Bus <= RAM_Data when RAM_CS = '1' and File_Rd = '1' else "ZZZZZZZZ";
Op_Mux <= RAM_Data when RAM_CS = '1' else Op_Bus;
pr : PPX_RAM
generic map(Bottom => 12, Top => 79, AddrWidth => 7)
port map(
155,9 → 196,6
Data_Out => RAM_Data);
 
-- Option Register
Op_Bus <= OPTION when
to_integer(unsigned(File_Addr_r(7 downto 0))) = 129 and
File_Rd = '1' else "ZZZZZZZZ";
process (Clk)
begin
if Clk'event and Clk = '1' then
174,15 → 212,12
Int_Trig <= (INTCON(0) and INTCON(3)) or
(INTCON(1) and INTCON(4)) or
(INTCON(2) and INTCON(5));
Op_Bus <= INTCON when
to_integer(unsigned(File_Addr_r(7 downto 0))) = 11 and
File_Rd = '1' else "ZZZZZZZZ";
process (Reset_s_n, Clk)
begin
if Reset_s_n = '0' then
INTCON <= (others => '0');
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_r(7 downto 0))) = 11 then
if to_integer(unsigned(File_Addr_r(6 downto 0))) = 11 then
INTCON <= Res_Bus;
end if;
if Int_Acc = '1' then
189,7 → 224,7
INTCON(7) <= '0';
end if;
if Int_Ret = '1' then
INTCON(7) <= '0';
INTCON(7) <= '1';
end if;
if TOF = '1' then
INTCON(2) <= '1';
226,10 → 261,14
Int_Ret => Int_Ret,
File_Addr => File_Addr,
File_Addr_r => File_Addr_r,
File_Rd => File_Rd,
File_Wr => File_Wr,
W_Wr => W_Wr,
Instruction => Instruction,
Op_Bus => Op_Bus,
Op_Bus => Op_Mux,
W => W,
PCLATH => PCLATH,
STATUS => STATUS,
FSR => FSR,
Res_Bus => Res_Bus);
 
tmr0 : PPX_TMR
242,36 → 281,31
PS => OPTION(2 downto 0),
PSA => OPTION(3),
TMR_Sel => TMR_CS,
Rd => File_Rd,
Wr => File_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Data_Out => TMR,
TOF => TOF);
 
porta : PPX_Port
aport : PPX_Port
port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(5),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_A_Rd,
Port_Wr => Port_A_Wr,
Tris_Wr => Tris_A_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Port_In => PortA,
Tris => TrisA,
IOPort => Port_A);
 
portb : PPX_Port
bport : PPX_Port
port map(
Clk => Clk,
Reset_n => Reset_s_n,
Port_CS => File_CS(6),
Rd => File_Rd,
Wr => File_Wr,
Tris_Rd => Tris_B_Rd,
Port_Wr => Port_B_Wr,
Tris_Wr => Tris_B_Wr,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Port_In => PortB,
Tris => TrisB,
IOPort => Port_B);
 
end;
/trunk/rtl/vhdl/PPX_ALU.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
-- Version : 0222
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
51,7 → 51,8
 
entity PPX_ALU is
generic(
InstructionLength : integer
InstructionLength : integer;
TriState : boolean := false
);
port (
Clk : in std_logic;
58,7 → 59,7
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Q : inout std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
Skip : in std_logic;
Carry : in std_logic;
Z_Skip : out std_logic;
110,8 → 111,7
signal Do_BITSET : std_logic;
signal Do_BITTESTCLR : std_logic;
signal Do_BITTESTSET : std_logic;
signal Do_CLR : std_logic;
signal Do_PASSA : std_logic;
signal Do_CLR : std_logic;
 
signal Inst_Top : std_logic_vector(11 downto 0);
 
118,15 → 118,52
signal Bit_Pattern : std_logic_vector(7 downto 0);
signal Bit_Test : std_logic_vector(7 downto 0);
 
signal IDD : std_logic_vector(7 downto 0);
signal Q_ID : std_logic_vector(7 downto 0);
signal Q_L : std_logic_vector(7 downto 0);
signal Q_C : std_logic_vector(7 downto 0);
signal Q_RR : std_logic_vector(7 downto 0);
signal Q_RL : std_logic_vector(7 downto 0);
signal Q_S : std_logic_vector(7 downto 0);
signal Q_BC : std_logic_vector(7 downto 0);
signal Q_BS : std_logic_vector(7 downto 0);
 
signal DC_i : std_logic;
signal AddSubRes : std_logic_vector(8 downto 0);
 
signal Q_i : std_logic_vector(7 downto 0);
 
begin
 
Q <= Q_i;
 
Inst_Top <= ROM_Data(InstructionLength - 1 downto InstructionLength - 12);
 
gNoTri : if not TriState generate
Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else
AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else
Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else
Q_C when Do_COM = '1' else
Q_RR when Do_RRF = '1' else
Q_RL when Do_RLF = '1' else
Q_S when Do_SWAP = '1' else
Q_BC when Do_BITCLR = '1' else
Q_BS when Do_BITSET = '1' else
"00000000";
end generate;
 
gTri : if TriState generate
Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
Q_i <= AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else "ZZZZZZZZ";
Q_i <= Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else "ZZZZZZZZ";
Q_i <= Q_C when Do_COM = '1' else "ZZZZZZZZ";
Q_i <= Q_RR when Do_RRF = '1' else "ZZZZZZZZ";
Q_i <= Q_RL when Do_RLF = '1' else "ZZZZZZZZ";
Q_i <= Q_S when Do_SWAP = '1' else "ZZZZZZZZ";
Q_i <= Q_BC when Do_BITCLR = '1' else "ZZZZZZZZ";
Q_i <= Q_BS when Do_BITSET = '1' else "ZZZZZZZZ";
Q_i <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
end generate;
 
process (Clk)
begin
if Clk'event and Clk = '1' then
147,7 → 184,6
Do_BITTESTCLR <= '0';
Do_BITTESTSET <= '0';
Do_CLR <= '0';
Do_PASSA <= '0';
if Skip = '0' then
if InstructionLength = 12 then
if Inst_Top(11 downto 6) = "000111" then
241,10 → 277,6
-- CLRF, CLRW
Do_CLR <= '1';
end if;
if Inst_Top(11 downto 6) = "001000" then
-- MOVF
Do_PASSA <= '1';
end if;
end if;
 
case Inst_Top(7 downto 5) is
268,38 → 300,32
end if;
end process;
 
IDD <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
std_logic_vector(unsigned(A) - 1) when Do_DEC = '1' else "ZZZZZZZZ";
Q <= IDD when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
Q_ID <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
std_logic_vector(unsigned(A) - 1);
 
Q <= AddSubRes(7 downto 0) when (Do_ADD = '1' OR Do_SUB = '1') else "ZZZZZZZZ";
AddSub(A(3 downto 0), B(3 downto 0), Do_SUB, Do_SUB, AddSubRes(3 downto 0), DC_i);
AddSub(A(7 downto 4), B(7 downto 4), Do_SUB, DC_i, AddSubRes(7 downto 4), AddSubRes(8));
 
Q <= (A and B) when Do_AND = '1' else
Q_L <= (A and B) when Do_AND = '1' else
(A or B) when Do_OR = '1' else
(A xor B) when Do_XOR = '1' else "ZZZZZZZZ";
Q <= (not A) when Do_COM = '1' else "ZZZZZZZZ";
(A xor B);
Q_C <= (not A);
 
Q <= Carry & A(7 downto 1) when Do_RRF = '1' else "ZZZZZZZZ";
Q <= A(6 downto 0) & Carry when Do_RLF = '1' else "ZZZZZZZZ";
Q_RR <= Carry & A(7 downto 1);
Q_RL <= A(6 downto 0) & Carry;
 
Q <= A(3 downto 0) & A(7 downto 4) when Do_SWAP = '1' else "ZZZZZZZZ";
Q_S <= A(3 downto 0) & A(7 downto 4);
 
Q <= ((not Bit_Pattern) and A) when Do_BITCLR = '1' else "ZZZZZZZZ";
Q <= (Bit_Pattern or A) when Do_BITSET = '1' else "ZZZZZZZZ";
Q_BC <= ((not Bit_Pattern) and A);
Q_BS <= (Bit_Pattern or A);
 
Q <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
 
Q <= A when Do_PASSA = '1' else "ZZZZZZZZ";
 
Bit_Test <= Bit_Pattern and A;
 
Z_Skip <= '1' when (Do_IDTEST = '1' and IDD = "00000000") or
Z_Skip <= '1' when (Do_IDTEST = '1' and Q_ID = "00000000") or
(Bit_Test /= "00000000" and Do_BITTESTSET = '1') or
(Bit_Test = "00000000" and Do_BITTESTCLR = '1') else '0';
 
STATUS_d(2) <= '1' when Q(7 downto 0) = "00000000" else '0';
STATUS_d(2) <= '1' when Q_i(7 downto 0) = "00000000" else '0';
STATUS_d(1) <= DC_i;
STATUS_d(0) <= A(0) when Do_RRF = '1' else
A(7) when Do_RLF = '1' else
309,7 → 335,7
STATUS_Wr(2) <= '1' when Do_SUB = '1' or Do_ADD = '1' or
((Do_DEC = '1' or Do_INC = '1') and Do_IDTEST = '0') or
Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' or
Do_CLR = '1' or Do_COM = '1' or Do_PASSA = '1' else '0';
Do_CLR = '1' or Do_COM = '1' else '0';
-- DC
STATUS_Wr(1) <= '1' when Do_SUB = '1' or Do_ADD = '1' else '0';
-- C
/trunk/rtl/vhdl/PPX_TMR.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
61,7 → 61,6
PS : in std_logic_vector(2 downto 0);
PSA : in std_logic;
TMR_Sel : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
77,8 → 76,9
 
begin
 
Data_Out <= TMR;
 
-- Registers and counter
Data_Out <= TMR when Rd = '1' and TMR_Sel = '1' else "ZZZZZZZZ";
process (Reset_n, Clk)
begin
if Reset_n = '0' then
/trunk/rtl/vhdl/PPX_Ctrl.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
-- Version : 0222
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
55,12 → 55,14
InstructionLength : integer
);
port(
Clk : in std_logic;
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
Inst : in std_logic_vector(InstructionLength - 1 downto 0);
File_Rd : out std_logic;
Skip : in std_logic;
File_Wr : out std_logic;
W_Wr : out std_logic;
W_Rd : out std_logic;
Imm_Op : out std_logic;
A2Res : out std_logic;
B2Res : out std_logic;
Push : out std_logic;
Pop : out std_logic;
75,42 → 77,97
 
begin
 
File_Wr <= '1' when (Inst(InstructionLength - 1 downto InstructionLength - 2) = "00" and
Inst(InstructionLength - 7) = '1') or
Inst(InstructionLength - 1 downto InstructionLength - 3) = "010" else '0';
File_Rd <= not Inst(InstructionLength - 1);
W_Rd <= Inst(InstructionLength - 1);
Imm_Op <= Inst(InstructionLength - 1);
Goto <= '1' when Inst(InstructionLength - 1 downto InstructionLength - 3) = "101" else '0';
 
i12 : if InstructionLength = 12 generate
Push <= '1' when Inst(11 downto 8) = "1001" else '0'; -- CALL
Pop <= '1' when Inst(11 downto 8) = "1000" else '0'; -- RETLW
B_Skip <= '1' when Inst(11 downto 10) = "10" else '0';
Sleep <= '1' when Inst(11 downto 0) = "000000000011" else '0';
B2Res <= '1' when Inst(11 downto 8) = "1100" or -- MOVLW
Inst(11 downto 8) = "1000" or -- RETLW
Inst(11 downto 6) = "000000" else '0'; -- MOVWF/TRIS/OPTION and some others
Sleep <= '1' when ROM_Data(11 downto 0) = "000000000011" else '0';
W_Wr <= '1' when Inst(11 downto 8) = "1000" or
Inst(11 downto 10) = "11" or
(Inst(11 downto 10) = "00" and Inst(5) = '0' and Inst(9 downto 6) /= "0000") else '0';
IRet <= '0';
process (Clk)
begin
if Clk'event and Clk = '1' then
File_Wr <= '0';
Goto <= '0';
Push <= '0';
Pop <= '0';
A2Res <= '0';
B2Res <= '0';
if Skip = '0' then
if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
ROM_Data(InstructionLength - 7) = '1') or
ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "010" then
File_Wr <= '1';
end if;
if ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "101" then
Goto <= '1';
end if;
if ROM_Data(11 downto 8) = "1001" then -- CALL
Push <= '1';
end if;
if ROM_Data(11 downto 8) = "1000" then -- RETLW
Pop <= '1';
end if;
if ROM_Data(11 downto 6) = "001000" then
-- MOVF
A2Res <= '1';
end if;
if ROM_Data(11 downto 8) = "1100" or -- MOVLW
ROM_Data(11 downto 8) = "1000" or -- RETLW
ROM_Data(11 downto 6) = "000000" then -- MOVWF/TRIS/OPTION and some others
B2Res <= '1';
end if;
end if;
end if;
end process;
end generate;
 
i14 : if InstructionLength = 14 generate
Push <= '1' when Inst(13 downto 11) = "100" else '0'; -- CALL
Pop <= '1' when Inst(13 downto 10) = "1101" or -- RETLW
Inst(13 downto 1) = "0000000000100" else '0'; -- RETURN, RETFIE
B_Skip <= '1' when Inst(13 downto 12) = "10" or Inst(13 downto 10) = "1101" or
Inst(13 downto 1) = "0000000000100" else '0';
Sleep <= '1' when Inst(13 downto 0) = "00000001100011" else '0';
B2Res <= '1' when Inst(13 downto 10) = "1100" or -- MOVLW
Inst(13 downto 10) = "1101" or -- RETLW
Inst(13 downto 8) = "000000" else '0'; -- MOVWF/TRIS/OPTION and some others
Sleep <= '1' when ROM_Data(13 downto 0) = "00000001100011" else '0';
W_Wr <= '1' when Inst(13 downto 12) = "11" or
(Inst(13 downto 12) = "00" and Inst(7) = '0' and Inst(11 downto 8) /= "0000") else '0';
IRet <= '1' when Inst(13 downto 0) = "00000000001001" else '0'; -- RETFIE
process (Clk)
begin
if Clk'event and Clk = '1' then
File_Wr <= '0';
Goto <= '0';
Push <= '0';
Pop <= '0';
A2Res <= '0';
B2Res <= '0';
if Skip = '0' then
if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
ROM_Data(InstructionLength - 7) = '1') or
ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "010" then
File_Wr <= '1';
end if;
if ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "101" then
Goto <= '1';
end if;
if ROM_Data(13 downto 11) = "100" then
Push <= '1'; -- CALL
end if;
if ROM_Data(13 downto 10) = "1101" or -- RETLW
ROM_Data(13 downto 1) = "0000000000100" then -- RETURN, RETFIE
Pop <= '1';
end if;
if ROM_Data(13 downto 8) = "001000" then
-- MOVF
A2Res <= '1';
end if;
if ROM_Data(13 downto 10) = "1100" or -- MOVLW
ROM_Data(13 downto 10) = "1101" or -- RETLW
ROM_Data(13 downto 8) = "000000" then -- MOVWF/TRIS/OPTION and some others
B2Res <= '1';
end if;
end if;
end if;
end process;
end generate;
 
end;
 
/trunk/rtl/vhdl/PPX_Port.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
54,13 → 54,11
port(
Clk : in std_logic;
Reset_n : in std_logic;
Port_CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Tris_Rd : in std_logic;
Port_Wr : in std_logic;
Tris_Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Port_In : out std_logic_vector(7 downto 0);
Tris : out std_logic_vector(7 downto 0);
IOPort : inout std_logic_vector(7 downto 0)
);
end PPX_Port;
67,28 → 65,29
 
architecture rtl of PPX_Port is
 
signal Tris : std_logic_vector(7 downto 0);
signal Tris_i : std_logic_vector(7 downto 0);
signal Port_Output : std_logic_vector(7 downto 0);
signal Port_Input : std_logic_vector(7 downto 0);
 
begin
 
IOPort(0) <= Port_Output(0) when Tris(0) = '0' else 'Z';
IOPort(1) <= Port_Output(1) when Tris(1) = '0' else 'Z';
IOPort(2) <= Port_Output(2) when Tris(2) = '0' else 'Z';
IOPort(3) <= Port_Output(3) when Tris(3) = '0' else 'Z';
IOPort(4) <= Port_Output(4) when Tris(4) = '0' else 'Z';
IOPort(5) <= Port_Output(5) when Tris(5) = '0' else 'Z';
IOPort(6) <= Port_Output(6) when Tris(6) = '0' else 'Z';
IOPort(7) <= Port_Output(7) when Tris(7) = '0' else 'Z';
Port_In <= Port_Input;
Tris <= Tris_i;
 
Data_Out <= Port_Input when Port_CS = '1' and Rd = '1' else "ZZZZZZZZ";
IOPort(0) <= Port_Output(0) when Tris_i(0) = '0' else 'Z';
IOPort(1) <= Port_Output(1) when Tris_i(1) = '0' else 'Z';
IOPort(2) <= Port_Output(2) when Tris_i(2) = '0' else 'Z';
IOPort(3) <= Port_Output(3) when Tris_i(3) = '0' else 'Z';
IOPort(4) <= Port_Output(4) when Tris_i(4) = '0' else 'Z';
IOPort(5) <= Port_Output(5) when Tris_i(5) = '0' else 'Z';
IOPort(6) <= Port_Output(6) when Tris_i(6) = '0' else 'Z';
IOPort(7) <= Port_Output(7) when Tris_i(7) = '0' else 'Z';
 
process (Clk)
begin
if Clk'event and Clk = '1' then
Port_Input <= IOPort; -- Synchronise input
if Port_CS = '1' and Wr = '1' then
if Port_Wr = '1' then
Port_Output <= Data_In;
Port_Input <= Data_In;
end if;
95,15 → 94,13
end if;
end process;
 
Data_Out <= Tris when Tris_Rd = '1' else "ZZZZZZZZ";
 
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Tris <= "11111111";
Tris_i <= "11111111";
elsif Clk'event and Clk = '1' then
if Tris_Wr = '1' then
Tris <= Data_In;
Tris_i <= Data_In;
end if;
end if;
end process;
/trunk/rtl/vhdl/PPX_PCS.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0220
-- Version : 0222
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
59,10 → 59,8
Clk : in std_logic;
Reset_n : in std_logic;
CS : in std_logic;
Rd : in std_logic;
Wr : in std_logic;
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0);
Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
PCLATH : in std_logic_vector(4 downto 0);
STATUS : in std_logic_vector(6 downto 5);
87,19 → 85,21
 
begin
 
Data_Out <= std_logic_vector(PC_i(7 downto 0)) when CS = '1' and Rd = '1' else "ZZZZZZZZ";
NPC <= std_logic_vector(NPC_i);
 
process (Clk)
begin
if Clk'event and Clk = '1' then
if Push = '1' or Int = '1' then
if Push = '1' then
Stack(to_integer(StackPtr)) <= PC_i;
end if;
if Int = '1' then
Stack(to_integer(StackPtr)) <= PC_i - 1;
end if;
end if;
end process;
 
process (PC_i, Sleep, CS, Wr, PCLATH, STATUS, Push, Pop, Goto, Int, Data_In, Addr_In, Stack, StackPtr)
process (PC_i, Sleep, CS, Wr, PCLATH, STATUS, Push, Pop, Goto, Data_In, Addr_In, Int, Stack, StackPtr)
begin
NPC_i <= PC_i;
if Sleep = '0' then
/trunk/rtl/vhdl/PPX16.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0220
-- Version : 0222
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
70,11 → 70,15
Int_Ret : out std_logic;
File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
File_Rd : out std_logic;
File_Wr : out std_logic;
W_Wr : out std_logic;
Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
Op_Bus : inout std_logic_vector(7 downto 0);
Res_Bus : inout std_logic_vector(7 downto 0)
Op_Bus : in std_logic_vector(7 downto 0);
W : out std_logic_vector(7 downto 0);
STATUS : out std_logic_vector(7 downto 0);
FSR : out std_logic_vector(7 downto 0);
PCLATH : out std_logic_vector(4 downto 0);
Res_Bus : out std_logic_vector(7 downto 0)
);
end PPX16;
 
83,41 → 87,51
-- File control
signal File_Addr_i : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Addr_i_r : std_logic_vector(InstructionLength - 6 downto 0);
signal File_Rd_i : std_logic;
signal File_Wr_i : std_logic;
signal PC_CS : std_logic;
 
-- Registers
signal STATUS : std_logic_vector(7 downto 0);
signal W : std_logic_vector(7 downto 0);
signal FSR : std_logic_vector(7 downto 0);
signal PCLATH : std_logic_vector(4 downto 0);
signal W_i : std_logic_vector(7 downto 0);
signal PCLATH_i : std_logic_vector(4 downto 0);
signal STATUS_i : std_logic_vector(7 downto 0);
signal FSR_i : std_logic_vector(7 downto 0);
signal NPC : std_logic_vector(InstructionLength - 2 downto 0);
 
-- Registered instruction word
signal Inst : std_logic_vector(InstructionLength - 1 downto 0);
 
-- Control signals
signal Inst : std_logic_vector(InstructionLength - 1 downto 0);
signal Res_Bus_i : std_logic_vector(7 downto 0);
signal Q : std_logic_vector(7 downto 0);
signal Op_Mux : std_logic_vector(7 downto 0);
signal STATUS_d_i : std_logic_vector(7 downto 0);
signal STATUS_d : std_logic_vector(2 downto 0);
signal STATUS_Wr : std_logic_vector(2 downto 0);
signal Z_Skip : std_logic;
signal B_Skip : std_logic;
signal Inst_Skip : std_logic;
signal W_Wr : std_logic;
signal W_Rd : std_logic;
signal W_Wr_i : std_logic;
signal Imm_Op : std_logic;
signal Push : std_logic;
signal Pop : std_logic;
signal Goto : std_logic;
signal IRet : std_logic;
signal A2Res : std_logic;
signal B2Res : std_logic;
signal Sleep : std_logic;
signal Sleep_r : std_logic;
signal Int : std_logic;
signal Int_Pending : std_logic;
 
begin
begin
 
Int_Acc <= Int;
W_Wr <= W_Wr_i;
W <= W_i;
STATUS <= STATUS_d_i;
PCLATH <= PCLATH_i;
FSR <= FSR_i;
 
-- Instruction register
Instruction <= Inst;
process (Reset_n, Clk)
136,23 → 150,20
-- File address
File_Addr <= File_Addr_i;
i12 : if InstructionLength = 12 generate
File_Addr_i <= FSR(6 downto 0) when
File_Addr_i <= FSR_i(6 downto 0) when
-- pragma translate_off
is_x(ROM_Data) or
-- pragma translate_on
unsigned(ROM_Data(4 downto 0)) = 0 else
FSR(6 downto 5) & ROM_Data(4 downto 0);
FSR_i(6 downto 5) & ROM_Data(4 downto 0);
end generate;
i14 : if InstructionLength = 14 generate
File_Addr_i <= STATUS(7) & FSR(7 downto 0) when
File_Addr_i <= STATUS_i(7) & FSR_i(7 downto 0) when
-- pragma translate_off
is_x(ROM_Data) or
-- pragma translate_on
unsigned(ROM_Data(6 downto 0)) = 0 else
STATUS(6 downto 5) & ROM_Data(6 downto 0);
Op_Bus(4 downto 0) <= PCLATH when
to_integer(unsigned(File_Addr_i_r(6 downto 0))) = 10 and
File_Rd_i = '1' else "ZZZZZ";
STATUS_i(6 downto 5) & ROM_Data(6 downto 0);
end generate;
process (Clk)
begin
166,63 → 177,67
process (Reset_n, Clk)
begin
if Reset_n = '0' then
PCLATH <= "00000";
PCLATH_i <= "00000";
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_i_r(6 downto 0))) = 10 and File_Wr_i = '1' then
PCLATH <= Res_Bus(4 downto 0);
PCLATH_i <= Res_Bus_i(4 downto 0);
end if;
end if;
end process;
 
-- Working register
Op_Bus <= W when W_Rd = '1' else "ZZZZZZZZ";
process (Clk)
begin
if Clk'event and Clk = '1' then
if W_Wr = '1' then
W <= Res_Bus;
if W_Wr_i = '1' then
W_i <= Res_Bus_i;
end if;
end if;
end process;
 
-- Status register
Op_Bus <= STATUS when
to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 3 and
File_Rd_i = '1' else "ZZZZZZZZ";
process (STATUS_Wr, STATUS_d, STATUS_i, A2Res, Op_Bus)
begin
STATUS_d_i <= STATUS_i;
if STATUS_Wr(0) = '1' then
STATUS_d_i(0) <= STATUS_d(0);
end if;
if STATUS_Wr(1) = '1' then
STATUS_d_i(1) <= STATUS_d(1);
end if;
if STATUS_Wr(2) = '1' then
STATUS_d_i(2) <= STATUS_d(2);
end if;
if A2Res = '1' then
STATUS_d_i(2) <= '0';
if Op_Bus = "00000000" then
STATUS_d_i(2) <= '1';
end if;
end if;
end process;
process (Reset_n, Clk)
begin
if Reset_n = '0' then
STATUS <= "00011000";
STATUS_i <= "00011000";
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 3 and
File_Wr_i = '1' then
STATUS <= Res_Bus;
STATUS_i <= Res_Bus_i;
else
if STATUS_Wr(0) = '1' then
STATUS(0) <= STATUS_d(0);
end if;
if STATUS_Wr(1) = '1' then
STATUS(1) <= STATUS_d(1);
end if;
if STATUS_Wr(2) = '1' then
STATUS(2) <= STATUS_d(2);
end if;
STATUS_i <= STATUS_d_i;
end if;
end if;
end process;
 
-- FSR Register
Op_Bus <= FSR when
to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 4 and
File_Rd_i = '1' else "ZZZZZZZZ";
process (Reset_n, Clk)
begin
if Reset_n = '0' then
FSR <= "11111111";
FSR_i <= "11111111";
elsif Clk'event and Clk = '1' then
if to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 4 and
File_Wr_i = '1' then
FSR <= Res_Bus;
FSR_i <= Res_Bus_i;
end if;
end if;
end process;
239,13 → 254,11
Clk => Clk,
Reset_n => Reset_n,
CS => PC_CS,
Rd => File_Rd_i,
Wr => File_Wr_i,
Data_In => Res_Bus,
Data_Out => Op_Bus,
Data_In => Res_Bus_i,
Addr_In => Inst(InstructionLength - 4 downto 0),
PCLATH => PCLATH,
STATUS => STATUS(6 downto 5),
PCLATH => PCLATH_i,
STATUS => STATUS_i(6 downto 5),
NPC => NPC,
Int => Int,
Sleep => Sleep_r,
254,8 → 267,9
Goto => Goto);
 
-- ALU
Op_Mux <= Inst(7 downto 0) when Imm_Op = '1' else W;
Res_Bus <= Op_Mux when B2Res = '1' else "ZZZZZZZZ";
Op_Mux <= Inst(7 downto 0) when Imm_Op = '1' else W_i;
Res_Bus <= Res_Bus_i;
Res_Bus_i <= Op_Bus when A2Res = '1' else Op_Mux when B2Res = '1' else Q;
alu : PPX_ALU
generic map(InstructionLength => InstructionLength)
port map(
263,26 → 277,27
ROM_Data => ROM_Data,
A => Op_Bus,
B => Op_Mux,
Q => Res_Bus,
Q => Q,
Skip => Inst_Skip,
Carry => STATUS(0),
Carry => STATUS_i(0),
Z_Skip => Z_Skip,
STATUS_d => STATUS_d,
STATUS_Wr => STATUS_Wr);
 
-- Instruction decoder
File_Rd <= File_Rd_i;
File_Wr <= File_Wr_i;
Inst_Skip <= Z_Skip or B_Skip or Sleep_r;
Inst_Skip <= Z_Skip or B_Skip or Sleep_r or Int_Pending;
id : PPX_Ctrl
generic map(InstructionLength => InstructionLength)
port map(
Clk => Clk,
ROM_Data => ROM_Data,
Inst => Inst,
File_Rd => File_Rd_i,
Skip => Inst_Skip,
File_Wr => File_Wr_i,
W_Wr => W_Wr,
W_Rd => W_Rd,
W_Wr => W_Wr_i,
Imm_Op => Imm_Op,
A2Res => A2Res,
B2Res => B2Res,
Push => Push,
Pop => Pop,
291,13 → 306,13
B_Skip => B_Skip,
Sleep => Sleep);
 
-- Interrupts and stuff
-- Interrupt
process (Reset_n, Clk)
begin
if Reset_n = '0' then
Sleep_r <= '0';
Int <= '0';
Int_Acc <= '0';
Int_Pending <= '0';
Int_Ret <= '0';
elsif Clk'event and Clk = '1' then
if Sleep = '1' then
306,12 → 321,13
if Int_Trig = '1' then
Sleep_r <= '0';
end if;
if Int_Trig = '1' and GIE = '1' then -- extra check ???????????????
Int_Pending <= '0';
Int <= '0';
if Int_Trig = '1' and GIE = '1' and Int = '0' then
Int_Pending <= '1';
end if;
if Int_Pending = '1' and Int = '0' and (Z_Skip or B_Skip or Sleep_r) = '0' then
Int <= '1';
Int_Acc <= '1';
else
Int <= '0';
Int_Acc <= '0';
end if;
if IRet = '1' then
Int_Ret <= '1';

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