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Subversion Repositories simple_fm_receiver

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Rev 10 → Rev 11

/trunk/source/phase_detector.vhdl
1,4 → 1,4
-- $Id: phase_detector.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
-- $Id: phase_detector.vhdl,v 1.2 2005-02-21 06:28:29 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Phase detector
-- Project : FM Receiver
7,16 → 7,37
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2004/12/18
-- Last update :
-- Simulators : Modelsim 6.0
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : multiply input signal with signal nco
-------------------------------------------------------------------------------
-- Copyright (c) 2004 Arif E. Nugroho
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
54,8 → 75,13
process (clock)
begin
if ((clock = '1') and clock'event) then
phase_output <= output_mult(15 downto 8);
end if;
 
if ((clock = '1') and clock'event) then
 
phase_output <= output_mult(15 downto 8);
 
end if;
 
end process;
end structural;
/trunk/source/loop_filter.vhdl
1,4 → 1,4
-- $Id: loop_filter.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
-- $Id: loop_filter.vhdl,v 1.2 2005-02-21 06:28:28 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Loop filter component
-- Project : FM Receiver
7,16 → 7,37
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2004/11/12
-- Last update :
-- Simulators : Modelsim 6.0
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : loop filter in PLL loop
-------------------------------------------------------------------------------
-- Copyright (c) 2004 Arif E. Nugroho
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
55,7 → 76,6
signal loop_out_back1 : bit_vector (11 downto 0);
signal multiply_output01 : bit_vector (11 downto 0);
signal adder_output01 : bit_vector (12 downto 0);
signal adder_output01_reg: bit_vector (12 downto 0);
 
begin
101,46 → 121,34
 
loop_out_div <= multiply_output01;
 
adder_output01_reg (11) <= (adder_output01 (11) and not(clear));
adder_output01_reg (10) <= (adder_output01 (10) and not(clear));
adder_output01_reg (09) <= (adder_output01 (09) and not(clear));
adder_output01_reg (08) <= (adder_output01 (08) and not(clear));
adder_output01_reg (07) <= (adder_output01 (07) and not(clear));
adder_output01_reg (06) <= (adder_output01 (06) and not(clear));
adder_output01_reg (05) <= (adder_output01 (05) and not(clear));
adder_output01_reg (04) <= (adder_output01 (04) and not(clear));
adder_output01_reg (03) <= (adder_output01 (03) and not(clear));
adder_output01_reg (02) <= (adder_output01 (02) and not(clear));
adder_output01_reg (01) <= (adder_output01 (01) and not(clear));
adder_output01_reg (00) <= (adder_output01 (00) and not(clear));
process (clock, clear)
 
process (clock)
begin
 
--if (((clock = '1') and (not (clear = '1'))) and clock'event) then
if ((clock = '1') and clock'event) then
-- loop_out (11) <= adder_output01_reg (12);
loop_out (11) <= adder_output01_reg (11);
loop_out (10) <= adder_output01_reg (10);
loop_out (09) <= adder_output01_reg (09);
loop_out (08) <= adder_output01_reg (08);
loop_out (07) <= adder_output01_reg (07);
loop_out (06) <= adder_output01_reg (06);
loop_out (05) <= adder_output01_reg (05);
loop_out (04) <= adder_output01_reg (04);
loop_out (03) <= adder_output01_reg (03);
loop_out (02) <= adder_output01_reg (02);
loop_out (01) <= adder_output01_reg (01);
loop_out (00) <= adder_output01_reg (00);
if (clear = '1') then
 
-- end if;
loop_out <= (others => '0');
 
-- elsif (clear = '1') then -- can't be synhesized in Xilinx
-- loop_out <= (others => '0');
elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then
 
-- loop_out (11) <= adder_output01 (12);
loop_out (11) <= adder_output01 (11);
loop_out (10) <= adder_output01 (10);
loop_out (09) <= adder_output01 (09);
loop_out (08) <= adder_output01 (08);
loop_out (07) <= adder_output01 (07);
loop_out (06) <= adder_output01 (06);
loop_out (05) <= adder_output01 (05);
loop_out (04) <= adder_output01 (04);
loop_out (03) <= adder_output01 (03);
loop_out (02) <= adder_output01 (02);
loop_out (01) <= adder_output01 (01);
loop_out (00) <= adder_output01 (00);
 
end if;
 
end process;
 
output_loop <= loop_out;
output_loop <= loop_out;
 
end structural;
/trunk/source/nco.vhdl
1,4 → 1,4
-- $Id: nco.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
-- $Id: nco.vhdl,v 1.2 2005-02-21 06:28:20 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : NCO (Numerical Controlled Oscillator)
-- Project : FM Receiver
6,17 → 6,38
-- File : nco.vhdl
-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created : 2004/10/27
-- Last update : 2005/01/01
-- Simulators : Modelsim 6.0
-- Last update :
-- Simulators :
-- Synthesizers:
-- Target :
-------------------------------------------------------------------------------
-- Description : Works like VCO in analog PLL
-------------------------------------------------------------------------------
-- Copyright (c) 2004 Arif E. Nugroho
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
--
-------------------------------------------------------------------------------
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
54,25 → 75,6
signal output_rom : bit_vector (07 downto 0);
 
begin
address_in (9) <= adder_output(17);
address_in (8) <= adder_output(16);
address_in (7) <= adder_output(15);
address_in (6) <= adder_output(14);
address_in (5) <= adder_output(13);
address_in (4) <= adder_output(12);
address_in (3) <= adder_output(11);
address_in (2) <= adder_output(10);
address_in (1) <= adder_output(09);
address_in (0) <= adder_output(08);
 
output_nco (07) <= (output_rom (07) and not(clear));
output_nco (06) <= (output_rom (06) and not(clear));
output_nco (05) <= (output_rom (05) and not(clear));
output_nco (04) <= (output_rom (04) and not(clear));
output_nco (03) <= (output_rom (03) and not(clear));
output_nco (02) <= (output_rom (02) and not(clear));
output_nco (01) <= (output_rom (01) and not(clear));
output_nco (00) <= (output_rom (00) and not(clear));
myaddacc : addacc
port map (
87,4 → 89,38
data (07 downto 0) => output_rom
);
 
address_in (09) <= (adder_output(17));
address_in (08) <= (adder_output(16));
address_in (07) <= (adder_output(15));
address_in (06) <= (adder_output(14));
address_in (05) <= (adder_output(13));
address_in (04) <= (adder_output(12));
address_in (03) <= (adder_output(11));
address_in (02) <= (adder_output(10));
address_in (01) <= (adder_output(09));
address_in (00) <= (adder_output(08));
 
process (clock, clear)
 
begin
 
if (clear = '1') then
 
output_nco <= (others => '0');
 
elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then
 
output_nco (07) <= (output_rom(07));
output_nco (06) <= (output_rom(06));
output_nco (05) <= (output_rom(05));
output_nco (04) <= (output_rom(04));
output_nco (03) <= (output_rom(03));
output_nco (02) <= (output_rom(02));
output_nco (01) <= (output_rom(01));
output_nco (00) <= (output_rom(00));
 
end if;
end process;
 
end structural;

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