URL
https://opencores.org/ocsvn/spartan6_pcie/spartan6_pcie/trunk
Subversion Repositories spartan6_pcie
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- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/spartan6_pcie/trunk/ToDo.txt
0,0 → 1,6
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-MIG core for DDR3 can use a calibration resistor (50R resistor between any BANK3 pin and Gnd). This could be added. |
-Termination resistor can be added on CLK/CLK# pin on DDR3 |
-Control of memory CS signal could be removed (not useful) |
-All SPI devices (Flash memory and 2x SDHC) could be on the same SPI bus |
-SDHC cards could be used in native move rather than SPI, but require bidirectionnal io |