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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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Rev 10 → Rev 11

/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_s.v
37,7 → 37,7
input p_reset,
output p_srdy,
input p_drdy,
output [width-1:0] p_data
output reg [width-1:0] p_data
);
 
localparam asz = $clog2(depth);
48,7 → 48,6
wire [asz:0] rdptr_tail, rdptr_tail_sync;
wire wr_en;
wire [asz:0] wrptr_head, wrptr_head_sync;
reg [width-1:0] p_data;
reg dly_rd_en;
wire [asz-1:0] rd_addr, wr_addr;
 
/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
131,11 → 131,11
cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
end
 
reg [asz-1:0] rdaddr_s0, rdaddr_a, rdaddr_b;
reg [asz-1:0] nxt_com_rdptr;
generate
if (commit == 1)
begin : gen_s0
reg [asz-1:0] rdaddr_s0, rdaddr_a, rdaddr_b;
reg [asz-1:0] nxt_com_rdptr;
 
always @(posedge clk)
begin
173,7 → 173,7
 
generate
if (commit == 1)
begin
begin : gen_s2
wire [asz-1:0] ip_rdaddr, p_rdaddr;
 
sd_input #(asz+width) rbuf1
201,7 → 201,7
end
end // if (commit == 1)
else
begin
begin : gen_ns2
sd_input #(width) rbuf1
(.clk (clk), .reset (p_abort | reset),
.c_srdy (prev_re),
/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap_fsm.v
27,7 → 27,8
reg [4:0] state, nxt_state;
 
wire [`NUM_PORTS-1:0] port_mask;
reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec;
//reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec;
wire [`NUM_PORTS-1:0] nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
 
assign port_mask = 1 << portnum;
 
77,7 → 78,7
if (lri_data[`PRW_DATA] & port_mask)
begin
// packet is for our port
nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
//nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
 
// if enable vector is not empty, send the
// vector to the next port
89,7 → 90,7
lri_drdy = 1;
nxt_state = ns_rcopy;
end
else
else if (nxt_pe_vec == 0)
begin
lri_drdy = 1;
nxt_state = ns_rsink;
157,7 → 158,7
 
// data on ring is for our port and we are the last port
// copy ring data to our TX buffer but do not copy to ring
state[s_rcopy] :
state[s_rsink] :
begin
lptx_data = lri_data[`PFW_SZ-1:0];
if (lri_srdy & lptx_drdy)
/srdydrdy_lib/trunk/examples/bridge/rtl/concentrator.v
13,9 → 13,6
// End of automatics
);
 
wire [`PFW_SZ-1:0] ic_data; // From body of template_body_1i1o.v
wire ic_drdy; // From sdout of sd_output.v
wire ic_srdy; // From body of template_body_1i1o.v
wire [7:0] ip_data; // From sdin of sd_input.v
wire [1:0] ip_code;
reg ip_drdy;
22,10 → 19,10
wire ip_srdy; // From sdin of sd_input.v
 
reg [`PFW_SZ-1:0] nxt_p_data;
reg [1:0] nxt_pkt_code, pkt_code;
reg nxt_p_srdy;
reg [2:0] count, nxt_count;
reg nxt_p_abort, nxt_p_commit;
wire [1:0] pkt_code = p_data[`PRW_PCC];
 
sd_input #(8+2) sdin
(
44,7 → 41,6
begin
nxt_p_data = p_data;
nxt_p_srdy = p_srdy;
nxt_pkt_code = pkt_code;
nxt_p_data = p_data;
nxt_count = count;
nxt_p_commit = p_commit;
57,7 → 53,7
nxt_p_srdy = 0;
nxt_p_commit = 0;
ip_drdy = 1;
nxt_pkt_code = `PCC_DATA;
nxt_p_data[`PRW_PCC] = `PCC_DATA;
nxt_count = 0;
 
if (ip_srdy)
64,7 → 60,7
begin
nxt_count = 1;
if (ip_code != `PCC_DATA)
nxt_pkt_code = ip_code;
nxt_p_data[`PRW_PCC] = ip_code;
nxt_p_data[63:56] = ip_data;
end
end
73,7 → 69,7
begin
ip_drdy = 1;
if (ip_code != `PCC_DATA)
nxt_pkt_code = ip_code;
nxt_p_data[`PRW_PCC] = ip_code;
 
nxt_count = count + 1;
case (count)
92,6 → 88,7
begin
nxt_p_commit = 1;
nxt_p_srdy = 1;
nxt_p_data[`PRW_VALID] = count + 1;
end
else if ((ip_code == `PCC_BADEOP) || (pkt_code == `PCC_BADEOP))
begin
98,7 → 95,10
nxt_p_abort = 1;
end
else
nxt_p_srdy = 1;
begin
nxt_p_srdy = 1;
nxt_p_data[`PRW_VALID] = 0;
end
end
end
end // always @ *
/srdydrdy_lib/trunk/examples/bridge/rtl/port_macro.v
1,4 → 1,5
module port_macro
#(parameter port_num = 0)
(input clk,
input reset,
 
7,17 → 8,17
input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input fli_srdy, // To ring_tap of port_ring_tap.v
input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
input p2f_drdy, // To pkt_parse of pkt_parse.v
input ri_srdy, // To ring_tap of port_ring_tap.v
input ro_drdy, // To ring_tap of port_ring_tap.v
input fli_srdy, // To ring_tap of port_ring_tap.v
input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
input p2f_drdy, // To pkt_parse of pkt_parse.v
input ri_srdy, // To ring_tap of port_ring_tap.v
input ro_drdy, // To ring_tap of port_ring_tap.v
// End of automatics
 
output fli_drdy, // From ring_tap of port_ring_tap.v
output gmii_tx_dv, // From tx_gmii of sd_tx_gigmac.v
output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
output p2f_srdy, // From pkt_parse of pkt_parse.v
35,36 → 36,36
wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire crx_abort; // From con of concentrator.v
wire crx_commit; // From con of concentrator.v
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
wire crx_drdy; // From fifo_rx of sd_fifo_b.v
wire crx_srdy; // From con of concentrator.v
wire ctx_abort; // From oflow of egr_oflow.v
wire ctx_commit; // From oflow of egr_oflow.v
wire ctx_drdy; // From fifo_tx of sd_fifo_b.v
wire ctx_srdy; // From oflow of egr_oflow.v
wire gmii_rx_reset; // From port_clocking of port_clocking.v
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v
wire pdo_drdy; // From con of concentrator.v
wire pdo_srdy; // From pkt_parse of pkt_parse.v
wire prx_drdy; // From ring_tap of port_ring_tap.v
wire prx_srdy; // From fifo_rx of sd_fifo_b.v
wire ptx_drdy; // From dst of distributor.v
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
wire rttx_drdy; // From oflow of egr_oflow.v
wire rttx_srdy; // From ring_tap of port_ring_tap.v
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v
wire rxg_drdy; // From pkt_parse of pkt_parse.v
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v
wire [1:0] txg_code; // From dst of distributor.v
wire [7:0] txg_data; // From dst of distributor.v
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v
wire txg_srdy; // From dst of distributor.v
wire crx_abort; // From con of concentrator.v
wire crx_commit; // From con of concentrator.v
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
wire crx_drdy; // From fifo_rx of sd_fifo_b.v
wire crx_srdy; // From con of concentrator.v
wire ctx_abort; // From oflow of egr_oflow.v
wire ctx_commit; // From oflow of egr_oflow.v
wire ctx_drdy; // From fifo_tx of sd_fifo_b.v
wire ctx_srdy; // From oflow of egr_oflow.v
wire gmii_rx_reset; // From port_clocking of port_clocking.v
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v
wire pdo_drdy; // From con of concentrator.v
wire pdo_srdy; // From pkt_parse of pkt_parse.v
wire prx_drdy; // From ring_tap of port_ring_tap.v
wire prx_srdy; // From fifo_rx of sd_fifo_b.v
wire ptx_drdy; // From dst of distributor.v
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
wire rttx_drdy; // From oflow of egr_oflow.v
wire rttx_srdy; // From ring_tap of port_ring_tap.v
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v
wire rxg_drdy; // From pkt_parse of pkt_parse.v
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v
wire [1:0] txg_code; // From dst of distributor.v
wire [7:0] txg_data; // From dst of distributor.v
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v
wire txg_srdy; // From dst of distributor.v
// End of automatics
 
 
71,11 → 72,11
port_clocking port_clocking
(/*AUTOINST*/
// Outputs
.gmii_rx_reset (gmii_rx_reset),
.gmii_rx_reset (gmii_rx_reset),
// Inputs
.clk (clk),
.reset (reset),
.gmii_rx_clk (gmii_rx_clk));
.clk (clk),
.reset (reset),
.gmii_rx_clk (gmii_rx_clk));
 
/* sd_rx_gigmac AUTO_TEMPLATE
(
87,15 → 88,15
sd_rx_gigmac rx_gigmac
(/*AUTOINST*/
// Outputs
.rxg_srdy (rxc_rxg_srdy), // Templated
.rxg_code (rxc_rxg_code[1:0]), // Templated
.rxg_data (rxc_rxg_data[7:0]), // Templated
.rxg_srdy (rxc_rxg_srdy), // Templated
.rxg_code (rxc_rxg_code[1:0]), // Templated
.rxg_data (rxc_rxg_data[7:0]), // Templated
// Inputs
.clk (gmii_rx_clk), // Templated
.reset (gmii_rx_reset), // Templated
.gmii_rx_dv (gmii_rx_dv),
.gmii_rxd (gmii_rxd[7:0]),
.rxg_drdy (rxc_rxg_drdy)); // Templated
.clk (gmii_rx_clk), // Templated
.reset (gmii_rx_reset), // Templated
.gmii_rx_dv (gmii_rx_dv),
.gmii_rxd (gmii_rxd[7:0]),
.rxg_drdy (rxc_rxg_drdy)); // Templated
 
/* sd_fifo_s AUTO_TEMPLATE
(
112,35 → 113,35
sd_fifo_s #(8+2,16,1) rx_sync_fifo
(/*AUTOINST*/
// Outputs
.c_drdy (rxc_rxg_drdy), // Templated
.p_srdy (rxg_srdy), // Templated
.p_data ({rxg_code,rxg_data}), // Templated
.c_drdy (rxc_rxg_drdy), // Templated
.p_srdy (rxg_srdy), // Templated
.p_data ({rxg_code,rxg_data}), // Templated
// Inputs
.c_clk (gmii_rx_clk), // Templated
.c_reset (gmii_rx_reset), // Templated
.c_srdy (rxc_rxg_srdy), // Templated
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated
.p_clk (clk), // Templated
.p_reset (reset), // Templated
.p_drdy (rxg_drdy)); // Templated
.c_clk (gmii_rx_clk), // Templated
.c_reset (gmii_rx_reset), // Templated
.c_srdy (rxc_rxg_srdy), // Templated
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated
.p_clk (clk), // Templated
.p_reset (reset), // Templated
.p_drdy (rxg_drdy)); // Templated
 
pkt_parse pkt_parse
pkt_parse #(port_num) pkt_parse
(/*AUTOINST*/
// Outputs
.rxg_drdy (rxg_drdy),
.p2f_srdy (p2f_srdy),
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
.pdo_srdy (pdo_srdy),
.pdo_code (pdo_code[1:0]),
.pdo_data (pdo_data[7:0]),
.rxg_drdy (rxg_drdy),
.p2f_srdy (p2f_srdy),
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
.pdo_srdy (pdo_srdy),
.pdo_code (pdo_code[1:0]),
.pdo_data (pdo_data[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.rxg_srdy (rxg_srdy),
.rxg_code (rxg_code[1:0]),
.rxg_data (rxg_data[7:0]),
.p2f_drdy (p2f_drdy),
.pdo_drdy (pdo_drdy));
.clk (clk),
.reset (reset),
.rxg_srdy (rxg_srdy),
.rxg_code (rxg_code[1:0]),
.rxg_data (rxg_data[7:0]),
.p2f_drdy (p2f_drdy),
.pdo_drdy (pdo_drdy));
 
/* concentrator AUTO_TEMPLATE
(
151,18 → 152,18
concentrator con
(/*AUTOINST*/
// Outputs
.c_drdy (pdo_drdy), // Templated
.p_data (crx_data[`PFW_SZ-1:0]), // Templated
.p_srdy (crx_srdy), // Templated
.p_commit (crx_commit), // Templated
.p_abort (crx_abort), // Templated
.c_drdy (pdo_drdy), // Templated
.p_data (crx_data[`PFW_SZ-1:0]), // Templated
.p_srdy (crx_srdy), // Templated
.p_commit (crx_commit), // Templated
.p_abort (crx_abort), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_data (pdo_data[7:0]), // Templated
.c_code (pdo_code[1:0]), // Templated
.c_srdy (pdo_srdy), // Templated
.p_drdy (crx_drdy)); // Templated
.clk (clk),
.reset (reset),
.c_data (pdo_data[7:0]), // Templated
.c_code (pdo_code[1:0]), // Templated
.c_srdy (pdo_srdy), // Templated
.p_drdy (crx_drdy)); // Templated
 
/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"
(
176,38 → 177,38
sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
(/*AUTOINST*/
// Outputs
.c_drdy (crx_drdy), // Templated
.p_srdy (prx_srdy), // Templated
.p_data (prx_data), // Templated
.usage (rx_usage), // Templated
.c_drdy (crx_drdy), // Templated
.p_srdy (prx_srdy), // Templated
.p_data (prx_data), // Templated
.usage (rx_usage), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (crx_srdy), // Templated
.c_commit (crx_commit), // Templated
.c_abort (crx_abort), // Templated
.c_data (crx_data), // Templated
.p_drdy (prx_drdy), // Templated
.p_commit (1'b0), // Templated
.p_abort (1'b0)); // Templated
.clk (clk),
.reset (reset),
.c_srdy (crx_srdy), // Templated
.c_commit (crx_commit), // Templated
.c_abort (crx_abort), // Templated
.c_data (crx_data), // Templated
.p_drdy (prx_drdy), // Templated
.p_commit (1'b0), // Templated
.p_abort (1'b0)); // Templated
 
sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
(/*AUTOINST*/
// Outputs
.c_drdy (ctx_drdy), // Templated
.p_srdy (ptx_srdy), // Templated
.p_data (ptx_data), // Templated
.usage (tx_usage), // Templated
.c_drdy (ctx_drdy), // Templated
.p_srdy (ptx_srdy), // Templated
.p_data (ptx_data), // Templated
.usage (tx_usage), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (ctx_srdy), // Templated
.c_commit (ctx_commit), // Templated
.c_abort (ctx_abort), // Templated
.c_data (ctx_data), // Templated
.p_drdy (ptx_drdy), // Templated
.p_commit (1'b0), // Templated
.p_abort (1'b0)); // Templated
.clk (clk),
.reset (reset),
.c_srdy (ctx_srdy), // Templated
.c_commit (ctx_commit), // Templated
.c_abort (ctx_abort), // Templated
.c_data (ctx_data), // Templated
.p_drdy (ptx_drdy), // Templated
.p_commit (1'b0), // Templated
.p_abort (1'b0)); // Templated
 
/* port_ring_tap AUTO_TEMPLATE
(
217,27 → 218,27
.ptx_\(.*\) (rttx_\1),
);
*/
port_ring_tap ring_tap
port_ring_tap #(port_num) ring_tap
(/*AUTOINST*/
// Outputs
.ri_drdy (ri_drdy),
.prx_drdy (prx_drdy), // Templated
.ro_srdy (ro_srdy),
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
.ptx_srdy (rttx_srdy), // Templated
.ptx_data (rttx_data), // Templated
.fli_drdy (fli_drdy),
.ri_drdy (ri_drdy),
.prx_drdy (prx_drdy), // Templated
.ro_srdy (ro_srdy),
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
.ptx_srdy (rttx_srdy), // Templated
.ptx_data (rttx_data), // Templated
.fli_drdy (fli_drdy),
// Inputs
.clk (clk),
.reset (reset),
.ri_srdy (ri_srdy),
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
.prx_srdy (prx_srdy), // Templated
.prx_data (prx_data), // Templated
.ro_drdy (ro_drdy),
.ptx_drdy (rttx_drdy), // Templated
.fli_srdy (fli_srdy),
.fli_data (fli_data[`NUM_PORTS-1:0]));
.clk (clk),
.reset (reset),
.ri_srdy (ri_srdy),
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
.prx_srdy (prx_srdy), // Templated
.prx_data (prx_data), // Templated
.ro_drdy (ro_drdy),
.ptx_drdy (rttx_drdy), // Templated
.fli_srdy (fli_srdy),
.fli_data (fli_data[`NUM_PORTS-1:0]));
 
/* egr_oflow AUTO_TEMPLATE
(
248,18 → 249,18
egr_oflow oflow
(/*AUTOINST*/
// Outputs
.c_drdy (rttx_drdy), // Templated
.p_srdy (ctx_srdy), // Templated
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated
.p_commit (ctx_commit), // Templated
.p_abort (ctx_abort), // Templated
.c_drdy (rttx_drdy), // Templated
.p_srdy (ctx_srdy), // Templated
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated
.p_commit (ctx_commit), // Templated
.p_abort (ctx_abort), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (rttx_srdy), // Templated
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated
.tx_usage (tx_usage[`TX_USG_SZ-1:0]),
.p_drdy (ctx_drdy)); // Templated
.clk (clk),
.reset (reset),
.c_srdy (rttx_srdy), // Templated
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated
.tx_usage (tx_usage[`TX_USG_SZ-1:0]),
.p_drdy (ctx_drdy)); // Templated
 
/* distributor AUTO_TEMPLATE
(
269,29 → 270,29
distributor dst
(/*AUTOINST*/
// Outputs
.ptx_drdy (ptx_drdy),
.p_srdy (txg_srdy), // Templated
.p_code (txg_code[1:0]), // Templated
.p_data (txg_data[7:0]), // Templated
.ptx_drdy (ptx_drdy),
.p_srdy (txg_srdy), // Templated
.p_code (txg_code[1:0]), // Templated
.p_data (txg_data[7:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.ptx_srdy (ptx_srdy),
.ptx_data (ptx_data[`PFW_SZ-1:0]),
.p_drdy (txg_drdy)); // Templated
.clk (clk),
.reset (reset),
.ptx_srdy (ptx_srdy),
.ptx_data (ptx_data[`PFW_SZ-1:0]),
.p_drdy (txg_drdy)); // Templated
 
sd_tx_gigmac tx_gmii
(/*AUTOINST*/
// Outputs
.gmii_tx_dv (gmii_tx_dv),
.gmii_txd (gmii_txd[7:0]),
.txg_drdy (txg_drdy),
.gmii_tx_en (gmii_tx_en),
.gmii_txd (gmii_txd[7:0]),
.txg_drdy (txg_drdy),
// Inputs
.clk (clk),
.reset (reset),
.txg_srdy (txg_srdy),
.txg_code (txg_code[1:0]),
.txg_data (txg_data[7:0]));
.clk (clk),
.reset (reset),
.txg_srdy (txg_srdy),
.txg_code (txg_code[1:0]),
.txg_data (txg_data[7:0]));
endmodule // port_macro
// Local Variables:
/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap.v
2,9 → 2,10
// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)
 
module port_ring_tap
#(parameter rdp_sz = `PRW_SZ,
parameter pdp_sz = `PFW_SZ,
parameter portnum = 0)
#(parameter portnum = 0,
parameter rdp_sz = `PRW_SZ,
parameter pdp_sz = `PFW_SZ
)
(
input clk,
input reset,
/srdydrdy_lib/trunk/examples/bridge/rtl/pkt_parse.v
8,6 → 8,7
// a parse result to the FIB for lookup. Otherwise aborts the
// packet so it is flushed from the packet FIFO.
module pkt_parse
#(parameter port_num=0)
(input clk,
input reset,
 
74,7 → 75,10
0, 1, 2, 3, 4, 5 :
begin
if (count == 0)
nxt_p2f_data = 0;
begin
nxt_p2f_data = 0;
nxt_p2f_data[`PAR_SRCPORT] = port_num;
end
 
if ((lp_code == `PCC_EOP) || (lp_code == `PCC_BADEOP))
begin
/srdydrdy_lib/trunk/examples/bridge/rtl/sd_tx_gigmac.v
10,7 → 10,7
(
input clk,
input reset,
output reg gmii_tx_dv,
output reg gmii_tx_en,
output reg [7:0] gmii_txd,
 
input txg_srdy,
26,7 → 26,7
reg [3:0] count, nxt_count;
 
reg [7:0] nxt_gmii_txd;
reg nxt_gmii_tx_dv;
reg nxt_gmii_tx_en;
reg [3:0] state, nxt_state;
 
localparam s_idle = 0, s_preamble = 1, s_payload = 2, s_ipg = 3;
49,7 → 49,7
begin
ip_drdy = 0;
nxt_count = count;
nxt_gmii_tx_dv = 0;
nxt_gmii_tx_en = 0;
nxt_gmii_txd = gmii_txd;
 
case (1'b1)
57,7 → 57,7
begin
if (ip_srdy & (ip_code == `PCC_SOP))
begin
nxt_gmii_tx_dv = 1;
nxt_gmii_tx_en = 1;
nxt_gmii_txd = `GMII_PRE;
nxt_count = 1;
nxt_state = ns_preamble;
71,23 → 71,24
state[s_preamble] :
begin
nxt_count = count + 1;
nxt_gmii_tx_dv = 1;
nxt_gmii_tx_en = 1;
if (count == 6)
nxt_gmii_txd = `GMII_SFD;
begin
nxt_gmii_txd = `GMII_SFD;
nxt_state = ns_payload;
end
else
nxt_gmii_txd = `GMII_PRE;
 
if (count == 7)
nxt_state = ns_payload;
end // case: state[s_preamble]
 
state[s_payload] :
begin
ip_drdy = 1;
 
nxt_gmii_tx_en = 1;
nxt_gmii_txd = ip_data;
if (!ip_srdy | ((ip_code == `PCC_EOP) | (ip_code == `PCC_BADEOP)))
begin
nxt_gmii_tx_dv = 0;
nxt_count = 0;
nxt_state = ns_ipg;
end
95,7 → 96,7
 
state[s_ipg] :
begin
nxt_gmii_tx_dv = 0;
nxt_gmii_tx_en = 0;
ip_drdy = 0;
nxt_count = count + 1;
if (count == 11)
112,17 → 113,17
begin
state <= #1 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count <= 4'h0;
gmii_tx_dv <= 1'h0;
gmii_txd <= 8'h0;
// End of automatics
// Beginning of autoreset for uninitialized flops
count <= 4'h0;
gmii_tx_en <= 1'h0;
gmii_txd <= 8'h0;
// End of automatics
end
else
begin
state <= #1 nxt_state;
count <= #1 nxt_count;
gmii_tx_dv <= #1 nxt_gmii_tx_dv;
gmii_tx_en <= #1 nxt_gmii_tx_en;
gmii_txd <= #1 nxt_gmii_txd;
end // else: !if(reset)
end // always @ (posedge clk)
/srdydrdy_lib/trunk/examples/bridge/rtl/bridge_ex1.v
11,29 → 11,29
input reset,
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input gmii_rx_clk_0, // To p0 of port_macro.v
input gmii_rx_clk_1, // To p1 of port_macro.v
input gmii_rx_clk_2, // To p2 of port_macro.v
input gmii_rx_clk_3, // To p3 of port_macro.v
input gmii_rx_dv_0, // To p0 of port_macro.v
input gmii_rx_dv_1, // To p1 of port_macro.v
input gmii_rx_dv_2, // To p2 of port_macro.v
input gmii_rx_dv_3, // To p3 of port_macro.v
input [7:0] gmii_rxd_0, // To p0 of port_macro.v
input [7:0] gmii_rxd_1, // To p1 of port_macro.v
input [7:0] gmii_rxd_2, // To p2 of port_macro.v
input [7:0] gmii_rxd_3, // To p3 of port_macro.v
input gmii_rx_clk_0, // To p0 of port_macro.v
input gmii_rx_clk_1, // To p1 of port_macro.v
input gmii_rx_clk_2, // To p2 of port_macro.v
input gmii_rx_clk_3, // To p3 of port_macro.v
input gmii_rx_dv_0, // To p0 of port_macro.v
input gmii_rx_dv_1, // To p1 of port_macro.v
input gmii_rx_dv_2, // To p2 of port_macro.v
input gmii_rx_dv_3, // To p3 of port_macro.v
input [7:0] gmii_rxd_0, // To p0 of port_macro.v
input [7:0] gmii_rxd_1, // To p1 of port_macro.v
input [7:0] gmii_rxd_2, // To p2 of port_macro.v
input [7:0] gmii_rxd_3, // To p3 of port_macro.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output gmii_tx_dv_0, // From p0 of port_macro.v
output gmii_tx_dv_1, // From p1 of port_macro.v
output gmii_tx_dv_2, // From p2 of port_macro.v
output gmii_tx_dv_3, // From p3 of port_macro.v
output [7:0] gmii_txd_0, // From p0 of port_macro.v
output [7:0] gmii_txd_1, // From p1 of port_macro.v
output [7:0] gmii_txd_2, // From p2 of port_macro.v
output [7:0] gmii_txd_3 // From p3 of port_macro.v
output gmii_tx_en_0, // From p0 of port_macro.v
output gmii_tx_en_1, // From p1 of port_macro.v
output gmii_tx_en_2, // From p2 of port_macro.v
output gmii_tx_en_3, // From p3 of port_macro.v
output [7:0] gmii_txd_0, // From p0 of port_macro.v
output [7:0] gmii_txd_1, // From p1 of port_macro.v
output [7:0] gmii_txd_2, // From p2 of port_macro.v
output [7:0] gmii_txd_3 // From p3 of port_macro.v
// End of automatics
);
 
43,26 → 43,26
wire [`PRW_SZ-1:0] ri_data_3;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`NUM_PORTS-1:0] flo_data; // From fib_lookup of fib_lookup.v
wire [3:0] flo_drdy; // From p0 of port_macro.v, ...
wire [`NUM_PORTS-1:0] flo_srdy; // From fib_lookup of fib_lookup.v
wire [`PAR_DATA_SZ-1:0] p2f_data_0; // From p0 of port_macro.v
wire [`PAR_DATA_SZ-1:0] p2f_data_1; // From p1 of port_macro.v
wire [`PAR_DATA_SZ-1:0] p2f_data_2; // From p2 of port_macro.v
wire [`PAR_DATA_SZ-1:0] p2f_data_3; // From p3 of port_macro.v
wire [`NUM_PORTS-1:0] p2f_drdy; // From fib_arb of sd_rrslow.v
wire [3:0] p2f_srdy; // From p0 of port_macro.v, ...
wire [`PAR_DATA_SZ-1:0] ppi_data; // From fib_arb of sd_rrslow.v
wire ppi_drdy; // From fib_lookup of fib_lookup.v
wire ppi_srdy; // From fib_arb of sd_rrslow.v
wire ri_drdy_0; // From p0 of port_macro.v
wire ri_drdy_1; // From p1 of port_macro.v
wire ri_drdy_2; // From p2 of port_macro.v
wire ri_drdy_3; // From p3 of port_macro.v
wire ri_srdy_0; // From p3 of port_macro.v
wire ri_srdy_1; // From p0 of port_macro.v
wire ri_srdy_2; // From p1 of port_macro.v
wire ri_srdy_3; // From p2 of port_macro.v
wire [`NUM_PORTS-1:0] flo_data; // From fib_lookup of fib_lookup.v
wire [3:0] flo_drdy; // From p0 of port_macro.v, ...
wire [`NUM_PORTS-1:0] flo_srdy; // From fib_lookup of fib_lookup.v
wire [`PAR_DATA_SZ-1:0] p2f_data_0; // From p0 of port_macro.v
wire [`PAR_DATA_SZ-1:0] p2f_data_1; // From p1 of port_macro.v
wire [`PAR_DATA_SZ-1:0] p2f_data_2; // From p2 of port_macro.v
wire [`PAR_DATA_SZ-1:0] p2f_data_3; // From p3 of port_macro.v
wire [`NUM_PORTS-1:0] p2f_drdy; // From fib_arb of sd_rrslow.v
wire [3:0] p2f_srdy; // From p0 of port_macro.v, ...
wire [`PAR_DATA_SZ-1:0] ppi_data; // From fib_arb of sd_rrslow.v
wire ppi_drdy; // From fib_lookup of fib_lookup.v
wire ppi_srdy; // From fib_arb of sd_rrslow.v
wire ri_drdy_0; // From p0 of port_macro.v
wire ri_drdy_1; // From p1 of port_macro.v
wire ri_drdy_2; // From p2 of port_macro.v
wire ri_drdy_3; // From p3 of port_macro.v
wire ri_srdy_0; // From p3 of port_macro.v
wire ri_srdy_1; // From p0 of port_macro.v
wire ri_srdy_2; // From p1 of port_macro.v
wire ri_srdy_3; // From p2 of port_macro.v
// End of automatics
 
/* port_macro AUTO_TEMPLATE
79,101 → 79,101
.\(.*\) (\1_@[]),
);
*/
port_macro p0
port_macro #(0) p0
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_1), // Templated
.fli_drdy (flo_drdy[0]), // Templated
.gmii_tx_dv (gmii_tx_dv_0), // Templated
.gmii_txd (gmii_txd_0[7:0]), // Templated
.p2f_data (p2f_data_0[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[0]), // Templated
.ri_drdy (ri_drdy_0), // Templated
.ro_srdy (ri_srdy_1), // Templated
.ro_data (ri_data_1), // Templated
.fli_drdy (flo_drdy[0]), // Templated
.gmii_tx_en (gmii_tx_en_0), // Templated
.gmii_txd (gmii_txd_0[7:0]), // Templated
.p2f_data (p2f_data_0[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[0]), // Templated
.ri_drdy (ri_drdy_0), // Templated
.ro_srdy (ri_srdy_1), // Templated
// Inputs
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_0), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[0]), // Templated
.gmii_rx_clk (gmii_rx_clk_0), // Templated
.gmii_rx_dv (gmii_rx_dv_0), // Templated
.gmii_rxd (gmii_rxd_0[7:0]), // Templated
.p2f_drdy (p2f_drdy[0]), // Templated
.ri_srdy (ri_srdy_0), // Templated
.ro_drdy (ri_drdy_1)); // Templated
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_0), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[0]), // Templated
.gmii_rx_clk (gmii_rx_clk_0), // Templated
.gmii_rx_dv (gmii_rx_dv_0), // Templated
.gmii_rxd (gmii_rxd_0[7:0]), // Templated
.p2f_drdy (p2f_drdy[0]), // Templated
.ri_srdy (ri_srdy_0), // Templated
.ro_drdy (ri_drdy_1)); // Templated
 
port_macro p1
port_macro #(1) p1
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_2), // Templated
.fli_drdy (flo_drdy[1]), // Templated
.gmii_tx_dv (gmii_tx_dv_1), // Templated
.gmii_txd (gmii_txd_1[7:0]), // Templated
.p2f_data (p2f_data_1[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[1]), // Templated
.ri_drdy (ri_drdy_1), // Templated
.ro_srdy (ri_srdy_2), // Templated
.ro_data (ri_data_2), // Templated
.fli_drdy (flo_drdy[1]), // Templated
.gmii_tx_en (gmii_tx_en_1), // Templated
.gmii_txd (gmii_txd_1[7:0]), // Templated
.p2f_data (p2f_data_1[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[1]), // Templated
.ri_drdy (ri_drdy_1), // Templated
.ro_srdy (ri_srdy_2), // Templated
// Inputs
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_1), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[1]), // Templated
.gmii_rx_clk (gmii_rx_clk_1), // Templated
.gmii_rx_dv (gmii_rx_dv_1), // Templated
.gmii_rxd (gmii_rxd_1[7:0]), // Templated
.p2f_drdy (p2f_drdy[1]), // Templated
.ri_srdy (ri_srdy_1), // Templated
.ro_drdy (ri_drdy_2)); // Templated
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_1), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[1]), // Templated
.gmii_rx_clk (gmii_rx_clk_1), // Templated
.gmii_rx_dv (gmii_rx_dv_1), // Templated
.gmii_rxd (gmii_rxd_1[7:0]), // Templated
.p2f_drdy (p2f_drdy[1]), // Templated
.ri_srdy (ri_srdy_1), // Templated
.ro_drdy (ri_drdy_2)); // Templated
 
port_macro p2
port_macro #(2) p2
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_3), // Templated
.fli_drdy (flo_drdy[2]), // Templated
.gmii_tx_dv (gmii_tx_dv_2), // Templated
.gmii_txd (gmii_txd_2[7:0]), // Templated
.p2f_data (p2f_data_2[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[2]), // Templated
.ri_drdy (ri_drdy_2), // Templated
.ro_srdy (ri_srdy_3), // Templated
.ro_data (ri_data_3), // Templated
.fli_drdy (flo_drdy[2]), // Templated
.gmii_tx_en (gmii_tx_en_2), // Templated
.gmii_txd (gmii_txd_2[7:0]), // Templated
.p2f_data (p2f_data_2[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[2]), // Templated
.ri_drdy (ri_drdy_2), // Templated
.ro_srdy (ri_srdy_3), // Templated
// Inputs
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_2), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[2]), // Templated
.gmii_rx_clk (gmii_rx_clk_2), // Templated
.gmii_rx_dv (gmii_rx_dv_2), // Templated
.gmii_rxd (gmii_rxd_2[7:0]), // Templated
.p2f_drdy (p2f_drdy[2]), // Templated
.ri_srdy (ri_srdy_2), // Templated
.ro_drdy (ri_drdy_3)); // Templated
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_2), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[2]), // Templated
.gmii_rx_clk (gmii_rx_clk_2), // Templated
.gmii_rx_dv (gmii_rx_dv_2), // Templated
.gmii_rxd (gmii_rxd_2[7:0]), // Templated
.p2f_drdy (p2f_drdy[2]), // Templated
.ri_srdy (ri_srdy_2), // Templated
.ro_drdy (ri_drdy_3)); // Templated
 
port_macro p3
port_macro #(3) p3
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_0), // Templated
.fli_drdy (flo_drdy[3]), // Templated
.gmii_tx_dv (gmii_tx_dv_3), // Templated
.gmii_txd (gmii_txd_3[7:0]), // Templated
.p2f_data (p2f_data_3[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[3]), // Templated
.ri_drdy (ri_drdy_3), // Templated
.ro_srdy (ri_srdy_0), // Templated
.ro_data (ri_data_0), // Templated
.fli_drdy (flo_drdy[3]), // Templated
.gmii_tx_en (gmii_tx_en_3), // Templated
.gmii_txd (gmii_txd_3[7:0]), // Templated
.p2f_data (p2f_data_3[`PAR_DATA_SZ-1:0]), // Templated
.p2f_srdy (p2f_srdy[3]), // Templated
.ri_drdy (ri_drdy_3), // Templated
.ro_srdy (ri_srdy_0), // Templated
// Inputs
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_3), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[3]), // Templated
.gmii_rx_clk (gmii_rx_clk_3), // Templated
.gmii_rx_dv (gmii_rx_dv_3), // Templated
.gmii_rxd (gmii_rxd_3[7:0]), // Templated
.p2f_drdy (p2f_drdy[3]), // Templated
.ri_srdy (ri_srdy_3), // Templated
.ro_drdy (ri_drdy_0)); // Templated
.clk (clk), // Templated
.reset (reset), // Templated
.ri_data (ri_data_3), // Templated
.fli_data (flo_data), // Templated
.fli_srdy (flo_srdy[3]), // Templated
.gmii_rx_clk (gmii_rx_clk_3), // Templated
.gmii_rx_dv (gmii_rx_dv_3), // Templated
.gmii_rxd (gmii_rxd_3[7:0]), // Templated
.p2f_drdy (p2f_drdy[3]), // Templated
.ri_srdy (ri_srdy_3), // Templated
.ro_drdy (ri_drdy_0)); // Templated
 
/* sd_rrslow AUTO_TEMPLATE
(
188,28 → 188,28
sd_rrslow #(`PAR_DATA_SZ,`NUM_PORTS,0) fib_arb
(/*AUTOINST*/
// Outputs
.c_drdy (p2f_drdy[`NUM_PORTS-1:0]), // Templated
.p_data (ppi_data[`PAR_DATA_SZ-1:0]), // Templated
.p_srdy (ppi_srdy), // Templated
.c_drdy (p2f_drdy[`NUM_PORTS-1:0]), // Templated
.p_data (ppi_data[`PAR_DATA_SZ-1:0]), // Templated
.p_srdy (ppi_srdy), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}), // Templated
.c_srdy (p2f_srdy[`NUM_PORTS-1:0]), // Templated
.p_drdy (ppi_drdy)); // Templated
.clk (clk),
.reset (reset),
.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}), // Templated
.c_srdy (p2f_srdy[`NUM_PORTS-1:0]), // Templated
.p_drdy (ppi_drdy)); // Templated
 
fib_lookup fib_lookup
(/*AUTOINST*/
// Outputs
.flo_data (flo_data[`NUM_PORTS-1:0]),
.flo_srdy (flo_srdy[`NUM_PORTS-1:0]),
.ppi_drdy (ppi_drdy),
.flo_data (flo_data[`NUM_PORTS-1:0]),
.flo_srdy (flo_srdy[`NUM_PORTS-1:0]),
.ppi_drdy (ppi_drdy),
// Inputs
.clk (clk),
.reset (reset),
.ppi_data (ppi_data[`PAR_DATA_SZ-1:0]),
.flo_drdy (flo_drdy[`NUM_PORTS-1:0]),
.ppi_srdy (ppi_srdy));
.clk (clk),
.reset (reset),
.ppi_data (ppi_data[`PAR_DATA_SZ-1:0]),
.flo_drdy (flo_drdy[`NUM_PORTS-1:0]),
.ppi_srdy (ppi_srdy));
 
endmodule // bridge_ex1
// Local Variables:
/srdydrdy_lib/trunk/examples/bridge/rtl/distributor.v
1,5 → 1,4
module distributor
#(parameter width=8)
(input clk,
input reset,
 
13,84 → 12,106
output [7:0] p_data
);
 
wire [width-1:0] ic_data; // From body of template_body_1i1o.v
wire ic_drdy; // From sdout of sd_output.v
wire ic_srdy; // From body of template_body_1i1o.v
wire [width-1:0] ip_data; // From sdin of sd_input.v
wire ip_drdy; // From body of template_body_1i1o.v
wire ip_srdy; // From sdin of sd_input.v
// End of automatics
reg [7:0] ic_data;
reg [1:0] ic_code;
wire ic_drdy;
reg ic_srdy;
wire [`PFW_SZ-1:0] ip_data;
reg ip_drdy;
wire ip_srdy;
reg [7:0] remain, nxt_remain;
 
sd_input #(width) sdin
(/*AUTOINST*/
sd_input #(`PFW_SZ) sdin
(
// Outputs
.c_drdy (c_drdy),
.c_drdy (ptx_drdy),
.ip_srdy (ip_srdy),
.ip_data (ip_data[width-1:0]),
.ip_data (ip_data),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_data (c_data[width-1:0]),
.c_srdy (ptx_srdy),
.c_data (ptx_data),
.ip_drdy (ip_drdy));
 
template_body_1i1o #(width) body
(/*AUTOINST*/
// Outputs
.ic_data (ic_data[width-1:0]),
.ic_srdy (ic_srdy),
.ip_drdy (ip_drdy),
// Inputs
.clk (clk),
.reset (reset),
.ic_drdy (ic_drdy),
.ip_data (ip_data[width-1:0]),
.ip_srdy (ip_srdy));
always @*
begin
nxt_remain = remain;
ic_srdy = 0;
ip_drdy = 0;
 
sd_output #(width) sdout
(/*AUTOINST*/
case (remain)
0 : ic_data = ip_data[63:56];
7 : ic_data = ip_data[55:48];
6 : ic_data = ip_data[47:40];
5 : ic_data = ip_data[39:32];
4 : ic_data = ip_data[31:24];
3 : ic_data = ip_data[23:16];
2 : ic_data = ip_data[15: 8];
1 : ic_data = ip_data[ 7: 0];
default : ic_data = ip_data[63:56];
endcase
if (ip_srdy & ic_drdy)
begin
if (remain == 0)
begin
ic_srdy = 1;
if (ip_data[`PRW_VALID] == 0)
nxt_remain = 7;
else
nxt_remain = ip_data[`PRW_VALID]-1;
if (nxt_remain == 0)
ip_drdy = 1;
if (ip_data[`PRW_PCC] == `PCC_SOP)
ic_code = `PCC_SOP;
else
ic_code = `PCC_DATA;
end // if (remain == 0)
else
begin
ic_srdy = 1;
nxt_remain = remain - 1;
if (nxt_remain == 0)
begin
ip_drdy = 1;
if ((ip_data[`PRW_PCC] == `PCC_EOP) |
(ip_data[`PRW_PCC] == `PCC_BADEOP))
ic_code = ip_data[`PRW_PCC];
else
ic_code = `PCC_DATA;
end
else
ic_code = `PCC_DATA;
end // else: !if(remain == 0)
end
end // always @ *
 
always @(posedge clk)
begin
if (reset)
remain <= #1 0;
else
remain <= #1 nxt_remain;
end
 
sd_output #(8+2) sdout
(
// Outputs
.ic_drdy (ic_drdy),
.p_srdy (p_srdy),
.p_data (p_data[width-1:0]),
.p_data ({p_code,p_data}),
// Inputs
.clk (clk),
.reset (reset),
.ic_srdy (ic_srdy),
.ic_data (ic_data[width-1:0]),
.ic_data ({ic_code,ic_data}),
.p_drdy (p_drdy));
 
endmodule // template_1i1o
 
module template_body_1i1o
#(parameter width=8)
(input clk,
input reset,
output reg [width-1:0] ic_data,
output reg ic_srdy,
output reg ip_drdy,
input ic_drdy,
input [width-1:0] ip_data,
input ip_srdy
);
 
always @*
begin
ic_data = ip_data;
if (ip_srdy & ip_drdy)
begin
ic_srdy = 1;
ip_drdy = 1;
end
else
begin
ic_srdy = 0;
ip_drdy = 0;
end
end
endmodule // template_body_1i1o
 
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:
/srdydrdy_lib/trunk/examples/bridge/env/gmii_monitor.v
0,0 → 1,90
module gmii_monitor
(/*AUTOARG*/
// Inputs
clk, gmii_tx_en, gmii_txd
);
input clk;
input gmii_tx_en;
input [7:0] gmii_txd;
 
parameter depth = 2048;
reg [7:0] rxbuf [0:depth-1];
integer rxptr;
event pkt_rcvd;
integer state,rxpkt_num;
integer err_cnt;
integer i;
parameter st_idle = 4, st_norm = 0, st_pre = 1;
initial
begin
rxptr = 0;
state = st_idle;
rxpkt_num = 0;
err_cnt = 0;
end
always @(posedge clk)
begin
case (state)
st_idle :
begin
if (gmii_tx_en)
begin
if (gmii_txd == `GMII_SFD)
state = st_norm;
else
state = st_pre;
end
end
 
st_pre :
begin
if (gmii_txd == `GMII_SFD)
state = st_norm;
else if (!gmii_tx_en)
begin
$display ("%t: ERROR %m: Detected packet with no SFD", $time);
state = st_idle;
end
end
st_norm :
begin
if (gmii_tx_en)
begin
rxbuf[rxptr ] <= #1 gmii_txd;
rxptr = rxptr + 1;
end
else
begin
->pkt_rcvd;
state = st_idle;
end
end // case: st_norm
endcase
end // always @ (posedge clk)
 
always @(pkt_rcvd)
begin
#2;
rxpkt_num = rxpkt_num + 1;
//pid = {rxbuf[rxptr-2], rxbuf[rxptr-1]};
$display ("%t: INFO : %m: Received packet %0d length %0d", $time,rxpkt_num,rxptr);
 
for (i=0; i<rxptr; i=i+1)
begin
if (i % 16 == 0) $write ("%x: ", i[15:0]);
$write ("%x ", rxbuf[i]);
if (i % 16 == 7) $write ("| ");
if (i % 16 == 15) $write ("\n");
end
if (i % 16 != 0) $write ("\n");
rxptr = 0;
end
endmodule // it_monitor
/srdydrdy_lib/trunk/examples/bridge/env/gmii_driver.v
67,6 → 67,21
end
endtask
 
task print_packet;
input [31:0] length;
integer i;
begin
for (i=0; i<length; i=i+1)
begin
if (i % 16 == 0) $write ("%x: ", i[15:0]);
$write ("%x ", rxbuf[i]);
if (i % 16 == 7) $write ("| ");
if (i % 16 == 15) $write ("\n");
end
if (i % 16 != 0) $write ("\n");
end
endtask
 
task send_packet;
input [47:0] da, sa;
input [15:0] length;
82,6 → 97,8
rxbuf[length-2], rxbuf[length-1] } = crc32_result;
 
$display ("%m : Sending packet DA=%x SA=%x of length %0d", da, sa, length);
print_packet (length);
repeat (7)
begin
@(posedge rx_clk);
/srdydrdy_lib/trunk/examples/bridge/env/run
1,5 → 1,11
#!/bin/bash
 
which vcs &> /dev/null
if [ "$?" == "-1" ]; then
iverilog -f bridge.vf
./a.out
else
vcs -full64 +v2k -R -I -f bridge.vf
#vcd2vpd env_top.vcd env_top.vpd
fi
 
/srdydrdy_lib/trunk/examples/bridge/env/bridge.vf
2,6 → 2,7
 
env_top.v
gmii_driver.v
gmii_monitor.v
 
../rtl/basic_hashfunc.v
../rtl/bridge_ex1.v
/srdydrdy_lib/trunk/examples/bridge/env/env_top.v
12,8 → 12,12
 
initial
begin
`ifdef VCS
$vcdpluson;
`else
$dumpfile ("env_top.vcd");
$dumpvars;
`endif
reset = 1;
#200;
reset = 0;
35,26 → 39,26
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire gmii_rx_clk_0; // From driver0 of gmii_driver.v
wire gmii_rx_clk_1; // From driver1 of gmii_driver.v
wire gmii_rx_clk_2; // From driver2 of gmii_driver.v
wire gmii_rx_clk_3; // From driver3 of gmii_driver.v
wire gmii_rx_dv_0; // From driver0 of gmii_driver.v
wire gmii_rx_dv_1; // From driver1 of gmii_driver.v
wire gmii_rx_dv_2; // From driver2 of gmii_driver.v
wire gmii_rx_dv_3; // From driver3 of gmii_driver.v
wire [7:0] gmii_rxd_0; // From driver0 of gmii_driver.v
wire [7:0] gmii_rxd_1; // From driver1 of gmii_driver.v
wire [7:0] gmii_rxd_2; // From driver2 of gmii_driver.v
wire [7:0] gmii_rxd_3; // From driver3 of gmii_driver.v
wire gmii_tx_dv_0; // From bridge of bridge_ex1.v
wire gmii_tx_dv_1; // From bridge of bridge_ex1.v
wire gmii_tx_dv_2; // From bridge of bridge_ex1.v
wire gmii_tx_dv_3; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_0; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_1; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_2; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_3; // From bridge of bridge_ex1.v
wire gmii_rx_clk_0; // From driver0 of gmii_driver.v
wire gmii_rx_clk_1; // From driver1 of gmii_driver.v
wire gmii_rx_clk_2; // From driver2 of gmii_driver.v
wire gmii_rx_clk_3; // From driver3 of gmii_driver.v
wire gmii_rx_dv_0; // From driver0 of gmii_driver.v
wire gmii_rx_dv_1; // From driver1 of gmii_driver.v
wire gmii_rx_dv_2; // From driver2 of gmii_driver.v
wire gmii_rx_dv_3; // From driver3 of gmii_driver.v
wire [7:0] gmii_rxd_0; // From driver0 of gmii_driver.v
wire [7:0] gmii_rxd_1; // From driver1 of gmii_driver.v
wire [7:0] gmii_rxd_2; // From driver2 of gmii_driver.v
wire [7:0] gmii_rxd_3; // From driver3 of gmii_driver.v
wire gmii_tx_en_0; // From bridge of bridge_ex1.v
wire gmii_tx_en_1; // From bridge of bridge_ex1.v
wire gmii_tx_en_2; // From bridge of bridge_ex1.v
wire gmii_tx_en_3; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_0; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_1; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_2; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_3; // From bridge of bridge_ex1.v
// End of automatics
 
/* gmii_driver AUTO_TEMPLATE
65,58 → 69,92
gmii_driver driver0
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_0[7:0]), // Templated
.rx_dv (gmii_rx_dv_0), // Templated
.rx_clk (gmii_rx_clk_0)); // Templated
.rxd (gmii_rxd_0[7:0]), // Templated
.rx_dv (gmii_rx_dv_0), // Templated
.rx_clk (gmii_rx_clk_0)); // Templated
 
gmii_driver driver1
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_1[7:0]), // Templated
.rx_dv (gmii_rx_dv_1), // Templated
.rx_clk (gmii_rx_clk_1)); // Templated
.rxd (gmii_rxd_1[7:0]), // Templated
.rx_dv (gmii_rx_dv_1), // Templated
.rx_clk (gmii_rx_clk_1)); // Templated
 
gmii_driver driver2
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_2[7:0]), // Templated
.rx_dv (gmii_rx_dv_2), // Templated
.rx_clk (gmii_rx_clk_2)); // Templated
.rxd (gmii_rxd_2[7:0]), // Templated
.rx_dv (gmii_rx_dv_2), // Templated
.rx_clk (gmii_rx_clk_2)); // Templated
 
gmii_driver driver3
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_3[7:0]), // Templated
.rx_dv (gmii_rx_dv_3), // Templated
.rx_clk (gmii_rx_clk_3)); // Templated
.rxd (gmii_rxd_3[7:0]), // Templated
.rx_dv (gmii_rx_dv_3), // Templated
.rx_clk (gmii_rx_clk_3)); // Templated
 
bridge_ex1 bridge
(/*AUTOINST*/
// Outputs
.gmii_tx_dv_0 (gmii_tx_dv_0),
.gmii_tx_dv_1 (gmii_tx_dv_1),
.gmii_tx_dv_2 (gmii_tx_dv_2),
.gmii_tx_dv_3 (gmii_tx_dv_3),
.gmii_txd_0 (gmii_txd_0[7:0]),
.gmii_txd_1 (gmii_txd_1[7:0]),
.gmii_txd_2 (gmii_txd_2[7:0]),
.gmii_txd_3 (gmii_txd_3[7:0]),
.gmii_tx_en_0 (gmii_tx_en_0),
.gmii_tx_en_1 (gmii_tx_en_1),
.gmii_tx_en_2 (gmii_tx_en_2),
.gmii_tx_en_3 (gmii_tx_en_3),
.gmii_txd_0 (gmii_txd_0[7:0]),
.gmii_txd_1 (gmii_txd_1[7:0]),
.gmii_txd_2 (gmii_txd_2[7:0]),
.gmii_txd_3 (gmii_txd_3[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.gmii_rx_clk_0 (gmii_rx_clk_0),
.gmii_rx_clk_1 (gmii_rx_clk_1),
.gmii_rx_clk_2 (gmii_rx_clk_2),
.gmii_rx_clk_3 (gmii_rx_clk_3),
.gmii_rx_dv_0 (gmii_rx_dv_0),
.gmii_rx_dv_1 (gmii_rx_dv_1),
.gmii_rx_dv_2 (gmii_rx_dv_2),
.gmii_rx_dv_3 (gmii_rx_dv_3),
.gmii_rxd_0 (gmii_rxd_0[7:0]),
.gmii_rxd_1 (gmii_rxd_1[7:0]),
.gmii_rxd_2 (gmii_rxd_2[7:0]),
.gmii_rxd_3 (gmii_rxd_3[7:0]));
.clk (clk),
.reset (reset),
.gmii_rx_clk_0 (gmii_rx_clk_0),
.gmii_rx_clk_1 (gmii_rx_clk_1),
.gmii_rx_clk_2 (gmii_rx_clk_2),
.gmii_rx_clk_3 (gmii_rx_clk_3),
.gmii_rx_dv_0 (gmii_rx_dv_0),
.gmii_rx_dv_1 (gmii_rx_dv_1),
.gmii_rx_dv_2 (gmii_rx_dv_2),
.gmii_rx_dv_3 (gmii_rx_dv_3),
.gmii_rxd_0 (gmii_rxd_0[7:0]),
.gmii_rxd_1 (gmii_rxd_1[7:0]),
.gmii_rxd_2 (gmii_rxd_2[7:0]),
.gmii_rxd_3 (gmii_rxd_3[7:0]));
 
/* gmii_monitor AUTO_TEMPLATE
(
.clk (clk),
.\(.*\) (\1_@[]),
);
*/
gmii_monitor mon0
(/*AUTOINST*/
// Inputs
.clk (clk), // Templated
.gmii_tx_en (gmii_tx_en_0), // Templated
.gmii_txd (gmii_txd_0[7:0])); // Templated
 
gmii_monitor mon1
(/*AUTOINST*/
// Inputs
.clk (clk), // Templated
.gmii_tx_en (gmii_tx_en_1), // Templated
.gmii_txd (gmii_txd_1[7:0])); // Templated
 
gmii_monitor mon2
(/*AUTOINST*/
// Inputs
.clk (clk), // Templated
.gmii_tx_en (gmii_tx_en_2), // Templated
.gmii_txd (gmii_txd_2[7:0])); // Templated
 
gmii_monitor mon3
(/*AUTOINST*/
// Inputs
.clk (clk), // Templated
.gmii_tx_en (gmii_tx_en_3), // Templated
.gmii_txd (gmii_txd_3[7:0])); // Templated
 
endmodule // env_top
// Local Variables:
// verilog-library-directories:("." "../rtl")

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